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Merge tag 'sunxi-fixes-for-5.0' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
1 /*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include "en.h"
34 #include "en/port.h"
35 #include "lib/clock.h"
36
37 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
38 struct ethtool_drvinfo *drvinfo)
39 {
40 struct mlx5_core_dev *mdev = priv->mdev;
41
42 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
43 strlcpy(drvinfo->version, DRIVER_VERSION,
44 sizeof(drvinfo->version));
45 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
46 "%d.%d.%04d (%.16s)",
47 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
48 mdev->board_id);
49 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
50 sizeof(drvinfo->bus_info));
51 }
52
53 static void mlx5e_get_drvinfo(struct net_device *dev,
54 struct ethtool_drvinfo *drvinfo)
55 {
56 struct mlx5e_priv *priv = netdev_priv(dev);
57
58 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
59 }
60
61 struct ptys2ethtool_config {
62 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
64 };
65
66 static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
67
68 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, ...) \
69 ({ \
70 struct ptys2ethtool_config *cfg; \
71 const unsigned int modes[] = { __VA_ARGS__ }; \
72 unsigned int i; \
73 cfg = &ptys2ethtool_table[reg_]; \
74 bitmap_zero(cfg->supported, \
75 __ETHTOOL_LINK_MODE_MASK_NBITS); \
76 bitmap_zero(cfg->advertised, \
77 __ETHTOOL_LINK_MODE_MASK_NBITS); \
78 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
79 __set_bit(modes[i], cfg->supported); \
80 __set_bit(modes[i], cfg->advertised); \
81 } \
82 })
83
84 void mlx5e_build_ptys2ethtool_map(void)
85 {
86 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII,
87 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
88 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX,
89 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
90 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4,
91 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
92 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4,
93 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR,
95 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2,
97 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4,
99 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4,
101 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4,
103 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR,
105 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR,
107 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER,
109 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4,
111 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4,
113 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2,
115 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4,
117 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4,
119 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4,
121 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4,
123 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T,
125 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR,
127 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR,
129 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR,
131 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2,
133 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2,
135 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
136 }
137
138 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
139
140 struct pflag_desc {
141 char name[ETH_GSTRING_LEN];
142 mlx5e_pflag_handler handler;
143 };
144
145 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
146
147 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
148 {
149 int i, num_stats = 0;
150
151 switch (sset) {
152 case ETH_SS_STATS:
153 for (i = 0; i < mlx5e_num_stats_grps; i++)
154 num_stats += mlx5e_stats_grps[i].get_num_stats(priv);
155 return num_stats;
156 case ETH_SS_PRIV_FLAGS:
157 return MLX5E_NUM_PFLAGS;
158 case ETH_SS_TEST:
159 return mlx5e_self_test_num(priv);
160 /* fallthrough */
161 default:
162 return -EOPNOTSUPP;
163 }
164 }
165
166 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
167 {
168 struct mlx5e_priv *priv = netdev_priv(dev);
169
170 return mlx5e_ethtool_get_sset_count(priv, sset);
171 }
172
173 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data)
174 {
175 int i, idx = 0;
176
177 for (i = 0; i < mlx5e_num_stats_grps; i++)
178 idx = mlx5e_stats_grps[i].fill_strings(priv, data, idx);
179 }
180
181 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
182 {
183 int i;
184
185 switch (stringset) {
186 case ETH_SS_PRIV_FLAGS:
187 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
188 strcpy(data + i * ETH_GSTRING_LEN,
189 mlx5e_priv_flags[i].name);
190 break;
191
192 case ETH_SS_TEST:
193 for (i = 0; i < mlx5e_self_test_num(priv); i++)
194 strcpy(data + i * ETH_GSTRING_LEN,
195 mlx5e_self_tests[i]);
196 break;
197
198 case ETH_SS_STATS:
199 mlx5e_fill_stats_strings(priv, data);
200 break;
201 }
202 }
203
204 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
205 {
206 struct mlx5e_priv *priv = netdev_priv(dev);
207
208 mlx5e_ethtool_get_strings(priv, stringset, data);
209 }
210
211 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
212 struct ethtool_stats *stats, u64 *data)
213 {
214 int i, idx = 0;
215
216 mutex_lock(&priv->state_lock);
217 mlx5e_update_stats(priv);
218 mutex_unlock(&priv->state_lock);
219
220 for (i = 0; i < mlx5e_num_stats_grps; i++)
221 idx = mlx5e_stats_grps[i].fill_stats(priv, data, idx);
222 }
223
224 static void mlx5e_get_ethtool_stats(struct net_device *dev,
225 struct ethtool_stats *stats,
226 u64 *data)
227 {
228 struct mlx5e_priv *priv = netdev_priv(dev);
229
230 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
231 }
232
233 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
234 struct ethtool_ringparam *param)
235 {
236 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
237 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
238 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
239 param->tx_pending = 1 << priv->channels.params.log_sq_size;
240 }
241
242 static void mlx5e_get_ringparam(struct net_device *dev,
243 struct ethtool_ringparam *param)
244 {
245 struct mlx5e_priv *priv = netdev_priv(dev);
246
247 mlx5e_ethtool_get_ringparam(priv, param);
248 }
249
250 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
251 struct ethtool_ringparam *param)
252 {
253 struct mlx5e_channels new_channels = {};
254 u8 log_rq_size;
255 u8 log_sq_size;
256 int err = 0;
257
258 if (param->rx_jumbo_pending) {
259 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
260 __func__);
261 return -EINVAL;
262 }
263 if (param->rx_mini_pending) {
264 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
265 __func__);
266 return -EINVAL;
267 }
268
269 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
270 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
271 __func__, param->rx_pending,
272 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
273 return -EINVAL;
274 }
275
276 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
277 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
278 __func__, param->tx_pending,
279 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
280 return -EINVAL;
281 }
282
283 log_rq_size = order_base_2(param->rx_pending);
284 log_sq_size = order_base_2(param->tx_pending);
285
286 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
287 log_sq_size == priv->channels.params.log_sq_size)
288 return 0;
289
290 mutex_lock(&priv->state_lock);
291
292 new_channels.params = priv->channels.params;
293 new_channels.params.log_rq_mtu_frames = log_rq_size;
294 new_channels.params.log_sq_size = log_sq_size;
295
296 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
297 priv->channels.params = new_channels.params;
298 goto unlock;
299 }
300
301 err = mlx5e_open_channels(priv, &new_channels);
302 if (err)
303 goto unlock;
304
305 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
306
307 unlock:
308 mutex_unlock(&priv->state_lock);
309
310 return err;
311 }
312
313 static int mlx5e_set_ringparam(struct net_device *dev,
314 struct ethtool_ringparam *param)
315 {
316 struct mlx5e_priv *priv = netdev_priv(dev);
317
318 return mlx5e_ethtool_set_ringparam(priv, param);
319 }
320
321 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
322 struct ethtool_channels *ch)
323 {
324 ch->max_combined = mlx5e_get_netdev_max_channels(priv->netdev);
325 ch->combined_count = priv->channels.params.num_channels;
326 }
327
328 static void mlx5e_get_channels(struct net_device *dev,
329 struct ethtool_channels *ch)
330 {
331 struct mlx5e_priv *priv = netdev_priv(dev);
332
333 mlx5e_ethtool_get_channels(priv, ch);
334 }
335
336 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
337 struct ethtool_channels *ch)
338 {
339 unsigned int count = ch->combined_count;
340 struct mlx5e_channels new_channels = {};
341 bool arfs_enabled;
342 int err = 0;
343
344 if (!count) {
345 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
346 __func__);
347 return -EINVAL;
348 }
349
350 if (priv->channels.params.num_channels == count)
351 return 0;
352
353 mutex_lock(&priv->state_lock);
354
355 new_channels.params = priv->channels.params;
356 new_channels.params.num_channels = count;
357 if (!netif_is_rxfh_configured(priv->netdev))
358 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
359 MLX5E_INDIR_RQT_SIZE, count);
360
361 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
362 priv->channels.params = new_channels.params;
363 goto out;
364 }
365
366 /* Create fresh channels with new parameters */
367 err = mlx5e_open_channels(priv, &new_channels);
368 if (err)
369 goto out;
370
371 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
372 if (arfs_enabled)
373 mlx5e_arfs_disable(priv);
374
375 /* Switch to new channels, set new parameters and close old ones */
376 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
377
378 if (arfs_enabled) {
379 err = mlx5e_arfs_enable(priv);
380 if (err)
381 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
382 __func__, err);
383 }
384
385 out:
386 mutex_unlock(&priv->state_lock);
387
388 return err;
389 }
390
391 static int mlx5e_set_channels(struct net_device *dev,
392 struct ethtool_channels *ch)
393 {
394 struct mlx5e_priv *priv = netdev_priv(dev);
395
396 return mlx5e_ethtool_set_channels(priv, ch);
397 }
398
399 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
400 struct ethtool_coalesce *coal)
401 {
402 struct net_dim_cq_moder *rx_moder, *tx_moder;
403
404 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
405 return -EOPNOTSUPP;
406
407 rx_moder = &priv->channels.params.rx_cq_moderation;
408 coal->rx_coalesce_usecs = rx_moder->usec;
409 coal->rx_max_coalesced_frames = rx_moder->pkts;
410 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
411
412 tx_moder = &priv->channels.params.tx_cq_moderation;
413 coal->tx_coalesce_usecs = tx_moder->usec;
414 coal->tx_max_coalesced_frames = tx_moder->pkts;
415 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
416
417 return 0;
418 }
419
420 static int mlx5e_get_coalesce(struct net_device *netdev,
421 struct ethtool_coalesce *coal)
422 {
423 struct mlx5e_priv *priv = netdev_priv(netdev);
424
425 return mlx5e_ethtool_get_coalesce(priv, coal);
426 }
427
428 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
429 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
430
431 static void
432 mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
433 {
434 struct mlx5_core_dev *mdev = priv->mdev;
435 int tc;
436 int i;
437
438 for (i = 0; i < priv->channels.num; ++i) {
439 struct mlx5e_channel *c = priv->channels.c[i];
440
441 for (tc = 0; tc < c->num_tc; tc++) {
442 mlx5_core_modify_cq_moderation(mdev,
443 &c->sq[tc].cq.mcq,
444 coal->tx_coalesce_usecs,
445 coal->tx_max_coalesced_frames);
446 }
447
448 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
449 coal->rx_coalesce_usecs,
450 coal->rx_max_coalesced_frames);
451 }
452 }
453
454 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
455 struct ethtool_coalesce *coal)
456 {
457 struct net_dim_cq_moder *rx_moder, *tx_moder;
458 struct mlx5_core_dev *mdev = priv->mdev;
459 struct mlx5e_channels new_channels = {};
460 int err = 0;
461 bool reset;
462
463 if (!MLX5_CAP_GEN(mdev, cq_moderation))
464 return -EOPNOTSUPP;
465
466 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
467 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
468 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
469 __func__, MLX5E_MAX_COAL_TIME);
470 return -ERANGE;
471 }
472
473 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
474 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
475 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
476 __func__, MLX5E_MAX_COAL_FRAMES);
477 return -ERANGE;
478 }
479
480 mutex_lock(&priv->state_lock);
481 new_channels.params = priv->channels.params;
482
483 rx_moder = &new_channels.params.rx_cq_moderation;
484 rx_moder->usec = coal->rx_coalesce_usecs;
485 rx_moder->pkts = coal->rx_max_coalesced_frames;
486 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
487
488 tx_moder = &new_channels.params.tx_cq_moderation;
489 tx_moder->usec = coal->tx_coalesce_usecs;
490 tx_moder->pkts = coal->tx_max_coalesced_frames;
491 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
492
493 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
494 priv->channels.params = new_channels.params;
495 goto out;
496 }
497 /* we are opened */
498
499 reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) ||
500 (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled);
501
502 if (!reset) {
503 mlx5e_set_priv_channels_coalesce(priv, coal);
504 priv->channels.params = new_channels.params;
505 goto out;
506 }
507
508 /* open fresh channels with new coal parameters */
509 err = mlx5e_open_channels(priv, &new_channels);
510 if (err)
511 goto out;
512
513 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
514
515 out:
516 mutex_unlock(&priv->state_lock);
517 return err;
518 }
519
520 static int mlx5e_set_coalesce(struct net_device *netdev,
521 struct ethtool_coalesce *coal)
522 {
523 struct mlx5e_priv *priv = netdev_priv(netdev);
524
525 return mlx5e_ethtool_set_coalesce(priv, coal);
526 }
527
528 static void ptys2ethtool_supported_link(unsigned long *supported_modes,
529 u32 eth_proto_cap)
530 {
531 unsigned long proto_cap = eth_proto_cap;
532 int proto;
533
534 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
535 bitmap_or(supported_modes, supported_modes,
536 ptys2ethtool_table[proto].supported,
537 __ETHTOOL_LINK_MODE_MASK_NBITS);
538 }
539
540 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
541 u32 eth_proto_cap)
542 {
543 unsigned long proto_cap = eth_proto_cap;
544 int proto;
545
546 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
547 bitmap_or(advertising_modes, advertising_modes,
548 ptys2ethtool_table[proto].advertised,
549 __ETHTOOL_LINK_MODE_MASK_NBITS);
550 }
551
552 static const u32 pplm_fec_2_ethtool[] = {
553 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
554 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
555 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
556 };
557
558 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
559 {
560 int mode = 0;
561
562 if (!fec_mode)
563 return ETHTOOL_FEC_AUTO;
564
565 mode = find_first_bit(&fec_mode, size);
566
567 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
568 return pplm_fec_2_ethtool[mode];
569
570 return 0;
571 }
572
573 /* we use ETHTOOL_FEC_* offset and apply it to ETHTOOL_LINK_MODE_FEC_*_BIT */
574 static u32 ethtool_fec2ethtool_caps(u_long ethtool_fec_code)
575 {
576 u32 offset;
577
578 offset = find_first_bit(&ethtool_fec_code, sizeof(u32));
579 offset -= ETHTOOL_FEC_OFF_BIT;
580 offset += ETHTOOL_LINK_MODE_FEC_NONE_BIT;
581
582 return offset;
583 }
584
585 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
586 struct ethtool_link_ksettings *link_ksettings)
587 {
588 u_long fec_caps = 0;
589 u32 active_fec = 0;
590 u32 offset;
591 u32 bitn;
592 int err;
593
594 err = mlx5e_get_fec_caps(dev, (u8 *)&fec_caps);
595 if (err)
596 return (err == -EOPNOTSUPP) ? 0 : err;
597
598 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
599 if (err)
600 return err;
601
602 for_each_set_bit(bitn, &fec_caps, ARRAY_SIZE(pplm_fec_2_ethtool)) {
603 u_long ethtool_bitmask = pplm_fec_2_ethtool[bitn];
604
605 offset = ethtool_fec2ethtool_caps(ethtool_bitmask);
606 __set_bit(offset, link_ksettings->link_modes.supported);
607 }
608
609 active_fec = pplm2ethtool_fec(active_fec, sizeof(u32) * BITS_PER_BYTE);
610 offset = ethtool_fec2ethtool_caps(active_fec);
611 __set_bit(offset, link_ksettings->link_modes.advertising);
612
613 return 0;
614 }
615
616 static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
617 u32 eth_proto_cap,
618 u8 connector_type)
619 {
620 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
621 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
622 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
623 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
624 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
625 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
626 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
627 ethtool_link_ksettings_add_link_mode(link_ksettings,
628 supported,
629 FIBRE);
630 ethtool_link_ksettings_add_link_mode(link_ksettings,
631 advertising,
632 FIBRE);
633 }
634
635 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
636 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
637 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
638 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
639 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
640 ethtool_link_ksettings_add_link_mode(link_ksettings,
641 supported,
642 Backplane);
643 ethtool_link_ksettings_add_link_mode(link_ksettings,
644 advertising,
645 Backplane);
646 }
647 return;
648 }
649
650 switch (connector_type) {
651 case MLX5E_PORT_TP:
652 ethtool_link_ksettings_add_link_mode(link_ksettings,
653 supported, TP);
654 ethtool_link_ksettings_add_link_mode(link_ksettings,
655 advertising, TP);
656 break;
657 case MLX5E_PORT_AUI:
658 ethtool_link_ksettings_add_link_mode(link_ksettings,
659 supported, AUI);
660 ethtool_link_ksettings_add_link_mode(link_ksettings,
661 advertising, AUI);
662 break;
663 case MLX5E_PORT_BNC:
664 ethtool_link_ksettings_add_link_mode(link_ksettings,
665 supported, BNC);
666 ethtool_link_ksettings_add_link_mode(link_ksettings,
667 advertising, BNC);
668 break;
669 case MLX5E_PORT_MII:
670 ethtool_link_ksettings_add_link_mode(link_ksettings,
671 supported, MII);
672 ethtool_link_ksettings_add_link_mode(link_ksettings,
673 advertising, MII);
674 break;
675 case MLX5E_PORT_FIBRE:
676 ethtool_link_ksettings_add_link_mode(link_ksettings,
677 supported, FIBRE);
678 ethtool_link_ksettings_add_link_mode(link_ksettings,
679 advertising, FIBRE);
680 break;
681 case MLX5E_PORT_DA:
682 ethtool_link_ksettings_add_link_mode(link_ksettings,
683 supported, Backplane);
684 ethtool_link_ksettings_add_link_mode(link_ksettings,
685 advertising, Backplane);
686 break;
687 case MLX5E_PORT_NONE:
688 case MLX5E_PORT_OTHER:
689 default:
690 break;
691 }
692 }
693
694 static void get_speed_duplex(struct net_device *netdev,
695 u32 eth_proto_oper,
696 struct ethtool_link_ksettings *link_ksettings)
697 {
698 u32 speed = SPEED_UNKNOWN;
699 u8 duplex = DUPLEX_UNKNOWN;
700
701 if (!netif_carrier_ok(netdev))
702 goto out;
703
704 speed = mlx5e_port_ptys2speed(eth_proto_oper);
705 if (!speed) {
706 speed = SPEED_UNKNOWN;
707 goto out;
708 }
709
710 duplex = DUPLEX_FULL;
711
712 out:
713 link_ksettings->base.speed = speed;
714 link_ksettings->base.duplex = duplex;
715 }
716
717 static void get_supported(u32 eth_proto_cap,
718 struct ethtool_link_ksettings *link_ksettings)
719 {
720 unsigned long *supported = link_ksettings->link_modes.supported;
721
722 ptys2ethtool_supported_link(supported, eth_proto_cap);
723 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
724 }
725
726 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
727 u8 rx_pause,
728 struct ethtool_link_ksettings *link_ksettings)
729 {
730 unsigned long *advertising = link_ksettings->link_modes.advertising;
731
732 ptys2ethtool_adver_link(advertising, eth_proto_cap);
733 if (rx_pause)
734 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
735 if (tx_pause ^ rx_pause)
736 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
737 }
738
739 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
740 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
741 [MLX5E_PORT_NONE] = PORT_NONE,
742 [MLX5E_PORT_TP] = PORT_TP,
743 [MLX5E_PORT_AUI] = PORT_AUI,
744 [MLX5E_PORT_BNC] = PORT_BNC,
745 [MLX5E_PORT_MII] = PORT_MII,
746 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
747 [MLX5E_PORT_DA] = PORT_DA,
748 [MLX5E_PORT_OTHER] = PORT_OTHER,
749 };
750
751 static u8 get_connector_port(u32 eth_proto, u8 connector_type)
752 {
753 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
754 return ptys2connector_type[connector_type];
755
756 if (eth_proto &
757 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
758 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
759 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
760 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
761 return PORT_FIBRE;
762 }
763
764 if (eth_proto &
765 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
766 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
767 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
768 return PORT_DA;
769 }
770
771 if (eth_proto &
772 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
773 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
774 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
775 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
776 return PORT_NONE;
777 }
778
779 return PORT_OTHER;
780 }
781
782 static void get_lp_advertising(u32 eth_proto_lp,
783 struct ethtool_link_ksettings *link_ksettings)
784 {
785 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
786
787 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
788 }
789
790 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
791 struct ethtool_link_ksettings *link_ksettings)
792 {
793 struct mlx5_core_dev *mdev = priv->mdev;
794 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
795 u32 rx_pause = 0;
796 u32 tx_pause = 0;
797 u32 eth_proto_cap;
798 u32 eth_proto_admin;
799 u32 eth_proto_lp;
800 u32 eth_proto_oper;
801 u8 an_disable_admin;
802 u8 an_status;
803 u8 connector_type;
804 int err;
805
806 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
807 if (err) {
808 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
809 __func__, err);
810 goto err_query_regs;
811 }
812
813 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
814 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
815 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
816 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
817 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
818 an_status = MLX5_GET(ptys_reg, out, an_status);
819 connector_type = MLX5_GET(ptys_reg, out, connector_type);
820
821 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
822
823 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
824 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
825
826 get_supported(eth_proto_cap, link_ksettings);
827 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings);
828 get_speed_duplex(priv->netdev, eth_proto_oper, link_ksettings);
829
830 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
831
832 link_ksettings->base.port = get_connector_port(eth_proto_oper,
833 connector_type);
834 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
835 connector_type);
836 get_lp_advertising(eth_proto_lp, link_ksettings);
837
838 if (an_status == MLX5_AN_COMPLETE)
839 ethtool_link_ksettings_add_link_mode(link_ksettings,
840 lp_advertising, Autoneg);
841
842 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
843 AUTONEG_ENABLE;
844 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
845 Autoneg);
846
847 err = get_fec_supported_advertised(mdev, link_ksettings);
848 if (err) {
849 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
850 __func__, err);
851 err = 0; /* don't fail caps query because of FEC error */
852 }
853
854 if (!an_disable_admin)
855 ethtool_link_ksettings_add_link_mode(link_ksettings,
856 advertising, Autoneg);
857
858 err_query_regs:
859 return err;
860 }
861
862 static int mlx5e_get_link_ksettings(struct net_device *netdev,
863 struct ethtool_link_ksettings *link_ksettings)
864 {
865 struct mlx5e_priv *priv = netdev_priv(netdev);
866
867 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
868 }
869
870 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
871 {
872 u32 i, ptys_modes = 0;
873
874 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
875 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
876 link_modes,
877 __ETHTOOL_LINK_MODE_MASK_NBITS))
878 ptys_modes |= MLX5E_PROT_MASK(i);
879 }
880
881 return ptys_modes;
882 }
883
884 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
885 const struct ethtool_link_ksettings *link_ksettings)
886 {
887 struct mlx5_core_dev *mdev = priv->mdev;
888 u32 eth_proto_cap, eth_proto_admin;
889 bool an_changes = false;
890 u8 an_disable_admin;
891 u8 an_disable_cap;
892 bool an_disable;
893 u32 link_modes;
894 u8 an_status;
895 u32 speed;
896 int err;
897
898 speed = link_ksettings->base.speed;
899
900 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
901 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
902 mlx5e_port_speed2linkmodes(speed);
903
904 err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
905 if (err) {
906 netdev_err(priv->netdev, "%s: query port eth proto cap failed: %d\n",
907 __func__, err);
908 goto out;
909 }
910
911 link_modes = link_modes & eth_proto_cap;
912 if (!link_modes) {
913 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
914 __func__);
915 err = -EINVAL;
916 goto out;
917 }
918
919 err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
920 if (err) {
921 netdev_err(priv->netdev, "%s: query port eth proto admin failed: %d\n",
922 __func__, err);
923 goto out;
924 }
925
926 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
927 &an_disable_cap, &an_disable_admin);
928
929 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
930 an_changes = ((!an_disable && an_disable_admin) ||
931 (an_disable && !an_disable_admin));
932
933 if (!an_changes && link_modes == eth_proto_admin)
934 goto out;
935
936 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
937 mlx5_toggle_port_link(mdev);
938
939 out:
940 return err;
941 }
942
943 static int mlx5e_set_link_ksettings(struct net_device *netdev,
944 const struct ethtool_link_ksettings *link_ksettings)
945 {
946 struct mlx5e_priv *priv = netdev_priv(netdev);
947
948 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
949 }
950
951 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
952 {
953 return sizeof(priv->rss_params.toeplitz_hash_key);
954 }
955
956 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
957 {
958 struct mlx5e_priv *priv = netdev_priv(netdev);
959
960 return mlx5e_ethtool_get_rxfh_key_size(priv);
961 }
962
963 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
964 {
965 return MLX5E_INDIR_RQT_SIZE;
966 }
967
968 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
969 {
970 struct mlx5e_priv *priv = netdev_priv(netdev);
971
972 return mlx5e_ethtool_get_rxfh_indir_size(priv);
973 }
974
975 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
976 u8 *hfunc)
977 {
978 struct mlx5e_priv *priv = netdev_priv(netdev);
979 struct mlx5e_rss_params *rss = &priv->rss_params;
980
981 if (indir)
982 memcpy(indir, rss->indirection_rqt,
983 sizeof(rss->indirection_rqt));
984
985 if (key)
986 memcpy(key, rss->toeplitz_hash_key,
987 sizeof(rss->toeplitz_hash_key));
988
989 if (hfunc)
990 *hfunc = rss->hfunc;
991
992 return 0;
993 }
994
995 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
996 const u8 *key, const u8 hfunc)
997 {
998 struct mlx5e_priv *priv = netdev_priv(dev);
999 struct mlx5e_rss_params *rss = &priv->rss_params;
1000 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1001 bool hash_changed = false;
1002 void *in;
1003
1004 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1005 (hfunc != ETH_RSS_HASH_XOR) &&
1006 (hfunc != ETH_RSS_HASH_TOP))
1007 return -EINVAL;
1008
1009 in = kvzalloc(inlen, GFP_KERNEL);
1010 if (!in)
1011 return -ENOMEM;
1012
1013 mutex_lock(&priv->state_lock);
1014
1015 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1016 rss->hfunc = hfunc;
1017 hash_changed = true;
1018 }
1019
1020 if (indir) {
1021 memcpy(rss->indirection_rqt, indir,
1022 sizeof(rss->indirection_rqt));
1023
1024 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1025 u32 rqtn = priv->indir_rqt.rqtn;
1026 struct mlx5e_redirect_rqt_param rrp = {
1027 .is_rss = true,
1028 {
1029 .rss = {
1030 .hfunc = rss->hfunc,
1031 .channels = &priv->channels,
1032 },
1033 },
1034 };
1035
1036 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1037 }
1038 }
1039
1040 if (key) {
1041 memcpy(rss->toeplitz_hash_key, key,
1042 sizeof(rss->toeplitz_hash_key));
1043 hash_changed = hash_changed || rss->hfunc == ETH_RSS_HASH_TOP;
1044 }
1045
1046 if (hash_changed)
1047 mlx5e_modify_tirs_hash(priv, in, inlen);
1048
1049 mutex_unlock(&priv->state_lock);
1050
1051 kvfree(in);
1052
1053 return 0;
1054 }
1055
1056 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1057 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1058 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1059 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1060 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1061 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1062 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1063
1064 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1065 u16 *pfc_prevention_tout)
1066 {
1067 struct mlx5e_priv *priv = netdev_priv(netdev);
1068 struct mlx5_core_dev *mdev = priv->mdev;
1069
1070 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1071 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1072 return -EOPNOTSUPP;
1073
1074 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1075 }
1076
1077 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1078 u16 pfc_preven)
1079 {
1080 struct mlx5e_priv *priv = netdev_priv(netdev);
1081 struct mlx5_core_dev *mdev = priv->mdev;
1082 u16 critical_tout;
1083 u16 minor;
1084
1085 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1086 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1087 return -EOPNOTSUPP;
1088
1089 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1090 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1091 pfc_preven;
1092
1093 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1094 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1095 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1096 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1097 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1098 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1099 return -EINVAL;
1100 }
1101
1102 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1103 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1104 minor);
1105 }
1106
1107 static int mlx5e_get_tunable(struct net_device *dev,
1108 const struct ethtool_tunable *tuna,
1109 void *data)
1110 {
1111 int err;
1112
1113 switch (tuna->id) {
1114 case ETHTOOL_PFC_PREVENTION_TOUT:
1115 err = mlx5e_get_pfc_prevention_tout(dev, data);
1116 break;
1117 default:
1118 err = -EINVAL;
1119 break;
1120 }
1121
1122 return err;
1123 }
1124
1125 static int mlx5e_set_tunable(struct net_device *dev,
1126 const struct ethtool_tunable *tuna,
1127 const void *data)
1128 {
1129 struct mlx5e_priv *priv = netdev_priv(dev);
1130 int err;
1131
1132 mutex_lock(&priv->state_lock);
1133
1134 switch (tuna->id) {
1135 case ETHTOOL_PFC_PREVENTION_TOUT:
1136 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1137 break;
1138 default:
1139 err = -EINVAL;
1140 break;
1141 }
1142
1143 mutex_unlock(&priv->state_lock);
1144 return err;
1145 }
1146
1147 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1148 struct ethtool_pauseparam *pauseparam)
1149 {
1150 struct mlx5_core_dev *mdev = priv->mdev;
1151 int err;
1152
1153 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1154 &pauseparam->tx_pause);
1155 if (err) {
1156 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1157 __func__, err);
1158 }
1159 }
1160
1161 static void mlx5e_get_pauseparam(struct net_device *netdev,
1162 struct ethtool_pauseparam *pauseparam)
1163 {
1164 struct mlx5e_priv *priv = netdev_priv(netdev);
1165
1166 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1167 }
1168
1169 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1170 struct ethtool_pauseparam *pauseparam)
1171 {
1172 struct mlx5_core_dev *mdev = priv->mdev;
1173 int err;
1174
1175 if (pauseparam->autoneg)
1176 return -EINVAL;
1177
1178 err = mlx5_set_port_pause(mdev,
1179 pauseparam->rx_pause ? 1 : 0,
1180 pauseparam->tx_pause ? 1 : 0);
1181 if (err) {
1182 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1183 __func__, err);
1184 }
1185
1186 return err;
1187 }
1188
1189 static int mlx5e_set_pauseparam(struct net_device *netdev,
1190 struct ethtool_pauseparam *pauseparam)
1191 {
1192 struct mlx5e_priv *priv = netdev_priv(netdev);
1193
1194 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1195 }
1196
1197 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1198 struct ethtool_ts_info *info)
1199 {
1200 struct mlx5_core_dev *mdev = priv->mdev;
1201
1202 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1203
1204 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1205 info->phc_index == -1)
1206 return 0;
1207
1208 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1209 SOF_TIMESTAMPING_RX_HARDWARE |
1210 SOF_TIMESTAMPING_RAW_HARDWARE;
1211
1212 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1213 BIT(HWTSTAMP_TX_ON);
1214
1215 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1216 BIT(HWTSTAMP_FILTER_ALL);
1217
1218 return 0;
1219 }
1220
1221 static int mlx5e_get_ts_info(struct net_device *dev,
1222 struct ethtool_ts_info *info)
1223 {
1224 struct mlx5e_priv *priv = netdev_priv(dev);
1225
1226 return mlx5e_ethtool_get_ts_info(priv, info);
1227 }
1228
1229 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1230 {
1231 __u32 ret = 0;
1232
1233 if (MLX5_CAP_GEN(mdev, wol_g))
1234 ret |= WAKE_MAGIC;
1235
1236 if (MLX5_CAP_GEN(mdev, wol_s))
1237 ret |= WAKE_MAGICSECURE;
1238
1239 if (MLX5_CAP_GEN(mdev, wol_a))
1240 ret |= WAKE_ARP;
1241
1242 if (MLX5_CAP_GEN(mdev, wol_b))
1243 ret |= WAKE_BCAST;
1244
1245 if (MLX5_CAP_GEN(mdev, wol_m))
1246 ret |= WAKE_MCAST;
1247
1248 if (MLX5_CAP_GEN(mdev, wol_u))
1249 ret |= WAKE_UCAST;
1250
1251 if (MLX5_CAP_GEN(mdev, wol_p))
1252 ret |= WAKE_PHY;
1253
1254 return ret;
1255 }
1256
1257 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1258 {
1259 __u32 ret = 0;
1260
1261 if (mode & MLX5_WOL_MAGIC)
1262 ret |= WAKE_MAGIC;
1263
1264 if (mode & MLX5_WOL_SECURED_MAGIC)
1265 ret |= WAKE_MAGICSECURE;
1266
1267 if (mode & MLX5_WOL_ARP)
1268 ret |= WAKE_ARP;
1269
1270 if (mode & MLX5_WOL_BROADCAST)
1271 ret |= WAKE_BCAST;
1272
1273 if (mode & MLX5_WOL_MULTICAST)
1274 ret |= WAKE_MCAST;
1275
1276 if (mode & MLX5_WOL_UNICAST)
1277 ret |= WAKE_UCAST;
1278
1279 if (mode & MLX5_WOL_PHY_ACTIVITY)
1280 ret |= WAKE_PHY;
1281
1282 return ret;
1283 }
1284
1285 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1286 {
1287 u8 ret = 0;
1288
1289 if (mode & WAKE_MAGIC)
1290 ret |= MLX5_WOL_MAGIC;
1291
1292 if (mode & WAKE_MAGICSECURE)
1293 ret |= MLX5_WOL_SECURED_MAGIC;
1294
1295 if (mode & WAKE_ARP)
1296 ret |= MLX5_WOL_ARP;
1297
1298 if (mode & WAKE_BCAST)
1299 ret |= MLX5_WOL_BROADCAST;
1300
1301 if (mode & WAKE_MCAST)
1302 ret |= MLX5_WOL_MULTICAST;
1303
1304 if (mode & WAKE_UCAST)
1305 ret |= MLX5_WOL_UNICAST;
1306
1307 if (mode & WAKE_PHY)
1308 ret |= MLX5_WOL_PHY_ACTIVITY;
1309
1310 return ret;
1311 }
1312
1313 static void mlx5e_get_wol(struct net_device *netdev,
1314 struct ethtool_wolinfo *wol)
1315 {
1316 struct mlx5e_priv *priv = netdev_priv(netdev);
1317 struct mlx5_core_dev *mdev = priv->mdev;
1318 u8 mlx5_wol_mode;
1319 int err;
1320
1321 memset(wol, 0, sizeof(*wol));
1322
1323 wol->supported = mlx5e_get_wol_supported(mdev);
1324 if (!wol->supported)
1325 return;
1326
1327 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1328 if (err)
1329 return;
1330
1331 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1332 }
1333
1334 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1335 {
1336 struct mlx5e_priv *priv = netdev_priv(netdev);
1337 struct mlx5_core_dev *mdev = priv->mdev;
1338 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1339 u32 mlx5_wol_mode;
1340
1341 if (!wol_supported)
1342 return -EOPNOTSUPP;
1343
1344 if (wol->wolopts & ~wol_supported)
1345 return -EINVAL;
1346
1347 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1348
1349 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1350 }
1351
1352 static int mlx5e_get_fecparam(struct net_device *netdev,
1353 struct ethtool_fecparam *fecparam)
1354 {
1355 struct mlx5e_priv *priv = netdev_priv(netdev);
1356 struct mlx5_core_dev *mdev = priv->mdev;
1357 u8 fec_configured = 0;
1358 u32 fec_active = 0;
1359 int err;
1360
1361 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1362
1363 if (err)
1364 return err;
1365
1366 fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active,
1367 sizeof(u32) * BITS_PER_BYTE);
1368
1369 if (!fecparam->active_fec)
1370 return -EOPNOTSUPP;
1371
1372 fecparam->fec = pplm2ethtool_fec((u_long)fec_configured,
1373 sizeof(u8) * BITS_PER_BYTE);
1374
1375 return 0;
1376 }
1377
1378 static int mlx5e_set_fecparam(struct net_device *netdev,
1379 struct ethtool_fecparam *fecparam)
1380 {
1381 struct mlx5e_priv *priv = netdev_priv(netdev);
1382 struct mlx5_core_dev *mdev = priv->mdev;
1383 u8 fec_policy = 0;
1384 int mode;
1385 int err;
1386
1387 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1388 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1389 continue;
1390 fec_policy |= (1 << mode);
1391 break;
1392 }
1393
1394 err = mlx5e_set_fec_mode(mdev, fec_policy);
1395
1396 if (err)
1397 return err;
1398
1399 mlx5_toggle_port_link(mdev);
1400
1401 return 0;
1402 }
1403
1404 static u32 mlx5e_get_msglevel(struct net_device *dev)
1405 {
1406 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1407 }
1408
1409 static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1410 {
1411 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1412 }
1413
1414 static int mlx5e_set_phys_id(struct net_device *dev,
1415 enum ethtool_phys_id_state state)
1416 {
1417 struct mlx5e_priv *priv = netdev_priv(dev);
1418 struct mlx5_core_dev *mdev = priv->mdev;
1419 u16 beacon_duration;
1420
1421 if (!MLX5_CAP_GEN(mdev, beacon_led))
1422 return -EOPNOTSUPP;
1423
1424 switch (state) {
1425 case ETHTOOL_ID_ACTIVE:
1426 beacon_duration = MLX5_BEACON_DURATION_INF;
1427 break;
1428 case ETHTOOL_ID_INACTIVE:
1429 beacon_duration = MLX5_BEACON_DURATION_OFF;
1430 break;
1431 default:
1432 return -EOPNOTSUPP;
1433 }
1434
1435 return mlx5_set_port_beacon(mdev, beacon_duration);
1436 }
1437
1438 static int mlx5e_get_module_info(struct net_device *netdev,
1439 struct ethtool_modinfo *modinfo)
1440 {
1441 struct mlx5e_priv *priv = netdev_priv(netdev);
1442 struct mlx5_core_dev *dev = priv->mdev;
1443 int size_read = 0;
1444 u8 data[4];
1445
1446 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1447 if (size_read < 2)
1448 return -EIO;
1449
1450 /* data[0] = identifier byte */
1451 switch (data[0]) {
1452 case MLX5_MODULE_ID_QSFP:
1453 modinfo->type = ETH_MODULE_SFF_8436;
1454 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1455 break;
1456 case MLX5_MODULE_ID_QSFP_PLUS:
1457 case MLX5_MODULE_ID_QSFP28:
1458 /* data[1] = revision id */
1459 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1460 modinfo->type = ETH_MODULE_SFF_8636;
1461 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1462 } else {
1463 modinfo->type = ETH_MODULE_SFF_8436;
1464 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1465 }
1466 break;
1467 case MLX5_MODULE_ID_SFP:
1468 modinfo->type = ETH_MODULE_SFF_8472;
1469 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1470 break;
1471 default:
1472 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1473 __func__, data[0]);
1474 return -EINVAL;
1475 }
1476
1477 return 0;
1478 }
1479
1480 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1481 struct ethtool_eeprom *ee,
1482 u8 *data)
1483 {
1484 struct mlx5e_priv *priv = netdev_priv(netdev);
1485 struct mlx5_core_dev *mdev = priv->mdev;
1486 int offset = ee->offset;
1487 int size_read;
1488 int i = 0;
1489
1490 if (!ee->len)
1491 return -EINVAL;
1492
1493 memset(data, 0, ee->len);
1494
1495 while (i < ee->len) {
1496 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1497 data + i);
1498
1499 if (!size_read)
1500 /* Done reading */
1501 return 0;
1502
1503 if (size_read < 0) {
1504 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1505 __func__, size_read);
1506 return 0;
1507 }
1508
1509 i += size_read;
1510 offset += size_read;
1511 }
1512
1513 return 0;
1514 }
1515
1516 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1517 bool is_rx_cq)
1518 {
1519 struct mlx5e_priv *priv = netdev_priv(netdev);
1520 struct mlx5_core_dev *mdev = priv->mdev;
1521 struct mlx5e_channels new_channels = {};
1522 bool mode_changed;
1523 u8 cq_period_mode, current_cq_period_mode;
1524 int err = 0;
1525
1526 cq_period_mode = enable ?
1527 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1528 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1529 current_cq_period_mode = is_rx_cq ?
1530 priv->channels.params.rx_cq_moderation.cq_period_mode :
1531 priv->channels.params.tx_cq_moderation.cq_period_mode;
1532 mode_changed = cq_period_mode != current_cq_period_mode;
1533
1534 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1535 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1536 return -EOPNOTSUPP;
1537
1538 if (!mode_changed)
1539 return 0;
1540
1541 new_channels.params = priv->channels.params;
1542 if (is_rx_cq)
1543 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1544 else
1545 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
1546
1547 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1548 priv->channels.params = new_channels.params;
1549 return 0;
1550 }
1551
1552 err = mlx5e_open_channels(priv, &new_channels);
1553 if (err)
1554 return err;
1555
1556 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1557 return 0;
1558 }
1559
1560 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1561 {
1562 return set_pflag_cqe_based_moder(netdev, enable, false);
1563 }
1564
1565 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1566 {
1567 return set_pflag_cqe_based_moder(netdev, enable, true);
1568 }
1569
1570 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1571 {
1572 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1573 struct mlx5e_channels new_channels = {};
1574 int err = 0;
1575
1576 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1577 return new_val ? -EOPNOTSUPP : 0;
1578
1579 if (curr_val == new_val)
1580 return 0;
1581
1582 new_channels.params = priv->channels.params;
1583 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1584
1585 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1586 priv->channels.params = new_channels.params;
1587 return 0;
1588 }
1589
1590 err = mlx5e_open_channels(priv, &new_channels);
1591 if (err)
1592 return err;
1593
1594 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1595 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1596 MLX5E_GET_PFLAG(&priv->channels.params,
1597 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1598
1599 return 0;
1600 }
1601
1602 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1603 bool enable)
1604 {
1605 struct mlx5e_priv *priv = netdev_priv(netdev);
1606 struct mlx5_core_dev *mdev = priv->mdev;
1607
1608 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1609 return -EOPNOTSUPP;
1610
1611 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
1612 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1613 return -EINVAL;
1614 }
1615
1616 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1617 priv->channels.params.rx_cqe_compress_def = enable;
1618
1619 return 0;
1620 }
1621
1622 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1623 {
1624 struct mlx5e_priv *priv = netdev_priv(netdev);
1625 struct mlx5_core_dev *mdev = priv->mdev;
1626 struct mlx5e_channels new_channels = {};
1627 int err;
1628
1629 if (enable) {
1630 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1631 return -EOPNOTSUPP;
1632 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1633 return -EINVAL;
1634 } else if (priv->channels.params.lro_en) {
1635 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1636 return -EINVAL;
1637 }
1638
1639 new_channels.params = priv->channels.params;
1640
1641 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1642 mlx5e_set_rq_type(mdev, &new_channels.params);
1643
1644 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1645 priv->channels.params = new_channels.params;
1646 return 0;
1647 }
1648
1649 err = mlx5e_open_channels(priv, &new_channels);
1650 if (err)
1651 return err;
1652
1653 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1654 return 0;
1655 }
1656
1657 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1658 {
1659 struct mlx5e_priv *priv = netdev_priv(netdev);
1660 struct mlx5e_channels *channels = &priv->channels;
1661 struct mlx5e_channel *c;
1662 int i;
1663
1664 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1665 return 0;
1666
1667 for (i = 0; i < channels->num; i++) {
1668 c = channels->c[i];
1669 if (enable)
1670 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1671 else
1672 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1673 }
1674
1675 return 0;
1676 }
1677
1678 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1679 {
1680 struct mlx5e_priv *priv = netdev_priv(netdev);
1681 struct mlx5_core_dev *mdev = priv->mdev;
1682 struct mlx5e_channels new_channels = {};
1683 int err;
1684
1685 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1686 return -EOPNOTSUPP;
1687
1688 new_channels.params = priv->channels.params;
1689
1690 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1691
1692 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1693 priv->channels.params = new_channels.params;
1694 return 0;
1695 }
1696
1697 err = mlx5e_open_channels(priv, &new_channels);
1698 if (err)
1699 return err;
1700
1701 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1702 return 0;
1703 }
1704
1705 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
1706 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
1707 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
1708 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
1709 { "rx_striding_rq", set_pflag_rx_striding_rq },
1710 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
1711 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
1712 };
1713
1714 static int mlx5e_handle_pflag(struct net_device *netdev,
1715 u32 wanted_flags,
1716 enum mlx5e_priv_flag flag)
1717 {
1718 struct mlx5e_priv *priv = netdev_priv(netdev);
1719 bool enable = !!(wanted_flags & BIT(flag));
1720 u32 changes = wanted_flags ^ priv->channels.params.pflags;
1721 int err;
1722
1723 if (!(changes & BIT(flag)))
1724 return 0;
1725
1726 err = mlx5e_priv_flags[flag].handler(netdev, enable);
1727 if (err) {
1728 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
1729 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
1730 return err;
1731 }
1732
1733 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
1734 return 0;
1735 }
1736
1737 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1738 {
1739 struct mlx5e_priv *priv = netdev_priv(netdev);
1740 enum mlx5e_priv_flag pflag;
1741 int err;
1742
1743 mutex_lock(&priv->state_lock);
1744
1745 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
1746 err = mlx5e_handle_pflag(netdev, pflags, pflag);
1747 if (err)
1748 break;
1749 }
1750
1751 mutex_unlock(&priv->state_lock);
1752
1753 /* Need to fix some features.. */
1754 netdev_update_features(netdev);
1755
1756 return err;
1757 }
1758
1759 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1760 {
1761 struct mlx5e_priv *priv = netdev_priv(netdev);
1762
1763 return priv->channels.params.pflags;
1764 }
1765
1766 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1767 struct ethtool_flash *flash)
1768 {
1769 struct mlx5_core_dev *mdev = priv->mdev;
1770 struct net_device *dev = priv->netdev;
1771 const struct firmware *fw;
1772 int err;
1773
1774 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1775 return -EOPNOTSUPP;
1776
1777 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1778 if (err)
1779 return err;
1780
1781 dev_hold(dev);
1782 rtnl_unlock();
1783
1784 err = mlx5_firmware_flash(mdev, fw);
1785 release_firmware(fw);
1786
1787 rtnl_lock();
1788 dev_put(dev);
1789 return err;
1790 }
1791
1792 static int mlx5e_flash_device(struct net_device *dev,
1793 struct ethtool_flash *flash)
1794 {
1795 struct mlx5e_priv *priv = netdev_priv(dev);
1796
1797 return mlx5e_ethtool_flash_device(priv, flash);
1798 }
1799
1800 const struct ethtool_ops mlx5e_ethtool_ops = {
1801 .get_drvinfo = mlx5e_get_drvinfo,
1802 .get_link = ethtool_op_get_link,
1803 .get_strings = mlx5e_get_strings,
1804 .get_sset_count = mlx5e_get_sset_count,
1805 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1806 .get_ringparam = mlx5e_get_ringparam,
1807 .set_ringparam = mlx5e_set_ringparam,
1808 .get_channels = mlx5e_get_channels,
1809 .set_channels = mlx5e_set_channels,
1810 .get_coalesce = mlx5e_get_coalesce,
1811 .set_coalesce = mlx5e_set_coalesce,
1812 .get_link_ksettings = mlx5e_get_link_ksettings,
1813 .set_link_ksettings = mlx5e_set_link_ksettings,
1814 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1815 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1816 .get_rxfh = mlx5e_get_rxfh,
1817 .set_rxfh = mlx5e_set_rxfh,
1818 #ifdef CONFIG_MLX5_EN_RXNFC
1819 .get_rxnfc = mlx5e_get_rxnfc,
1820 .set_rxnfc = mlx5e_set_rxnfc,
1821 #endif
1822 .flash_device = mlx5e_flash_device,
1823 .get_tunable = mlx5e_get_tunable,
1824 .set_tunable = mlx5e_set_tunable,
1825 .get_pauseparam = mlx5e_get_pauseparam,
1826 .set_pauseparam = mlx5e_set_pauseparam,
1827 .get_ts_info = mlx5e_get_ts_info,
1828 .set_phys_id = mlx5e_set_phys_id,
1829 .get_wol = mlx5e_get_wol,
1830 .set_wol = mlx5e_set_wol,
1831 .get_module_info = mlx5e_get_module_info,
1832 .get_module_eeprom = mlx5e_get_module_eeprom,
1833 .get_priv_flags = mlx5e_get_priv_flags,
1834 .set_priv_flags = mlx5e_set_priv_flags,
1835 .self_test = mlx5e_self_test,
1836 .get_msglevel = mlx5e_get_msglevel,
1837 .set_msglevel = mlx5e_set_msglevel,
1838 .get_fecparam = mlx5e_get_fecparam,
1839 .set_fecparam = mlx5e_set_fecparam,
1840 };
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