2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
42 struct mlx5e_rq_param
{
43 u32 rqc
[MLX5_ST_SZ_DW(rqc
)];
44 struct mlx5_wq_param wq
;
48 struct mlx5e_sq_param
{
49 u32 sqc
[MLX5_ST_SZ_DW(sqc
)];
50 struct mlx5_wq_param wq
;
56 struct mlx5e_cq_param
{
57 u32 cqc
[MLX5_ST_SZ_DW(cqc
)];
58 struct mlx5_wq_param wq
;
63 struct mlx5e_channel_param
{
64 struct mlx5e_rq_param rq
;
65 struct mlx5e_sq_param sq
;
66 struct mlx5e_sq_param icosq
;
67 struct mlx5e_cq_param rx_cq
;
68 struct mlx5e_cq_param tx_cq
;
69 struct mlx5e_cq_param icosq_cq
;
72 static void mlx5e_update_carrier(struct mlx5e_priv
*priv
)
74 struct mlx5_core_dev
*mdev
= priv
->mdev
;
77 port_state
= mlx5_query_vport_state(mdev
,
78 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT
, 0);
80 if (port_state
== VPORT_STATE_UP
) {
81 netdev_info(priv
->netdev
, "Link up\n");
82 netif_carrier_on(priv
->netdev
);
84 netdev_info(priv
->netdev
, "Link down\n");
85 netif_carrier_off(priv
->netdev
);
89 static void mlx5e_update_carrier_work(struct work_struct
*work
)
91 struct mlx5e_priv
*priv
= container_of(work
, struct mlx5e_priv
,
94 mutex_lock(&priv
->state_lock
);
95 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
96 mlx5e_update_carrier(priv
);
97 mutex_unlock(&priv
->state_lock
);
100 static void mlx5e_tx_timeout_work(struct work_struct
*work
)
102 struct mlx5e_priv
*priv
= container_of(work
, struct mlx5e_priv
,
107 mutex_lock(&priv
->state_lock
);
108 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
110 mlx5e_close_locked(priv
->netdev
);
111 err
= mlx5e_open_locked(priv
->netdev
);
113 netdev_err(priv
->netdev
, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
116 mutex_unlock(&priv
->state_lock
);
120 static void mlx5e_update_sw_counters(struct mlx5e_priv
*priv
)
122 struct mlx5e_sw_stats
*s
= &priv
->stats
.sw
;
123 struct mlx5e_rq_stats
*rq_stats
;
124 struct mlx5e_sq_stats
*sq_stats
;
125 u64 tx_offload_none
= 0;
128 memset(s
, 0, sizeof(*s
));
129 for (i
= 0; i
< priv
->params
.num_channels
; i
++) {
130 rq_stats
= &priv
->channel
[i
]->rq
.stats
;
132 s
->rx_packets
+= rq_stats
->packets
;
133 s
->rx_bytes
+= rq_stats
->bytes
;
134 s
->rx_lro_packets
+= rq_stats
->lro_packets
;
135 s
->rx_lro_bytes
+= rq_stats
->lro_bytes
;
136 s
->rx_csum_none
+= rq_stats
->csum_none
;
137 s
->rx_csum_complete
+= rq_stats
->csum_complete
;
138 s
->rx_csum_unnecessary_inner
+= rq_stats
->csum_unnecessary_inner
;
139 s
->rx_wqe_err
+= rq_stats
->wqe_err
;
140 s
->rx_mpwqe_filler
+= rq_stats
->mpwqe_filler
;
141 s
->rx_mpwqe_frag
+= rq_stats
->mpwqe_frag
;
142 s
->rx_buff_alloc_err
+= rq_stats
->buff_alloc_err
;
143 s
->rx_cqe_compress_blks
+= rq_stats
->cqe_compress_blks
;
144 s
->rx_cqe_compress_pkts
+= rq_stats
->cqe_compress_pkts
;
146 for (j
= 0; j
< priv
->params
.num_tc
; j
++) {
147 sq_stats
= &priv
->channel
[i
]->sq
[j
].stats
;
149 s
->tx_packets
+= sq_stats
->packets
;
150 s
->tx_bytes
+= sq_stats
->bytes
;
151 s
->tx_tso_packets
+= sq_stats
->tso_packets
;
152 s
->tx_tso_bytes
+= sq_stats
->tso_bytes
;
153 s
->tx_tso_inner_packets
+= sq_stats
->tso_inner_packets
;
154 s
->tx_tso_inner_bytes
+= sq_stats
->tso_inner_bytes
;
155 s
->tx_queue_stopped
+= sq_stats
->stopped
;
156 s
->tx_queue_wake
+= sq_stats
->wake
;
157 s
->tx_queue_dropped
+= sq_stats
->dropped
;
158 s
->tx_xmit_more
+= sq_stats
->xmit_more
;
159 s
->tx_csum_partial_inner
+= sq_stats
->csum_partial_inner
;
160 tx_offload_none
+= sq_stats
->csum_none
;
164 /* Update calculated offload counters */
165 s
->tx_csum_partial
= s
->tx_packets
- tx_offload_none
- s
->tx_csum_partial_inner
;
166 s
->rx_csum_unnecessary
= s
->rx_packets
- s
->rx_csum_none
- s
->rx_csum_complete
;
168 s
->link_down_events_phy
= MLX5_GET(ppcnt_reg
,
169 priv
->stats
.pport
.phy_counters
,
170 counter_set
.phys_layer_cntrs
.link_down_events
);
173 static void mlx5e_update_vport_counters(struct mlx5e_priv
*priv
)
175 int outlen
= MLX5_ST_SZ_BYTES(query_vport_counter_out
);
176 u32
*out
= (u32
*)priv
->stats
.vport
.query_vport_out
;
177 u32 in
[MLX5_ST_SZ_DW(query_vport_counter_in
)];
178 struct mlx5_core_dev
*mdev
= priv
->mdev
;
180 memset(in
, 0, sizeof(in
));
182 MLX5_SET(query_vport_counter_in
, in
, opcode
,
183 MLX5_CMD_OP_QUERY_VPORT_COUNTER
);
184 MLX5_SET(query_vport_counter_in
, in
, op_mod
, 0);
185 MLX5_SET(query_vport_counter_in
, in
, other_vport
, 0);
187 memset(out
, 0, outlen
);
189 mlx5_cmd_exec(mdev
, in
, sizeof(in
), out
, outlen
);
192 static void mlx5e_update_pport_counters(struct mlx5e_priv
*priv
)
194 struct mlx5e_pport_stats
*pstats
= &priv
->stats
.pport
;
195 struct mlx5_core_dev
*mdev
= priv
->mdev
;
196 int sz
= MLX5_ST_SZ_BYTES(ppcnt_reg
);
201 in
= mlx5_vzalloc(sz
);
205 MLX5_SET(ppcnt_reg
, in
, local_port
, 1);
207 out
= pstats
->IEEE_802_3_counters
;
208 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_IEEE_802_3_COUNTERS_GROUP
);
209 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
211 out
= pstats
->RFC_2863_counters
;
212 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2863_COUNTERS_GROUP
);
213 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
215 out
= pstats
->RFC_2819_counters
;
216 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2819_COUNTERS_GROUP
);
217 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
219 out
= pstats
->phy_counters
;
220 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP
);
221 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
223 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PER_PRIORITY_COUNTERS_GROUP
);
224 for (prio
= 0; prio
< NUM_PPORT_PRIO
; prio
++) {
225 out
= pstats
->per_prio_counters
[prio
];
226 MLX5_SET(ppcnt_reg
, in
, prio_tc
, prio
);
227 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
,
228 MLX5_REG_PPCNT
, 0, 0);
235 static void mlx5e_update_q_counter(struct mlx5e_priv
*priv
)
237 struct mlx5e_qcounter_stats
*qcnt
= &priv
->stats
.qcnt
;
239 if (!priv
->q_counter
)
242 mlx5_core_query_out_of_buffer(priv
->mdev
, priv
->q_counter
,
243 &qcnt
->rx_out_of_buffer
);
246 void mlx5e_update_stats(struct mlx5e_priv
*priv
)
248 mlx5e_update_q_counter(priv
);
249 mlx5e_update_vport_counters(priv
);
250 mlx5e_update_pport_counters(priv
);
251 mlx5e_update_sw_counters(priv
);
254 void mlx5e_update_stats_work(struct work_struct
*work
)
256 struct delayed_work
*dwork
= to_delayed_work(work
);
257 struct mlx5e_priv
*priv
= container_of(dwork
, struct mlx5e_priv
,
259 mutex_lock(&priv
->state_lock
);
260 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
)) {
261 priv
->profile
->update_stats(priv
);
262 queue_delayed_work(priv
->wq
, dwork
,
263 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL
));
265 mutex_unlock(&priv
->state_lock
);
268 static void mlx5e_async_event(struct mlx5_core_dev
*mdev
, void *vpriv
,
269 enum mlx5_dev_event event
, unsigned long param
)
271 struct mlx5e_priv
*priv
= vpriv
;
273 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
))
277 case MLX5_DEV_EVENT_PORT_UP
:
278 case MLX5_DEV_EVENT_PORT_DOWN
:
279 queue_work(priv
->wq
, &priv
->update_carrier_work
);
287 static void mlx5e_enable_async_events(struct mlx5e_priv
*priv
)
289 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
);
292 static void mlx5e_disable_async_events(struct mlx5e_priv
*priv
)
294 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
);
295 synchronize_irq(mlx5_get_msix_vec(priv
->mdev
, MLX5_EQ_VEC_ASYNC
));
298 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
299 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
301 static int mlx5e_create_rq(struct mlx5e_channel
*c
,
302 struct mlx5e_rq_param
*param
,
305 struct mlx5e_priv
*priv
= c
->priv
;
306 struct mlx5_core_dev
*mdev
= priv
->mdev
;
307 void *rqc
= param
->rqc
;
308 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
314 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
316 err
= mlx5_wq_ll_create(mdev
, ¶m
->wq
, rqc_wq
, &rq
->wq
,
321 rq
->wq
.db
= &rq
->wq
.db
[MLX5_RCV_DBR
];
323 wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
325 switch (priv
->params
.rq_wq_type
) {
326 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
327 rq
->wqe_info
= kzalloc_node(wq_sz
* sizeof(*rq
->wqe_info
),
328 GFP_KERNEL
, cpu_to_node(c
->cpu
));
331 goto err_rq_wq_destroy
;
333 rq
->handle_rx_cqe
= mlx5e_handle_rx_cqe_mpwrq
;
334 rq
->alloc_wqe
= mlx5e_alloc_rx_mpwqe
;
335 rq
->dealloc_wqe
= mlx5e_dealloc_rx_mpwqe
;
337 rq
->mpwqe_mtt_offset
= c
->ix
*
338 MLX5E_REQUIRED_MTTS(1, BIT(priv
->params
.log_rq_size
));
340 rq
->mpwqe_stride_sz
= BIT(priv
->params
.mpwqe_log_stride_sz
);
341 rq
->mpwqe_num_strides
= BIT(priv
->params
.mpwqe_log_num_strides
);
342 rq
->wqe_sz
= rq
->mpwqe_stride_sz
* rq
->mpwqe_num_strides
;
343 byte_count
= rq
->wqe_sz
;
345 default: /* MLX5_WQ_TYPE_LINKED_LIST */
346 rq
->skb
= kzalloc_node(wq_sz
* sizeof(*rq
->skb
), GFP_KERNEL
,
347 cpu_to_node(c
->cpu
));
350 goto err_rq_wq_destroy
;
352 rq
->handle_rx_cqe
= mlx5e_handle_rx_cqe
;
353 rq
->alloc_wqe
= mlx5e_alloc_rx_wqe
;
354 rq
->dealloc_wqe
= mlx5e_dealloc_rx_wqe
;
356 rq
->wqe_sz
= (priv
->params
.lro_en
) ?
357 priv
->params
.lro_wqe_sz
:
358 MLX5E_SW2HW_MTU(priv
->netdev
->mtu
);
359 rq
->wqe_sz
= SKB_DATA_ALIGN(rq
->wqe_sz
);
360 byte_count
= rq
->wqe_sz
;
361 byte_count
|= MLX5_HW_START_PADDING
;
364 for (i
= 0; i
< wq_sz
; i
++) {
365 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, i
);
367 wqe
->data
.byte_count
= cpu_to_be32(byte_count
);
370 INIT_WORK(&rq
->am
.work
, mlx5e_rx_am_work
);
371 rq
->am
.mode
= priv
->params
.rx_cq_period_mode
;
373 rq
->wq_type
= priv
->params
.rq_wq_type
;
375 rq
->netdev
= c
->netdev
;
376 rq
->tstamp
= &priv
->tstamp
;
380 rq
->mkey_be
= c
->mkey_be
;
381 rq
->umr_mkey_be
= cpu_to_be32(c
->priv
->umr_mkey
.key
);
386 mlx5_wq_destroy(&rq
->wq_ctrl
);
391 static void mlx5e_destroy_rq(struct mlx5e_rq
*rq
)
393 switch (rq
->wq_type
) {
394 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
397 default: /* MLX5_WQ_TYPE_LINKED_LIST */
401 mlx5_wq_destroy(&rq
->wq_ctrl
);
404 static int mlx5e_enable_rq(struct mlx5e_rq
*rq
, struct mlx5e_rq_param
*param
)
406 struct mlx5e_priv
*priv
= rq
->priv
;
407 struct mlx5_core_dev
*mdev
= priv
->mdev
;
415 inlen
= MLX5_ST_SZ_BYTES(create_rq_in
) +
416 sizeof(u64
) * rq
->wq_ctrl
.buf
.npages
;
417 in
= mlx5_vzalloc(inlen
);
421 rqc
= MLX5_ADDR_OF(create_rq_in
, in
, ctx
);
422 wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
424 memcpy(rqc
, param
->rqc
, sizeof(param
->rqc
));
426 MLX5_SET(rqc
, rqc
, cqn
, rq
->cq
.mcq
.cqn
);
427 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RST
);
428 MLX5_SET(rqc
, rqc
, vsd
, priv
->params
.vlan_strip_disable
);
429 MLX5_SET(wq
, wq
, log_wq_pg_sz
, rq
->wq_ctrl
.buf
.page_shift
-
430 MLX5_ADAPTER_PAGE_SHIFT
);
431 MLX5_SET64(wq
, wq
, dbr_addr
, rq
->wq_ctrl
.db
.dma
);
433 mlx5_fill_page_array(&rq
->wq_ctrl
.buf
,
434 (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
436 err
= mlx5_core_create_rq(mdev
, in
, inlen
, &rq
->rqn
);
443 static int mlx5e_modify_rq_state(struct mlx5e_rq
*rq
, int curr_state
,
446 struct mlx5e_channel
*c
= rq
->channel
;
447 struct mlx5e_priv
*priv
= c
->priv
;
448 struct mlx5_core_dev
*mdev
= priv
->mdev
;
455 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
456 in
= mlx5_vzalloc(inlen
);
460 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
462 MLX5_SET(modify_rq_in
, in
, rq_state
, curr_state
);
463 MLX5_SET(rqc
, rqc
, state
, next_state
);
465 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
472 static int mlx5e_modify_rq_vsd(struct mlx5e_rq
*rq
, bool vsd
)
474 struct mlx5e_channel
*c
= rq
->channel
;
475 struct mlx5e_priv
*priv
= c
->priv
;
476 struct mlx5_core_dev
*mdev
= priv
->mdev
;
483 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
484 in
= mlx5_vzalloc(inlen
);
488 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
490 MLX5_SET(modify_rq_in
, in
, rq_state
, MLX5_RQC_STATE_RDY
);
491 MLX5_SET64(modify_rq_in
, in
, modify_bitmask
, MLX5_RQ_BITMASK_VSD
);
492 MLX5_SET(rqc
, rqc
, vsd
, vsd
);
493 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RDY
);
495 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
502 static void mlx5e_disable_rq(struct mlx5e_rq
*rq
)
504 mlx5_core_destroy_rq(rq
->priv
->mdev
, rq
->rqn
);
507 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq
*rq
)
509 unsigned long exp_time
= jiffies
+ msecs_to_jiffies(20000);
510 struct mlx5e_channel
*c
= rq
->channel
;
511 struct mlx5e_priv
*priv
= c
->priv
;
512 struct mlx5_wq_ll
*wq
= &rq
->wq
;
514 while (time_before(jiffies
, exp_time
)) {
515 if (wq
->cur_sz
>= priv
->params
.min_rx_wqes
)
524 static void mlx5e_free_rx_descs(struct mlx5e_rq
*rq
)
526 struct mlx5_wq_ll
*wq
= &rq
->wq
;
527 struct mlx5e_rx_wqe
*wqe
;
531 /* UMR WQE (if in progress) is always at wq->head */
532 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS
, &rq
->state
))
533 mlx5e_free_rx_fragmented_mpwqe(rq
, &rq
->wqe_info
[wq
->head
]);
535 while (!mlx5_wq_ll_is_empty(wq
)) {
536 wqe_ix_be
= *wq
->tail_next
;
537 wqe_ix
= be16_to_cpu(wqe_ix_be
);
538 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_ix
);
539 rq
->dealloc_wqe(rq
, wqe_ix
);
540 mlx5_wq_ll_pop(&rq
->wq
, wqe_ix_be
,
541 &wqe
->next
.next_wqe_index
);
545 static int mlx5e_open_rq(struct mlx5e_channel
*c
,
546 struct mlx5e_rq_param
*param
,
549 struct mlx5e_sq
*sq
= &c
->icosq
;
550 u16 pi
= sq
->pc
& sq
->wq
.sz_m1
;
553 err
= mlx5e_create_rq(c
, param
, rq
);
557 err
= mlx5e_enable_rq(rq
, param
);
561 err
= mlx5e_modify_rq_state(rq
, MLX5_RQC_STATE_RST
, MLX5_RQC_STATE_RDY
);
565 if (param
->am_enabled
)
566 set_bit(MLX5E_RQ_STATE_AM
, &c
->rq
.state
);
568 sq
->ico_wqe_info
[pi
].opcode
= MLX5_OPCODE_NOP
;
569 sq
->ico_wqe_info
[pi
].num_wqebbs
= 1;
570 mlx5e_send_nop(sq
, true); /* trigger mlx5e_post_rx_wqes() */
575 mlx5e_disable_rq(rq
);
577 mlx5e_destroy_rq(rq
);
582 static void mlx5e_close_rq(struct mlx5e_rq
*rq
)
584 set_bit(MLX5E_RQ_STATE_FLUSH
, &rq
->state
);
585 napi_synchronize(&rq
->channel
->napi
); /* prevent mlx5e_post_rx_wqes */
586 cancel_work_sync(&rq
->am
.work
);
588 mlx5e_disable_rq(rq
);
589 mlx5e_free_rx_descs(rq
);
590 mlx5e_destroy_rq(rq
);
593 static void mlx5e_free_sq_db(struct mlx5e_sq
*sq
)
600 static int mlx5e_alloc_sq_db(struct mlx5e_sq
*sq
, int numa
)
602 int wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
603 int df_sz
= wq_sz
* MLX5_SEND_WQEBB_NUM_DS
;
605 sq
->skb
= kzalloc_node(wq_sz
* sizeof(*sq
->skb
), GFP_KERNEL
, numa
);
606 sq
->dma_fifo
= kzalloc_node(df_sz
* sizeof(*sq
->dma_fifo
), GFP_KERNEL
,
608 sq
->wqe_info
= kzalloc_node(wq_sz
* sizeof(*sq
->wqe_info
), GFP_KERNEL
,
611 if (!sq
->skb
|| !sq
->dma_fifo
|| !sq
->wqe_info
) {
612 mlx5e_free_sq_db(sq
);
616 sq
->dma_fifo_mask
= df_sz
- 1;
621 static int mlx5e_create_sq(struct mlx5e_channel
*c
,
623 struct mlx5e_sq_param
*param
,
626 struct mlx5e_priv
*priv
= c
->priv
;
627 struct mlx5_core_dev
*mdev
= priv
->mdev
;
629 void *sqc
= param
->sqc
;
630 void *sqc_wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
633 err
= mlx5_alloc_map_uar(mdev
, &sq
->uar
, !!MLX5_CAP_GEN(mdev
, bf
));
637 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
639 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
,
642 goto err_unmap_free_uar
;
644 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
645 if (sq
->uar
.bf_map
) {
646 set_bit(MLX5E_SQ_STATE_BF_ENABLE
, &sq
->state
);
647 sq
->uar_map
= sq
->uar
.bf_map
;
649 sq
->uar_map
= sq
->uar
.map
;
651 sq
->bf_buf_size
= (1 << MLX5_CAP_GEN(mdev
, log_bf_reg_size
)) / 2;
652 sq
->max_inline
= param
->max_inline
;
653 sq
->min_inline_mode
=
654 MLX5_CAP_ETH(mdev
, wqe_inline_mode
) == MLX5E_INLINE_MODE_VPORT_CONTEXT
?
655 param
->min_inline_mode
: 0;
657 err
= mlx5e_alloc_sq_db(sq
, cpu_to_node(c
->cpu
));
659 goto err_sq_wq_destroy
;
662 u8 wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
664 sq
->ico_wqe_info
= kzalloc_node(sizeof(*sq
->ico_wqe_info
) *
667 cpu_to_node(c
->cpu
));
668 if (!sq
->ico_wqe_info
) {
675 txq_ix
= c
->ix
+ tc
* priv
->params
.num_channels
;
676 sq
->txq
= netdev_get_tx_queue(priv
->netdev
, txq_ix
);
677 priv
->txq_to_sq_map
[txq_ix
] = sq
;
681 sq
->tstamp
= &priv
->tstamp
;
682 sq
->mkey_be
= c
->mkey_be
;
685 sq
->edge
= (sq
->wq
.sz_m1
+ 1) - MLX5_SEND_WQE_MAX_WQEBBS
;
686 sq
->bf_budget
= MLX5E_SQ_BF_BUDGET
;
691 mlx5e_free_sq_db(sq
);
694 mlx5_wq_destroy(&sq
->wq_ctrl
);
697 mlx5_unmap_free_uar(mdev
, &sq
->uar
);
702 static void mlx5e_destroy_sq(struct mlx5e_sq
*sq
)
704 struct mlx5e_channel
*c
= sq
->channel
;
705 struct mlx5e_priv
*priv
= c
->priv
;
707 kfree(sq
->ico_wqe_info
);
708 mlx5e_free_sq_db(sq
);
709 mlx5_wq_destroy(&sq
->wq_ctrl
);
710 mlx5_unmap_free_uar(priv
->mdev
, &sq
->uar
);
713 static int mlx5e_enable_sq(struct mlx5e_sq
*sq
, struct mlx5e_sq_param
*param
)
715 struct mlx5e_channel
*c
= sq
->channel
;
716 struct mlx5e_priv
*priv
= c
->priv
;
717 struct mlx5_core_dev
*mdev
= priv
->mdev
;
725 inlen
= MLX5_ST_SZ_BYTES(create_sq_in
) +
726 sizeof(u64
) * sq
->wq_ctrl
.buf
.npages
;
727 in
= mlx5_vzalloc(inlen
);
731 sqc
= MLX5_ADDR_OF(create_sq_in
, in
, ctx
);
732 wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
734 memcpy(sqc
, param
->sqc
, sizeof(param
->sqc
));
736 MLX5_SET(sqc
, sqc
, tis_num_0
, param
->icosq
? 0 : priv
->tisn
[sq
->tc
]);
737 MLX5_SET(sqc
, sqc
, cqn
, sq
->cq
.mcq
.cqn
);
738 MLX5_SET(sqc
, sqc
, min_wqe_inline_mode
, sq
->min_inline_mode
);
739 MLX5_SET(sqc
, sqc
, state
, MLX5_SQC_STATE_RST
);
740 MLX5_SET(sqc
, sqc
, tis_lst_sz
, param
->icosq
? 0 : 1);
741 MLX5_SET(sqc
, sqc
, flush_in_error_en
, 1);
743 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
744 MLX5_SET(wq
, wq
, uar_page
, sq
->uar
.index
);
745 MLX5_SET(wq
, wq
, log_wq_pg_sz
, sq
->wq_ctrl
.buf
.page_shift
-
746 MLX5_ADAPTER_PAGE_SHIFT
);
747 MLX5_SET64(wq
, wq
, dbr_addr
, sq
->wq_ctrl
.db
.dma
);
749 mlx5_fill_page_array(&sq
->wq_ctrl
.buf
,
750 (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
752 err
= mlx5_core_create_sq(mdev
, in
, inlen
, &sq
->sqn
);
759 static int mlx5e_modify_sq(struct mlx5e_sq
*sq
, int curr_state
,
760 int next_state
, bool update_rl
, int rl_index
)
762 struct mlx5e_channel
*c
= sq
->channel
;
763 struct mlx5e_priv
*priv
= c
->priv
;
764 struct mlx5_core_dev
*mdev
= priv
->mdev
;
771 inlen
= MLX5_ST_SZ_BYTES(modify_sq_in
);
772 in
= mlx5_vzalloc(inlen
);
776 sqc
= MLX5_ADDR_OF(modify_sq_in
, in
, ctx
);
778 MLX5_SET(modify_sq_in
, in
, sq_state
, curr_state
);
779 MLX5_SET(sqc
, sqc
, state
, next_state
);
780 if (update_rl
&& next_state
== MLX5_SQC_STATE_RDY
) {
781 MLX5_SET64(modify_sq_in
, in
, modify_bitmask
, 1);
782 MLX5_SET(sqc
, sqc
, packet_pacing_rate_limit_index
, rl_index
);
785 err
= mlx5_core_modify_sq(mdev
, sq
->sqn
, in
, inlen
);
792 static void mlx5e_disable_sq(struct mlx5e_sq
*sq
)
794 struct mlx5e_channel
*c
= sq
->channel
;
795 struct mlx5e_priv
*priv
= c
->priv
;
796 struct mlx5_core_dev
*mdev
= priv
->mdev
;
798 mlx5_core_destroy_sq(mdev
, sq
->sqn
);
800 mlx5_rl_remove_rate(mdev
, sq
->rate_limit
);
803 static int mlx5e_open_sq(struct mlx5e_channel
*c
,
805 struct mlx5e_sq_param
*param
,
810 err
= mlx5e_create_sq(c
, tc
, param
, sq
);
814 err
= mlx5e_enable_sq(sq
, param
);
818 err
= mlx5e_modify_sq(sq
, MLX5_SQC_STATE_RST
, MLX5_SQC_STATE_RDY
,
824 netdev_tx_reset_queue(sq
->txq
);
825 netif_tx_start_queue(sq
->txq
);
831 mlx5e_disable_sq(sq
);
833 mlx5e_destroy_sq(sq
);
838 static inline void netif_tx_disable_queue(struct netdev_queue
*txq
)
840 __netif_tx_lock_bh(txq
);
841 netif_tx_stop_queue(txq
);
842 __netif_tx_unlock_bh(txq
);
845 static void mlx5e_close_sq(struct mlx5e_sq
*sq
)
847 set_bit(MLX5E_SQ_STATE_FLUSH
, &sq
->state
);
848 /* prevent netif_tx_wake_queue */
849 napi_synchronize(&sq
->channel
->napi
);
852 netif_tx_disable_queue(sq
->txq
);
854 /* last doorbell out, godspeed .. */
855 if (mlx5e_sq_has_room_for(sq
, 1))
856 mlx5e_send_nop(sq
, true);
859 mlx5e_disable_sq(sq
);
860 mlx5e_free_tx_descs(sq
);
861 mlx5e_destroy_sq(sq
);
864 static int mlx5e_create_cq(struct mlx5e_channel
*c
,
865 struct mlx5e_cq_param
*param
,
868 struct mlx5e_priv
*priv
= c
->priv
;
869 struct mlx5_core_dev
*mdev
= priv
->mdev
;
870 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
876 param
->wq
.buf_numa_node
= cpu_to_node(c
->cpu
);
877 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
878 param
->eq_ix
= c
->ix
;
880 err
= mlx5_cqwq_create(mdev
, ¶m
->wq
, param
->cqc
, &cq
->wq
,
885 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn_not_used
, &irqn
);
890 mcq
->set_ci_db
= cq
->wq_ctrl
.db
.db
;
891 mcq
->arm_db
= cq
->wq_ctrl
.db
.db
+ 1;
894 mcq
->vector
= param
->eq_ix
;
895 mcq
->comp
= mlx5e_completion_event
;
896 mcq
->event
= mlx5e_cq_error_event
;
898 mcq
->uar
= &mdev
->mlx5e_res
.cq_uar
;
900 for (i
= 0; i
< mlx5_cqwq_get_size(&cq
->wq
); i
++) {
901 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, i
);
912 static void mlx5e_destroy_cq(struct mlx5e_cq
*cq
)
914 mlx5_wq_destroy(&cq
->wq_ctrl
);
917 static int mlx5e_enable_cq(struct mlx5e_cq
*cq
, struct mlx5e_cq_param
*param
)
919 struct mlx5e_priv
*priv
= cq
->priv
;
920 struct mlx5_core_dev
*mdev
= priv
->mdev
;
921 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
926 unsigned int irqn_not_used
;
930 inlen
= MLX5_ST_SZ_BYTES(create_cq_in
) +
931 sizeof(u64
) * cq
->wq_ctrl
.buf
.npages
;
932 in
= mlx5_vzalloc(inlen
);
936 cqc
= MLX5_ADDR_OF(create_cq_in
, in
, cq_context
);
938 memcpy(cqc
, param
->cqc
, sizeof(param
->cqc
));
940 mlx5_fill_page_array(&cq
->wq_ctrl
.buf
,
941 (__be64
*)MLX5_ADDR_OF(create_cq_in
, in
, pas
));
943 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn
, &irqn_not_used
);
945 MLX5_SET(cqc
, cqc
, cq_period_mode
, param
->cq_period_mode
);
946 MLX5_SET(cqc
, cqc
, c_eqn
, eqn
);
947 MLX5_SET(cqc
, cqc
, uar_page
, mcq
->uar
->index
);
948 MLX5_SET(cqc
, cqc
, log_page_size
, cq
->wq_ctrl
.buf
.page_shift
-
949 MLX5_ADAPTER_PAGE_SHIFT
);
950 MLX5_SET64(cqc
, cqc
, dbr_addr
, cq
->wq_ctrl
.db
.dma
);
952 err
= mlx5_core_create_cq(mdev
, mcq
, in
, inlen
);
964 static void mlx5e_disable_cq(struct mlx5e_cq
*cq
)
966 struct mlx5e_priv
*priv
= cq
->priv
;
967 struct mlx5_core_dev
*mdev
= priv
->mdev
;
969 mlx5_core_destroy_cq(mdev
, &cq
->mcq
);
972 static int mlx5e_open_cq(struct mlx5e_channel
*c
,
973 struct mlx5e_cq_param
*param
,
975 struct mlx5e_cq_moder moderation
)
978 struct mlx5e_priv
*priv
= c
->priv
;
979 struct mlx5_core_dev
*mdev
= priv
->mdev
;
981 err
= mlx5e_create_cq(c
, param
, cq
);
985 err
= mlx5e_enable_cq(cq
, param
);
989 if (MLX5_CAP_GEN(mdev
, cq_moderation
))
990 mlx5_core_modify_cq_moderation(mdev
, &cq
->mcq
,
996 mlx5e_destroy_cq(cq
);
1001 static void mlx5e_close_cq(struct mlx5e_cq
*cq
)
1003 mlx5e_disable_cq(cq
);
1004 mlx5e_destroy_cq(cq
);
1007 static int mlx5e_get_cpu(struct mlx5e_priv
*priv
, int ix
)
1009 return cpumask_first(priv
->mdev
->priv
.irq_info
[ix
].mask
);
1012 static int mlx5e_open_tx_cqs(struct mlx5e_channel
*c
,
1013 struct mlx5e_channel_param
*cparam
)
1015 struct mlx5e_priv
*priv
= c
->priv
;
1019 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
1020 err
= mlx5e_open_cq(c
, &cparam
->tx_cq
, &c
->sq
[tc
].cq
,
1021 priv
->params
.tx_cq_moderation
);
1023 goto err_close_tx_cqs
;
1029 for (tc
--; tc
>= 0; tc
--)
1030 mlx5e_close_cq(&c
->sq
[tc
].cq
);
1035 static void mlx5e_close_tx_cqs(struct mlx5e_channel
*c
)
1039 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1040 mlx5e_close_cq(&c
->sq
[tc
].cq
);
1043 static int mlx5e_open_sqs(struct mlx5e_channel
*c
,
1044 struct mlx5e_channel_param
*cparam
)
1049 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
1050 err
= mlx5e_open_sq(c
, tc
, &cparam
->sq
, &c
->sq
[tc
]);
1058 for (tc
--; tc
>= 0; tc
--)
1059 mlx5e_close_sq(&c
->sq
[tc
]);
1064 static void mlx5e_close_sqs(struct mlx5e_channel
*c
)
1068 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1069 mlx5e_close_sq(&c
->sq
[tc
]);
1072 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv
*priv
, int ix
)
1076 for (i
= 0; i
< priv
->profile
->max_tc
; i
++)
1077 priv
->channeltc_to_txq_map
[ix
][i
] =
1078 ix
+ i
* priv
->params
.num_channels
;
1081 static int mlx5e_set_sq_maxrate(struct net_device
*dev
,
1082 struct mlx5e_sq
*sq
, u32 rate
)
1084 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1085 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1089 if (rate
== sq
->rate_limit
)
1094 /* remove current rl index to free space to next ones */
1095 mlx5_rl_remove_rate(mdev
, sq
->rate_limit
);
1100 err
= mlx5_rl_add_rate(mdev
, rate
, &rl_index
);
1102 netdev_err(dev
, "Failed configuring rate %u: %d\n",
1108 err
= mlx5e_modify_sq(sq
, MLX5_SQC_STATE_RDY
,
1109 MLX5_SQC_STATE_RDY
, true, rl_index
);
1111 netdev_err(dev
, "Failed configuring rate %u: %d\n",
1113 /* remove the rate from the table */
1115 mlx5_rl_remove_rate(mdev
, rate
);
1119 sq
->rate_limit
= rate
;
1123 static int mlx5e_set_tx_maxrate(struct net_device
*dev
, int index
, u32 rate
)
1125 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1126 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1127 struct mlx5e_sq
*sq
= priv
->txq_to_sq_map
[index
];
1130 if (!mlx5_rl_is_supported(mdev
)) {
1131 netdev_err(dev
, "Rate limiting is not supported on this device\n");
1135 /* rate is given in Mb/sec, HW config is in Kb/sec */
1138 /* Check whether rate in valid range, 0 is always valid */
1139 if (rate
&& !mlx5_rl_is_in_range(mdev
, rate
)) {
1140 netdev_err(dev
, "TX rate %u, is not in range\n", rate
);
1144 mutex_lock(&priv
->state_lock
);
1145 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
1146 err
= mlx5e_set_sq_maxrate(dev
, sq
, rate
);
1148 priv
->tx_rates
[index
] = rate
;
1149 mutex_unlock(&priv
->state_lock
);
1154 static int mlx5e_open_channel(struct mlx5e_priv
*priv
, int ix
,
1155 struct mlx5e_channel_param
*cparam
,
1156 struct mlx5e_channel
**cp
)
1158 struct mlx5e_cq_moder icosq_cq_moder
= {0, 0};
1159 struct net_device
*netdev
= priv
->netdev
;
1160 struct mlx5e_cq_moder rx_cq_profile
;
1161 int cpu
= mlx5e_get_cpu(priv
, ix
);
1162 struct mlx5e_channel
*c
;
1163 struct mlx5e_sq
*sq
;
1167 c
= kzalloc_node(sizeof(*c
), GFP_KERNEL
, cpu_to_node(cpu
));
1174 c
->pdev
= &priv
->mdev
->pdev
->dev
;
1175 c
->netdev
= priv
->netdev
;
1176 c
->mkey_be
= cpu_to_be32(priv
->mdev
->mlx5e_res
.mkey
.key
);
1177 c
->num_tc
= priv
->params
.num_tc
;
1179 if (priv
->params
.rx_am_enabled
)
1180 rx_cq_profile
= mlx5e_am_get_def_profile(priv
->params
.rx_cq_period_mode
);
1182 rx_cq_profile
= priv
->params
.rx_cq_moderation
;
1184 mlx5e_build_channeltc_to_txq_map(priv
, ix
);
1186 netif_napi_add(netdev
, &c
->napi
, mlx5e_napi_poll
, 64);
1188 err
= mlx5e_open_cq(c
, &cparam
->icosq_cq
, &c
->icosq
.cq
, icosq_cq_moder
);
1192 err
= mlx5e_open_tx_cqs(c
, cparam
);
1194 goto err_close_icosq_cq
;
1196 err
= mlx5e_open_cq(c
, &cparam
->rx_cq
, &c
->rq
.cq
,
1199 goto err_close_tx_cqs
;
1201 napi_enable(&c
->napi
);
1203 err
= mlx5e_open_sq(c
, 0, &cparam
->icosq
, &c
->icosq
);
1205 goto err_disable_napi
;
1207 err
= mlx5e_open_sqs(c
, cparam
);
1209 goto err_close_icosq
;
1211 for (i
= 0; i
< priv
->params
.num_tc
; i
++) {
1212 u32 txq_ix
= priv
->channeltc_to_txq_map
[ix
][i
];
1214 if (priv
->tx_rates
[txq_ix
]) {
1215 sq
= priv
->txq_to_sq_map
[txq_ix
];
1216 mlx5e_set_sq_maxrate(priv
->netdev
, sq
,
1217 priv
->tx_rates
[txq_ix
]);
1221 err
= mlx5e_open_rq(c
, &cparam
->rq
, &c
->rq
);
1225 netif_set_xps_queue(netdev
, get_cpu_mask(c
->cpu
), ix
);
1234 mlx5e_close_sq(&c
->icosq
);
1237 napi_disable(&c
->napi
);
1238 mlx5e_close_cq(&c
->rq
.cq
);
1241 mlx5e_close_tx_cqs(c
);
1244 mlx5e_close_cq(&c
->icosq
.cq
);
1247 netif_napi_del(&c
->napi
);
1248 napi_hash_del(&c
->napi
);
1254 static void mlx5e_close_channel(struct mlx5e_channel
*c
)
1256 mlx5e_close_rq(&c
->rq
);
1258 mlx5e_close_sq(&c
->icosq
);
1259 napi_disable(&c
->napi
);
1260 mlx5e_close_cq(&c
->rq
.cq
);
1261 mlx5e_close_tx_cqs(c
);
1262 mlx5e_close_cq(&c
->icosq
.cq
);
1263 netif_napi_del(&c
->napi
);
1265 napi_hash_del(&c
->napi
);
1271 static void mlx5e_build_rq_param(struct mlx5e_priv
*priv
,
1272 struct mlx5e_rq_param
*param
)
1274 void *rqc
= param
->rqc
;
1275 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1277 switch (priv
->params
.rq_wq_type
) {
1278 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
1279 MLX5_SET(wq
, wq
, log_wqe_num_of_strides
,
1280 priv
->params
.mpwqe_log_num_strides
- 9);
1281 MLX5_SET(wq
, wq
, log_wqe_stride_size
,
1282 priv
->params
.mpwqe_log_stride_sz
- 6);
1283 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
);
1285 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1286 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1289 MLX5_SET(wq
, wq
, end_padding_mode
, MLX5_WQ_END_PAD_MODE_ALIGN
);
1290 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1291 MLX5_SET(wq
, wq
, log_wq_sz
, priv
->params
.log_rq_size
);
1292 MLX5_SET(wq
, wq
, pd
, priv
->mdev
->mlx5e_res
.pdn
);
1293 MLX5_SET(rqc
, rqc
, counter_set_id
, priv
->q_counter
);
1295 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1296 param
->wq
.linear
= 1;
1298 param
->am_enabled
= priv
->params
.rx_am_enabled
;
1301 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param
*param
)
1303 void *rqc
= param
->rqc
;
1304 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1306 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1307 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1310 static void mlx5e_build_sq_param_common(struct mlx5e_priv
*priv
,
1311 struct mlx5e_sq_param
*param
)
1313 void *sqc
= param
->sqc
;
1314 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1316 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(MLX5_SEND_WQE_BB
));
1317 MLX5_SET(wq
, wq
, pd
, priv
->mdev
->mlx5e_res
.pdn
);
1319 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1322 static void mlx5e_build_sq_param(struct mlx5e_priv
*priv
,
1323 struct mlx5e_sq_param
*param
)
1325 void *sqc
= param
->sqc
;
1326 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1328 mlx5e_build_sq_param_common(priv
, param
);
1329 MLX5_SET(wq
, wq
, log_wq_sz
, priv
->params
.log_sq_size
);
1331 param
->max_inline
= priv
->params
.tx_max_inline
;
1332 param
->min_inline_mode
= priv
->params
.tx_min_inline_mode
;
1335 static void mlx5e_build_common_cq_param(struct mlx5e_priv
*priv
,
1336 struct mlx5e_cq_param
*param
)
1338 void *cqc
= param
->cqc
;
1340 MLX5_SET(cqc
, cqc
, uar_page
, priv
->mdev
->mlx5e_res
.cq_uar
.index
);
1343 static void mlx5e_build_rx_cq_param(struct mlx5e_priv
*priv
,
1344 struct mlx5e_cq_param
*param
)
1346 void *cqc
= param
->cqc
;
1349 switch (priv
->params
.rq_wq_type
) {
1350 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
1351 log_cq_size
= priv
->params
.log_rq_size
+
1352 priv
->params
.mpwqe_log_num_strides
;
1354 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1355 log_cq_size
= priv
->params
.log_rq_size
;
1358 MLX5_SET(cqc
, cqc
, log_cq_size
, log_cq_size
);
1359 if (priv
->params
.rx_cqe_compress
) {
1360 MLX5_SET(cqc
, cqc
, mini_cqe_res_format
, MLX5_CQE_FORMAT_CSUM
);
1361 MLX5_SET(cqc
, cqc
, cqe_comp_en
, 1);
1364 mlx5e_build_common_cq_param(priv
, param
);
1366 param
->cq_period_mode
= priv
->params
.rx_cq_period_mode
;
1369 static void mlx5e_build_tx_cq_param(struct mlx5e_priv
*priv
,
1370 struct mlx5e_cq_param
*param
)
1372 void *cqc
= param
->cqc
;
1374 MLX5_SET(cqc
, cqc
, log_cq_size
, priv
->params
.log_sq_size
);
1376 mlx5e_build_common_cq_param(priv
, param
);
1378 param
->cq_period_mode
= MLX5_CQ_PERIOD_MODE_START_FROM_EQE
;
1381 static void mlx5e_build_ico_cq_param(struct mlx5e_priv
*priv
,
1382 struct mlx5e_cq_param
*param
,
1385 void *cqc
= param
->cqc
;
1387 MLX5_SET(cqc
, cqc
, log_cq_size
, log_wq_size
);
1389 mlx5e_build_common_cq_param(priv
, param
);
1391 param
->cq_period_mode
= MLX5_CQ_PERIOD_MODE_START_FROM_EQE
;
1394 static void mlx5e_build_icosq_param(struct mlx5e_priv
*priv
,
1395 struct mlx5e_sq_param
*param
,
1398 void *sqc
= param
->sqc
;
1399 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1401 mlx5e_build_sq_param_common(priv
, param
);
1403 MLX5_SET(wq
, wq
, log_wq_sz
, log_wq_size
);
1404 MLX5_SET(sqc
, sqc
, reg_umr
, MLX5_CAP_ETH(priv
->mdev
, reg_umr_sq
));
1406 param
->icosq
= true;
1409 static void mlx5e_build_channel_param(struct mlx5e_priv
*priv
, struct mlx5e_channel_param
*cparam
)
1411 u8 icosq_log_wq_sz
= MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE
;
1413 mlx5e_build_rq_param(priv
, &cparam
->rq
);
1414 mlx5e_build_sq_param(priv
, &cparam
->sq
);
1415 mlx5e_build_icosq_param(priv
, &cparam
->icosq
, icosq_log_wq_sz
);
1416 mlx5e_build_rx_cq_param(priv
, &cparam
->rx_cq
);
1417 mlx5e_build_tx_cq_param(priv
, &cparam
->tx_cq
);
1418 mlx5e_build_ico_cq_param(priv
, &cparam
->icosq_cq
, icosq_log_wq_sz
);
1421 static int mlx5e_open_channels(struct mlx5e_priv
*priv
)
1423 struct mlx5e_channel_param
*cparam
;
1424 int nch
= priv
->params
.num_channels
;
1429 priv
->channel
= kcalloc(nch
, sizeof(struct mlx5e_channel
*),
1432 priv
->txq_to_sq_map
= kcalloc(nch
* priv
->params
.num_tc
,
1433 sizeof(struct mlx5e_sq
*), GFP_KERNEL
);
1435 cparam
= kzalloc(sizeof(struct mlx5e_channel_param
), GFP_KERNEL
);
1437 if (!priv
->channel
|| !priv
->txq_to_sq_map
|| !cparam
)
1438 goto err_free_txq_to_sq_map
;
1440 mlx5e_build_channel_param(priv
, cparam
);
1442 for (i
= 0; i
< nch
; i
++) {
1443 err
= mlx5e_open_channel(priv
, i
, cparam
, &priv
->channel
[i
]);
1445 goto err_close_channels
;
1448 for (j
= 0; j
< nch
; j
++) {
1449 err
= mlx5e_wait_for_min_rx_wqes(&priv
->channel
[j
]->rq
);
1451 goto err_close_channels
;
1454 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1455 * polling for inactive tx queues.
1457 netif_tx_start_all_queues(priv
->netdev
);
1463 for (i
--; i
>= 0; i
--)
1464 mlx5e_close_channel(priv
->channel
[i
]);
1466 err_free_txq_to_sq_map
:
1467 kfree(priv
->txq_to_sq_map
);
1468 kfree(priv
->channel
);
1474 static void mlx5e_close_channels(struct mlx5e_priv
*priv
)
1478 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1479 * polling for inactive tx queues.
1481 netif_tx_stop_all_queues(priv
->netdev
);
1482 netif_tx_disable(priv
->netdev
);
1484 for (i
= 0; i
< priv
->params
.num_channels
; i
++)
1485 mlx5e_close_channel(priv
->channel
[i
]);
1487 kfree(priv
->txq_to_sq_map
);
1488 kfree(priv
->channel
);
1491 static int mlx5e_rx_hash_fn(int hfunc
)
1493 return (hfunc
== ETH_RSS_HASH_TOP
) ?
1494 MLX5_RX_HASH_FN_TOEPLITZ
:
1495 MLX5_RX_HASH_FN_INVERTED_XOR8
;
1498 static int mlx5e_bits_invert(unsigned long a
, int size
)
1503 for (i
= 0; i
< size
; i
++)
1504 inv
|= (test_bit(size
- i
- 1, &a
) ? 1 : 0) << i
;
1509 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv
*priv
, void *rqtc
)
1513 for (i
= 0; i
< MLX5E_INDIR_RQT_SIZE
; i
++) {
1517 if (priv
->params
.rss_hfunc
== ETH_RSS_HASH_XOR
)
1518 ix
= mlx5e_bits_invert(i
, MLX5E_LOG_INDIR_RQT_SIZE
);
1520 ix
= priv
->params
.indirection_rqt
[ix
];
1521 rqn
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
) ?
1522 priv
->channel
[ix
]->rq
.rqn
:
1524 MLX5_SET(rqtc
, rqtc
, rq_num
[i
], rqn
);
1528 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv
*priv
, void *rqtc
,
1531 u32 rqn
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
) ?
1532 priv
->channel
[ix
]->rq
.rqn
:
1535 MLX5_SET(rqtc
, rqtc
, rq_num
[0], rqn
);
1538 static int mlx5e_create_rqt(struct mlx5e_priv
*priv
, int sz
,
1539 int ix
, struct mlx5e_rqt
*rqt
)
1541 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1547 inlen
= MLX5_ST_SZ_BYTES(create_rqt_in
) + sizeof(u32
) * sz
;
1548 in
= mlx5_vzalloc(inlen
);
1552 rqtc
= MLX5_ADDR_OF(create_rqt_in
, in
, rqt_context
);
1554 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
1555 MLX5_SET(rqtc
, rqtc
, rqt_max_size
, sz
);
1557 if (sz
> 1) /* RSS */
1558 mlx5e_fill_indir_rqt_rqns(priv
, rqtc
);
1560 mlx5e_fill_direct_rqt_rqn(priv
, rqtc
, ix
);
1562 err
= mlx5_core_create_rqt(mdev
, in
, inlen
, &rqt
->rqtn
);
1564 rqt
->enabled
= true;
1570 void mlx5e_destroy_rqt(struct mlx5e_priv
*priv
, struct mlx5e_rqt
*rqt
)
1572 rqt
->enabled
= false;
1573 mlx5_core_destroy_rqt(priv
->mdev
, rqt
->rqtn
);
1576 static int mlx5e_create_indirect_rqts(struct mlx5e_priv
*priv
)
1578 struct mlx5e_rqt
*rqt
= &priv
->indir_rqt
;
1580 return mlx5e_create_rqt(priv
, MLX5E_INDIR_RQT_SIZE
, 0, rqt
);
1583 int mlx5e_create_direct_rqts(struct mlx5e_priv
*priv
)
1585 struct mlx5e_rqt
*rqt
;
1589 for (ix
= 0; ix
< priv
->profile
->max_nch(priv
->mdev
); ix
++) {
1590 rqt
= &priv
->direct_tir
[ix
].rqt
;
1591 err
= mlx5e_create_rqt(priv
, 1 /*size */, ix
, rqt
);
1593 goto err_destroy_rqts
;
1599 for (ix
--; ix
>= 0; ix
--)
1600 mlx5e_destroy_rqt(priv
, &priv
->direct_tir
[ix
].rqt
);
1605 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, u32 rqtn
, int sz
, int ix
)
1607 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1613 inlen
= MLX5_ST_SZ_BYTES(modify_rqt_in
) + sizeof(u32
) * sz
;
1614 in
= mlx5_vzalloc(inlen
);
1618 rqtc
= MLX5_ADDR_OF(modify_rqt_in
, in
, ctx
);
1620 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
1621 if (sz
> 1) /* RSS */
1622 mlx5e_fill_indir_rqt_rqns(priv
, rqtc
);
1624 mlx5e_fill_direct_rqt_rqn(priv
, rqtc
, ix
);
1626 MLX5_SET(modify_rqt_in
, in
, bitmask
.rqn_list
, 1);
1628 err
= mlx5_core_modify_rqt(mdev
, rqtn
, in
, inlen
);
1635 static void mlx5e_redirect_rqts(struct mlx5e_priv
*priv
)
1640 if (priv
->indir_rqt
.enabled
) {
1641 rqtn
= priv
->indir_rqt
.rqtn
;
1642 mlx5e_redirect_rqt(priv
, rqtn
, MLX5E_INDIR_RQT_SIZE
, 0);
1645 for (ix
= 0; ix
< priv
->params
.num_channels
; ix
++) {
1646 if (!priv
->direct_tir
[ix
].rqt
.enabled
)
1648 rqtn
= priv
->direct_tir
[ix
].rqt
.rqtn
;
1649 mlx5e_redirect_rqt(priv
, rqtn
, 1, ix
);
1653 static void mlx5e_build_tir_ctx_lro(void *tirc
, struct mlx5e_priv
*priv
)
1655 if (!priv
->params
.lro_en
)
1658 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1660 MLX5_SET(tirc
, tirc
, lro_enable_mask
,
1661 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
|
1662 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
);
1663 MLX5_SET(tirc
, tirc
, lro_max_ip_payload_size
,
1664 (priv
->params
.lro_wqe_sz
-
1665 ROUGH_MAX_L2_L3_HDR_SZ
) >> 8);
1666 MLX5_SET(tirc
, tirc
, lro_timeout_period_usecs
,
1667 MLX5_CAP_ETH(priv
->mdev
,
1668 lro_timer_supported_periods
[2]));
1671 void mlx5e_build_tir_ctx_hash(void *tirc
, struct mlx5e_priv
*priv
)
1673 MLX5_SET(tirc
, tirc
, rx_hash_fn
,
1674 mlx5e_rx_hash_fn(priv
->params
.rss_hfunc
));
1675 if (priv
->params
.rss_hfunc
== ETH_RSS_HASH_TOP
) {
1676 void *rss_key
= MLX5_ADDR_OF(tirc
, tirc
,
1677 rx_hash_toeplitz_key
);
1678 size_t len
= MLX5_FLD_SZ_BYTES(tirc
,
1679 rx_hash_toeplitz_key
);
1681 MLX5_SET(tirc
, tirc
, rx_hash_symmetric
, 1);
1682 memcpy(rss_key
, priv
->params
.toeplitz_hash_key
, len
);
1686 static int mlx5e_modify_tirs_lro(struct mlx5e_priv
*priv
)
1688 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1697 inlen
= MLX5_ST_SZ_BYTES(modify_tir_in
);
1698 in
= mlx5_vzalloc(inlen
);
1702 MLX5_SET(modify_tir_in
, in
, bitmask
.lro
, 1);
1703 tirc
= MLX5_ADDR_OF(modify_tir_in
, in
, ctx
);
1705 mlx5e_build_tir_ctx_lro(tirc
, priv
);
1707 for (tt
= 0; tt
< MLX5E_NUM_INDIR_TIRS
; tt
++) {
1708 err
= mlx5_core_modify_tir(mdev
, priv
->indir_tir
[tt
].tirn
, in
,
1714 for (ix
= 0; ix
< priv
->profile
->max_nch(priv
->mdev
); ix
++) {
1715 err
= mlx5_core_modify_tir(mdev
, priv
->direct_tir
[ix
].tirn
,
1727 static int mlx5e_set_mtu(struct mlx5e_priv
*priv
, u16 mtu
)
1729 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1730 u16 hw_mtu
= MLX5E_SW2HW_MTU(mtu
);
1733 err
= mlx5_set_port_mtu(mdev
, hw_mtu
, 1);
1737 /* Update vport context MTU */
1738 mlx5_modify_nic_vport_mtu(mdev
, hw_mtu
);
1742 static void mlx5e_query_mtu(struct mlx5e_priv
*priv
, u16
*mtu
)
1744 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1748 err
= mlx5_query_nic_vport_mtu(mdev
, &hw_mtu
);
1749 if (err
|| !hw_mtu
) /* fallback to port oper mtu */
1750 mlx5_query_port_oper_mtu(mdev
, &hw_mtu
, 1);
1752 *mtu
= MLX5E_HW2SW_MTU(hw_mtu
);
1755 static int mlx5e_set_dev_port_mtu(struct net_device
*netdev
)
1757 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1761 err
= mlx5e_set_mtu(priv
, netdev
->mtu
);
1765 mlx5e_query_mtu(priv
, &mtu
);
1766 if (mtu
!= netdev
->mtu
)
1767 netdev_warn(netdev
, "%s: VPort MTU %d is different than netdev mtu %d\n",
1768 __func__
, mtu
, netdev
->mtu
);
1774 static void mlx5e_netdev_set_tcs(struct net_device
*netdev
)
1776 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1777 int nch
= priv
->params
.num_channels
;
1778 int ntc
= priv
->params
.num_tc
;
1781 netdev_reset_tc(netdev
);
1786 netdev_set_num_tc(netdev
, ntc
);
1788 /* Map netdev TCs to offset 0
1789 * We have our own UP to TXQ mapping for QoS
1791 for (tc
= 0; tc
< ntc
; tc
++)
1792 netdev_set_tc_queue(netdev
, tc
, nch
, 0);
1795 int mlx5e_open_locked(struct net_device
*netdev
)
1797 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1798 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1802 set_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1804 mlx5e_netdev_set_tcs(netdev
);
1806 num_txqs
= priv
->params
.num_channels
* priv
->params
.num_tc
;
1807 netif_set_real_num_tx_queues(netdev
, num_txqs
);
1808 netif_set_real_num_rx_queues(netdev
, priv
->params
.num_channels
);
1810 err
= mlx5e_open_channels(priv
);
1812 netdev_err(netdev
, "%s: mlx5e_open_channels failed, %d\n",
1814 goto err_clear_state_opened_flag
;
1817 err
= mlx5e_refresh_tirs_self_loopback_enable(priv
->mdev
);
1819 netdev_err(netdev
, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1821 goto err_close_channels
;
1824 mlx5e_redirect_rqts(priv
);
1825 mlx5e_update_carrier(priv
);
1826 mlx5e_timestamp_init(priv
);
1827 #ifdef CONFIG_RFS_ACCEL
1828 priv
->netdev
->rx_cpu_rmap
= priv
->mdev
->rmap
;
1830 if (priv
->profile
->update_stats
)
1831 queue_delayed_work(priv
->wq
, &priv
->update_stats_work
, 0);
1833 if (MLX5_CAP_GEN(mdev
, vport_group_manager
)) {
1834 err
= mlx5e_add_sqs_fwd_rules(priv
);
1836 goto err_close_channels
;
1841 mlx5e_close_channels(priv
);
1842 err_clear_state_opened_flag
:
1843 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1847 int mlx5e_open(struct net_device
*netdev
)
1849 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1852 mutex_lock(&priv
->state_lock
);
1853 err
= mlx5e_open_locked(netdev
);
1854 mutex_unlock(&priv
->state_lock
);
1859 int mlx5e_close_locked(struct net_device
*netdev
)
1861 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1862 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1864 /* May already be CLOSED in case a previous configuration operation
1865 * (e.g RX/TX queue size change) that involves close&open failed.
1867 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
1870 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1872 if (MLX5_CAP_GEN(mdev
, vport_group_manager
))
1873 mlx5e_remove_sqs_fwd_rules(priv
);
1875 mlx5e_timestamp_cleanup(priv
);
1876 netif_carrier_off(priv
->netdev
);
1877 mlx5e_redirect_rqts(priv
);
1878 mlx5e_close_channels(priv
);
1883 int mlx5e_close(struct net_device
*netdev
)
1885 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1888 mutex_lock(&priv
->state_lock
);
1889 err
= mlx5e_close_locked(netdev
);
1890 mutex_unlock(&priv
->state_lock
);
1895 static int mlx5e_create_drop_rq(struct mlx5e_priv
*priv
,
1896 struct mlx5e_rq
*rq
,
1897 struct mlx5e_rq_param
*param
)
1899 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1900 void *rqc
= param
->rqc
;
1901 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1904 param
->wq
.db_numa_node
= param
->wq
.buf_numa_node
;
1906 err
= mlx5_wq_ll_create(mdev
, ¶m
->wq
, rqc_wq
, &rq
->wq
,
1916 static int mlx5e_create_drop_cq(struct mlx5e_priv
*priv
,
1917 struct mlx5e_cq
*cq
,
1918 struct mlx5e_cq_param
*param
)
1920 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1921 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
1926 err
= mlx5_cqwq_create(mdev
, ¶m
->wq
, param
->cqc
, &cq
->wq
,
1931 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn_not_used
, &irqn
);
1934 mcq
->set_ci_db
= cq
->wq_ctrl
.db
.db
;
1935 mcq
->arm_db
= cq
->wq_ctrl
.db
.db
+ 1;
1936 *mcq
->set_ci_db
= 0;
1938 mcq
->vector
= param
->eq_ix
;
1939 mcq
->comp
= mlx5e_completion_event
;
1940 mcq
->event
= mlx5e_cq_error_event
;
1942 mcq
->uar
= &mdev
->mlx5e_res
.cq_uar
;
1949 static int mlx5e_open_drop_rq(struct mlx5e_priv
*priv
)
1951 struct mlx5e_cq_param cq_param
;
1952 struct mlx5e_rq_param rq_param
;
1953 struct mlx5e_rq
*rq
= &priv
->drop_rq
;
1954 struct mlx5e_cq
*cq
= &priv
->drop_rq
.cq
;
1957 memset(&cq_param
, 0, sizeof(cq_param
));
1958 memset(&rq_param
, 0, sizeof(rq_param
));
1959 mlx5e_build_drop_rq_param(&rq_param
);
1961 err
= mlx5e_create_drop_cq(priv
, cq
, &cq_param
);
1965 err
= mlx5e_enable_cq(cq
, &cq_param
);
1967 goto err_destroy_cq
;
1969 err
= mlx5e_create_drop_rq(priv
, rq
, &rq_param
);
1971 goto err_disable_cq
;
1973 err
= mlx5e_enable_rq(rq
, &rq_param
);
1975 goto err_destroy_rq
;
1980 mlx5e_destroy_rq(&priv
->drop_rq
);
1983 mlx5e_disable_cq(&priv
->drop_rq
.cq
);
1986 mlx5e_destroy_cq(&priv
->drop_rq
.cq
);
1991 static void mlx5e_close_drop_rq(struct mlx5e_priv
*priv
)
1993 mlx5e_disable_rq(&priv
->drop_rq
);
1994 mlx5e_destroy_rq(&priv
->drop_rq
);
1995 mlx5e_disable_cq(&priv
->drop_rq
.cq
);
1996 mlx5e_destroy_cq(&priv
->drop_rq
.cq
);
1999 static int mlx5e_create_tis(struct mlx5e_priv
*priv
, int tc
)
2001 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2002 u32 in
[MLX5_ST_SZ_DW(create_tis_in
)];
2003 void *tisc
= MLX5_ADDR_OF(create_tis_in
, in
, ctx
);
2005 memset(in
, 0, sizeof(in
));
2007 MLX5_SET(tisc
, tisc
, prio
, tc
<< 1);
2008 MLX5_SET(tisc
, tisc
, transport_domain
, mdev
->mlx5e_res
.td
.tdn
);
2010 return mlx5_core_create_tis(mdev
, in
, sizeof(in
), &priv
->tisn
[tc
]);
2013 static void mlx5e_destroy_tis(struct mlx5e_priv
*priv
, int tc
)
2015 mlx5_core_destroy_tis(priv
->mdev
, priv
->tisn
[tc
]);
2018 int mlx5e_create_tises(struct mlx5e_priv
*priv
)
2023 for (tc
= 0; tc
< priv
->profile
->max_tc
; tc
++) {
2024 err
= mlx5e_create_tis(priv
, tc
);
2026 goto err_close_tises
;
2032 for (tc
--; tc
>= 0; tc
--)
2033 mlx5e_destroy_tis(priv
, tc
);
2038 void mlx5e_cleanup_nic_tx(struct mlx5e_priv
*priv
)
2042 for (tc
= 0; tc
< priv
->profile
->max_tc
; tc
++)
2043 mlx5e_destroy_tis(priv
, tc
);
2046 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv
*priv
, u32
*tirc
,
2047 enum mlx5e_traffic_types tt
)
2049 void *hfso
= MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_outer
);
2051 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->mdev
->mlx5e_res
.td
.tdn
);
2053 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2054 MLX5_HASH_FIELD_SEL_DST_IP)
2056 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2057 MLX5_HASH_FIELD_SEL_DST_IP |\
2058 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2059 MLX5_HASH_FIELD_SEL_L4_DPORT)
2061 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2062 MLX5_HASH_FIELD_SEL_DST_IP |\
2063 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2065 mlx5e_build_tir_ctx_lro(tirc
, priv
);
2067 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
2068 MLX5_SET(tirc
, tirc
, indirect_table
, priv
->indir_rqt
.rqtn
);
2069 mlx5e_build_tir_ctx_hash(tirc
, priv
);
2072 case MLX5E_TT_IPV4_TCP
:
2073 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2074 MLX5_L3_PROT_TYPE_IPV4
);
2075 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2076 MLX5_L4_PROT_TYPE_TCP
);
2077 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2078 MLX5_HASH_IP_L4PORTS
);
2081 case MLX5E_TT_IPV6_TCP
:
2082 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2083 MLX5_L3_PROT_TYPE_IPV6
);
2084 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2085 MLX5_L4_PROT_TYPE_TCP
);
2086 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2087 MLX5_HASH_IP_L4PORTS
);
2090 case MLX5E_TT_IPV4_UDP
:
2091 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2092 MLX5_L3_PROT_TYPE_IPV4
);
2093 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2094 MLX5_L4_PROT_TYPE_UDP
);
2095 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2096 MLX5_HASH_IP_L4PORTS
);
2099 case MLX5E_TT_IPV6_UDP
:
2100 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2101 MLX5_L3_PROT_TYPE_IPV6
);
2102 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2103 MLX5_L4_PROT_TYPE_UDP
);
2104 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2105 MLX5_HASH_IP_L4PORTS
);
2108 case MLX5E_TT_IPV4_IPSEC_AH
:
2109 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2110 MLX5_L3_PROT_TYPE_IPV4
);
2111 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2112 MLX5_HASH_IP_IPSEC_SPI
);
2115 case MLX5E_TT_IPV6_IPSEC_AH
:
2116 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2117 MLX5_L3_PROT_TYPE_IPV6
);
2118 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2119 MLX5_HASH_IP_IPSEC_SPI
);
2122 case MLX5E_TT_IPV4_IPSEC_ESP
:
2123 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2124 MLX5_L3_PROT_TYPE_IPV4
);
2125 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2126 MLX5_HASH_IP_IPSEC_SPI
);
2129 case MLX5E_TT_IPV6_IPSEC_ESP
:
2130 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2131 MLX5_L3_PROT_TYPE_IPV6
);
2132 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2133 MLX5_HASH_IP_IPSEC_SPI
);
2137 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2138 MLX5_L3_PROT_TYPE_IPV4
);
2139 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2144 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2145 MLX5_L3_PROT_TYPE_IPV6
);
2146 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2151 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2155 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv
*priv
, u32
*tirc
,
2158 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->mdev
->mlx5e_res
.td
.tdn
);
2160 mlx5e_build_tir_ctx_lro(tirc
, priv
);
2162 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
2163 MLX5_SET(tirc
, tirc
, indirect_table
, rqtn
);
2164 MLX5_SET(tirc
, tirc
, rx_hash_fn
, MLX5_RX_HASH_FN_INVERTED_XOR8
);
2167 static int mlx5e_create_indirect_tirs(struct mlx5e_priv
*priv
)
2169 struct mlx5e_tir
*tir
;
2176 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
2177 in
= mlx5_vzalloc(inlen
);
2181 for (tt
= 0; tt
< MLX5E_NUM_INDIR_TIRS
; tt
++) {
2182 memset(in
, 0, inlen
);
2183 tir
= &priv
->indir_tir
[tt
];
2184 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
2185 mlx5e_build_indir_tir_ctx(priv
, tirc
, tt
);
2186 err
= mlx5e_create_tir(priv
->mdev
, tir
, in
, inlen
);
2188 goto err_destroy_tirs
;
2196 for (tt
--; tt
>= 0; tt
--)
2197 mlx5e_destroy_tir(priv
->mdev
, &priv
->indir_tir
[tt
]);
2204 int mlx5e_create_direct_tirs(struct mlx5e_priv
*priv
)
2206 int nch
= priv
->profile
->max_nch(priv
->mdev
);
2207 struct mlx5e_tir
*tir
;
2214 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
2215 in
= mlx5_vzalloc(inlen
);
2219 for (ix
= 0; ix
< nch
; ix
++) {
2220 memset(in
, 0, inlen
);
2221 tir
= &priv
->direct_tir
[ix
];
2222 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
2223 mlx5e_build_direct_tir_ctx(priv
, tirc
,
2224 priv
->direct_tir
[ix
].rqt
.rqtn
);
2225 err
= mlx5e_create_tir(priv
->mdev
, tir
, in
, inlen
);
2227 goto err_destroy_ch_tirs
;
2234 err_destroy_ch_tirs
:
2235 for (ix
--; ix
>= 0; ix
--)
2236 mlx5e_destroy_tir(priv
->mdev
, &priv
->direct_tir
[ix
]);
2243 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv
*priv
)
2247 for (i
= 0; i
< MLX5E_NUM_INDIR_TIRS
; i
++)
2248 mlx5e_destroy_tir(priv
->mdev
, &priv
->indir_tir
[i
]);
2251 void mlx5e_destroy_direct_tirs(struct mlx5e_priv
*priv
)
2253 int nch
= priv
->profile
->max_nch(priv
->mdev
);
2256 for (i
= 0; i
< nch
; i
++)
2257 mlx5e_destroy_tir(priv
->mdev
, &priv
->direct_tir
[i
]);
2260 int mlx5e_modify_rqs_vsd(struct mlx5e_priv
*priv
, bool vsd
)
2265 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
2268 for (i
= 0; i
< priv
->params
.num_channels
; i
++) {
2269 err
= mlx5e_modify_rq_vsd(&priv
->channel
[i
]->rq
, vsd
);
2277 static int mlx5e_setup_tc(struct net_device
*netdev
, u8 tc
)
2279 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2283 if (tc
&& tc
!= MLX5E_MAX_NUM_TC
)
2286 mutex_lock(&priv
->state_lock
);
2288 was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2290 mlx5e_close_locked(priv
->netdev
);
2292 priv
->params
.num_tc
= tc
? tc
: 1;
2295 err
= mlx5e_open_locked(priv
->netdev
);
2297 mutex_unlock(&priv
->state_lock
);
2302 static int mlx5e_ndo_setup_tc(struct net_device
*dev
, u32 handle
,
2303 __be16 proto
, struct tc_to_netdev
*tc
)
2305 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2307 if (TC_H_MAJ(handle
) != TC_H_MAJ(TC_H_INGRESS
))
2311 case TC_SETUP_CLSFLOWER
:
2312 switch (tc
->cls_flower
->command
) {
2313 case TC_CLSFLOWER_REPLACE
:
2314 return mlx5e_configure_flower(priv
, proto
, tc
->cls_flower
);
2315 case TC_CLSFLOWER_DESTROY
:
2316 return mlx5e_delete_flower(priv
, tc
->cls_flower
);
2317 case TC_CLSFLOWER_STATS
:
2318 return mlx5e_stats_flower(priv
, tc
->cls_flower
);
2325 if (tc
->type
!= TC_SETUP_MQPRIO
)
2328 return mlx5e_setup_tc(dev
, tc
->tc
);
2331 struct rtnl_link_stats64
*
2332 mlx5e_get_stats(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
2334 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2335 struct mlx5e_sw_stats
*sstats
= &priv
->stats
.sw
;
2336 struct mlx5e_vport_stats
*vstats
= &priv
->stats
.vport
;
2337 struct mlx5e_pport_stats
*pstats
= &priv
->stats
.pport
;
2339 stats
->rx_packets
= sstats
->rx_packets
;
2340 stats
->rx_bytes
= sstats
->rx_bytes
;
2341 stats
->tx_packets
= sstats
->tx_packets
;
2342 stats
->tx_bytes
= sstats
->tx_bytes
;
2344 stats
->rx_dropped
= priv
->stats
.qcnt
.rx_out_of_buffer
;
2345 stats
->tx_dropped
= sstats
->tx_queue_dropped
;
2347 stats
->rx_length_errors
=
2348 PPORT_802_3_GET(pstats
, a_in_range_length_errors
) +
2349 PPORT_802_3_GET(pstats
, a_out_of_range_length_field
) +
2350 PPORT_802_3_GET(pstats
, a_frame_too_long_errors
);
2351 stats
->rx_crc_errors
=
2352 PPORT_802_3_GET(pstats
, a_frame_check_sequence_errors
);
2353 stats
->rx_frame_errors
= PPORT_802_3_GET(pstats
, a_alignment_errors
);
2354 stats
->tx_aborted_errors
= PPORT_2863_GET(pstats
, if_out_discards
);
2355 stats
->tx_carrier_errors
=
2356 PPORT_802_3_GET(pstats
, a_symbol_error_during_carrier
);
2357 stats
->rx_errors
= stats
->rx_length_errors
+ stats
->rx_crc_errors
+
2358 stats
->rx_frame_errors
;
2359 stats
->tx_errors
= stats
->tx_aborted_errors
+ stats
->tx_carrier_errors
;
2361 /* vport multicast also counts packets that are dropped due to steering
2362 * or rx out of buffer
2365 VPORT_COUNTER_GET(vstats
, received_eth_multicast
.packets
);
2370 static void mlx5e_set_rx_mode(struct net_device
*dev
)
2372 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2374 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
2377 static int mlx5e_set_mac(struct net_device
*netdev
, void *addr
)
2379 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2380 struct sockaddr
*saddr
= addr
;
2382 if (!is_valid_ether_addr(saddr
->sa_data
))
2383 return -EADDRNOTAVAIL
;
2385 netif_addr_lock_bh(netdev
);
2386 ether_addr_copy(netdev
->dev_addr
, saddr
->sa_data
);
2387 netif_addr_unlock_bh(netdev
);
2389 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
2394 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2397 netdev->features |= feature; \
2399 netdev->features &= ~feature; \
2402 typedef int (*mlx5e_feature_handler
)(struct net_device
*netdev
, bool enable
);
2404 static int set_feature_lro(struct net_device
*netdev
, bool enable
)
2406 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2407 bool was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2410 mutex_lock(&priv
->state_lock
);
2412 if (was_opened
&& (priv
->params
.rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST
))
2413 mlx5e_close_locked(priv
->netdev
);
2415 priv
->params
.lro_en
= enable
;
2416 err
= mlx5e_modify_tirs_lro(priv
);
2418 netdev_err(netdev
, "lro modify failed, %d\n", err
);
2419 priv
->params
.lro_en
= !enable
;
2422 if (was_opened
&& (priv
->params
.rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST
))
2423 mlx5e_open_locked(priv
->netdev
);
2425 mutex_unlock(&priv
->state_lock
);
2430 static int set_feature_vlan_filter(struct net_device
*netdev
, bool enable
)
2432 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2435 mlx5e_enable_vlan_filter(priv
);
2437 mlx5e_disable_vlan_filter(priv
);
2442 static int set_feature_tc_num_filters(struct net_device
*netdev
, bool enable
)
2444 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2446 if (!enable
&& mlx5e_tc_num_filters(priv
)) {
2448 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2455 static int set_feature_rx_all(struct net_device
*netdev
, bool enable
)
2457 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2458 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2460 return mlx5_set_port_fcs(mdev
, !enable
);
2463 static int set_feature_rx_vlan(struct net_device
*netdev
, bool enable
)
2465 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2468 mutex_lock(&priv
->state_lock
);
2470 priv
->params
.vlan_strip_disable
= !enable
;
2471 err
= mlx5e_modify_rqs_vsd(priv
, !enable
);
2473 priv
->params
.vlan_strip_disable
= enable
;
2475 mutex_unlock(&priv
->state_lock
);
2480 #ifdef CONFIG_RFS_ACCEL
2481 static int set_feature_arfs(struct net_device
*netdev
, bool enable
)
2483 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2487 err
= mlx5e_arfs_enable(priv
);
2489 err
= mlx5e_arfs_disable(priv
);
2495 static int mlx5e_handle_feature(struct net_device
*netdev
,
2496 netdev_features_t wanted_features
,
2497 netdev_features_t feature
,
2498 mlx5e_feature_handler feature_handler
)
2500 netdev_features_t changes
= wanted_features
^ netdev
->features
;
2501 bool enable
= !!(wanted_features
& feature
);
2504 if (!(changes
& feature
))
2507 err
= feature_handler(netdev
, enable
);
2509 netdev_err(netdev
, "%s feature 0x%llx failed err %d\n",
2510 enable
? "Enable" : "Disable", feature
, err
);
2514 MLX5E_SET_FEATURE(netdev
, feature
, enable
);
2518 static int mlx5e_set_features(struct net_device
*netdev
,
2519 netdev_features_t features
)
2523 err
= mlx5e_handle_feature(netdev
, features
, NETIF_F_LRO
,
2525 err
|= mlx5e_handle_feature(netdev
, features
,
2526 NETIF_F_HW_VLAN_CTAG_FILTER
,
2527 set_feature_vlan_filter
);
2528 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_HW_TC
,
2529 set_feature_tc_num_filters
);
2530 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_RXALL
,
2531 set_feature_rx_all
);
2532 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_HW_VLAN_CTAG_RX
,
2533 set_feature_rx_vlan
);
2534 #ifdef CONFIG_RFS_ACCEL
2535 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_NTUPLE
,
2539 return err
? -EINVAL
: 0;
2542 #define MXL5_HW_MIN_MTU 64
2543 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2545 static int mlx5e_change_mtu(struct net_device
*netdev
, int new_mtu
)
2547 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2548 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2555 mlx5_query_port_max_mtu(mdev
, &max_mtu
, 1);
2557 max_mtu
= MLX5E_HW2SW_MTU(max_mtu
);
2558 min_mtu
= MLX5E_HW2SW_MTU(MXL5E_MIN_MTU
);
2560 if (new_mtu
> max_mtu
|| new_mtu
< min_mtu
) {
2562 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2563 __func__
, new_mtu
, min_mtu
, max_mtu
);
2567 mutex_lock(&priv
->state_lock
);
2569 reset
= !priv
->params
.lro_en
&&
2570 (priv
->params
.rq_wq_type
!=
2571 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
);
2573 was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2574 if (was_opened
&& reset
)
2575 mlx5e_close_locked(netdev
);
2577 netdev
->mtu
= new_mtu
;
2578 mlx5e_set_dev_port_mtu(netdev
);
2580 if (was_opened
&& reset
)
2581 err
= mlx5e_open_locked(netdev
);
2583 mutex_unlock(&priv
->state_lock
);
2588 static int mlx5e_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2592 return mlx5e_hwstamp_set(dev
, ifr
);
2594 return mlx5e_hwstamp_get(dev
, ifr
);
2600 static int mlx5e_set_vf_mac(struct net_device
*dev
, int vf
, u8
*mac
)
2602 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2603 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2605 return mlx5_eswitch_set_vport_mac(mdev
->priv
.eswitch
, vf
+ 1, mac
);
2608 static int mlx5e_set_vf_vlan(struct net_device
*dev
, int vf
, u16 vlan
, u8 qos
)
2610 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2611 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2613 return mlx5_eswitch_set_vport_vlan(mdev
->priv
.eswitch
, vf
+ 1,
2617 static int mlx5e_set_vf_spoofchk(struct net_device
*dev
, int vf
, bool setting
)
2619 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2620 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2622 return mlx5_eswitch_set_vport_spoofchk(mdev
->priv
.eswitch
, vf
+ 1, setting
);
2625 static int mlx5e_set_vf_trust(struct net_device
*dev
, int vf
, bool setting
)
2627 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2628 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2630 return mlx5_eswitch_set_vport_trust(mdev
->priv
.eswitch
, vf
+ 1, setting
);
2632 static int mlx5_vport_link2ifla(u8 esw_link
)
2635 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN
:
2636 return IFLA_VF_LINK_STATE_DISABLE
;
2637 case MLX5_ESW_VPORT_ADMIN_STATE_UP
:
2638 return IFLA_VF_LINK_STATE_ENABLE
;
2640 return IFLA_VF_LINK_STATE_AUTO
;
2643 static int mlx5_ifla_link2vport(u8 ifla_link
)
2645 switch (ifla_link
) {
2646 case IFLA_VF_LINK_STATE_DISABLE
:
2647 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN
;
2648 case IFLA_VF_LINK_STATE_ENABLE
:
2649 return MLX5_ESW_VPORT_ADMIN_STATE_UP
;
2651 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO
;
2654 static int mlx5e_set_vf_link_state(struct net_device
*dev
, int vf
,
2657 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2658 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2660 return mlx5_eswitch_set_vport_state(mdev
->priv
.eswitch
, vf
+ 1,
2661 mlx5_ifla_link2vport(link_state
));
2664 static int mlx5e_get_vf_config(struct net_device
*dev
,
2665 int vf
, struct ifla_vf_info
*ivi
)
2667 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2668 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2671 err
= mlx5_eswitch_get_vport_config(mdev
->priv
.eswitch
, vf
+ 1, ivi
);
2674 ivi
->linkstate
= mlx5_vport_link2ifla(ivi
->linkstate
);
2678 static int mlx5e_get_vf_stats(struct net_device
*dev
,
2679 int vf
, struct ifla_vf_stats
*vf_stats
)
2681 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2682 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2684 return mlx5_eswitch_get_vport_stats(mdev
->priv
.eswitch
, vf
+ 1,
2688 static void mlx5e_add_vxlan_port(struct net_device
*netdev
,
2689 struct udp_tunnel_info
*ti
)
2691 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2693 if (ti
->type
!= UDP_TUNNEL_TYPE_VXLAN
)
2696 if (!mlx5e_vxlan_allowed(priv
->mdev
))
2699 mlx5e_vxlan_queue_work(priv
, ti
->sa_family
, be16_to_cpu(ti
->port
), 1);
2702 static void mlx5e_del_vxlan_port(struct net_device
*netdev
,
2703 struct udp_tunnel_info
*ti
)
2705 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2707 if (ti
->type
!= UDP_TUNNEL_TYPE_VXLAN
)
2710 if (!mlx5e_vxlan_allowed(priv
->mdev
))
2713 mlx5e_vxlan_queue_work(priv
, ti
->sa_family
, be16_to_cpu(ti
->port
), 0);
2716 static netdev_features_t
mlx5e_vxlan_features_check(struct mlx5e_priv
*priv
,
2717 struct sk_buff
*skb
,
2718 netdev_features_t features
)
2720 struct udphdr
*udph
;
2724 switch (vlan_get_protocol(skb
)) {
2725 case htons(ETH_P_IP
):
2726 proto
= ip_hdr(skb
)->protocol
;
2728 case htons(ETH_P_IPV6
):
2729 proto
= ipv6_hdr(skb
)->nexthdr
;
2735 if (proto
== IPPROTO_UDP
) {
2736 udph
= udp_hdr(skb
);
2737 port
= be16_to_cpu(udph
->dest
);
2740 /* Verify if UDP port is being offloaded by HW */
2741 if (port
&& mlx5e_vxlan_lookup_port(priv
, port
))
2745 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2746 return features
& ~(NETIF_F_CSUM_MASK
| NETIF_F_GSO_MASK
);
2749 static netdev_features_t
mlx5e_features_check(struct sk_buff
*skb
,
2750 struct net_device
*netdev
,
2751 netdev_features_t features
)
2753 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2755 features
= vlan_features_check(skb
, features
);
2756 features
= vxlan_features_check(skb
, features
);
2758 /* Validate if the tunneled packet is being offloaded by HW */
2759 if (skb
->encapsulation
&&
2760 (features
& NETIF_F_CSUM_MASK
|| features
& NETIF_F_GSO_MASK
))
2761 return mlx5e_vxlan_features_check(priv
, skb
, features
);
2766 static void mlx5e_tx_timeout(struct net_device
*dev
)
2768 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2769 bool sched_work
= false;
2772 netdev_err(dev
, "TX timeout detected\n");
2774 for (i
= 0; i
< priv
->params
.num_channels
* priv
->params
.num_tc
; i
++) {
2775 struct mlx5e_sq
*sq
= priv
->txq_to_sq_map
[i
];
2777 if (!netif_xmit_stopped(netdev_get_tx_queue(dev
, i
)))
2780 set_bit(MLX5E_SQ_STATE_FLUSH
, &sq
->state
);
2781 netdev_err(dev
, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2782 i
, sq
->sqn
, sq
->cq
.mcq
.cqn
, sq
->cc
, sq
->pc
);
2785 if (sched_work
&& test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
2786 schedule_work(&priv
->tx_timeout_work
);
2789 static const struct net_device_ops mlx5e_netdev_ops_basic
= {
2790 .ndo_open
= mlx5e_open
,
2791 .ndo_stop
= mlx5e_close
,
2792 .ndo_start_xmit
= mlx5e_xmit
,
2793 .ndo_setup_tc
= mlx5e_ndo_setup_tc
,
2794 .ndo_select_queue
= mlx5e_select_queue
,
2795 .ndo_get_stats64
= mlx5e_get_stats
,
2796 .ndo_set_rx_mode
= mlx5e_set_rx_mode
,
2797 .ndo_set_mac_address
= mlx5e_set_mac
,
2798 .ndo_vlan_rx_add_vid
= mlx5e_vlan_rx_add_vid
,
2799 .ndo_vlan_rx_kill_vid
= mlx5e_vlan_rx_kill_vid
,
2800 .ndo_set_features
= mlx5e_set_features
,
2801 .ndo_change_mtu
= mlx5e_change_mtu
,
2802 .ndo_do_ioctl
= mlx5e_ioctl
,
2803 .ndo_set_tx_maxrate
= mlx5e_set_tx_maxrate
,
2804 #ifdef CONFIG_RFS_ACCEL
2805 .ndo_rx_flow_steer
= mlx5e_rx_flow_steer
,
2807 .ndo_tx_timeout
= mlx5e_tx_timeout
,
2810 static const struct net_device_ops mlx5e_netdev_ops_sriov
= {
2811 .ndo_open
= mlx5e_open
,
2812 .ndo_stop
= mlx5e_close
,
2813 .ndo_start_xmit
= mlx5e_xmit
,
2814 .ndo_setup_tc
= mlx5e_ndo_setup_tc
,
2815 .ndo_select_queue
= mlx5e_select_queue
,
2816 .ndo_get_stats64
= mlx5e_get_stats
,
2817 .ndo_set_rx_mode
= mlx5e_set_rx_mode
,
2818 .ndo_set_mac_address
= mlx5e_set_mac
,
2819 .ndo_vlan_rx_add_vid
= mlx5e_vlan_rx_add_vid
,
2820 .ndo_vlan_rx_kill_vid
= mlx5e_vlan_rx_kill_vid
,
2821 .ndo_set_features
= mlx5e_set_features
,
2822 .ndo_change_mtu
= mlx5e_change_mtu
,
2823 .ndo_do_ioctl
= mlx5e_ioctl
,
2824 .ndo_udp_tunnel_add
= mlx5e_add_vxlan_port
,
2825 .ndo_udp_tunnel_del
= mlx5e_del_vxlan_port
,
2826 .ndo_set_tx_maxrate
= mlx5e_set_tx_maxrate
,
2827 .ndo_features_check
= mlx5e_features_check
,
2828 #ifdef CONFIG_RFS_ACCEL
2829 .ndo_rx_flow_steer
= mlx5e_rx_flow_steer
,
2831 .ndo_set_vf_mac
= mlx5e_set_vf_mac
,
2832 .ndo_set_vf_vlan
= mlx5e_set_vf_vlan
,
2833 .ndo_set_vf_spoofchk
= mlx5e_set_vf_spoofchk
,
2834 .ndo_set_vf_trust
= mlx5e_set_vf_trust
,
2835 .ndo_get_vf_config
= mlx5e_get_vf_config
,
2836 .ndo_set_vf_link_state
= mlx5e_set_vf_link_state
,
2837 .ndo_get_vf_stats
= mlx5e_get_vf_stats
,
2838 .ndo_tx_timeout
= mlx5e_tx_timeout
,
2841 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev
*mdev
)
2843 if (MLX5_CAP_GEN(mdev
, port_type
) != MLX5_CAP_PORT_TYPE_ETH
)
2845 if (!MLX5_CAP_GEN(mdev
, eth_net_offloads
) ||
2846 !MLX5_CAP_GEN(mdev
, nic_flow_table
) ||
2847 !MLX5_CAP_ETH(mdev
, csum_cap
) ||
2848 !MLX5_CAP_ETH(mdev
, max_lso_cap
) ||
2849 !MLX5_CAP_ETH(mdev
, vlan_cap
) ||
2850 !MLX5_CAP_ETH(mdev
, rss_ind_tbl_cap
) ||
2851 MLX5_CAP_FLOWTABLE(mdev
,
2852 flow_table_properties_nic_receive
.max_ft_level
)
2854 mlx5_core_warn(mdev
,
2855 "Not creating net device, some required device capabilities are missing\n");
2858 if (!MLX5_CAP_ETH(mdev
, self_lb_en_modifiable
))
2859 mlx5_core_warn(mdev
, "Self loop back prevention is not supported\n");
2860 if (!MLX5_CAP_GEN(mdev
, cq_moderation
))
2861 mlx5_core_warn(mdev
, "CQ modiration is not supported\n");
2866 u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev
*mdev
)
2868 int bf_buf_size
= (1 << MLX5_CAP_GEN(mdev
, log_bf_reg_size
)) / 2;
2870 return bf_buf_size
-
2871 sizeof(struct mlx5e_tx_wqe
) +
2872 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2875 #ifdef CONFIG_MLX5_CORE_EN_DCB
2876 static void mlx5e_ets_init(struct mlx5e_priv
*priv
)
2880 priv
->params
.ets
.ets_cap
= mlx5_max_tc(priv
->mdev
) + 1;
2881 for (i
= 0; i
< priv
->params
.ets
.ets_cap
; i
++) {
2882 priv
->params
.ets
.tc_tx_bw
[i
] = MLX5E_MAX_BW_ALLOC
;
2883 priv
->params
.ets
.tc_tsa
[i
] = IEEE_8021QAZ_TSA_VENDOR
;
2884 priv
->params
.ets
.prio_tc
[i
] = i
;
2887 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2888 priv
->params
.ets
.prio_tc
[0] = 1;
2889 priv
->params
.ets
.prio_tc
[1] = 0;
2893 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev
*mdev
,
2894 u32
*indirection_rqt
, int len
,
2897 int node
= mdev
->priv
.numa_node
;
2898 int node_num_of_cores
;
2902 node
= first_online_node
;
2904 node_num_of_cores
= cpumask_weight(cpumask_of_node(node
));
2906 if (node_num_of_cores
)
2907 num_channels
= min_t(int, num_channels
, node_num_of_cores
);
2909 for (i
= 0; i
< len
; i
++)
2910 indirection_rqt
[i
] = i
% num_channels
;
2913 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev
*mdev
)
2915 return MLX5_CAP_GEN(mdev
, striding_rq
) &&
2916 MLX5_CAP_GEN(mdev
, umr_ptr_rlky
) &&
2917 MLX5_CAP_ETH(mdev
, reg_umr_sq
);
2920 static int mlx5e_get_pci_bw(struct mlx5_core_dev
*mdev
, u32
*pci_bw
)
2922 enum pcie_link_width width
;
2923 enum pci_bus_speed speed
;
2926 err
= pcie_get_minimum_link(mdev
->pdev
, &speed
, &width
);
2930 if (speed
== PCI_SPEED_UNKNOWN
|| width
== PCIE_LNK_WIDTH_UNKNOWN
)
2934 case PCIE_SPEED_2_5GT
:
2935 *pci_bw
= 2500 * width
;
2937 case PCIE_SPEED_5_0GT
:
2938 *pci_bw
= 5000 * width
;
2940 case PCIE_SPEED_8_0GT
:
2941 *pci_bw
= 8000 * width
;
2950 static bool cqe_compress_heuristic(u32 link_speed
, u32 pci_bw
)
2952 return (link_speed
&& pci_bw
&&
2953 (pci_bw
< 40000) && (pci_bw
< link_speed
));
2956 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params
*params
, u8 cq_period_mode
)
2958 params
->rx_cq_period_mode
= cq_period_mode
;
2960 params
->rx_cq_moderation
.pkts
=
2961 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS
;
2962 params
->rx_cq_moderation
.usec
=
2963 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC
;
2965 if (cq_period_mode
== MLX5_CQ_PERIOD_MODE_START_FROM_CQE
)
2966 params
->rx_cq_moderation
.usec
=
2967 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE
;
2970 static void mlx5e_query_min_inline(struct mlx5_core_dev
*mdev
,
2971 u8
*min_inline_mode
)
2973 switch (MLX5_CAP_ETH(mdev
, wqe_inline_mode
)) {
2974 case MLX5E_INLINE_MODE_L2
:
2975 *min_inline_mode
= MLX5_INLINE_MODE_L2
;
2977 case MLX5E_INLINE_MODE_VPORT_CONTEXT
:
2978 mlx5_query_nic_vport_min_inline(mdev
,
2981 case MLX5_INLINE_MODE_NOT_REQUIRED
:
2982 *min_inline_mode
= MLX5_INLINE_MODE_NONE
;
2987 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev
*mdev
,
2988 struct net_device
*netdev
,
2989 const struct mlx5e_profile
*profile
,
2992 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2995 u8 cq_period_mode
= MLX5_CAP_GEN(mdev
, cq_period_start_from_cqe
) ?
2996 MLX5_CQ_PERIOD_MODE_START_FROM_CQE
:
2997 MLX5_CQ_PERIOD_MODE_START_FROM_EQE
;
2999 priv
->params
.log_sq_size
=
3000 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE
;
3001 priv
->params
.rq_wq_type
= mlx5e_check_fragmented_striding_rq_cap(mdev
) ?
3002 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
3003 MLX5_WQ_TYPE_LINKED_LIST
;
3005 /* set CQE compression */
3006 priv
->params
.rx_cqe_compress_admin
= false;
3007 if (MLX5_CAP_GEN(mdev
, cqe_compression
) &&
3008 MLX5_CAP_GEN(mdev
, vport_group_manager
)) {
3009 mlx5e_get_max_linkspeed(mdev
, &link_speed
);
3010 mlx5e_get_pci_bw(mdev
, &pci_bw
);
3011 mlx5_core_dbg(mdev
, "Max link speed = %d, PCI BW = %d\n",
3012 link_speed
, pci_bw
);
3013 priv
->params
.rx_cqe_compress_admin
=
3014 cqe_compress_heuristic(link_speed
, pci_bw
);
3017 priv
->params
.rx_cqe_compress
= priv
->params
.rx_cqe_compress_admin
;
3019 switch (priv
->params
.rq_wq_type
) {
3020 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
3021 priv
->params
.log_rq_size
= MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW
;
3022 priv
->params
.mpwqe_log_stride_sz
=
3023 priv
->params
.rx_cqe_compress
?
3024 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS
:
3025 MLX5_MPWRQ_LOG_STRIDE_SIZE
;
3026 priv
->params
.mpwqe_log_num_strides
= MLX5_MPWRQ_LOG_WQE_SZ
-
3027 priv
->params
.mpwqe_log_stride_sz
;
3028 priv
->params
.lro_en
= true;
3030 default: /* MLX5_WQ_TYPE_LINKED_LIST */
3031 priv
->params
.log_rq_size
= MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE
;
3034 mlx5_core_info(mdev
,
3035 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
3036 priv
->params
.rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
,
3037 BIT(priv
->params
.log_rq_size
),
3038 BIT(priv
->params
.mpwqe_log_stride_sz
),
3039 priv
->params
.rx_cqe_compress_admin
);
3041 priv
->params
.min_rx_wqes
= mlx5_min_rx_wqes(priv
->params
.rq_wq_type
,
3042 BIT(priv
->params
.log_rq_size
));
3044 priv
->params
.rx_am_enabled
= MLX5_CAP_GEN(mdev
, cq_moderation
);
3045 mlx5e_set_rx_cq_mode_params(&priv
->params
, cq_period_mode
);
3047 priv
->params
.tx_cq_moderation
.usec
=
3048 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC
;
3049 priv
->params
.tx_cq_moderation
.pkts
=
3050 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS
;
3051 priv
->params
.tx_max_inline
= mlx5e_get_max_inline_cap(mdev
);
3052 mlx5e_query_min_inline(mdev
, &priv
->params
.tx_min_inline_mode
);
3053 priv
->params
.num_tc
= 1;
3054 priv
->params
.rss_hfunc
= ETH_RSS_HASH_XOR
;
3056 netdev_rss_key_fill(priv
->params
.toeplitz_hash_key
,
3057 sizeof(priv
->params
.toeplitz_hash_key
));
3059 mlx5e_build_default_indir_rqt(mdev
, priv
->params
.indirection_rqt
,
3060 MLX5E_INDIR_RQT_SIZE
, profile
->max_nch(mdev
));
3062 priv
->params
.lro_wqe_sz
=
3063 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ
;
3065 /* Initialize pflags */
3066 MLX5E_SET_PRIV_FLAG(priv
, MLX5E_PFLAG_RX_CQE_BASED_MODER
,
3067 priv
->params
.rx_cq_period_mode
== MLX5_CQ_PERIOD_MODE_START_FROM_CQE
);
3070 priv
->netdev
= netdev
;
3071 priv
->params
.num_channels
= profile
->max_nch(mdev
);
3072 priv
->profile
= profile
;
3073 priv
->ppriv
= ppriv
;
3075 #ifdef CONFIG_MLX5_CORE_EN_DCB
3076 mlx5e_ets_init(priv
);
3079 mutex_init(&priv
->state_lock
);
3081 INIT_WORK(&priv
->update_carrier_work
, mlx5e_update_carrier_work
);
3082 INIT_WORK(&priv
->set_rx_mode_work
, mlx5e_set_rx_mode_work
);
3083 INIT_WORK(&priv
->tx_timeout_work
, mlx5e_tx_timeout_work
);
3084 INIT_DELAYED_WORK(&priv
->update_stats_work
, mlx5e_update_stats_work
);
3087 static void mlx5e_set_netdev_dev_addr(struct net_device
*netdev
)
3089 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3091 mlx5_query_nic_vport_mac_address(priv
->mdev
, 0, netdev
->dev_addr
);
3092 if (is_zero_ether_addr(netdev
->dev_addr
) &&
3093 !MLX5_CAP_GEN(priv
->mdev
, vport_group_manager
)) {
3094 eth_hw_addr_random(netdev
);
3095 mlx5_core_info(priv
->mdev
, "Assigned random MAC address %pM\n", netdev
->dev_addr
);
3099 static const struct switchdev_ops mlx5e_switchdev_ops
= {
3100 .switchdev_port_attr_get
= mlx5e_attr_get
,
3103 static void mlx5e_build_nic_netdev(struct net_device
*netdev
)
3105 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3106 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3110 SET_NETDEV_DEV(netdev
, &mdev
->pdev
->dev
);
3112 if (MLX5_CAP_GEN(mdev
, vport_group_manager
)) {
3113 netdev
->netdev_ops
= &mlx5e_netdev_ops_sriov
;
3114 #ifdef CONFIG_MLX5_CORE_EN_DCB
3115 netdev
->dcbnl_ops
= &mlx5e_dcbnl_ops
;
3118 netdev
->netdev_ops
= &mlx5e_netdev_ops_basic
;
3121 netdev
->watchdog_timeo
= 15 * HZ
;
3123 netdev
->ethtool_ops
= &mlx5e_ethtool_ops
;
3125 netdev
->vlan_features
|= NETIF_F_SG
;
3126 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
3127 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
3128 netdev
->vlan_features
|= NETIF_F_GRO
;
3129 netdev
->vlan_features
|= NETIF_F_TSO
;
3130 netdev
->vlan_features
|= NETIF_F_TSO6
;
3131 netdev
->vlan_features
|= NETIF_F_RXCSUM
;
3132 netdev
->vlan_features
|= NETIF_F_RXHASH
;
3134 if (!!MLX5_CAP_ETH(mdev
, lro_cap
))
3135 netdev
->vlan_features
|= NETIF_F_LRO
;
3137 netdev
->hw_features
= netdev
->vlan_features
;
3138 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_TX
;
3139 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
;
3140 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
3142 if (mlx5e_vxlan_allowed(mdev
)) {
3143 netdev
->hw_features
|= NETIF_F_GSO_UDP_TUNNEL
|
3144 NETIF_F_GSO_UDP_TUNNEL_CSUM
|
3145 NETIF_F_GSO_PARTIAL
;
3146 netdev
->hw_enc_features
|= NETIF_F_IP_CSUM
;
3147 netdev
->hw_enc_features
|= NETIF_F_IPV6_CSUM
;
3148 netdev
->hw_enc_features
|= NETIF_F_TSO
;
3149 netdev
->hw_enc_features
|= NETIF_F_TSO6
;
3150 netdev
->hw_enc_features
|= NETIF_F_GSO_UDP_TUNNEL
;
3151 netdev
->hw_enc_features
|= NETIF_F_GSO_UDP_TUNNEL_CSUM
|
3152 NETIF_F_GSO_PARTIAL
;
3153 netdev
->gso_partial_features
= NETIF_F_GSO_UDP_TUNNEL_CSUM
;
3156 mlx5_query_port_fcs(mdev
, &fcs_supported
, &fcs_enabled
);
3159 netdev
->hw_features
|= NETIF_F_RXALL
;
3161 netdev
->features
= netdev
->hw_features
;
3162 if (!priv
->params
.lro_en
)
3163 netdev
->features
&= ~NETIF_F_LRO
;
3166 netdev
->features
&= ~NETIF_F_RXALL
;
3168 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3169 if (FT_CAP(flow_modify_en
) &&
3170 FT_CAP(modify_root
) &&
3171 FT_CAP(identified_miss_table_mode
) &&
3172 FT_CAP(flow_table_modify
)) {
3173 netdev
->hw_features
|= NETIF_F_HW_TC
;
3174 #ifdef CONFIG_RFS_ACCEL
3175 netdev
->hw_features
|= NETIF_F_NTUPLE
;
3179 netdev
->features
|= NETIF_F_HIGHDMA
;
3181 netdev
->priv_flags
|= IFF_UNICAST_FLT
;
3183 mlx5e_set_netdev_dev_addr(netdev
);
3185 #ifdef CONFIG_NET_SWITCHDEV
3186 if (MLX5_CAP_GEN(mdev
, vport_group_manager
))
3187 netdev
->switchdev_ops
= &mlx5e_switchdev_ops
;
3191 static void mlx5e_create_q_counter(struct mlx5e_priv
*priv
)
3193 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3196 err
= mlx5_core_alloc_q_counter(mdev
, &priv
->q_counter
);
3198 mlx5_core_warn(mdev
, "alloc queue counter failed, %d\n", err
);
3199 priv
->q_counter
= 0;
3203 static void mlx5e_destroy_q_counter(struct mlx5e_priv
*priv
)
3205 if (!priv
->q_counter
)
3208 mlx5_core_dealloc_q_counter(priv
->mdev
, priv
->q_counter
);
3211 static int mlx5e_create_umr_mkey(struct mlx5e_priv
*priv
)
3213 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3214 struct mlx5_create_mkey_mbox_in
*in
;
3215 struct mlx5_mkey_seg
*mkc
;
3216 int inlen
= sizeof(*in
);
3217 u64 npages
= MLX5E_REQUIRED_MTTS(priv
->profile
->max_nch(mdev
),
3218 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW
));
3221 in
= mlx5_vzalloc(inlen
);
3226 mkc
->status
= MLX5_MKEY_STATUS_FREE
;
3227 mkc
->flags
= MLX5_PERM_UMR_EN
|
3228 MLX5_PERM_LOCAL_READ
|
3229 MLX5_PERM_LOCAL_WRITE
|
3230 MLX5_ACCESS_MODE_MTT
;
3232 npages
= min_t(u32
, ALIGN(U16_MAX
, 4) * 2, npages
);
3234 mkc
->qpn_mkey7_0
= cpu_to_be32(0xffffff << 8);
3235 mkc
->flags_pd
= cpu_to_be32(mdev
->mlx5e_res
.pdn
);
3236 mkc
->len
= cpu_to_be64(npages
<< PAGE_SHIFT
);
3237 mkc
->xlt_oct_size
= cpu_to_be32(MLX5_MTT_OCTW(npages
));
3238 mkc
->log2_page_size
= PAGE_SHIFT
;
3240 err
= mlx5_core_create_mkey(mdev
, &priv
->umr_mkey
, in
, inlen
, NULL
,
3248 static void mlx5e_nic_init(struct mlx5_core_dev
*mdev
,
3249 struct net_device
*netdev
,
3250 const struct mlx5e_profile
*profile
,
3253 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3255 mlx5e_build_nic_netdev_priv(mdev
, netdev
, profile
, ppriv
);
3256 mlx5e_build_nic_netdev(netdev
);
3257 mlx5e_vxlan_init(priv
);
3260 static void mlx5e_nic_cleanup(struct mlx5e_priv
*priv
)
3262 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3263 struct mlx5_eswitch
*esw
= mdev
->priv
.eswitch
;
3265 mlx5e_vxlan_cleanup(priv
);
3267 if (MLX5_CAP_GEN(mdev
, vport_group_manager
))
3268 mlx5_eswitch_unregister_vport_rep(esw
, 0);
3271 static int mlx5e_init_nic_rx(struct mlx5e_priv
*priv
)
3273 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3277 err
= mlx5e_create_indirect_rqts(priv
);
3279 mlx5_core_warn(mdev
, "create indirect rqts failed, %d\n", err
);
3283 err
= mlx5e_create_direct_rqts(priv
);
3285 mlx5_core_warn(mdev
, "create direct rqts failed, %d\n", err
);
3286 goto err_destroy_indirect_rqts
;
3289 err
= mlx5e_create_indirect_tirs(priv
);
3291 mlx5_core_warn(mdev
, "create indirect tirs failed, %d\n", err
);
3292 goto err_destroy_direct_rqts
;
3295 err
= mlx5e_create_direct_tirs(priv
);
3297 mlx5_core_warn(mdev
, "create direct tirs failed, %d\n", err
);
3298 goto err_destroy_indirect_tirs
;
3301 err
= mlx5e_create_flow_steering(priv
);
3303 mlx5_core_warn(mdev
, "create flow steering failed, %d\n", err
);
3304 goto err_destroy_direct_tirs
;
3307 err
= mlx5e_tc_init(priv
);
3309 goto err_destroy_flow_steering
;
3313 err_destroy_flow_steering
:
3314 mlx5e_destroy_flow_steering(priv
);
3315 err_destroy_direct_tirs
:
3316 mlx5e_destroy_direct_tirs(priv
);
3317 err_destroy_indirect_tirs
:
3318 mlx5e_destroy_indirect_tirs(priv
);
3319 err_destroy_direct_rqts
:
3320 for (i
= 0; i
< priv
->profile
->max_nch(mdev
); i
++)
3321 mlx5e_destroy_rqt(priv
, &priv
->direct_tir
[i
].rqt
);
3322 err_destroy_indirect_rqts
:
3323 mlx5e_destroy_rqt(priv
, &priv
->indir_rqt
);
3327 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv
*priv
)
3331 mlx5e_tc_cleanup(priv
);
3332 mlx5e_destroy_flow_steering(priv
);
3333 mlx5e_destroy_direct_tirs(priv
);
3334 mlx5e_destroy_indirect_tirs(priv
);
3335 for (i
= 0; i
< priv
->profile
->max_nch(priv
->mdev
); i
++)
3336 mlx5e_destroy_rqt(priv
, &priv
->direct_tir
[i
].rqt
);
3337 mlx5e_destroy_rqt(priv
, &priv
->indir_rqt
);
3340 static int mlx5e_init_nic_tx(struct mlx5e_priv
*priv
)
3344 err
= mlx5e_create_tises(priv
);
3346 mlx5_core_warn(priv
->mdev
, "create tises failed, %d\n", err
);
3350 #ifdef CONFIG_MLX5_CORE_EN_DCB
3351 mlx5e_dcbnl_ieee_setets_core(priv
, &priv
->params
.ets
);
3356 static void mlx5e_nic_enable(struct mlx5e_priv
*priv
)
3358 struct net_device
*netdev
= priv
->netdev
;
3359 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3360 struct mlx5_eswitch
*esw
= mdev
->priv
.eswitch
;
3361 struct mlx5_eswitch_rep rep
;
3363 if (mlx5e_vxlan_allowed(mdev
)) {
3365 udp_tunnel_get_rx_info(netdev
);
3369 mlx5e_enable_async_events(priv
);
3370 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
3372 if (MLX5_CAP_GEN(mdev
, vport_group_manager
)) {
3373 mlx5_query_nic_vport_mac_address(mdev
, 0, rep
.hw_id
);
3374 rep
.load
= mlx5e_nic_rep_load
;
3375 rep
.unload
= mlx5e_nic_rep_unload
;
3377 rep
.priv_data
= priv
;
3378 mlx5_eswitch_register_vport_rep(esw
, &rep
);
3382 static void mlx5e_nic_disable(struct mlx5e_priv
*priv
)
3384 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
3385 mlx5e_disable_async_events(priv
);
3388 static const struct mlx5e_profile mlx5e_nic_profile
= {
3389 .init
= mlx5e_nic_init
,
3390 .cleanup
= mlx5e_nic_cleanup
,
3391 .init_rx
= mlx5e_init_nic_rx
,
3392 .cleanup_rx
= mlx5e_cleanup_nic_rx
,
3393 .init_tx
= mlx5e_init_nic_tx
,
3394 .cleanup_tx
= mlx5e_cleanup_nic_tx
,
3395 .enable
= mlx5e_nic_enable
,
3396 .disable
= mlx5e_nic_disable
,
3397 .update_stats
= mlx5e_update_stats
,
3398 .max_nch
= mlx5e_get_max_num_channels
,
3399 .max_tc
= MLX5E_MAX_NUM_TC
,
3402 void *mlx5e_create_netdev(struct mlx5_core_dev
*mdev
,
3403 const struct mlx5e_profile
*profile
, void *ppriv
)
3405 struct net_device
*netdev
;
3406 struct mlx5e_priv
*priv
;
3407 int nch
= profile
->max_nch(mdev
);
3410 netdev
= alloc_etherdev_mqs(sizeof(struct mlx5e_priv
),
3411 nch
* profile
->max_tc
,
3414 mlx5_core_err(mdev
, "alloc_etherdev_mqs() failed\n");
3418 profile
->init(mdev
, netdev
, profile
, ppriv
);
3420 netif_carrier_off(netdev
);
3422 priv
= netdev_priv(netdev
);
3424 priv
->wq
= create_singlethread_workqueue("mlx5e");
3426 goto err_free_netdev
;
3428 err
= mlx5e_create_umr_mkey(priv
);
3430 mlx5_core_err(mdev
, "create umr mkey failed, %d\n", err
);
3431 goto err_destroy_wq
;
3434 err
= profile
->init_tx(priv
);
3436 goto err_destroy_umr_mkey
;
3438 err
= mlx5e_open_drop_rq(priv
);
3440 mlx5_core_err(mdev
, "open drop rq failed, %d\n", err
);
3441 goto err_cleanup_tx
;
3444 err
= profile
->init_rx(priv
);
3446 goto err_close_drop_rq
;
3448 mlx5e_create_q_counter(priv
);
3450 mlx5e_init_l2_addr(priv
);
3452 mlx5e_set_dev_port_mtu(netdev
);
3454 err
= register_netdev(netdev
);
3456 mlx5_core_err(mdev
, "register_netdev failed, %d\n", err
);
3457 goto err_dealloc_q_counters
;
3460 if (profile
->enable
)
3461 profile
->enable(priv
);
3465 err_dealloc_q_counters
:
3466 mlx5e_destroy_q_counter(priv
);
3467 profile
->cleanup_rx(priv
);
3470 mlx5e_close_drop_rq(priv
);
3473 profile
->cleanup_tx(priv
);
3475 err_destroy_umr_mkey
:
3476 mlx5_core_destroy_mkey(mdev
, &priv
->umr_mkey
);
3479 destroy_workqueue(priv
->wq
);
3482 free_netdev(netdev
);
3487 static void mlx5e_register_vport_rep(struct mlx5_core_dev
*mdev
)
3489 struct mlx5_eswitch
*esw
= mdev
->priv
.eswitch
;
3490 int total_vfs
= MLX5_TOTAL_VPORTS(mdev
);
3494 if (!MLX5_CAP_GEN(mdev
, vport_group_manager
))
3497 mlx5_query_nic_vport_mac_address(mdev
, 0, mac
);
3499 for (vport
= 1; vport
< total_vfs
; vport
++) {
3500 struct mlx5_eswitch_rep rep
;
3502 rep
.load
= mlx5e_vport_rep_load
;
3503 rep
.unload
= mlx5e_vport_rep_unload
;
3505 ether_addr_copy(rep
.hw_id
, mac
);
3506 mlx5_eswitch_register_vport_rep(esw
, &rep
);
3510 static void *mlx5e_add(struct mlx5_core_dev
*mdev
)
3512 struct mlx5_eswitch
*esw
= mdev
->priv
.eswitch
;
3516 if (mlx5e_check_required_hca_cap(mdev
))
3519 if (mlx5e_create_mdev_resources(mdev
))
3522 mlx5e_register_vport_rep(mdev
);
3524 if (MLX5_CAP_GEN(mdev
, vport_group_manager
))
3525 ppriv
= &esw
->offloads
.vport_reps
[0];
3527 ret
= mlx5e_create_netdev(mdev
, &mlx5e_nic_profile
, ppriv
);
3529 mlx5e_destroy_mdev_resources(mdev
);
3535 void mlx5e_destroy_netdev(struct mlx5_core_dev
*mdev
, struct mlx5e_priv
*priv
)
3537 const struct mlx5e_profile
*profile
= priv
->profile
;
3538 struct net_device
*netdev
= priv
->netdev
;
3540 set_bit(MLX5E_STATE_DESTROYING
, &priv
->state
);
3541 if (profile
->disable
)
3542 profile
->disable(priv
);
3544 flush_workqueue(priv
->wq
);
3545 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN
, &mdev
->intf_state
)) {
3546 netif_device_detach(netdev
);
3547 mlx5e_close(netdev
);
3549 unregister_netdev(netdev
);
3552 mlx5e_destroy_q_counter(priv
);
3553 profile
->cleanup_rx(priv
);
3554 mlx5e_close_drop_rq(priv
);
3555 profile
->cleanup_tx(priv
);
3556 mlx5_core_destroy_mkey(priv
->mdev
, &priv
->umr_mkey
);
3557 cancel_delayed_work_sync(&priv
->update_stats_work
);
3558 destroy_workqueue(priv
->wq
);
3559 if (profile
->cleanup
)
3560 profile
->cleanup(priv
);
3562 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN
, &mdev
->intf_state
))
3563 free_netdev(netdev
);
3566 static void mlx5e_remove(struct mlx5_core_dev
*mdev
, void *vpriv
)
3568 struct mlx5_eswitch
*esw
= mdev
->priv
.eswitch
;
3569 int total_vfs
= MLX5_TOTAL_VPORTS(mdev
);
3570 struct mlx5e_priv
*priv
= vpriv
;
3573 mlx5e_destroy_netdev(mdev
, priv
);
3575 for (vport
= 1; vport
< total_vfs
; vport
++)
3576 mlx5_eswitch_unregister_vport_rep(esw
, vport
);
3578 mlx5e_destroy_mdev_resources(mdev
);
3581 static void *mlx5e_get_netdev(void *vpriv
)
3583 struct mlx5e_priv
*priv
= vpriv
;
3585 return priv
->netdev
;
3588 static struct mlx5_interface mlx5e_interface
= {
3590 .remove
= mlx5e_remove
,
3591 .event
= mlx5e_async_event
,
3592 .protocol
= MLX5_INTERFACE_PROTOCOL_ETH
,
3593 .get_dev
= mlx5e_get_netdev
,
3596 void mlx5e_init(void)
3598 mlx5e_build_ptys2ethtool_map();
3599 mlx5_register_interface(&mlx5e_interface
);
3602 void mlx5e_cleanup(void)
3604 mlx5_unregister_interface(&mlx5e_interface
);