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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include "en.h"
38 #include "en_tc.h"
39 #include "eswitch.h"
40 #include "vxlan.h"
41
42 struct mlx5e_rq_param {
43 u32 rqc[MLX5_ST_SZ_DW(rqc)];
44 struct mlx5_wq_param wq;
45 bool am_enabled;
46 };
47
48 struct mlx5e_sq_param {
49 u32 sqc[MLX5_ST_SZ_DW(sqc)];
50 struct mlx5_wq_param wq;
51 u16 max_inline;
52 u8 min_inline_mode;
53 bool icosq;
54 };
55
56 struct mlx5e_cq_param {
57 u32 cqc[MLX5_ST_SZ_DW(cqc)];
58 struct mlx5_wq_param wq;
59 u16 eq_ix;
60 u8 cq_period_mode;
61 };
62
63 struct mlx5e_channel_param {
64 struct mlx5e_rq_param rq;
65 struct mlx5e_sq_param sq;
66 struct mlx5e_sq_param icosq;
67 struct mlx5e_cq_param rx_cq;
68 struct mlx5e_cq_param tx_cq;
69 struct mlx5e_cq_param icosq_cq;
70 };
71
72 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
73 {
74 struct mlx5_core_dev *mdev = priv->mdev;
75 u8 port_state;
76
77 port_state = mlx5_query_vport_state(mdev,
78 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
79
80 if (port_state == VPORT_STATE_UP) {
81 netdev_info(priv->netdev, "Link up\n");
82 netif_carrier_on(priv->netdev);
83 } else {
84 netdev_info(priv->netdev, "Link down\n");
85 netif_carrier_off(priv->netdev);
86 }
87 }
88
89 static void mlx5e_update_carrier_work(struct work_struct *work)
90 {
91 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
92 update_carrier_work);
93
94 mutex_lock(&priv->state_lock);
95 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
96 mlx5e_update_carrier(priv);
97 mutex_unlock(&priv->state_lock);
98 }
99
100 static void mlx5e_tx_timeout_work(struct work_struct *work)
101 {
102 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
103 tx_timeout_work);
104 int err;
105
106 rtnl_lock();
107 mutex_lock(&priv->state_lock);
108 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
109 goto unlock;
110 mlx5e_close_locked(priv->netdev);
111 err = mlx5e_open_locked(priv->netdev);
112 if (err)
113 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
114 err);
115 unlock:
116 mutex_unlock(&priv->state_lock);
117 rtnl_unlock();
118 }
119
120 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
121 {
122 struct mlx5e_sw_stats *s = &priv->stats.sw;
123 struct mlx5e_rq_stats *rq_stats;
124 struct mlx5e_sq_stats *sq_stats;
125 u64 tx_offload_none = 0;
126 int i, j;
127
128 memset(s, 0, sizeof(*s));
129 for (i = 0; i < priv->params.num_channels; i++) {
130 rq_stats = &priv->channel[i]->rq.stats;
131
132 s->rx_packets += rq_stats->packets;
133 s->rx_bytes += rq_stats->bytes;
134 s->rx_lro_packets += rq_stats->lro_packets;
135 s->rx_lro_bytes += rq_stats->lro_bytes;
136 s->rx_csum_none += rq_stats->csum_none;
137 s->rx_csum_complete += rq_stats->csum_complete;
138 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
139 s->rx_wqe_err += rq_stats->wqe_err;
140 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
141 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
142 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
143 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
144 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
145
146 for (j = 0; j < priv->params.num_tc; j++) {
147 sq_stats = &priv->channel[i]->sq[j].stats;
148
149 s->tx_packets += sq_stats->packets;
150 s->tx_bytes += sq_stats->bytes;
151 s->tx_tso_packets += sq_stats->tso_packets;
152 s->tx_tso_bytes += sq_stats->tso_bytes;
153 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
154 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
155 s->tx_queue_stopped += sq_stats->stopped;
156 s->tx_queue_wake += sq_stats->wake;
157 s->tx_queue_dropped += sq_stats->dropped;
158 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
159 tx_offload_none += sq_stats->csum_none;
160 }
161 }
162
163 /* Update calculated offload counters */
164 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
165 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
166
167 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
168 priv->stats.pport.phy_counters,
169 counter_set.phys_layer_cntrs.link_down_events);
170 }
171
172 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
173 {
174 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
175 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
176 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
177 struct mlx5_core_dev *mdev = priv->mdev;
178
179 memset(in, 0, sizeof(in));
180
181 MLX5_SET(query_vport_counter_in, in, opcode,
182 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
183 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
184 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
185
186 memset(out, 0, outlen);
187
188 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
189 }
190
191 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
192 {
193 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
194 struct mlx5_core_dev *mdev = priv->mdev;
195 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
196 int prio;
197 void *out;
198 u32 *in;
199
200 in = mlx5_vzalloc(sz);
201 if (!in)
202 goto free_out;
203
204 MLX5_SET(ppcnt_reg, in, local_port, 1);
205
206 out = pstats->IEEE_802_3_counters;
207 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
208 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
209
210 out = pstats->RFC_2863_counters;
211 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
212 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
213
214 out = pstats->RFC_2819_counters;
215 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
216 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
217
218 out = pstats->phy_counters;
219 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
220 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
221
222 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
223 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
224 out = pstats->per_prio_counters[prio];
225 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
226 mlx5_core_access_reg(mdev, in, sz, out, sz,
227 MLX5_REG_PPCNT, 0, 0);
228 }
229
230 free_out:
231 kvfree(in);
232 }
233
234 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
235 {
236 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
237
238 if (!priv->q_counter)
239 return;
240
241 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
242 &qcnt->rx_out_of_buffer);
243 }
244
245 void mlx5e_update_stats(struct mlx5e_priv *priv)
246 {
247 mlx5e_update_q_counter(priv);
248 mlx5e_update_vport_counters(priv);
249 mlx5e_update_pport_counters(priv);
250 mlx5e_update_sw_counters(priv);
251 }
252
253 void mlx5e_update_stats_work(struct work_struct *work)
254 {
255 struct delayed_work *dwork = to_delayed_work(work);
256 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
257 update_stats_work);
258 mutex_lock(&priv->state_lock);
259 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
260 priv->profile->update_stats(priv);
261 queue_delayed_work(priv->wq, dwork,
262 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
263 }
264 mutex_unlock(&priv->state_lock);
265 }
266
267 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
268 enum mlx5_dev_event event, unsigned long param)
269 {
270 struct mlx5e_priv *priv = vpriv;
271
272 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
273 return;
274
275 switch (event) {
276 case MLX5_DEV_EVENT_PORT_UP:
277 case MLX5_DEV_EVENT_PORT_DOWN:
278 queue_work(priv->wq, &priv->update_carrier_work);
279 break;
280
281 default:
282 break;
283 }
284 }
285
286 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
287 {
288 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
289 }
290
291 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
292 {
293 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
294 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
295 }
296
297 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
298 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
299
300 static int mlx5e_create_rq(struct mlx5e_channel *c,
301 struct mlx5e_rq_param *param,
302 struct mlx5e_rq *rq)
303 {
304 struct mlx5e_priv *priv = c->priv;
305 struct mlx5_core_dev *mdev = priv->mdev;
306 void *rqc = param->rqc;
307 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
308 u32 byte_count;
309 int wq_sz;
310 int err;
311 int i;
312
313 param->wq.db_numa_node = cpu_to_node(c->cpu);
314
315 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
316 &rq->wq_ctrl);
317 if (err)
318 return err;
319
320 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
321
322 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
323
324 switch (priv->params.rq_wq_type) {
325 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
326 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
327 GFP_KERNEL, cpu_to_node(c->cpu));
328 if (!rq->wqe_info) {
329 err = -ENOMEM;
330 goto err_rq_wq_destroy;
331 }
332 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
333 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
334 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
335
336 rq->mpwqe_mtt_offset = c->ix *
337 MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
338
339 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
340 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
341 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
342 byte_count = rq->wqe_sz;
343 break;
344 default: /* MLX5_WQ_TYPE_LINKED_LIST */
345 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
346 cpu_to_node(c->cpu));
347 if (!rq->skb) {
348 err = -ENOMEM;
349 goto err_rq_wq_destroy;
350 }
351 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
352 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
353 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
354
355 rq->wqe_sz = (priv->params.lro_en) ?
356 priv->params.lro_wqe_sz :
357 MLX5E_SW2HW_MTU(priv->netdev->mtu);
358 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
359 byte_count = rq->wqe_sz;
360 byte_count |= MLX5_HW_START_PADDING;
361 }
362
363 for (i = 0; i < wq_sz; i++) {
364 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
365
366 wqe->data.byte_count = cpu_to_be32(byte_count);
367 }
368
369 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
370 rq->am.mode = priv->params.rx_cq_period_mode;
371
372 rq->wq_type = priv->params.rq_wq_type;
373 rq->pdev = c->pdev;
374 rq->netdev = c->netdev;
375 rq->tstamp = &priv->tstamp;
376 rq->channel = c;
377 rq->ix = c->ix;
378 rq->priv = c->priv;
379 rq->mkey_be = c->mkey_be;
380 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
381
382 return 0;
383
384 err_rq_wq_destroy:
385 mlx5_wq_destroy(&rq->wq_ctrl);
386
387 return err;
388 }
389
390 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
391 {
392 switch (rq->wq_type) {
393 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
394 kfree(rq->wqe_info);
395 break;
396 default: /* MLX5_WQ_TYPE_LINKED_LIST */
397 kfree(rq->skb);
398 }
399
400 mlx5_wq_destroy(&rq->wq_ctrl);
401 }
402
403 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
404 {
405 struct mlx5e_priv *priv = rq->priv;
406 struct mlx5_core_dev *mdev = priv->mdev;
407
408 void *in;
409 void *rqc;
410 void *wq;
411 int inlen;
412 int err;
413
414 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
415 sizeof(u64) * rq->wq_ctrl.buf.npages;
416 in = mlx5_vzalloc(inlen);
417 if (!in)
418 return -ENOMEM;
419
420 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
421 wq = MLX5_ADDR_OF(rqc, rqc, wq);
422
423 memcpy(rqc, param->rqc, sizeof(param->rqc));
424
425 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
426 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
427 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
428 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
429 MLX5_ADAPTER_PAGE_SHIFT);
430 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
431
432 mlx5_fill_page_array(&rq->wq_ctrl.buf,
433 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
434
435 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
436
437 kvfree(in);
438
439 return err;
440 }
441
442 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
443 int next_state)
444 {
445 struct mlx5e_channel *c = rq->channel;
446 struct mlx5e_priv *priv = c->priv;
447 struct mlx5_core_dev *mdev = priv->mdev;
448
449 void *in;
450 void *rqc;
451 int inlen;
452 int err;
453
454 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
455 in = mlx5_vzalloc(inlen);
456 if (!in)
457 return -ENOMEM;
458
459 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
460
461 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
462 MLX5_SET(rqc, rqc, state, next_state);
463
464 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
465
466 kvfree(in);
467
468 return err;
469 }
470
471 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
472 {
473 struct mlx5e_channel *c = rq->channel;
474 struct mlx5e_priv *priv = c->priv;
475 struct mlx5_core_dev *mdev = priv->mdev;
476
477 void *in;
478 void *rqc;
479 int inlen;
480 int err;
481
482 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
483 in = mlx5_vzalloc(inlen);
484 if (!in)
485 return -ENOMEM;
486
487 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
488
489 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
490 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
491 MLX5_SET(rqc, rqc, vsd, vsd);
492 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
493
494 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
495
496 kvfree(in);
497
498 return err;
499 }
500
501 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
502 {
503 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
504 }
505
506 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
507 {
508 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
509 struct mlx5e_channel *c = rq->channel;
510 struct mlx5e_priv *priv = c->priv;
511 struct mlx5_wq_ll *wq = &rq->wq;
512
513 while (time_before(jiffies, exp_time)) {
514 if (wq->cur_sz >= priv->params.min_rx_wqes)
515 return 0;
516
517 msleep(20);
518 }
519
520 return -ETIMEDOUT;
521 }
522
523 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
524 {
525 struct mlx5_wq_ll *wq = &rq->wq;
526 struct mlx5e_rx_wqe *wqe;
527 __be16 wqe_ix_be;
528 u16 wqe_ix;
529
530 /* UMR WQE (if in progress) is always at wq->head */
531 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
532 mlx5e_free_rx_fragmented_mpwqe(rq, &rq->wqe_info[wq->head]);
533
534 while (!mlx5_wq_ll_is_empty(wq)) {
535 wqe_ix_be = *wq->tail_next;
536 wqe_ix = be16_to_cpu(wqe_ix_be);
537 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
538 rq->dealloc_wqe(rq, wqe_ix);
539 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
540 &wqe->next.next_wqe_index);
541 }
542 }
543
544 static int mlx5e_open_rq(struct mlx5e_channel *c,
545 struct mlx5e_rq_param *param,
546 struct mlx5e_rq *rq)
547 {
548 struct mlx5e_sq *sq = &c->icosq;
549 u16 pi = sq->pc & sq->wq.sz_m1;
550 int err;
551
552 err = mlx5e_create_rq(c, param, rq);
553 if (err)
554 return err;
555
556 err = mlx5e_enable_rq(rq, param);
557 if (err)
558 goto err_destroy_rq;
559
560 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
561 if (err)
562 goto err_disable_rq;
563
564 if (param->am_enabled)
565 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
566
567 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
568 sq->ico_wqe_info[pi].num_wqebbs = 1;
569 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
570
571 return 0;
572
573 err_disable_rq:
574 mlx5e_disable_rq(rq);
575 err_destroy_rq:
576 mlx5e_destroy_rq(rq);
577
578 return err;
579 }
580
581 static void mlx5e_close_rq(struct mlx5e_rq *rq)
582 {
583 set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
584 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
585 cancel_work_sync(&rq->am.work);
586
587 mlx5e_disable_rq(rq);
588 mlx5e_free_rx_descs(rq);
589 mlx5e_destroy_rq(rq);
590 }
591
592 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
593 {
594 kfree(sq->wqe_info);
595 kfree(sq->dma_fifo);
596 kfree(sq->skb);
597 }
598
599 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
600 {
601 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
602 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
603
604 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
605 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
606 numa);
607 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
608 numa);
609
610 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
611 mlx5e_free_sq_db(sq);
612 return -ENOMEM;
613 }
614
615 sq->dma_fifo_mask = df_sz - 1;
616
617 return 0;
618 }
619
620 static int mlx5e_create_sq(struct mlx5e_channel *c,
621 int tc,
622 struct mlx5e_sq_param *param,
623 struct mlx5e_sq *sq)
624 {
625 struct mlx5e_priv *priv = c->priv;
626 struct mlx5_core_dev *mdev = priv->mdev;
627
628 void *sqc = param->sqc;
629 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
630 int err;
631
632 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
633 if (err)
634 return err;
635
636 param->wq.db_numa_node = cpu_to_node(c->cpu);
637
638 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
639 &sq->wq_ctrl);
640 if (err)
641 goto err_unmap_free_uar;
642
643 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
644 if (sq->uar.bf_map) {
645 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
646 sq->uar_map = sq->uar.bf_map;
647 } else {
648 sq->uar_map = sq->uar.map;
649 }
650 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
651 sq->max_inline = param->max_inline;
652 sq->min_inline_mode =
653 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
654 param->min_inline_mode : 0;
655
656 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
657 if (err)
658 goto err_sq_wq_destroy;
659
660 if (param->icosq) {
661 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
662
663 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
664 wq_sz,
665 GFP_KERNEL,
666 cpu_to_node(c->cpu));
667 if (!sq->ico_wqe_info) {
668 err = -ENOMEM;
669 goto err_free_sq_db;
670 }
671 } else {
672 int txq_ix;
673
674 txq_ix = c->ix + tc * priv->params.num_channels;
675 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
676 priv->txq_to_sq_map[txq_ix] = sq;
677 }
678
679 sq->pdev = c->pdev;
680 sq->tstamp = &priv->tstamp;
681 sq->mkey_be = c->mkey_be;
682 sq->channel = c;
683 sq->tc = tc;
684 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
685 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
686
687 return 0;
688
689 err_free_sq_db:
690 mlx5e_free_sq_db(sq);
691
692 err_sq_wq_destroy:
693 mlx5_wq_destroy(&sq->wq_ctrl);
694
695 err_unmap_free_uar:
696 mlx5_unmap_free_uar(mdev, &sq->uar);
697
698 return err;
699 }
700
701 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
702 {
703 struct mlx5e_channel *c = sq->channel;
704 struct mlx5e_priv *priv = c->priv;
705
706 kfree(sq->ico_wqe_info);
707 mlx5e_free_sq_db(sq);
708 mlx5_wq_destroy(&sq->wq_ctrl);
709 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
710 }
711
712 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
713 {
714 struct mlx5e_channel *c = sq->channel;
715 struct mlx5e_priv *priv = c->priv;
716 struct mlx5_core_dev *mdev = priv->mdev;
717
718 void *in;
719 void *sqc;
720 void *wq;
721 int inlen;
722 int err;
723
724 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
725 sizeof(u64) * sq->wq_ctrl.buf.npages;
726 in = mlx5_vzalloc(inlen);
727 if (!in)
728 return -ENOMEM;
729
730 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
731 wq = MLX5_ADDR_OF(sqc, sqc, wq);
732
733 memcpy(sqc, param->sqc, sizeof(param->sqc));
734
735 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
736 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
737 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
738 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
739 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
740 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
741
742 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
743 MLX5_SET(wq, wq, uar_page, sq->uar.index);
744 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
745 MLX5_ADAPTER_PAGE_SHIFT);
746 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
747
748 mlx5_fill_page_array(&sq->wq_ctrl.buf,
749 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
750
751 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
752
753 kvfree(in);
754
755 return err;
756 }
757
758 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
759 int next_state, bool update_rl, int rl_index)
760 {
761 struct mlx5e_channel *c = sq->channel;
762 struct mlx5e_priv *priv = c->priv;
763 struct mlx5_core_dev *mdev = priv->mdev;
764
765 void *in;
766 void *sqc;
767 int inlen;
768 int err;
769
770 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
771 in = mlx5_vzalloc(inlen);
772 if (!in)
773 return -ENOMEM;
774
775 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
776
777 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
778 MLX5_SET(sqc, sqc, state, next_state);
779 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
780 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
781 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
782 }
783
784 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
785
786 kvfree(in);
787
788 return err;
789 }
790
791 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
792 {
793 struct mlx5e_channel *c = sq->channel;
794 struct mlx5e_priv *priv = c->priv;
795 struct mlx5_core_dev *mdev = priv->mdev;
796
797 mlx5_core_destroy_sq(mdev, sq->sqn);
798 if (sq->rate_limit)
799 mlx5_rl_remove_rate(mdev, sq->rate_limit);
800 }
801
802 static int mlx5e_open_sq(struct mlx5e_channel *c,
803 int tc,
804 struct mlx5e_sq_param *param,
805 struct mlx5e_sq *sq)
806 {
807 int err;
808
809 err = mlx5e_create_sq(c, tc, param, sq);
810 if (err)
811 return err;
812
813 err = mlx5e_enable_sq(sq, param);
814 if (err)
815 goto err_destroy_sq;
816
817 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
818 false, 0);
819 if (err)
820 goto err_disable_sq;
821
822 if (sq->txq) {
823 netdev_tx_reset_queue(sq->txq);
824 netif_tx_start_queue(sq->txq);
825 }
826
827 return 0;
828
829 err_disable_sq:
830 mlx5e_disable_sq(sq);
831 err_destroy_sq:
832 mlx5e_destroy_sq(sq);
833
834 return err;
835 }
836
837 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
838 {
839 __netif_tx_lock_bh(txq);
840 netif_tx_stop_queue(txq);
841 __netif_tx_unlock_bh(txq);
842 }
843
844 static void mlx5e_close_sq(struct mlx5e_sq *sq)
845 {
846 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
847 /* prevent netif_tx_wake_queue */
848 napi_synchronize(&sq->channel->napi);
849
850 if (sq->txq) {
851 netif_tx_disable_queue(sq->txq);
852
853 /* last doorbell out, godspeed .. */
854 if (mlx5e_sq_has_room_for(sq, 1))
855 mlx5e_send_nop(sq, true);
856 }
857
858 mlx5e_disable_sq(sq);
859 mlx5e_free_tx_descs(sq);
860 mlx5e_destroy_sq(sq);
861 }
862
863 static int mlx5e_create_cq(struct mlx5e_channel *c,
864 struct mlx5e_cq_param *param,
865 struct mlx5e_cq *cq)
866 {
867 struct mlx5e_priv *priv = c->priv;
868 struct mlx5_core_dev *mdev = priv->mdev;
869 struct mlx5_core_cq *mcq = &cq->mcq;
870 int eqn_not_used;
871 unsigned int irqn;
872 int err;
873 u32 i;
874
875 param->wq.buf_numa_node = cpu_to_node(c->cpu);
876 param->wq.db_numa_node = cpu_to_node(c->cpu);
877 param->eq_ix = c->ix;
878
879 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
880 &cq->wq_ctrl);
881 if (err)
882 return err;
883
884 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
885
886 cq->napi = &c->napi;
887
888 mcq->cqe_sz = 64;
889 mcq->set_ci_db = cq->wq_ctrl.db.db;
890 mcq->arm_db = cq->wq_ctrl.db.db + 1;
891 *mcq->set_ci_db = 0;
892 *mcq->arm_db = 0;
893 mcq->vector = param->eq_ix;
894 mcq->comp = mlx5e_completion_event;
895 mcq->event = mlx5e_cq_error_event;
896 mcq->irqn = irqn;
897 mcq->uar = &mdev->mlx5e_res.cq_uar;
898
899 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
900 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
901
902 cqe->op_own = 0xf1;
903 }
904
905 cq->channel = c;
906 cq->priv = priv;
907
908 return 0;
909 }
910
911 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
912 {
913 mlx5_wq_destroy(&cq->wq_ctrl);
914 }
915
916 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
917 {
918 struct mlx5e_priv *priv = cq->priv;
919 struct mlx5_core_dev *mdev = priv->mdev;
920 struct mlx5_core_cq *mcq = &cq->mcq;
921
922 void *in;
923 void *cqc;
924 int inlen;
925 unsigned int irqn_not_used;
926 int eqn;
927 int err;
928
929 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
930 sizeof(u64) * cq->wq_ctrl.buf.npages;
931 in = mlx5_vzalloc(inlen);
932 if (!in)
933 return -ENOMEM;
934
935 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
936
937 memcpy(cqc, param->cqc, sizeof(param->cqc));
938
939 mlx5_fill_page_array(&cq->wq_ctrl.buf,
940 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
941
942 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
943
944 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
945 MLX5_SET(cqc, cqc, c_eqn, eqn);
946 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
947 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
948 MLX5_ADAPTER_PAGE_SHIFT);
949 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
950
951 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
952
953 kvfree(in);
954
955 if (err)
956 return err;
957
958 mlx5e_cq_arm(cq);
959
960 return 0;
961 }
962
963 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
964 {
965 struct mlx5e_priv *priv = cq->priv;
966 struct mlx5_core_dev *mdev = priv->mdev;
967
968 mlx5_core_destroy_cq(mdev, &cq->mcq);
969 }
970
971 static int mlx5e_open_cq(struct mlx5e_channel *c,
972 struct mlx5e_cq_param *param,
973 struct mlx5e_cq *cq,
974 struct mlx5e_cq_moder moderation)
975 {
976 int err;
977 struct mlx5e_priv *priv = c->priv;
978 struct mlx5_core_dev *mdev = priv->mdev;
979
980 err = mlx5e_create_cq(c, param, cq);
981 if (err)
982 return err;
983
984 err = mlx5e_enable_cq(cq, param);
985 if (err)
986 goto err_destroy_cq;
987
988 if (MLX5_CAP_GEN(mdev, cq_moderation))
989 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
990 moderation.usec,
991 moderation.pkts);
992 return 0;
993
994 err_destroy_cq:
995 mlx5e_destroy_cq(cq);
996
997 return err;
998 }
999
1000 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1001 {
1002 mlx5e_disable_cq(cq);
1003 mlx5e_destroy_cq(cq);
1004 }
1005
1006 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1007 {
1008 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1009 }
1010
1011 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1012 struct mlx5e_channel_param *cparam)
1013 {
1014 struct mlx5e_priv *priv = c->priv;
1015 int err;
1016 int tc;
1017
1018 for (tc = 0; tc < c->num_tc; tc++) {
1019 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1020 priv->params.tx_cq_moderation);
1021 if (err)
1022 goto err_close_tx_cqs;
1023 }
1024
1025 return 0;
1026
1027 err_close_tx_cqs:
1028 for (tc--; tc >= 0; tc--)
1029 mlx5e_close_cq(&c->sq[tc].cq);
1030
1031 return err;
1032 }
1033
1034 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1035 {
1036 int tc;
1037
1038 for (tc = 0; tc < c->num_tc; tc++)
1039 mlx5e_close_cq(&c->sq[tc].cq);
1040 }
1041
1042 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1043 struct mlx5e_channel_param *cparam)
1044 {
1045 int err;
1046 int tc;
1047
1048 for (tc = 0; tc < c->num_tc; tc++) {
1049 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1050 if (err)
1051 goto err_close_sqs;
1052 }
1053
1054 return 0;
1055
1056 err_close_sqs:
1057 for (tc--; tc >= 0; tc--)
1058 mlx5e_close_sq(&c->sq[tc]);
1059
1060 return err;
1061 }
1062
1063 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1064 {
1065 int tc;
1066
1067 for (tc = 0; tc < c->num_tc; tc++)
1068 mlx5e_close_sq(&c->sq[tc]);
1069 }
1070
1071 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1072 {
1073 int i;
1074
1075 for (i = 0; i < priv->profile->max_tc; i++)
1076 priv->channeltc_to_txq_map[ix][i] =
1077 ix + i * priv->params.num_channels;
1078 }
1079
1080 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1081 struct mlx5e_sq *sq, u32 rate)
1082 {
1083 struct mlx5e_priv *priv = netdev_priv(dev);
1084 struct mlx5_core_dev *mdev = priv->mdev;
1085 u16 rl_index = 0;
1086 int err;
1087
1088 if (rate == sq->rate_limit)
1089 /* nothing to do */
1090 return 0;
1091
1092 if (sq->rate_limit)
1093 /* remove current rl index to free space to next ones */
1094 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1095
1096 sq->rate_limit = 0;
1097
1098 if (rate) {
1099 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1100 if (err) {
1101 netdev_err(dev, "Failed configuring rate %u: %d\n",
1102 rate, err);
1103 return err;
1104 }
1105 }
1106
1107 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1108 MLX5_SQC_STATE_RDY, true, rl_index);
1109 if (err) {
1110 netdev_err(dev, "Failed configuring rate %u: %d\n",
1111 rate, err);
1112 /* remove the rate from the table */
1113 if (rate)
1114 mlx5_rl_remove_rate(mdev, rate);
1115 return err;
1116 }
1117
1118 sq->rate_limit = rate;
1119 return 0;
1120 }
1121
1122 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1123 {
1124 struct mlx5e_priv *priv = netdev_priv(dev);
1125 struct mlx5_core_dev *mdev = priv->mdev;
1126 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1127 int err = 0;
1128
1129 if (!mlx5_rl_is_supported(mdev)) {
1130 netdev_err(dev, "Rate limiting is not supported on this device\n");
1131 return -EINVAL;
1132 }
1133
1134 /* rate is given in Mb/sec, HW config is in Kb/sec */
1135 rate = rate << 10;
1136
1137 /* Check whether rate in valid range, 0 is always valid */
1138 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1139 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1140 return -ERANGE;
1141 }
1142
1143 mutex_lock(&priv->state_lock);
1144 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1145 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1146 if (!err)
1147 priv->tx_rates[index] = rate;
1148 mutex_unlock(&priv->state_lock);
1149
1150 return err;
1151 }
1152
1153 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1154 struct mlx5e_channel_param *cparam,
1155 struct mlx5e_channel **cp)
1156 {
1157 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1158 struct net_device *netdev = priv->netdev;
1159 struct mlx5e_cq_moder rx_cq_profile;
1160 int cpu = mlx5e_get_cpu(priv, ix);
1161 struct mlx5e_channel *c;
1162 struct mlx5e_sq *sq;
1163 int err;
1164 int i;
1165
1166 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1167 if (!c)
1168 return -ENOMEM;
1169
1170 c->priv = priv;
1171 c->ix = ix;
1172 c->cpu = cpu;
1173 c->pdev = &priv->mdev->pdev->dev;
1174 c->netdev = priv->netdev;
1175 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1176 c->num_tc = priv->params.num_tc;
1177
1178 if (priv->params.rx_am_enabled)
1179 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1180 else
1181 rx_cq_profile = priv->params.rx_cq_moderation;
1182
1183 mlx5e_build_channeltc_to_txq_map(priv, ix);
1184
1185 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1186
1187 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1188 if (err)
1189 goto err_napi_del;
1190
1191 err = mlx5e_open_tx_cqs(c, cparam);
1192 if (err)
1193 goto err_close_icosq_cq;
1194
1195 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1196 rx_cq_profile);
1197 if (err)
1198 goto err_close_tx_cqs;
1199
1200 napi_enable(&c->napi);
1201
1202 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1203 if (err)
1204 goto err_disable_napi;
1205
1206 err = mlx5e_open_sqs(c, cparam);
1207 if (err)
1208 goto err_close_icosq;
1209
1210 for (i = 0; i < priv->params.num_tc; i++) {
1211 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1212
1213 if (priv->tx_rates[txq_ix]) {
1214 sq = priv->txq_to_sq_map[txq_ix];
1215 mlx5e_set_sq_maxrate(priv->netdev, sq,
1216 priv->tx_rates[txq_ix]);
1217 }
1218 }
1219
1220 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1221 if (err)
1222 goto err_close_sqs;
1223
1224 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1225 *cp = c;
1226
1227 return 0;
1228
1229 err_close_sqs:
1230 mlx5e_close_sqs(c);
1231
1232 err_close_icosq:
1233 mlx5e_close_sq(&c->icosq);
1234
1235 err_disable_napi:
1236 napi_disable(&c->napi);
1237 mlx5e_close_cq(&c->rq.cq);
1238
1239 err_close_tx_cqs:
1240 mlx5e_close_tx_cqs(c);
1241
1242 err_close_icosq_cq:
1243 mlx5e_close_cq(&c->icosq.cq);
1244
1245 err_napi_del:
1246 netif_napi_del(&c->napi);
1247 napi_hash_del(&c->napi);
1248 kfree(c);
1249
1250 return err;
1251 }
1252
1253 static void mlx5e_close_channel(struct mlx5e_channel *c)
1254 {
1255 mlx5e_close_rq(&c->rq);
1256 mlx5e_close_sqs(c);
1257 mlx5e_close_sq(&c->icosq);
1258 napi_disable(&c->napi);
1259 mlx5e_close_cq(&c->rq.cq);
1260 mlx5e_close_tx_cqs(c);
1261 mlx5e_close_cq(&c->icosq.cq);
1262 netif_napi_del(&c->napi);
1263
1264 napi_hash_del(&c->napi);
1265 synchronize_rcu();
1266
1267 kfree(c);
1268 }
1269
1270 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1271 struct mlx5e_rq_param *param)
1272 {
1273 void *rqc = param->rqc;
1274 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1275
1276 switch (priv->params.rq_wq_type) {
1277 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1278 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1279 priv->params.mpwqe_log_num_strides - 9);
1280 MLX5_SET(wq, wq, log_wqe_stride_size,
1281 priv->params.mpwqe_log_stride_sz - 6);
1282 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1283 break;
1284 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1285 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1286 }
1287
1288 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1289 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1290 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1291 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1292 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1293
1294 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1295 param->wq.linear = 1;
1296
1297 param->am_enabled = priv->params.rx_am_enabled;
1298 }
1299
1300 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1301 {
1302 void *rqc = param->rqc;
1303 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1304
1305 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1306 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1307 }
1308
1309 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1310 struct mlx5e_sq_param *param)
1311 {
1312 void *sqc = param->sqc;
1313 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1314
1315 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1316 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1317
1318 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1319 }
1320
1321 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1322 struct mlx5e_sq_param *param)
1323 {
1324 void *sqc = param->sqc;
1325 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1326
1327 mlx5e_build_sq_param_common(priv, param);
1328 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1329
1330 param->max_inline = priv->params.tx_max_inline;
1331 param->min_inline_mode = priv->params.tx_min_inline_mode;
1332 }
1333
1334 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1335 struct mlx5e_cq_param *param)
1336 {
1337 void *cqc = param->cqc;
1338
1339 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1340 }
1341
1342 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1343 struct mlx5e_cq_param *param)
1344 {
1345 void *cqc = param->cqc;
1346 u8 log_cq_size;
1347
1348 switch (priv->params.rq_wq_type) {
1349 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1350 log_cq_size = priv->params.log_rq_size +
1351 priv->params.mpwqe_log_num_strides;
1352 break;
1353 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1354 log_cq_size = priv->params.log_rq_size;
1355 }
1356
1357 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1358 if (priv->params.rx_cqe_compress) {
1359 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1360 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1361 }
1362
1363 mlx5e_build_common_cq_param(priv, param);
1364
1365 param->cq_period_mode = priv->params.rx_cq_period_mode;
1366 }
1367
1368 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1369 struct mlx5e_cq_param *param)
1370 {
1371 void *cqc = param->cqc;
1372
1373 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1374
1375 mlx5e_build_common_cq_param(priv, param);
1376
1377 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1378 }
1379
1380 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1381 struct mlx5e_cq_param *param,
1382 u8 log_wq_size)
1383 {
1384 void *cqc = param->cqc;
1385
1386 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1387
1388 mlx5e_build_common_cq_param(priv, param);
1389
1390 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1391 }
1392
1393 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1394 struct mlx5e_sq_param *param,
1395 u8 log_wq_size)
1396 {
1397 void *sqc = param->sqc;
1398 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1399
1400 mlx5e_build_sq_param_common(priv, param);
1401
1402 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1403 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1404
1405 param->icosq = true;
1406 }
1407
1408 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1409 {
1410 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1411
1412 mlx5e_build_rq_param(priv, &cparam->rq);
1413 mlx5e_build_sq_param(priv, &cparam->sq);
1414 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1415 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1416 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1417 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1418 }
1419
1420 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1421 {
1422 struct mlx5e_channel_param *cparam;
1423 int nch = priv->params.num_channels;
1424 int err = -ENOMEM;
1425 int i;
1426 int j;
1427
1428 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1429 GFP_KERNEL);
1430
1431 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1432 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1433
1434 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1435
1436 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1437 goto err_free_txq_to_sq_map;
1438
1439 mlx5e_build_channel_param(priv, cparam);
1440
1441 for (i = 0; i < nch; i++) {
1442 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1443 if (err)
1444 goto err_close_channels;
1445 }
1446
1447 for (j = 0; j < nch; j++) {
1448 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1449 if (err)
1450 goto err_close_channels;
1451 }
1452
1453 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1454 * polling for inactive tx queues.
1455 */
1456 netif_tx_start_all_queues(priv->netdev);
1457
1458 kfree(cparam);
1459 return 0;
1460
1461 err_close_channels:
1462 for (i--; i >= 0; i--)
1463 mlx5e_close_channel(priv->channel[i]);
1464
1465 err_free_txq_to_sq_map:
1466 kfree(priv->txq_to_sq_map);
1467 kfree(priv->channel);
1468 kfree(cparam);
1469
1470 return err;
1471 }
1472
1473 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1474 {
1475 int i;
1476
1477 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1478 * polling for inactive tx queues.
1479 */
1480 netif_tx_stop_all_queues(priv->netdev);
1481 netif_tx_disable(priv->netdev);
1482
1483 for (i = 0; i < priv->params.num_channels; i++)
1484 mlx5e_close_channel(priv->channel[i]);
1485
1486 kfree(priv->txq_to_sq_map);
1487 kfree(priv->channel);
1488 }
1489
1490 static int mlx5e_rx_hash_fn(int hfunc)
1491 {
1492 return (hfunc == ETH_RSS_HASH_TOP) ?
1493 MLX5_RX_HASH_FN_TOEPLITZ :
1494 MLX5_RX_HASH_FN_INVERTED_XOR8;
1495 }
1496
1497 static int mlx5e_bits_invert(unsigned long a, int size)
1498 {
1499 int inv = 0;
1500 int i;
1501
1502 for (i = 0; i < size; i++)
1503 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1504
1505 return inv;
1506 }
1507
1508 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1509 {
1510 int i;
1511
1512 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1513 int ix = i;
1514 u32 rqn;
1515
1516 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1517 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1518
1519 ix = priv->params.indirection_rqt[ix];
1520 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1521 priv->channel[ix]->rq.rqn :
1522 priv->drop_rq.rqn;
1523 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1524 }
1525 }
1526
1527 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1528 int ix)
1529 {
1530 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1531 priv->channel[ix]->rq.rqn :
1532 priv->drop_rq.rqn;
1533
1534 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1535 }
1536
1537 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1538 int ix, struct mlx5e_rqt *rqt)
1539 {
1540 struct mlx5_core_dev *mdev = priv->mdev;
1541 void *rqtc;
1542 int inlen;
1543 int err;
1544 u32 *in;
1545
1546 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1547 in = mlx5_vzalloc(inlen);
1548 if (!in)
1549 return -ENOMEM;
1550
1551 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1552
1553 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1554 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1555
1556 if (sz > 1) /* RSS */
1557 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1558 else
1559 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1560
1561 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1562 if (!err)
1563 rqt->enabled = true;
1564
1565 kvfree(in);
1566 return err;
1567 }
1568
1569 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1570 {
1571 rqt->enabled = false;
1572 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1573 }
1574
1575 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1576 {
1577 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1578
1579 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1580 }
1581
1582 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1583 {
1584 struct mlx5e_rqt *rqt;
1585 int err;
1586 int ix;
1587
1588 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1589 rqt = &priv->direct_tir[ix].rqt;
1590 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1591 if (err)
1592 goto err_destroy_rqts;
1593 }
1594
1595 return 0;
1596
1597 err_destroy_rqts:
1598 for (ix--; ix >= 0; ix--)
1599 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1600
1601 return err;
1602 }
1603
1604 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1605 {
1606 struct mlx5_core_dev *mdev = priv->mdev;
1607 void *rqtc;
1608 int inlen;
1609 u32 *in;
1610 int err;
1611
1612 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1613 in = mlx5_vzalloc(inlen);
1614 if (!in)
1615 return -ENOMEM;
1616
1617 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1618
1619 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1620 if (sz > 1) /* RSS */
1621 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1622 else
1623 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1624
1625 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1626
1627 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1628
1629 kvfree(in);
1630
1631 return err;
1632 }
1633
1634 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1635 {
1636 u32 rqtn;
1637 int ix;
1638
1639 if (priv->indir_rqt.enabled) {
1640 rqtn = priv->indir_rqt.rqtn;
1641 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1642 }
1643
1644 for (ix = 0; ix < priv->params.num_channels; ix++) {
1645 if (!priv->direct_tir[ix].rqt.enabled)
1646 continue;
1647 rqtn = priv->direct_tir[ix].rqt.rqtn;
1648 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1649 }
1650 }
1651
1652 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1653 {
1654 if (!priv->params.lro_en)
1655 return;
1656
1657 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1658
1659 MLX5_SET(tirc, tirc, lro_enable_mask,
1660 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1661 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1662 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1663 (priv->params.lro_wqe_sz -
1664 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1665 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1666 MLX5_CAP_ETH(priv->mdev,
1667 lro_timer_supported_periods[2]));
1668 }
1669
1670 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1671 {
1672 MLX5_SET(tirc, tirc, rx_hash_fn,
1673 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1674 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1675 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1676 rx_hash_toeplitz_key);
1677 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1678 rx_hash_toeplitz_key);
1679
1680 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1681 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1682 }
1683 }
1684
1685 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1686 {
1687 struct mlx5_core_dev *mdev = priv->mdev;
1688
1689 void *in;
1690 void *tirc;
1691 int inlen;
1692 int err;
1693 int tt;
1694 int ix;
1695
1696 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1697 in = mlx5_vzalloc(inlen);
1698 if (!in)
1699 return -ENOMEM;
1700
1701 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1702 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1703
1704 mlx5e_build_tir_ctx_lro(tirc, priv);
1705
1706 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1707 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1708 inlen);
1709 if (err)
1710 goto free_in;
1711 }
1712
1713 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1714 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1715 in, inlen);
1716 if (err)
1717 goto free_in;
1718 }
1719
1720 free_in:
1721 kvfree(in);
1722
1723 return err;
1724 }
1725
1726 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1727 {
1728 struct mlx5_core_dev *mdev = priv->mdev;
1729 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1730 int err;
1731
1732 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1733 if (err)
1734 return err;
1735
1736 /* Update vport context MTU */
1737 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1738 return 0;
1739 }
1740
1741 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1742 {
1743 struct mlx5_core_dev *mdev = priv->mdev;
1744 u16 hw_mtu = 0;
1745 int err;
1746
1747 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1748 if (err || !hw_mtu) /* fallback to port oper mtu */
1749 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1750
1751 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1752 }
1753
1754 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1755 {
1756 struct mlx5e_priv *priv = netdev_priv(netdev);
1757 u16 mtu;
1758 int err;
1759
1760 err = mlx5e_set_mtu(priv, netdev->mtu);
1761 if (err)
1762 return err;
1763
1764 mlx5e_query_mtu(priv, &mtu);
1765 if (mtu != netdev->mtu)
1766 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1767 __func__, mtu, netdev->mtu);
1768
1769 netdev->mtu = mtu;
1770 return 0;
1771 }
1772
1773 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1774 {
1775 struct mlx5e_priv *priv = netdev_priv(netdev);
1776 int nch = priv->params.num_channels;
1777 int ntc = priv->params.num_tc;
1778 int tc;
1779
1780 netdev_reset_tc(netdev);
1781
1782 if (ntc == 1)
1783 return;
1784
1785 netdev_set_num_tc(netdev, ntc);
1786
1787 /* Map netdev TCs to offset 0
1788 * We have our own UP to TXQ mapping for QoS
1789 */
1790 for (tc = 0; tc < ntc; tc++)
1791 netdev_set_tc_queue(netdev, tc, nch, 0);
1792 }
1793
1794 int mlx5e_open_locked(struct net_device *netdev)
1795 {
1796 struct mlx5e_priv *priv = netdev_priv(netdev);
1797 struct mlx5_core_dev *mdev = priv->mdev;
1798 int num_txqs;
1799 int err;
1800
1801 set_bit(MLX5E_STATE_OPENED, &priv->state);
1802
1803 mlx5e_netdev_set_tcs(netdev);
1804
1805 num_txqs = priv->params.num_channels * priv->params.num_tc;
1806 netif_set_real_num_tx_queues(netdev, num_txqs);
1807 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1808
1809 err = mlx5e_open_channels(priv);
1810 if (err) {
1811 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1812 __func__, err);
1813 goto err_clear_state_opened_flag;
1814 }
1815
1816 err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
1817 if (err) {
1818 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1819 __func__, err);
1820 goto err_close_channels;
1821 }
1822
1823 mlx5e_redirect_rqts(priv);
1824 mlx5e_update_carrier(priv);
1825 mlx5e_timestamp_init(priv);
1826 #ifdef CONFIG_RFS_ACCEL
1827 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1828 #endif
1829 if (priv->profile->update_stats)
1830 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1831
1832 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
1833 err = mlx5e_add_sqs_fwd_rules(priv);
1834 if (err)
1835 goto err_close_channels;
1836 }
1837 return 0;
1838
1839 err_close_channels:
1840 mlx5e_close_channels(priv);
1841 err_clear_state_opened_flag:
1842 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1843 return err;
1844 }
1845
1846 int mlx5e_open(struct net_device *netdev)
1847 {
1848 struct mlx5e_priv *priv = netdev_priv(netdev);
1849 int err;
1850
1851 mutex_lock(&priv->state_lock);
1852 err = mlx5e_open_locked(netdev);
1853 mutex_unlock(&priv->state_lock);
1854
1855 return err;
1856 }
1857
1858 int mlx5e_close_locked(struct net_device *netdev)
1859 {
1860 struct mlx5e_priv *priv = netdev_priv(netdev);
1861 struct mlx5_core_dev *mdev = priv->mdev;
1862
1863 /* May already be CLOSED in case a previous configuration operation
1864 * (e.g RX/TX queue size change) that involves close&open failed.
1865 */
1866 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1867 return 0;
1868
1869 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1870
1871 if (MLX5_CAP_GEN(mdev, vport_group_manager))
1872 mlx5e_remove_sqs_fwd_rules(priv);
1873
1874 mlx5e_timestamp_cleanup(priv);
1875 netif_carrier_off(priv->netdev);
1876 mlx5e_redirect_rqts(priv);
1877 mlx5e_close_channels(priv);
1878
1879 return 0;
1880 }
1881
1882 int mlx5e_close(struct net_device *netdev)
1883 {
1884 struct mlx5e_priv *priv = netdev_priv(netdev);
1885 int err;
1886
1887 mutex_lock(&priv->state_lock);
1888 err = mlx5e_close_locked(netdev);
1889 mutex_unlock(&priv->state_lock);
1890
1891 return err;
1892 }
1893
1894 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1895 struct mlx5e_rq *rq,
1896 struct mlx5e_rq_param *param)
1897 {
1898 struct mlx5_core_dev *mdev = priv->mdev;
1899 void *rqc = param->rqc;
1900 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1901 int err;
1902
1903 param->wq.db_numa_node = param->wq.buf_numa_node;
1904
1905 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1906 &rq->wq_ctrl);
1907 if (err)
1908 return err;
1909
1910 rq->priv = priv;
1911
1912 return 0;
1913 }
1914
1915 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1916 struct mlx5e_cq *cq,
1917 struct mlx5e_cq_param *param)
1918 {
1919 struct mlx5_core_dev *mdev = priv->mdev;
1920 struct mlx5_core_cq *mcq = &cq->mcq;
1921 int eqn_not_used;
1922 unsigned int irqn;
1923 int err;
1924
1925 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1926 &cq->wq_ctrl);
1927 if (err)
1928 return err;
1929
1930 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1931
1932 mcq->cqe_sz = 64;
1933 mcq->set_ci_db = cq->wq_ctrl.db.db;
1934 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1935 *mcq->set_ci_db = 0;
1936 *mcq->arm_db = 0;
1937 mcq->vector = param->eq_ix;
1938 mcq->comp = mlx5e_completion_event;
1939 mcq->event = mlx5e_cq_error_event;
1940 mcq->irqn = irqn;
1941 mcq->uar = &mdev->mlx5e_res.cq_uar;
1942
1943 cq->priv = priv;
1944
1945 return 0;
1946 }
1947
1948 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1949 {
1950 struct mlx5e_cq_param cq_param;
1951 struct mlx5e_rq_param rq_param;
1952 struct mlx5e_rq *rq = &priv->drop_rq;
1953 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1954 int err;
1955
1956 memset(&cq_param, 0, sizeof(cq_param));
1957 memset(&rq_param, 0, sizeof(rq_param));
1958 mlx5e_build_drop_rq_param(&rq_param);
1959
1960 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1961 if (err)
1962 return err;
1963
1964 err = mlx5e_enable_cq(cq, &cq_param);
1965 if (err)
1966 goto err_destroy_cq;
1967
1968 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1969 if (err)
1970 goto err_disable_cq;
1971
1972 err = mlx5e_enable_rq(rq, &rq_param);
1973 if (err)
1974 goto err_destroy_rq;
1975
1976 return 0;
1977
1978 err_destroy_rq:
1979 mlx5e_destroy_rq(&priv->drop_rq);
1980
1981 err_disable_cq:
1982 mlx5e_disable_cq(&priv->drop_rq.cq);
1983
1984 err_destroy_cq:
1985 mlx5e_destroy_cq(&priv->drop_rq.cq);
1986
1987 return err;
1988 }
1989
1990 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1991 {
1992 mlx5e_disable_rq(&priv->drop_rq);
1993 mlx5e_destroy_rq(&priv->drop_rq);
1994 mlx5e_disable_cq(&priv->drop_rq.cq);
1995 mlx5e_destroy_cq(&priv->drop_rq.cq);
1996 }
1997
1998 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1999 {
2000 struct mlx5_core_dev *mdev = priv->mdev;
2001 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2002 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2003
2004 memset(in, 0, sizeof(in));
2005
2006 MLX5_SET(tisc, tisc, prio, tc << 1);
2007 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2008
2009 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2010 }
2011
2012 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2013 {
2014 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2015 }
2016
2017 int mlx5e_create_tises(struct mlx5e_priv *priv)
2018 {
2019 int err;
2020 int tc;
2021
2022 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2023 err = mlx5e_create_tis(priv, tc);
2024 if (err)
2025 goto err_close_tises;
2026 }
2027
2028 return 0;
2029
2030 err_close_tises:
2031 for (tc--; tc >= 0; tc--)
2032 mlx5e_destroy_tis(priv, tc);
2033
2034 return err;
2035 }
2036
2037 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2038 {
2039 int tc;
2040
2041 for (tc = 0; tc < priv->profile->max_tc; tc++)
2042 mlx5e_destroy_tis(priv, tc);
2043 }
2044
2045 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2046 enum mlx5e_traffic_types tt)
2047 {
2048 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2049
2050 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2051
2052 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2053 MLX5_HASH_FIELD_SEL_DST_IP)
2054
2055 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2056 MLX5_HASH_FIELD_SEL_DST_IP |\
2057 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2058 MLX5_HASH_FIELD_SEL_L4_DPORT)
2059
2060 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2061 MLX5_HASH_FIELD_SEL_DST_IP |\
2062 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2063
2064 mlx5e_build_tir_ctx_lro(tirc, priv);
2065
2066 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2067 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2068 mlx5e_build_tir_ctx_hash(tirc, priv);
2069
2070 switch (tt) {
2071 case MLX5E_TT_IPV4_TCP:
2072 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2073 MLX5_L3_PROT_TYPE_IPV4);
2074 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2075 MLX5_L4_PROT_TYPE_TCP);
2076 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2077 MLX5_HASH_IP_L4PORTS);
2078 break;
2079
2080 case MLX5E_TT_IPV6_TCP:
2081 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2082 MLX5_L3_PROT_TYPE_IPV6);
2083 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2084 MLX5_L4_PROT_TYPE_TCP);
2085 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2086 MLX5_HASH_IP_L4PORTS);
2087 break;
2088
2089 case MLX5E_TT_IPV4_UDP:
2090 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2091 MLX5_L3_PROT_TYPE_IPV4);
2092 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2093 MLX5_L4_PROT_TYPE_UDP);
2094 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2095 MLX5_HASH_IP_L4PORTS);
2096 break;
2097
2098 case MLX5E_TT_IPV6_UDP:
2099 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2100 MLX5_L3_PROT_TYPE_IPV6);
2101 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2102 MLX5_L4_PROT_TYPE_UDP);
2103 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2104 MLX5_HASH_IP_L4PORTS);
2105 break;
2106
2107 case MLX5E_TT_IPV4_IPSEC_AH:
2108 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2109 MLX5_L3_PROT_TYPE_IPV4);
2110 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2111 MLX5_HASH_IP_IPSEC_SPI);
2112 break;
2113
2114 case MLX5E_TT_IPV6_IPSEC_AH:
2115 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2116 MLX5_L3_PROT_TYPE_IPV6);
2117 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2118 MLX5_HASH_IP_IPSEC_SPI);
2119 break;
2120
2121 case MLX5E_TT_IPV4_IPSEC_ESP:
2122 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2123 MLX5_L3_PROT_TYPE_IPV4);
2124 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2125 MLX5_HASH_IP_IPSEC_SPI);
2126 break;
2127
2128 case MLX5E_TT_IPV6_IPSEC_ESP:
2129 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2130 MLX5_L3_PROT_TYPE_IPV6);
2131 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2132 MLX5_HASH_IP_IPSEC_SPI);
2133 break;
2134
2135 case MLX5E_TT_IPV4:
2136 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2137 MLX5_L3_PROT_TYPE_IPV4);
2138 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2139 MLX5_HASH_IP);
2140 break;
2141
2142 case MLX5E_TT_IPV6:
2143 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2144 MLX5_L3_PROT_TYPE_IPV6);
2145 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2146 MLX5_HASH_IP);
2147 break;
2148 default:
2149 WARN_ONCE(true,
2150 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2151 }
2152 }
2153
2154 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2155 u32 rqtn)
2156 {
2157 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2158
2159 mlx5e_build_tir_ctx_lro(tirc, priv);
2160
2161 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2162 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2163 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2164 }
2165
2166 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2167 {
2168 struct mlx5e_tir *tir;
2169 void *tirc;
2170 int inlen;
2171 int err;
2172 u32 *in;
2173 int tt;
2174
2175 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2176 in = mlx5_vzalloc(inlen);
2177 if (!in)
2178 return -ENOMEM;
2179
2180 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2181 memset(in, 0, inlen);
2182 tir = &priv->indir_tir[tt];
2183 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2184 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2185 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2186 if (err)
2187 goto err_destroy_tirs;
2188 }
2189
2190 kvfree(in);
2191
2192 return 0;
2193
2194 err_destroy_tirs:
2195 for (tt--; tt >= 0; tt--)
2196 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2197
2198 kvfree(in);
2199
2200 return err;
2201 }
2202
2203 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2204 {
2205 int nch = priv->profile->max_nch(priv->mdev);
2206 struct mlx5e_tir *tir;
2207 void *tirc;
2208 int inlen;
2209 int err;
2210 u32 *in;
2211 int ix;
2212
2213 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2214 in = mlx5_vzalloc(inlen);
2215 if (!in)
2216 return -ENOMEM;
2217
2218 for (ix = 0; ix < nch; ix++) {
2219 memset(in, 0, inlen);
2220 tir = &priv->direct_tir[ix];
2221 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2222 mlx5e_build_direct_tir_ctx(priv, tirc,
2223 priv->direct_tir[ix].rqt.rqtn);
2224 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2225 if (err)
2226 goto err_destroy_ch_tirs;
2227 }
2228
2229 kvfree(in);
2230
2231 return 0;
2232
2233 err_destroy_ch_tirs:
2234 for (ix--; ix >= 0; ix--)
2235 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2236
2237 kvfree(in);
2238
2239 return err;
2240 }
2241
2242 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2243 {
2244 int i;
2245
2246 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2247 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2248 }
2249
2250 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2251 {
2252 int nch = priv->profile->max_nch(priv->mdev);
2253 int i;
2254
2255 for (i = 0; i < nch; i++)
2256 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2257 }
2258
2259 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2260 {
2261 int err = 0;
2262 int i;
2263
2264 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2265 return 0;
2266
2267 for (i = 0; i < priv->params.num_channels; i++) {
2268 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2269 if (err)
2270 return err;
2271 }
2272
2273 return 0;
2274 }
2275
2276 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2277 {
2278 struct mlx5e_priv *priv = netdev_priv(netdev);
2279 bool was_opened;
2280 int err = 0;
2281
2282 if (tc && tc != MLX5E_MAX_NUM_TC)
2283 return -EINVAL;
2284
2285 mutex_lock(&priv->state_lock);
2286
2287 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2288 if (was_opened)
2289 mlx5e_close_locked(priv->netdev);
2290
2291 priv->params.num_tc = tc ? tc : 1;
2292
2293 if (was_opened)
2294 err = mlx5e_open_locked(priv->netdev);
2295
2296 mutex_unlock(&priv->state_lock);
2297
2298 return err;
2299 }
2300
2301 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2302 __be16 proto, struct tc_to_netdev *tc)
2303 {
2304 struct mlx5e_priv *priv = netdev_priv(dev);
2305
2306 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2307 goto mqprio;
2308
2309 switch (tc->type) {
2310 case TC_SETUP_CLSFLOWER:
2311 switch (tc->cls_flower->command) {
2312 case TC_CLSFLOWER_REPLACE:
2313 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2314 case TC_CLSFLOWER_DESTROY:
2315 return mlx5e_delete_flower(priv, tc->cls_flower);
2316 case TC_CLSFLOWER_STATS:
2317 return mlx5e_stats_flower(priv, tc->cls_flower);
2318 }
2319 default:
2320 return -EOPNOTSUPP;
2321 }
2322
2323 mqprio:
2324 if (tc->type != TC_SETUP_MQPRIO)
2325 return -EINVAL;
2326
2327 return mlx5e_setup_tc(dev, tc->tc);
2328 }
2329
2330 struct rtnl_link_stats64 *
2331 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2332 {
2333 struct mlx5e_priv *priv = netdev_priv(dev);
2334 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2335 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2336 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2337
2338 stats->rx_packets = sstats->rx_packets;
2339 stats->rx_bytes = sstats->rx_bytes;
2340 stats->tx_packets = sstats->tx_packets;
2341 stats->tx_bytes = sstats->tx_bytes;
2342
2343 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2344 stats->tx_dropped = sstats->tx_queue_dropped;
2345
2346 stats->rx_length_errors =
2347 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2348 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2349 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2350 stats->rx_crc_errors =
2351 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2352 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2353 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2354 stats->tx_carrier_errors =
2355 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2356 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2357 stats->rx_frame_errors;
2358 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2359
2360 /* vport multicast also counts packets that are dropped due to steering
2361 * or rx out of buffer
2362 */
2363 stats->multicast =
2364 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2365
2366 return stats;
2367 }
2368
2369 static void mlx5e_set_rx_mode(struct net_device *dev)
2370 {
2371 struct mlx5e_priv *priv = netdev_priv(dev);
2372
2373 queue_work(priv->wq, &priv->set_rx_mode_work);
2374 }
2375
2376 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2377 {
2378 struct mlx5e_priv *priv = netdev_priv(netdev);
2379 struct sockaddr *saddr = addr;
2380
2381 if (!is_valid_ether_addr(saddr->sa_data))
2382 return -EADDRNOTAVAIL;
2383
2384 netif_addr_lock_bh(netdev);
2385 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2386 netif_addr_unlock_bh(netdev);
2387
2388 queue_work(priv->wq, &priv->set_rx_mode_work);
2389
2390 return 0;
2391 }
2392
2393 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2394 do { \
2395 if (enable) \
2396 netdev->features |= feature; \
2397 else \
2398 netdev->features &= ~feature; \
2399 } while (0)
2400
2401 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2402
2403 static int set_feature_lro(struct net_device *netdev, bool enable)
2404 {
2405 struct mlx5e_priv *priv = netdev_priv(netdev);
2406 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2407 int err;
2408
2409 mutex_lock(&priv->state_lock);
2410
2411 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2412 mlx5e_close_locked(priv->netdev);
2413
2414 priv->params.lro_en = enable;
2415 err = mlx5e_modify_tirs_lro(priv);
2416 if (err) {
2417 netdev_err(netdev, "lro modify failed, %d\n", err);
2418 priv->params.lro_en = !enable;
2419 }
2420
2421 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2422 mlx5e_open_locked(priv->netdev);
2423
2424 mutex_unlock(&priv->state_lock);
2425
2426 return err;
2427 }
2428
2429 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2430 {
2431 struct mlx5e_priv *priv = netdev_priv(netdev);
2432
2433 if (enable)
2434 mlx5e_enable_vlan_filter(priv);
2435 else
2436 mlx5e_disable_vlan_filter(priv);
2437
2438 return 0;
2439 }
2440
2441 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2442 {
2443 struct mlx5e_priv *priv = netdev_priv(netdev);
2444
2445 if (!enable && mlx5e_tc_num_filters(priv)) {
2446 netdev_err(netdev,
2447 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2448 return -EINVAL;
2449 }
2450
2451 return 0;
2452 }
2453
2454 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2455 {
2456 struct mlx5e_priv *priv = netdev_priv(netdev);
2457 struct mlx5_core_dev *mdev = priv->mdev;
2458
2459 return mlx5_set_port_fcs(mdev, !enable);
2460 }
2461
2462 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2463 {
2464 struct mlx5e_priv *priv = netdev_priv(netdev);
2465 int err;
2466
2467 mutex_lock(&priv->state_lock);
2468
2469 priv->params.vlan_strip_disable = !enable;
2470 err = mlx5e_modify_rqs_vsd(priv, !enable);
2471 if (err)
2472 priv->params.vlan_strip_disable = enable;
2473
2474 mutex_unlock(&priv->state_lock);
2475
2476 return err;
2477 }
2478
2479 #ifdef CONFIG_RFS_ACCEL
2480 static int set_feature_arfs(struct net_device *netdev, bool enable)
2481 {
2482 struct mlx5e_priv *priv = netdev_priv(netdev);
2483 int err;
2484
2485 if (enable)
2486 err = mlx5e_arfs_enable(priv);
2487 else
2488 err = mlx5e_arfs_disable(priv);
2489
2490 return err;
2491 }
2492 #endif
2493
2494 static int mlx5e_handle_feature(struct net_device *netdev,
2495 netdev_features_t wanted_features,
2496 netdev_features_t feature,
2497 mlx5e_feature_handler feature_handler)
2498 {
2499 netdev_features_t changes = wanted_features ^ netdev->features;
2500 bool enable = !!(wanted_features & feature);
2501 int err;
2502
2503 if (!(changes & feature))
2504 return 0;
2505
2506 err = feature_handler(netdev, enable);
2507 if (err) {
2508 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2509 enable ? "Enable" : "Disable", feature, err);
2510 return err;
2511 }
2512
2513 MLX5E_SET_FEATURE(netdev, feature, enable);
2514 return 0;
2515 }
2516
2517 static int mlx5e_set_features(struct net_device *netdev,
2518 netdev_features_t features)
2519 {
2520 int err;
2521
2522 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2523 set_feature_lro);
2524 err |= mlx5e_handle_feature(netdev, features,
2525 NETIF_F_HW_VLAN_CTAG_FILTER,
2526 set_feature_vlan_filter);
2527 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2528 set_feature_tc_num_filters);
2529 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2530 set_feature_rx_all);
2531 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2532 set_feature_rx_vlan);
2533 #ifdef CONFIG_RFS_ACCEL
2534 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2535 set_feature_arfs);
2536 #endif
2537
2538 return err ? -EINVAL : 0;
2539 }
2540
2541 #define MXL5_HW_MIN_MTU 64
2542 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2543
2544 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2545 {
2546 struct mlx5e_priv *priv = netdev_priv(netdev);
2547 struct mlx5_core_dev *mdev = priv->mdev;
2548 bool was_opened;
2549 u16 max_mtu;
2550 u16 min_mtu;
2551 int err = 0;
2552 bool reset;
2553
2554 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2555
2556 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2557 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2558
2559 if (new_mtu > max_mtu || new_mtu < min_mtu) {
2560 netdev_err(netdev,
2561 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2562 __func__, new_mtu, min_mtu, max_mtu);
2563 return -EINVAL;
2564 }
2565
2566 mutex_lock(&priv->state_lock);
2567
2568 reset = !priv->params.lro_en &&
2569 (priv->params.rq_wq_type !=
2570 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2571
2572 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2573 if (was_opened && reset)
2574 mlx5e_close_locked(netdev);
2575
2576 netdev->mtu = new_mtu;
2577 mlx5e_set_dev_port_mtu(netdev);
2578
2579 if (was_opened && reset)
2580 err = mlx5e_open_locked(netdev);
2581
2582 mutex_unlock(&priv->state_lock);
2583
2584 return err;
2585 }
2586
2587 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2588 {
2589 switch (cmd) {
2590 case SIOCSHWTSTAMP:
2591 return mlx5e_hwstamp_set(dev, ifr);
2592 case SIOCGHWTSTAMP:
2593 return mlx5e_hwstamp_get(dev, ifr);
2594 default:
2595 return -EOPNOTSUPP;
2596 }
2597 }
2598
2599 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2600 {
2601 struct mlx5e_priv *priv = netdev_priv(dev);
2602 struct mlx5_core_dev *mdev = priv->mdev;
2603
2604 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2605 }
2606
2607 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2608 {
2609 struct mlx5e_priv *priv = netdev_priv(dev);
2610 struct mlx5_core_dev *mdev = priv->mdev;
2611
2612 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2613 vlan, qos);
2614 }
2615
2616 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2617 {
2618 struct mlx5e_priv *priv = netdev_priv(dev);
2619 struct mlx5_core_dev *mdev = priv->mdev;
2620
2621 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2622 }
2623
2624 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2625 {
2626 struct mlx5e_priv *priv = netdev_priv(dev);
2627 struct mlx5_core_dev *mdev = priv->mdev;
2628
2629 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2630 }
2631 static int mlx5_vport_link2ifla(u8 esw_link)
2632 {
2633 switch (esw_link) {
2634 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2635 return IFLA_VF_LINK_STATE_DISABLE;
2636 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2637 return IFLA_VF_LINK_STATE_ENABLE;
2638 }
2639 return IFLA_VF_LINK_STATE_AUTO;
2640 }
2641
2642 static int mlx5_ifla_link2vport(u8 ifla_link)
2643 {
2644 switch (ifla_link) {
2645 case IFLA_VF_LINK_STATE_DISABLE:
2646 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2647 case IFLA_VF_LINK_STATE_ENABLE:
2648 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2649 }
2650 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2651 }
2652
2653 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2654 int link_state)
2655 {
2656 struct mlx5e_priv *priv = netdev_priv(dev);
2657 struct mlx5_core_dev *mdev = priv->mdev;
2658
2659 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2660 mlx5_ifla_link2vport(link_state));
2661 }
2662
2663 static int mlx5e_get_vf_config(struct net_device *dev,
2664 int vf, struct ifla_vf_info *ivi)
2665 {
2666 struct mlx5e_priv *priv = netdev_priv(dev);
2667 struct mlx5_core_dev *mdev = priv->mdev;
2668 int err;
2669
2670 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2671 if (err)
2672 return err;
2673 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2674 return 0;
2675 }
2676
2677 static int mlx5e_get_vf_stats(struct net_device *dev,
2678 int vf, struct ifla_vf_stats *vf_stats)
2679 {
2680 struct mlx5e_priv *priv = netdev_priv(dev);
2681 struct mlx5_core_dev *mdev = priv->mdev;
2682
2683 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2684 vf_stats);
2685 }
2686
2687 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2688 struct udp_tunnel_info *ti)
2689 {
2690 struct mlx5e_priv *priv = netdev_priv(netdev);
2691
2692 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2693 return;
2694
2695 if (!mlx5e_vxlan_allowed(priv->mdev))
2696 return;
2697
2698 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
2699 }
2700
2701 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2702 struct udp_tunnel_info *ti)
2703 {
2704 struct mlx5e_priv *priv = netdev_priv(netdev);
2705
2706 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2707 return;
2708
2709 if (!mlx5e_vxlan_allowed(priv->mdev))
2710 return;
2711
2712 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
2713 }
2714
2715 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2716 struct sk_buff *skb,
2717 netdev_features_t features)
2718 {
2719 struct udphdr *udph;
2720 u16 proto;
2721 u16 port = 0;
2722
2723 switch (vlan_get_protocol(skb)) {
2724 case htons(ETH_P_IP):
2725 proto = ip_hdr(skb)->protocol;
2726 break;
2727 case htons(ETH_P_IPV6):
2728 proto = ipv6_hdr(skb)->nexthdr;
2729 break;
2730 default:
2731 goto out;
2732 }
2733
2734 if (proto == IPPROTO_UDP) {
2735 udph = udp_hdr(skb);
2736 port = be16_to_cpu(udph->dest);
2737 }
2738
2739 /* Verify if UDP port is being offloaded by HW */
2740 if (port && mlx5e_vxlan_lookup_port(priv, port))
2741 return features;
2742
2743 out:
2744 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2745 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2746 }
2747
2748 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2749 struct net_device *netdev,
2750 netdev_features_t features)
2751 {
2752 struct mlx5e_priv *priv = netdev_priv(netdev);
2753
2754 features = vlan_features_check(skb, features);
2755 features = vxlan_features_check(skb, features);
2756
2757 /* Validate if the tunneled packet is being offloaded by HW */
2758 if (skb->encapsulation &&
2759 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2760 return mlx5e_vxlan_features_check(priv, skb, features);
2761
2762 return features;
2763 }
2764
2765 static void mlx5e_tx_timeout(struct net_device *dev)
2766 {
2767 struct mlx5e_priv *priv = netdev_priv(dev);
2768 bool sched_work = false;
2769 int i;
2770
2771 netdev_err(dev, "TX timeout detected\n");
2772
2773 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2774 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2775
2776 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
2777 continue;
2778 sched_work = true;
2779 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
2780 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2781 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2782 }
2783
2784 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2785 schedule_work(&priv->tx_timeout_work);
2786 }
2787
2788 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2789 .ndo_open = mlx5e_open,
2790 .ndo_stop = mlx5e_close,
2791 .ndo_start_xmit = mlx5e_xmit,
2792 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2793 .ndo_select_queue = mlx5e_select_queue,
2794 .ndo_get_stats64 = mlx5e_get_stats,
2795 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2796 .ndo_set_mac_address = mlx5e_set_mac,
2797 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2798 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2799 .ndo_set_features = mlx5e_set_features,
2800 .ndo_change_mtu = mlx5e_change_mtu,
2801 .ndo_do_ioctl = mlx5e_ioctl,
2802 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
2803 #ifdef CONFIG_RFS_ACCEL
2804 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2805 #endif
2806 .ndo_tx_timeout = mlx5e_tx_timeout,
2807 };
2808
2809 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2810 .ndo_open = mlx5e_open,
2811 .ndo_stop = mlx5e_close,
2812 .ndo_start_xmit = mlx5e_xmit,
2813 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2814 .ndo_select_queue = mlx5e_select_queue,
2815 .ndo_get_stats64 = mlx5e_get_stats,
2816 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2817 .ndo_set_mac_address = mlx5e_set_mac,
2818 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2819 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2820 .ndo_set_features = mlx5e_set_features,
2821 .ndo_change_mtu = mlx5e_change_mtu,
2822 .ndo_do_ioctl = mlx5e_ioctl,
2823 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
2824 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
2825 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
2826 .ndo_features_check = mlx5e_features_check,
2827 #ifdef CONFIG_RFS_ACCEL
2828 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2829 #endif
2830 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2831 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2832 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
2833 .ndo_set_vf_trust = mlx5e_set_vf_trust,
2834 .ndo_get_vf_config = mlx5e_get_vf_config,
2835 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2836 .ndo_get_vf_stats = mlx5e_get_vf_stats,
2837 .ndo_tx_timeout = mlx5e_tx_timeout,
2838 };
2839
2840 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2841 {
2842 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2843 return -ENOTSUPP;
2844 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2845 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2846 !MLX5_CAP_ETH(mdev, csum_cap) ||
2847 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2848 !MLX5_CAP_ETH(mdev, vlan_cap) ||
2849 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2850 MLX5_CAP_FLOWTABLE(mdev,
2851 flow_table_properties_nic_receive.max_ft_level)
2852 < 3) {
2853 mlx5_core_warn(mdev,
2854 "Not creating net device, some required device capabilities are missing\n");
2855 return -ENOTSUPP;
2856 }
2857 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2858 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2859 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2860 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2861
2862 return 0;
2863 }
2864
2865 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2866 {
2867 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2868
2869 return bf_buf_size -
2870 sizeof(struct mlx5e_tx_wqe) +
2871 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2872 }
2873
2874 #ifdef CONFIG_MLX5_CORE_EN_DCB
2875 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2876 {
2877 int i;
2878
2879 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2880 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2881 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2882 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2883 priv->params.ets.prio_tc[i] = i;
2884 }
2885
2886 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2887 priv->params.ets.prio_tc[0] = 1;
2888 priv->params.ets.prio_tc[1] = 0;
2889 }
2890 #endif
2891
2892 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2893 u32 *indirection_rqt, int len,
2894 int num_channels)
2895 {
2896 int node = mdev->priv.numa_node;
2897 int node_num_of_cores;
2898 int i;
2899
2900 if (node == -1)
2901 node = first_online_node;
2902
2903 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2904
2905 if (node_num_of_cores)
2906 num_channels = min_t(int, num_channels, node_num_of_cores);
2907
2908 for (i = 0; i < len; i++)
2909 indirection_rqt[i] = i % num_channels;
2910 }
2911
2912 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2913 {
2914 return MLX5_CAP_GEN(mdev, striding_rq) &&
2915 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2916 MLX5_CAP_ETH(mdev, reg_umr_sq);
2917 }
2918
2919 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2920 {
2921 enum pcie_link_width width;
2922 enum pci_bus_speed speed;
2923 int err = 0;
2924
2925 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2926 if (err)
2927 return err;
2928
2929 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2930 return -EINVAL;
2931
2932 switch (speed) {
2933 case PCIE_SPEED_2_5GT:
2934 *pci_bw = 2500 * width;
2935 break;
2936 case PCIE_SPEED_5_0GT:
2937 *pci_bw = 5000 * width;
2938 break;
2939 case PCIE_SPEED_8_0GT:
2940 *pci_bw = 8000 * width;
2941 break;
2942 default:
2943 return -EINVAL;
2944 }
2945
2946 return 0;
2947 }
2948
2949 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2950 {
2951 return (link_speed && pci_bw &&
2952 (pci_bw < 40000) && (pci_bw < link_speed));
2953 }
2954
2955 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
2956 {
2957 params->rx_cq_period_mode = cq_period_mode;
2958
2959 params->rx_cq_moderation.pkts =
2960 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2961 params->rx_cq_moderation.usec =
2962 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2963
2964 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
2965 params->rx_cq_moderation.usec =
2966 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
2967 }
2968
2969 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
2970 u8 *min_inline_mode)
2971 {
2972 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
2973 case MLX5E_INLINE_MODE_L2:
2974 *min_inline_mode = MLX5_INLINE_MODE_L2;
2975 break;
2976 case MLX5E_INLINE_MODE_VPORT_CONTEXT:
2977 mlx5_query_nic_vport_min_inline(mdev,
2978 min_inline_mode);
2979 break;
2980 case MLX5_INLINE_MODE_NOT_REQUIRED:
2981 *min_inline_mode = MLX5_INLINE_MODE_NONE;
2982 break;
2983 }
2984 }
2985
2986 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
2987 struct net_device *netdev,
2988 const struct mlx5e_profile *profile,
2989 void *ppriv)
2990 {
2991 struct mlx5e_priv *priv = netdev_priv(netdev);
2992 u32 link_speed = 0;
2993 u32 pci_bw = 0;
2994 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2995 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
2996 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2997
2998 priv->params.log_sq_size =
2999 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3000 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
3001 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
3002 MLX5_WQ_TYPE_LINKED_LIST;
3003
3004 /* set CQE compression */
3005 priv->params.rx_cqe_compress_admin = false;
3006 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3007 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3008 mlx5e_get_max_linkspeed(mdev, &link_speed);
3009 mlx5e_get_pci_bw(mdev, &pci_bw);
3010 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3011 link_speed, pci_bw);
3012 priv->params.rx_cqe_compress_admin =
3013 cqe_compress_heuristic(link_speed, pci_bw);
3014 }
3015
3016 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3017
3018 switch (priv->params.rq_wq_type) {
3019 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
3020 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
3021 priv->params.mpwqe_log_stride_sz =
3022 priv->params.rx_cqe_compress ?
3023 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
3024 MLX5_MPWRQ_LOG_STRIDE_SIZE;
3025 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
3026 priv->params.mpwqe_log_stride_sz;
3027 priv->params.lro_en = true;
3028 break;
3029 default: /* MLX5_WQ_TYPE_LINKED_LIST */
3030 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3031 }
3032
3033 mlx5_core_info(mdev,
3034 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
3035 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
3036 BIT(priv->params.log_rq_size),
3037 BIT(priv->params.mpwqe_log_stride_sz),
3038 priv->params.rx_cqe_compress_admin);
3039
3040 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
3041 BIT(priv->params.log_rq_size));
3042
3043 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3044 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3045
3046 priv->params.tx_cq_moderation.usec =
3047 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3048 priv->params.tx_cq_moderation.pkts =
3049 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3050 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3051 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3052 priv->params.num_tc = 1;
3053 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
3054
3055 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3056 sizeof(priv->params.toeplitz_hash_key));
3057
3058 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3059 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3060
3061 priv->params.lro_wqe_sz =
3062 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3063
3064 /* Initialize pflags */
3065 MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3066 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3067
3068 priv->mdev = mdev;
3069 priv->netdev = netdev;
3070 priv->params.num_channels = profile->max_nch(mdev);
3071 priv->profile = profile;
3072 priv->ppriv = ppriv;
3073
3074 #ifdef CONFIG_MLX5_CORE_EN_DCB
3075 mlx5e_ets_init(priv);
3076 #endif
3077
3078 mutex_init(&priv->state_lock);
3079
3080 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3081 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3082 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3083 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3084 }
3085
3086 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3087 {
3088 struct mlx5e_priv *priv = netdev_priv(netdev);
3089
3090 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3091 if (is_zero_ether_addr(netdev->dev_addr) &&
3092 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3093 eth_hw_addr_random(netdev);
3094 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3095 }
3096 }
3097
3098 static const struct switchdev_ops mlx5e_switchdev_ops = {
3099 .switchdev_port_attr_get = mlx5e_attr_get,
3100 };
3101
3102 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3103 {
3104 struct mlx5e_priv *priv = netdev_priv(netdev);
3105 struct mlx5_core_dev *mdev = priv->mdev;
3106 bool fcs_supported;
3107 bool fcs_enabled;
3108
3109 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3110
3111 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3112 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3113 #ifdef CONFIG_MLX5_CORE_EN_DCB
3114 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3115 #endif
3116 } else {
3117 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3118 }
3119
3120 netdev->watchdog_timeo = 15 * HZ;
3121
3122 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3123
3124 netdev->vlan_features |= NETIF_F_SG;
3125 netdev->vlan_features |= NETIF_F_IP_CSUM;
3126 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3127 netdev->vlan_features |= NETIF_F_GRO;
3128 netdev->vlan_features |= NETIF_F_TSO;
3129 netdev->vlan_features |= NETIF_F_TSO6;
3130 netdev->vlan_features |= NETIF_F_RXCSUM;
3131 netdev->vlan_features |= NETIF_F_RXHASH;
3132
3133 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3134 netdev->vlan_features |= NETIF_F_LRO;
3135
3136 netdev->hw_features = netdev->vlan_features;
3137 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
3138 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3139 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3140
3141 if (mlx5e_vxlan_allowed(mdev)) {
3142 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3143 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3144 NETIF_F_GSO_PARTIAL;
3145 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3146 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3147 netdev->hw_enc_features |= NETIF_F_TSO;
3148 netdev->hw_enc_features |= NETIF_F_TSO6;
3149 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3150 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3151 NETIF_F_GSO_PARTIAL;
3152 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3153 }
3154
3155 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3156
3157 if (fcs_supported)
3158 netdev->hw_features |= NETIF_F_RXALL;
3159
3160 netdev->features = netdev->hw_features;
3161 if (!priv->params.lro_en)
3162 netdev->features &= ~NETIF_F_LRO;
3163
3164 if (fcs_enabled)
3165 netdev->features &= ~NETIF_F_RXALL;
3166
3167 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3168 if (FT_CAP(flow_modify_en) &&
3169 FT_CAP(modify_root) &&
3170 FT_CAP(identified_miss_table_mode) &&
3171 FT_CAP(flow_table_modify)) {
3172 netdev->hw_features |= NETIF_F_HW_TC;
3173 #ifdef CONFIG_RFS_ACCEL
3174 netdev->hw_features |= NETIF_F_NTUPLE;
3175 #endif
3176 }
3177
3178 netdev->features |= NETIF_F_HIGHDMA;
3179
3180 netdev->priv_flags |= IFF_UNICAST_FLT;
3181
3182 mlx5e_set_netdev_dev_addr(netdev);
3183
3184 #ifdef CONFIG_NET_SWITCHDEV
3185 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3186 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3187 #endif
3188 }
3189
3190 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3191 {
3192 struct mlx5_core_dev *mdev = priv->mdev;
3193 int err;
3194
3195 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3196 if (err) {
3197 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3198 priv->q_counter = 0;
3199 }
3200 }
3201
3202 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3203 {
3204 if (!priv->q_counter)
3205 return;
3206
3207 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3208 }
3209
3210 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3211 {
3212 struct mlx5_core_dev *mdev = priv->mdev;
3213 struct mlx5_create_mkey_mbox_in *in;
3214 struct mlx5_mkey_seg *mkc;
3215 int inlen = sizeof(*in);
3216 u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3217 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
3218 int err;
3219
3220 in = mlx5_vzalloc(inlen);
3221 if (!in)
3222 return -ENOMEM;
3223
3224 mkc = &in->seg;
3225 mkc->status = MLX5_MKEY_STATUS_FREE;
3226 mkc->flags = MLX5_PERM_UMR_EN |
3227 MLX5_PERM_LOCAL_READ |
3228 MLX5_PERM_LOCAL_WRITE |
3229 MLX5_ACCESS_MODE_MTT;
3230
3231 npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3232
3233 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3234 mkc->flags_pd = cpu_to_be32(mdev->mlx5e_res.pdn);
3235 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3236 mkc->xlt_oct_size = cpu_to_be32(MLX5_MTT_OCTW(npages));
3237 mkc->log2_page_size = PAGE_SHIFT;
3238
3239 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3240 NULL, NULL);
3241
3242 kvfree(in);
3243
3244 return err;
3245 }
3246
3247 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3248 struct net_device *netdev,
3249 const struct mlx5e_profile *profile,
3250 void *ppriv)
3251 {
3252 struct mlx5e_priv *priv = netdev_priv(netdev);
3253
3254 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3255 mlx5e_build_nic_netdev(netdev);
3256 mlx5e_vxlan_init(priv);
3257 }
3258
3259 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3260 {
3261 struct mlx5_core_dev *mdev = priv->mdev;
3262 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3263
3264 mlx5e_vxlan_cleanup(priv);
3265
3266 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3267 mlx5_eswitch_unregister_vport_rep(esw, 0);
3268 }
3269
3270 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3271 {
3272 struct mlx5_core_dev *mdev = priv->mdev;
3273 int err;
3274 int i;
3275
3276 err = mlx5e_create_indirect_rqts(priv);
3277 if (err) {
3278 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3279 return err;
3280 }
3281
3282 err = mlx5e_create_direct_rqts(priv);
3283 if (err) {
3284 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3285 goto err_destroy_indirect_rqts;
3286 }
3287
3288 err = mlx5e_create_indirect_tirs(priv);
3289 if (err) {
3290 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3291 goto err_destroy_direct_rqts;
3292 }
3293
3294 err = mlx5e_create_direct_tirs(priv);
3295 if (err) {
3296 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3297 goto err_destroy_indirect_tirs;
3298 }
3299
3300 err = mlx5e_create_flow_steering(priv);
3301 if (err) {
3302 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3303 goto err_destroy_direct_tirs;
3304 }
3305
3306 err = mlx5e_tc_init(priv);
3307 if (err)
3308 goto err_destroy_flow_steering;
3309
3310 return 0;
3311
3312 err_destroy_flow_steering:
3313 mlx5e_destroy_flow_steering(priv);
3314 err_destroy_direct_tirs:
3315 mlx5e_destroy_direct_tirs(priv);
3316 err_destroy_indirect_tirs:
3317 mlx5e_destroy_indirect_tirs(priv);
3318 err_destroy_direct_rqts:
3319 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3320 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3321 err_destroy_indirect_rqts:
3322 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3323 return err;
3324 }
3325
3326 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3327 {
3328 int i;
3329
3330 mlx5e_tc_cleanup(priv);
3331 mlx5e_destroy_flow_steering(priv);
3332 mlx5e_destroy_direct_tirs(priv);
3333 mlx5e_destroy_indirect_tirs(priv);
3334 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3335 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3336 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3337 }
3338
3339 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3340 {
3341 int err;
3342
3343 err = mlx5e_create_tises(priv);
3344 if (err) {
3345 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3346 return err;
3347 }
3348
3349 #ifdef CONFIG_MLX5_CORE_EN_DCB
3350 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3351 #endif
3352 return 0;
3353 }
3354
3355 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3356 {
3357 struct net_device *netdev = priv->netdev;
3358 struct mlx5_core_dev *mdev = priv->mdev;
3359 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3360 struct mlx5_eswitch_rep rep;
3361
3362 if (mlx5e_vxlan_allowed(mdev)) {
3363 rtnl_lock();
3364 udp_tunnel_get_rx_info(netdev);
3365 rtnl_unlock();
3366 }
3367
3368 mlx5e_enable_async_events(priv);
3369 queue_work(priv->wq, &priv->set_rx_mode_work);
3370
3371 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3372 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3373 rep.load = mlx5e_nic_rep_load;
3374 rep.unload = mlx5e_nic_rep_unload;
3375 rep.vport = 0;
3376 rep.priv_data = priv;
3377 mlx5_eswitch_register_vport_rep(esw, &rep);
3378 }
3379 }
3380
3381 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3382 {
3383 queue_work(priv->wq, &priv->set_rx_mode_work);
3384 mlx5e_disable_async_events(priv);
3385 }
3386
3387 static const struct mlx5e_profile mlx5e_nic_profile = {
3388 .init = mlx5e_nic_init,
3389 .cleanup = mlx5e_nic_cleanup,
3390 .init_rx = mlx5e_init_nic_rx,
3391 .cleanup_rx = mlx5e_cleanup_nic_rx,
3392 .init_tx = mlx5e_init_nic_tx,
3393 .cleanup_tx = mlx5e_cleanup_nic_tx,
3394 .enable = mlx5e_nic_enable,
3395 .disable = mlx5e_nic_disable,
3396 .update_stats = mlx5e_update_stats,
3397 .max_nch = mlx5e_get_max_num_channels,
3398 .max_tc = MLX5E_MAX_NUM_TC,
3399 };
3400
3401 void *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3402 const struct mlx5e_profile *profile, void *ppriv)
3403 {
3404 struct net_device *netdev;
3405 struct mlx5e_priv *priv;
3406 int nch = profile->max_nch(mdev);
3407 int err;
3408
3409 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3410 nch * profile->max_tc,
3411 nch);
3412 if (!netdev) {
3413 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3414 return NULL;
3415 }
3416
3417 profile->init(mdev, netdev, profile, ppriv);
3418
3419 netif_carrier_off(netdev);
3420
3421 priv = netdev_priv(netdev);
3422
3423 priv->wq = create_singlethread_workqueue("mlx5e");
3424 if (!priv->wq)
3425 goto err_free_netdev;
3426
3427 err = mlx5e_create_umr_mkey(priv);
3428 if (err) {
3429 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3430 goto err_destroy_wq;
3431 }
3432
3433 err = profile->init_tx(priv);
3434 if (err)
3435 goto err_destroy_umr_mkey;
3436
3437 err = mlx5e_open_drop_rq(priv);
3438 if (err) {
3439 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3440 goto err_cleanup_tx;
3441 }
3442
3443 err = profile->init_rx(priv);
3444 if (err)
3445 goto err_close_drop_rq;
3446
3447 mlx5e_create_q_counter(priv);
3448
3449 mlx5e_init_l2_addr(priv);
3450
3451 mlx5e_set_dev_port_mtu(netdev);
3452
3453 err = register_netdev(netdev);
3454 if (err) {
3455 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3456 goto err_dealloc_q_counters;
3457 }
3458
3459 if (profile->enable)
3460 profile->enable(priv);
3461
3462 return priv;
3463
3464 err_dealloc_q_counters:
3465 mlx5e_destroy_q_counter(priv);
3466 profile->cleanup_rx(priv);
3467
3468 err_close_drop_rq:
3469 mlx5e_close_drop_rq(priv);
3470
3471 err_cleanup_tx:
3472 profile->cleanup_tx(priv);
3473
3474 err_destroy_umr_mkey:
3475 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3476
3477 err_destroy_wq:
3478 destroy_workqueue(priv->wq);
3479
3480 err_free_netdev:
3481 free_netdev(netdev);
3482
3483 return NULL;
3484 }
3485
3486 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3487 {
3488 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3489 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3490 int vport;
3491 u8 mac[ETH_ALEN];
3492
3493 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3494 return;
3495
3496 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3497
3498 for (vport = 1; vport < total_vfs; vport++) {
3499 struct mlx5_eswitch_rep rep;
3500
3501 rep.load = mlx5e_vport_rep_load;
3502 rep.unload = mlx5e_vport_rep_unload;
3503 rep.vport = vport;
3504 ether_addr_copy(rep.hw_id, mac);
3505 mlx5_eswitch_register_vport_rep(esw, &rep);
3506 }
3507 }
3508
3509 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3510 {
3511 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3512 void *ppriv = NULL;
3513 void *ret;
3514
3515 if (mlx5e_check_required_hca_cap(mdev))
3516 return NULL;
3517
3518 if (mlx5e_create_mdev_resources(mdev))
3519 return NULL;
3520
3521 mlx5e_register_vport_rep(mdev);
3522
3523 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3524 ppriv = &esw->offloads.vport_reps[0];
3525
3526 ret = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
3527 if (!ret) {
3528 mlx5e_destroy_mdev_resources(mdev);
3529 return NULL;
3530 }
3531 return ret;
3532 }
3533
3534 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
3535 {
3536 const struct mlx5e_profile *profile = priv->profile;
3537 struct net_device *netdev = priv->netdev;
3538
3539 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3540 if (profile->disable)
3541 profile->disable(priv);
3542
3543 flush_workqueue(priv->wq);
3544 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3545 netif_device_detach(netdev);
3546 mlx5e_close(netdev);
3547 } else {
3548 unregister_netdev(netdev);
3549 }
3550
3551 mlx5e_destroy_q_counter(priv);
3552 profile->cleanup_rx(priv);
3553 mlx5e_close_drop_rq(priv);
3554 profile->cleanup_tx(priv);
3555 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3556 cancel_delayed_work_sync(&priv->update_stats_work);
3557 destroy_workqueue(priv->wq);
3558 if (profile->cleanup)
3559 profile->cleanup(priv);
3560
3561 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3562 free_netdev(netdev);
3563 }
3564
3565 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3566 {
3567 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3568 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3569 struct mlx5e_priv *priv = vpriv;
3570 int vport;
3571
3572 mlx5e_destroy_netdev(mdev, priv);
3573
3574 for (vport = 1; vport < total_vfs; vport++)
3575 mlx5_eswitch_unregister_vport_rep(esw, vport);
3576
3577 mlx5e_destroy_mdev_resources(mdev);
3578 }
3579
3580 static void *mlx5e_get_netdev(void *vpriv)
3581 {
3582 struct mlx5e_priv *priv = vpriv;
3583
3584 return priv->netdev;
3585 }
3586
3587 static struct mlx5_interface mlx5e_interface = {
3588 .add = mlx5e_add,
3589 .remove = mlx5e_remove,
3590 .event = mlx5e_async_event,
3591 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3592 .get_dev = mlx5e_get_netdev,
3593 };
3594
3595 void mlx5e_init(void)
3596 {
3597 mlx5e_build_ptys2ethtool_map();
3598 mlx5_register_interface(&mlx5e_interface);
3599 }
3600
3601 void mlx5e_cleanup(void)
3602 {
3603 mlx5_unregister_interface(&mlx5e_interface);
3604 }
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