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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <linux/crash_dump.h>
35 #include <net/pkt_cls.h>
36 #include <linux/mlx5/fs.h>
37 #include <net/vxlan.h>
38 #include <linux/bpf.h>
39 #include "en.h"
40 #include "en_tc.h"
41 #include "eswitch.h"
42 #include "vxlan.h"
43
44 struct mlx5e_rq_param {
45 u32 rqc[MLX5_ST_SZ_DW(rqc)];
46 struct mlx5_wq_param wq;
47 bool am_enabled;
48 };
49
50 struct mlx5e_sq_param {
51 u32 sqc[MLX5_ST_SZ_DW(sqc)];
52 struct mlx5_wq_param wq;
53 u16 max_inline;
54 u8 min_inline_mode;
55 enum mlx5e_sq_type type;
56 };
57
58 struct mlx5e_cq_param {
59 u32 cqc[MLX5_ST_SZ_DW(cqc)];
60 struct mlx5_wq_param wq;
61 u16 eq_ix;
62 u8 cq_period_mode;
63 };
64
65 struct mlx5e_channel_param {
66 struct mlx5e_rq_param rq;
67 struct mlx5e_sq_param sq;
68 struct mlx5e_sq_param xdp_sq;
69 struct mlx5e_sq_param icosq;
70 struct mlx5e_cq_param rx_cq;
71 struct mlx5e_cq_param tx_cq;
72 struct mlx5e_cq_param icosq_cq;
73 };
74
75 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
76 {
77 return MLX5_CAP_GEN(mdev, striding_rq) &&
78 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
79 MLX5_CAP_ETH(mdev, reg_umr_sq);
80 }
81
82 static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
83 {
84 priv->params.rq_wq_type = rq_type;
85 switch (priv->params.rq_wq_type) {
86 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
87 priv->params.log_rq_size = is_kdump_kernel() ?
88 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
89 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
90 priv->params.mpwqe_log_stride_sz =
91 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
92 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(priv->mdev) :
93 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(priv->mdev);
94 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
95 priv->params.mpwqe_log_stride_sz;
96 break;
97 default: /* MLX5_WQ_TYPE_LINKED_LIST */
98 priv->params.log_rq_size = is_kdump_kernel() ?
99 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
100 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
101 }
102 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
103 BIT(priv->params.log_rq_size));
104
105 mlx5_core_info(priv->mdev,
106 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
107 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
108 BIT(priv->params.log_rq_size),
109 BIT(priv->params.mpwqe_log_stride_sz),
110 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS));
111 }
112
113 static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
114 {
115 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
116 !priv->xdp_prog ?
117 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
118 MLX5_WQ_TYPE_LINKED_LIST;
119 mlx5e_set_rq_type_params(priv, rq_type);
120 }
121
122 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
123 {
124 struct mlx5_core_dev *mdev = priv->mdev;
125 u8 port_state;
126
127 port_state = mlx5_query_vport_state(mdev,
128 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
129
130 if (port_state == VPORT_STATE_UP) {
131 netdev_info(priv->netdev, "Link up\n");
132 netif_carrier_on(priv->netdev);
133 } else {
134 netdev_info(priv->netdev, "Link down\n");
135 netif_carrier_off(priv->netdev);
136 }
137 }
138
139 static void mlx5e_update_carrier_work(struct work_struct *work)
140 {
141 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
142 update_carrier_work);
143
144 mutex_lock(&priv->state_lock);
145 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
146 mlx5e_update_carrier(priv);
147 mutex_unlock(&priv->state_lock);
148 }
149
150 static void mlx5e_tx_timeout_work(struct work_struct *work)
151 {
152 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
153 tx_timeout_work);
154 int err;
155
156 rtnl_lock();
157 mutex_lock(&priv->state_lock);
158 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
159 goto unlock;
160 mlx5e_close_locked(priv->netdev);
161 err = mlx5e_open_locked(priv->netdev);
162 if (err)
163 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
164 err);
165 unlock:
166 mutex_unlock(&priv->state_lock);
167 rtnl_unlock();
168 }
169
170 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
171 {
172 struct mlx5e_sw_stats *s = &priv->stats.sw;
173 struct mlx5e_rq_stats *rq_stats;
174 struct mlx5e_sq_stats *sq_stats;
175 u64 tx_offload_none = 0;
176 int i, j;
177
178 memset(s, 0, sizeof(*s));
179 for (i = 0; i < priv->params.num_channels; i++) {
180 rq_stats = &priv->channel[i]->rq.stats;
181
182 s->rx_packets += rq_stats->packets;
183 s->rx_bytes += rq_stats->bytes;
184 s->rx_lro_packets += rq_stats->lro_packets;
185 s->rx_lro_bytes += rq_stats->lro_bytes;
186 s->rx_csum_none += rq_stats->csum_none;
187 s->rx_csum_complete += rq_stats->csum_complete;
188 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
189 s->rx_xdp_drop += rq_stats->xdp_drop;
190 s->rx_xdp_tx += rq_stats->xdp_tx;
191 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
192 s->rx_wqe_err += rq_stats->wqe_err;
193 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
194 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
195 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
196 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
197 s->rx_cache_reuse += rq_stats->cache_reuse;
198 s->rx_cache_full += rq_stats->cache_full;
199 s->rx_cache_empty += rq_stats->cache_empty;
200 s->rx_cache_busy += rq_stats->cache_busy;
201
202 for (j = 0; j < priv->params.num_tc; j++) {
203 sq_stats = &priv->channel[i]->sq[j].stats;
204
205 s->tx_packets += sq_stats->packets;
206 s->tx_bytes += sq_stats->bytes;
207 s->tx_tso_packets += sq_stats->tso_packets;
208 s->tx_tso_bytes += sq_stats->tso_bytes;
209 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
210 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
211 s->tx_queue_stopped += sq_stats->stopped;
212 s->tx_queue_wake += sq_stats->wake;
213 s->tx_queue_dropped += sq_stats->dropped;
214 s->tx_xmit_more += sq_stats->xmit_more;
215 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
216 tx_offload_none += sq_stats->csum_none;
217 }
218 }
219
220 /* Update calculated offload counters */
221 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
222 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
223
224 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
225 priv->stats.pport.phy_counters,
226 counter_set.phys_layer_cntrs.link_down_events);
227 }
228
229 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
230 {
231 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
232 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
233 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
234 struct mlx5_core_dev *mdev = priv->mdev;
235
236 MLX5_SET(query_vport_counter_in, in, opcode,
237 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
238 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
239 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
240
241 memset(out, 0, outlen);
242 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
243 }
244
245 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
246 {
247 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
248 struct mlx5_core_dev *mdev = priv->mdev;
249 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
250 int prio;
251 void *out;
252 u32 *in;
253
254 in = mlx5_vzalloc(sz);
255 if (!in)
256 goto free_out;
257
258 MLX5_SET(ppcnt_reg, in, local_port, 1);
259
260 out = pstats->IEEE_802_3_counters;
261 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
262 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
263
264 out = pstats->RFC_2863_counters;
265 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
266 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
267
268 out = pstats->RFC_2819_counters;
269 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
270 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
271
272 out = pstats->phy_counters;
273 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
274 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
275
276 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
277 out = pstats->phy_statistical_counters;
278 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
279 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
280 }
281
282 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
283 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
284 out = pstats->per_prio_counters[prio];
285 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
286 mlx5_core_access_reg(mdev, in, sz, out, sz,
287 MLX5_REG_PPCNT, 0, 0);
288 }
289
290 free_out:
291 kvfree(in);
292 }
293
294 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
295 {
296 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
297
298 if (!priv->q_counter)
299 return;
300
301 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
302 &qcnt->rx_out_of_buffer);
303 }
304
305 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
306 {
307 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
308 struct mlx5_core_dev *mdev = priv->mdev;
309 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
310 void *out;
311 u32 *in;
312
313 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
314 return;
315
316 in = mlx5_vzalloc(sz);
317 if (!in)
318 return;
319
320 out = pcie_stats->pcie_perf_counters;
321 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
322 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
323
324 kvfree(in);
325 }
326
327 void mlx5e_update_stats(struct mlx5e_priv *priv)
328 {
329 mlx5e_update_pcie_counters(priv);
330 mlx5e_update_pport_counters(priv);
331 mlx5e_update_vport_counters(priv);
332 mlx5e_update_q_counter(priv);
333 mlx5e_update_sw_counters(priv);
334 }
335
336 void mlx5e_update_stats_work(struct work_struct *work)
337 {
338 struct delayed_work *dwork = to_delayed_work(work);
339 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
340 update_stats_work);
341 mutex_lock(&priv->state_lock);
342 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
343 priv->profile->update_stats(priv);
344 queue_delayed_work(priv->wq, dwork,
345 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
346 }
347 mutex_unlock(&priv->state_lock);
348 }
349
350 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
351 enum mlx5_dev_event event, unsigned long param)
352 {
353 struct mlx5e_priv *priv = vpriv;
354 struct ptp_clock_event ptp_event;
355 struct mlx5_eqe *eqe = NULL;
356
357 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
358 return;
359
360 switch (event) {
361 case MLX5_DEV_EVENT_PORT_UP:
362 case MLX5_DEV_EVENT_PORT_DOWN:
363 queue_work(priv->wq, &priv->update_carrier_work);
364 break;
365 case MLX5_DEV_EVENT_PPS:
366 eqe = (struct mlx5_eqe *)param;
367 ptp_event.type = PTP_CLOCK_EXTTS;
368 ptp_event.index = eqe->data.pps.pin;
369 ptp_event.timestamp =
370 timecounter_cyc2time(&priv->tstamp.clock,
371 be64_to_cpu(eqe->data.pps.time_stamp));
372 mlx5e_pps_event_handler(vpriv, &ptp_event);
373 break;
374 default:
375 break;
376 }
377 }
378
379 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
380 {
381 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
382 }
383
384 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
385 {
386 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
387 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
388 }
389
390 static inline int mlx5e_get_wqe_mtt_sz(void)
391 {
392 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
393 * To avoid copying garbage after the mtt array, we allocate
394 * a little more.
395 */
396 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
397 MLX5_UMR_MTT_ALIGNMENT);
398 }
399
400 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
401 struct mlx5e_umr_wqe *wqe, u16 ix)
402 {
403 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
404 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
405 struct mlx5_wqe_data_seg *dseg = &wqe->data;
406 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
407 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
408 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
409
410 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
411 ds_cnt);
412 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
413 cseg->imm = rq->mkey_be;
414
415 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
416 ucseg->xlt_octowords =
417 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
418 ucseg->bsf_octowords =
419 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
420 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
421
422 dseg->lkey = sq->mkey_be;
423 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
424 }
425
426 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
427 struct mlx5e_channel *c)
428 {
429 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
430 int mtt_sz = mlx5e_get_wqe_mtt_sz();
431 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
432 int i;
433
434 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
435 GFP_KERNEL, cpu_to_node(c->cpu));
436 if (!rq->mpwqe.info)
437 goto err_out;
438
439 /* We allocate more than mtt_sz as we will align the pointer */
440 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
441 cpu_to_node(c->cpu));
442 if (unlikely(!rq->mpwqe.mtt_no_align))
443 goto err_free_wqe_info;
444
445 for (i = 0; i < wq_sz; i++) {
446 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
447
448 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
449 MLX5_UMR_ALIGN);
450 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
451 PCI_DMA_TODEVICE);
452 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
453 goto err_unmap_mtts;
454
455 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
456 }
457
458 return 0;
459
460 err_unmap_mtts:
461 while (--i >= 0) {
462 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
463
464 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
465 PCI_DMA_TODEVICE);
466 }
467 kfree(rq->mpwqe.mtt_no_align);
468 err_free_wqe_info:
469 kfree(rq->mpwqe.info);
470
471 err_out:
472 return -ENOMEM;
473 }
474
475 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
476 {
477 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
478 int mtt_sz = mlx5e_get_wqe_mtt_sz();
479 int i;
480
481 for (i = 0; i < wq_sz; i++) {
482 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
483
484 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
485 PCI_DMA_TODEVICE);
486 }
487 kfree(rq->mpwqe.mtt_no_align);
488 kfree(rq->mpwqe.info);
489 }
490
491 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv,
492 u64 npages, u8 page_shift,
493 struct mlx5_core_mkey *umr_mkey)
494 {
495 struct mlx5_core_dev *mdev = priv->mdev;
496 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
497 void *mkc;
498 u32 *in;
499 int err;
500
501 if (!MLX5E_VALID_NUM_MTTS(npages))
502 return -EINVAL;
503
504 in = mlx5_vzalloc(inlen);
505 if (!in)
506 return -ENOMEM;
507
508 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
509
510 MLX5_SET(mkc, mkc, free, 1);
511 MLX5_SET(mkc, mkc, umr_en, 1);
512 MLX5_SET(mkc, mkc, lw, 1);
513 MLX5_SET(mkc, mkc, lr, 1);
514 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
515
516 MLX5_SET(mkc, mkc, qpn, 0xffffff);
517 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
518 MLX5_SET64(mkc, mkc, len, npages << page_shift);
519 MLX5_SET(mkc, mkc, translations_octword_size,
520 MLX5_MTT_OCTW(npages));
521 MLX5_SET(mkc, mkc, log_page_size, page_shift);
522
523 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
524
525 kvfree(in);
526 return err;
527 }
528
529 static int mlx5e_create_rq_umr_mkey(struct mlx5e_rq *rq)
530 {
531 struct mlx5e_priv *priv = rq->priv;
532 u64 num_mtts = MLX5E_REQUIRED_MTTS(BIT(priv->params.log_rq_size));
533
534 return mlx5e_create_umr_mkey(priv, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
535 }
536
537 static int mlx5e_create_rq(struct mlx5e_channel *c,
538 struct mlx5e_rq_param *param,
539 struct mlx5e_rq *rq)
540 {
541 struct mlx5e_priv *priv = c->priv;
542 struct mlx5_core_dev *mdev = priv->mdev;
543 void *rqc = param->rqc;
544 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
545 u32 byte_count;
546 u32 frag_sz;
547 int npages;
548 int wq_sz;
549 int err;
550 int i;
551
552 param->wq.db_numa_node = cpu_to_node(c->cpu);
553
554 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
555 &rq->wq_ctrl);
556 if (err)
557 return err;
558
559 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
560
561 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
562
563 rq->wq_type = priv->params.rq_wq_type;
564 rq->pdev = c->pdev;
565 rq->netdev = c->netdev;
566 rq->tstamp = &priv->tstamp;
567 rq->channel = c;
568 rq->ix = c->ix;
569 rq->priv = c->priv;
570
571 rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
572 if (IS_ERR(rq->xdp_prog)) {
573 err = PTR_ERR(rq->xdp_prog);
574 rq->xdp_prog = NULL;
575 goto err_rq_wq_destroy;
576 }
577
578 if (rq->xdp_prog) {
579 rq->buff.map_dir = DMA_BIDIRECTIONAL;
580 rq->rx_headroom = XDP_PACKET_HEADROOM;
581 } else {
582 rq->buff.map_dir = DMA_FROM_DEVICE;
583 rq->rx_headroom = MLX5_RX_HEADROOM;
584 }
585
586 switch (priv->params.rq_wq_type) {
587 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
588 if (mlx5e_is_vf_vport_rep(priv)) {
589 err = -EINVAL;
590 goto err_rq_wq_destroy;
591 }
592
593 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
594 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
595 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
596
597 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
598 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
599
600 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
601 byte_count = rq->buff.wqe_sz;
602
603 err = mlx5e_create_rq_umr_mkey(rq);
604 if (err)
605 goto err_rq_wq_destroy;
606 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
607
608 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
609 if (err)
610 goto err_destroy_umr_mkey;
611 break;
612 default: /* MLX5_WQ_TYPE_LINKED_LIST */
613 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
614 GFP_KERNEL, cpu_to_node(c->cpu));
615 if (!rq->dma_info) {
616 err = -ENOMEM;
617 goto err_rq_wq_destroy;
618 }
619
620 if (mlx5e_is_vf_vport_rep(priv))
621 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
622 else
623 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
624
625 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
626 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
627
628 rq->buff.wqe_sz = (priv->params.lro_en) ?
629 priv->params.lro_wqe_sz :
630 MLX5E_SW2HW_MTU(priv->netdev->mtu);
631 byte_count = rq->buff.wqe_sz;
632
633 /* calc the required page order */
634 frag_sz = rq->rx_headroom +
635 byte_count /* packet data */ +
636 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
637 frag_sz = SKB_DATA_ALIGN(frag_sz);
638
639 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
640 rq->buff.page_order = order_base_2(npages);
641
642 byte_count |= MLX5_HW_START_PADDING;
643 rq->mkey_be = c->mkey_be;
644 }
645
646 for (i = 0; i < wq_sz; i++) {
647 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
648
649 wqe->data.byte_count = cpu_to_be32(byte_count);
650 wqe->data.lkey = rq->mkey_be;
651 }
652
653 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
654 rq->am.mode = priv->params.rx_cq_period_mode;
655
656 rq->page_cache.head = 0;
657 rq->page_cache.tail = 0;
658
659 return 0;
660
661 err_destroy_umr_mkey:
662 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
663
664 err_rq_wq_destroy:
665 if (rq->xdp_prog)
666 bpf_prog_put(rq->xdp_prog);
667 mlx5_wq_destroy(&rq->wq_ctrl);
668
669 return err;
670 }
671
672 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
673 {
674 int i;
675
676 if (rq->xdp_prog)
677 bpf_prog_put(rq->xdp_prog);
678
679 switch (rq->wq_type) {
680 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
681 mlx5e_rq_free_mpwqe_info(rq);
682 mlx5_core_destroy_mkey(rq->priv->mdev, &rq->umr_mkey);
683 break;
684 default: /* MLX5_WQ_TYPE_LINKED_LIST */
685 kfree(rq->dma_info);
686 }
687
688 for (i = rq->page_cache.head; i != rq->page_cache.tail;
689 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
690 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
691
692 mlx5e_page_release(rq, dma_info, false);
693 }
694 mlx5_wq_destroy(&rq->wq_ctrl);
695 }
696
697 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
698 {
699 struct mlx5e_priv *priv = rq->priv;
700 struct mlx5_core_dev *mdev = priv->mdev;
701
702 void *in;
703 void *rqc;
704 void *wq;
705 int inlen;
706 int err;
707
708 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
709 sizeof(u64) * rq->wq_ctrl.buf.npages;
710 in = mlx5_vzalloc(inlen);
711 if (!in)
712 return -ENOMEM;
713
714 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
715 wq = MLX5_ADDR_OF(rqc, rqc, wq);
716
717 memcpy(rqc, param->rqc, sizeof(param->rqc));
718
719 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
720 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
721 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
722 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
723 MLX5_ADAPTER_PAGE_SHIFT);
724 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
725
726 mlx5_fill_page_array(&rq->wq_ctrl.buf,
727 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
728
729 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
730
731 kvfree(in);
732
733 return err;
734 }
735
736 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
737 int next_state)
738 {
739 struct mlx5e_channel *c = rq->channel;
740 struct mlx5e_priv *priv = c->priv;
741 struct mlx5_core_dev *mdev = priv->mdev;
742
743 void *in;
744 void *rqc;
745 int inlen;
746 int err;
747
748 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
749 in = mlx5_vzalloc(inlen);
750 if (!in)
751 return -ENOMEM;
752
753 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
754
755 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
756 MLX5_SET(rqc, rqc, state, next_state);
757
758 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
759
760 kvfree(in);
761
762 return err;
763 }
764
765 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
766 {
767 struct mlx5e_channel *c = rq->channel;
768 struct mlx5e_priv *priv = c->priv;
769 struct mlx5_core_dev *mdev = priv->mdev;
770
771 void *in;
772 void *rqc;
773 int inlen;
774 int err;
775
776 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
777 in = mlx5_vzalloc(inlen);
778 if (!in)
779 return -ENOMEM;
780
781 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
782
783 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
784 MLX5_SET64(modify_rq_in, in, modify_bitmask,
785 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
786 MLX5_SET(rqc, rqc, vsd, vsd);
787 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
788
789 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
790
791 kvfree(in);
792
793 return err;
794 }
795
796 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
797 {
798 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
799 }
800
801 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
802 {
803 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
804 struct mlx5e_channel *c = rq->channel;
805 struct mlx5e_priv *priv = c->priv;
806 struct mlx5_wq_ll *wq = &rq->wq;
807
808 while (time_before(jiffies, exp_time)) {
809 if (wq->cur_sz >= priv->params.min_rx_wqes)
810 return 0;
811
812 msleep(20);
813 }
814
815 return -ETIMEDOUT;
816 }
817
818 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
819 {
820 struct mlx5_wq_ll *wq = &rq->wq;
821 struct mlx5e_rx_wqe *wqe;
822 __be16 wqe_ix_be;
823 u16 wqe_ix;
824
825 /* UMR WQE (if in progress) is always at wq->head */
826 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
827 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
828
829 while (!mlx5_wq_ll_is_empty(wq)) {
830 wqe_ix_be = *wq->tail_next;
831 wqe_ix = be16_to_cpu(wqe_ix_be);
832 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
833 rq->dealloc_wqe(rq, wqe_ix);
834 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
835 &wqe->next.next_wqe_index);
836 }
837 }
838
839 static int mlx5e_open_rq(struct mlx5e_channel *c,
840 struct mlx5e_rq_param *param,
841 struct mlx5e_rq *rq)
842 {
843 struct mlx5e_sq *sq = &c->icosq;
844 u16 pi = sq->pc & sq->wq.sz_m1;
845 int err;
846
847 err = mlx5e_create_rq(c, param, rq);
848 if (err)
849 return err;
850
851 err = mlx5e_enable_rq(rq, param);
852 if (err)
853 goto err_destroy_rq;
854
855 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
856 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
857 if (err)
858 goto err_disable_rq;
859
860 if (param->am_enabled)
861 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
862
863 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
864 sq->db.ico_wqe[pi].num_wqebbs = 1;
865 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
866
867 return 0;
868
869 err_disable_rq:
870 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
871 mlx5e_disable_rq(rq);
872 err_destroy_rq:
873 mlx5e_destroy_rq(rq);
874
875 return err;
876 }
877
878 static void mlx5e_close_rq(struct mlx5e_rq *rq)
879 {
880 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
881 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
882 cancel_work_sync(&rq->am.work);
883
884 mlx5e_disable_rq(rq);
885 mlx5e_free_rx_descs(rq);
886 mlx5e_destroy_rq(rq);
887 }
888
889 static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
890 {
891 kfree(sq->db.xdp.di);
892 kfree(sq->db.xdp.wqe_info);
893 }
894
895 static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
896 {
897 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
898
899 sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
900 GFP_KERNEL, numa);
901 sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
902 GFP_KERNEL, numa);
903 if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
904 mlx5e_free_sq_xdp_db(sq);
905 return -ENOMEM;
906 }
907
908 return 0;
909 }
910
911 static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
912 {
913 kfree(sq->db.ico_wqe);
914 }
915
916 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
917 {
918 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
919
920 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
921 GFP_KERNEL, numa);
922 if (!sq->db.ico_wqe)
923 return -ENOMEM;
924
925 return 0;
926 }
927
928 static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
929 {
930 kfree(sq->db.txq.wqe_info);
931 kfree(sq->db.txq.dma_fifo);
932 kfree(sq->db.txq.skb);
933 }
934
935 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
936 {
937 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
938 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
939
940 sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
941 GFP_KERNEL, numa);
942 sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
943 GFP_KERNEL, numa);
944 sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
945 GFP_KERNEL, numa);
946 if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
947 mlx5e_free_sq_txq_db(sq);
948 return -ENOMEM;
949 }
950
951 sq->dma_fifo_mask = df_sz - 1;
952
953 return 0;
954 }
955
956 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
957 {
958 switch (sq->type) {
959 case MLX5E_SQ_TXQ:
960 mlx5e_free_sq_txq_db(sq);
961 break;
962 case MLX5E_SQ_ICO:
963 mlx5e_free_sq_ico_db(sq);
964 break;
965 case MLX5E_SQ_XDP:
966 mlx5e_free_sq_xdp_db(sq);
967 break;
968 }
969 }
970
971 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
972 {
973 switch (sq->type) {
974 case MLX5E_SQ_TXQ:
975 return mlx5e_alloc_sq_txq_db(sq, numa);
976 case MLX5E_SQ_ICO:
977 return mlx5e_alloc_sq_ico_db(sq, numa);
978 case MLX5E_SQ_XDP:
979 return mlx5e_alloc_sq_xdp_db(sq, numa);
980 }
981
982 return 0;
983 }
984
985 static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
986 {
987 switch (sq_type) {
988 case MLX5E_SQ_ICO:
989 return MLX5E_ICOSQ_MAX_WQEBBS;
990 case MLX5E_SQ_XDP:
991 return MLX5E_XDP_TX_WQEBBS;
992 }
993 return MLX5_SEND_WQE_MAX_WQEBBS;
994 }
995
996 static int mlx5e_create_sq(struct mlx5e_channel *c,
997 int tc,
998 struct mlx5e_sq_param *param,
999 struct mlx5e_sq *sq)
1000 {
1001 struct mlx5e_priv *priv = c->priv;
1002 struct mlx5_core_dev *mdev = priv->mdev;
1003
1004 void *sqc = param->sqc;
1005 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1006 int err;
1007
1008 sq->type = param->type;
1009 sq->pdev = c->pdev;
1010 sq->tstamp = &priv->tstamp;
1011 sq->mkey_be = c->mkey_be;
1012 sq->channel = c;
1013 sq->tc = tc;
1014
1015 err = mlx5_alloc_bfreg(mdev, &sq->bfreg, MLX5_CAP_GEN(mdev, bf), false);
1016 if (err)
1017 return err;
1018
1019 sq->uar_map = sq->bfreg.map;
1020 param->wq.db_numa_node = cpu_to_node(c->cpu);
1021
1022 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1023 &sq->wq_ctrl);
1024 if (err)
1025 goto err_unmap_free_uar;
1026
1027 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1028 if (sq->bfreg.wc)
1029 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
1030
1031 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1032 sq->max_inline = param->max_inline;
1033 sq->min_inline_mode = param->min_inline_mode;
1034
1035 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
1036 if (err)
1037 goto err_sq_wq_destroy;
1038
1039 if (sq->type == MLX5E_SQ_TXQ) {
1040 int txq_ix;
1041
1042 txq_ix = c->ix + tc * priv->params.num_channels;
1043 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
1044 priv->txq_to_sq_map[txq_ix] = sq;
1045 }
1046
1047 sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
1048 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
1049
1050 return 0;
1051
1052 err_sq_wq_destroy:
1053 mlx5_wq_destroy(&sq->wq_ctrl);
1054
1055 err_unmap_free_uar:
1056 mlx5_free_bfreg(mdev, &sq->bfreg);
1057
1058 return err;
1059 }
1060
1061 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
1062 {
1063 struct mlx5e_channel *c = sq->channel;
1064 struct mlx5e_priv *priv = c->priv;
1065
1066 mlx5e_free_sq_db(sq);
1067 mlx5_wq_destroy(&sq->wq_ctrl);
1068 mlx5_free_bfreg(priv->mdev, &sq->bfreg);
1069 }
1070
1071 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1072 {
1073 struct mlx5e_channel *c = sq->channel;
1074 struct mlx5e_priv *priv = c->priv;
1075 struct mlx5_core_dev *mdev = priv->mdev;
1076
1077 void *in;
1078 void *sqc;
1079 void *wq;
1080 int inlen;
1081 int err;
1082
1083 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1084 sizeof(u64) * sq->wq_ctrl.buf.npages;
1085 in = mlx5_vzalloc(inlen);
1086 if (!in)
1087 return -ENOMEM;
1088
1089 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1090 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1091
1092 memcpy(sqc, param->sqc, sizeof(param->sqc));
1093
1094 MLX5_SET(sqc, sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1095 0 : priv->tisn[sq->tc]);
1096 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1097
1098 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1099 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
1100
1101 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1102 MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
1103
1104 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1105 MLX5_SET(wq, wq, uar_page, sq->bfreg.index);
1106 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1107 MLX5_ADAPTER_PAGE_SHIFT);
1108 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1109
1110 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1111 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1112
1113 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1114
1115 kvfree(in);
1116
1117 return err;
1118 }
1119
1120 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1121 int next_state, bool update_rl, int rl_index)
1122 {
1123 struct mlx5e_channel *c = sq->channel;
1124 struct mlx5e_priv *priv = c->priv;
1125 struct mlx5_core_dev *mdev = priv->mdev;
1126
1127 void *in;
1128 void *sqc;
1129 int inlen;
1130 int err;
1131
1132 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1133 in = mlx5_vzalloc(inlen);
1134 if (!in)
1135 return -ENOMEM;
1136
1137 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1138
1139 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1140 MLX5_SET(sqc, sqc, state, next_state);
1141 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1142 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1143 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
1144 }
1145
1146 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
1147
1148 kvfree(in);
1149
1150 return err;
1151 }
1152
1153 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1154 {
1155 struct mlx5e_channel *c = sq->channel;
1156 struct mlx5e_priv *priv = c->priv;
1157 struct mlx5_core_dev *mdev = priv->mdev;
1158
1159 mlx5_core_destroy_sq(mdev, sq->sqn);
1160 if (sq->rate_limit)
1161 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1162 }
1163
1164 static int mlx5e_open_sq(struct mlx5e_channel *c,
1165 int tc,
1166 struct mlx5e_sq_param *param,
1167 struct mlx5e_sq *sq)
1168 {
1169 int err;
1170
1171 err = mlx5e_create_sq(c, tc, param, sq);
1172 if (err)
1173 return err;
1174
1175 err = mlx5e_enable_sq(sq, param);
1176 if (err)
1177 goto err_destroy_sq;
1178
1179 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1180 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1181 false, 0);
1182 if (err)
1183 goto err_disable_sq;
1184
1185 if (sq->txq) {
1186 netdev_tx_reset_queue(sq->txq);
1187 netif_tx_start_queue(sq->txq);
1188 }
1189
1190 return 0;
1191
1192 err_disable_sq:
1193 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1194 mlx5e_disable_sq(sq);
1195 err_destroy_sq:
1196 mlx5e_destroy_sq(sq);
1197
1198 return err;
1199 }
1200
1201 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1202 {
1203 __netif_tx_lock_bh(txq);
1204 netif_tx_stop_queue(txq);
1205 __netif_tx_unlock_bh(txq);
1206 }
1207
1208 static void mlx5e_close_sq(struct mlx5e_sq *sq)
1209 {
1210 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1211 /* prevent netif_tx_wake_queue */
1212 napi_synchronize(&sq->channel->napi);
1213
1214 if (sq->txq) {
1215 netif_tx_disable_queue(sq->txq);
1216
1217 /* last doorbell out, godspeed .. */
1218 if (mlx5e_sq_has_room_for(sq, 1)) {
1219 sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1220 mlx5e_send_nop(sq, true);
1221 }
1222 }
1223
1224 mlx5e_disable_sq(sq);
1225 mlx5e_free_sq_descs(sq);
1226 mlx5e_destroy_sq(sq);
1227 }
1228
1229 static int mlx5e_create_cq(struct mlx5e_channel *c,
1230 struct mlx5e_cq_param *param,
1231 struct mlx5e_cq *cq)
1232 {
1233 struct mlx5e_priv *priv = c->priv;
1234 struct mlx5_core_dev *mdev = priv->mdev;
1235 struct mlx5_core_cq *mcq = &cq->mcq;
1236 int eqn_not_used;
1237 unsigned int irqn;
1238 int err;
1239 u32 i;
1240
1241 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1242 param->wq.db_numa_node = cpu_to_node(c->cpu);
1243 param->eq_ix = c->ix;
1244
1245 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1246 &cq->wq_ctrl);
1247 if (err)
1248 return err;
1249
1250 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1251
1252 cq->napi = &c->napi;
1253
1254 mcq->cqe_sz = 64;
1255 mcq->set_ci_db = cq->wq_ctrl.db.db;
1256 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1257 *mcq->set_ci_db = 0;
1258 *mcq->arm_db = 0;
1259 mcq->vector = param->eq_ix;
1260 mcq->comp = mlx5e_completion_event;
1261 mcq->event = mlx5e_cq_error_event;
1262 mcq->irqn = irqn;
1263
1264 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1265 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1266
1267 cqe->op_own = 0xf1;
1268 }
1269
1270 cq->channel = c;
1271 cq->priv = priv;
1272
1273 return 0;
1274 }
1275
1276 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1277 {
1278 mlx5_cqwq_destroy(&cq->wq_ctrl);
1279 }
1280
1281 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1282 {
1283 struct mlx5e_priv *priv = cq->priv;
1284 struct mlx5_core_dev *mdev = priv->mdev;
1285 struct mlx5_core_cq *mcq = &cq->mcq;
1286
1287 void *in;
1288 void *cqc;
1289 int inlen;
1290 unsigned int irqn_not_used;
1291 int eqn;
1292 int err;
1293
1294 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1295 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1296 in = mlx5_vzalloc(inlen);
1297 if (!in)
1298 return -ENOMEM;
1299
1300 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1301
1302 memcpy(cqc, param->cqc, sizeof(param->cqc));
1303
1304 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1305 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1306
1307 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1308
1309 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1310 MLX5_SET(cqc, cqc, c_eqn, eqn);
1311 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1312 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1313 MLX5_ADAPTER_PAGE_SHIFT);
1314 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1315
1316 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1317
1318 kvfree(in);
1319
1320 if (err)
1321 return err;
1322
1323 mlx5e_cq_arm(cq);
1324
1325 return 0;
1326 }
1327
1328 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1329 {
1330 struct mlx5e_priv *priv = cq->priv;
1331 struct mlx5_core_dev *mdev = priv->mdev;
1332
1333 mlx5_core_destroy_cq(mdev, &cq->mcq);
1334 }
1335
1336 static int mlx5e_open_cq(struct mlx5e_channel *c,
1337 struct mlx5e_cq_param *param,
1338 struct mlx5e_cq *cq,
1339 struct mlx5e_cq_moder moderation)
1340 {
1341 int err;
1342 struct mlx5e_priv *priv = c->priv;
1343 struct mlx5_core_dev *mdev = priv->mdev;
1344
1345 err = mlx5e_create_cq(c, param, cq);
1346 if (err)
1347 return err;
1348
1349 err = mlx5e_enable_cq(cq, param);
1350 if (err)
1351 goto err_destroy_cq;
1352
1353 if (MLX5_CAP_GEN(mdev, cq_moderation))
1354 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1355 moderation.usec,
1356 moderation.pkts);
1357 return 0;
1358
1359 err_destroy_cq:
1360 mlx5e_destroy_cq(cq);
1361
1362 return err;
1363 }
1364
1365 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1366 {
1367 mlx5e_disable_cq(cq);
1368 mlx5e_destroy_cq(cq);
1369 }
1370
1371 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1372 {
1373 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1374 }
1375
1376 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1377 struct mlx5e_channel_param *cparam)
1378 {
1379 struct mlx5e_priv *priv = c->priv;
1380 int err;
1381 int tc;
1382
1383 for (tc = 0; tc < c->num_tc; tc++) {
1384 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1385 priv->params.tx_cq_moderation);
1386 if (err)
1387 goto err_close_tx_cqs;
1388 }
1389
1390 return 0;
1391
1392 err_close_tx_cqs:
1393 for (tc--; tc >= 0; tc--)
1394 mlx5e_close_cq(&c->sq[tc].cq);
1395
1396 return err;
1397 }
1398
1399 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1400 {
1401 int tc;
1402
1403 for (tc = 0; tc < c->num_tc; tc++)
1404 mlx5e_close_cq(&c->sq[tc].cq);
1405 }
1406
1407 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1408 struct mlx5e_channel_param *cparam)
1409 {
1410 int err;
1411 int tc;
1412
1413 for (tc = 0; tc < c->num_tc; tc++) {
1414 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1415 if (err)
1416 goto err_close_sqs;
1417 }
1418
1419 return 0;
1420
1421 err_close_sqs:
1422 for (tc--; tc >= 0; tc--)
1423 mlx5e_close_sq(&c->sq[tc]);
1424
1425 return err;
1426 }
1427
1428 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1429 {
1430 int tc;
1431
1432 for (tc = 0; tc < c->num_tc; tc++)
1433 mlx5e_close_sq(&c->sq[tc]);
1434 }
1435
1436 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1437 {
1438 int i;
1439
1440 for (i = 0; i < priv->profile->max_tc; i++)
1441 priv->channeltc_to_txq_map[ix][i] =
1442 ix + i * priv->params.num_channels;
1443 }
1444
1445 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1446 struct mlx5e_sq *sq, u32 rate)
1447 {
1448 struct mlx5e_priv *priv = netdev_priv(dev);
1449 struct mlx5_core_dev *mdev = priv->mdev;
1450 u16 rl_index = 0;
1451 int err;
1452
1453 if (rate == sq->rate_limit)
1454 /* nothing to do */
1455 return 0;
1456
1457 if (sq->rate_limit)
1458 /* remove current rl index to free space to next ones */
1459 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1460
1461 sq->rate_limit = 0;
1462
1463 if (rate) {
1464 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1465 if (err) {
1466 netdev_err(dev, "Failed configuring rate %u: %d\n",
1467 rate, err);
1468 return err;
1469 }
1470 }
1471
1472 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1473 MLX5_SQC_STATE_RDY, true, rl_index);
1474 if (err) {
1475 netdev_err(dev, "Failed configuring rate %u: %d\n",
1476 rate, err);
1477 /* remove the rate from the table */
1478 if (rate)
1479 mlx5_rl_remove_rate(mdev, rate);
1480 return err;
1481 }
1482
1483 sq->rate_limit = rate;
1484 return 0;
1485 }
1486
1487 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1488 {
1489 struct mlx5e_priv *priv = netdev_priv(dev);
1490 struct mlx5_core_dev *mdev = priv->mdev;
1491 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1492 int err = 0;
1493
1494 if (!mlx5_rl_is_supported(mdev)) {
1495 netdev_err(dev, "Rate limiting is not supported on this device\n");
1496 return -EINVAL;
1497 }
1498
1499 /* rate is given in Mb/sec, HW config is in Kb/sec */
1500 rate = rate << 10;
1501
1502 /* Check whether rate in valid range, 0 is always valid */
1503 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1504 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1505 return -ERANGE;
1506 }
1507
1508 mutex_lock(&priv->state_lock);
1509 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1510 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1511 if (!err)
1512 priv->tx_rates[index] = rate;
1513 mutex_unlock(&priv->state_lock);
1514
1515 return err;
1516 }
1517
1518 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
1519 {
1520 return is_kdump_kernel() ?
1521 MLX5E_MIN_NUM_CHANNELS :
1522 min_t(int, mdev->priv.eq_table.num_comp_vectors,
1523 MLX5E_MAX_NUM_CHANNELS);
1524 }
1525
1526 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1527 struct mlx5e_channel_param *cparam,
1528 struct mlx5e_channel **cp)
1529 {
1530 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1531 struct net_device *netdev = priv->netdev;
1532 struct mlx5e_cq_moder rx_cq_profile;
1533 int cpu = mlx5e_get_cpu(priv, ix);
1534 struct mlx5e_channel *c;
1535 struct mlx5e_sq *sq;
1536 int err;
1537 int i;
1538
1539 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1540 if (!c)
1541 return -ENOMEM;
1542
1543 c->priv = priv;
1544 c->ix = ix;
1545 c->cpu = cpu;
1546 c->pdev = &priv->mdev->pdev->dev;
1547 c->netdev = priv->netdev;
1548 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1549 c->num_tc = priv->params.num_tc;
1550 c->xdp = !!priv->xdp_prog;
1551
1552 if (priv->params.rx_am_enabled)
1553 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1554 else
1555 rx_cq_profile = priv->params.rx_cq_moderation;
1556
1557 mlx5e_build_channeltc_to_txq_map(priv, ix);
1558
1559 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1560
1561 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1562 if (err)
1563 goto err_napi_del;
1564
1565 err = mlx5e_open_tx_cqs(c, cparam);
1566 if (err)
1567 goto err_close_icosq_cq;
1568
1569 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1570 rx_cq_profile);
1571 if (err)
1572 goto err_close_tx_cqs;
1573
1574 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1575 err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1576 priv->params.tx_cq_moderation) : 0;
1577 if (err)
1578 goto err_close_rx_cq;
1579
1580 napi_enable(&c->napi);
1581
1582 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1583 if (err)
1584 goto err_disable_napi;
1585
1586 err = mlx5e_open_sqs(c, cparam);
1587 if (err)
1588 goto err_close_icosq;
1589
1590 for (i = 0; i < priv->params.num_tc; i++) {
1591 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1592
1593 if (priv->tx_rates[txq_ix]) {
1594 sq = priv->txq_to_sq_map[txq_ix];
1595 mlx5e_set_sq_maxrate(priv->netdev, sq,
1596 priv->tx_rates[txq_ix]);
1597 }
1598 }
1599
1600 err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1601 if (err)
1602 goto err_close_sqs;
1603
1604 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1605 if (err)
1606 goto err_close_xdp_sq;
1607
1608 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1609 *cp = c;
1610
1611 return 0;
1612 err_close_xdp_sq:
1613 if (c->xdp)
1614 mlx5e_close_sq(&c->xdp_sq);
1615
1616 err_close_sqs:
1617 mlx5e_close_sqs(c);
1618
1619 err_close_icosq:
1620 mlx5e_close_sq(&c->icosq);
1621
1622 err_disable_napi:
1623 napi_disable(&c->napi);
1624 if (c->xdp)
1625 mlx5e_close_cq(&c->xdp_sq.cq);
1626
1627 err_close_rx_cq:
1628 mlx5e_close_cq(&c->rq.cq);
1629
1630 err_close_tx_cqs:
1631 mlx5e_close_tx_cqs(c);
1632
1633 err_close_icosq_cq:
1634 mlx5e_close_cq(&c->icosq.cq);
1635
1636 err_napi_del:
1637 netif_napi_del(&c->napi);
1638 kfree(c);
1639
1640 return err;
1641 }
1642
1643 static void mlx5e_close_channel(struct mlx5e_channel *c)
1644 {
1645 mlx5e_close_rq(&c->rq);
1646 if (c->xdp)
1647 mlx5e_close_sq(&c->xdp_sq);
1648 mlx5e_close_sqs(c);
1649 mlx5e_close_sq(&c->icosq);
1650 napi_disable(&c->napi);
1651 if (c->xdp)
1652 mlx5e_close_cq(&c->xdp_sq.cq);
1653 mlx5e_close_cq(&c->rq.cq);
1654 mlx5e_close_tx_cqs(c);
1655 mlx5e_close_cq(&c->icosq.cq);
1656 netif_napi_del(&c->napi);
1657
1658 kfree(c);
1659 }
1660
1661 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1662 struct mlx5e_rq_param *param)
1663 {
1664 void *rqc = param->rqc;
1665 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1666
1667 switch (priv->params.rq_wq_type) {
1668 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1669 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1670 priv->params.mpwqe_log_num_strides - 9);
1671 MLX5_SET(wq, wq, log_wqe_stride_size,
1672 priv->params.mpwqe_log_stride_sz - 6);
1673 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1674 break;
1675 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1676 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1677 }
1678
1679 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1680 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1681 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1682 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1683 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1684
1685 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1686 param->wq.linear = 1;
1687
1688 param->am_enabled = priv->params.rx_am_enabled;
1689 }
1690
1691 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1692 {
1693 void *rqc = param->rqc;
1694 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1695
1696 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1697 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1698 }
1699
1700 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1701 struct mlx5e_sq_param *param)
1702 {
1703 void *sqc = param->sqc;
1704 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1705
1706 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1707 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1708
1709 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1710 }
1711
1712 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1713 struct mlx5e_sq_param *param)
1714 {
1715 void *sqc = param->sqc;
1716 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1717
1718 mlx5e_build_sq_param_common(priv, param);
1719 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1720
1721 param->max_inline = priv->params.tx_max_inline;
1722 param->min_inline_mode = priv->params.tx_min_inline_mode;
1723 param->type = MLX5E_SQ_TXQ;
1724 }
1725
1726 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1727 struct mlx5e_cq_param *param)
1728 {
1729 void *cqc = param->cqc;
1730
1731 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1732 }
1733
1734 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1735 struct mlx5e_cq_param *param)
1736 {
1737 void *cqc = param->cqc;
1738 u8 log_cq_size;
1739
1740 switch (priv->params.rq_wq_type) {
1741 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1742 log_cq_size = priv->params.log_rq_size +
1743 priv->params.mpwqe_log_num_strides;
1744 break;
1745 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1746 log_cq_size = priv->params.log_rq_size;
1747 }
1748
1749 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1750 if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1751 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1752 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1753 }
1754
1755 mlx5e_build_common_cq_param(priv, param);
1756
1757 param->cq_period_mode = priv->params.rx_cq_period_mode;
1758 }
1759
1760 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1761 struct mlx5e_cq_param *param)
1762 {
1763 void *cqc = param->cqc;
1764
1765 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1766
1767 mlx5e_build_common_cq_param(priv, param);
1768
1769 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1770 }
1771
1772 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1773 struct mlx5e_cq_param *param,
1774 u8 log_wq_size)
1775 {
1776 void *cqc = param->cqc;
1777
1778 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1779
1780 mlx5e_build_common_cq_param(priv, param);
1781
1782 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1783 }
1784
1785 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1786 struct mlx5e_sq_param *param,
1787 u8 log_wq_size)
1788 {
1789 void *sqc = param->sqc;
1790 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1791
1792 mlx5e_build_sq_param_common(priv, param);
1793
1794 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1795 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1796
1797 param->type = MLX5E_SQ_ICO;
1798 }
1799
1800 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1801 struct mlx5e_sq_param *param)
1802 {
1803 void *sqc = param->sqc;
1804 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1805
1806 mlx5e_build_sq_param_common(priv, param);
1807 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1808
1809 param->max_inline = priv->params.tx_max_inline;
1810 param->min_inline_mode = priv->params.tx_min_inline_mode;
1811 param->type = MLX5E_SQ_XDP;
1812 }
1813
1814 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1815 {
1816 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1817
1818 mlx5e_build_rq_param(priv, &cparam->rq);
1819 mlx5e_build_sq_param(priv, &cparam->sq);
1820 mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
1821 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1822 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1823 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1824 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1825 }
1826
1827 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1828 {
1829 struct mlx5e_channel_param *cparam;
1830 int nch = priv->params.num_channels;
1831 int err = -ENOMEM;
1832 int i;
1833 int j;
1834
1835 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1836 GFP_KERNEL);
1837
1838 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1839 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1840
1841 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1842
1843 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1844 goto err_free_txq_to_sq_map;
1845
1846 mlx5e_build_channel_param(priv, cparam);
1847
1848 for (i = 0; i < nch; i++) {
1849 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1850 if (err)
1851 goto err_close_channels;
1852 }
1853
1854 for (j = 0; j < nch; j++) {
1855 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1856 if (err)
1857 goto err_close_channels;
1858 }
1859
1860 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1861 * polling for inactive tx queues.
1862 */
1863 netif_tx_start_all_queues(priv->netdev);
1864
1865 kfree(cparam);
1866 return 0;
1867
1868 err_close_channels:
1869 for (i--; i >= 0; i--)
1870 mlx5e_close_channel(priv->channel[i]);
1871
1872 err_free_txq_to_sq_map:
1873 kfree(priv->txq_to_sq_map);
1874 kfree(priv->channel);
1875 kfree(cparam);
1876
1877 return err;
1878 }
1879
1880 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1881 {
1882 int i;
1883
1884 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1885 * polling for inactive tx queues.
1886 */
1887 netif_tx_stop_all_queues(priv->netdev);
1888 netif_tx_disable(priv->netdev);
1889
1890 for (i = 0; i < priv->params.num_channels; i++)
1891 mlx5e_close_channel(priv->channel[i]);
1892
1893 kfree(priv->txq_to_sq_map);
1894 kfree(priv->channel);
1895 }
1896
1897 static int mlx5e_rx_hash_fn(int hfunc)
1898 {
1899 return (hfunc == ETH_RSS_HASH_TOP) ?
1900 MLX5_RX_HASH_FN_TOEPLITZ :
1901 MLX5_RX_HASH_FN_INVERTED_XOR8;
1902 }
1903
1904 static int mlx5e_bits_invert(unsigned long a, int size)
1905 {
1906 int inv = 0;
1907 int i;
1908
1909 for (i = 0; i < size; i++)
1910 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1911
1912 return inv;
1913 }
1914
1915 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1916 {
1917 int i;
1918
1919 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1920 int ix = i;
1921 u32 rqn;
1922
1923 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1924 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1925
1926 ix = priv->params.indirection_rqt[ix];
1927 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1928 priv->channel[ix]->rq.rqn :
1929 priv->drop_rq.rqn;
1930 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1931 }
1932 }
1933
1934 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1935 int ix)
1936 {
1937 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1938 priv->channel[ix]->rq.rqn :
1939 priv->drop_rq.rqn;
1940
1941 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1942 }
1943
1944 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1945 int ix, struct mlx5e_rqt *rqt)
1946 {
1947 struct mlx5_core_dev *mdev = priv->mdev;
1948 void *rqtc;
1949 int inlen;
1950 int err;
1951 u32 *in;
1952
1953 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1954 in = mlx5_vzalloc(inlen);
1955 if (!in)
1956 return -ENOMEM;
1957
1958 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1959
1960 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1961 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1962
1963 if (sz > 1) /* RSS */
1964 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1965 else
1966 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1967
1968 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1969 if (!err)
1970 rqt->enabled = true;
1971
1972 kvfree(in);
1973 return err;
1974 }
1975
1976 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1977 {
1978 rqt->enabled = false;
1979 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1980 }
1981
1982 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1983 {
1984 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1985
1986 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1987 }
1988
1989 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1990 {
1991 struct mlx5e_rqt *rqt;
1992 int err;
1993 int ix;
1994
1995 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1996 rqt = &priv->direct_tir[ix].rqt;
1997 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1998 if (err)
1999 goto err_destroy_rqts;
2000 }
2001
2002 return 0;
2003
2004 err_destroy_rqts:
2005 for (ix--; ix >= 0; ix--)
2006 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2007
2008 return err;
2009 }
2010
2011 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
2012 {
2013 struct mlx5_core_dev *mdev = priv->mdev;
2014 void *rqtc;
2015 int inlen;
2016 u32 *in;
2017 int err;
2018
2019 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2020 in = mlx5_vzalloc(inlen);
2021 if (!in)
2022 return -ENOMEM;
2023
2024 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2025
2026 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2027 if (sz > 1) /* RSS */
2028 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
2029 else
2030 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2031
2032 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2033
2034 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2035
2036 kvfree(in);
2037
2038 return err;
2039 }
2040
2041 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
2042 {
2043 u32 rqtn;
2044 int ix;
2045
2046 if (priv->indir_rqt.enabled) {
2047 rqtn = priv->indir_rqt.rqtn;
2048 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
2049 }
2050
2051 for (ix = 0; ix < priv->params.num_channels; ix++) {
2052 if (!priv->direct_tir[ix].rqt.enabled)
2053 continue;
2054 rqtn = priv->direct_tir[ix].rqt.rqtn;
2055 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
2056 }
2057 }
2058
2059 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
2060 {
2061 if (!priv->params.lro_en)
2062 return;
2063
2064 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2065
2066 MLX5_SET(tirc, tirc, lro_enable_mask,
2067 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2068 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2069 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2070 (priv->params.lro_wqe_sz -
2071 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2072 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
2073 }
2074
2075 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc,
2076 enum mlx5e_traffic_types tt)
2077 {
2078 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2079
2080 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2081 MLX5_HASH_FIELD_SEL_DST_IP)
2082
2083 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2084 MLX5_HASH_FIELD_SEL_DST_IP |\
2085 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2086 MLX5_HASH_FIELD_SEL_L4_DPORT)
2087
2088 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2089 MLX5_HASH_FIELD_SEL_DST_IP |\
2090 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2091
2092 MLX5_SET(tirc, tirc, rx_hash_fn,
2093 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
2094 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
2095 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2096 rx_hash_toeplitz_key);
2097 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2098 rx_hash_toeplitz_key);
2099
2100 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2101 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2102 }
2103
2104 switch (tt) {
2105 case MLX5E_TT_IPV4_TCP:
2106 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2107 MLX5_L3_PROT_TYPE_IPV4);
2108 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2109 MLX5_L4_PROT_TYPE_TCP);
2110 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2111 MLX5_HASH_IP_L4PORTS);
2112 break;
2113
2114 case MLX5E_TT_IPV6_TCP:
2115 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2116 MLX5_L3_PROT_TYPE_IPV6);
2117 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2118 MLX5_L4_PROT_TYPE_TCP);
2119 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2120 MLX5_HASH_IP_L4PORTS);
2121 break;
2122
2123 case MLX5E_TT_IPV4_UDP:
2124 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2125 MLX5_L3_PROT_TYPE_IPV4);
2126 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2127 MLX5_L4_PROT_TYPE_UDP);
2128 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2129 MLX5_HASH_IP_L4PORTS);
2130 break;
2131
2132 case MLX5E_TT_IPV6_UDP:
2133 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2134 MLX5_L3_PROT_TYPE_IPV6);
2135 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2136 MLX5_L4_PROT_TYPE_UDP);
2137 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2138 MLX5_HASH_IP_L4PORTS);
2139 break;
2140
2141 case MLX5E_TT_IPV4_IPSEC_AH:
2142 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2143 MLX5_L3_PROT_TYPE_IPV4);
2144 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2145 MLX5_HASH_IP_IPSEC_SPI);
2146 break;
2147
2148 case MLX5E_TT_IPV6_IPSEC_AH:
2149 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2150 MLX5_L3_PROT_TYPE_IPV6);
2151 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2152 MLX5_HASH_IP_IPSEC_SPI);
2153 break;
2154
2155 case MLX5E_TT_IPV4_IPSEC_ESP:
2156 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2157 MLX5_L3_PROT_TYPE_IPV4);
2158 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2159 MLX5_HASH_IP_IPSEC_SPI);
2160 break;
2161
2162 case MLX5E_TT_IPV6_IPSEC_ESP:
2163 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2164 MLX5_L3_PROT_TYPE_IPV6);
2165 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2166 MLX5_HASH_IP_IPSEC_SPI);
2167 break;
2168
2169 case MLX5E_TT_IPV4:
2170 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2171 MLX5_L3_PROT_TYPE_IPV4);
2172 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2173 MLX5_HASH_IP);
2174 break;
2175
2176 case MLX5E_TT_IPV6:
2177 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2178 MLX5_L3_PROT_TYPE_IPV6);
2179 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2180 MLX5_HASH_IP);
2181 break;
2182 default:
2183 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2184 }
2185 }
2186
2187 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2188 {
2189 struct mlx5_core_dev *mdev = priv->mdev;
2190
2191 void *in;
2192 void *tirc;
2193 int inlen;
2194 int err;
2195 int tt;
2196 int ix;
2197
2198 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2199 in = mlx5_vzalloc(inlen);
2200 if (!in)
2201 return -ENOMEM;
2202
2203 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2204 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2205
2206 mlx5e_build_tir_ctx_lro(tirc, priv);
2207
2208 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2209 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2210 inlen);
2211 if (err)
2212 goto free_in;
2213 }
2214
2215 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2216 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2217 in, inlen);
2218 if (err)
2219 goto free_in;
2220 }
2221
2222 free_in:
2223 kvfree(in);
2224
2225 return err;
2226 }
2227
2228 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2229 {
2230 struct mlx5_core_dev *mdev = priv->mdev;
2231 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2232 int err;
2233
2234 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2235 if (err)
2236 return err;
2237
2238 /* Update vport context MTU */
2239 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2240 return 0;
2241 }
2242
2243 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2244 {
2245 struct mlx5_core_dev *mdev = priv->mdev;
2246 u16 hw_mtu = 0;
2247 int err;
2248
2249 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2250 if (err || !hw_mtu) /* fallback to port oper mtu */
2251 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2252
2253 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2254 }
2255
2256 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2257 {
2258 struct mlx5e_priv *priv = netdev_priv(netdev);
2259 u16 mtu;
2260 int err;
2261
2262 err = mlx5e_set_mtu(priv, netdev->mtu);
2263 if (err)
2264 return err;
2265
2266 mlx5e_query_mtu(priv, &mtu);
2267 if (mtu != netdev->mtu)
2268 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2269 __func__, mtu, netdev->mtu);
2270
2271 netdev->mtu = mtu;
2272 return 0;
2273 }
2274
2275 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2276 {
2277 struct mlx5e_priv *priv = netdev_priv(netdev);
2278 int nch = priv->params.num_channels;
2279 int ntc = priv->params.num_tc;
2280 int tc;
2281
2282 netdev_reset_tc(netdev);
2283
2284 if (ntc == 1)
2285 return;
2286
2287 netdev_set_num_tc(netdev, ntc);
2288
2289 /* Map netdev TCs to offset 0
2290 * We have our own UP to TXQ mapping for QoS
2291 */
2292 for (tc = 0; tc < ntc; tc++)
2293 netdev_set_tc_queue(netdev, tc, nch, 0);
2294 }
2295
2296 int mlx5e_open_locked(struct net_device *netdev)
2297 {
2298 struct mlx5e_priv *priv = netdev_priv(netdev);
2299 struct mlx5_core_dev *mdev = priv->mdev;
2300 int num_txqs;
2301 int err;
2302
2303 set_bit(MLX5E_STATE_OPENED, &priv->state);
2304
2305 mlx5e_netdev_set_tcs(netdev);
2306
2307 num_txqs = priv->params.num_channels * priv->params.num_tc;
2308 netif_set_real_num_tx_queues(netdev, num_txqs);
2309 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2310
2311 err = mlx5e_open_channels(priv);
2312 if (err) {
2313 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2314 __func__, err);
2315 goto err_clear_state_opened_flag;
2316 }
2317
2318 err = mlx5e_refresh_tirs_self_loopback(priv->mdev, false);
2319 if (err) {
2320 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2321 __func__, err);
2322 goto err_close_channels;
2323 }
2324
2325 mlx5e_redirect_rqts(priv);
2326 mlx5e_update_carrier(priv);
2327 mlx5e_timestamp_init(priv);
2328 #ifdef CONFIG_RFS_ACCEL
2329 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2330 #endif
2331 if (priv->profile->update_stats)
2332 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2333
2334 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2335 err = mlx5e_add_sqs_fwd_rules(priv);
2336 if (err)
2337 goto err_close_channels;
2338 }
2339 return 0;
2340
2341 err_close_channels:
2342 mlx5e_close_channels(priv);
2343 err_clear_state_opened_flag:
2344 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2345 return err;
2346 }
2347
2348 int mlx5e_open(struct net_device *netdev)
2349 {
2350 struct mlx5e_priv *priv = netdev_priv(netdev);
2351 int err;
2352
2353 mutex_lock(&priv->state_lock);
2354 err = mlx5e_open_locked(netdev);
2355 mutex_unlock(&priv->state_lock);
2356
2357 return err;
2358 }
2359
2360 int mlx5e_close_locked(struct net_device *netdev)
2361 {
2362 struct mlx5e_priv *priv = netdev_priv(netdev);
2363 struct mlx5_core_dev *mdev = priv->mdev;
2364
2365 /* May already be CLOSED in case a previous configuration operation
2366 * (e.g RX/TX queue size change) that involves close&open failed.
2367 */
2368 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2369 return 0;
2370
2371 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2372
2373 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2374 mlx5e_remove_sqs_fwd_rules(priv);
2375
2376 mlx5e_timestamp_cleanup(priv);
2377 netif_carrier_off(priv->netdev);
2378 mlx5e_redirect_rqts(priv);
2379 mlx5e_close_channels(priv);
2380
2381 return 0;
2382 }
2383
2384 int mlx5e_close(struct net_device *netdev)
2385 {
2386 struct mlx5e_priv *priv = netdev_priv(netdev);
2387 int err;
2388
2389 if (!netif_device_present(netdev))
2390 return -ENODEV;
2391
2392 mutex_lock(&priv->state_lock);
2393 err = mlx5e_close_locked(netdev);
2394 mutex_unlock(&priv->state_lock);
2395
2396 return err;
2397 }
2398
2399 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2400 struct mlx5e_rq *rq,
2401 struct mlx5e_rq_param *param)
2402 {
2403 struct mlx5_core_dev *mdev = priv->mdev;
2404 void *rqc = param->rqc;
2405 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2406 int err;
2407
2408 param->wq.db_numa_node = param->wq.buf_numa_node;
2409
2410 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2411 &rq->wq_ctrl);
2412 if (err)
2413 return err;
2414
2415 rq->priv = priv;
2416
2417 return 0;
2418 }
2419
2420 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2421 struct mlx5e_cq *cq,
2422 struct mlx5e_cq_param *param)
2423 {
2424 struct mlx5_core_dev *mdev = priv->mdev;
2425 struct mlx5_core_cq *mcq = &cq->mcq;
2426 int eqn_not_used;
2427 unsigned int irqn;
2428 int err;
2429
2430 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2431 &cq->wq_ctrl);
2432 if (err)
2433 return err;
2434
2435 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2436
2437 mcq->cqe_sz = 64;
2438 mcq->set_ci_db = cq->wq_ctrl.db.db;
2439 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2440 *mcq->set_ci_db = 0;
2441 *mcq->arm_db = 0;
2442 mcq->vector = param->eq_ix;
2443 mcq->comp = mlx5e_completion_event;
2444 mcq->event = mlx5e_cq_error_event;
2445 mcq->irqn = irqn;
2446
2447 cq->priv = priv;
2448
2449 return 0;
2450 }
2451
2452 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2453 {
2454 struct mlx5e_cq_param cq_param;
2455 struct mlx5e_rq_param rq_param;
2456 struct mlx5e_rq *rq = &priv->drop_rq;
2457 struct mlx5e_cq *cq = &priv->drop_rq.cq;
2458 int err;
2459
2460 memset(&cq_param, 0, sizeof(cq_param));
2461 memset(&rq_param, 0, sizeof(rq_param));
2462 mlx5e_build_drop_rq_param(&rq_param);
2463
2464 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2465 if (err)
2466 return err;
2467
2468 err = mlx5e_enable_cq(cq, &cq_param);
2469 if (err)
2470 goto err_destroy_cq;
2471
2472 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2473 if (err)
2474 goto err_disable_cq;
2475
2476 err = mlx5e_enable_rq(rq, &rq_param);
2477 if (err)
2478 goto err_destroy_rq;
2479
2480 return 0;
2481
2482 err_destroy_rq:
2483 mlx5e_destroy_rq(&priv->drop_rq);
2484
2485 err_disable_cq:
2486 mlx5e_disable_cq(&priv->drop_rq.cq);
2487
2488 err_destroy_cq:
2489 mlx5e_destroy_cq(&priv->drop_rq.cq);
2490
2491 return err;
2492 }
2493
2494 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2495 {
2496 mlx5e_disable_rq(&priv->drop_rq);
2497 mlx5e_destroy_rq(&priv->drop_rq);
2498 mlx5e_disable_cq(&priv->drop_rq.cq);
2499 mlx5e_destroy_cq(&priv->drop_rq.cq);
2500 }
2501
2502 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2503 {
2504 struct mlx5_core_dev *mdev = priv->mdev;
2505 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2506 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2507
2508 MLX5_SET(tisc, tisc, prio, tc << 1);
2509 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2510
2511 if (mlx5_lag_is_lacp_owner(mdev))
2512 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2513
2514 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2515 }
2516
2517 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2518 {
2519 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2520 }
2521
2522 int mlx5e_create_tises(struct mlx5e_priv *priv)
2523 {
2524 int err;
2525 int tc;
2526
2527 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2528 err = mlx5e_create_tis(priv, tc);
2529 if (err)
2530 goto err_close_tises;
2531 }
2532
2533 return 0;
2534
2535 err_close_tises:
2536 for (tc--; tc >= 0; tc--)
2537 mlx5e_destroy_tis(priv, tc);
2538
2539 return err;
2540 }
2541
2542 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2543 {
2544 int tc;
2545
2546 for (tc = 0; tc < priv->profile->max_tc; tc++)
2547 mlx5e_destroy_tis(priv, tc);
2548 }
2549
2550 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2551 enum mlx5e_traffic_types tt)
2552 {
2553 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2554
2555 mlx5e_build_tir_ctx_lro(tirc, priv);
2556
2557 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2558 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2559 mlx5e_build_indir_tir_ctx_hash(priv, tirc, tt);
2560 }
2561
2562 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2563 u32 rqtn)
2564 {
2565 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2566
2567 mlx5e_build_tir_ctx_lro(tirc, priv);
2568
2569 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2570 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2571 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2572 }
2573
2574 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2575 {
2576 struct mlx5e_tir *tir;
2577 void *tirc;
2578 int inlen;
2579 int err;
2580 u32 *in;
2581 int tt;
2582
2583 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2584 in = mlx5_vzalloc(inlen);
2585 if (!in)
2586 return -ENOMEM;
2587
2588 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2589 memset(in, 0, inlen);
2590 tir = &priv->indir_tir[tt];
2591 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2592 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2593 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2594 if (err)
2595 goto err_destroy_tirs;
2596 }
2597
2598 kvfree(in);
2599
2600 return 0;
2601
2602 err_destroy_tirs:
2603 for (tt--; tt >= 0; tt--)
2604 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2605
2606 kvfree(in);
2607
2608 return err;
2609 }
2610
2611 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2612 {
2613 int nch = priv->profile->max_nch(priv->mdev);
2614 struct mlx5e_tir *tir;
2615 void *tirc;
2616 int inlen;
2617 int err;
2618 u32 *in;
2619 int ix;
2620
2621 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2622 in = mlx5_vzalloc(inlen);
2623 if (!in)
2624 return -ENOMEM;
2625
2626 for (ix = 0; ix < nch; ix++) {
2627 memset(in, 0, inlen);
2628 tir = &priv->direct_tir[ix];
2629 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2630 mlx5e_build_direct_tir_ctx(priv, tirc,
2631 priv->direct_tir[ix].rqt.rqtn);
2632 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2633 if (err)
2634 goto err_destroy_ch_tirs;
2635 }
2636
2637 kvfree(in);
2638
2639 return 0;
2640
2641 err_destroy_ch_tirs:
2642 for (ix--; ix >= 0; ix--)
2643 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2644
2645 kvfree(in);
2646
2647 return err;
2648 }
2649
2650 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2651 {
2652 int i;
2653
2654 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2655 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2656 }
2657
2658 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2659 {
2660 int nch = priv->profile->max_nch(priv->mdev);
2661 int i;
2662
2663 for (i = 0; i < nch; i++)
2664 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2665 }
2666
2667 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2668 {
2669 int err = 0;
2670 int i;
2671
2672 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2673 return 0;
2674
2675 for (i = 0; i < priv->params.num_channels; i++) {
2676 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2677 if (err)
2678 return err;
2679 }
2680
2681 return 0;
2682 }
2683
2684 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2685 {
2686 struct mlx5e_priv *priv = netdev_priv(netdev);
2687 bool was_opened;
2688 int err = 0;
2689
2690 if (tc && tc != MLX5E_MAX_NUM_TC)
2691 return -EINVAL;
2692
2693 mutex_lock(&priv->state_lock);
2694
2695 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2696 if (was_opened)
2697 mlx5e_close_locked(priv->netdev);
2698
2699 priv->params.num_tc = tc ? tc : 1;
2700
2701 if (was_opened)
2702 err = mlx5e_open_locked(priv->netdev);
2703
2704 mutex_unlock(&priv->state_lock);
2705
2706 return err;
2707 }
2708
2709 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2710 __be16 proto, struct tc_to_netdev *tc)
2711 {
2712 struct mlx5e_priv *priv = netdev_priv(dev);
2713
2714 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2715 goto mqprio;
2716
2717 switch (tc->type) {
2718 case TC_SETUP_CLSFLOWER:
2719 switch (tc->cls_flower->command) {
2720 case TC_CLSFLOWER_REPLACE:
2721 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2722 case TC_CLSFLOWER_DESTROY:
2723 return mlx5e_delete_flower(priv, tc->cls_flower);
2724 case TC_CLSFLOWER_STATS:
2725 return mlx5e_stats_flower(priv, tc->cls_flower);
2726 }
2727 default:
2728 return -EOPNOTSUPP;
2729 }
2730
2731 mqprio:
2732 if (tc->type != TC_SETUP_MQPRIO)
2733 return -EINVAL;
2734
2735 return mlx5e_setup_tc(dev, tc->tc);
2736 }
2737
2738 static void
2739 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2740 {
2741 struct mlx5e_priv *priv = netdev_priv(dev);
2742 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2743 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2744 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2745
2746 if (mlx5e_is_uplink_rep(priv)) {
2747 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2748 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
2749 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2750 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2751 } else {
2752 stats->rx_packets = sstats->rx_packets;
2753 stats->rx_bytes = sstats->rx_bytes;
2754 stats->tx_packets = sstats->tx_packets;
2755 stats->tx_bytes = sstats->tx_bytes;
2756 stats->tx_dropped = sstats->tx_queue_dropped;
2757 }
2758
2759 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2760
2761 stats->rx_length_errors =
2762 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2763 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2764 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2765 stats->rx_crc_errors =
2766 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2767 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2768 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2769 stats->tx_carrier_errors =
2770 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2771 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2772 stats->rx_frame_errors;
2773 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2774
2775 /* vport multicast also counts packets that are dropped due to steering
2776 * or rx out of buffer
2777 */
2778 stats->multicast =
2779 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2780
2781 }
2782
2783 static void mlx5e_set_rx_mode(struct net_device *dev)
2784 {
2785 struct mlx5e_priv *priv = netdev_priv(dev);
2786
2787 queue_work(priv->wq, &priv->set_rx_mode_work);
2788 }
2789
2790 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2791 {
2792 struct mlx5e_priv *priv = netdev_priv(netdev);
2793 struct sockaddr *saddr = addr;
2794
2795 if (!is_valid_ether_addr(saddr->sa_data))
2796 return -EADDRNOTAVAIL;
2797
2798 netif_addr_lock_bh(netdev);
2799 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2800 netif_addr_unlock_bh(netdev);
2801
2802 queue_work(priv->wq, &priv->set_rx_mode_work);
2803
2804 return 0;
2805 }
2806
2807 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2808 do { \
2809 if (enable) \
2810 netdev->features |= feature; \
2811 else \
2812 netdev->features &= ~feature; \
2813 } while (0)
2814
2815 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2816
2817 static int set_feature_lro(struct net_device *netdev, bool enable)
2818 {
2819 struct mlx5e_priv *priv = netdev_priv(netdev);
2820 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2821 int err;
2822
2823 mutex_lock(&priv->state_lock);
2824
2825 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2826 mlx5e_close_locked(priv->netdev);
2827
2828 priv->params.lro_en = enable;
2829 err = mlx5e_modify_tirs_lro(priv);
2830 if (err) {
2831 netdev_err(netdev, "lro modify failed, %d\n", err);
2832 priv->params.lro_en = !enable;
2833 }
2834
2835 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2836 mlx5e_open_locked(priv->netdev);
2837
2838 mutex_unlock(&priv->state_lock);
2839
2840 return err;
2841 }
2842
2843 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2844 {
2845 struct mlx5e_priv *priv = netdev_priv(netdev);
2846
2847 if (enable)
2848 mlx5e_enable_vlan_filter(priv);
2849 else
2850 mlx5e_disable_vlan_filter(priv);
2851
2852 return 0;
2853 }
2854
2855 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2856 {
2857 struct mlx5e_priv *priv = netdev_priv(netdev);
2858
2859 if (!enable && mlx5e_tc_num_filters(priv)) {
2860 netdev_err(netdev,
2861 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2862 return -EINVAL;
2863 }
2864
2865 return 0;
2866 }
2867
2868 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2869 {
2870 struct mlx5e_priv *priv = netdev_priv(netdev);
2871 struct mlx5_core_dev *mdev = priv->mdev;
2872
2873 return mlx5_set_port_fcs(mdev, !enable);
2874 }
2875
2876 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2877 {
2878 struct mlx5e_priv *priv = netdev_priv(netdev);
2879 int err;
2880
2881 mutex_lock(&priv->state_lock);
2882
2883 priv->params.vlan_strip_disable = !enable;
2884 err = mlx5e_modify_rqs_vsd(priv, !enable);
2885 if (err)
2886 priv->params.vlan_strip_disable = enable;
2887
2888 mutex_unlock(&priv->state_lock);
2889
2890 return err;
2891 }
2892
2893 #ifdef CONFIG_RFS_ACCEL
2894 static int set_feature_arfs(struct net_device *netdev, bool enable)
2895 {
2896 struct mlx5e_priv *priv = netdev_priv(netdev);
2897 int err;
2898
2899 if (enable)
2900 err = mlx5e_arfs_enable(priv);
2901 else
2902 err = mlx5e_arfs_disable(priv);
2903
2904 return err;
2905 }
2906 #endif
2907
2908 static int mlx5e_handle_feature(struct net_device *netdev,
2909 netdev_features_t wanted_features,
2910 netdev_features_t feature,
2911 mlx5e_feature_handler feature_handler)
2912 {
2913 netdev_features_t changes = wanted_features ^ netdev->features;
2914 bool enable = !!(wanted_features & feature);
2915 int err;
2916
2917 if (!(changes & feature))
2918 return 0;
2919
2920 err = feature_handler(netdev, enable);
2921 if (err) {
2922 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2923 enable ? "Enable" : "Disable", feature, err);
2924 return err;
2925 }
2926
2927 MLX5E_SET_FEATURE(netdev, feature, enable);
2928 return 0;
2929 }
2930
2931 static int mlx5e_set_features(struct net_device *netdev,
2932 netdev_features_t features)
2933 {
2934 int err;
2935
2936 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2937 set_feature_lro);
2938 err |= mlx5e_handle_feature(netdev, features,
2939 NETIF_F_HW_VLAN_CTAG_FILTER,
2940 set_feature_vlan_filter);
2941 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2942 set_feature_tc_num_filters);
2943 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2944 set_feature_rx_all);
2945 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2946 set_feature_rx_vlan);
2947 #ifdef CONFIG_RFS_ACCEL
2948 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2949 set_feature_arfs);
2950 #endif
2951
2952 return err ? -EINVAL : 0;
2953 }
2954
2955 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2956 {
2957 struct mlx5e_priv *priv = netdev_priv(netdev);
2958 bool was_opened;
2959 int err = 0;
2960 bool reset;
2961
2962 mutex_lock(&priv->state_lock);
2963
2964 reset = !priv->params.lro_en &&
2965 (priv->params.rq_wq_type !=
2966 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2967
2968 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2969 if (was_opened && reset)
2970 mlx5e_close_locked(netdev);
2971
2972 netdev->mtu = new_mtu;
2973 mlx5e_set_dev_port_mtu(netdev);
2974
2975 if (was_opened && reset)
2976 err = mlx5e_open_locked(netdev);
2977
2978 mutex_unlock(&priv->state_lock);
2979
2980 return err;
2981 }
2982
2983 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2984 {
2985 switch (cmd) {
2986 case SIOCSHWTSTAMP:
2987 return mlx5e_hwstamp_set(dev, ifr);
2988 case SIOCGHWTSTAMP:
2989 return mlx5e_hwstamp_get(dev, ifr);
2990 default:
2991 return -EOPNOTSUPP;
2992 }
2993 }
2994
2995 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2996 {
2997 struct mlx5e_priv *priv = netdev_priv(dev);
2998 struct mlx5_core_dev *mdev = priv->mdev;
2999
3000 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3001 }
3002
3003 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3004 __be16 vlan_proto)
3005 {
3006 struct mlx5e_priv *priv = netdev_priv(dev);
3007 struct mlx5_core_dev *mdev = priv->mdev;
3008
3009 if (vlan_proto != htons(ETH_P_8021Q))
3010 return -EPROTONOSUPPORT;
3011
3012 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3013 vlan, qos);
3014 }
3015
3016 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3017 {
3018 struct mlx5e_priv *priv = netdev_priv(dev);
3019 struct mlx5_core_dev *mdev = priv->mdev;
3020
3021 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3022 }
3023
3024 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3025 {
3026 struct mlx5e_priv *priv = netdev_priv(dev);
3027 struct mlx5_core_dev *mdev = priv->mdev;
3028
3029 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3030 }
3031
3032 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3033 int max_tx_rate)
3034 {
3035 struct mlx5e_priv *priv = netdev_priv(dev);
3036 struct mlx5_core_dev *mdev = priv->mdev;
3037
3038 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3039 max_tx_rate, min_tx_rate);
3040 }
3041
3042 static int mlx5_vport_link2ifla(u8 esw_link)
3043 {
3044 switch (esw_link) {
3045 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3046 return IFLA_VF_LINK_STATE_DISABLE;
3047 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3048 return IFLA_VF_LINK_STATE_ENABLE;
3049 }
3050 return IFLA_VF_LINK_STATE_AUTO;
3051 }
3052
3053 static int mlx5_ifla_link2vport(u8 ifla_link)
3054 {
3055 switch (ifla_link) {
3056 case IFLA_VF_LINK_STATE_DISABLE:
3057 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3058 case IFLA_VF_LINK_STATE_ENABLE:
3059 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3060 }
3061 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3062 }
3063
3064 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3065 int link_state)
3066 {
3067 struct mlx5e_priv *priv = netdev_priv(dev);
3068 struct mlx5_core_dev *mdev = priv->mdev;
3069
3070 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3071 mlx5_ifla_link2vport(link_state));
3072 }
3073
3074 static int mlx5e_get_vf_config(struct net_device *dev,
3075 int vf, struct ifla_vf_info *ivi)
3076 {
3077 struct mlx5e_priv *priv = netdev_priv(dev);
3078 struct mlx5_core_dev *mdev = priv->mdev;
3079 int err;
3080
3081 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3082 if (err)
3083 return err;
3084 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3085 return 0;
3086 }
3087
3088 static int mlx5e_get_vf_stats(struct net_device *dev,
3089 int vf, struct ifla_vf_stats *vf_stats)
3090 {
3091 struct mlx5e_priv *priv = netdev_priv(dev);
3092 struct mlx5_core_dev *mdev = priv->mdev;
3093
3094 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3095 vf_stats);
3096 }
3097
3098 void mlx5e_add_vxlan_port(struct net_device *netdev,
3099 struct udp_tunnel_info *ti)
3100 {
3101 struct mlx5e_priv *priv = netdev_priv(netdev);
3102
3103 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3104 return;
3105
3106 if (!mlx5e_vxlan_allowed(priv->mdev))
3107 return;
3108
3109 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3110 }
3111
3112 void mlx5e_del_vxlan_port(struct net_device *netdev,
3113 struct udp_tunnel_info *ti)
3114 {
3115 struct mlx5e_priv *priv = netdev_priv(netdev);
3116
3117 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3118 return;
3119
3120 if (!mlx5e_vxlan_allowed(priv->mdev))
3121 return;
3122
3123 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3124 }
3125
3126 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3127 struct sk_buff *skb,
3128 netdev_features_t features)
3129 {
3130 struct udphdr *udph;
3131 u16 proto;
3132 u16 port = 0;
3133
3134 switch (vlan_get_protocol(skb)) {
3135 case htons(ETH_P_IP):
3136 proto = ip_hdr(skb)->protocol;
3137 break;
3138 case htons(ETH_P_IPV6):
3139 proto = ipv6_hdr(skb)->nexthdr;
3140 break;
3141 default:
3142 goto out;
3143 }
3144
3145 if (proto == IPPROTO_UDP) {
3146 udph = udp_hdr(skb);
3147 port = be16_to_cpu(udph->dest);
3148 }
3149
3150 /* Verify if UDP port is being offloaded by HW */
3151 if (port && mlx5e_vxlan_lookup_port(priv, port))
3152 return features;
3153
3154 out:
3155 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3156 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3157 }
3158
3159 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3160 struct net_device *netdev,
3161 netdev_features_t features)
3162 {
3163 struct mlx5e_priv *priv = netdev_priv(netdev);
3164
3165 features = vlan_features_check(skb, features);
3166 features = vxlan_features_check(skb, features);
3167
3168 /* Validate if the tunneled packet is being offloaded by HW */
3169 if (skb->encapsulation &&
3170 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3171 return mlx5e_vxlan_features_check(priv, skb, features);
3172
3173 return features;
3174 }
3175
3176 static void mlx5e_tx_timeout(struct net_device *dev)
3177 {
3178 struct mlx5e_priv *priv = netdev_priv(dev);
3179 bool sched_work = false;
3180 int i;
3181
3182 netdev_err(dev, "TX timeout detected\n");
3183
3184 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3185 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3186
3187 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3188 continue;
3189 sched_work = true;
3190 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3191 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3192 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3193 }
3194
3195 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3196 schedule_work(&priv->tx_timeout_work);
3197 }
3198
3199 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3200 {
3201 struct mlx5e_priv *priv = netdev_priv(netdev);
3202 struct bpf_prog *old_prog;
3203 int err = 0;
3204 bool reset, was_opened;
3205 int i;
3206
3207 mutex_lock(&priv->state_lock);
3208
3209 if ((netdev->features & NETIF_F_LRO) && prog) {
3210 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3211 err = -EINVAL;
3212 goto unlock;
3213 }
3214
3215 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3216 /* no need for full reset when exchanging programs */
3217 reset = (!priv->xdp_prog || !prog);
3218
3219 if (was_opened && reset)
3220 mlx5e_close_locked(netdev);
3221 if (was_opened && !reset) {
3222 /* num_channels is invariant here, so we can take the
3223 * batched reference right upfront.
3224 */
3225 prog = bpf_prog_add(prog, priv->params.num_channels);
3226 if (IS_ERR(prog)) {
3227 err = PTR_ERR(prog);
3228 goto unlock;
3229 }
3230 }
3231
3232 /* exchange programs, extra prog reference we got from caller
3233 * as long as we don't fail from this point onwards.
3234 */
3235 old_prog = xchg(&priv->xdp_prog, prog);
3236 if (old_prog)
3237 bpf_prog_put(old_prog);
3238
3239 if (reset) /* change RQ type according to priv->xdp_prog */
3240 mlx5e_set_rq_priv_params(priv);
3241
3242 if (was_opened && reset)
3243 mlx5e_open_locked(netdev);
3244
3245 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3246 goto unlock;
3247
3248 /* exchanging programs w/o reset, we update ref counts on behalf
3249 * of the channels RQs here.
3250 */
3251 for (i = 0; i < priv->params.num_channels; i++) {
3252 struct mlx5e_channel *c = priv->channel[i];
3253
3254 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3255 napi_synchronize(&c->napi);
3256 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3257
3258 old_prog = xchg(&c->rq.xdp_prog, prog);
3259
3260 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3261 /* napi_schedule in case we have missed anything */
3262 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3263 napi_schedule(&c->napi);
3264
3265 if (old_prog)
3266 bpf_prog_put(old_prog);
3267 }
3268
3269 unlock:
3270 mutex_unlock(&priv->state_lock);
3271 return err;
3272 }
3273
3274 static bool mlx5e_xdp_attached(struct net_device *dev)
3275 {
3276 struct mlx5e_priv *priv = netdev_priv(dev);
3277
3278 return !!priv->xdp_prog;
3279 }
3280
3281 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3282 {
3283 switch (xdp->command) {
3284 case XDP_SETUP_PROG:
3285 return mlx5e_xdp_set(dev, xdp->prog);
3286 case XDP_QUERY_PROG:
3287 xdp->prog_attached = mlx5e_xdp_attached(dev);
3288 return 0;
3289 default:
3290 return -EINVAL;
3291 }
3292 }
3293
3294 #ifdef CONFIG_NET_POLL_CONTROLLER
3295 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3296 * reenabling interrupts.
3297 */
3298 static void mlx5e_netpoll(struct net_device *dev)
3299 {
3300 struct mlx5e_priv *priv = netdev_priv(dev);
3301 int i;
3302
3303 for (i = 0; i < priv->params.num_channels; i++)
3304 napi_schedule(&priv->channel[i]->napi);
3305 }
3306 #endif
3307
3308 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3309 .ndo_open = mlx5e_open,
3310 .ndo_stop = mlx5e_close,
3311 .ndo_start_xmit = mlx5e_xmit,
3312 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3313 .ndo_select_queue = mlx5e_select_queue,
3314 .ndo_get_stats64 = mlx5e_get_stats,
3315 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3316 .ndo_set_mac_address = mlx5e_set_mac,
3317 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3318 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3319 .ndo_set_features = mlx5e_set_features,
3320 .ndo_change_mtu = mlx5e_change_mtu,
3321 .ndo_do_ioctl = mlx5e_ioctl,
3322 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3323 #ifdef CONFIG_RFS_ACCEL
3324 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3325 #endif
3326 .ndo_tx_timeout = mlx5e_tx_timeout,
3327 .ndo_xdp = mlx5e_xdp,
3328 #ifdef CONFIG_NET_POLL_CONTROLLER
3329 .ndo_poll_controller = mlx5e_netpoll,
3330 #endif
3331 };
3332
3333 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3334 .ndo_open = mlx5e_open,
3335 .ndo_stop = mlx5e_close,
3336 .ndo_start_xmit = mlx5e_xmit,
3337 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3338 .ndo_select_queue = mlx5e_select_queue,
3339 .ndo_get_stats64 = mlx5e_get_stats,
3340 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3341 .ndo_set_mac_address = mlx5e_set_mac,
3342 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3343 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3344 .ndo_set_features = mlx5e_set_features,
3345 .ndo_change_mtu = mlx5e_change_mtu,
3346 .ndo_do_ioctl = mlx5e_ioctl,
3347 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3348 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3349 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3350 .ndo_features_check = mlx5e_features_check,
3351 #ifdef CONFIG_RFS_ACCEL
3352 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3353 #endif
3354 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3355 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
3356 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
3357 .ndo_set_vf_trust = mlx5e_set_vf_trust,
3358 .ndo_set_vf_rate = mlx5e_set_vf_rate,
3359 .ndo_get_vf_config = mlx5e_get_vf_config,
3360 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3361 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3362 .ndo_tx_timeout = mlx5e_tx_timeout,
3363 .ndo_xdp = mlx5e_xdp,
3364 #ifdef CONFIG_NET_POLL_CONTROLLER
3365 .ndo_poll_controller = mlx5e_netpoll,
3366 #endif
3367 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3368 .ndo_get_offload_stats = mlx5e_get_offload_stats,
3369 };
3370
3371 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3372 {
3373 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3374 return -EOPNOTSUPP;
3375 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3376 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3377 !MLX5_CAP_ETH(mdev, csum_cap) ||
3378 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3379 !MLX5_CAP_ETH(mdev, vlan_cap) ||
3380 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3381 MLX5_CAP_FLOWTABLE(mdev,
3382 flow_table_properties_nic_receive.max_ft_level)
3383 < 3) {
3384 mlx5_core_warn(mdev,
3385 "Not creating net device, some required device capabilities are missing\n");
3386 return -EOPNOTSUPP;
3387 }
3388 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3389 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3390 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3391 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3392
3393 return 0;
3394 }
3395
3396 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3397 {
3398 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3399
3400 return bf_buf_size -
3401 sizeof(struct mlx5e_tx_wqe) +
3402 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3403 }
3404
3405 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3406 u32 *indirection_rqt, int len,
3407 int num_channels)
3408 {
3409 int node = mdev->priv.numa_node;
3410 int node_num_of_cores;
3411 int i;
3412
3413 if (node == -1)
3414 node = first_online_node;
3415
3416 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3417
3418 if (node_num_of_cores)
3419 num_channels = min_t(int, num_channels, node_num_of_cores);
3420
3421 for (i = 0; i < len; i++)
3422 indirection_rqt[i] = i % num_channels;
3423 }
3424
3425 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3426 {
3427 enum pcie_link_width width;
3428 enum pci_bus_speed speed;
3429 int err = 0;
3430
3431 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3432 if (err)
3433 return err;
3434
3435 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3436 return -EINVAL;
3437
3438 switch (speed) {
3439 case PCIE_SPEED_2_5GT:
3440 *pci_bw = 2500 * width;
3441 break;
3442 case PCIE_SPEED_5_0GT:
3443 *pci_bw = 5000 * width;
3444 break;
3445 case PCIE_SPEED_8_0GT:
3446 *pci_bw = 8000 * width;
3447 break;
3448 default:
3449 return -EINVAL;
3450 }
3451
3452 return 0;
3453 }
3454
3455 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3456 {
3457 return (link_speed && pci_bw &&
3458 (pci_bw < 40000) && (pci_bw < link_speed));
3459 }
3460
3461 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3462 {
3463 params->rx_cq_period_mode = cq_period_mode;
3464
3465 params->rx_cq_moderation.pkts =
3466 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3467 params->rx_cq_moderation.usec =
3468 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3469
3470 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3471 params->rx_cq_moderation.usec =
3472 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3473 }
3474
3475 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3476 {
3477 int i;
3478
3479 /* The supported periods are organized in ascending order */
3480 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3481 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3482 break;
3483
3484 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3485 }
3486
3487 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3488 struct net_device *netdev,
3489 const struct mlx5e_profile *profile,
3490 void *ppriv)
3491 {
3492 struct mlx5e_priv *priv = netdev_priv(netdev);
3493 u32 link_speed = 0;
3494 u32 pci_bw = 0;
3495 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3496 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3497 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3498
3499 priv->mdev = mdev;
3500 priv->netdev = netdev;
3501 priv->params.num_channels = profile->max_nch(mdev);
3502 priv->profile = profile;
3503 priv->ppriv = ppriv;
3504
3505 priv->params.lro_timeout =
3506 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3507
3508 priv->params.log_sq_size = is_kdump_kernel() ?
3509 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3510 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3511
3512 /* set CQE compression */
3513 priv->params.rx_cqe_compress_def = false;
3514 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3515 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3516 mlx5e_get_max_linkspeed(mdev, &link_speed);
3517 mlx5e_get_pci_bw(mdev, &pci_bw);
3518 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3519 link_speed, pci_bw);
3520 priv->params.rx_cqe_compress_def =
3521 cqe_compress_heuristic(link_speed, pci_bw);
3522 }
3523
3524 mlx5e_set_rq_priv_params(priv);
3525 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3526 priv->params.lro_en = true;
3527
3528 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3529 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3530
3531 priv->params.tx_cq_moderation.usec =
3532 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3533 priv->params.tx_cq_moderation.pkts =
3534 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3535 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3536 mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3537 if (priv->params.tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
3538 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
3539 priv->params.tx_min_inline_mode = MLX5_INLINE_MODE_L2;
3540
3541 priv->params.num_tc = 1;
3542 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
3543
3544 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3545 sizeof(priv->params.toeplitz_hash_key));
3546
3547 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3548 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3549
3550 priv->params.lro_wqe_sz =
3551 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3552 /* Extra room needed for build_skb */
3553 MLX5_RX_HEADROOM -
3554 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3555
3556 /* Initialize pflags */
3557 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3558 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3559 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, priv->params.rx_cqe_compress_def);
3560
3561 mutex_init(&priv->state_lock);
3562
3563 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3564 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3565 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3566 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3567 }
3568
3569 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3570 {
3571 struct mlx5e_priv *priv = netdev_priv(netdev);
3572
3573 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3574 if (is_zero_ether_addr(netdev->dev_addr) &&
3575 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3576 eth_hw_addr_random(netdev);
3577 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3578 }
3579 }
3580
3581 static const struct switchdev_ops mlx5e_switchdev_ops = {
3582 .switchdev_port_attr_get = mlx5e_attr_get,
3583 };
3584
3585 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3586 {
3587 struct mlx5e_priv *priv = netdev_priv(netdev);
3588 struct mlx5_core_dev *mdev = priv->mdev;
3589 bool fcs_supported;
3590 bool fcs_enabled;
3591
3592 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3593
3594 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3595 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3596 #ifdef CONFIG_MLX5_CORE_EN_DCB
3597 if (MLX5_CAP_GEN(mdev, qos))
3598 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3599 #endif
3600 } else {
3601 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3602 }
3603
3604 netdev->watchdog_timeo = 15 * HZ;
3605
3606 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3607
3608 netdev->vlan_features |= NETIF_F_SG;
3609 netdev->vlan_features |= NETIF_F_IP_CSUM;
3610 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3611 netdev->vlan_features |= NETIF_F_GRO;
3612 netdev->vlan_features |= NETIF_F_TSO;
3613 netdev->vlan_features |= NETIF_F_TSO6;
3614 netdev->vlan_features |= NETIF_F_RXCSUM;
3615 netdev->vlan_features |= NETIF_F_RXHASH;
3616
3617 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3618 netdev->vlan_features |= NETIF_F_LRO;
3619
3620 netdev->hw_features = netdev->vlan_features;
3621 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
3622 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3623 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3624
3625 if (mlx5e_vxlan_allowed(mdev)) {
3626 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3627 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3628 NETIF_F_GSO_PARTIAL;
3629 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3630 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3631 netdev->hw_enc_features |= NETIF_F_TSO;
3632 netdev->hw_enc_features |= NETIF_F_TSO6;
3633 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3634 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3635 NETIF_F_GSO_PARTIAL;
3636 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3637 }
3638
3639 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3640
3641 if (fcs_supported)
3642 netdev->hw_features |= NETIF_F_RXALL;
3643
3644 netdev->features = netdev->hw_features;
3645 if (!priv->params.lro_en)
3646 netdev->features &= ~NETIF_F_LRO;
3647
3648 if (fcs_enabled)
3649 netdev->features &= ~NETIF_F_RXALL;
3650
3651 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3652 if (FT_CAP(flow_modify_en) &&
3653 FT_CAP(modify_root) &&
3654 FT_CAP(identified_miss_table_mode) &&
3655 FT_CAP(flow_table_modify)) {
3656 netdev->hw_features |= NETIF_F_HW_TC;
3657 #ifdef CONFIG_RFS_ACCEL
3658 netdev->hw_features |= NETIF_F_NTUPLE;
3659 #endif
3660 }
3661
3662 netdev->features |= NETIF_F_HIGHDMA;
3663
3664 netdev->priv_flags |= IFF_UNICAST_FLT;
3665
3666 mlx5e_set_netdev_dev_addr(netdev);
3667
3668 #ifdef CONFIG_NET_SWITCHDEV
3669 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3670 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3671 #endif
3672 }
3673
3674 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3675 {
3676 struct mlx5_core_dev *mdev = priv->mdev;
3677 int err;
3678
3679 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3680 if (err) {
3681 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3682 priv->q_counter = 0;
3683 }
3684 }
3685
3686 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3687 {
3688 if (!priv->q_counter)
3689 return;
3690
3691 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3692 }
3693
3694 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3695 struct net_device *netdev,
3696 const struct mlx5e_profile *profile,
3697 void *ppriv)
3698 {
3699 struct mlx5e_priv *priv = netdev_priv(netdev);
3700
3701 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3702 mlx5e_build_nic_netdev(netdev);
3703 mlx5e_vxlan_init(priv);
3704 }
3705
3706 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3707 {
3708 mlx5e_vxlan_cleanup(priv);
3709
3710 if (priv->xdp_prog)
3711 bpf_prog_put(priv->xdp_prog);
3712 }
3713
3714 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3715 {
3716 struct mlx5_core_dev *mdev = priv->mdev;
3717 int err;
3718 int i;
3719
3720 err = mlx5e_create_indirect_rqts(priv);
3721 if (err) {
3722 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3723 return err;
3724 }
3725
3726 err = mlx5e_create_direct_rqts(priv);
3727 if (err) {
3728 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3729 goto err_destroy_indirect_rqts;
3730 }
3731
3732 err = mlx5e_create_indirect_tirs(priv);
3733 if (err) {
3734 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3735 goto err_destroy_direct_rqts;
3736 }
3737
3738 err = mlx5e_create_direct_tirs(priv);
3739 if (err) {
3740 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3741 goto err_destroy_indirect_tirs;
3742 }
3743
3744 err = mlx5e_create_flow_steering(priv);
3745 if (err) {
3746 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3747 goto err_destroy_direct_tirs;
3748 }
3749
3750 err = mlx5e_tc_init(priv);
3751 if (err)
3752 goto err_destroy_flow_steering;
3753
3754 return 0;
3755
3756 err_destroy_flow_steering:
3757 mlx5e_destroy_flow_steering(priv);
3758 err_destroy_direct_tirs:
3759 mlx5e_destroy_direct_tirs(priv);
3760 err_destroy_indirect_tirs:
3761 mlx5e_destroy_indirect_tirs(priv);
3762 err_destroy_direct_rqts:
3763 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3764 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3765 err_destroy_indirect_rqts:
3766 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3767 return err;
3768 }
3769
3770 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3771 {
3772 int i;
3773
3774 mlx5e_tc_cleanup(priv);
3775 mlx5e_destroy_flow_steering(priv);
3776 mlx5e_destroy_direct_tirs(priv);
3777 mlx5e_destroy_indirect_tirs(priv);
3778 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3779 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3780 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3781 }
3782
3783 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3784 {
3785 int err;
3786
3787 err = mlx5e_create_tises(priv);
3788 if (err) {
3789 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3790 return err;
3791 }
3792
3793 #ifdef CONFIG_MLX5_CORE_EN_DCB
3794 mlx5e_dcbnl_initialize(priv);
3795 #endif
3796 return 0;
3797 }
3798
3799 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3800 {
3801 struct net_device *netdev = priv->netdev;
3802 struct mlx5_core_dev *mdev = priv->mdev;
3803 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3804 struct mlx5_eswitch_rep rep;
3805
3806 mlx5_lag_add(mdev, netdev);
3807
3808 mlx5e_enable_async_events(priv);
3809
3810 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3811 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3812 rep.load = mlx5e_nic_rep_load;
3813 rep.unload = mlx5e_nic_rep_unload;
3814 rep.vport = FDB_UPLINK_VPORT;
3815 rep.netdev = netdev;
3816 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
3817 }
3818
3819 if (netdev->reg_state != NETREG_REGISTERED)
3820 return;
3821
3822 /* Device already registered: sync netdev system state */
3823 if (mlx5e_vxlan_allowed(mdev)) {
3824 rtnl_lock();
3825 udp_tunnel_get_rx_info(netdev);
3826 rtnl_unlock();
3827 }
3828
3829 queue_work(priv->wq, &priv->set_rx_mode_work);
3830 }
3831
3832 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3833 {
3834 struct mlx5_core_dev *mdev = priv->mdev;
3835 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3836
3837 queue_work(priv->wq, &priv->set_rx_mode_work);
3838 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3839 mlx5_eswitch_unregister_vport_rep(esw, 0);
3840 mlx5e_disable_async_events(priv);
3841 mlx5_lag_remove(mdev);
3842 }
3843
3844 static const struct mlx5e_profile mlx5e_nic_profile = {
3845 .init = mlx5e_nic_init,
3846 .cleanup = mlx5e_nic_cleanup,
3847 .init_rx = mlx5e_init_nic_rx,
3848 .cleanup_rx = mlx5e_cleanup_nic_rx,
3849 .init_tx = mlx5e_init_nic_tx,
3850 .cleanup_tx = mlx5e_cleanup_nic_tx,
3851 .enable = mlx5e_nic_enable,
3852 .disable = mlx5e_nic_disable,
3853 .update_stats = mlx5e_update_stats,
3854 .max_nch = mlx5e_get_max_num_channels,
3855 .max_tc = MLX5E_MAX_NUM_TC,
3856 };
3857
3858 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3859 const struct mlx5e_profile *profile,
3860 void *ppriv)
3861 {
3862 int nch = profile->max_nch(mdev);
3863 struct net_device *netdev;
3864 struct mlx5e_priv *priv;
3865
3866 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3867 nch * profile->max_tc,
3868 nch);
3869 if (!netdev) {
3870 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3871 return NULL;
3872 }
3873
3874 profile->init(mdev, netdev, profile, ppriv);
3875
3876 netif_carrier_off(netdev);
3877
3878 priv = netdev_priv(netdev);
3879
3880 priv->wq = create_singlethread_workqueue("mlx5e");
3881 if (!priv->wq)
3882 goto err_cleanup_nic;
3883
3884 return netdev;
3885
3886 err_cleanup_nic:
3887 profile->cleanup(priv);
3888 free_netdev(netdev);
3889
3890 return NULL;
3891 }
3892
3893 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3894 {
3895 const struct mlx5e_profile *profile;
3896 struct mlx5e_priv *priv;
3897 u16 max_mtu;
3898 int err;
3899
3900 priv = netdev_priv(netdev);
3901 profile = priv->profile;
3902 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
3903
3904 err = profile->init_tx(priv);
3905 if (err)
3906 goto out;
3907
3908 err = mlx5e_open_drop_rq(priv);
3909 if (err) {
3910 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3911 goto err_cleanup_tx;
3912 }
3913
3914 err = profile->init_rx(priv);
3915 if (err)
3916 goto err_close_drop_rq;
3917
3918 mlx5e_create_q_counter(priv);
3919
3920 mlx5e_init_l2_addr(priv);
3921
3922 /* MTU range: 68 - hw-specific max */
3923 netdev->min_mtu = ETH_MIN_MTU;
3924 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
3925 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
3926
3927 mlx5e_set_dev_port_mtu(netdev);
3928
3929 if (profile->enable)
3930 profile->enable(priv);
3931
3932 rtnl_lock();
3933 if (netif_running(netdev))
3934 mlx5e_open(netdev);
3935 netif_device_attach(netdev);
3936 rtnl_unlock();
3937
3938 return 0;
3939
3940 err_close_drop_rq:
3941 mlx5e_close_drop_rq(priv);
3942
3943 err_cleanup_tx:
3944 profile->cleanup_tx(priv);
3945
3946 out:
3947 return err;
3948 }
3949
3950 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3951 {
3952 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3953 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3954 int vport;
3955 u8 mac[ETH_ALEN];
3956
3957 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3958 return;
3959
3960 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3961
3962 for (vport = 1; vport < total_vfs; vport++) {
3963 struct mlx5_eswitch_rep rep;
3964
3965 rep.load = mlx5e_vport_rep_load;
3966 rep.unload = mlx5e_vport_rep_unload;
3967 rep.vport = vport;
3968 ether_addr_copy(rep.hw_id, mac);
3969 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
3970 }
3971 }
3972
3973 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3974 {
3975 struct mlx5e_priv *priv = netdev_priv(netdev);
3976 const struct mlx5e_profile *profile = priv->profile;
3977
3978 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3979
3980 rtnl_lock();
3981 if (netif_running(netdev))
3982 mlx5e_close(netdev);
3983 netif_device_detach(netdev);
3984 rtnl_unlock();
3985
3986 if (profile->disable)
3987 profile->disable(priv);
3988 flush_workqueue(priv->wq);
3989
3990 mlx5e_destroy_q_counter(priv);
3991 profile->cleanup_rx(priv);
3992 mlx5e_close_drop_rq(priv);
3993 profile->cleanup_tx(priv);
3994 cancel_delayed_work_sync(&priv->update_stats_work);
3995 }
3996
3997 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3998 * hardware contexts and to connect it to the current netdev.
3999 */
4000 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4001 {
4002 struct mlx5e_priv *priv = vpriv;
4003 struct net_device *netdev = priv->netdev;
4004 int err;
4005
4006 if (netif_device_present(netdev))
4007 return 0;
4008
4009 err = mlx5e_create_mdev_resources(mdev);
4010 if (err)
4011 return err;
4012
4013 err = mlx5e_attach_netdev(mdev, netdev);
4014 if (err) {
4015 mlx5e_destroy_mdev_resources(mdev);
4016 return err;
4017 }
4018
4019 return 0;
4020 }
4021
4022 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4023 {
4024 struct mlx5e_priv *priv = vpriv;
4025 struct net_device *netdev = priv->netdev;
4026
4027 if (!netif_device_present(netdev))
4028 return;
4029
4030 mlx5e_detach_netdev(mdev, netdev);
4031 mlx5e_destroy_mdev_resources(mdev);
4032 }
4033
4034 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4035 {
4036 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4037 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4038 void *ppriv = NULL;
4039 void *priv;
4040 int vport;
4041 int err;
4042 struct net_device *netdev;
4043
4044 err = mlx5e_check_required_hca_cap(mdev);
4045 if (err)
4046 return NULL;
4047
4048 mlx5e_register_vport_rep(mdev);
4049
4050 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4051 ppriv = &esw->offloads.vport_reps[0];
4052
4053 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4054 if (!netdev) {
4055 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4056 goto err_unregister_reps;
4057 }
4058
4059 priv = netdev_priv(netdev);
4060
4061 err = mlx5e_attach(mdev, priv);
4062 if (err) {
4063 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4064 goto err_destroy_netdev;
4065 }
4066
4067 err = register_netdev(netdev);
4068 if (err) {
4069 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4070 goto err_detach;
4071 }
4072
4073 return priv;
4074
4075 err_detach:
4076 mlx5e_detach(mdev, priv);
4077
4078 err_destroy_netdev:
4079 mlx5e_destroy_netdev(mdev, priv);
4080
4081 err_unregister_reps:
4082 for (vport = 1; vport < total_vfs; vport++)
4083 mlx5_eswitch_unregister_vport_rep(esw, vport);
4084
4085 return NULL;
4086 }
4087
4088 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
4089 {
4090 const struct mlx5e_profile *profile = priv->profile;
4091 struct net_device *netdev = priv->netdev;
4092
4093 destroy_workqueue(priv->wq);
4094 if (profile->cleanup)
4095 profile->cleanup(priv);
4096 free_netdev(netdev);
4097 }
4098
4099 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4100 {
4101 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4102 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4103 struct mlx5e_priv *priv = vpriv;
4104 int vport;
4105
4106 for (vport = 1; vport < total_vfs; vport++)
4107 mlx5_eswitch_unregister_vport_rep(esw, vport);
4108
4109 unregister_netdev(priv->netdev);
4110 mlx5e_detach(mdev, vpriv);
4111 mlx5e_destroy_netdev(mdev, priv);
4112 }
4113
4114 static void *mlx5e_get_netdev(void *vpriv)
4115 {
4116 struct mlx5e_priv *priv = vpriv;
4117
4118 return priv->netdev;
4119 }
4120
4121 static struct mlx5_interface mlx5e_interface = {
4122 .add = mlx5e_add,
4123 .remove = mlx5e_remove,
4124 .attach = mlx5e_attach,
4125 .detach = mlx5e_detach,
4126 .event = mlx5e_async_event,
4127 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4128 .get_dev = mlx5e_get_netdev,
4129 };
4130
4131 void mlx5e_init(void)
4132 {
4133 mlx5e_build_ptys2ethtool_map();
4134 mlx5_register_interface(&mlx5e_interface);
4135 }
4136
4137 void mlx5e_cleanup(void)
4138 {
4139 mlx5_unregister_interface(&mlx5e_interface);
4140 }
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