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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include "eswitch.h"
39 #include "en.h"
40 #include "en_tc.h"
41 #include "en_rep.h"
42 #include "en_accel/ipsec.h"
43 #include "en_accel/ipsec_rxtx.h"
44 #include "accel/ipsec.h"
45 #include "vxlan.h"
46
47 struct mlx5e_rq_param {
48 u32 rqc[MLX5_ST_SZ_DW(rqc)];
49 struct mlx5_wq_param wq;
50 };
51
52 struct mlx5e_sq_param {
53 u32 sqc[MLX5_ST_SZ_DW(sqc)];
54 struct mlx5_wq_param wq;
55 };
56
57 struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
61 u8 cq_period_mode;
62 };
63
64 struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
67 struct mlx5e_sq_param xdp_sq;
68 struct mlx5e_sq_param icosq;
69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
71 struct mlx5e_cq_param icosq_cq;
72 };
73
74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75 {
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79 }
80
81 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
82 struct mlx5e_params *params, u8 rq_type)
83 {
84 params->rq_wq_type = rq_type;
85 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
86 switch (params->rq_wq_type) {
87 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
88 params->log_rq_size = is_kdump_kernel() ?
89 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
90 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
91 params->mpwqe_log_stride_sz = MLX5E_MPWQE_STRIDE_SZ(mdev,
92 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
93 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
94 params->mpwqe_log_stride_sz;
95 break;
96 default: /* MLX5_WQ_TYPE_LINKED_LIST */
97 params->log_rq_size = is_kdump_kernel() ?
98 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
99 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
100 params->rq_headroom = params->xdp_prog ?
101 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
102 params->rq_headroom += NET_IP_ALIGN;
103
104 /* Extra room needed for build_skb */
105 params->lro_wqe_sz -= params->rq_headroom +
106 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
107 }
108
109 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
110 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
111 BIT(params->log_rq_size),
112 BIT(params->mpwqe_log_stride_sz),
113 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
114 }
115
116 static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev,
117 struct mlx5e_params *params)
118 {
119 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
120 !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
121 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
122 MLX5_WQ_TYPE_LINKED_LIST;
123 mlx5e_init_rq_type_params(mdev, params, rq_type);
124 }
125
126 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
127 {
128 struct mlx5_core_dev *mdev = priv->mdev;
129 u8 port_state;
130
131 port_state = mlx5_query_vport_state(mdev,
132 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
133 0);
134
135 if (port_state == VPORT_STATE_UP) {
136 netdev_info(priv->netdev, "Link up\n");
137 netif_carrier_on(priv->netdev);
138 } else {
139 netdev_info(priv->netdev, "Link down\n");
140 netif_carrier_off(priv->netdev);
141 }
142 }
143
144 static void mlx5e_update_carrier_work(struct work_struct *work)
145 {
146 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
147 update_carrier_work);
148
149 mutex_lock(&priv->state_lock);
150 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
151 if (priv->profile->update_carrier)
152 priv->profile->update_carrier(priv);
153 mutex_unlock(&priv->state_lock);
154 }
155
156 static void mlx5e_tx_timeout_work(struct work_struct *work)
157 {
158 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
159 tx_timeout_work);
160 int err;
161
162 rtnl_lock();
163 mutex_lock(&priv->state_lock);
164 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
165 goto unlock;
166 mlx5e_close_locked(priv->netdev);
167 err = mlx5e_open_locked(priv->netdev);
168 if (err)
169 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
170 err);
171 unlock:
172 mutex_unlock(&priv->state_lock);
173 rtnl_unlock();
174 }
175
176 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
177 {
178 struct mlx5e_sw_stats temp, *s = &temp;
179 struct mlx5e_rq_stats *rq_stats;
180 struct mlx5e_sq_stats *sq_stats;
181 int i, j;
182
183 memset(s, 0, sizeof(*s));
184 for (i = 0; i < priv->channels.num; i++) {
185 struct mlx5e_channel *c = priv->channels.c[i];
186
187 rq_stats = &c->rq.stats;
188
189 s->rx_packets += rq_stats->packets;
190 s->rx_bytes += rq_stats->bytes;
191 s->rx_lro_packets += rq_stats->lro_packets;
192 s->rx_lro_bytes += rq_stats->lro_bytes;
193 s->rx_ecn_mark += rq_stats->ecn_mark;
194 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
195 s->rx_csum_none += rq_stats->csum_none;
196 s->rx_csum_complete += rq_stats->csum_complete;
197 s->rx_csum_complete_tail += rq_stats->csum_complete_tail;
198 s->rx_csum_complete_tail_slow += rq_stats->csum_complete_tail_slow;
199 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
200 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
201 s->rx_xdp_drop += rq_stats->xdp_drop;
202 s->rx_xdp_tx += rq_stats->xdp_tx;
203 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
204 s->rx_wqe_err += rq_stats->wqe_err;
205 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
206 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
207 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
208 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
209 s->rx_page_reuse += rq_stats->page_reuse;
210 s->rx_cache_reuse += rq_stats->cache_reuse;
211 s->rx_cache_full += rq_stats->cache_full;
212 s->rx_cache_empty += rq_stats->cache_empty;
213 s->rx_cache_busy += rq_stats->cache_busy;
214 s->rx_cache_waive += rq_stats->cache_waive;
215
216 for (j = 0; j < priv->channels.params.num_tc; j++) {
217 sq_stats = &c->sq[j].stats;
218
219 s->tx_packets += sq_stats->packets;
220 s->tx_bytes += sq_stats->bytes;
221 s->tx_tso_packets += sq_stats->tso_packets;
222 s->tx_tso_bytes += sq_stats->tso_bytes;
223 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
224 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
225 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
226 s->tx_queue_stopped += sq_stats->stopped;
227 s->tx_queue_wake += sq_stats->wake;
228 s->tx_queue_dropped += sq_stats->dropped;
229 s->tx_xmit_more += sq_stats->xmit_more;
230 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
231 s->tx_csum_none += sq_stats->csum_none;
232 s->tx_csum_partial += sq_stats->csum_partial;
233 }
234 }
235
236 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
237 priv->stats.pport.phy_counters,
238 counter_set.phys_layer_cntrs.link_down_events);
239 memcpy(&priv->stats.sw, s, sizeof(*s));
240 }
241
242 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
243 {
244 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
245 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
246 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
247 struct mlx5_core_dev *mdev = priv->mdev;
248
249 MLX5_SET(query_vport_counter_in, in, opcode,
250 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
251 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
252 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
253
254 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
255 }
256
257 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
258 {
259 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
260 struct mlx5_core_dev *mdev = priv->mdev;
261 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
262 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
263 int prio;
264 void *out;
265
266 MLX5_SET(ppcnt_reg, in, local_port, 1);
267
268 out = pstats->IEEE_802_3_counters;
269 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
270 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
271
272 if (!full)
273 return;
274
275 out = pstats->RFC_2863_counters;
276 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
277 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
278
279 out = pstats->RFC_2819_counters;
280 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
281 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
282
283 out = pstats->phy_counters;
284 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
285 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
286
287 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
288 out = pstats->phy_statistical_counters;
289 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
290 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
291 }
292
293 if (MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) {
294 out = pstats->eth_ext_counters;
295 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
296 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
297 }
298
299 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
300 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
301 out = pstats->per_prio_counters[prio];
302 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
303 mlx5_core_access_reg(mdev, in, sz, out, sz,
304 MLX5_REG_PPCNT, 0, 0);
305 }
306 }
307
308 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
309 {
310 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
311 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
312 int err;
313
314 if (!priv->q_counter)
315 return;
316
317 err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
318 if (err)
319 return;
320
321 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
322 }
323
324 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
325 {
326 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
327 struct mlx5_core_dev *mdev = priv->mdev;
328 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
329 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
330 void *out;
331
332 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
333 return;
334
335 out = pcie_stats->pcie_perf_counters;
336 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
337 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
338 }
339
340 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
341 {
342 if (full) {
343 mlx5e_update_pcie_counters(priv);
344 mlx5e_ipsec_update_stats(priv);
345 }
346 mlx5e_update_pport_counters(priv, full);
347 mlx5e_update_vport_counters(priv);
348 mlx5e_update_q_counter(priv);
349 mlx5e_update_sw_counters(priv);
350 }
351
352 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
353 {
354 mlx5e_update_stats(priv, false);
355 }
356
357 void mlx5e_update_stats_work(struct work_struct *work)
358 {
359 struct delayed_work *dwork = to_delayed_work(work);
360 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
361 update_stats_work);
362 mutex_lock(&priv->state_lock);
363 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
364 priv->profile->update_stats(priv);
365 queue_delayed_work(priv->wq, dwork,
366 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
367 }
368 mutex_unlock(&priv->state_lock);
369 }
370
371 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
372 enum mlx5_dev_event event, unsigned long param)
373 {
374 struct mlx5e_priv *priv = vpriv;
375
376 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
377 return;
378
379 switch (event) {
380 case MLX5_DEV_EVENT_PORT_UP:
381 case MLX5_DEV_EVENT_PORT_DOWN:
382 queue_work(priv->wq, &priv->update_carrier_work);
383 break;
384 default:
385 break;
386 }
387 }
388
389 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
390 {
391 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
392 }
393
394 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
395 {
396 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
397 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
398 }
399
400 static inline int mlx5e_get_wqe_mtt_sz(void)
401 {
402 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
403 * To avoid copying garbage after the mtt array, we allocate
404 * a little more.
405 */
406 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
407 MLX5_UMR_MTT_ALIGNMENT);
408 }
409
410 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
411 struct mlx5e_icosq *sq,
412 struct mlx5e_umr_wqe *wqe,
413 u16 ix)
414 {
415 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
416 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
417 struct mlx5_wqe_data_seg *dseg = &wqe->data;
418 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
419 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
420 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
421
422 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
423 ds_cnt);
424 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
425 cseg->imm = rq->mkey_be;
426
427 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
428 ucseg->xlt_octowords =
429 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
430 ucseg->bsf_octowords =
431 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
432 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
433
434 dseg->lkey = sq->mkey_be;
435 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
436 }
437
438 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
439 struct mlx5e_channel *c)
440 {
441 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
442 int mtt_sz = mlx5e_get_wqe_mtt_sz();
443 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
444 int i;
445
446 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
447 GFP_KERNEL, cpu_to_node(c->cpu));
448 if (!rq->mpwqe.info)
449 goto err_out;
450
451 /* We allocate more than mtt_sz as we will align the pointer */
452 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
453 cpu_to_node(c->cpu));
454 if (unlikely(!rq->mpwqe.mtt_no_align))
455 goto err_free_wqe_info;
456
457 for (i = 0; i < wq_sz; i++) {
458 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
459
460 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
461 MLX5_UMR_ALIGN);
462 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
463 PCI_DMA_TODEVICE);
464 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
465 goto err_unmap_mtts;
466
467 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
468 }
469
470 return 0;
471
472 err_unmap_mtts:
473 while (--i >= 0) {
474 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
475
476 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
477 PCI_DMA_TODEVICE);
478 }
479 kfree(rq->mpwqe.mtt_no_align);
480 err_free_wqe_info:
481 kfree(rq->mpwqe.info);
482
483 err_out:
484 return -ENOMEM;
485 }
486
487 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
488 {
489 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
490 int mtt_sz = mlx5e_get_wqe_mtt_sz();
491 int i;
492
493 for (i = 0; i < wq_sz; i++) {
494 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
495
496 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
497 PCI_DMA_TODEVICE);
498 }
499 kfree(rq->mpwqe.mtt_no_align);
500 kfree(rq->mpwqe.info);
501 }
502
503 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
504 u64 npages, u8 page_shift,
505 struct mlx5_core_mkey *umr_mkey)
506 {
507 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
508 void *mkc;
509 u32 *in;
510 int err;
511
512 if (!MLX5E_VALID_NUM_MTTS(npages))
513 return -EINVAL;
514
515 in = kvzalloc(inlen, GFP_KERNEL);
516 if (!in)
517 return -ENOMEM;
518
519 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
520
521 MLX5_SET(mkc, mkc, free, 1);
522 MLX5_SET(mkc, mkc, umr_en, 1);
523 MLX5_SET(mkc, mkc, lw, 1);
524 MLX5_SET(mkc, mkc, lr, 1);
525 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
526
527 MLX5_SET(mkc, mkc, qpn, 0xffffff);
528 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
529 MLX5_SET64(mkc, mkc, len, npages << page_shift);
530 MLX5_SET(mkc, mkc, translations_octword_size,
531 MLX5_MTT_OCTW(npages));
532 MLX5_SET(mkc, mkc, log_page_size, page_shift);
533
534 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
535
536 kvfree(in);
537 return err;
538 }
539
540 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
541 {
542 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
543
544 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
545 }
546
547 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
548 struct mlx5e_params *params,
549 struct mlx5e_rq_param *rqp,
550 struct mlx5e_rq *rq)
551 {
552 struct mlx5_core_dev *mdev = c->mdev;
553 void *rqc = rqp->rqc;
554 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
555 u32 byte_count;
556 int npages;
557 int wq_sz;
558 int err;
559 int i;
560
561 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
562
563 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
564 &rq->wq_ctrl);
565 if (err)
566 return err;
567
568 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
569
570 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
571
572 rq->wq_type = params->rq_wq_type;
573 rq->pdev = c->pdev;
574 rq->netdev = c->netdev;
575 rq->tstamp = c->tstamp;
576 rq->clock = &mdev->clock;
577 rq->channel = c;
578 rq->ix = c->ix;
579 rq->mdev = mdev;
580
581 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
582 if (IS_ERR(rq->xdp_prog)) {
583 err = PTR_ERR(rq->xdp_prog);
584 rq->xdp_prog = NULL;
585 goto err_rq_wq_destroy;
586 }
587
588 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
589 rq->buff.headroom = params->rq_headroom;
590
591 switch (rq->wq_type) {
592 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
593
594 rq->post_wqes = mlx5e_post_rx_mpwqes;
595 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
596
597 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
598 #ifdef CONFIG_MLX5_EN_IPSEC
599 if (MLX5_IPSEC_DEV(mdev)) {
600 err = -EINVAL;
601 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
602 goto err_rq_wq_destroy;
603 }
604 #endif
605 if (!rq->handle_rx_cqe) {
606 err = -EINVAL;
607 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
608 goto err_rq_wq_destroy;
609 }
610
611 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
612 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
613
614 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
615
616 err = mlx5e_create_rq_umr_mkey(mdev, rq);
617 if (err)
618 goto err_rq_wq_destroy;
619 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
620
621 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
622 if (err)
623 goto err_destroy_umr_mkey;
624 break;
625 default: /* MLX5_WQ_TYPE_LINKED_LIST */
626 rq->wqe.frag_info =
627 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
628 GFP_KERNEL, cpu_to_node(c->cpu));
629 if (!rq->wqe.frag_info) {
630 err = -ENOMEM;
631 goto err_rq_wq_destroy;
632 }
633 rq->post_wqes = mlx5e_post_rx_wqes;
634 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
635
636 #ifdef CONFIG_MLX5_EN_IPSEC
637 if (c->priv->ipsec)
638 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
639 else
640 #endif
641 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
642 if (!rq->handle_rx_cqe) {
643 kfree(rq->wqe.frag_info);
644 err = -EINVAL;
645 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
646 goto err_rq_wq_destroy;
647 }
648
649 byte_count = params->lro_en ?
650 params->lro_wqe_sz :
651 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
652 #ifdef CONFIG_MLX5_EN_IPSEC
653 if (MLX5_IPSEC_DEV(mdev))
654 byte_count += MLX5E_METADATA_ETHER_LEN;
655 #endif
656 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
657
658 /* calc the required page order */
659 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
660 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
661 rq->buff.page_order = order_base_2(npages);
662
663 byte_count |= MLX5_HW_START_PADDING;
664 rq->mkey_be = c->mkey_be;
665 }
666
667 for (i = 0; i < wq_sz; i++) {
668 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
669
670 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
671 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
672
673 wqe->data.addr = cpu_to_be64(dma_offset);
674 }
675
676 wqe->data.byte_count = cpu_to_be32(byte_count);
677 wqe->data.lkey = rq->mkey_be;
678 }
679
680 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
681 rq->am.mode = params->rx_cq_moderation.cq_period_mode;
682 rq->page_cache.head = 0;
683 rq->page_cache.tail = 0;
684
685 return 0;
686
687 err_destroy_umr_mkey:
688 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
689
690 err_rq_wq_destroy:
691 if (rq->xdp_prog)
692 bpf_prog_put(rq->xdp_prog);
693 mlx5_wq_destroy(&rq->wq_ctrl);
694
695 return err;
696 }
697
698 static void mlx5e_free_rq(struct mlx5e_rq *rq)
699 {
700 int i;
701
702 if (rq->xdp_prog)
703 bpf_prog_put(rq->xdp_prog);
704
705 switch (rq->wq_type) {
706 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
707 mlx5e_rq_free_mpwqe_info(rq);
708 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
709 break;
710 default: /* MLX5_WQ_TYPE_LINKED_LIST */
711 kfree(rq->wqe.frag_info);
712 }
713
714 for (i = rq->page_cache.head; i != rq->page_cache.tail;
715 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
716 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
717
718 mlx5e_page_release(rq, dma_info, false);
719 }
720 mlx5_wq_destroy(&rq->wq_ctrl);
721 }
722
723 static int mlx5e_create_rq(struct mlx5e_rq *rq,
724 struct mlx5e_rq_param *param)
725 {
726 struct mlx5_core_dev *mdev = rq->mdev;
727
728 void *in;
729 void *rqc;
730 void *wq;
731 int inlen;
732 int err;
733
734 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
735 sizeof(u64) * rq->wq_ctrl.buf.npages;
736 in = kvzalloc(inlen, GFP_KERNEL);
737 if (!in)
738 return -ENOMEM;
739
740 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
741 wq = MLX5_ADDR_OF(rqc, rqc, wq);
742
743 memcpy(rqc, param->rqc, sizeof(param->rqc));
744
745 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
746 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
747 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
748 MLX5_ADAPTER_PAGE_SHIFT);
749 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
750
751 mlx5_fill_page_array(&rq->wq_ctrl.buf,
752 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
753
754 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
755
756 kvfree(in);
757
758 return err;
759 }
760
761 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
762 int next_state)
763 {
764 struct mlx5e_channel *c = rq->channel;
765 struct mlx5_core_dev *mdev = c->mdev;
766
767 void *in;
768 void *rqc;
769 int inlen;
770 int err;
771
772 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
773 in = kvzalloc(inlen, GFP_KERNEL);
774 if (!in)
775 return -ENOMEM;
776
777 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
778
779 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
780 MLX5_SET(rqc, rqc, state, next_state);
781
782 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
783
784 kvfree(in);
785
786 return err;
787 }
788
789 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
790 {
791 struct mlx5e_channel *c = rq->channel;
792 struct mlx5e_priv *priv = c->priv;
793 struct mlx5_core_dev *mdev = priv->mdev;
794
795 void *in;
796 void *rqc;
797 int inlen;
798 int err;
799
800 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
801 in = kvzalloc(inlen, GFP_KERNEL);
802 if (!in)
803 return -ENOMEM;
804
805 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
806
807 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
808 MLX5_SET64(modify_rq_in, in, modify_bitmask,
809 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
810 MLX5_SET(rqc, rqc, scatter_fcs, enable);
811 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
812
813 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
814
815 kvfree(in);
816
817 return err;
818 }
819
820 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
821 {
822 struct mlx5e_channel *c = rq->channel;
823 struct mlx5_core_dev *mdev = c->mdev;
824 void *in;
825 void *rqc;
826 int inlen;
827 int err;
828
829 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
830 in = kvzalloc(inlen, GFP_KERNEL);
831 if (!in)
832 return -ENOMEM;
833
834 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
835
836 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
837 MLX5_SET64(modify_rq_in, in, modify_bitmask,
838 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
839 MLX5_SET(rqc, rqc, vsd, vsd);
840 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
841
842 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
843
844 kvfree(in);
845
846 return err;
847 }
848
849 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
850 {
851 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
852 }
853
854 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
855 {
856 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
857 struct mlx5e_channel *c = rq->channel;
858
859 struct mlx5_wq_ll *wq = &rq->wq;
860 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
861
862 while (time_before(jiffies, exp_time)) {
863 if (wq->cur_sz >= min_wqes)
864 return 0;
865
866 msleep(20);
867 }
868
869 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
870 rq->rqn, wq->cur_sz, min_wqes);
871 return -ETIMEDOUT;
872 }
873
874 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
875 {
876 struct mlx5_wq_ll *wq = &rq->wq;
877 struct mlx5e_rx_wqe *wqe;
878 __be16 wqe_ix_be;
879 u16 wqe_ix;
880
881 /* UMR WQE (if in progress) is always at wq->head */
882 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
883 rq->mpwqe.umr_in_progress)
884 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
885
886 while (!mlx5_wq_ll_is_empty(wq)) {
887 wqe_ix_be = *wq->tail_next;
888 wqe_ix = be16_to_cpu(wqe_ix_be);
889 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
890 rq->dealloc_wqe(rq, wqe_ix);
891 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
892 &wqe->next.next_wqe_index);
893 }
894
895 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
896 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
897 * but yet to be re-posted.
898 */
899 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
900
901 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
902 rq->dealloc_wqe(rq, wqe_ix);
903 }
904 }
905
906 static int mlx5e_open_rq(struct mlx5e_channel *c,
907 struct mlx5e_params *params,
908 struct mlx5e_rq_param *param,
909 struct mlx5e_rq *rq)
910 {
911 int err;
912
913 err = mlx5e_alloc_rq(c, params, param, rq);
914 if (err)
915 return err;
916
917 err = mlx5e_create_rq(rq, param);
918 if (err)
919 goto err_free_rq;
920
921 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
922 if (err)
923 goto err_destroy_rq;
924
925 if (params->rx_am_enabled)
926 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
927
928 /* We disable csum_complete when XDP is enabled since
929 * XDP programs might manipulate packets which will render
930 * skb->checksum incorrect.
931 */
932 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
933 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
934
935 return 0;
936
937 err_destroy_rq:
938 mlx5e_destroy_rq(rq);
939 err_free_rq:
940 mlx5e_free_rq(rq);
941
942 return err;
943 }
944
945 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
946 {
947 struct mlx5e_icosq *sq = &rq->channel->icosq;
948 u16 pi = sq->pc & sq->wq.sz_m1;
949 struct mlx5e_tx_wqe *nopwqe;
950
951 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
952 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
953 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
954 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
955 }
956
957 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
958 {
959 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
960 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
961 }
962
963 static void mlx5e_close_rq(struct mlx5e_rq *rq)
964 {
965 cancel_work_sync(&rq->am.work);
966 mlx5e_destroy_rq(rq);
967 mlx5e_free_rx_descs(rq);
968 mlx5e_free_rq(rq);
969 }
970
971 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
972 {
973 kfree(sq->db.di);
974 }
975
976 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
977 {
978 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
979
980 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
981 GFP_KERNEL, numa);
982 if (!sq->db.di) {
983 mlx5e_free_xdpsq_db(sq);
984 return -ENOMEM;
985 }
986
987 return 0;
988 }
989
990 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
991 struct mlx5e_params *params,
992 struct mlx5e_sq_param *param,
993 struct mlx5e_xdpsq *sq)
994 {
995 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
996 struct mlx5_core_dev *mdev = c->mdev;
997 int err;
998
999 sq->pdev = c->pdev;
1000 sq->mkey_be = c->mkey_be;
1001 sq->channel = c;
1002 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1003 sq->min_inline_mode = params->tx_min_inline_mode;
1004
1005 param->wq.db_numa_node = cpu_to_node(c->cpu);
1006 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1007 if (err)
1008 return err;
1009 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1010
1011 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1012 if (err)
1013 goto err_sq_wq_destroy;
1014
1015 return 0;
1016
1017 err_sq_wq_destroy:
1018 mlx5_wq_destroy(&sq->wq_ctrl);
1019
1020 return err;
1021 }
1022
1023 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1024 {
1025 mlx5e_free_xdpsq_db(sq);
1026 mlx5_wq_destroy(&sq->wq_ctrl);
1027 }
1028
1029 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1030 {
1031 kfree(sq->db.ico_wqe);
1032 }
1033
1034 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1035 {
1036 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1037
1038 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1039 GFP_KERNEL, numa);
1040 if (!sq->db.ico_wqe)
1041 return -ENOMEM;
1042
1043 return 0;
1044 }
1045
1046 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1047 struct mlx5e_sq_param *param,
1048 struct mlx5e_icosq *sq)
1049 {
1050 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1051 struct mlx5_core_dev *mdev = c->mdev;
1052 int err;
1053
1054 sq->mkey_be = c->mkey_be;
1055 sq->channel = c;
1056 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1057
1058 param->wq.db_numa_node = cpu_to_node(c->cpu);
1059 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1060 if (err)
1061 return err;
1062 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1063
1064 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1065 if (err)
1066 goto err_sq_wq_destroy;
1067
1068 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
1069
1070 return 0;
1071
1072 err_sq_wq_destroy:
1073 mlx5_wq_destroy(&sq->wq_ctrl);
1074
1075 return err;
1076 }
1077
1078 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1079 {
1080 mlx5e_free_icosq_db(sq);
1081 mlx5_wq_destroy(&sq->wq_ctrl);
1082 }
1083
1084 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1085 {
1086 kfree(sq->db.wqe_info);
1087 kfree(sq->db.dma_fifo);
1088 }
1089
1090 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1091 {
1092 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1093 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1094
1095 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1096 GFP_KERNEL, numa);
1097 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1098 GFP_KERNEL, numa);
1099 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1100 mlx5e_free_txqsq_db(sq);
1101 return -ENOMEM;
1102 }
1103
1104 sq->dma_fifo_mask = df_sz - 1;
1105
1106 return 0;
1107 }
1108
1109 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1110 int txq_ix,
1111 struct mlx5e_params *params,
1112 struct mlx5e_sq_param *param,
1113 struct mlx5e_txqsq *sq)
1114 {
1115 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1116 struct mlx5_core_dev *mdev = c->mdev;
1117 int err;
1118
1119 sq->pdev = c->pdev;
1120 sq->tstamp = c->tstamp;
1121 sq->clock = &mdev->clock;
1122 sq->mkey_be = c->mkey_be;
1123 sq->channel = c;
1124 sq->txq_ix = txq_ix;
1125 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1126 sq->max_inline = params->tx_max_inline;
1127 sq->min_inline_mode = params->tx_min_inline_mode;
1128 if (MLX5_IPSEC_DEV(c->priv->mdev))
1129 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1130
1131 param->wq.db_numa_node = cpu_to_node(c->cpu);
1132 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1133 if (err)
1134 return err;
1135 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1136
1137 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1138 if (err)
1139 goto err_sq_wq_destroy;
1140
1141 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1142
1143 return 0;
1144
1145 err_sq_wq_destroy:
1146 mlx5_wq_destroy(&sq->wq_ctrl);
1147
1148 return err;
1149 }
1150
1151 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1152 {
1153 mlx5e_free_txqsq_db(sq);
1154 mlx5_wq_destroy(&sq->wq_ctrl);
1155 }
1156
1157 struct mlx5e_create_sq_param {
1158 struct mlx5_wq_ctrl *wq_ctrl;
1159 u32 cqn;
1160 u32 tisn;
1161 u8 tis_lst_sz;
1162 u8 min_inline_mode;
1163 };
1164
1165 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1166 struct mlx5e_sq_param *param,
1167 struct mlx5e_create_sq_param *csp,
1168 u32 *sqn)
1169 {
1170 void *in;
1171 void *sqc;
1172 void *wq;
1173 int inlen;
1174 int err;
1175
1176 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1177 sizeof(u64) * csp->wq_ctrl->buf.npages;
1178 in = kvzalloc(inlen, GFP_KERNEL);
1179 if (!in)
1180 return -ENOMEM;
1181
1182 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1183 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1184
1185 memcpy(sqc, param->sqc, sizeof(param->sqc));
1186 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1187 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1188 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1189
1190 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1191 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1192
1193 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1194
1195 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1196 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1197 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1198 MLX5_ADAPTER_PAGE_SHIFT);
1199 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1200
1201 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1202
1203 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1204
1205 kvfree(in);
1206
1207 return err;
1208 }
1209
1210 struct mlx5e_modify_sq_param {
1211 int curr_state;
1212 int next_state;
1213 bool rl_update;
1214 int rl_index;
1215 };
1216
1217 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1218 struct mlx5e_modify_sq_param *p)
1219 {
1220 void *in;
1221 void *sqc;
1222 int inlen;
1223 int err;
1224
1225 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1226 in = kvzalloc(inlen, GFP_KERNEL);
1227 if (!in)
1228 return -ENOMEM;
1229
1230 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1231
1232 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1233 MLX5_SET(sqc, sqc, state, p->next_state);
1234 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1235 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1236 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1237 }
1238
1239 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1240
1241 kvfree(in);
1242
1243 return err;
1244 }
1245
1246 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1247 {
1248 mlx5_core_destroy_sq(mdev, sqn);
1249 }
1250
1251 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1252 struct mlx5e_sq_param *param,
1253 struct mlx5e_create_sq_param *csp,
1254 u32 *sqn)
1255 {
1256 struct mlx5e_modify_sq_param msp = {0};
1257 int err;
1258
1259 err = mlx5e_create_sq(mdev, param, csp, sqn);
1260 if (err)
1261 return err;
1262
1263 msp.curr_state = MLX5_SQC_STATE_RST;
1264 msp.next_state = MLX5_SQC_STATE_RDY;
1265 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1266 if (err)
1267 mlx5e_destroy_sq(mdev, *sqn);
1268
1269 return err;
1270 }
1271
1272 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1273 struct mlx5e_txqsq *sq, u32 rate);
1274
1275 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1276 u32 tisn,
1277 int txq_ix,
1278 struct mlx5e_params *params,
1279 struct mlx5e_sq_param *param,
1280 struct mlx5e_txqsq *sq)
1281 {
1282 struct mlx5e_create_sq_param csp = {};
1283 u32 tx_rate;
1284 int err;
1285
1286 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1287 if (err)
1288 return err;
1289
1290 csp.tisn = tisn;
1291 csp.tis_lst_sz = 1;
1292 csp.cqn = sq->cq.mcq.cqn;
1293 csp.wq_ctrl = &sq->wq_ctrl;
1294 csp.min_inline_mode = sq->min_inline_mode;
1295 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1296 if (err)
1297 goto err_free_txqsq;
1298
1299 tx_rate = c->priv->tx_rates[sq->txq_ix];
1300 if (tx_rate)
1301 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1302
1303 return 0;
1304
1305 err_free_txqsq:
1306 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1307 mlx5e_free_txqsq(sq);
1308
1309 return err;
1310 }
1311
1312 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1313 {
1314 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1315 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1316 netdev_tx_reset_queue(sq->txq);
1317 netif_tx_start_queue(sq->txq);
1318 }
1319
1320 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1321 {
1322 __netif_tx_lock_bh(txq);
1323 netif_tx_stop_queue(txq);
1324 __netif_tx_unlock_bh(txq);
1325 }
1326
1327 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1328 {
1329 struct mlx5e_channel *c = sq->channel;
1330
1331 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1332 /* prevent netif_tx_wake_queue */
1333 napi_synchronize(&c->napi);
1334
1335 netif_tx_disable_queue(sq->txq);
1336
1337 /* last doorbell out, godspeed .. */
1338 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1339 struct mlx5e_tx_wqe *nop;
1340
1341 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1342 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1343 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1344 }
1345 }
1346
1347 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1348 {
1349 struct mlx5e_channel *c = sq->channel;
1350 struct mlx5_core_dev *mdev = c->mdev;
1351
1352 mlx5e_destroy_sq(mdev, sq->sqn);
1353 if (sq->rate_limit)
1354 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1355 mlx5e_free_txqsq_descs(sq);
1356 mlx5e_free_txqsq(sq);
1357 }
1358
1359 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1360 struct mlx5e_params *params,
1361 struct mlx5e_sq_param *param,
1362 struct mlx5e_icosq *sq)
1363 {
1364 struct mlx5e_create_sq_param csp = {};
1365 int err;
1366
1367 err = mlx5e_alloc_icosq(c, param, sq);
1368 if (err)
1369 return err;
1370
1371 csp.cqn = sq->cq.mcq.cqn;
1372 csp.wq_ctrl = &sq->wq_ctrl;
1373 csp.min_inline_mode = params->tx_min_inline_mode;
1374 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1375 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1376 if (err)
1377 goto err_free_icosq;
1378
1379 return 0;
1380
1381 err_free_icosq:
1382 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1383 mlx5e_free_icosq(sq);
1384
1385 return err;
1386 }
1387
1388 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1389 {
1390 struct mlx5e_channel *c = sq->channel;
1391
1392 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1393 napi_synchronize(&c->napi);
1394
1395 mlx5e_destroy_sq(c->mdev, sq->sqn);
1396 mlx5e_free_icosq(sq);
1397 }
1398
1399 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1400 struct mlx5e_params *params,
1401 struct mlx5e_sq_param *param,
1402 struct mlx5e_xdpsq *sq)
1403 {
1404 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1405 struct mlx5e_create_sq_param csp = {};
1406 unsigned int inline_hdr_sz = 0;
1407 int err;
1408 int i;
1409
1410 err = mlx5e_alloc_xdpsq(c, params, param, sq);
1411 if (err)
1412 return err;
1413
1414 csp.tis_lst_sz = 1;
1415 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1416 csp.cqn = sq->cq.mcq.cqn;
1417 csp.wq_ctrl = &sq->wq_ctrl;
1418 csp.min_inline_mode = sq->min_inline_mode;
1419 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1420 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1421 if (err)
1422 goto err_free_xdpsq;
1423
1424 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1425 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1426 ds_cnt++;
1427 }
1428
1429 /* Pre initialize fixed WQE fields */
1430 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1431 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1432 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1433 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1434 struct mlx5_wqe_data_seg *dseg;
1435
1436 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1437 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1438
1439 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1440 dseg->lkey = sq->mkey_be;
1441 }
1442
1443 return 0;
1444
1445 err_free_xdpsq:
1446 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1447 mlx5e_free_xdpsq(sq);
1448
1449 return err;
1450 }
1451
1452 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1453 {
1454 struct mlx5e_channel *c = sq->channel;
1455
1456 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1457 napi_synchronize(&c->napi);
1458
1459 mlx5e_destroy_sq(c->mdev, sq->sqn);
1460 mlx5e_free_xdpsq_descs(sq);
1461 mlx5e_free_xdpsq(sq);
1462 }
1463
1464 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1465 struct mlx5e_cq_param *param,
1466 struct mlx5e_cq *cq)
1467 {
1468 struct mlx5_core_cq *mcq = &cq->mcq;
1469 int eqn_not_used;
1470 unsigned int irqn;
1471 int err;
1472 u32 i;
1473
1474 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1475 if (err)
1476 return err;
1477
1478 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1479 &cq->wq_ctrl);
1480 if (err)
1481 return err;
1482
1483 mcq->cqe_sz = 64;
1484 mcq->set_ci_db = cq->wq_ctrl.db.db;
1485 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1486 *mcq->set_ci_db = 0;
1487 *mcq->arm_db = 0;
1488 mcq->vector = param->eq_ix;
1489 mcq->comp = mlx5e_completion_event;
1490 mcq->event = mlx5e_cq_error_event;
1491 mcq->irqn = irqn;
1492
1493 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1494 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1495
1496 cqe->op_own = 0xf1;
1497 }
1498
1499 cq->mdev = mdev;
1500
1501 return 0;
1502 }
1503
1504 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1505 struct mlx5e_cq_param *param,
1506 struct mlx5e_cq *cq)
1507 {
1508 struct mlx5_core_dev *mdev = c->priv->mdev;
1509 int err;
1510
1511 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1512 param->wq.db_numa_node = cpu_to_node(c->cpu);
1513 param->eq_ix = c->ix;
1514
1515 err = mlx5e_alloc_cq_common(mdev, param, cq);
1516
1517 cq->napi = &c->napi;
1518 cq->channel = c;
1519
1520 return err;
1521 }
1522
1523 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1524 {
1525 mlx5_cqwq_destroy(&cq->wq_ctrl);
1526 }
1527
1528 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1529 {
1530 struct mlx5_core_dev *mdev = cq->mdev;
1531 struct mlx5_core_cq *mcq = &cq->mcq;
1532
1533 void *in;
1534 void *cqc;
1535 int inlen;
1536 unsigned int irqn_not_used;
1537 int eqn;
1538 int err;
1539
1540 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1541 if (err)
1542 return err;
1543
1544 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1545 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1546 in = kvzalloc(inlen, GFP_KERNEL);
1547 if (!in)
1548 return -ENOMEM;
1549
1550 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1551
1552 memcpy(cqc, param->cqc, sizeof(param->cqc));
1553
1554 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1555 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1556
1557 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1558 MLX5_SET(cqc, cqc, c_eqn, eqn);
1559 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1560 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1561 MLX5_ADAPTER_PAGE_SHIFT);
1562 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1563
1564 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1565
1566 kvfree(in);
1567
1568 if (err)
1569 return err;
1570
1571 mlx5e_cq_arm(cq);
1572
1573 return 0;
1574 }
1575
1576 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1577 {
1578 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1579 }
1580
1581 static int mlx5e_open_cq(struct mlx5e_channel *c,
1582 struct mlx5e_cq_moder moder,
1583 struct mlx5e_cq_param *param,
1584 struct mlx5e_cq *cq)
1585 {
1586 struct mlx5_core_dev *mdev = c->mdev;
1587 int err;
1588
1589 err = mlx5e_alloc_cq(c, param, cq);
1590 if (err)
1591 return err;
1592
1593 err = mlx5e_create_cq(cq, param);
1594 if (err)
1595 goto err_free_cq;
1596
1597 if (MLX5_CAP_GEN(mdev, cq_moderation))
1598 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1599 return 0;
1600
1601 err_free_cq:
1602 mlx5e_free_cq(cq);
1603
1604 return err;
1605 }
1606
1607 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1608 {
1609 mlx5e_destroy_cq(cq);
1610 mlx5e_free_cq(cq);
1611 }
1612
1613 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1614 {
1615 return cpumask_first(priv->mdev->priv.irq_info[ix + MLX5_EQ_VEC_COMP_BASE].mask);
1616 }
1617
1618 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1619 struct mlx5e_params *params,
1620 struct mlx5e_channel_param *cparam)
1621 {
1622 int err;
1623 int tc;
1624
1625 for (tc = 0; tc < c->num_tc; tc++) {
1626 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1627 &cparam->tx_cq, &c->sq[tc].cq);
1628 if (err)
1629 goto err_close_tx_cqs;
1630 }
1631
1632 return 0;
1633
1634 err_close_tx_cqs:
1635 for (tc--; tc >= 0; tc--)
1636 mlx5e_close_cq(&c->sq[tc].cq);
1637
1638 return err;
1639 }
1640
1641 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1642 {
1643 int tc;
1644
1645 for (tc = 0; tc < c->num_tc; tc++)
1646 mlx5e_close_cq(&c->sq[tc].cq);
1647 }
1648
1649 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1650 struct mlx5e_params *params,
1651 struct mlx5e_channel_param *cparam)
1652 {
1653 int err;
1654 int tc;
1655
1656 for (tc = 0; tc < params->num_tc; tc++) {
1657 int txq_ix = c->ix + tc * params->num_channels;
1658
1659 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1660 params, &cparam->sq, &c->sq[tc]);
1661 if (err)
1662 goto err_close_sqs;
1663 }
1664
1665 return 0;
1666
1667 err_close_sqs:
1668 for (tc--; tc >= 0; tc--)
1669 mlx5e_close_txqsq(&c->sq[tc]);
1670
1671 return err;
1672 }
1673
1674 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1675 {
1676 int tc;
1677
1678 for (tc = 0; tc < c->num_tc; tc++)
1679 mlx5e_close_txqsq(&c->sq[tc]);
1680 }
1681
1682 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1683 struct mlx5e_txqsq *sq, u32 rate)
1684 {
1685 struct mlx5e_priv *priv = netdev_priv(dev);
1686 struct mlx5_core_dev *mdev = priv->mdev;
1687 struct mlx5e_modify_sq_param msp = {0};
1688 u16 rl_index = 0;
1689 int err;
1690
1691 if (rate == sq->rate_limit)
1692 /* nothing to do */
1693 return 0;
1694
1695 if (sq->rate_limit)
1696 /* remove current rl index to free space to next ones */
1697 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1698
1699 sq->rate_limit = 0;
1700
1701 if (rate) {
1702 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1703 if (err) {
1704 netdev_err(dev, "Failed configuring rate %u: %d\n",
1705 rate, err);
1706 return err;
1707 }
1708 }
1709
1710 msp.curr_state = MLX5_SQC_STATE_RDY;
1711 msp.next_state = MLX5_SQC_STATE_RDY;
1712 msp.rl_index = rl_index;
1713 msp.rl_update = true;
1714 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1715 if (err) {
1716 netdev_err(dev, "Failed configuring rate %u: %d\n",
1717 rate, err);
1718 /* remove the rate from the table */
1719 if (rate)
1720 mlx5_rl_remove_rate(mdev, rate);
1721 return err;
1722 }
1723
1724 sq->rate_limit = rate;
1725 return 0;
1726 }
1727
1728 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1729 {
1730 struct mlx5e_priv *priv = netdev_priv(dev);
1731 struct mlx5_core_dev *mdev = priv->mdev;
1732 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1733 int err = 0;
1734
1735 if (!mlx5_rl_is_supported(mdev)) {
1736 netdev_err(dev, "Rate limiting is not supported on this device\n");
1737 return -EINVAL;
1738 }
1739
1740 /* rate is given in Mb/sec, HW config is in Kb/sec */
1741 rate = rate << 10;
1742
1743 /* Check whether rate in valid range, 0 is always valid */
1744 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1745 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1746 return -ERANGE;
1747 }
1748
1749 mutex_lock(&priv->state_lock);
1750 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1751 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1752 if (!err)
1753 priv->tx_rates[index] = rate;
1754 mutex_unlock(&priv->state_lock);
1755
1756 return err;
1757 }
1758
1759 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1760 struct mlx5e_params *params,
1761 struct mlx5e_channel_param *cparam,
1762 struct mlx5e_channel **cp)
1763 {
1764 struct mlx5e_cq_moder icocq_moder = {0, 0};
1765 struct net_device *netdev = priv->netdev;
1766 int cpu = mlx5e_get_cpu(priv, ix);
1767 struct mlx5e_channel *c;
1768 unsigned int irq;
1769 int err;
1770 int eqn;
1771
1772 err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1773 if (err)
1774 return err;
1775
1776 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1777 if (!c)
1778 return -ENOMEM;
1779
1780 c->priv = priv;
1781 c->mdev = priv->mdev;
1782 c->tstamp = &priv->tstamp;
1783 c->ix = ix;
1784 c->cpu = cpu;
1785 c->pdev = &priv->mdev->pdev->dev;
1786 c->netdev = priv->netdev;
1787 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1788 c->num_tc = params->num_tc;
1789 c->xdp = !!params->xdp_prog;
1790
1791 c->irq_desc = irq_to_desc(irq);
1792
1793 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1794
1795 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1796 if (err)
1797 goto err_napi_del;
1798
1799 err = mlx5e_open_tx_cqs(c, params, cparam);
1800 if (err)
1801 goto err_close_icosq_cq;
1802
1803 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1804 if (err)
1805 goto err_close_tx_cqs;
1806
1807 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1808 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1809 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1810 if (err)
1811 goto err_close_rx_cq;
1812
1813 napi_enable(&c->napi);
1814
1815 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1816 if (err)
1817 goto err_disable_napi;
1818
1819 err = mlx5e_open_sqs(c, params, cparam);
1820 if (err)
1821 goto err_close_icosq;
1822
1823 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1824 if (err)
1825 goto err_close_sqs;
1826
1827 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1828 if (err)
1829 goto err_close_xdp_sq;
1830
1831 *cp = c;
1832
1833 return 0;
1834 err_close_xdp_sq:
1835 if (c->xdp)
1836 mlx5e_close_xdpsq(&c->rq.xdpsq);
1837
1838 err_close_sqs:
1839 mlx5e_close_sqs(c);
1840
1841 err_close_icosq:
1842 mlx5e_close_icosq(&c->icosq);
1843
1844 err_disable_napi:
1845 napi_disable(&c->napi);
1846 if (c->xdp)
1847 mlx5e_close_cq(&c->rq.xdpsq.cq);
1848
1849 err_close_rx_cq:
1850 mlx5e_close_cq(&c->rq.cq);
1851
1852 err_close_tx_cqs:
1853 mlx5e_close_tx_cqs(c);
1854
1855 err_close_icosq_cq:
1856 mlx5e_close_cq(&c->icosq.cq);
1857
1858 err_napi_del:
1859 netif_napi_del(&c->napi);
1860 kfree(c);
1861
1862 return err;
1863 }
1864
1865 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1866 {
1867 int tc;
1868
1869 for (tc = 0; tc < c->num_tc; tc++)
1870 mlx5e_activate_txqsq(&c->sq[tc]);
1871 mlx5e_activate_rq(&c->rq);
1872 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1873 }
1874
1875 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1876 {
1877 int tc;
1878
1879 mlx5e_deactivate_rq(&c->rq);
1880 for (tc = 0; tc < c->num_tc; tc++)
1881 mlx5e_deactivate_txqsq(&c->sq[tc]);
1882 }
1883
1884 static void mlx5e_close_channel(struct mlx5e_channel *c)
1885 {
1886 mlx5e_close_rq(&c->rq);
1887 if (c->xdp)
1888 mlx5e_close_xdpsq(&c->rq.xdpsq);
1889 mlx5e_close_sqs(c);
1890 mlx5e_close_icosq(&c->icosq);
1891 napi_disable(&c->napi);
1892 if (c->xdp)
1893 mlx5e_close_cq(&c->rq.xdpsq.cq);
1894 mlx5e_close_cq(&c->rq.cq);
1895 mlx5e_close_tx_cqs(c);
1896 mlx5e_close_cq(&c->icosq.cq);
1897 netif_napi_del(&c->napi);
1898
1899 kfree(c);
1900 }
1901
1902 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1903 struct mlx5e_params *params,
1904 struct mlx5e_rq_param *param)
1905 {
1906 void *rqc = param->rqc;
1907 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1908
1909 switch (params->rq_wq_type) {
1910 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1911 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1912 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
1913 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1914 break;
1915 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1916 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1917 }
1918
1919 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1920 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1921 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
1922 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1923 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1924 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
1925 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
1926
1927 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1928 param->wq.linear = 1;
1929 }
1930
1931 static void mlx5e_build_drop_rq_param(struct mlx5_core_dev *mdev,
1932 struct mlx5e_rq_param *param)
1933 {
1934 void *rqc = param->rqc;
1935 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1936
1937 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1938 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1939
1940 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1941 }
1942
1943 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1944 struct mlx5e_sq_param *param)
1945 {
1946 void *sqc = param->sqc;
1947 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1948
1949 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1950 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1951
1952 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1953 }
1954
1955 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1956 struct mlx5e_params *params,
1957 struct mlx5e_sq_param *param)
1958 {
1959 void *sqc = param->sqc;
1960 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1961
1962 mlx5e_build_sq_param_common(priv, param);
1963 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1964 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1965 }
1966
1967 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1968 struct mlx5e_cq_param *param)
1969 {
1970 void *cqc = param->cqc;
1971
1972 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1973 }
1974
1975 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1976 struct mlx5e_params *params,
1977 struct mlx5e_cq_param *param)
1978 {
1979 void *cqc = param->cqc;
1980 u8 log_cq_size;
1981
1982 switch (params->rq_wq_type) {
1983 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1984 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
1985 break;
1986 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1987 log_cq_size = params->log_rq_size;
1988 }
1989
1990 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1991 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1992 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1993 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1994 }
1995
1996 mlx5e_build_common_cq_param(priv, param);
1997 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
1998 }
1999
2000 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2001 struct mlx5e_params *params,
2002 struct mlx5e_cq_param *param)
2003 {
2004 void *cqc = param->cqc;
2005
2006 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2007
2008 mlx5e_build_common_cq_param(priv, param);
2009 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2010 }
2011
2012 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2013 u8 log_wq_size,
2014 struct mlx5e_cq_param *param)
2015 {
2016 void *cqc = param->cqc;
2017
2018 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2019
2020 mlx5e_build_common_cq_param(priv, param);
2021
2022 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2023 }
2024
2025 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2026 u8 log_wq_size,
2027 struct mlx5e_sq_param *param)
2028 {
2029 void *sqc = param->sqc;
2030 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2031
2032 mlx5e_build_sq_param_common(priv, param);
2033
2034 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2035 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2036 }
2037
2038 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2039 struct mlx5e_params *params,
2040 struct mlx5e_sq_param *param)
2041 {
2042 void *sqc = param->sqc;
2043 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2044
2045 mlx5e_build_sq_param_common(priv, param);
2046 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2047 }
2048
2049 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2050 struct mlx5e_params *params,
2051 struct mlx5e_channel_param *cparam)
2052 {
2053 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2054
2055 mlx5e_build_rq_param(priv, params, &cparam->rq);
2056 mlx5e_build_sq_param(priv, params, &cparam->sq);
2057 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2058 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2059 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2060 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2061 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2062 }
2063
2064 int mlx5e_open_channels(struct mlx5e_priv *priv,
2065 struct mlx5e_channels *chs)
2066 {
2067 struct mlx5e_channel_param *cparam;
2068 int err = -ENOMEM;
2069 int i;
2070
2071 chs->num = chs->params.num_channels;
2072
2073 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2074 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2075 if (!chs->c || !cparam)
2076 goto err_free;
2077
2078 mlx5e_build_channel_param(priv, &chs->params, cparam);
2079 for (i = 0; i < chs->num; i++) {
2080 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2081 if (err)
2082 goto err_close_channels;
2083 }
2084
2085 kfree(cparam);
2086 return 0;
2087
2088 err_close_channels:
2089 for (i--; i >= 0; i--)
2090 mlx5e_close_channel(chs->c[i]);
2091
2092 err_free:
2093 kfree(chs->c);
2094 kfree(cparam);
2095 chs->num = 0;
2096 return err;
2097 }
2098
2099 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2100 {
2101 int i;
2102
2103 for (i = 0; i < chs->num; i++)
2104 mlx5e_activate_channel(chs->c[i]);
2105 }
2106
2107 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2108 {
2109 int err = 0;
2110 int i;
2111
2112 for (i = 0; i < chs->num; i++) {
2113 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2114 if (err)
2115 break;
2116 }
2117
2118 return err;
2119 }
2120
2121 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2122 {
2123 int i;
2124
2125 for (i = 0; i < chs->num; i++)
2126 mlx5e_deactivate_channel(chs->c[i]);
2127 }
2128
2129 void mlx5e_close_channels(struct mlx5e_channels *chs)
2130 {
2131 int i;
2132
2133 for (i = 0; i < chs->num; i++)
2134 mlx5e_close_channel(chs->c[i]);
2135
2136 kfree(chs->c);
2137 chs->num = 0;
2138 }
2139
2140 static int
2141 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2142 {
2143 struct mlx5_core_dev *mdev = priv->mdev;
2144 void *rqtc;
2145 int inlen;
2146 int err;
2147 u32 *in;
2148 int i;
2149
2150 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2151 in = kvzalloc(inlen, GFP_KERNEL);
2152 if (!in)
2153 return -ENOMEM;
2154
2155 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2156
2157 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2158 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2159
2160 for (i = 0; i < sz; i++)
2161 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2162
2163 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2164 if (!err)
2165 rqt->enabled = true;
2166
2167 kvfree(in);
2168 return err;
2169 }
2170
2171 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2172 {
2173 rqt->enabled = false;
2174 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2175 }
2176
2177 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2178 {
2179 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2180 int err;
2181
2182 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2183 if (err)
2184 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2185 return err;
2186 }
2187
2188 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2189 {
2190 struct mlx5e_rqt *rqt;
2191 int err;
2192 int ix;
2193
2194 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2195 rqt = &priv->direct_tir[ix].rqt;
2196 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2197 if (err)
2198 goto err_destroy_rqts;
2199 }
2200
2201 return 0;
2202
2203 err_destroy_rqts:
2204 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2205 for (ix--; ix >= 0; ix--)
2206 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2207
2208 return err;
2209 }
2210
2211 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2212 {
2213 int i;
2214
2215 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2216 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2217 }
2218
2219 static int mlx5e_rx_hash_fn(int hfunc)
2220 {
2221 return (hfunc == ETH_RSS_HASH_TOP) ?
2222 MLX5_RX_HASH_FN_TOEPLITZ :
2223 MLX5_RX_HASH_FN_INVERTED_XOR8;
2224 }
2225
2226 static int mlx5e_bits_invert(unsigned long a, int size)
2227 {
2228 int inv = 0;
2229 int i;
2230
2231 for (i = 0; i < size; i++)
2232 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2233
2234 return inv;
2235 }
2236
2237 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2238 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2239 {
2240 int i;
2241
2242 for (i = 0; i < sz; i++) {
2243 u32 rqn;
2244
2245 if (rrp.is_rss) {
2246 int ix = i;
2247
2248 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2249 ix = mlx5e_bits_invert(i, ilog2(sz));
2250
2251 ix = priv->channels.params.indirection_rqt[ix];
2252 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2253 } else {
2254 rqn = rrp.rqn;
2255 }
2256 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2257 }
2258 }
2259
2260 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2261 struct mlx5e_redirect_rqt_param rrp)
2262 {
2263 struct mlx5_core_dev *mdev = priv->mdev;
2264 void *rqtc;
2265 int inlen;
2266 u32 *in;
2267 int err;
2268
2269 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2270 in = kvzalloc(inlen, GFP_KERNEL);
2271 if (!in)
2272 return -ENOMEM;
2273
2274 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2275
2276 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2277 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2278 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2279 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2280
2281 kvfree(in);
2282 return err;
2283 }
2284
2285 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2286 struct mlx5e_redirect_rqt_param rrp)
2287 {
2288 if (!rrp.is_rss)
2289 return rrp.rqn;
2290
2291 if (ix >= rrp.rss.channels->num)
2292 return priv->drop_rq.rqn;
2293
2294 return rrp.rss.channels->c[ix]->rq.rqn;
2295 }
2296
2297 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2298 struct mlx5e_redirect_rqt_param rrp)
2299 {
2300 u32 rqtn;
2301 int ix;
2302
2303 if (priv->indir_rqt.enabled) {
2304 /* RSS RQ table */
2305 rqtn = priv->indir_rqt.rqtn;
2306 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2307 }
2308
2309 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2310 struct mlx5e_redirect_rqt_param direct_rrp = {
2311 .is_rss = false,
2312 {
2313 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2314 },
2315 };
2316
2317 /* Direct RQ Tables */
2318 if (!priv->direct_tir[ix].rqt.enabled)
2319 continue;
2320
2321 rqtn = priv->direct_tir[ix].rqt.rqtn;
2322 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2323 }
2324 }
2325
2326 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2327 struct mlx5e_channels *chs)
2328 {
2329 struct mlx5e_redirect_rqt_param rrp = {
2330 .is_rss = true,
2331 {
2332 .rss = {
2333 .channels = chs,
2334 .hfunc = chs->params.rss_hfunc,
2335 }
2336 },
2337 };
2338
2339 mlx5e_redirect_rqts(priv, rrp);
2340 }
2341
2342 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2343 {
2344 struct mlx5e_redirect_rqt_param drop_rrp = {
2345 .is_rss = false,
2346 {
2347 .rqn = priv->drop_rq.rqn,
2348 },
2349 };
2350
2351 mlx5e_redirect_rqts(priv, drop_rrp);
2352 }
2353
2354 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2355 {
2356 if (!params->lro_en)
2357 return;
2358
2359 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2360
2361 MLX5_SET(tirc, tirc, lro_enable_mask,
2362 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2363 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2364 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2365 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2366 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2367 }
2368
2369 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2370 enum mlx5e_traffic_types tt,
2371 void *tirc, bool inner)
2372 {
2373 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2374 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2375
2376 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2377 MLX5_HASH_FIELD_SEL_DST_IP)
2378
2379 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2380 MLX5_HASH_FIELD_SEL_DST_IP |\
2381 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2382 MLX5_HASH_FIELD_SEL_L4_DPORT)
2383
2384 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2385 MLX5_HASH_FIELD_SEL_DST_IP |\
2386 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2387
2388 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2389 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2390 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2391 rx_hash_toeplitz_key);
2392 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2393 rx_hash_toeplitz_key);
2394
2395 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2396 memcpy(rss_key, params->toeplitz_hash_key, len);
2397 }
2398
2399 switch (tt) {
2400 case MLX5E_TT_IPV4_TCP:
2401 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2402 MLX5_L3_PROT_TYPE_IPV4);
2403 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2404 MLX5_L4_PROT_TYPE_TCP);
2405 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2406 MLX5_HASH_IP_L4PORTS);
2407 break;
2408
2409 case MLX5E_TT_IPV6_TCP:
2410 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2411 MLX5_L3_PROT_TYPE_IPV6);
2412 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2413 MLX5_L4_PROT_TYPE_TCP);
2414 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2415 MLX5_HASH_IP_L4PORTS);
2416 break;
2417
2418 case MLX5E_TT_IPV4_UDP:
2419 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2420 MLX5_L3_PROT_TYPE_IPV4);
2421 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2422 MLX5_L4_PROT_TYPE_UDP);
2423 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2424 MLX5_HASH_IP_L4PORTS);
2425 break;
2426
2427 case MLX5E_TT_IPV6_UDP:
2428 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2429 MLX5_L3_PROT_TYPE_IPV6);
2430 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2431 MLX5_L4_PROT_TYPE_UDP);
2432 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2433 MLX5_HASH_IP_L4PORTS);
2434 break;
2435
2436 case MLX5E_TT_IPV4_IPSEC_AH:
2437 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2438 MLX5_L3_PROT_TYPE_IPV4);
2439 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2440 MLX5_HASH_IP_IPSEC_SPI);
2441 break;
2442
2443 case MLX5E_TT_IPV6_IPSEC_AH:
2444 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2445 MLX5_L3_PROT_TYPE_IPV6);
2446 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2447 MLX5_HASH_IP_IPSEC_SPI);
2448 break;
2449
2450 case MLX5E_TT_IPV4_IPSEC_ESP:
2451 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2452 MLX5_L3_PROT_TYPE_IPV4);
2453 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2454 MLX5_HASH_IP_IPSEC_SPI);
2455 break;
2456
2457 case MLX5E_TT_IPV6_IPSEC_ESP:
2458 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2459 MLX5_L3_PROT_TYPE_IPV6);
2460 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2461 MLX5_HASH_IP_IPSEC_SPI);
2462 break;
2463
2464 case MLX5E_TT_IPV4:
2465 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2466 MLX5_L3_PROT_TYPE_IPV4);
2467 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2468 MLX5_HASH_IP);
2469 break;
2470
2471 case MLX5E_TT_IPV6:
2472 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2473 MLX5_L3_PROT_TYPE_IPV6);
2474 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2475 MLX5_HASH_IP);
2476 break;
2477 default:
2478 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2479 }
2480 }
2481
2482 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2483 {
2484 struct mlx5_core_dev *mdev = priv->mdev;
2485
2486 void *in;
2487 void *tirc;
2488 int inlen;
2489 int err;
2490 int tt;
2491 int ix;
2492
2493 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2494 in = kvzalloc(inlen, GFP_KERNEL);
2495 if (!in)
2496 return -ENOMEM;
2497
2498 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2499 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2500
2501 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2502
2503 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2504 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2505 inlen);
2506 if (err)
2507 goto free_in;
2508 }
2509
2510 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2511 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2512 in, inlen);
2513 if (err)
2514 goto free_in;
2515 }
2516
2517 free_in:
2518 kvfree(in);
2519
2520 return err;
2521 }
2522
2523 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2524 enum mlx5e_traffic_types tt,
2525 u32 *tirc)
2526 {
2527 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2528
2529 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2530
2531 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2532 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2533 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2534
2535 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2536 }
2537
2538 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2539 {
2540 struct mlx5_core_dev *mdev = priv->mdev;
2541 u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
2542 int err;
2543
2544 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2545 if (err)
2546 return err;
2547
2548 /* Update vport context MTU */
2549 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2550 return 0;
2551 }
2552
2553 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2554 {
2555 struct mlx5_core_dev *mdev = priv->mdev;
2556 u16 hw_mtu = 0;
2557 int err;
2558
2559 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2560 if (err || !hw_mtu) /* fallback to port oper mtu */
2561 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2562
2563 *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
2564 }
2565
2566 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2567 {
2568 struct net_device *netdev = priv->netdev;
2569 u16 mtu;
2570 int err;
2571
2572 err = mlx5e_set_mtu(priv, netdev->mtu);
2573 if (err)
2574 return err;
2575
2576 mlx5e_query_mtu(priv, &mtu);
2577 if (mtu != netdev->mtu)
2578 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2579 __func__, mtu, netdev->mtu);
2580
2581 netdev->mtu = mtu;
2582 return 0;
2583 }
2584
2585 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2586 {
2587 struct mlx5e_priv *priv = netdev_priv(netdev);
2588 int nch = priv->channels.params.num_channels;
2589 int ntc = priv->channels.params.num_tc;
2590 int tc;
2591
2592 netdev_reset_tc(netdev);
2593
2594 if (ntc == 1)
2595 return;
2596
2597 netdev_set_num_tc(netdev, ntc);
2598
2599 /* Map netdev TCs to offset 0
2600 * We have our own UP to TXQ mapping for QoS
2601 */
2602 for (tc = 0; tc < ntc; tc++)
2603 netdev_set_tc_queue(netdev, tc, nch, 0);
2604 }
2605
2606 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2607 {
2608 struct mlx5e_channel *c;
2609 struct mlx5e_txqsq *sq;
2610 int i, tc;
2611
2612 for (i = 0; i < priv->channels.num; i++)
2613 for (tc = 0; tc < priv->profile->max_tc; tc++)
2614 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2615
2616 for (i = 0; i < priv->channels.num; i++) {
2617 c = priv->channels.c[i];
2618 for (tc = 0; tc < c->num_tc; tc++) {
2619 sq = &c->sq[tc];
2620 priv->txq2sq[sq->txq_ix] = sq;
2621 }
2622 }
2623 }
2624
2625 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2626 {
2627 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2628 struct net_device *netdev = priv->netdev;
2629
2630 mlx5e_netdev_set_tcs(netdev);
2631 netif_set_real_num_tx_queues(netdev, num_txqs);
2632 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2633
2634 mlx5e_build_channels_tx_maps(priv);
2635 mlx5e_activate_channels(&priv->channels);
2636 netif_tx_start_all_queues(priv->netdev);
2637
2638 if (MLX5_ESWITCH_MANAGER(priv->mdev))
2639 mlx5e_add_sqs_fwd_rules(priv);
2640
2641 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2642 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2643 }
2644
2645 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2646 {
2647 mlx5e_redirect_rqts_to_drop(priv);
2648
2649 if (MLX5_ESWITCH_MANAGER(priv->mdev))
2650 mlx5e_remove_sqs_fwd_rules(priv);
2651
2652 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2653 * polling for inactive tx queues.
2654 */
2655 netif_tx_stop_all_queues(priv->netdev);
2656 netif_tx_disable(priv->netdev);
2657 mlx5e_deactivate_channels(&priv->channels);
2658 }
2659
2660 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2661 struct mlx5e_channels *new_chs,
2662 mlx5e_fp_hw_modify hw_modify)
2663 {
2664 struct net_device *netdev = priv->netdev;
2665 int new_num_txqs;
2666 int carrier_ok;
2667 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2668
2669 carrier_ok = netif_carrier_ok(netdev);
2670 netif_carrier_off(netdev);
2671
2672 if (new_num_txqs < netdev->real_num_tx_queues)
2673 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2674
2675 mlx5e_deactivate_priv_channels(priv);
2676 mlx5e_close_channels(&priv->channels);
2677
2678 priv->channels = *new_chs;
2679
2680 /* New channels are ready to roll, modify HW settings if needed */
2681 if (hw_modify)
2682 hw_modify(priv);
2683
2684 mlx5e_refresh_tirs(priv, false);
2685 mlx5e_activate_priv_channels(priv);
2686
2687 /* return carrier back if needed */
2688 if (carrier_ok)
2689 netif_carrier_on(netdev);
2690 }
2691
2692 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2693 {
2694 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2695 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2696 }
2697
2698 int mlx5e_open_locked(struct net_device *netdev)
2699 {
2700 struct mlx5e_priv *priv = netdev_priv(netdev);
2701 int err;
2702
2703 set_bit(MLX5E_STATE_OPENED, &priv->state);
2704
2705 err = mlx5e_open_channels(priv, &priv->channels);
2706 if (err)
2707 goto err_clear_state_opened_flag;
2708
2709 mlx5e_refresh_tirs(priv, false);
2710 mlx5e_activate_priv_channels(priv);
2711 if (priv->profile->update_carrier)
2712 priv->profile->update_carrier(priv);
2713
2714 if (priv->profile->update_stats)
2715 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2716
2717 return 0;
2718
2719 err_clear_state_opened_flag:
2720 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2721 return err;
2722 }
2723
2724 int mlx5e_open(struct net_device *netdev)
2725 {
2726 struct mlx5e_priv *priv = netdev_priv(netdev);
2727 int err;
2728
2729 mutex_lock(&priv->state_lock);
2730 err = mlx5e_open_locked(netdev);
2731 if (!err)
2732 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2733 mutex_unlock(&priv->state_lock);
2734
2735 if (mlx5e_vxlan_allowed(priv->mdev))
2736 udp_tunnel_get_rx_info(netdev);
2737
2738 return err;
2739 }
2740
2741 int mlx5e_close_locked(struct net_device *netdev)
2742 {
2743 struct mlx5e_priv *priv = netdev_priv(netdev);
2744
2745 /* May already be CLOSED in case a previous configuration operation
2746 * (e.g RX/TX queue size change) that involves close&open failed.
2747 */
2748 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2749 return 0;
2750
2751 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2752
2753 netif_carrier_off(priv->netdev);
2754 mlx5e_deactivate_priv_channels(priv);
2755 mlx5e_close_channels(&priv->channels);
2756
2757 return 0;
2758 }
2759
2760 int mlx5e_close(struct net_device *netdev)
2761 {
2762 struct mlx5e_priv *priv = netdev_priv(netdev);
2763 int err;
2764
2765 if (!netif_device_present(netdev))
2766 return -ENODEV;
2767
2768 mutex_lock(&priv->state_lock);
2769 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2770 err = mlx5e_close_locked(netdev);
2771 mutex_unlock(&priv->state_lock);
2772
2773 return err;
2774 }
2775
2776 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2777 struct mlx5e_rq *rq,
2778 struct mlx5e_rq_param *param)
2779 {
2780 void *rqc = param->rqc;
2781 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2782 int err;
2783
2784 param->wq.db_numa_node = param->wq.buf_numa_node;
2785
2786 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2787 &rq->wq_ctrl);
2788 if (err)
2789 return err;
2790
2791 rq->mdev = mdev;
2792
2793 return 0;
2794 }
2795
2796 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2797 struct mlx5e_cq *cq,
2798 struct mlx5e_cq_param *param)
2799 {
2800 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2801 param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev);
2802
2803 return mlx5e_alloc_cq_common(mdev, param, cq);
2804 }
2805
2806 static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2807 struct mlx5e_rq *drop_rq)
2808 {
2809 struct mlx5e_cq_param cq_param = {};
2810 struct mlx5e_rq_param rq_param = {};
2811 struct mlx5e_cq *cq = &drop_rq->cq;
2812 int err;
2813
2814 mlx5e_build_drop_rq_param(mdev, &rq_param);
2815
2816 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2817 if (err)
2818 return err;
2819
2820 err = mlx5e_create_cq(cq, &cq_param);
2821 if (err)
2822 goto err_free_cq;
2823
2824 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2825 if (err)
2826 goto err_destroy_cq;
2827
2828 err = mlx5e_create_rq(drop_rq, &rq_param);
2829 if (err)
2830 goto err_free_rq;
2831
2832 return 0;
2833
2834 err_free_rq:
2835 mlx5e_free_rq(drop_rq);
2836
2837 err_destroy_cq:
2838 mlx5e_destroy_cq(cq);
2839
2840 err_free_cq:
2841 mlx5e_free_cq(cq);
2842
2843 return err;
2844 }
2845
2846 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2847 {
2848 mlx5e_destroy_rq(drop_rq);
2849 mlx5e_free_rq(drop_rq);
2850 mlx5e_destroy_cq(&drop_rq->cq);
2851 mlx5e_free_cq(&drop_rq->cq);
2852 }
2853
2854 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2855 u32 underlay_qpn, u32 *tisn)
2856 {
2857 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2858 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2859
2860 MLX5_SET(tisc, tisc, prio, tc << 1);
2861 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2862 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2863
2864 if (mlx5_lag_is_lacp_owner(mdev))
2865 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2866
2867 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2868 }
2869
2870 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2871 {
2872 mlx5_core_destroy_tis(mdev, tisn);
2873 }
2874
2875 int mlx5e_create_tises(struct mlx5e_priv *priv)
2876 {
2877 int err;
2878 int tc;
2879
2880 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2881 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2882 if (err)
2883 goto err_close_tises;
2884 }
2885
2886 return 0;
2887
2888 err_close_tises:
2889 for (tc--; tc >= 0; tc--)
2890 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2891
2892 return err;
2893 }
2894
2895 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2896 {
2897 int tc;
2898
2899 for (tc = 0; tc < priv->profile->max_tc; tc++)
2900 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2901 }
2902
2903 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2904 enum mlx5e_traffic_types tt,
2905 u32 *tirc)
2906 {
2907 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2908
2909 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2910
2911 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2912 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2913 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2914 }
2915
2916 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2917 {
2918 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2919
2920 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2921
2922 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2923 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2924 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2925 }
2926
2927 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2928 {
2929 struct mlx5e_tir *tir;
2930 void *tirc;
2931 int inlen;
2932 int i = 0;
2933 int err;
2934 u32 *in;
2935 int tt;
2936
2937 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2938 in = kvzalloc(inlen, GFP_KERNEL);
2939 if (!in)
2940 return -ENOMEM;
2941
2942 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2943 memset(in, 0, inlen);
2944 tir = &priv->indir_tir[tt];
2945 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2946 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2947 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2948 if (err) {
2949 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2950 goto err_destroy_inner_tirs;
2951 }
2952 }
2953
2954 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2955 goto out;
2956
2957 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2958 memset(in, 0, inlen);
2959 tir = &priv->inner_indir_tir[i];
2960 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2961 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2962 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2963 if (err) {
2964 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2965 goto err_destroy_inner_tirs;
2966 }
2967 }
2968
2969 out:
2970 kvfree(in);
2971
2972 return 0;
2973
2974 err_destroy_inner_tirs:
2975 for (i--; i >= 0; i--)
2976 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2977
2978 for (tt--; tt >= 0; tt--)
2979 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2980
2981 kvfree(in);
2982
2983 return err;
2984 }
2985
2986 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2987 {
2988 int nch = priv->profile->max_nch(priv->mdev);
2989 struct mlx5e_tir *tir;
2990 void *tirc;
2991 int inlen;
2992 int err;
2993 u32 *in;
2994 int ix;
2995
2996 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2997 in = kvzalloc(inlen, GFP_KERNEL);
2998 if (!in)
2999 return -ENOMEM;
3000
3001 for (ix = 0; ix < nch; ix++) {
3002 memset(in, 0, inlen);
3003 tir = &priv->direct_tir[ix];
3004 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3005 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3006 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3007 if (err)
3008 goto err_destroy_ch_tirs;
3009 }
3010
3011 kvfree(in);
3012
3013 return 0;
3014
3015 err_destroy_ch_tirs:
3016 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3017 for (ix--; ix >= 0; ix--)
3018 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3019
3020 kvfree(in);
3021
3022 return err;
3023 }
3024
3025 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3026 {
3027 int i;
3028
3029 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3030 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3031
3032 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3033 return;
3034
3035 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3036 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3037 }
3038
3039 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3040 {
3041 int nch = priv->profile->max_nch(priv->mdev);
3042 int i;
3043
3044 for (i = 0; i < nch; i++)
3045 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3046 }
3047
3048 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3049 {
3050 int err = 0;
3051 int i;
3052
3053 for (i = 0; i < chs->num; i++) {
3054 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3055 if (err)
3056 return err;
3057 }
3058
3059 return 0;
3060 }
3061
3062 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3063 {
3064 int err = 0;
3065 int i;
3066
3067 for (i = 0; i < chs->num; i++) {
3068 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3069 if (err)
3070 return err;
3071 }
3072
3073 return 0;
3074 }
3075
3076 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3077 struct tc_mqprio_qopt *mqprio)
3078 {
3079 struct mlx5e_priv *priv = netdev_priv(netdev);
3080 struct mlx5e_channels new_channels = {};
3081 u8 tc = mqprio->num_tc;
3082 int err = 0;
3083
3084 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3085
3086 if (tc && tc != MLX5E_MAX_NUM_TC)
3087 return -EINVAL;
3088
3089 mutex_lock(&priv->state_lock);
3090
3091 new_channels.params = priv->channels.params;
3092 new_channels.params.num_tc = tc ? tc : 1;
3093
3094 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3095 priv->channels.params = new_channels.params;
3096 goto out;
3097 }
3098
3099 err = mlx5e_open_channels(priv, &new_channels);
3100 if (err)
3101 goto out;
3102
3103 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3104 out:
3105 mutex_unlock(&priv->state_lock);
3106 return err;
3107 }
3108
3109 #ifdef CONFIG_MLX5_ESWITCH
3110 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3111 struct tc_cls_flower_offload *cls_flower)
3112 {
3113 if (cls_flower->common.chain_index)
3114 return -EOPNOTSUPP;
3115
3116 switch (cls_flower->command) {
3117 case TC_CLSFLOWER_REPLACE:
3118 return mlx5e_configure_flower(priv, cls_flower);
3119 case TC_CLSFLOWER_DESTROY:
3120 return mlx5e_delete_flower(priv, cls_flower);
3121 case TC_CLSFLOWER_STATS:
3122 return mlx5e_stats_flower(priv, cls_flower);
3123 default:
3124 return -EOPNOTSUPP;
3125 }
3126 }
3127
3128 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3129 void *cb_priv)
3130 {
3131 struct mlx5e_priv *priv = cb_priv;
3132
3133 if (!tc_can_offload(priv->netdev))
3134 return -EOPNOTSUPP;
3135
3136 switch (type) {
3137 case TC_SETUP_CLSFLOWER:
3138 return mlx5e_setup_tc_cls_flower(priv, type_data);
3139 default:
3140 return -EOPNOTSUPP;
3141 }
3142 }
3143
3144 static int mlx5e_setup_tc_block(struct net_device *dev,
3145 struct tc_block_offload *f)
3146 {
3147 struct mlx5e_priv *priv = netdev_priv(dev);
3148
3149 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3150 return -EOPNOTSUPP;
3151
3152 switch (f->command) {
3153 case TC_BLOCK_BIND:
3154 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3155 priv, priv);
3156 case TC_BLOCK_UNBIND:
3157 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3158 priv);
3159 return 0;
3160 default:
3161 return -EOPNOTSUPP;
3162 }
3163 }
3164 #endif
3165
3166 int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3167 void *type_data)
3168 {
3169 switch (type) {
3170 #ifdef CONFIG_MLX5_ESWITCH
3171 case TC_SETUP_BLOCK:
3172 return mlx5e_setup_tc_block(dev, type_data);
3173 #endif
3174 case TC_SETUP_QDISC_MQPRIO:
3175 return mlx5e_setup_tc_mqprio(dev, type_data);
3176 default:
3177 return -EOPNOTSUPP;
3178 }
3179 }
3180
3181 static void
3182 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3183 {
3184 struct mlx5e_priv *priv = netdev_priv(dev);
3185 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3186 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3187 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3188
3189 if (mlx5e_is_uplink_rep(priv)) {
3190 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3191 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3192 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3193 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3194 } else {
3195 stats->rx_packets = sstats->rx_packets;
3196 stats->rx_bytes = sstats->rx_bytes;
3197 stats->tx_packets = sstats->tx_packets;
3198 stats->tx_bytes = sstats->tx_bytes;
3199 stats->tx_dropped = sstats->tx_queue_dropped;
3200 }
3201
3202 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3203
3204 stats->rx_length_errors =
3205 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3206 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3207 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3208 stats->rx_crc_errors =
3209 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3210 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3211 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3212 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3213 stats->rx_frame_errors;
3214 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3215
3216 /* vport multicast also counts packets that are dropped due to steering
3217 * or rx out of buffer
3218 */
3219 stats->multicast =
3220 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3221 }
3222
3223 static void mlx5e_set_rx_mode(struct net_device *dev)
3224 {
3225 struct mlx5e_priv *priv = netdev_priv(dev);
3226
3227 queue_work(priv->wq, &priv->set_rx_mode_work);
3228 }
3229
3230 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3231 {
3232 struct mlx5e_priv *priv = netdev_priv(netdev);
3233 struct sockaddr *saddr = addr;
3234
3235 if (!is_valid_ether_addr(saddr->sa_data))
3236 return -EADDRNOTAVAIL;
3237
3238 netif_addr_lock_bh(netdev);
3239 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3240 netif_addr_unlock_bh(netdev);
3241
3242 queue_work(priv->wq, &priv->set_rx_mode_work);
3243
3244 return 0;
3245 }
3246
3247 #define MLX5E_SET_FEATURE(features, feature, enable) \
3248 do { \
3249 if (enable) \
3250 *features |= feature; \
3251 else \
3252 *features &= ~feature; \
3253 } while (0)
3254
3255 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3256
3257 static int set_feature_lro(struct net_device *netdev, bool enable)
3258 {
3259 struct mlx5e_priv *priv = netdev_priv(netdev);
3260 struct mlx5e_channels new_channels = {};
3261 int err = 0;
3262 bool reset;
3263
3264 mutex_lock(&priv->state_lock);
3265
3266 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3267 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3268
3269 new_channels.params = priv->channels.params;
3270 new_channels.params.lro_en = enable;
3271
3272 if (!reset) {
3273 priv->channels.params = new_channels.params;
3274 err = mlx5e_modify_tirs_lro(priv);
3275 goto out;
3276 }
3277
3278 err = mlx5e_open_channels(priv, &new_channels);
3279 if (err)
3280 goto out;
3281
3282 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3283 out:
3284 mutex_unlock(&priv->state_lock);
3285 return err;
3286 }
3287
3288 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3289 {
3290 struct mlx5e_priv *priv = netdev_priv(netdev);
3291
3292 if (enable)
3293 mlx5e_enable_cvlan_filter(priv);
3294 else
3295 mlx5e_disable_cvlan_filter(priv);
3296
3297 return 0;
3298 }
3299
3300 #ifdef CONFIG_MLX5_ESWITCH
3301 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3302 {
3303 struct mlx5e_priv *priv = netdev_priv(netdev);
3304
3305 if (!enable && mlx5e_tc_num_filters(priv)) {
3306 netdev_err(netdev,
3307 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3308 return -EINVAL;
3309 }
3310
3311 return 0;
3312 }
3313 #endif
3314
3315 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3316 {
3317 struct mlx5e_priv *priv = netdev_priv(netdev);
3318 struct mlx5_core_dev *mdev = priv->mdev;
3319
3320 return mlx5_set_port_fcs(mdev, !enable);
3321 }
3322
3323 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3324 {
3325 struct mlx5e_priv *priv = netdev_priv(netdev);
3326 int err;
3327
3328 mutex_lock(&priv->state_lock);
3329
3330 priv->channels.params.scatter_fcs_en = enable;
3331 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3332 if (err)
3333 priv->channels.params.scatter_fcs_en = !enable;
3334
3335 mutex_unlock(&priv->state_lock);
3336
3337 return err;
3338 }
3339
3340 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3341 {
3342 struct mlx5e_priv *priv = netdev_priv(netdev);
3343 int err = 0;
3344
3345 mutex_lock(&priv->state_lock);
3346
3347 priv->channels.params.vlan_strip_disable = !enable;
3348 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3349 goto unlock;
3350
3351 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3352 if (err)
3353 priv->channels.params.vlan_strip_disable = enable;
3354
3355 unlock:
3356 mutex_unlock(&priv->state_lock);
3357
3358 return err;
3359 }
3360
3361 #ifdef CONFIG_RFS_ACCEL
3362 static int set_feature_arfs(struct net_device *netdev, bool enable)
3363 {
3364 struct mlx5e_priv *priv = netdev_priv(netdev);
3365 int err;
3366
3367 if (enable)
3368 err = mlx5e_arfs_enable(priv);
3369 else
3370 err = mlx5e_arfs_disable(priv);
3371
3372 return err;
3373 }
3374 #endif
3375
3376 static int mlx5e_handle_feature(struct net_device *netdev,
3377 netdev_features_t *features,
3378 netdev_features_t wanted_features,
3379 netdev_features_t feature,
3380 mlx5e_feature_handler feature_handler)
3381 {
3382 netdev_features_t changes = wanted_features ^ netdev->features;
3383 bool enable = !!(wanted_features & feature);
3384 int err;
3385
3386 if (!(changes & feature))
3387 return 0;
3388
3389 err = feature_handler(netdev, enable);
3390 if (err) {
3391 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3392 enable ? "Enable" : "Disable", &feature, err);
3393 return err;
3394 }
3395
3396 MLX5E_SET_FEATURE(features, feature, enable);
3397 return 0;
3398 }
3399
3400 static int mlx5e_set_features(struct net_device *netdev,
3401 netdev_features_t features)
3402 {
3403 netdev_features_t oper_features = netdev->features;
3404 int err;
3405
3406 err = mlx5e_handle_feature(netdev, &oper_features, features,
3407 NETIF_F_LRO, set_feature_lro);
3408 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3409 NETIF_F_HW_VLAN_CTAG_FILTER,
3410 set_feature_cvlan_filter);
3411 #ifdef CONFIG_MLX5_ESWITCH
3412 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3413 NETIF_F_HW_TC, set_feature_tc_num_filters);
3414 #endif
3415 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3416 NETIF_F_RXALL, set_feature_rx_all);
3417 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3418 NETIF_F_RXFCS, set_feature_rx_fcs);
3419 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3420 NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3421 #ifdef CONFIG_RFS_ACCEL
3422 err |= mlx5e_handle_feature(netdev, &oper_features, features,
3423 NETIF_F_NTUPLE, set_feature_arfs);
3424 #endif
3425
3426 if (err) {
3427 netdev->features = oper_features;
3428 return -EINVAL;
3429 }
3430
3431 return 0;
3432 }
3433
3434 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3435 netdev_features_t features)
3436 {
3437 struct mlx5e_priv *priv = netdev_priv(netdev);
3438
3439 mutex_lock(&priv->state_lock);
3440 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3441 /* HW strips the outer C-tag header, this is a problem
3442 * for S-tag traffic.
3443 */
3444 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3445 if (!priv->channels.params.vlan_strip_disable)
3446 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3447 }
3448 mutex_unlock(&priv->state_lock);
3449
3450 return features;
3451 }
3452
3453 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3454 {
3455 struct mlx5e_priv *priv = netdev_priv(netdev);
3456 struct mlx5e_channels new_channels = {};
3457 int curr_mtu;
3458 int err = 0;
3459 bool reset;
3460
3461 mutex_lock(&priv->state_lock);
3462
3463 reset = !priv->channels.params.lro_en &&
3464 (priv->channels.params.rq_wq_type !=
3465 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3466
3467 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3468
3469 curr_mtu = netdev->mtu;
3470 netdev->mtu = new_mtu;
3471
3472 if (!reset) {
3473 mlx5e_set_dev_port_mtu(priv);
3474 goto out;
3475 }
3476
3477 new_channels.params = priv->channels.params;
3478 err = mlx5e_open_channels(priv, &new_channels);
3479 if (err) {
3480 netdev->mtu = curr_mtu;
3481 goto out;
3482 }
3483
3484 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3485
3486 out:
3487 mutex_unlock(&priv->state_lock);
3488 return err;
3489 }
3490
3491 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3492 {
3493 struct hwtstamp_config config;
3494 int err;
3495
3496 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3497 return -EOPNOTSUPP;
3498
3499 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3500 return -EFAULT;
3501
3502 /* TX HW timestamp */
3503 switch (config.tx_type) {
3504 case HWTSTAMP_TX_OFF:
3505 case HWTSTAMP_TX_ON:
3506 break;
3507 default:
3508 return -ERANGE;
3509 }
3510
3511 mutex_lock(&priv->state_lock);
3512 /* RX HW timestamp */
3513 switch (config.rx_filter) {
3514 case HWTSTAMP_FILTER_NONE:
3515 /* Reset CQE compression to Admin default */
3516 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3517 break;
3518 case HWTSTAMP_FILTER_ALL:
3519 case HWTSTAMP_FILTER_SOME:
3520 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3521 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3522 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3523 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3524 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3525 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3526 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3527 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3528 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3529 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3530 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3531 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3532 case HWTSTAMP_FILTER_NTP_ALL:
3533 /* Disable CQE compression */
3534 netdev_warn(priv->netdev, "Disabling cqe compression");
3535 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3536 if (err) {
3537 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3538 mutex_unlock(&priv->state_lock);
3539 return err;
3540 }
3541 config.rx_filter = HWTSTAMP_FILTER_ALL;
3542 break;
3543 default:
3544 mutex_unlock(&priv->state_lock);
3545 return -ERANGE;
3546 }
3547
3548 memcpy(&priv->tstamp, &config, sizeof(config));
3549 mutex_unlock(&priv->state_lock);
3550
3551 return copy_to_user(ifr->ifr_data, &config,
3552 sizeof(config)) ? -EFAULT : 0;
3553 }
3554
3555 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3556 {
3557 struct hwtstamp_config *cfg = &priv->tstamp;
3558
3559 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3560 return -EOPNOTSUPP;
3561
3562 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3563 }
3564
3565 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3566 {
3567 struct mlx5e_priv *priv = netdev_priv(dev);
3568
3569 switch (cmd) {
3570 case SIOCSHWTSTAMP:
3571 return mlx5e_hwstamp_set(priv, ifr);
3572 case SIOCGHWTSTAMP:
3573 return mlx5e_hwstamp_get(priv, ifr);
3574 default:
3575 return -EOPNOTSUPP;
3576 }
3577 }
3578
3579 #ifdef CONFIG_MLX5_ESWITCH
3580 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3581 {
3582 struct mlx5e_priv *priv = netdev_priv(dev);
3583 struct mlx5_core_dev *mdev = priv->mdev;
3584
3585 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3586 }
3587
3588 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3589 __be16 vlan_proto)
3590 {
3591 struct mlx5e_priv *priv = netdev_priv(dev);
3592 struct mlx5_core_dev *mdev = priv->mdev;
3593
3594 if (vlan_proto != htons(ETH_P_8021Q))
3595 return -EPROTONOSUPPORT;
3596
3597 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3598 vlan, qos);
3599 }
3600
3601 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3602 {
3603 struct mlx5e_priv *priv = netdev_priv(dev);
3604 struct mlx5_core_dev *mdev = priv->mdev;
3605
3606 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3607 }
3608
3609 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3610 {
3611 struct mlx5e_priv *priv = netdev_priv(dev);
3612 struct mlx5_core_dev *mdev = priv->mdev;
3613
3614 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3615 }
3616
3617 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3618 int max_tx_rate)
3619 {
3620 struct mlx5e_priv *priv = netdev_priv(dev);
3621 struct mlx5_core_dev *mdev = priv->mdev;
3622
3623 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3624 max_tx_rate, min_tx_rate);
3625 }
3626
3627 static int mlx5_vport_link2ifla(u8 esw_link)
3628 {
3629 switch (esw_link) {
3630 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3631 return IFLA_VF_LINK_STATE_DISABLE;
3632 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3633 return IFLA_VF_LINK_STATE_ENABLE;
3634 }
3635 return IFLA_VF_LINK_STATE_AUTO;
3636 }
3637
3638 static int mlx5_ifla_link2vport(u8 ifla_link)
3639 {
3640 switch (ifla_link) {
3641 case IFLA_VF_LINK_STATE_DISABLE:
3642 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3643 case IFLA_VF_LINK_STATE_ENABLE:
3644 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3645 }
3646 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3647 }
3648
3649 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3650 int link_state)
3651 {
3652 struct mlx5e_priv *priv = netdev_priv(dev);
3653 struct mlx5_core_dev *mdev = priv->mdev;
3654
3655 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3656 mlx5_ifla_link2vport(link_state));
3657 }
3658
3659 static int mlx5e_get_vf_config(struct net_device *dev,
3660 int vf, struct ifla_vf_info *ivi)
3661 {
3662 struct mlx5e_priv *priv = netdev_priv(dev);
3663 struct mlx5_core_dev *mdev = priv->mdev;
3664 int err;
3665
3666 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3667 if (err)
3668 return err;
3669 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3670 return 0;
3671 }
3672
3673 static int mlx5e_get_vf_stats(struct net_device *dev,
3674 int vf, struct ifla_vf_stats *vf_stats)
3675 {
3676 struct mlx5e_priv *priv = netdev_priv(dev);
3677 struct mlx5_core_dev *mdev = priv->mdev;
3678
3679 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3680 vf_stats);
3681 }
3682 #endif
3683
3684 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3685 struct udp_tunnel_info *ti)
3686 {
3687 struct mlx5e_priv *priv = netdev_priv(netdev);
3688
3689 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3690 return;
3691
3692 if (!mlx5e_vxlan_allowed(priv->mdev))
3693 return;
3694
3695 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3696 }
3697
3698 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3699 struct udp_tunnel_info *ti)
3700 {
3701 struct mlx5e_priv *priv = netdev_priv(netdev);
3702
3703 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3704 return;
3705
3706 if (!mlx5e_vxlan_allowed(priv->mdev))
3707 return;
3708
3709 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3710 }
3711
3712 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3713 struct sk_buff *skb,
3714 netdev_features_t features)
3715 {
3716 unsigned int offset = 0;
3717 struct udphdr *udph;
3718 u8 proto;
3719 u16 port;
3720
3721 switch (vlan_get_protocol(skb)) {
3722 case htons(ETH_P_IP):
3723 proto = ip_hdr(skb)->protocol;
3724 break;
3725 case htons(ETH_P_IPV6):
3726 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3727 break;
3728 default:
3729 goto out;
3730 }
3731
3732 switch (proto) {
3733 case IPPROTO_GRE:
3734 return features;
3735 case IPPROTO_UDP:
3736 udph = udp_hdr(skb);
3737 port = be16_to_cpu(udph->dest);
3738
3739 /* Verify if UDP port is being offloaded by HW */
3740 if (mlx5e_vxlan_lookup_port(priv, port))
3741 return features;
3742 }
3743
3744 out:
3745 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3746 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3747 }
3748
3749 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3750 struct net_device *netdev,
3751 netdev_features_t features)
3752 {
3753 struct mlx5e_priv *priv = netdev_priv(netdev);
3754
3755 features = vlan_features_check(skb, features);
3756 features = vxlan_features_check(skb, features);
3757
3758 #ifdef CONFIG_MLX5_EN_IPSEC
3759 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3760 return features;
3761 #endif
3762
3763 /* Validate if the tunneled packet is being offloaded by HW */
3764 if (skb->encapsulation &&
3765 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3766 return mlx5e_tunnel_features_check(priv, skb, features);
3767
3768 return features;
3769 }
3770
3771 static void mlx5e_tx_timeout(struct net_device *dev)
3772 {
3773 struct mlx5e_priv *priv = netdev_priv(dev);
3774 bool sched_work = false;
3775 int i;
3776
3777 netdev_err(dev, "TX timeout detected\n");
3778
3779 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3780 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3781
3782 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3783 continue;
3784 sched_work = true;
3785 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3786 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3787 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3788 }
3789
3790 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3791 schedule_work(&priv->tx_timeout_work);
3792 }
3793
3794 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3795 {
3796 struct mlx5e_priv *priv = netdev_priv(netdev);
3797 struct bpf_prog *old_prog;
3798 int err = 0;
3799 bool reset, was_opened;
3800 int i;
3801
3802 mutex_lock(&priv->state_lock);
3803
3804 if ((netdev->features & NETIF_F_LRO) && prog) {
3805 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3806 err = -EINVAL;
3807 goto unlock;
3808 }
3809
3810 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3811 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3812 err = -EINVAL;
3813 goto unlock;
3814 }
3815
3816 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3817 /* no need for full reset when exchanging programs */
3818 reset = (!priv->channels.params.xdp_prog || !prog);
3819
3820 if (was_opened && reset)
3821 mlx5e_close_locked(netdev);
3822 if (was_opened && !reset) {
3823 /* num_channels is invariant here, so we can take the
3824 * batched reference right upfront.
3825 */
3826 prog = bpf_prog_add(prog, priv->channels.num);
3827 if (IS_ERR(prog)) {
3828 err = PTR_ERR(prog);
3829 goto unlock;
3830 }
3831 }
3832
3833 /* exchange programs, extra prog reference we got from caller
3834 * as long as we don't fail from this point onwards.
3835 */
3836 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3837 if (old_prog)
3838 bpf_prog_put(old_prog);
3839
3840 if (reset) /* change RQ type according to priv->xdp_prog */
3841 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
3842
3843 if (was_opened && reset)
3844 mlx5e_open_locked(netdev);
3845
3846 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3847 goto unlock;
3848
3849 /* exchanging programs w/o reset, we update ref counts on behalf
3850 * of the channels RQs here.
3851 */
3852 for (i = 0; i < priv->channels.num; i++) {
3853 struct mlx5e_channel *c = priv->channels.c[i];
3854
3855 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3856 napi_synchronize(&c->napi);
3857 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3858
3859 old_prog = xchg(&c->rq.xdp_prog, prog);
3860
3861 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3862 /* napi_schedule in case we have missed anything */
3863 napi_schedule(&c->napi);
3864
3865 if (old_prog)
3866 bpf_prog_put(old_prog);
3867 }
3868
3869 unlock:
3870 mutex_unlock(&priv->state_lock);
3871 return err;
3872 }
3873
3874 static u32 mlx5e_xdp_query(struct net_device *dev)
3875 {
3876 struct mlx5e_priv *priv = netdev_priv(dev);
3877 const struct bpf_prog *xdp_prog;
3878 u32 prog_id = 0;
3879
3880 mutex_lock(&priv->state_lock);
3881 xdp_prog = priv->channels.params.xdp_prog;
3882 if (xdp_prog)
3883 prog_id = xdp_prog->aux->id;
3884 mutex_unlock(&priv->state_lock);
3885
3886 return prog_id;
3887 }
3888
3889 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3890 {
3891 switch (xdp->command) {
3892 case XDP_SETUP_PROG:
3893 return mlx5e_xdp_set(dev, xdp->prog);
3894 case XDP_QUERY_PROG:
3895 xdp->prog_id = mlx5e_xdp_query(dev);
3896 xdp->prog_attached = !!xdp->prog_id;
3897 return 0;
3898 default:
3899 return -EINVAL;
3900 }
3901 }
3902
3903 #ifdef CONFIG_NET_POLL_CONTROLLER
3904 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3905 * reenabling interrupts.
3906 */
3907 static void mlx5e_netpoll(struct net_device *dev)
3908 {
3909 struct mlx5e_priv *priv = netdev_priv(dev);
3910 struct mlx5e_channels *chs = &priv->channels;
3911
3912 int i;
3913
3914 for (i = 0; i < chs->num; i++)
3915 napi_schedule(&chs->c[i]->napi);
3916 }
3917 #endif
3918
3919 static const struct net_device_ops mlx5e_netdev_ops = {
3920 .ndo_open = mlx5e_open,
3921 .ndo_stop = mlx5e_close,
3922 .ndo_start_xmit = mlx5e_xmit,
3923 .ndo_setup_tc = mlx5e_setup_tc,
3924 .ndo_select_queue = mlx5e_select_queue,
3925 .ndo_get_stats64 = mlx5e_get_stats,
3926 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3927 .ndo_set_mac_address = mlx5e_set_mac,
3928 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3929 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3930 .ndo_set_features = mlx5e_set_features,
3931 .ndo_fix_features = mlx5e_fix_features,
3932 .ndo_change_mtu = mlx5e_change_mtu,
3933 .ndo_do_ioctl = mlx5e_ioctl,
3934 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3935 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3936 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3937 .ndo_features_check = mlx5e_features_check,
3938 #ifdef CONFIG_RFS_ACCEL
3939 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3940 #endif
3941 .ndo_tx_timeout = mlx5e_tx_timeout,
3942 .ndo_bpf = mlx5e_xdp,
3943 #ifdef CONFIG_NET_POLL_CONTROLLER
3944 .ndo_poll_controller = mlx5e_netpoll,
3945 #endif
3946 #ifdef CONFIG_MLX5_ESWITCH
3947 /* SRIOV E-Switch NDOs */
3948 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3949 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
3950 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
3951 .ndo_set_vf_trust = mlx5e_set_vf_trust,
3952 .ndo_set_vf_rate = mlx5e_set_vf_rate,
3953 .ndo_get_vf_config = mlx5e_get_vf_config,
3954 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3955 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3956 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3957 .ndo_get_offload_stats = mlx5e_get_offload_stats,
3958 #endif
3959 };
3960
3961 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3962 {
3963 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3964 return -EOPNOTSUPP;
3965 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3966 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3967 !MLX5_CAP_ETH(mdev, csum_cap) ||
3968 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3969 !MLX5_CAP_ETH(mdev, vlan_cap) ||
3970 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3971 MLX5_CAP_FLOWTABLE(mdev,
3972 flow_table_properties_nic_receive.max_ft_level)
3973 < 3) {
3974 mlx5_core_warn(mdev,
3975 "Not creating net device, some required device capabilities are missing\n");
3976 return -EOPNOTSUPP;
3977 }
3978 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3979 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3980 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3981 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
3982
3983 return 0;
3984 }
3985
3986 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3987 {
3988 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3989
3990 return bf_buf_size -
3991 sizeof(struct mlx5e_tx_wqe) +
3992 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3993 }
3994
3995 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
3996 int num_channels)
3997 {
3998 int i;
3999
4000 for (i = 0; i < len; i++)
4001 indirection_rqt[i] = i % num_channels;
4002 }
4003
4004 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
4005 {
4006 enum pcie_link_width width;
4007 enum pci_bus_speed speed;
4008 int err = 0;
4009
4010 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
4011 if (err)
4012 return err;
4013
4014 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
4015 return -EINVAL;
4016
4017 switch (speed) {
4018 case PCIE_SPEED_2_5GT:
4019 *pci_bw = 2500 * width;
4020 break;
4021 case PCIE_SPEED_5_0GT:
4022 *pci_bw = 5000 * width;
4023 break;
4024 case PCIE_SPEED_8_0GT:
4025 *pci_bw = 8000 * width;
4026 break;
4027 default:
4028 return -EINVAL;
4029 }
4030
4031 return 0;
4032 }
4033
4034 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
4035 {
4036 return (link_speed && pci_bw &&
4037 (pci_bw < 40000) && (pci_bw < link_speed));
4038 }
4039
4040 static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
4041 {
4042 return !(link_speed && pci_bw &&
4043 (pci_bw <= 16000) && (pci_bw < link_speed));
4044 }
4045
4046 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4047 {
4048 params->tx_cq_moderation.cq_period_mode = cq_period_mode;
4049
4050 params->tx_cq_moderation.pkts =
4051 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4052 params->tx_cq_moderation.usec =
4053 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4054
4055 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4056 params->tx_cq_moderation.usec =
4057 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4058
4059 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4060 params->tx_cq_moderation.cq_period_mode ==
4061 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4062 }
4063
4064 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4065 {
4066 params->rx_cq_moderation.cq_period_mode = cq_period_mode;
4067
4068 params->rx_cq_moderation.pkts =
4069 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4070 params->rx_cq_moderation.usec =
4071 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4072
4073 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4074 params->rx_cq_moderation.usec =
4075 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4076
4077 if (params->rx_am_enabled)
4078 params->rx_cq_moderation =
4079 mlx5e_am_get_def_profile(cq_period_mode);
4080
4081 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4082 params->rx_cq_moderation.cq_period_mode ==
4083 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4084 }
4085
4086 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4087 {
4088 int i;
4089
4090 /* The supported periods are organized in ascending order */
4091 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4092 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4093 break;
4094
4095 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4096 }
4097
4098 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4099 struct mlx5e_params *params,
4100 u16 max_channels)
4101 {
4102 u8 rx_cq_period_mode;
4103 u32 link_speed = 0;
4104 u32 pci_bw = 0;
4105
4106 params->num_channels = max_channels;
4107 params->num_tc = 1;
4108
4109 mlx5e_get_max_linkspeed(mdev, &link_speed);
4110 mlx5e_get_pci_bw(mdev, &pci_bw);
4111 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
4112 link_speed, pci_bw);
4113
4114 /* SQ */
4115 params->log_sq_size = is_kdump_kernel() ?
4116 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4117 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4118
4119 /* set CQE compression */
4120 params->rx_cqe_compress_def = false;
4121 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4122 MLX5_CAP_GEN(mdev, vport_group_manager))
4123 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
4124
4125 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4126 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4127
4128 /* RQ */
4129 mlx5e_set_rq_params(mdev, params);
4130
4131 /* HW LRO */
4132
4133 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4134 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4135 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
4136 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4137
4138 /* CQ moderation params */
4139 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4140 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4141 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4142 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4143 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4144 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4145
4146 /* TX inline */
4147 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
4148 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4149
4150 /* RSS */
4151 params->rss_hfunc = ETH_RSS_HASH_XOR;
4152 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4153 mlx5e_build_default_indir_rqt(params->indirection_rqt,
4154 MLX5E_INDIR_RQT_SIZE, max_channels);
4155 }
4156
4157 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4158 struct net_device *netdev,
4159 const struct mlx5e_profile *profile,
4160 void *ppriv)
4161 {
4162 struct mlx5e_priv *priv = netdev_priv(netdev);
4163
4164 priv->mdev = mdev;
4165 priv->netdev = netdev;
4166 priv->profile = profile;
4167 priv->ppriv = ppriv;
4168 priv->msglevel = MLX5E_MSG_LEVEL;
4169 priv->hard_mtu = MLX5E_ETH_HARD_MTU;
4170
4171 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
4172
4173 mutex_init(&priv->state_lock);
4174
4175 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4176 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4177 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4178 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4179
4180 mlx5e_timestamp_init(priv);
4181 }
4182
4183 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4184 {
4185 struct mlx5e_priv *priv = netdev_priv(netdev);
4186
4187 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4188 if (is_zero_ether_addr(netdev->dev_addr) &&
4189 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4190 eth_hw_addr_random(netdev);
4191 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4192 }
4193 }
4194
4195 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4196 static const struct switchdev_ops mlx5e_switchdev_ops = {
4197 .switchdev_port_attr_get = mlx5e_attr_get,
4198 };
4199 #endif
4200
4201 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4202 {
4203 struct mlx5e_priv *priv = netdev_priv(netdev);
4204 struct mlx5_core_dev *mdev = priv->mdev;
4205 bool fcs_supported;
4206 bool fcs_enabled;
4207
4208 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4209
4210 netdev->netdev_ops = &mlx5e_netdev_ops;
4211
4212 #ifdef CONFIG_MLX5_CORE_EN_DCB
4213 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4214 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4215 #endif
4216
4217 netdev->watchdog_timeo = 15 * HZ;
4218
4219 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4220
4221 netdev->vlan_features |= NETIF_F_SG;
4222 netdev->vlan_features |= NETIF_F_IP_CSUM;
4223 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4224 netdev->vlan_features |= NETIF_F_GRO;
4225 netdev->vlan_features |= NETIF_F_TSO;
4226 netdev->vlan_features |= NETIF_F_TSO6;
4227 netdev->vlan_features |= NETIF_F_RXCSUM;
4228 netdev->vlan_features |= NETIF_F_RXHASH;
4229
4230 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4231 netdev->vlan_features |= NETIF_F_LRO;
4232
4233 netdev->hw_features = netdev->vlan_features;
4234 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4235 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4236 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4237 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4238
4239 if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4240 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4241 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4242 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4243 netdev->hw_enc_features |= NETIF_F_TSO;
4244 netdev->hw_enc_features |= NETIF_F_TSO6;
4245 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4246 }
4247
4248 if (mlx5e_vxlan_allowed(mdev)) {
4249 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4250 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4251 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4252 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4253 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4254 }
4255
4256 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4257 netdev->hw_features |= NETIF_F_GSO_GRE |
4258 NETIF_F_GSO_GRE_CSUM;
4259 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4260 NETIF_F_GSO_GRE_CSUM;
4261 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4262 NETIF_F_GSO_GRE_CSUM;
4263 }
4264
4265 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4266
4267 if (fcs_supported)
4268 netdev->hw_features |= NETIF_F_RXALL;
4269
4270 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4271 netdev->hw_features |= NETIF_F_RXFCS;
4272
4273 netdev->features = netdev->hw_features;
4274 if (!priv->channels.params.lro_en)
4275 netdev->features &= ~NETIF_F_LRO;
4276
4277 if (fcs_enabled)
4278 netdev->features &= ~NETIF_F_RXALL;
4279
4280 if (!priv->channels.params.scatter_fcs_en)
4281 netdev->features &= ~NETIF_F_RXFCS;
4282
4283 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4284 if (FT_CAP(flow_modify_en) &&
4285 FT_CAP(modify_root) &&
4286 FT_CAP(identified_miss_table_mode) &&
4287 FT_CAP(flow_table_modify)) {
4288 netdev->hw_features |= NETIF_F_HW_TC;
4289 #ifdef CONFIG_RFS_ACCEL
4290 netdev->hw_features |= NETIF_F_NTUPLE;
4291 #endif
4292 }
4293
4294 netdev->features |= NETIF_F_HIGHDMA;
4295 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4296
4297 netdev->priv_flags |= IFF_UNICAST_FLT;
4298
4299 mlx5e_set_netdev_dev_addr(netdev);
4300
4301 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4302 if (MLX5_ESWITCH_MANAGER(mdev))
4303 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4304 #endif
4305
4306 mlx5e_ipsec_build_netdev(priv);
4307 }
4308
4309 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4310 {
4311 struct mlx5_core_dev *mdev = priv->mdev;
4312 int err;
4313
4314 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4315 if (err) {
4316 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4317 priv->q_counter = 0;
4318 }
4319 }
4320
4321 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4322 {
4323 if (!priv->q_counter)
4324 return;
4325
4326 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4327 }
4328
4329 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4330 struct net_device *netdev,
4331 const struct mlx5e_profile *profile,
4332 void *ppriv)
4333 {
4334 struct mlx5e_priv *priv = netdev_priv(netdev);
4335 int err;
4336
4337 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4338 err = mlx5e_ipsec_init(priv);
4339 if (err)
4340 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4341 mlx5e_build_nic_netdev(netdev);
4342 mlx5e_vxlan_init(priv);
4343 }
4344
4345 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4346 {
4347 mlx5e_ipsec_cleanup(priv);
4348 mlx5e_vxlan_cleanup(priv);
4349
4350 if (priv->channels.params.xdp_prog)
4351 bpf_prog_put(priv->channels.params.xdp_prog);
4352 }
4353
4354 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4355 {
4356 struct mlx5_core_dev *mdev = priv->mdev;
4357 int err;
4358
4359 err = mlx5e_create_indirect_rqt(priv);
4360 if (err)
4361 return err;
4362
4363 err = mlx5e_create_direct_rqts(priv);
4364 if (err)
4365 goto err_destroy_indirect_rqts;
4366
4367 err = mlx5e_create_indirect_tirs(priv);
4368 if (err)
4369 goto err_destroy_direct_rqts;
4370
4371 err = mlx5e_create_direct_tirs(priv);
4372 if (err)
4373 goto err_destroy_indirect_tirs;
4374
4375 err = mlx5e_create_flow_steering(priv);
4376 if (err) {
4377 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4378 goto err_destroy_direct_tirs;
4379 }
4380
4381 err = mlx5e_tc_init(priv);
4382 if (err)
4383 goto err_destroy_flow_steering;
4384
4385 return 0;
4386
4387 err_destroy_flow_steering:
4388 mlx5e_destroy_flow_steering(priv);
4389 err_destroy_direct_tirs:
4390 mlx5e_destroy_direct_tirs(priv);
4391 err_destroy_indirect_tirs:
4392 mlx5e_destroy_indirect_tirs(priv);
4393 err_destroy_direct_rqts:
4394 mlx5e_destroy_direct_rqts(priv);
4395 err_destroy_indirect_rqts:
4396 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4397 return err;
4398 }
4399
4400 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4401 {
4402 mlx5e_tc_cleanup(priv);
4403 mlx5e_destroy_flow_steering(priv);
4404 mlx5e_destroy_direct_tirs(priv);
4405 mlx5e_destroy_indirect_tirs(priv);
4406 mlx5e_destroy_direct_rqts(priv);
4407 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4408 }
4409
4410 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4411 {
4412 int err;
4413
4414 err = mlx5e_create_tises(priv);
4415 if (err) {
4416 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4417 return err;
4418 }
4419
4420 #ifdef CONFIG_MLX5_CORE_EN_DCB
4421 mlx5e_dcbnl_initialize(priv);
4422 #endif
4423 return 0;
4424 }
4425
4426 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4427 {
4428 struct net_device *netdev = priv->netdev;
4429 struct mlx5_core_dev *mdev = priv->mdev;
4430 u16 max_mtu;
4431
4432 mlx5e_init_l2_addr(priv);
4433
4434 /* Marking the link as currently not needed by the Driver */
4435 if (!netif_running(netdev))
4436 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4437
4438 /* MTU range: 68 - hw-specific max */
4439 netdev->min_mtu = ETH_MIN_MTU;
4440 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4441 netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
4442 mlx5e_set_dev_port_mtu(priv);
4443
4444 mlx5_lag_add(mdev, netdev);
4445
4446 mlx5e_enable_async_events(priv);
4447
4448 if (MLX5_ESWITCH_MANAGER(priv->mdev))
4449 mlx5e_register_vport_reps(priv);
4450
4451 if (netdev->reg_state != NETREG_REGISTERED)
4452 return;
4453 #ifdef CONFIG_MLX5_CORE_EN_DCB
4454 mlx5e_dcbnl_init_app(priv);
4455 #endif
4456
4457 queue_work(priv->wq, &priv->set_rx_mode_work);
4458
4459 rtnl_lock();
4460 if (netif_running(netdev))
4461 mlx5e_open(netdev);
4462 netif_device_attach(netdev);
4463 rtnl_unlock();
4464 }
4465
4466 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4467 {
4468 struct mlx5_core_dev *mdev = priv->mdev;
4469
4470 #ifdef CONFIG_MLX5_CORE_EN_DCB
4471 if (priv->netdev->reg_state == NETREG_REGISTERED)
4472 mlx5e_dcbnl_delete_app(priv);
4473 #endif
4474
4475 rtnl_lock();
4476 if (netif_running(priv->netdev))
4477 mlx5e_close(priv->netdev);
4478 netif_device_detach(priv->netdev);
4479 rtnl_unlock();
4480
4481 queue_work(priv->wq, &priv->set_rx_mode_work);
4482
4483 if (MLX5_ESWITCH_MANAGER(priv->mdev))
4484 mlx5e_unregister_vport_reps(priv);
4485
4486 mlx5e_disable_async_events(priv);
4487 mlx5_lag_remove(mdev);
4488 }
4489
4490 static const struct mlx5e_profile mlx5e_nic_profile = {
4491 .init = mlx5e_nic_init,
4492 .cleanup = mlx5e_nic_cleanup,
4493 .init_rx = mlx5e_init_nic_rx,
4494 .cleanup_rx = mlx5e_cleanup_nic_rx,
4495 .init_tx = mlx5e_init_nic_tx,
4496 .cleanup_tx = mlx5e_cleanup_nic_tx,
4497 .enable = mlx5e_nic_enable,
4498 .disable = mlx5e_nic_disable,
4499 .update_stats = mlx5e_update_ndo_stats,
4500 .max_nch = mlx5e_get_max_num_channels,
4501 .update_carrier = mlx5e_update_carrier,
4502 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4503 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4504 .max_tc = MLX5E_MAX_NUM_TC,
4505 };
4506
4507 /* mlx5e generic netdev management API (move to en_common.c) */
4508
4509 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4510 const struct mlx5e_profile *profile,
4511 void *ppriv)
4512 {
4513 int nch = profile->max_nch(mdev);
4514 struct net_device *netdev;
4515 struct mlx5e_priv *priv;
4516
4517 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4518 nch * profile->max_tc,
4519 nch);
4520 if (!netdev) {
4521 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4522 return NULL;
4523 }
4524
4525 #ifdef CONFIG_RFS_ACCEL
4526 netdev->rx_cpu_rmap = mdev->rmap;
4527 #endif
4528
4529 profile->init(mdev, netdev, profile, ppriv);
4530
4531 netif_carrier_off(netdev);
4532
4533 priv = netdev_priv(netdev);
4534
4535 priv->wq = create_singlethread_workqueue("mlx5e");
4536 if (!priv->wq)
4537 goto err_cleanup_nic;
4538
4539 return netdev;
4540
4541 err_cleanup_nic:
4542 if (profile->cleanup)
4543 profile->cleanup(priv);
4544 free_netdev(netdev);
4545
4546 return NULL;
4547 }
4548
4549 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4550 {
4551 struct mlx5_core_dev *mdev = priv->mdev;
4552 const struct mlx5e_profile *profile;
4553 int max_nch;
4554 int err;
4555
4556 profile = priv->profile;
4557 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4558
4559 /* max number of channels may have changed */
4560 max_nch = mlx5e_get_max_num_channels(priv->mdev);
4561 if (priv->channels.params.num_channels > max_nch) {
4562 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
4563 priv->channels.params.num_channels = max_nch;
4564 mlx5e_build_default_indir_rqt(priv->channels.params.indirection_rqt,
4565 MLX5E_INDIR_RQT_SIZE, max_nch);
4566 }
4567
4568 err = profile->init_tx(priv);
4569 if (err)
4570 goto out;
4571
4572 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
4573 if (err) {
4574 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4575 goto err_cleanup_tx;
4576 }
4577
4578 err = profile->init_rx(priv);
4579 if (err)
4580 goto err_close_drop_rq;
4581
4582 mlx5e_create_q_counter(priv);
4583
4584 if (profile->enable)
4585 profile->enable(priv);
4586
4587 return 0;
4588
4589 err_close_drop_rq:
4590 mlx5e_close_drop_rq(&priv->drop_rq);
4591
4592 err_cleanup_tx:
4593 profile->cleanup_tx(priv);
4594
4595 out:
4596 return err;
4597 }
4598
4599 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4600 {
4601 const struct mlx5e_profile *profile = priv->profile;
4602
4603 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4604
4605 if (profile->disable)
4606 profile->disable(priv);
4607 flush_workqueue(priv->wq);
4608
4609 mlx5e_destroy_q_counter(priv);
4610 profile->cleanup_rx(priv);
4611 mlx5e_close_drop_rq(&priv->drop_rq);
4612 profile->cleanup_tx(priv);
4613 cancel_delayed_work_sync(&priv->update_stats_work);
4614 }
4615
4616 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4617 {
4618 const struct mlx5e_profile *profile = priv->profile;
4619 struct net_device *netdev = priv->netdev;
4620
4621 destroy_workqueue(priv->wq);
4622 if (profile->cleanup)
4623 profile->cleanup(priv);
4624 free_netdev(netdev);
4625 }
4626
4627 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4628 * hardware contexts and to connect it to the current netdev.
4629 */
4630 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4631 {
4632 struct mlx5e_priv *priv = vpriv;
4633 struct net_device *netdev = priv->netdev;
4634 int err;
4635
4636 if (netif_device_present(netdev))
4637 return 0;
4638
4639 err = mlx5e_create_mdev_resources(mdev);
4640 if (err)
4641 return err;
4642
4643 err = mlx5e_attach_netdev(priv);
4644 if (err) {
4645 mlx5e_destroy_mdev_resources(mdev);
4646 return err;
4647 }
4648
4649 return 0;
4650 }
4651
4652 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4653 {
4654 struct mlx5e_priv *priv = vpriv;
4655 struct net_device *netdev = priv->netdev;
4656
4657 if (!netif_device_present(netdev))
4658 return;
4659
4660 mlx5e_detach_netdev(priv);
4661 mlx5e_destroy_mdev_resources(mdev);
4662 }
4663
4664 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4665 {
4666 struct net_device *netdev;
4667 void *rpriv = NULL;
4668 void *priv;
4669 int err;
4670
4671 err = mlx5e_check_required_hca_cap(mdev);
4672 if (err)
4673 return NULL;
4674
4675 #ifdef CONFIG_MLX5_ESWITCH
4676 if (MLX5_ESWITCH_MANAGER(mdev)) {
4677 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4678 if (!rpriv) {
4679 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4680 return NULL;
4681 }
4682 }
4683 #endif
4684
4685 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4686 if (!netdev) {
4687 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4688 goto err_free_rpriv;
4689 }
4690
4691 priv = netdev_priv(netdev);
4692
4693 err = mlx5e_attach(mdev, priv);
4694 if (err) {
4695 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4696 goto err_destroy_netdev;
4697 }
4698
4699 err = register_netdev(netdev);
4700 if (err) {
4701 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4702 goto err_detach;
4703 }
4704
4705 #ifdef CONFIG_MLX5_CORE_EN_DCB
4706 mlx5e_dcbnl_init_app(priv);
4707 #endif
4708 return priv;
4709
4710 err_detach:
4711 mlx5e_detach(mdev, priv);
4712 err_destroy_netdev:
4713 mlx5e_destroy_netdev(priv);
4714 err_free_rpriv:
4715 kfree(rpriv);
4716 return NULL;
4717 }
4718
4719 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4720 {
4721 struct mlx5e_priv *priv = vpriv;
4722 void *ppriv = priv->ppriv;
4723
4724 #ifdef CONFIG_MLX5_CORE_EN_DCB
4725 mlx5e_dcbnl_delete_app(priv);
4726 #endif
4727 unregister_netdev(priv->netdev);
4728 mlx5e_detach(mdev, vpriv);
4729 mlx5e_destroy_netdev(priv);
4730 kfree(ppriv);
4731 }
4732
4733 static void *mlx5e_get_netdev(void *vpriv)
4734 {
4735 struct mlx5e_priv *priv = vpriv;
4736
4737 return priv->netdev;
4738 }
4739
4740 static struct mlx5_interface mlx5e_interface = {
4741 .add = mlx5e_add,
4742 .remove = mlx5e_remove,
4743 .attach = mlx5e_attach,
4744 .detach = mlx5e_detach,
4745 .event = mlx5e_async_event,
4746 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4747 .get_dev = mlx5e_get_netdev,
4748 };
4749
4750 void mlx5e_init(void)
4751 {
4752 mlx5e_ipsec_build_inverse_table();
4753 mlx5e_build_ptys2ethtool_map();
4754 mlx5_register_interface(&mlx5e_interface);
4755 }
4756
4757 void mlx5e_cleanup(void)
4758 {
4759 mlx5_unregister_interface(&mlx5e_interface);
4760 }
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