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net/mlx5e: Rearrange netdevice ops structures
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include "eswitch.h"
39 #include "en.h"
40 #include "en_tc.h"
41 #include "en_rep.h"
42 #include "en_accel/ipsec.h"
43 #include "en_accel/ipsec_rxtx.h"
44 #include "accel/ipsec.h"
45 #include "vxlan.h"
46
47 struct mlx5e_rq_param {
48 u32 rqc[MLX5_ST_SZ_DW(rqc)];
49 struct mlx5_wq_param wq;
50 };
51
52 struct mlx5e_sq_param {
53 u32 sqc[MLX5_ST_SZ_DW(sqc)];
54 struct mlx5_wq_param wq;
55 };
56
57 struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
61 u8 cq_period_mode;
62 };
63
64 struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
67 struct mlx5e_sq_param xdp_sq;
68 struct mlx5e_sq_param icosq;
69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
71 struct mlx5e_cq_param icosq_cq;
72 };
73
74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75 {
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79 }
80
81 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
82 struct mlx5e_params *params, u8 rq_type)
83 {
84 params->rq_wq_type = rq_type;
85 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
86 switch (params->rq_wq_type) {
87 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
88 params->log_rq_size = is_kdump_kernel() ?
89 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
90 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
91 params->mpwqe_log_stride_sz =
92 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
93 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
94 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
95 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
96 params->mpwqe_log_stride_sz;
97 break;
98 default: /* MLX5_WQ_TYPE_LINKED_LIST */
99 params->log_rq_size = is_kdump_kernel() ?
100 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
101 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
102 params->rq_headroom = params->xdp_prog ?
103 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
104 params->rq_headroom += NET_IP_ALIGN;
105
106 /* Extra room needed for build_skb */
107 params->lro_wqe_sz -= params->rq_headroom +
108 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
109 }
110
111 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
112 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
113 BIT(params->log_rq_size),
114 BIT(params->mpwqe_log_stride_sz),
115 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
116 }
117
118 static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
119 {
120 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
121 !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
122 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
123 MLX5_WQ_TYPE_LINKED_LIST;
124 mlx5e_set_rq_type_params(mdev, params, rq_type);
125 }
126
127 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
128 {
129 struct mlx5_core_dev *mdev = priv->mdev;
130 u8 port_state;
131
132 port_state = mlx5_query_vport_state(mdev,
133 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
134 0);
135
136 if (port_state == VPORT_STATE_UP) {
137 netdev_info(priv->netdev, "Link up\n");
138 netif_carrier_on(priv->netdev);
139 } else {
140 netdev_info(priv->netdev, "Link down\n");
141 netif_carrier_off(priv->netdev);
142 }
143 }
144
145 static void mlx5e_update_carrier_work(struct work_struct *work)
146 {
147 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
148 update_carrier_work);
149
150 mutex_lock(&priv->state_lock);
151 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
152 if (priv->profile->update_carrier)
153 priv->profile->update_carrier(priv);
154 mutex_unlock(&priv->state_lock);
155 }
156
157 static void mlx5e_tx_timeout_work(struct work_struct *work)
158 {
159 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
160 tx_timeout_work);
161 int err;
162
163 rtnl_lock();
164 mutex_lock(&priv->state_lock);
165 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
166 goto unlock;
167 mlx5e_close_locked(priv->netdev);
168 err = mlx5e_open_locked(priv->netdev);
169 if (err)
170 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
171 err);
172 unlock:
173 mutex_unlock(&priv->state_lock);
174 rtnl_unlock();
175 }
176
177 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
178 {
179 struct mlx5e_sw_stats temp, *s = &temp;
180 struct mlx5e_rq_stats *rq_stats;
181 struct mlx5e_sq_stats *sq_stats;
182 u64 tx_offload_none = 0;
183 int i, j;
184
185 memset(s, 0, sizeof(*s));
186 for (i = 0; i < priv->channels.num; i++) {
187 struct mlx5e_channel *c = priv->channels.c[i];
188
189 rq_stats = &c->rq.stats;
190
191 s->rx_packets += rq_stats->packets;
192 s->rx_bytes += rq_stats->bytes;
193 s->rx_lro_packets += rq_stats->lro_packets;
194 s->rx_lro_bytes += rq_stats->lro_bytes;
195 s->rx_csum_none += rq_stats->csum_none;
196 s->rx_csum_complete += rq_stats->csum_complete;
197 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
198 s->rx_xdp_drop += rq_stats->xdp_drop;
199 s->rx_xdp_tx += rq_stats->xdp_tx;
200 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
201 s->rx_wqe_err += rq_stats->wqe_err;
202 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
203 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
204 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
205 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
206 s->rx_page_reuse += rq_stats->page_reuse;
207 s->rx_cache_reuse += rq_stats->cache_reuse;
208 s->rx_cache_full += rq_stats->cache_full;
209 s->rx_cache_empty += rq_stats->cache_empty;
210 s->rx_cache_busy += rq_stats->cache_busy;
211
212 for (j = 0; j < priv->channels.params.num_tc; j++) {
213 sq_stats = &c->sq[j].stats;
214
215 s->tx_packets += sq_stats->packets;
216 s->tx_bytes += sq_stats->bytes;
217 s->tx_tso_packets += sq_stats->tso_packets;
218 s->tx_tso_bytes += sq_stats->tso_bytes;
219 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
220 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
221 s->tx_queue_stopped += sq_stats->stopped;
222 s->tx_queue_wake += sq_stats->wake;
223 s->tx_queue_dropped += sq_stats->dropped;
224 s->tx_xmit_more += sq_stats->xmit_more;
225 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
226 tx_offload_none += sq_stats->csum_none;
227 }
228 }
229
230 /* Update calculated offload counters */
231 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
232 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
233
234 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
235 priv->stats.pport.phy_counters,
236 counter_set.phys_layer_cntrs.link_down_events);
237 memcpy(&priv->stats.sw, s, sizeof(*s));
238 }
239
240 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
241 {
242 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
243 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
244 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
245 struct mlx5_core_dev *mdev = priv->mdev;
246
247 MLX5_SET(query_vport_counter_in, in, opcode,
248 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
249 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
250 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
251
252 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
253 }
254
255 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
256 {
257 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
258 struct mlx5_core_dev *mdev = priv->mdev;
259 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
260 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
261 int prio;
262 void *out;
263
264 MLX5_SET(ppcnt_reg, in, local_port, 1);
265
266 out = pstats->IEEE_802_3_counters;
267 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
268 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
269
270 if (!full)
271 return;
272
273 out = pstats->RFC_2863_counters;
274 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
275 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
276
277 out = pstats->RFC_2819_counters;
278 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
279 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
280
281 out = pstats->phy_counters;
282 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
283 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
284
285 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
286 out = pstats->phy_statistical_counters;
287 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
288 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
289 }
290
291 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
292 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
293 out = pstats->per_prio_counters[prio];
294 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
295 mlx5_core_access_reg(mdev, in, sz, out, sz,
296 MLX5_REG_PPCNT, 0, 0);
297 }
298 }
299
300 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
301 {
302 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
303 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
304 int err;
305
306 if (!priv->q_counter)
307 return;
308
309 err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
310 if (err)
311 return;
312
313 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
314 }
315
316 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
317 {
318 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
319 struct mlx5_core_dev *mdev = priv->mdev;
320 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
321 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
322 void *out;
323
324 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
325 return;
326
327 out = pcie_stats->pcie_perf_counters;
328 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
329 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
330 }
331
332 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
333 {
334 if (full) {
335 mlx5e_update_pcie_counters(priv);
336 mlx5e_ipsec_update_stats(priv);
337 }
338 mlx5e_update_pport_counters(priv, full);
339 mlx5e_update_vport_counters(priv);
340 mlx5e_update_q_counter(priv);
341 mlx5e_update_sw_counters(priv);
342 }
343
344 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
345 {
346 mlx5e_update_stats(priv, false);
347 }
348
349 void mlx5e_update_stats_work(struct work_struct *work)
350 {
351 struct delayed_work *dwork = to_delayed_work(work);
352 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
353 update_stats_work);
354 mutex_lock(&priv->state_lock);
355 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
356 priv->profile->update_stats(priv);
357 queue_delayed_work(priv->wq, dwork,
358 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
359 }
360 mutex_unlock(&priv->state_lock);
361 }
362
363 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
364 enum mlx5_dev_event event, unsigned long param)
365 {
366 struct mlx5e_priv *priv = vpriv;
367 struct ptp_clock_event ptp_event;
368 struct mlx5_eqe *eqe = NULL;
369
370 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
371 return;
372
373 switch (event) {
374 case MLX5_DEV_EVENT_PORT_UP:
375 case MLX5_DEV_EVENT_PORT_DOWN:
376 queue_work(priv->wq, &priv->update_carrier_work);
377 break;
378 case MLX5_DEV_EVENT_PPS:
379 eqe = (struct mlx5_eqe *)param;
380 ptp_event.index = eqe->data.pps.pin;
381 ptp_event.timestamp =
382 timecounter_cyc2time(&priv->tstamp.clock,
383 be64_to_cpu(eqe->data.pps.time_stamp));
384 mlx5e_pps_event_handler(vpriv, &ptp_event);
385 break;
386 default:
387 break;
388 }
389 }
390
391 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
392 {
393 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
394 }
395
396 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
397 {
398 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
399 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
400 }
401
402 static inline int mlx5e_get_wqe_mtt_sz(void)
403 {
404 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
405 * To avoid copying garbage after the mtt array, we allocate
406 * a little more.
407 */
408 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
409 MLX5_UMR_MTT_ALIGNMENT);
410 }
411
412 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
413 struct mlx5e_icosq *sq,
414 struct mlx5e_umr_wqe *wqe,
415 u16 ix)
416 {
417 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
418 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
419 struct mlx5_wqe_data_seg *dseg = &wqe->data;
420 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
421 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
422 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
423
424 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
425 ds_cnt);
426 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
427 cseg->imm = rq->mkey_be;
428
429 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
430 ucseg->xlt_octowords =
431 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
432 ucseg->bsf_octowords =
433 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
434 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
435
436 dseg->lkey = sq->mkey_be;
437 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
438 }
439
440 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
441 struct mlx5e_channel *c)
442 {
443 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
444 int mtt_sz = mlx5e_get_wqe_mtt_sz();
445 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
446 int i;
447
448 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
449 GFP_KERNEL, cpu_to_node(c->cpu));
450 if (!rq->mpwqe.info)
451 goto err_out;
452
453 /* We allocate more than mtt_sz as we will align the pointer */
454 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
455 cpu_to_node(c->cpu));
456 if (unlikely(!rq->mpwqe.mtt_no_align))
457 goto err_free_wqe_info;
458
459 for (i = 0; i < wq_sz; i++) {
460 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
461
462 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
463 MLX5_UMR_ALIGN);
464 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
465 PCI_DMA_TODEVICE);
466 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
467 goto err_unmap_mtts;
468
469 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
470 }
471
472 return 0;
473
474 err_unmap_mtts:
475 while (--i >= 0) {
476 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
477
478 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
479 PCI_DMA_TODEVICE);
480 }
481 kfree(rq->mpwqe.mtt_no_align);
482 err_free_wqe_info:
483 kfree(rq->mpwqe.info);
484
485 err_out:
486 return -ENOMEM;
487 }
488
489 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
490 {
491 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
492 int mtt_sz = mlx5e_get_wqe_mtt_sz();
493 int i;
494
495 for (i = 0; i < wq_sz; i++) {
496 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
497
498 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
499 PCI_DMA_TODEVICE);
500 }
501 kfree(rq->mpwqe.mtt_no_align);
502 kfree(rq->mpwqe.info);
503 }
504
505 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
506 u64 npages, u8 page_shift,
507 struct mlx5_core_mkey *umr_mkey)
508 {
509 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
510 void *mkc;
511 u32 *in;
512 int err;
513
514 if (!MLX5E_VALID_NUM_MTTS(npages))
515 return -EINVAL;
516
517 in = kvzalloc(inlen, GFP_KERNEL);
518 if (!in)
519 return -ENOMEM;
520
521 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
522
523 MLX5_SET(mkc, mkc, free, 1);
524 MLX5_SET(mkc, mkc, umr_en, 1);
525 MLX5_SET(mkc, mkc, lw, 1);
526 MLX5_SET(mkc, mkc, lr, 1);
527 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
528
529 MLX5_SET(mkc, mkc, qpn, 0xffffff);
530 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
531 MLX5_SET64(mkc, mkc, len, npages << page_shift);
532 MLX5_SET(mkc, mkc, translations_octword_size,
533 MLX5_MTT_OCTW(npages));
534 MLX5_SET(mkc, mkc, log_page_size, page_shift);
535
536 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
537
538 kvfree(in);
539 return err;
540 }
541
542 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
543 {
544 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
545
546 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
547 }
548
549 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
550 struct mlx5e_params *params,
551 struct mlx5e_rq_param *rqp,
552 struct mlx5e_rq *rq)
553 {
554 struct mlx5_core_dev *mdev = c->mdev;
555 void *rqc = rqp->rqc;
556 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
557 u32 byte_count;
558 int npages;
559 int wq_sz;
560 int err;
561 int i;
562
563 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
564
565 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
566 &rq->wq_ctrl);
567 if (err)
568 return err;
569
570 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
571
572 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
573
574 rq->wq_type = params->rq_wq_type;
575 rq->pdev = c->pdev;
576 rq->netdev = c->netdev;
577 rq->tstamp = c->tstamp;
578 rq->channel = c;
579 rq->ix = c->ix;
580 rq->mdev = mdev;
581
582 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
583 if (IS_ERR(rq->xdp_prog)) {
584 err = PTR_ERR(rq->xdp_prog);
585 rq->xdp_prog = NULL;
586 goto err_rq_wq_destroy;
587 }
588
589 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
590 rq->rx_headroom = params->rq_headroom;
591
592 switch (rq->wq_type) {
593 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
594
595 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
596 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
597
598 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
599 #ifdef CONFIG_MLX5_EN_IPSEC
600 if (MLX5_IPSEC_DEV(mdev)) {
601 err = -EINVAL;
602 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
603 goto err_rq_wq_destroy;
604 }
605 #endif
606 if (!rq->handle_rx_cqe) {
607 err = -EINVAL;
608 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
609 goto err_rq_wq_destroy;
610 }
611
612 rq->mpwqe_stride_sz = BIT(params->mpwqe_log_stride_sz);
613 rq->mpwqe_num_strides = BIT(params->mpwqe_log_num_strides);
614
615 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
616 byte_count = rq->buff.wqe_sz;
617
618 err = mlx5e_create_rq_umr_mkey(mdev, rq);
619 if (err)
620 goto err_rq_wq_destroy;
621 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
622
623 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
624 if (err)
625 goto err_destroy_umr_mkey;
626 break;
627 default: /* MLX5_WQ_TYPE_LINKED_LIST */
628 rq->wqe.frag_info =
629 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
630 GFP_KERNEL, cpu_to_node(c->cpu));
631 if (!rq->wqe.frag_info) {
632 err = -ENOMEM;
633 goto err_rq_wq_destroy;
634 }
635 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
636 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
637
638 #ifdef CONFIG_MLX5_EN_IPSEC
639 if (c->priv->ipsec)
640 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
641 else
642 #endif
643 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
644 if (!rq->handle_rx_cqe) {
645 kfree(rq->wqe.frag_info);
646 err = -EINVAL;
647 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
648 goto err_rq_wq_destroy;
649 }
650
651 rq->buff.wqe_sz = params->lro_en ?
652 params->lro_wqe_sz :
653 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
654 #ifdef CONFIG_MLX5_EN_IPSEC
655 if (MLX5_IPSEC_DEV(mdev))
656 rq->buff.wqe_sz += MLX5E_METADATA_ETHER_LEN;
657 #endif
658 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
659 byte_count = rq->buff.wqe_sz;
660
661 /* calc the required page order */
662 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->rx_headroom + byte_count);
663 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
664 rq->buff.page_order = order_base_2(npages);
665
666 byte_count |= MLX5_HW_START_PADDING;
667 rq->mkey_be = c->mkey_be;
668 }
669
670 for (i = 0; i < wq_sz; i++) {
671 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
672
673 wqe->data.byte_count = cpu_to_be32(byte_count);
674 wqe->data.lkey = rq->mkey_be;
675 }
676
677 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
678 rq->am.mode = params->rx_cq_period_mode;
679 rq->page_cache.head = 0;
680 rq->page_cache.tail = 0;
681
682 return 0;
683
684 err_destroy_umr_mkey:
685 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
686
687 err_rq_wq_destroy:
688 if (rq->xdp_prog)
689 bpf_prog_put(rq->xdp_prog);
690 mlx5_wq_destroy(&rq->wq_ctrl);
691
692 return err;
693 }
694
695 static void mlx5e_free_rq(struct mlx5e_rq *rq)
696 {
697 int i;
698
699 if (rq->xdp_prog)
700 bpf_prog_put(rq->xdp_prog);
701
702 switch (rq->wq_type) {
703 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
704 mlx5e_rq_free_mpwqe_info(rq);
705 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
706 break;
707 default: /* MLX5_WQ_TYPE_LINKED_LIST */
708 kfree(rq->wqe.frag_info);
709 }
710
711 for (i = rq->page_cache.head; i != rq->page_cache.tail;
712 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
713 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
714
715 mlx5e_page_release(rq, dma_info, false);
716 }
717 mlx5_wq_destroy(&rq->wq_ctrl);
718 }
719
720 static int mlx5e_create_rq(struct mlx5e_rq *rq,
721 struct mlx5e_rq_param *param)
722 {
723 struct mlx5_core_dev *mdev = rq->mdev;
724
725 void *in;
726 void *rqc;
727 void *wq;
728 int inlen;
729 int err;
730
731 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
732 sizeof(u64) * rq->wq_ctrl.buf.npages;
733 in = kvzalloc(inlen, GFP_KERNEL);
734 if (!in)
735 return -ENOMEM;
736
737 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
738 wq = MLX5_ADDR_OF(rqc, rqc, wq);
739
740 memcpy(rqc, param->rqc, sizeof(param->rqc));
741
742 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
743 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
744 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
745 MLX5_ADAPTER_PAGE_SHIFT);
746 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
747
748 mlx5_fill_page_array(&rq->wq_ctrl.buf,
749 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
750
751 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
752
753 kvfree(in);
754
755 return err;
756 }
757
758 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
759 int next_state)
760 {
761 struct mlx5e_channel *c = rq->channel;
762 struct mlx5_core_dev *mdev = c->mdev;
763
764 void *in;
765 void *rqc;
766 int inlen;
767 int err;
768
769 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
770 in = kvzalloc(inlen, GFP_KERNEL);
771 if (!in)
772 return -ENOMEM;
773
774 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
775
776 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
777 MLX5_SET(rqc, rqc, state, next_state);
778
779 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
780
781 kvfree(in);
782
783 return err;
784 }
785
786 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
787 {
788 struct mlx5e_channel *c = rq->channel;
789 struct mlx5e_priv *priv = c->priv;
790 struct mlx5_core_dev *mdev = priv->mdev;
791
792 void *in;
793 void *rqc;
794 int inlen;
795 int err;
796
797 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
798 in = kvzalloc(inlen, GFP_KERNEL);
799 if (!in)
800 return -ENOMEM;
801
802 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
803
804 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
805 MLX5_SET64(modify_rq_in, in, modify_bitmask,
806 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
807 MLX5_SET(rqc, rqc, scatter_fcs, enable);
808 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
809
810 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
811
812 kvfree(in);
813
814 return err;
815 }
816
817 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
818 {
819 struct mlx5e_channel *c = rq->channel;
820 struct mlx5_core_dev *mdev = c->mdev;
821 void *in;
822 void *rqc;
823 int inlen;
824 int err;
825
826 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
827 in = kvzalloc(inlen, GFP_KERNEL);
828 if (!in)
829 return -ENOMEM;
830
831 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
832
833 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
834 MLX5_SET64(modify_rq_in, in, modify_bitmask,
835 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
836 MLX5_SET(rqc, rqc, vsd, vsd);
837 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
838
839 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
840
841 kvfree(in);
842
843 return err;
844 }
845
846 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
847 {
848 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
849 }
850
851 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
852 {
853 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
854 struct mlx5e_channel *c = rq->channel;
855
856 struct mlx5_wq_ll *wq = &rq->wq;
857 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
858
859 while (time_before(jiffies, exp_time)) {
860 if (wq->cur_sz >= min_wqes)
861 return 0;
862
863 msleep(20);
864 }
865
866 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
867 rq->rqn, wq->cur_sz, min_wqes);
868 return -ETIMEDOUT;
869 }
870
871 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
872 {
873 struct mlx5_wq_ll *wq = &rq->wq;
874 struct mlx5e_rx_wqe *wqe;
875 __be16 wqe_ix_be;
876 u16 wqe_ix;
877
878 /* UMR WQE (if in progress) is always at wq->head */
879 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
880 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
881
882 while (!mlx5_wq_ll_is_empty(wq)) {
883 wqe_ix_be = *wq->tail_next;
884 wqe_ix = be16_to_cpu(wqe_ix_be);
885 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
886 rq->dealloc_wqe(rq, wqe_ix);
887 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
888 &wqe->next.next_wqe_index);
889 }
890
891 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
892 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
893 * but yet to be re-posted.
894 */
895 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
896
897 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
898 rq->dealloc_wqe(rq, wqe_ix);
899 }
900 }
901
902 static int mlx5e_open_rq(struct mlx5e_channel *c,
903 struct mlx5e_params *params,
904 struct mlx5e_rq_param *param,
905 struct mlx5e_rq *rq)
906 {
907 int err;
908
909 err = mlx5e_alloc_rq(c, params, param, rq);
910 if (err)
911 return err;
912
913 err = mlx5e_create_rq(rq, param);
914 if (err)
915 goto err_free_rq;
916
917 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
918 if (err)
919 goto err_destroy_rq;
920
921 if (params->rx_am_enabled)
922 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
923
924 return 0;
925
926 err_destroy_rq:
927 mlx5e_destroy_rq(rq);
928 err_free_rq:
929 mlx5e_free_rq(rq);
930
931 return err;
932 }
933
934 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
935 {
936 struct mlx5e_icosq *sq = &rq->channel->icosq;
937 u16 pi = sq->pc & sq->wq.sz_m1;
938 struct mlx5e_tx_wqe *nopwqe;
939
940 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
941 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
942 sq->db.ico_wqe[pi].num_wqebbs = 1;
943 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
944 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
945 }
946
947 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
948 {
949 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
950 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
951 }
952
953 static void mlx5e_close_rq(struct mlx5e_rq *rq)
954 {
955 cancel_work_sync(&rq->am.work);
956 mlx5e_destroy_rq(rq);
957 mlx5e_free_rx_descs(rq);
958 mlx5e_free_rq(rq);
959 }
960
961 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
962 {
963 kfree(sq->db.di);
964 }
965
966 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
967 {
968 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
969
970 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
971 GFP_KERNEL, numa);
972 if (!sq->db.di) {
973 mlx5e_free_xdpsq_db(sq);
974 return -ENOMEM;
975 }
976
977 return 0;
978 }
979
980 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
981 struct mlx5e_params *params,
982 struct mlx5e_sq_param *param,
983 struct mlx5e_xdpsq *sq)
984 {
985 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
986 struct mlx5_core_dev *mdev = c->mdev;
987 int err;
988
989 sq->pdev = c->pdev;
990 sq->mkey_be = c->mkey_be;
991 sq->channel = c;
992 sq->uar_map = mdev->mlx5e_res.bfreg.map;
993 sq->min_inline_mode = params->tx_min_inline_mode;
994
995 param->wq.db_numa_node = cpu_to_node(c->cpu);
996 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
997 if (err)
998 return err;
999 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1000
1001 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1002 if (err)
1003 goto err_sq_wq_destroy;
1004
1005 return 0;
1006
1007 err_sq_wq_destroy:
1008 mlx5_wq_destroy(&sq->wq_ctrl);
1009
1010 return err;
1011 }
1012
1013 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1014 {
1015 mlx5e_free_xdpsq_db(sq);
1016 mlx5_wq_destroy(&sq->wq_ctrl);
1017 }
1018
1019 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1020 {
1021 kfree(sq->db.ico_wqe);
1022 }
1023
1024 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1025 {
1026 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1027
1028 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1029 GFP_KERNEL, numa);
1030 if (!sq->db.ico_wqe)
1031 return -ENOMEM;
1032
1033 return 0;
1034 }
1035
1036 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1037 struct mlx5e_sq_param *param,
1038 struct mlx5e_icosq *sq)
1039 {
1040 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1041 struct mlx5_core_dev *mdev = c->mdev;
1042 int err;
1043
1044 sq->pdev = c->pdev;
1045 sq->mkey_be = c->mkey_be;
1046 sq->channel = c;
1047 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1048
1049 param->wq.db_numa_node = cpu_to_node(c->cpu);
1050 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1051 if (err)
1052 return err;
1053 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1054
1055 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1056 if (err)
1057 goto err_sq_wq_destroy;
1058
1059 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
1060
1061 return 0;
1062
1063 err_sq_wq_destroy:
1064 mlx5_wq_destroy(&sq->wq_ctrl);
1065
1066 return err;
1067 }
1068
1069 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1070 {
1071 mlx5e_free_icosq_db(sq);
1072 mlx5_wq_destroy(&sq->wq_ctrl);
1073 }
1074
1075 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1076 {
1077 kfree(sq->db.wqe_info);
1078 kfree(sq->db.dma_fifo);
1079 }
1080
1081 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1082 {
1083 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1084 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1085
1086 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1087 GFP_KERNEL, numa);
1088 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1089 GFP_KERNEL, numa);
1090 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1091 mlx5e_free_txqsq_db(sq);
1092 return -ENOMEM;
1093 }
1094
1095 sq->dma_fifo_mask = df_sz - 1;
1096
1097 return 0;
1098 }
1099
1100 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1101 int txq_ix,
1102 struct mlx5e_params *params,
1103 struct mlx5e_sq_param *param,
1104 struct mlx5e_txqsq *sq)
1105 {
1106 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1107 struct mlx5_core_dev *mdev = c->mdev;
1108 int err;
1109
1110 sq->pdev = c->pdev;
1111 sq->tstamp = c->tstamp;
1112 sq->mkey_be = c->mkey_be;
1113 sq->channel = c;
1114 sq->txq_ix = txq_ix;
1115 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1116 sq->max_inline = params->tx_max_inline;
1117 sq->min_inline_mode = params->tx_min_inline_mode;
1118 if (MLX5_IPSEC_DEV(c->priv->mdev))
1119 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1120
1121 param->wq.db_numa_node = cpu_to_node(c->cpu);
1122 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1123 if (err)
1124 return err;
1125 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1126
1127 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1128 if (err)
1129 goto err_sq_wq_destroy;
1130
1131 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1132
1133 return 0;
1134
1135 err_sq_wq_destroy:
1136 mlx5_wq_destroy(&sq->wq_ctrl);
1137
1138 return err;
1139 }
1140
1141 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1142 {
1143 mlx5e_free_txqsq_db(sq);
1144 mlx5_wq_destroy(&sq->wq_ctrl);
1145 }
1146
1147 struct mlx5e_create_sq_param {
1148 struct mlx5_wq_ctrl *wq_ctrl;
1149 u32 cqn;
1150 u32 tisn;
1151 u8 tis_lst_sz;
1152 u8 min_inline_mode;
1153 };
1154
1155 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1156 struct mlx5e_sq_param *param,
1157 struct mlx5e_create_sq_param *csp,
1158 u32 *sqn)
1159 {
1160 void *in;
1161 void *sqc;
1162 void *wq;
1163 int inlen;
1164 int err;
1165
1166 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1167 sizeof(u64) * csp->wq_ctrl->buf.npages;
1168 in = kvzalloc(inlen, GFP_KERNEL);
1169 if (!in)
1170 return -ENOMEM;
1171
1172 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1173 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1174
1175 memcpy(sqc, param->sqc, sizeof(param->sqc));
1176 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1177 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1178 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1179
1180 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1181 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1182
1183 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1184
1185 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1186 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1187 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1188 MLX5_ADAPTER_PAGE_SHIFT);
1189 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1190
1191 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1192
1193 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1194
1195 kvfree(in);
1196
1197 return err;
1198 }
1199
1200 struct mlx5e_modify_sq_param {
1201 int curr_state;
1202 int next_state;
1203 bool rl_update;
1204 int rl_index;
1205 };
1206
1207 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1208 struct mlx5e_modify_sq_param *p)
1209 {
1210 void *in;
1211 void *sqc;
1212 int inlen;
1213 int err;
1214
1215 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1216 in = kvzalloc(inlen, GFP_KERNEL);
1217 if (!in)
1218 return -ENOMEM;
1219
1220 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1221
1222 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1223 MLX5_SET(sqc, sqc, state, p->next_state);
1224 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1225 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1226 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1227 }
1228
1229 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1230
1231 kvfree(in);
1232
1233 return err;
1234 }
1235
1236 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1237 {
1238 mlx5_core_destroy_sq(mdev, sqn);
1239 }
1240
1241 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1242 struct mlx5e_sq_param *param,
1243 struct mlx5e_create_sq_param *csp,
1244 u32 *sqn)
1245 {
1246 struct mlx5e_modify_sq_param msp = {0};
1247 int err;
1248
1249 err = mlx5e_create_sq(mdev, param, csp, sqn);
1250 if (err)
1251 return err;
1252
1253 msp.curr_state = MLX5_SQC_STATE_RST;
1254 msp.next_state = MLX5_SQC_STATE_RDY;
1255 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1256 if (err)
1257 mlx5e_destroy_sq(mdev, *sqn);
1258
1259 return err;
1260 }
1261
1262 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1263 struct mlx5e_txqsq *sq, u32 rate);
1264
1265 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1266 u32 tisn,
1267 int txq_ix,
1268 struct mlx5e_params *params,
1269 struct mlx5e_sq_param *param,
1270 struct mlx5e_txqsq *sq)
1271 {
1272 struct mlx5e_create_sq_param csp = {};
1273 u32 tx_rate;
1274 int err;
1275
1276 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1277 if (err)
1278 return err;
1279
1280 csp.tisn = tisn;
1281 csp.tis_lst_sz = 1;
1282 csp.cqn = sq->cq.mcq.cqn;
1283 csp.wq_ctrl = &sq->wq_ctrl;
1284 csp.min_inline_mode = sq->min_inline_mode;
1285 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1286 if (err)
1287 goto err_free_txqsq;
1288
1289 tx_rate = c->priv->tx_rates[sq->txq_ix];
1290 if (tx_rate)
1291 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1292
1293 return 0;
1294
1295 err_free_txqsq:
1296 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1297 mlx5e_free_txqsq(sq);
1298
1299 return err;
1300 }
1301
1302 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1303 {
1304 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1305 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1306 netdev_tx_reset_queue(sq->txq);
1307 netif_tx_start_queue(sq->txq);
1308 }
1309
1310 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1311 {
1312 __netif_tx_lock_bh(txq);
1313 netif_tx_stop_queue(txq);
1314 __netif_tx_unlock_bh(txq);
1315 }
1316
1317 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1318 {
1319 struct mlx5e_channel *c = sq->channel;
1320
1321 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1322 /* prevent netif_tx_wake_queue */
1323 napi_synchronize(&c->napi);
1324
1325 netif_tx_disable_queue(sq->txq);
1326
1327 /* last doorbell out, godspeed .. */
1328 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1329 struct mlx5e_tx_wqe *nop;
1330
1331 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1332 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1333 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1334 }
1335 }
1336
1337 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1338 {
1339 struct mlx5e_channel *c = sq->channel;
1340 struct mlx5_core_dev *mdev = c->mdev;
1341
1342 mlx5e_destroy_sq(mdev, sq->sqn);
1343 if (sq->rate_limit)
1344 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1345 mlx5e_free_txqsq_descs(sq);
1346 mlx5e_free_txqsq(sq);
1347 }
1348
1349 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1350 struct mlx5e_params *params,
1351 struct mlx5e_sq_param *param,
1352 struct mlx5e_icosq *sq)
1353 {
1354 struct mlx5e_create_sq_param csp = {};
1355 int err;
1356
1357 err = mlx5e_alloc_icosq(c, param, sq);
1358 if (err)
1359 return err;
1360
1361 csp.cqn = sq->cq.mcq.cqn;
1362 csp.wq_ctrl = &sq->wq_ctrl;
1363 csp.min_inline_mode = params->tx_min_inline_mode;
1364 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1365 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1366 if (err)
1367 goto err_free_icosq;
1368
1369 return 0;
1370
1371 err_free_icosq:
1372 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1373 mlx5e_free_icosq(sq);
1374
1375 return err;
1376 }
1377
1378 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1379 {
1380 struct mlx5e_channel *c = sq->channel;
1381
1382 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1383 napi_synchronize(&c->napi);
1384
1385 mlx5e_destroy_sq(c->mdev, sq->sqn);
1386 mlx5e_free_icosq(sq);
1387 }
1388
1389 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1390 struct mlx5e_params *params,
1391 struct mlx5e_sq_param *param,
1392 struct mlx5e_xdpsq *sq)
1393 {
1394 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1395 struct mlx5e_create_sq_param csp = {};
1396 unsigned int inline_hdr_sz = 0;
1397 int err;
1398 int i;
1399
1400 err = mlx5e_alloc_xdpsq(c, params, param, sq);
1401 if (err)
1402 return err;
1403
1404 csp.tis_lst_sz = 1;
1405 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1406 csp.cqn = sq->cq.mcq.cqn;
1407 csp.wq_ctrl = &sq->wq_ctrl;
1408 csp.min_inline_mode = sq->min_inline_mode;
1409 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1410 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1411 if (err)
1412 goto err_free_xdpsq;
1413
1414 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1415 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1416 ds_cnt++;
1417 }
1418
1419 /* Pre initialize fixed WQE fields */
1420 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1421 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1422 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1423 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1424 struct mlx5_wqe_data_seg *dseg;
1425
1426 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1427 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1428
1429 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1430 dseg->lkey = sq->mkey_be;
1431 }
1432
1433 return 0;
1434
1435 err_free_xdpsq:
1436 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1437 mlx5e_free_xdpsq(sq);
1438
1439 return err;
1440 }
1441
1442 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1443 {
1444 struct mlx5e_channel *c = sq->channel;
1445
1446 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1447 napi_synchronize(&c->napi);
1448
1449 mlx5e_destroy_sq(c->mdev, sq->sqn);
1450 mlx5e_free_xdpsq_descs(sq);
1451 mlx5e_free_xdpsq(sq);
1452 }
1453
1454 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1455 struct mlx5e_cq_param *param,
1456 struct mlx5e_cq *cq)
1457 {
1458 struct mlx5_core_cq *mcq = &cq->mcq;
1459 int eqn_not_used;
1460 unsigned int irqn;
1461 int err;
1462 u32 i;
1463
1464 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1465 &cq->wq_ctrl);
1466 if (err)
1467 return err;
1468
1469 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1470
1471 mcq->cqe_sz = 64;
1472 mcq->set_ci_db = cq->wq_ctrl.db.db;
1473 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1474 *mcq->set_ci_db = 0;
1475 *mcq->arm_db = 0;
1476 mcq->vector = param->eq_ix;
1477 mcq->comp = mlx5e_completion_event;
1478 mcq->event = mlx5e_cq_error_event;
1479 mcq->irqn = irqn;
1480
1481 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1482 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1483
1484 cqe->op_own = 0xf1;
1485 }
1486
1487 cq->mdev = mdev;
1488
1489 return 0;
1490 }
1491
1492 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1493 struct mlx5e_cq_param *param,
1494 struct mlx5e_cq *cq)
1495 {
1496 struct mlx5_core_dev *mdev = c->priv->mdev;
1497 int err;
1498
1499 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1500 param->wq.db_numa_node = cpu_to_node(c->cpu);
1501 param->eq_ix = c->ix;
1502
1503 err = mlx5e_alloc_cq_common(mdev, param, cq);
1504
1505 cq->napi = &c->napi;
1506 cq->channel = c;
1507
1508 return err;
1509 }
1510
1511 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1512 {
1513 mlx5_cqwq_destroy(&cq->wq_ctrl);
1514 }
1515
1516 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1517 {
1518 struct mlx5_core_dev *mdev = cq->mdev;
1519 struct mlx5_core_cq *mcq = &cq->mcq;
1520
1521 void *in;
1522 void *cqc;
1523 int inlen;
1524 unsigned int irqn_not_used;
1525 int eqn;
1526 int err;
1527
1528 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1529 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1530 in = kvzalloc(inlen, GFP_KERNEL);
1531 if (!in)
1532 return -ENOMEM;
1533
1534 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1535
1536 memcpy(cqc, param->cqc, sizeof(param->cqc));
1537
1538 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1539 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1540
1541 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1542
1543 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1544 MLX5_SET(cqc, cqc, c_eqn, eqn);
1545 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1546 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1547 MLX5_ADAPTER_PAGE_SHIFT);
1548 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1549
1550 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1551
1552 kvfree(in);
1553
1554 if (err)
1555 return err;
1556
1557 mlx5e_cq_arm(cq);
1558
1559 return 0;
1560 }
1561
1562 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1563 {
1564 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1565 }
1566
1567 static int mlx5e_open_cq(struct mlx5e_channel *c,
1568 struct mlx5e_cq_moder moder,
1569 struct mlx5e_cq_param *param,
1570 struct mlx5e_cq *cq)
1571 {
1572 struct mlx5_core_dev *mdev = c->mdev;
1573 int err;
1574
1575 err = mlx5e_alloc_cq(c, param, cq);
1576 if (err)
1577 return err;
1578
1579 err = mlx5e_create_cq(cq, param);
1580 if (err)
1581 goto err_free_cq;
1582
1583 if (MLX5_CAP_GEN(mdev, cq_moderation))
1584 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1585 return 0;
1586
1587 err_free_cq:
1588 mlx5e_free_cq(cq);
1589
1590 return err;
1591 }
1592
1593 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1594 {
1595 mlx5e_destroy_cq(cq);
1596 mlx5e_free_cq(cq);
1597 }
1598
1599 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1600 {
1601 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1602 }
1603
1604 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1605 struct mlx5e_params *params,
1606 struct mlx5e_channel_param *cparam)
1607 {
1608 int err;
1609 int tc;
1610
1611 for (tc = 0; tc < c->num_tc; tc++) {
1612 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1613 &cparam->tx_cq, &c->sq[tc].cq);
1614 if (err)
1615 goto err_close_tx_cqs;
1616 }
1617
1618 return 0;
1619
1620 err_close_tx_cqs:
1621 for (tc--; tc >= 0; tc--)
1622 mlx5e_close_cq(&c->sq[tc].cq);
1623
1624 return err;
1625 }
1626
1627 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1628 {
1629 int tc;
1630
1631 for (tc = 0; tc < c->num_tc; tc++)
1632 mlx5e_close_cq(&c->sq[tc].cq);
1633 }
1634
1635 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1636 struct mlx5e_params *params,
1637 struct mlx5e_channel_param *cparam)
1638 {
1639 int err;
1640 int tc;
1641
1642 for (tc = 0; tc < params->num_tc; tc++) {
1643 int txq_ix = c->ix + tc * params->num_channels;
1644
1645 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1646 params, &cparam->sq, &c->sq[tc]);
1647 if (err)
1648 goto err_close_sqs;
1649 }
1650
1651 return 0;
1652
1653 err_close_sqs:
1654 for (tc--; tc >= 0; tc--)
1655 mlx5e_close_txqsq(&c->sq[tc]);
1656
1657 return err;
1658 }
1659
1660 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1661 {
1662 int tc;
1663
1664 for (tc = 0; tc < c->num_tc; tc++)
1665 mlx5e_close_txqsq(&c->sq[tc]);
1666 }
1667
1668 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1669 struct mlx5e_txqsq *sq, u32 rate)
1670 {
1671 struct mlx5e_priv *priv = netdev_priv(dev);
1672 struct mlx5_core_dev *mdev = priv->mdev;
1673 struct mlx5e_modify_sq_param msp = {0};
1674 u16 rl_index = 0;
1675 int err;
1676
1677 if (rate == sq->rate_limit)
1678 /* nothing to do */
1679 return 0;
1680
1681 if (sq->rate_limit)
1682 /* remove current rl index to free space to next ones */
1683 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1684
1685 sq->rate_limit = 0;
1686
1687 if (rate) {
1688 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1689 if (err) {
1690 netdev_err(dev, "Failed configuring rate %u: %d\n",
1691 rate, err);
1692 return err;
1693 }
1694 }
1695
1696 msp.curr_state = MLX5_SQC_STATE_RDY;
1697 msp.next_state = MLX5_SQC_STATE_RDY;
1698 msp.rl_index = rl_index;
1699 msp.rl_update = true;
1700 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1701 if (err) {
1702 netdev_err(dev, "Failed configuring rate %u: %d\n",
1703 rate, err);
1704 /* remove the rate from the table */
1705 if (rate)
1706 mlx5_rl_remove_rate(mdev, rate);
1707 return err;
1708 }
1709
1710 sq->rate_limit = rate;
1711 return 0;
1712 }
1713
1714 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1715 {
1716 struct mlx5e_priv *priv = netdev_priv(dev);
1717 struct mlx5_core_dev *mdev = priv->mdev;
1718 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1719 int err = 0;
1720
1721 if (!mlx5_rl_is_supported(mdev)) {
1722 netdev_err(dev, "Rate limiting is not supported on this device\n");
1723 return -EINVAL;
1724 }
1725
1726 /* rate is given in Mb/sec, HW config is in Kb/sec */
1727 rate = rate << 10;
1728
1729 /* Check whether rate in valid range, 0 is always valid */
1730 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1731 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1732 return -ERANGE;
1733 }
1734
1735 mutex_lock(&priv->state_lock);
1736 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1737 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1738 if (!err)
1739 priv->tx_rates[index] = rate;
1740 mutex_unlock(&priv->state_lock);
1741
1742 return err;
1743 }
1744
1745 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1746 struct mlx5e_params *params,
1747 struct mlx5e_channel_param *cparam,
1748 struct mlx5e_channel **cp)
1749 {
1750 struct mlx5e_cq_moder icocq_moder = {0, 0};
1751 struct net_device *netdev = priv->netdev;
1752 int cpu = mlx5e_get_cpu(priv, ix);
1753 struct mlx5e_channel *c;
1754 int err;
1755
1756 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1757 if (!c)
1758 return -ENOMEM;
1759
1760 c->priv = priv;
1761 c->mdev = priv->mdev;
1762 c->tstamp = &priv->tstamp;
1763 c->ix = ix;
1764 c->cpu = cpu;
1765 c->pdev = &priv->mdev->pdev->dev;
1766 c->netdev = priv->netdev;
1767 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1768 c->num_tc = params->num_tc;
1769 c->xdp = !!params->xdp_prog;
1770
1771 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1772
1773 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1774 if (err)
1775 goto err_napi_del;
1776
1777 err = mlx5e_open_tx_cqs(c, params, cparam);
1778 if (err)
1779 goto err_close_icosq_cq;
1780
1781 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1782 if (err)
1783 goto err_close_tx_cqs;
1784
1785 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1786 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1787 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1788 if (err)
1789 goto err_close_rx_cq;
1790
1791 napi_enable(&c->napi);
1792
1793 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1794 if (err)
1795 goto err_disable_napi;
1796
1797 err = mlx5e_open_sqs(c, params, cparam);
1798 if (err)
1799 goto err_close_icosq;
1800
1801 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1802 if (err)
1803 goto err_close_sqs;
1804
1805 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1806 if (err)
1807 goto err_close_xdp_sq;
1808
1809 *cp = c;
1810
1811 return 0;
1812 err_close_xdp_sq:
1813 if (c->xdp)
1814 mlx5e_close_xdpsq(&c->rq.xdpsq);
1815
1816 err_close_sqs:
1817 mlx5e_close_sqs(c);
1818
1819 err_close_icosq:
1820 mlx5e_close_icosq(&c->icosq);
1821
1822 err_disable_napi:
1823 napi_disable(&c->napi);
1824 if (c->xdp)
1825 mlx5e_close_cq(&c->rq.xdpsq.cq);
1826
1827 err_close_rx_cq:
1828 mlx5e_close_cq(&c->rq.cq);
1829
1830 err_close_tx_cqs:
1831 mlx5e_close_tx_cqs(c);
1832
1833 err_close_icosq_cq:
1834 mlx5e_close_cq(&c->icosq.cq);
1835
1836 err_napi_del:
1837 netif_napi_del(&c->napi);
1838 kfree(c);
1839
1840 return err;
1841 }
1842
1843 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1844 {
1845 int tc;
1846
1847 for (tc = 0; tc < c->num_tc; tc++)
1848 mlx5e_activate_txqsq(&c->sq[tc]);
1849 mlx5e_activate_rq(&c->rq);
1850 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1851 }
1852
1853 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1854 {
1855 int tc;
1856
1857 mlx5e_deactivate_rq(&c->rq);
1858 for (tc = 0; tc < c->num_tc; tc++)
1859 mlx5e_deactivate_txqsq(&c->sq[tc]);
1860 }
1861
1862 static void mlx5e_close_channel(struct mlx5e_channel *c)
1863 {
1864 mlx5e_close_rq(&c->rq);
1865 if (c->xdp)
1866 mlx5e_close_xdpsq(&c->rq.xdpsq);
1867 mlx5e_close_sqs(c);
1868 mlx5e_close_icosq(&c->icosq);
1869 napi_disable(&c->napi);
1870 if (c->xdp)
1871 mlx5e_close_cq(&c->rq.xdpsq.cq);
1872 mlx5e_close_cq(&c->rq.cq);
1873 mlx5e_close_tx_cqs(c);
1874 mlx5e_close_cq(&c->icosq.cq);
1875 netif_napi_del(&c->napi);
1876
1877 kfree(c);
1878 }
1879
1880 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1881 struct mlx5e_params *params,
1882 struct mlx5e_rq_param *param)
1883 {
1884 void *rqc = param->rqc;
1885 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1886
1887 switch (params->rq_wq_type) {
1888 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1889 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1890 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
1891 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1892 break;
1893 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1894 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1895 }
1896
1897 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1898 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1899 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
1900 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1901 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1902 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
1903 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
1904
1905 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1906 param->wq.linear = 1;
1907 }
1908
1909 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1910 {
1911 void *rqc = param->rqc;
1912 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1913
1914 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1915 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1916 }
1917
1918 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1919 struct mlx5e_sq_param *param)
1920 {
1921 void *sqc = param->sqc;
1922 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1923
1924 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1925 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1926
1927 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1928 }
1929
1930 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1931 struct mlx5e_params *params,
1932 struct mlx5e_sq_param *param)
1933 {
1934 void *sqc = param->sqc;
1935 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1936
1937 mlx5e_build_sq_param_common(priv, param);
1938 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1939 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1940 }
1941
1942 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1943 struct mlx5e_cq_param *param)
1944 {
1945 void *cqc = param->cqc;
1946
1947 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1948 }
1949
1950 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1951 struct mlx5e_params *params,
1952 struct mlx5e_cq_param *param)
1953 {
1954 void *cqc = param->cqc;
1955 u8 log_cq_size;
1956
1957 switch (params->rq_wq_type) {
1958 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1959 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
1960 break;
1961 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1962 log_cq_size = params->log_rq_size;
1963 }
1964
1965 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1966 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1967 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1968 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1969 }
1970
1971 mlx5e_build_common_cq_param(priv, param);
1972 }
1973
1974 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1975 struct mlx5e_params *params,
1976 struct mlx5e_cq_param *param)
1977 {
1978 void *cqc = param->cqc;
1979
1980 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1981
1982 mlx5e_build_common_cq_param(priv, param);
1983
1984 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1985 }
1986
1987 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1988 u8 log_wq_size,
1989 struct mlx5e_cq_param *param)
1990 {
1991 void *cqc = param->cqc;
1992
1993 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1994
1995 mlx5e_build_common_cq_param(priv, param);
1996
1997 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1998 }
1999
2000 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2001 u8 log_wq_size,
2002 struct mlx5e_sq_param *param)
2003 {
2004 void *sqc = param->sqc;
2005 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2006
2007 mlx5e_build_sq_param_common(priv, param);
2008
2009 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2010 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2011 }
2012
2013 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2014 struct mlx5e_params *params,
2015 struct mlx5e_sq_param *param)
2016 {
2017 void *sqc = param->sqc;
2018 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2019
2020 mlx5e_build_sq_param_common(priv, param);
2021 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2022 }
2023
2024 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2025 struct mlx5e_params *params,
2026 struct mlx5e_channel_param *cparam)
2027 {
2028 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2029
2030 mlx5e_build_rq_param(priv, params, &cparam->rq);
2031 mlx5e_build_sq_param(priv, params, &cparam->sq);
2032 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2033 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2034 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2035 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2036 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2037 }
2038
2039 int mlx5e_open_channels(struct mlx5e_priv *priv,
2040 struct mlx5e_channels *chs)
2041 {
2042 struct mlx5e_channel_param *cparam;
2043 int err = -ENOMEM;
2044 int i;
2045
2046 chs->num = chs->params.num_channels;
2047
2048 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2049 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2050 if (!chs->c || !cparam)
2051 goto err_free;
2052
2053 mlx5e_build_channel_param(priv, &chs->params, cparam);
2054 for (i = 0; i < chs->num; i++) {
2055 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2056 if (err)
2057 goto err_close_channels;
2058 }
2059
2060 kfree(cparam);
2061 return 0;
2062
2063 err_close_channels:
2064 for (i--; i >= 0; i--)
2065 mlx5e_close_channel(chs->c[i]);
2066
2067 err_free:
2068 kfree(chs->c);
2069 kfree(cparam);
2070 chs->num = 0;
2071 return err;
2072 }
2073
2074 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2075 {
2076 int i;
2077
2078 for (i = 0; i < chs->num; i++)
2079 mlx5e_activate_channel(chs->c[i]);
2080 }
2081
2082 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2083 {
2084 int err = 0;
2085 int i;
2086
2087 for (i = 0; i < chs->num; i++) {
2088 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2089 if (err)
2090 break;
2091 }
2092
2093 return err;
2094 }
2095
2096 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2097 {
2098 int i;
2099
2100 for (i = 0; i < chs->num; i++)
2101 mlx5e_deactivate_channel(chs->c[i]);
2102 }
2103
2104 void mlx5e_close_channels(struct mlx5e_channels *chs)
2105 {
2106 int i;
2107
2108 for (i = 0; i < chs->num; i++)
2109 mlx5e_close_channel(chs->c[i]);
2110
2111 kfree(chs->c);
2112 chs->num = 0;
2113 }
2114
2115 static int
2116 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2117 {
2118 struct mlx5_core_dev *mdev = priv->mdev;
2119 void *rqtc;
2120 int inlen;
2121 int err;
2122 u32 *in;
2123 int i;
2124
2125 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2126 in = kvzalloc(inlen, GFP_KERNEL);
2127 if (!in)
2128 return -ENOMEM;
2129
2130 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2131
2132 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2133 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2134
2135 for (i = 0; i < sz; i++)
2136 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2137
2138 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2139 if (!err)
2140 rqt->enabled = true;
2141
2142 kvfree(in);
2143 return err;
2144 }
2145
2146 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2147 {
2148 rqt->enabled = false;
2149 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2150 }
2151
2152 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2153 {
2154 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2155 int err;
2156
2157 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2158 if (err)
2159 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2160 return err;
2161 }
2162
2163 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2164 {
2165 struct mlx5e_rqt *rqt;
2166 int err;
2167 int ix;
2168
2169 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2170 rqt = &priv->direct_tir[ix].rqt;
2171 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2172 if (err)
2173 goto err_destroy_rqts;
2174 }
2175
2176 return 0;
2177
2178 err_destroy_rqts:
2179 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2180 for (ix--; ix >= 0; ix--)
2181 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2182
2183 return err;
2184 }
2185
2186 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2187 {
2188 int i;
2189
2190 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2191 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2192 }
2193
2194 static int mlx5e_rx_hash_fn(int hfunc)
2195 {
2196 return (hfunc == ETH_RSS_HASH_TOP) ?
2197 MLX5_RX_HASH_FN_TOEPLITZ :
2198 MLX5_RX_HASH_FN_INVERTED_XOR8;
2199 }
2200
2201 static int mlx5e_bits_invert(unsigned long a, int size)
2202 {
2203 int inv = 0;
2204 int i;
2205
2206 for (i = 0; i < size; i++)
2207 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2208
2209 return inv;
2210 }
2211
2212 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2213 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2214 {
2215 int i;
2216
2217 for (i = 0; i < sz; i++) {
2218 u32 rqn;
2219
2220 if (rrp.is_rss) {
2221 int ix = i;
2222
2223 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2224 ix = mlx5e_bits_invert(i, ilog2(sz));
2225
2226 ix = priv->channels.params.indirection_rqt[ix];
2227 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2228 } else {
2229 rqn = rrp.rqn;
2230 }
2231 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2232 }
2233 }
2234
2235 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2236 struct mlx5e_redirect_rqt_param rrp)
2237 {
2238 struct mlx5_core_dev *mdev = priv->mdev;
2239 void *rqtc;
2240 int inlen;
2241 u32 *in;
2242 int err;
2243
2244 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2245 in = kvzalloc(inlen, GFP_KERNEL);
2246 if (!in)
2247 return -ENOMEM;
2248
2249 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2250
2251 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2252 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2253 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2254 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2255
2256 kvfree(in);
2257 return err;
2258 }
2259
2260 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2261 struct mlx5e_redirect_rqt_param rrp)
2262 {
2263 if (!rrp.is_rss)
2264 return rrp.rqn;
2265
2266 if (ix >= rrp.rss.channels->num)
2267 return priv->drop_rq.rqn;
2268
2269 return rrp.rss.channels->c[ix]->rq.rqn;
2270 }
2271
2272 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2273 struct mlx5e_redirect_rqt_param rrp)
2274 {
2275 u32 rqtn;
2276 int ix;
2277
2278 if (priv->indir_rqt.enabled) {
2279 /* RSS RQ table */
2280 rqtn = priv->indir_rqt.rqtn;
2281 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2282 }
2283
2284 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2285 struct mlx5e_redirect_rqt_param direct_rrp = {
2286 .is_rss = false,
2287 {
2288 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2289 },
2290 };
2291
2292 /* Direct RQ Tables */
2293 if (!priv->direct_tir[ix].rqt.enabled)
2294 continue;
2295
2296 rqtn = priv->direct_tir[ix].rqt.rqtn;
2297 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2298 }
2299 }
2300
2301 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2302 struct mlx5e_channels *chs)
2303 {
2304 struct mlx5e_redirect_rqt_param rrp = {
2305 .is_rss = true,
2306 {
2307 .rss = {
2308 .channels = chs,
2309 .hfunc = chs->params.rss_hfunc,
2310 }
2311 },
2312 };
2313
2314 mlx5e_redirect_rqts(priv, rrp);
2315 }
2316
2317 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2318 {
2319 struct mlx5e_redirect_rqt_param drop_rrp = {
2320 .is_rss = false,
2321 {
2322 .rqn = priv->drop_rq.rqn,
2323 },
2324 };
2325
2326 mlx5e_redirect_rqts(priv, drop_rrp);
2327 }
2328
2329 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2330 {
2331 if (!params->lro_en)
2332 return;
2333
2334 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2335
2336 MLX5_SET(tirc, tirc, lro_enable_mask,
2337 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2338 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2339 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2340 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2341 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2342 }
2343
2344 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2345 enum mlx5e_traffic_types tt,
2346 void *tirc)
2347 {
2348 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2349
2350 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2351 MLX5_HASH_FIELD_SEL_DST_IP)
2352
2353 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2354 MLX5_HASH_FIELD_SEL_DST_IP |\
2355 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2356 MLX5_HASH_FIELD_SEL_L4_DPORT)
2357
2358 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2359 MLX5_HASH_FIELD_SEL_DST_IP |\
2360 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2361
2362 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2363 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2364 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2365 rx_hash_toeplitz_key);
2366 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2367 rx_hash_toeplitz_key);
2368
2369 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2370 memcpy(rss_key, params->toeplitz_hash_key, len);
2371 }
2372
2373 switch (tt) {
2374 case MLX5E_TT_IPV4_TCP:
2375 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2376 MLX5_L3_PROT_TYPE_IPV4);
2377 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2378 MLX5_L4_PROT_TYPE_TCP);
2379 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2380 MLX5_HASH_IP_L4PORTS);
2381 break;
2382
2383 case MLX5E_TT_IPV6_TCP:
2384 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2385 MLX5_L3_PROT_TYPE_IPV6);
2386 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2387 MLX5_L4_PROT_TYPE_TCP);
2388 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2389 MLX5_HASH_IP_L4PORTS);
2390 break;
2391
2392 case MLX5E_TT_IPV4_UDP:
2393 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2394 MLX5_L3_PROT_TYPE_IPV4);
2395 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2396 MLX5_L4_PROT_TYPE_UDP);
2397 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2398 MLX5_HASH_IP_L4PORTS);
2399 break;
2400
2401 case MLX5E_TT_IPV6_UDP:
2402 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2403 MLX5_L3_PROT_TYPE_IPV6);
2404 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2405 MLX5_L4_PROT_TYPE_UDP);
2406 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2407 MLX5_HASH_IP_L4PORTS);
2408 break;
2409
2410 case MLX5E_TT_IPV4_IPSEC_AH:
2411 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2412 MLX5_L3_PROT_TYPE_IPV4);
2413 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2414 MLX5_HASH_IP_IPSEC_SPI);
2415 break;
2416
2417 case MLX5E_TT_IPV6_IPSEC_AH:
2418 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2419 MLX5_L3_PROT_TYPE_IPV6);
2420 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2421 MLX5_HASH_IP_IPSEC_SPI);
2422 break;
2423
2424 case MLX5E_TT_IPV4_IPSEC_ESP:
2425 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2426 MLX5_L3_PROT_TYPE_IPV4);
2427 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2428 MLX5_HASH_IP_IPSEC_SPI);
2429 break;
2430
2431 case MLX5E_TT_IPV6_IPSEC_ESP:
2432 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2433 MLX5_L3_PROT_TYPE_IPV6);
2434 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2435 MLX5_HASH_IP_IPSEC_SPI);
2436 break;
2437
2438 case MLX5E_TT_IPV4:
2439 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2440 MLX5_L3_PROT_TYPE_IPV4);
2441 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2442 MLX5_HASH_IP);
2443 break;
2444
2445 case MLX5E_TT_IPV6:
2446 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2447 MLX5_L3_PROT_TYPE_IPV6);
2448 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2449 MLX5_HASH_IP);
2450 break;
2451 default:
2452 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2453 }
2454 }
2455
2456 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2457 {
2458 struct mlx5_core_dev *mdev = priv->mdev;
2459
2460 void *in;
2461 void *tirc;
2462 int inlen;
2463 int err;
2464 int tt;
2465 int ix;
2466
2467 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2468 in = kvzalloc(inlen, GFP_KERNEL);
2469 if (!in)
2470 return -ENOMEM;
2471
2472 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2473 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2474
2475 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2476
2477 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2478 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2479 inlen);
2480 if (err)
2481 goto free_in;
2482 }
2483
2484 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2485 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2486 in, inlen);
2487 if (err)
2488 goto free_in;
2489 }
2490
2491 free_in:
2492 kvfree(in);
2493
2494 return err;
2495 }
2496
2497 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2498 {
2499 struct mlx5_core_dev *mdev = priv->mdev;
2500 u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
2501 int err;
2502
2503 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2504 if (err)
2505 return err;
2506
2507 /* Update vport context MTU */
2508 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2509 return 0;
2510 }
2511
2512 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2513 {
2514 struct mlx5_core_dev *mdev = priv->mdev;
2515 u16 hw_mtu = 0;
2516 int err;
2517
2518 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2519 if (err || !hw_mtu) /* fallback to port oper mtu */
2520 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2521
2522 *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
2523 }
2524
2525 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2526 {
2527 struct net_device *netdev = priv->netdev;
2528 u16 mtu;
2529 int err;
2530
2531 err = mlx5e_set_mtu(priv, netdev->mtu);
2532 if (err)
2533 return err;
2534
2535 mlx5e_query_mtu(priv, &mtu);
2536 if (mtu != netdev->mtu)
2537 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2538 __func__, mtu, netdev->mtu);
2539
2540 netdev->mtu = mtu;
2541 return 0;
2542 }
2543
2544 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2545 {
2546 struct mlx5e_priv *priv = netdev_priv(netdev);
2547 int nch = priv->channels.params.num_channels;
2548 int ntc = priv->channels.params.num_tc;
2549 int tc;
2550
2551 netdev_reset_tc(netdev);
2552
2553 if (ntc == 1)
2554 return;
2555
2556 netdev_set_num_tc(netdev, ntc);
2557
2558 /* Map netdev TCs to offset 0
2559 * We have our own UP to TXQ mapping for QoS
2560 */
2561 for (tc = 0; tc < ntc; tc++)
2562 netdev_set_tc_queue(netdev, tc, nch, 0);
2563 }
2564
2565 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2566 {
2567 struct mlx5e_channel *c;
2568 struct mlx5e_txqsq *sq;
2569 int i, tc;
2570
2571 for (i = 0; i < priv->channels.num; i++)
2572 for (tc = 0; tc < priv->profile->max_tc; tc++)
2573 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2574
2575 for (i = 0; i < priv->channels.num; i++) {
2576 c = priv->channels.c[i];
2577 for (tc = 0; tc < c->num_tc; tc++) {
2578 sq = &c->sq[tc];
2579 priv->txq2sq[sq->txq_ix] = sq;
2580 }
2581 }
2582 }
2583
2584 static bool mlx5e_is_eswitch_vport_mngr(struct mlx5_core_dev *mdev)
2585 {
2586 return (MLX5_CAP_GEN(mdev, vport_group_manager) &&
2587 MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH);
2588 }
2589
2590 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2591 {
2592 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2593 struct net_device *netdev = priv->netdev;
2594
2595 mlx5e_netdev_set_tcs(netdev);
2596 netif_set_real_num_tx_queues(netdev, num_txqs);
2597 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2598
2599 mlx5e_build_channels_tx_maps(priv);
2600 mlx5e_activate_channels(&priv->channels);
2601 netif_tx_start_all_queues(priv->netdev);
2602
2603 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
2604 mlx5e_add_sqs_fwd_rules(priv);
2605
2606 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2607 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2608 }
2609
2610 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2611 {
2612 mlx5e_redirect_rqts_to_drop(priv);
2613
2614 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
2615 mlx5e_remove_sqs_fwd_rules(priv);
2616
2617 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2618 * polling for inactive tx queues.
2619 */
2620 netif_tx_stop_all_queues(priv->netdev);
2621 netif_tx_disable(priv->netdev);
2622 mlx5e_deactivate_channels(&priv->channels);
2623 }
2624
2625 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2626 struct mlx5e_channels *new_chs,
2627 mlx5e_fp_hw_modify hw_modify)
2628 {
2629 struct net_device *netdev = priv->netdev;
2630 int new_num_txqs;
2631 int carrier_ok;
2632 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2633
2634 carrier_ok = netif_carrier_ok(netdev);
2635 netif_carrier_off(netdev);
2636
2637 if (new_num_txqs < netdev->real_num_tx_queues)
2638 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2639
2640 mlx5e_deactivate_priv_channels(priv);
2641 mlx5e_close_channels(&priv->channels);
2642
2643 priv->channels = *new_chs;
2644
2645 /* New channels are ready to roll, modify HW settings if needed */
2646 if (hw_modify)
2647 hw_modify(priv);
2648
2649 mlx5e_refresh_tirs(priv, false);
2650 mlx5e_activate_priv_channels(priv);
2651
2652 /* return carrier back if needed */
2653 if (carrier_ok)
2654 netif_carrier_on(netdev);
2655 }
2656
2657 int mlx5e_open_locked(struct net_device *netdev)
2658 {
2659 struct mlx5e_priv *priv = netdev_priv(netdev);
2660 int err;
2661
2662 set_bit(MLX5E_STATE_OPENED, &priv->state);
2663
2664 err = mlx5e_open_channels(priv, &priv->channels);
2665 if (err)
2666 goto err_clear_state_opened_flag;
2667
2668 mlx5e_refresh_tirs(priv, false);
2669 mlx5e_activate_priv_channels(priv);
2670 if (priv->profile->update_carrier)
2671 priv->profile->update_carrier(priv);
2672 mlx5e_timestamp_init(priv);
2673
2674 if (priv->profile->update_stats)
2675 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2676
2677 return 0;
2678
2679 err_clear_state_opened_flag:
2680 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2681 return err;
2682 }
2683
2684 int mlx5e_open(struct net_device *netdev)
2685 {
2686 struct mlx5e_priv *priv = netdev_priv(netdev);
2687 int err;
2688
2689 mutex_lock(&priv->state_lock);
2690 err = mlx5e_open_locked(netdev);
2691 mutex_unlock(&priv->state_lock);
2692
2693 return err;
2694 }
2695
2696 int mlx5e_close_locked(struct net_device *netdev)
2697 {
2698 struct mlx5e_priv *priv = netdev_priv(netdev);
2699
2700 /* May already be CLOSED in case a previous configuration operation
2701 * (e.g RX/TX queue size change) that involves close&open failed.
2702 */
2703 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2704 return 0;
2705
2706 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2707
2708 mlx5e_timestamp_cleanup(priv);
2709 netif_carrier_off(priv->netdev);
2710 mlx5e_deactivate_priv_channels(priv);
2711 mlx5e_close_channels(&priv->channels);
2712
2713 return 0;
2714 }
2715
2716 int mlx5e_close(struct net_device *netdev)
2717 {
2718 struct mlx5e_priv *priv = netdev_priv(netdev);
2719 int err;
2720
2721 if (!netif_device_present(netdev))
2722 return -ENODEV;
2723
2724 mutex_lock(&priv->state_lock);
2725 err = mlx5e_close_locked(netdev);
2726 mutex_unlock(&priv->state_lock);
2727
2728 return err;
2729 }
2730
2731 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2732 struct mlx5e_rq *rq,
2733 struct mlx5e_rq_param *param)
2734 {
2735 void *rqc = param->rqc;
2736 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2737 int err;
2738
2739 param->wq.db_numa_node = param->wq.buf_numa_node;
2740
2741 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2742 &rq->wq_ctrl);
2743 if (err)
2744 return err;
2745
2746 rq->mdev = mdev;
2747
2748 return 0;
2749 }
2750
2751 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2752 struct mlx5e_cq *cq,
2753 struct mlx5e_cq_param *param)
2754 {
2755 return mlx5e_alloc_cq_common(mdev, param, cq);
2756 }
2757
2758 static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2759 struct mlx5e_rq *drop_rq)
2760 {
2761 struct mlx5e_cq_param cq_param = {};
2762 struct mlx5e_rq_param rq_param = {};
2763 struct mlx5e_cq *cq = &drop_rq->cq;
2764 int err;
2765
2766 mlx5e_build_drop_rq_param(&rq_param);
2767
2768 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2769 if (err)
2770 return err;
2771
2772 err = mlx5e_create_cq(cq, &cq_param);
2773 if (err)
2774 goto err_free_cq;
2775
2776 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2777 if (err)
2778 goto err_destroy_cq;
2779
2780 err = mlx5e_create_rq(drop_rq, &rq_param);
2781 if (err)
2782 goto err_free_rq;
2783
2784 return 0;
2785
2786 err_free_rq:
2787 mlx5e_free_rq(drop_rq);
2788
2789 err_destroy_cq:
2790 mlx5e_destroy_cq(cq);
2791
2792 err_free_cq:
2793 mlx5e_free_cq(cq);
2794
2795 return err;
2796 }
2797
2798 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2799 {
2800 mlx5e_destroy_rq(drop_rq);
2801 mlx5e_free_rq(drop_rq);
2802 mlx5e_destroy_cq(&drop_rq->cq);
2803 mlx5e_free_cq(&drop_rq->cq);
2804 }
2805
2806 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2807 u32 underlay_qpn, u32 *tisn)
2808 {
2809 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2810 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2811
2812 MLX5_SET(tisc, tisc, prio, tc << 1);
2813 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2814 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2815
2816 if (mlx5_lag_is_lacp_owner(mdev))
2817 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2818
2819 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2820 }
2821
2822 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2823 {
2824 mlx5_core_destroy_tis(mdev, tisn);
2825 }
2826
2827 int mlx5e_create_tises(struct mlx5e_priv *priv)
2828 {
2829 int err;
2830 int tc;
2831
2832 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2833 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2834 if (err)
2835 goto err_close_tises;
2836 }
2837
2838 return 0;
2839
2840 err_close_tises:
2841 for (tc--; tc >= 0; tc--)
2842 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2843
2844 return err;
2845 }
2846
2847 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2848 {
2849 int tc;
2850
2851 for (tc = 0; tc < priv->profile->max_tc; tc++)
2852 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2853 }
2854
2855 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2856 enum mlx5e_traffic_types tt,
2857 u32 *tirc)
2858 {
2859 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2860
2861 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2862
2863 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2864 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2865 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
2866 }
2867
2868 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2869 {
2870 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2871
2872 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2873
2874 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2875 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2876 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2877 }
2878
2879 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2880 {
2881 struct mlx5e_tir *tir;
2882 void *tirc;
2883 int inlen;
2884 int err;
2885 u32 *in;
2886 int tt;
2887
2888 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2889 in = kvzalloc(inlen, GFP_KERNEL);
2890 if (!in)
2891 return -ENOMEM;
2892
2893 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2894 memset(in, 0, inlen);
2895 tir = &priv->indir_tir[tt];
2896 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2897 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2898 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2899 if (err)
2900 goto err_destroy_tirs;
2901 }
2902
2903 kvfree(in);
2904
2905 return 0;
2906
2907 err_destroy_tirs:
2908 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2909 for (tt--; tt >= 0; tt--)
2910 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2911
2912 kvfree(in);
2913
2914 return err;
2915 }
2916
2917 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2918 {
2919 int nch = priv->profile->max_nch(priv->mdev);
2920 struct mlx5e_tir *tir;
2921 void *tirc;
2922 int inlen;
2923 int err;
2924 u32 *in;
2925 int ix;
2926
2927 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2928 in = kvzalloc(inlen, GFP_KERNEL);
2929 if (!in)
2930 return -ENOMEM;
2931
2932 for (ix = 0; ix < nch; ix++) {
2933 memset(in, 0, inlen);
2934 tir = &priv->direct_tir[ix];
2935 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2936 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2937 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2938 if (err)
2939 goto err_destroy_ch_tirs;
2940 }
2941
2942 kvfree(in);
2943
2944 return 0;
2945
2946 err_destroy_ch_tirs:
2947 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
2948 for (ix--; ix >= 0; ix--)
2949 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2950
2951 kvfree(in);
2952
2953 return err;
2954 }
2955
2956 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2957 {
2958 int i;
2959
2960 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2961 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2962 }
2963
2964 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2965 {
2966 int nch = priv->profile->max_nch(priv->mdev);
2967 int i;
2968
2969 for (i = 0; i < nch; i++)
2970 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2971 }
2972
2973 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2974 {
2975 int err = 0;
2976 int i;
2977
2978 for (i = 0; i < chs->num; i++) {
2979 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2980 if (err)
2981 return err;
2982 }
2983
2984 return 0;
2985 }
2986
2987 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
2988 {
2989 int err = 0;
2990 int i;
2991
2992 for (i = 0; i < chs->num; i++) {
2993 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
2994 if (err)
2995 return err;
2996 }
2997
2998 return 0;
2999 }
3000
3001 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
3002 {
3003 struct mlx5e_priv *priv = netdev_priv(netdev);
3004 struct mlx5e_channels new_channels = {};
3005 int err = 0;
3006
3007 if (tc && tc != MLX5E_MAX_NUM_TC)
3008 return -EINVAL;
3009
3010 mutex_lock(&priv->state_lock);
3011
3012 new_channels.params = priv->channels.params;
3013 new_channels.params.num_tc = tc ? tc : 1;
3014
3015 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3016 priv->channels.params = new_channels.params;
3017 goto out;
3018 }
3019
3020 err = mlx5e_open_channels(priv, &new_channels);
3021 if (err)
3022 goto out;
3023
3024 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3025 out:
3026 mutex_unlock(&priv->state_lock);
3027 return err;
3028 }
3029
3030 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
3031 u32 chain_index, __be16 proto,
3032 struct tc_to_netdev *tc)
3033 {
3034 struct mlx5e_priv *priv = netdev_priv(dev);
3035
3036 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
3037 goto mqprio;
3038
3039 if (chain_index)
3040 return -EOPNOTSUPP;
3041
3042 switch (tc->type) {
3043 case TC_SETUP_CLSFLOWER:
3044 switch (tc->cls_flower->command) {
3045 case TC_CLSFLOWER_REPLACE:
3046 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
3047 case TC_CLSFLOWER_DESTROY:
3048 return mlx5e_delete_flower(priv, tc->cls_flower);
3049 case TC_CLSFLOWER_STATS:
3050 return mlx5e_stats_flower(priv, tc->cls_flower);
3051 }
3052 default:
3053 return -EOPNOTSUPP;
3054 }
3055
3056 mqprio:
3057 if (tc->type != TC_SETUP_MQPRIO)
3058 return -EINVAL;
3059
3060 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3061
3062 return mlx5e_setup_tc(dev, tc->mqprio->num_tc);
3063 }
3064
3065 static void
3066 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3067 {
3068 struct mlx5e_priv *priv = netdev_priv(dev);
3069 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3070 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3071 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3072
3073 if (mlx5e_is_uplink_rep(priv)) {
3074 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3075 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3076 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3077 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3078 } else {
3079 stats->rx_packets = sstats->rx_packets;
3080 stats->rx_bytes = sstats->rx_bytes;
3081 stats->tx_packets = sstats->tx_packets;
3082 stats->tx_bytes = sstats->tx_bytes;
3083 stats->tx_dropped = sstats->tx_queue_dropped;
3084 }
3085
3086 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3087
3088 stats->rx_length_errors =
3089 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3090 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3091 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3092 stats->rx_crc_errors =
3093 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3094 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3095 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3096 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3097 stats->rx_frame_errors;
3098 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3099
3100 /* vport multicast also counts packets that are dropped due to steering
3101 * or rx out of buffer
3102 */
3103 stats->multicast =
3104 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3105 }
3106
3107 static void mlx5e_set_rx_mode(struct net_device *dev)
3108 {
3109 struct mlx5e_priv *priv = netdev_priv(dev);
3110
3111 queue_work(priv->wq, &priv->set_rx_mode_work);
3112 }
3113
3114 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3115 {
3116 struct mlx5e_priv *priv = netdev_priv(netdev);
3117 struct sockaddr *saddr = addr;
3118
3119 if (!is_valid_ether_addr(saddr->sa_data))
3120 return -EADDRNOTAVAIL;
3121
3122 netif_addr_lock_bh(netdev);
3123 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3124 netif_addr_unlock_bh(netdev);
3125
3126 queue_work(priv->wq, &priv->set_rx_mode_work);
3127
3128 return 0;
3129 }
3130
3131 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
3132 do { \
3133 if (enable) \
3134 netdev->features |= feature; \
3135 else \
3136 netdev->features &= ~feature; \
3137 } while (0)
3138
3139 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3140
3141 static int set_feature_lro(struct net_device *netdev, bool enable)
3142 {
3143 struct mlx5e_priv *priv = netdev_priv(netdev);
3144 struct mlx5e_channels new_channels = {};
3145 int err = 0;
3146 bool reset;
3147
3148 mutex_lock(&priv->state_lock);
3149
3150 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3151 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3152
3153 new_channels.params = priv->channels.params;
3154 new_channels.params.lro_en = enable;
3155
3156 if (!reset) {
3157 priv->channels.params = new_channels.params;
3158 err = mlx5e_modify_tirs_lro(priv);
3159 goto out;
3160 }
3161
3162 err = mlx5e_open_channels(priv, &new_channels);
3163 if (err)
3164 goto out;
3165
3166 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3167 out:
3168 mutex_unlock(&priv->state_lock);
3169 return err;
3170 }
3171
3172 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3173 {
3174 struct mlx5e_priv *priv = netdev_priv(netdev);
3175
3176 if (enable)
3177 mlx5e_enable_vlan_filter(priv);
3178 else
3179 mlx5e_disable_vlan_filter(priv);
3180
3181 return 0;
3182 }
3183
3184 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3185 {
3186 struct mlx5e_priv *priv = netdev_priv(netdev);
3187
3188 if (!enable && mlx5e_tc_num_filters(priv)) {
3189 netdev_err(netdev,
3190 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3191 return -EINVAL;
3192 }
3193
3194 return 0;
3195 }
3196
3197 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3198 {
3199 struct mlx5e_priv *priv = netdev_priv(netdev);
3200 struct mlx5_core_dev *mdev = priv->mdev;
3201
3202 return mlx5_set_port_fcs(mdev, !enable);
3203 }
3204
3205 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3206 {
3207 struct mlx5e_priv *priv = netdev_priv(netdev);
3208 int err;
3209
3210 mutex_lock(&priv->state_lock);
3211
3212 priv->channels.params.scatter_fcs_en = enable;
3213 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3214 if (err)
3215 priv->channels.params.scatter_fcs_en = !enable;
3216
3217 mutex_unlock(&priv->state_lock);
3218
3219 return err;
3220 }
3221
3222 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3223 {
3224 struct mlx5e_priv *priv = netdev_priv(netdev);
3225 int err = 0;
3226
3227 mutex_lock(&priv->state_lock);
3228
3229 priv->channels.params.vlan_strip_disable = !enable;
3230 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3231 goto unlock;
3232
3233 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3234 if (err)
3235 priv->channels.params.vlan_strip_disable = enable;
3236
3237 unlock:
3238 mutex_unlock(&priv->state_lock);
3239
3240 return err;
3241 }
3242
3243 #ifdef CONFIG_RFS_ACCEL
3244 static int set_feature_arfs(struct net_device *netdev, bool enable)
3245 {
3246 struct mlx5e_priv *priv = netdev_priv(netdev);
3247 int err;
3248
3249 if (enable)
3250 err = mlx5e_arfs_enable(priv);
3251 else
3252 err = mlx5e_arfs_disable(priv);
3253
3254 return err;
3255 }
3256 #endif
3257
3258 static int mlx5e_handle_feature(struct net_device *netdev,
3259 netdev_features_t wanted_features,
3260 netdev_features_t feature,
3261 mlx5e_feature_handler feature_handler)
3262 {
3263 netdev_features_t changes = wanted_features ^ netdev->features;
3264 bool enable = !!(wanted_features & feature);
3265 int err;
3266
3267 if (!(changes & feature))
3268 return 0;
3269
3270 err = feature_handler(netdev, enable);
3271 if (err) {
3272 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
3273 enable ? "Enable" : "Disable", feature, err);
3274 return err;
3275 }
3276
3277 MLX5E_SET_FEATURE(netdev, feature, enable);
3278 return 0;
3279 }
3280
3281 static int mlx5e_set_features(struct net_device *netdev,
3282 netdev_features_t features)
3283 {
3284 int err;
3285
3286 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3287 set_feature_lro);
3288 err |= mlx5e_handle_feature(netdev, features,
3289 NETIF_F_HW_VLAN_CTAG_FILTER,
3290 set_feature_vlan_filter);
3291 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3292 set_feature_tc_num_filters);
3293 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3294 set_feature_rx_all);
3295 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3296 set_feature_rx_fcs);
3297 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3298 set_feature_rx_vlan);
3299 #ifdef CONFIG_RFS_ACCEL
3300 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3301 set_feature_arfs);
3302 #endif
3303
3304 return err ? -EINVAL : 0;
3305 }
3306
3307 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3308 {
3309 struct mlx5e_priv *priv = netdev_priv(netdev);
3310 struct mlx5e_channels new_channels = {};
3311 int curr_mtu;
3312 int err = 0;
3313 bool reset;
3314
3315 mutex_lock(&priv->state_lock);
3316
3317 reset = !priv->channels.params.lro_en &&
3318 (priv->channels.params.rq_wq_type !=
3319 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3320
3321 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3322
3323 curr_mtu = netdev->mtu;
3324 netdev->mtu = new_mtu;
3325
3326 if (!reset) {
3327 mlx5e_set_dev_port_mtu(priv);
3328 goto out;
3329 }
3330
3331 new_channels.params = priv->channels.params;
3332 err = mlx5e_open_channels(priv, &new_channels);
3333 if (err) {
3334 netdev->mtu = curr_mtu;
3335 goto out;
3336 }
3337
3338 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3339
3340 out:
3341 mutex_unlock(&priv->state_lock);
3342 return err;
3343 }
3344
3345 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3346 {
3347 struct mlx5e_priv *priv = netdev_priv(dev);
3348
3349 switch (cmd) {
3350 case SIOCSHWTSTAMP:
3351 return mlx5e_hwstamp_set(priv, ifr);
3352 case SIOCGHWTSTAMP:
3353 return mlx5e_hwstamp_get(priv, ifr);
3354 default:
3355 return -EOPNOTSUPP;
3356 }
3357 }
3358
3359 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3360 {
3361 struct mlx5e_priv *priv = netdev_priv(dev);
3362 struct mlx5_core_dev *mdev = priv->mdev;
3363
3364 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3365 }
3366
3367 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3368 __be16 vlan_proto)
3369 {
3370 struct mlx5e_priv *priv = netdev_priv(dev);
3371 struct mlx5_core_dev *mdev = priv->mdev;
3372
3373 if (vlan_proto != htons(ETH_P_8021Q))
3374 return -EPROTONOSUPPORT;
3375
3376 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3377 vlan, qos);
3378 }
3379
3380 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3381 {
3382 struct mlx5e_priv *priv = netdev_priv(dev);
3383 struct mlx5_core_dev *mdev = priv->mdev;
3384
3385 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3386 }
3387
3388 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3389 {
3390 struct mlx5e_priv *priv = netdev_priv(dev);
3391 struct mlx5_core_dev *mdev = priv->mdev;
3392
3393 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3394 }
3395
3396 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3397 int max_tx_rate)
3398 {
3399 struct mlx5e_priv *priv = netdev_priv(dev);
3400 struct mlx5_core_dev *mdev = priv->mdev;
3401
3402 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3403 max_tx_rate, min_tx_rate);
3404 }
3405
3406 static int mlx5_vport_link2ifla(u8 esw_link)
3407 {
3408 switch (esw_link) {
3409 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3410 return IFLA_VF_LINK_STATE_DISABLE;
3411 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3412 return IFLA_VF_LINK_STATE_ENABLE;
3413 }
3414 return IFLA_VF_LINK_STATE_AUTO;
3415 }
3416
3417 static int mlx5_ifla_link2vport(u8 ifla_link)
3418 {
3419 switch (ifla_link) {
3420 case IFLA_VF_LINK_STATE_DISABLE:
3421 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3422 case IFLA_VF_LINK_STATE_ENABLE:
3423 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3424 }
3425 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3426 }
3427
3428 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3429 int link_state)
3430 {
3431 struct mlx5e_priv *priv = netdev_priv(dev);
3432 struct mlx5_core_dev *mdev = priv->mdev;
3433
3434 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3435 mlx5_ifla_link2vport(link_state));
3436 }
3437
3438 static int mlx5e_get_vf_config(struct net_device *dev,
3439 int vf, struct ifla_vf_info *ivi)
3440 {
3441 struct mlx5e_priv *priv = netdev_priv(dev);
3442 struct mlx5_core_dev *mdev = priv->mdev;
3443 int err;
3444
3445 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3446 if (err)
3447 return err;
3448 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3449 return 0;
3450 }
3451
3452 static int mlx5e_get_vf_stats(struct net_device *dev,
3453 int vf, struct ifla_vf_stats *vf_stats)
3454 {
3455 struct mlx5e_priv *priv = netdev_priv(dev);
3456 struct mlx5_core_dev *mdev = priv->mdev;
3457
3458 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3459 vf_stats);
3460 }
3461
3462 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3463 struct udp_tunnel_info *ti)
3464 {
3465 struct mlx5e_priv *priv = netdev_priv(netdev);
3466
3467 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3468 return;
3469
3470 if (!mlx5e_vxlan_allowed(priv->mdev))
3471 return;
3472
3473 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3474 }
3475
3476 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3477 struct udp_tunnel_info *ti)
3478 {
3479 struct mlx5e_priv *priv = netdev_priv(netdev);
3480
3481 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3482 return;
3483
3484 if (!mlx5e_vxlan_allowed(priv->mdev))
3485 return;
3486
3487 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3488 }
3489
3490 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3491 struct sk_buff *skb,
3492 netdev_features_t features)
3493 {
3494 struct udphdr *udph;
3495 u16 proto;
3496 u16 port = 0;
3497
3498 switch (vlan_get_protocol(skb)) {
3499 case htons(ETH_P_IP):
3500 proto = ip_hdr(skb)->protocol;
3501 break;
3502 case htons(ETH_P_IPV6):
3503 proto = ipv6_hdr(skb)->nexthdr;
3504 break;
3505 default:
3506 goto out;
3507 }
3508
3509 if (proto == IPPROTO_UDP) {
3510 udph = udp_hdr(skb);
3511 port = be16_to_cpu(udph->dest);
3512 }
3513
3514 /* Verify if UDP port is being offloaded by HW */
3515 if (port && mlx5e_vxlan_lookup_port(priv, port))
3516 return features;
3517
3518 out:
3519 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3520 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3521 }
3522
3523 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3524 struct net_device *netdev,
3525 netdev_features_t features)
3526 {
3527 struct mlx5e_priv *priv = netdev_priv(netdev);
3528
3529 features = vlan_features_check(skb, features);
3530 features = vxlan_features_check(skb, features);
3531
3532 #ifdef CONFIG_MLX5_EN_IPSEC
3533 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3534 return features;
3535 #endif
3536
3537 /* Validate if the tunneled packet is being offloaded by HW */
3538 if (skb->encapsulation &&
3539 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3540 return mlx5e_vxlan_features_check(priv, skb, features);
3541
3542 return features;
3543 }
3544
3545 static void mlx5e_tx_timeout(struct net_device *dev)
3546 {
3547 struct mlx5e_priv *priv = netdev_priv(dev);
3548 bool sched_work = false;
3549 int i;
3550
3551 netdev_err(dev, "TX timeout detected\n");
3552
3553 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3554 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3555
3556 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3557 continue;
3558 sched_work = true;
3559 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3560 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3561 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3562 }
3563
3564 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3565 schedule_work(&priv->tx_timeout_work);
3566 }
3567
3568 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3569 {
3570 struct mlx5e_priv *priv = netdev_priv(netdev);
3571 struct bpf_prog *old_prog;
3572 int err = 0;
3573 bool reset, was_opened;
3574 int i;
3575
3576 mutex_lock(&priv->state_lock);
3577
3578 if ((netdev->features & NETIF_F_LRO) && prog) {
3579 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3580 err = -EINVAL;
3581 goto unlock;
3582 }
3583
3584 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3585 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3586 err = -EINVAL;
3587 goto unlock;
3588 }
3589
3590 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3591 /* no need for full reset when exchanging programs */
3592 reset = (!priv->channels.params.xdp_prog || !prog);
3593
3594 if (was_opened && reset)
3595 mlx5e_close_locked(netdev);
3596 if (was_opened && !reset) {
3597 /* num_channels is invariant here, so we can take the
3598 * batched reference right upfront.
3599 */
3600 prog = bpf_prog_add(prog, priv->channels.num);
3601 if (IS_ERR(prog)) {
3602 err = PTR_ERR(prog);
3603 goto unlock;
3604 }
3605 }
3606
3607 /* exchange programs, extra prog reference we got from caller
3608 * as long as we don't fail from this point onwards.
3609 */
3610 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3611 if (old_prog)
3612 bpf_prog_put(old_prog);
3613
3614 if (reset) /* change RQ type according to priv->xdp_prog */
3615 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
3616
3617 if (was_opened && reset)
3618 mlx5e_open_locked(netdev);
3619
3620 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3621 goto unlock;
3622
3623 /* exchanging programs w/o reset, we update ref counts on behalf
3624 * of the channels RQs here.
3625 */
3626 for (i = 0; i < priv->channels.num; i++) {
3627 struct mlx5e_channel *c = priv->channels.c[i];
3628
3629 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3630 napi_synchronize(&c->napi);
3631 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3632
3633 old_prog = xchg(&c->rq.xdp_prog, prog);
3634
3635 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3636 /* napi_schedule in case we have missed anything */
3637 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3638 napi_schedule(&c->napi);
3639
3640 if (old_prog)
3641 bpf_prog_put(old_prog);
3642 }
3643
3644 unlock:
3645 mutex_unlock(&priv->state_lock);
3646 return err;
3647 }
3648
3649 static u32 mlx5e_xdp_query(struct net_device *dev)
3650 {
3651 struct mlx5e_priv *priv = netdev_priv(dev);
3652 const struct bpf_prog *xdp_prog;
3653 u32 prog_id = 0;
3654
3655 mutex_lock(&priv->state_lock);
3656 xdp_prog = priv->channels.params.xdp_prog;
3657 if (xdp_prog)
3658 prog_id = xdp_prog->aux->id;
3659 mutex_unlock(&priv->state_lock);
3660
3661 return prog_id;
3662 }
3663
3664 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3665 {
3666 switch (xdp->command) {
3667 case XDP_SETUP_PROG:
3668 return mlx5e_xdp_set(dev, xdp->prog);
3669 case XDP_QUERY_PROG:
3670 xdp->prog_id = mlx5e_xdp_query(dev);
3671 xdp->prog_attached = !!xdp->prog_id;
3672 return 0;
3673 default:
3674 return -EINVAL;
3675 }
3676 }
3677
3678 #ifdef CONFIG_NET_POLL_CONTROLLER
3679 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3680 * reenabling interrupts.
3681 */
3682 static void mlx5e_netpoll(struct net_device *dev)
3683 {
3684 struct mlx5e_priv *priv = netdev_priv(dev);
3685 struct mlx5e_channels *chs = &priv->channels;
3686
3687 int i;
3688
3689 for (i = 0; i < chs->num; i++)
3690 napi_schedule(&chs->c[i]->napi);
3691 }
3692 #endif
3693
3694 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3695 .ndo_open = mlx5e_open,
3696 .ndo_stop = mlx5e_close,
3697 .ndo_start_xmit = mlx5e_xmit,
3698 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3699 .ndo_select_queue = mlx5e_select_queue,
3700 .ndo_get_stats64 = mlx5e_get_stats,
3701 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3702 .ndo_set_mac_address = mlx5e_set_mac,
3703 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3704 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3705 .ndo_set_features = mlx5e_set_features,
3706 .ndo_change_mtu = mlx5e_change_mtu,
3707 .ndo_do_ioctl = mlx5e_ioctl,
3708 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3709 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3710 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3711 .ndo_features_check = mlx5e_features_check,
3712 #ifdef CONFIG_RFS_ACCEL
3713 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3714 #endif
3715 .ndo_tx_timeout = mlx5e_tx_timeout,
3716 .ndo_xdp = mlx5e_xdp,
3717 #ifdef CONFIG_NET_POLL_CONTROLLER
3718 .ndo_poll_controller = mlx5e_netpoll,
3719 #endif
3720 };
3721
3722 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3723 .ndo_open = mlx5e_open,
3724 .ndo_stop = mlx5e_close,
3725 .ndo_start_xmit = mlx5e_xmit,
3726 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3727 .ndo_select_queue = mlx5e_select_queue,
3728 .ndo_get_stats64 = mlx5e_get_stats,
3729 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3730 .ndo_set_mac_address = mlx5e_set_mac,
3731 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3732 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3733 .ndo_set_features = mlx5e_set_features,
3734 .ndo_change_mtu = mlx5e_change_mtu,
3735 .ndo_do_ioctl = mlx5e_ioctl,
3736 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3737 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3738 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3739 .ndo_features_check = mlx5e_features_check,
3740 #ifdef CONFIG_RFS_ACCEL
3741 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3742 #endif
3743 .ndo_tx_timeout = mlx5e_tx_timeout,
3744 .ndo_xdp = mlx5e_xdp,
3745 #ifdef CONFIG_NET_POLL_CONTROLLER
3746 .ndo_poll_controller = mlx5e_netpoll,
3747 #endif
3748 /* SRIOV E-Switch NDOs */
3749 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3750 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
3751 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
3752 .ndo_set_vf_trust = mlx5e_set_vf_trust,
3753 .ndo_set_vf_rate = mlx5e_set_vf_rate,
3754 .ndo_get_vf_config = mlx5e_get_vf_config,
3755 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3756 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3757 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3758 .ndo_get_offload_stats = mlx5e_get_offload_stats,
3759 };
3760
3761 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3762 {
3763 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3764 return -EOPNOTSUPP;
3765 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3766 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3767 !MLX5_CAP_ETH(mdev, csum_cap) ||
3768 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3769 !MLX5_CAP_ETH(mdev, vlan_cap) ||
3770 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3771 MLX5_CAP_FLOWTABLE(mdev,
3772 flow_table_properties_nic_receive.max_ft_level)
3773 < 3) {
3774 mlx5_core_warn(mdev,
3775 "Not creating net device, some required device capabilities are missing\n");
3776 return -EOPNOTSUPP;
3777 }
3778 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3779 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3780 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3781 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
3782
3783 return 0;
3784 }
3785
3786 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3787 {
3788 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3789
3790 return bf_buf_size -
3791 sizeof(struct mlx5e_tx_wqe) +
3792 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3793 }
3794
3795 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3796 u32 *indirection_rqt, int len,
3797 int num_channels)
3798 {
3799 int node = mdev->priv.numa_node;
3800 int node_num_of_cores;
3801 int i;
3802
3803 if (node == -1)
3804 node = first_online_node;
3805
3806 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3807
3808 if (node_num_of_cores)
3809 num_channels = min_t(int, num_channels, node_num_of_cores);
3810
3811 for (i = 0; i < len; i++)
3812 indirection_rqt[i] = i % num_channels;
3813 }
3814
3815 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3816 {
3817 enum pcie_link_width width;
3818 enum pci_bus_speed speed;
3819 int err = 0;
3820
3821 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3822 if (err)
3823 return err;
3824
3825 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3826 return -EINVAL;
3827
3828 switch (speed) {
3829 case PCIE_SPEED_2_5GT:
3830 *pci_bw = 2500 * width;
3831 break;
3832 case PCIE_SPEED_5_0GT:
3833 *pci_bw = 5000 * width;
3834 break;
3835 case PCIE_SPEED_8_0GT:
3836 *pci_bw = 8000 * width;
3837 break;
3838 default:
3839 return -EINVAL;
3840 }
3841
3842 return 0;
3843 }
3844
3845 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3846 {
3847 return (link_speed && pci_bw &&
3848 (pci_bw < 40000) && (pci_bw < link_speed));
3849 }
3850
3851 static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
3852 {
3853 return !(link_speed && pci_bw &&
3854 (pci_bw <= 16000) && (pci_bw < link_speed));
3855 }
3856
3857 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3858 {
3859 params->rx_cq_period_mode = cq_period_mode;
3860
3861 params->rx_cq_moderation.pkts =
3862 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3863 params->rx_cq_moderation.usec =
3864 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3865
3866 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3867 params->rx_cq_moderation.usec =
3868 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3869
3870 if (params->rx_am_enabled)
3871 params->rx_cq_moderation =
3872 mlx5e_am_get_def_profile(params->rx_cq_period_mode);
3873
3874 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3875 params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3876 }
3877
3878 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3879 {
3880 int i;
3881
3882 /* The supported periods are organized in ascending order */
3883 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3884 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3885 break;
3886
3887 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3888 }
3889
3890 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3891 struct mlx5e_params *params,
3892 u16 max_channels)
3893 {
3894 u8 cq_period_mode = 0;
3895 u32 link_speed = 0;
3896 u32 pci_bw = 0;
3897
3898 params->num_channels = max_channels;
3899 params->num_tc = 1;
3900
3901 mlx5e_get_max_linkspeed(mdev, &link_speed);
3902 mlx5e_get_pci_bw(mdev, &pci_bw);
3903 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3904 link_speed, pci_bw);
3905
3906 /* SQ */
3907 params->log_sq_size = is_kdump_kernel() ?
3908 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3909 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3910
3911 /* set CQE compression */
3912 params->rx_cqe_compress_def = false;
3913 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3914 MLX5_CAP_GEN(mdev, vport_group_manager))
3915 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
3916
3917 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3918
3919 /* RQ */
3920 mlx5e_set_rq_params(mdev, params);
3921
3922 /* HW LRO */
3923
3924 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
3925 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3926 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
3927 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3928
3929 /* CQ moderation params */
3930 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3931 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3932 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3933 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3934 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
3935
3936 params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3937 params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3938
3939 /* TX inline */
3940 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3941 mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
3942 if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
3943 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
3944 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
3945
3946 /* RSS */
3947 params->rss_hfunc = ETH_RSS_HASH_XOR;
3948 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3949 mlx5e_build_default_indir_rqt(mdev, params->indirection_rqt,
3950 MLX5E_INDIR_RQT_SIZE, max_channels);
3951 }
3952
3953 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3954 struct net_device *netdev,
3955 const struct mlx5e_profile *profile,
3956 void *ppriv)
3957 {
3958 struct mlx5e_priv *priv = netdev_priv(netdev);
3959
3960 priv->mdev = mdev;
3961 priv->netdev = netdev;
3962 priv->profile = profile;
3963 priv->ppriv = ppriv;
3964 priv->hard_mtu = MLX5E_ETH_HARD_MTU;
3965
3966 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
3967
3968 mutex_init(&priv->state_lock);
3969
3970 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3971 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3972 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3973 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3974 }
3975
3976 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3977 {
3978 struct mlx5e_priv *priv = netdev_priv(netdev);
3979
3980 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3981 if (is_zero_ether_addr(netdev->dev_addr) &&
3982 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3983 eth_hw_addr_random(netdev);
3984 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3985 }
3986 }
3987
3988 static const struct switchdev_ops mlx5e_switchdev_ops = {
3989 .switchdev_port_attr_get = mlx5e_attr_get,
3990 };
3991
3992 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3993 {
3994 struct mlx5e_priv *priv = netdev_priv(netdev);
3995 struct mlx5_core_dev *mdev = priv->mdev;
3996 bool fcs_supported;
3997 bool fcs_enabled;
3998
3999 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4000
4001 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
4002 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
4003 #ifdef CONFIG_MLX5_CORE_EN_DCB
4004 if (MLX5_CAP_GEN(mdev, qos))
4005 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4006 #endif
4007 } else {
4008 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
4009 }
4010
4011 netdev->watchdog_timeo = 15 * HZ;
4012
4013 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4014
4015 netdev->vlan_features |= NETIF_F_SG;
4016 netdev->vlan_features |= NETIF_F_IP_CSUM;
4017 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4018 netdev->vlan_features |= NETIF_F_GRO;
4019 netdev->vlan_features |= NETIF_F_TSO;
4020 netdev->vlan_features |= NETIF_F_TSO6;
4021 netdev->vlan_features |= NETIF_F_RXCSUM;
4022 netdev->vlan_features |= NETIF_F_RXHASH;
4023
4024 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4025 netdev->vlan_features |= NETIF_F_LRO;
4026
4027 netdev->hw_features = netdev->vlan_features;
4028 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4029 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4030 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4031
4032 if (mlx5e_vxlan_allowed(mdev)) {
4033 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4034 NETIF_F_GSO_UDP_TUNNEL_CSUM |
4035 NETIF_F_GSO_PARTIAL;
4036 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4037 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4038 netdev->hw_enc_features |= NETIF_F_TSO;
4039 netdev->hw_enc_features |= NETIF_F_TSO6;
4040 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4041 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
4042 NETIF_F_GSO_PARTIAL;
4043 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4044 }
4045
4046 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4047
4048 if (fcs_supported)
4049 netdev->hw_features |= NETIF_F_RXALL;
4050
4051 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4052 netdev->hw_features |= NETIF_F_RXFCS;
4053
4054 netdev->features = netdev->hw_features;
4055 if (!priv->channels.params.lro_en)
4056 netdev->features &= ~NETIF_F_LRO;
4057
4058 if (fcs_enabled)
4059 netdev->features &= ~NETIF_F_RXALL;
4060
4061 if (!priv->channels.params.scatter_fcs_en)
4062 netdev->features &= ~NETIF_F_RXFCS;
4063
4064 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4065 if (FT_CAP(flow_modify_en) &&
4066 FT_CAP(modify_root) &&
4067 FT_CAP(identified_miss_table_mode) &&
4068 FT_CAP(flow_table_modify)) {
4069 netdev->hw_features |= NETIF_F_HW_TC;
4070 #ifdef CONFIG_RFS_ACCEL
4071 netdev->hw_features |= NETIF_F_NTUPLE;
4072 #endif
4073 }
4074
4075 netdev->features |= NETIF_F_HIGHDMA;
4076
4077 netdev->priv_flags |= IFF_UNICAST_FLT;
4078
4079 mlx5e_set_netdev_dev_addr(netdev);
4080
4081 #ifdef CONFIG_NET_SWITCHDEV
4082 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4083 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4084 #endif
4085
4086 mlx5e_ipsec_build_netdev(priv);
4087 }
4088
4089 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4090 {
4091 struct mlx5_core_dev *mdev = priv->mdev;
4092 int err;
4093
4094 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4095 if (err) {
4096 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4097 priv->q_counter = 0;
4098 }
4099 }
4100
4101 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4102 {
4103 if (!priv->q_counter)
4104 return;
4105
4106 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4107 }
4108
4109 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4110 struct net_device *netdev,
4111 const struct mlx5e_profile *profile,
4112 void *ppriv)
4113 {
4114 struct mlx5e_priv *priv = netdev_priv(netdev);
4115 int err;
4116
4117 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4118 err = mlx5e_ipsec_init(priv);
4119 if (err)
4120 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4121 mlx5e_build_nic_netdev(netdev);
4122 mlx5e_vxlan_init(priv);
4123 }
4124
4125 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4126 {
4127 mlx5e_ipsec_cleanup(priv);
4128 mlx5e_vxlan_cleanup(priv);
4129
4130 if (priv->channels.params.xdp_prog)
4131 bpf_prog_put(priv->channels.params.xdp_prog);
4132 }
4133
4134 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4135 {
4136 struct mlx5_core_dev *mdev = priv->mdev;
4137 int err;
4138
4139 err = mlx5e_create_indirect_rqt(priv);
4140 if (err)
4141 return err;
4142
4143 err = mlx5e_create_direct_rqts(priv);
4144 if (err)
4145 goto err_destroy_indirect_rqts;
4146
4147 err = mlx5e_create_indirect_tirs(priv);
4148 if (err)
4149 goto err_destroy_direct_rqts;
4150
4151 err = mlx5e_create_direct_tirs(priv);
4152 if (err)
4153 goto err_destroy_indirect_tirs;
4154
4155 err = mlx5e_create_flow_steering(priv);
4156 if (err) {
4157 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4158 goto err_destroy_direct_tirs;
4159 }
4160
4161 err = mlx5e_tc_init(priv);
4162 if (err)
4163 goto err_destroy_flow_steering;
4164
4165 return 0;
4166
4167 err_destroy_flow_steering:
4168 mlx5e_destroy_flow_steering(priv);
4169 err_destroy_direct_tirs:
4170 mlx5e_destroy_direct_tirs(priv);
4171 err_destroy_indirect_tirs:
4172 mlx5e_destroy_indirect_tirs(priv);
4173 err_destroy_direct_rqts:
4174 mlx5e_destroy_direct_rqts(priv);
4175 err_destroy_indirect_rqts:
4176 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4177 return err;
4178 }
4179
4180 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4181 {
4182 mlx5e_tc_cleanup(priv);
4183 mlx5e_destroy_flow_steering(priv);
4184 mlx5e_destroy_direct_tirs(priv);
4185 mlx5e_destroy_indirect_tirs(priv);
4186 mlx5e_destroy_direct_rqts(priv);
4187 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4188 }
4189
4190 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4191 {
4192 int err;
4193
4194 err = mlx5e_create_tises(priv);
4195 if (err) {
4196 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4197 return err;
4198 }
4199
4200 #ifdef CONFIG_MLX5_CORE_EN_DCB
4201 mlx5e_dcbnl_initialize(priv);
4202 #endif
4203 return 0;
4204 }
4205
4206 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4207 {
4208 struct net_device *netdev = priv->netdev;
4209 struct mlx5_core_dev *mdev = priv->mdev;
4210 u16 max_mtu;
4211
4212 mlx5e_init_l2_addr(priv);
4213
4214 /* MTU range: 68 - hw-specific max */
4215 netdev->min_mtu = ETH_MIN_MTU;
4216 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4217 netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
4218 mlx5e_set_dev_port_mtu(priv);
4219
4220 mlx5_lag_add(mdev, netdev);
4221
4222 mlx5e_enable_async_events(priv);
4223
4224 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4225 mlx5e_register_vport_reps(priv);
4226
4227 if (netdev->reg_state != NETREG_REGISTERED)
4228 return;
4229
4230 /* Device already registered: sync netdev system state */
4231 if (mlx5e_vxlan_allowed(mdev)) {
4232 rtnl_lock();
4233 udp_tunnel_get_rx_info(netdev);
4234 rtnl_unlock();
4235 }
4236
4237 queue_work(priv->wq, &priv->set_rx_mode_work);
4238
4239 rtnl_lock();
4240 if (netif_running(netdev))
4241 mlx5e_open(netdev);
4242 netif_device_attach(netdev);
4243 rtnl_unlock();
4244 }
4245
4246 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4247 {
4248 struct mlx5_core_dev *mdev = priv->mdev;
4249
4250 rtnl_lock();
4251 if (netif_running(priv->netdev))
4252 mlx5e_close(priv->netdev);
4253 netif_device_detach(priv->netdev);
4254 rtnl_unlock();
4255
4256 queue_work(priv->wq, &priv->set_rx_mode_work);
4257
4258 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4259 mlx5e_unregister_vport_reps(priv);
4260
4261 mlx5e_disable_async_events(priv);
4262 mlx5_lag_remove(mdev);
4263 }
4264
4265 static const struct mlx5e_profile mlx5e_nic_profile = {
4266 .init = mlx5e_nic_init,
4267 .cleanup = mlx5e_nic_cleanup,
4268 .init_rx = mlx5e_init_nic_rx,
4269 .cleanup_rx = mlx5e_cleanup_nic_rx,
4270 .init_tx = mlx5e_init_nic_tx,
4271 .cleanup_tx = mlx5e_cleanup_nic_tx,
4272 .enable = mlx5e_nic_enable,
4273 .disable = mlx5e_nic_disable,
4274 .update_stats = mlx5e_update_ndo_stats,
4275 .max_nch = mlx5e_get_max_num_channels,
4276 .update_carrier = mlx5e_update_carrier,
4277 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4278 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4279 .max_tc = MLX5E_MAX_NUM_TC,
4280 };
4281
4282 /* mlx5e generic netdev management API (move to en_common.c) */
4283
4284 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4285 const struct mlx5e_profile *profile,
4286 void *ppriv)
4287 {
4288 int nch = profile->max_nch(mdev);
4289 struct net_device *netdev;
4290 struct mlx5e_priv *priv;
4291
4292 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4293 nch * profile->max_tc,
4294 nch);
4295 if (!netdev) {
4296 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4297 return NULL;
4298 }
4299
4300 #ifdef CONFIG_RFS_ACCEL
4301 netdev->rx_cpu_rmap = mdev->rmap;
4302 #endif
4303
4304 profile->init(mdev, netdev, profile, ppriv);
4305
4306 netif_carrier_off(netdev);
4307
4308 priv = netdev_priv(netdev);
4309
4310 priv->wq = create_singlethread_workqueue("mlx5e");
4311 if (!priv->wq)
4312 goto err_cleanup_nic;
4313
4314 return netdev;
4315
4316 err_cleanup_nic:
4317 if (profile->cleanup)
4318 profile->cleanup(priv);
4319 free_netdev(netdev);
4320
4321 return NULL;
4322 }
4323
4324 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4325 {
4326 struct mlx5_core_dev *mdev = priv->mdev;
4327 const struct mlx5e_profile *profile;
4328 int err;
4329
4330 profile = priv->profile;
4331 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4332
4333 err = profile->init_tx(priv);
4334 if (err)
4335 goto out;
4336
4337 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
4338 if (err) {
4339 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4340 goto err_cleanup_tx;
4341 }
4342
4343 err = profile->init_rx(priv);
4344 if (err)
4345 goto err_close_drop_rq;
4346
4347 mlx5e_create_q_counter(priv);
4348
4349 if (profile->enable)
4350 profile->enable(priv);
4351
4352 return 0;
4353
4354 err_close_drop_rq:
4355 mlx5e_close_drop_rq(&priv->drop_rq);
4356
4357 err_cleanup_tx:
4358 profile->cleanup_tx(priv);
4359
4360 out:
4361 return err;
4362 }
4363
4364 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4365 {
4366 const struct mlx5e_profile *profile = priv->profile;
4367
4368 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4369
4370 if (profile->disable)
4371 profile->disable(priv);
4372 flush_workqueue(priv->wq);
4373
4374 mlx5e_destroy_q_counter(priv);
4375 profile->cleanup_rx(priv);
4376 mlx5e_close_drop_rq(&priv->drop_rq);
4377 profile->cleanup_tx(priv);
4378 cancel_delayed_work_sync(&priv->update_stats_work);
4379 }
4380
4381 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4382 {
4383 const struct mlx5e_profile *profile = priv->profile;
4384 struct net_device *netdev = priv->netdev;
4385
4386 destroy_workqueue(priv->wq);
4387 if (profile->cleanup)
4388 profile->cleanup(priv);
4389 free_netdev(netdev);
4390 }
4391
4392 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4393 * hardware contexts and to connect it to the current netdev.
4394 */
4395 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4396 {
4397 struct mlx5e_priv *priv = vpriv;
4398 struct net_device *netdev = priv->netdev;
4399 int err;
4400
4401 if (netif_device_present(netdev))
4402 return 0;
4403
4404 err = mlx5e_create_mdev_resources(mdev);
4405 if (err)
4406 return err;
4407
4408 err = mlx5e_attach_netdev(priv);
4409 if (err) {
4410 mlx5e_destroy_mdev_resources(mdev);
4411 return err;
4412 }
4413
4414 return 0;
4415 }
4416
4417 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4418 {
4419 struct mlx5e_priv *priv = vpriv;
4420 struct net_device *netdev = priv->netdev;
4421
4422 if (!netif_device_present(netdev))
4423 return;
4424
4425 mlx5e_detach_netdev(priv);
4426 mlx5e_destroy_mdev_resources(mdev);
4427 }
4428
4429 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4430 {
4431 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4432 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4433 struct mlx5e_rep_priv *rpriv = NULL;
4434 void *priv;
4435 int vport;
4436 int err;
4437 struct net_device *netdev;
4438
4439 err = mlx5e_check_required_hca_cap(mdev);
4440 if (err)
4441 return NULL;
4442
4443 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
4444 rpriv = kzalloc(sizeof(*rpriv), GFP_KERNEL);
4445 if (!rpriv) {
4446 mlx5_core_warn(mdev,
4447 "Not creating net device, Failed to alloc rep priv data\n");
4448 return NULL;
4449 }
4450 rpriv->rep = &esw->offloads.vport_reps[0];
4451 }
4452
4453 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4454 if (!netdev) {
4455 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4456 goto err_unregister_reps;
4457 }
4458
4459 priv = netdev_priv(netdev);
4460
4461 err = mlx5e_attach(mdev, priv);
4462 if (err) {
4463 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4464 goto err_destroy_netdev;
4465 }
4466
4467 err = register_netdev(netdev);
4468 if (err) {
4469 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4470 goto err_detach;
4471 }
4472
4473 return priv;
4474
4475 err_detach:
4476 mlx5e_detach(mdev, priv);
4477
4478 err_destroy_netdev:
4479 mlx5e_destroy_netdev(priv);
4480
4481 err_unregister_reps:
4482 for (vport = 1; vport < total_vfs; vport++)
4483 mlx5_eswitch_unregister_vport_rep(esw, vport);
4484
4485 kfree(rpriv);
4486 return NULL;
4487 }
4488
4489 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4490 {
4491 struct mlx5e_priv *priv = vpriv;
4492 void *ppriv = priv->ppriv;
4493
4494 unregister_netdev(priv->netdev);
4495 mlx5e_detach(mdev, vpriv);
4496 mlx5e_destroy_netdev(priv);
4497 kfree(ppriv);
4498 }
4499
4500 static void *mlx5e_get_netdev(void *vpriv)
4501 {
4502 struct mlx5e_priv *priv = vpriv;
4503
4504 return priv->netdev;
4505 }
4506
4507 static struct mlx5_interface mlx5e_interface = {
4508 .add = mlx5e_add,
4509 .remove = mlx5e_remove,
4510 .attach = mlx5e_attach,
4511 .detach = mlx5e_detach,
4512 .event = mlx5e_async_event,
4513 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4514 .get_dev = mlx5e_get_netdev,
4515 };
4516
4517 void mlx5e_init(void)
4518 {
4519 mlx5e_ipsec_build_inverse_table();
4520 mlx5e_build_ptys2ethtool_map();
4521 mlx5_register_interface(&mlx5e_interface);
4522 }
4523
4524 void mlx5e_cleanup(void)
4525 {
4526 mlx5_unregister_interface(&mlx5e_interface);
4527 }
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