]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blob - drivers/net/ethernet/mellanox/mlx5/core/en_main.c
projects / mirror_ubuntu-focal-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ASoC: tlv320aic31xx: Reset registers during power up
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include "eswitch.h"
39 #include "en.h"
40 #include "en_tc.h"
41 #include "en_rep.h"
42 #include "en_accel/ipsec.h"
43 #include "en_accel/ipsec_rxtx.h"
44 #include "accel/ipsec.h"
45 #include "vxlan.h"
46
47 struct mlx5e_rq_param {
48 u32 rqc[MLX5_ST_SZ_DW(rqc)];
49 struct mlx5_wq_param wq;
50 };
51
52 struct mlx5e_sq_param {
53 u32 sqc[MLX5_ST_SZ_DW(sqc)];
54 struct mlx5_wq_param wq;
55 };
56
57 struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
61 u8 cq_period_mode;
62 };
63
64 struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
67 struct mlx5e_sq_param xdp_sq;
68 struct mlx5e_sq_param icosq;
69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
71 struct mlx5e_cq_param icosq_cq;
72 };
73
74 static int mlx5e_get_node(struct mlx5e_priv *priv, int ix)
75 {
76 return pci_irq_get_node(priv->mdev->pdev, MLX5_EQ_VEC_COMP_BASE + ix);
77 }
78
79 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
80 {
81 return MLX5_CAP_GEN(mdev, striding_rq) &&
82 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
83 MLX5_CAP_ETH(mdev, reg_umr_sq);
84 }
85
86 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
87 struct mlx5e_params *params, u8 rq_type)
88 {
89 params->rq_wq_type = rq_type;
90 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
91 switch (params->rq_wq_type) {
92 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
93 params->log_rq_size = is_kdump_kernel() ?
94 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
95 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
96 params->mpwqe_log_stride_sz =
97 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
98 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
99 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
100 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
101 params->mpwqe_log_stride_sz;
102 break;
103 default: /* MLX5_WQ_TYPE_LINKED_LIST */
104 params->log_rq_size = is_kdump_kernel() ?
105 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
106 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
107 params->rq_headroom = params->xdp_prog ?
108 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
109 params->rq_headroom += NET_IP_ALIGN;
110
111 /* Extra room needed for build_skb */
112 params->lro_wqe_sz -= params->rq_headroom +
113 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
114 }
115
116 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
117 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
118 BIT(params->log_rq_size),
119 BIT(params->mpwqe_log_stride_sz),
120 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
121 }
122
123 static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
124 {
125 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
126 !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
127 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
128 MLX5_WQ_TYPE_LINKED_LIST;
129 mlx5e_set_rq_type_params(mdev, params, rq_type);
130 }
131
132 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
133 {
134 struct mlx5_core_dev *mdev = priv->mdev;
135 u8 port_state;
136
137 port_state = mlx5_query_vport_state(mdev,
138 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
139 0);
140
141 if (port_state == VPORT_STATE_UP) {
142 netdev_info(priv->netdev, "Link up\n");
143 netif_carrier_on(priv->netdev);
144 } else {
145 netdev_info(priv->netdev, "Link down\n");
146 netif_carrier_off(priv->netdev);
147 }
148 }
149
150 static void mlx5e_update_carrier_work(struct work_struct *work)
151 {
152 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
153 update_carrier_work);
154
155 mutex_lock(&priv->state_lock);
156 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
157 if (priv->profile->update_carrier)
158 priv->profile->update_carrier(priv);
159 mutex_unlock(&priv->state_lock);
160 }
161
162 static void mlx5e_tx_timeout_work(struct work_struct *work)
163 {
164 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
165 tx_timeout_work);
166 int err;
167
168 rtnl_lock();
169 mutex_lock(&priv->state_lock);
170 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
171 goto unlock;
172 mlx5e_close_locked(priv->netdev);
173 err = mlx5e_open_locked(priv->netdev);
174 if (err)
175 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
176 err);
177 unlock:
178 mutex_unlock(&priv->state_lock);
179 rtnl_unlock();
180 }
181
182 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
183 {
184 struct mlx5e_sw_stats temp, *s = &temp;
185 struct mlx5e_rq_stats *rq_stats;
186 struct mlx5e_sq_stats *sq_stats;
187 int i, j;
188
189 memset(s, 0, sizeof(*s));
190 for (i = 0; i < priv->channels.num; i++) {
191 struct mlx5e_channel *c = priv->channels.c[i];
192
193 rq_stats = &c->rq.stats;
194
195 s->rx_packets += rq_stats->packets;
196 s->rx_bytes += rq_stats->bytes;
197 s->rx_lro_packets += rq_stats->lro_packets;
198 s->rx_lro_bytes += rq_stats->lro_bytes;
199 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
200 s->rx_csum_none += rq_stats->csum_none;
201 s->rx_csum_complete += rq_stats->csum_complete;
202 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
203 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
204 s->rx_xdp_drop += rq_stats->xdp_drop;
205 s->rx_xdp_tx += rq_stats->xdp_tx;
206 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
207 s->rx_wqe_err += rq_stats->wqe_err;
208 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
209 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
210 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
211 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
212 s->rx_page_reuse += rq_stats->page_reuse;
213 s->rx_cache_reuse += rq_stats->cache_reuse;
214 s->rx_cache_full += rq_stats->cache_full;
215 s->rx_cache_empty += rq_stats->cache_empty;
216 s->rx_cache_busy += rq_stats->cache_busy;
217 s->rx_cache_waive += rq_stats->cache_waive;
218
219 for (j = 0; j < priv->channels.params.num_tc; j++) {
220 sq_stats = &c->sq[j].stats;
221
222 s->tx_packets += sq_stats->packets;
223 s->tx_bytes += sq_stats->bytes;
224 s->tx_tso_packets += sq_stats->tso_packets;
225 s->tx_tso_bytes += sq_stats->tso_bytes;
226 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
227 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
228 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
229 s->tx_queue_stopped += sq_stats->stopped;
230 s->tx_queue_wake += sq_stats->wake;
231 s->tx_queue_dropped += sq_stats->dropped;
232 s->tx_xmit_more += sq_stats->xmit_more;
233 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
234 s->tx_csum_none += sq_stats->csum_none;
235 s->tx_csum_partial += sq_stats->csum_partial;
236 }
237 }
238
239 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
240 priv->stats.pport.phy_counters,
241 counter_set.phys_layer_cntrs.link_down_events);
242 memcpy(&priv->stats.sw, s, sizeof(*s));
243 }
244
245 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
246 {
247 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
248 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
249 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
250 struct mlx5_core_dev *mdev = priv->mdev;
251
252 MLX5_SET(query_vport_counter_in, in, opcode,
253 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
254 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
255 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
256
257 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
258 }
259
260 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
261 {
262 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
263 struct mlx5_core_dev *mdev = priv->mdev;
264 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
265 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
266 int prio;
267 void *out;
268
269 MLX5_SET(ppcnt_reg, in, local_port, 1);
270
271 out = pstats->IEEE_802_3_counters;
272 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
273 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
274
275 if (!full)
276 return;
277
278 out = pstats->RFC_2863_counters;
279 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
280 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
281
282 out = pstats->RFC_2819_counters;
283 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
284 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
285
286 out = pstats->phy_counters;
287 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
288 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
289
290 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
291 out = pstats->phy_statistical_counters;
292 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
293 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
294 }
295
296 if (MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) {
297 out = pstats->eth_ext_counters;
298 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
299 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
300 }
301
302 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
303 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
304 out = pstats->per_prio_counters[prio];
305 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
306 mlx5_core_access_reg(mdev, in, sz, out, sz,
307 MLX5_REG_PPCNT, 0, 0);
308 }
309 }
310
311 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
312 {
313 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
314 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
315 int err;
316
317 if (!priv->q_counter)
318 return;
319
320 err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
321 if (err)
322 return;
323
324 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
325 }
326
327 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
328 {
329 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
330 struct mlx5_core_dev *mdev = priv->mdev;
331 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
332 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
333 void *out;
334
335 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
336 return;
337
338 out = pcie_stats->pcie_perf_counters;
339 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
340 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
341 }
342
343 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
344 {
345 if (full) {
346 mlx5e_update_pcie_counters(priv);
347 mlx5e_ipsec_update_stats(priv);
348 }
349 mlx5e_update_pport_counters(priv, full);
350 mlx5e_update_vport_counters(priv);
351 mlx5e_update_q_counter(priv);
352 mlx5e_update_sw_counters(priv);
353 }
354
355 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
356 {
357 mlx5e_update_stats(priv, false);
358 }
359
360 void mlx5e_update_stats_work(struct work_struct *work)
361 {
362 struct delayed_work *dwork = to_delayed_work(work);
363 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
364 update_stats_work);
365 mutex_lock(&priv->state_lock);
366 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
367 priv->profile->update_stats(priv);
368 queue_delayed_work(priv->wq, dwork,
369 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
370 }
371 mutex_unlock(&priv->state_lock);
372 }
373
374 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
375 enum mlx5_dev_event event, unsigned long param)
376 {
377 struct mlx5e_priv *priv = vpriv;
378
379 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
380 return;
381
382 switch (event) {
383 case MLX5_DEV_EVENT_PORT_UP:
384 case MLX5_DEV_EVENT_PORT_DOWN:
385 queue_work(priv->wq, &priv->update_carrier_work);
386 break;
387 default:
388 break;
389 }
390 }
391
392 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
393 {
394 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
395 }
396
397 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
398 {
399 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
400 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
401 }
402
403 static inline int mlx5e_get_wqe_mtt_sz(void)
404 {
405 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
406 * To avoid copying garbage after the mtt array, we allocate
407 * a little more.
408 */
409 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
410 MLX5_UMR_MTT_ALIGNMENT);
411 }
412
413 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
414 struct mlx5e_icosq *sq,
415 struct mlx5e_umr_wqe *wqe,
416 u16 ix)
417 {
418 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
419 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
420 struct mlx5_wqe_data_seg *dseg = &wqe->data;
421 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
422 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
423 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
424
425 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
426 ds_cnt);
427 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
428 cseg->imm = rq->mkey_be;
429
430 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
431 ucseg->xlt_octowords =
432 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
433 ucseg->bsf_octowords =
434 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
435 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
436
437 dseg->lkey = sq->mkey_be;
438 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
439 }
440
441 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
442 struct mlx5e_channel *c)
443 {
444 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
445 int mtt_sz = mlx5e_get_wqe_mtt_sz();
446 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
447 int node = mlx5e_get_node(c->priv, c->ix);
448 int i;
449
450 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
451 GFP_KERNEL, node);
452 if (!rq->mpwqe.info)
453 goto err_out;
454
455 /* We allocate more than mtt_sz as we will align the pointer */
456 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz,
457 GFP_KERNEL, node);
458 if (unlikely(!rq->mpwqe.mtt_no_align))
459 goto err_free_wqe_info;
460
461 for (i = 0; i < wq_sz; i++) {
462 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
463
464 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
465 MLX5_UMR_ALIGN);
466 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
467 PCI_DMA_TODEVICE);
468 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
469 goto err_unmap_mtts;
470
471 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
472 }
473
474 return 0;
475
476 err_unmap_mtts:
477 while (--i >= 0) {
478 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
479
480 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
481 PCI_DMA_TODEVICE);
482 }
483 kfree(rq->mpwqe.mtt_no_align);
484 err_free_wqe_info:
485 kfree(rq->mpwqe.info);
486
487 err_out:
488 return -ENOMEM;
489 }
490
491 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
492 {
493 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
494 int mtt_sz = mlx5e_get_wqe_mtt_sz();
495 int i;
496
497 for (i = 0; i < wq_sz; i++) {
498 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
499
500 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
501 PCI_DMA_TODEVICE);
502 }
503 kfree(rq->mpwqe.mtt_no_align);
504 kfree(rq->mpwqe.info);
505 }
506
507 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
508 u64 npages, u8 page_shift,
509 struct mlx5_core_mkey *umr_mkey)
510 {
511 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
512 void *mkc;
513 u32 *in;
514 int err;
515
516 if (!MLX5E_VALID_NUM_MTTS(npages))
517 return -EINVAL;
518
519 in = kvzalloc(inlen, GFP_KERNEL);
520 if (!in)
521 return -ENOMEM;
522
523 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
524
525 MLX5_SET(mkc, mkc, free, 1);
526 MLX5_SET(mkc, mkc, umr_en, 1);
527 MLX5_SET(mkc, mkc, lw, 1);
528 MLX5_SET(mkc, mkc, lr, 1);
529 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
530
531 MLX5_SET(mkc, mkc, qpn, 0xffffff);
532 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
533 MLX5_SET64(mkc, mkc, len, npages << page_shift);
534 MLX5_SET(mkc, mkc, translations_octword_size,
535 MLX5_MTT_OCTW(npages));
536 MLX5_SET(mkc, mkc, log_page_size, page_shift);
537
538 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
539
540 kvfree(in);
541 return err;
542 }
543
544 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
545 {
546 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
547
548 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
549 }
550
551 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
552 struct mlx5e_params *params,
553 struct mlx5e_rq_param *rqp,
554 struct mlx5e_rq *rq)
555 {
556 struct mlx5_core_dev *mdev = c->mdev;
557 void *rqc = rqp->rqc;
558 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
559 u32 byte_count;
560 int npages;
561 int wq_sz;
562 int err;
563 int i;
564
565 rqp->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
566
567 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
568 &rq->wq_ctrl);
569 if (err)
570 return err;
571
572 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
573
574 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
575
576 rq->wq_type = params->rq_wq_type;
577 rq->pdev = c->pdev;
578 rq->netdev = c->netdev;
579 rq->tstamp = c->tstamp;
580 rq->clock = &mdev->clock;
581 rq->channel = c;
582 rq->ix = c->ix;
583 rq->mdev = mdev;
584
585 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
586 if (IS_ERR(rq->xdp_prog)) {
587 err = PTR_ERR(rq->xdp_prog);
588 rq->xdp_prog = NULL;
589 goto err_rq_wq_destroy;
590 }
591
592 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
593 rq->buff.headroom = params->rq_headroom;
594
595 switch (rq->wq_type) {
596 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
597
598 rq->post_wqes = mlx5e_post_rx_mpwqes;
599 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
600
601 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
602 #ifdef CONFIG_MLX5_EN_IPSEC
603 if (MLX5_IPSEC_DEV(mdev)) {
604 err = -EINVAL;
605 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
606 goto err_rq_wq_destroy;
607 }
608 #endif
609 if (!rq->handle_rx_cqe) {
610 err = -EINVAL;
611 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
612 goto err_rq_wq_destroy;
613 }
614
615 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
616 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
617
618 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
619
620 err = mlx5e_create_rq_umr_mkey(mdev, rq);
621 if (err)
622 goto err_rq_wq_destroy;
623 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
624
625 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
626 if (err)
627 goto err_destroy_umr_mkey;
628 break;
629 default: /* MLX5_WQ_TYPE_LINKED_LIST */
630 rq->wqe.frag_info =
631 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
632 GFP_KERNEL,
633 mlx5e_get_node(c->priv, c->ix));
634 if (!rq->wqe.frag_info) {
635 err = -ENOMEM;
636 goto err_rq_wq_destroy;
637 }
638 rq->post_wqes = mlx5e_post_rx_wqes;
639 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
640
641 #ifdef CONFIG_MLX5_EN_IPSEC
642 if (c->priv->ipsec)
643 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
644 else
645 #endif
646 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
647 if (!rq->handle_rx_cqe) {
648 kfree(rq->wqe.frag_info);
649 err = -EINVAL;
650 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
651 goto err_rq_wq_destroy;
652 }
653
654 byte_count = params->lro_en ?
655 params->lro_wqe_sz :
656 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
657 #ifdef CONFIG_MLX5_EN_IPSEC
658 if (MLX5_IPSEC_DEV(mdev))
659 byte_count += MLX5E_METADATA_ETHER_LEN;
660 #endif
661 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
662
663 /* calc the required page order */
664 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
665 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
666 rq->buff.page_order = order_base_2(npages);
667
668 byte_count |= MLX5_HW_START_PADDING;
669 rq->mkey_be = c->mkey_be;
670 }
671
672 for (i = 0; i < wq_sz; i++) {
673 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
674
675 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
676 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
677
678 wqe->data.addr = cpu_to_be64(dma_offset);
679 }
680
681 wqe->data.byte_count = cpu_to_be32(byte_count);
682 wqe->data.lkey = rq->mkey_be;
683 }
684
685 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
686 rq->am.mode = params->rx_cq_moderation.cq_period_mode;
687 rq->page_cache.head = 0;
688 rq->page_cache.tail = 0;
689
690 return 0;
691
692 err_destroy_umr_mkey:
693 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
694
695 err_rq_wq_destroy:
696 if (rq->xdp_prog)
697 bpf_prog_put(rq->xdp_prog);
698 mlx5_wq_destroy(&rq->wq_ctrl);
699
700 return err;
701 }
702
703 static void mlx5e_free_rq(struct mlx5e_rq *rq)
704 {
705 int i;
706
707 if (rq->xdp_prog)
708 bpf_prog_put(rq->xdp_prog);
709
710 switch (rq->wq_type) {
711 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
712 mlx5e_rq_free_mpwqe_info(rq);
713 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
714 break;
715 default: /* MLX5_WQ_TYPE_LINKED_LIST */
716 kfree(rq->wqe.frag_info);
717 }
718
719 for (i = rq->page_cache.head; i != rq->page_cache.tail;
720 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
721 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
722
723 mlx5e_page_release(rq, dma_info, false);
724 }
725 mlx5_wq_destroy(&rq->wq_ctrl);
726 }
727
728 static int mlx5e_create_rq(struct mlx5e_rq *rq,
729 struct mlx5e_rq_param *param)
730 {
731 struct mlx5_core_dev *mdev = rq->mdev;
732
733 void *in;
734 void *rqc;
735 void *wq;
736 int inlen;
737 int err;
738
739 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
740 sizeof(u64) * rq->wq_ctrl.buf.npages;
741 in = kvzalloc(inlen, GFP_KERNEL);
742 if (!in)
743 return -ENOMEM;
744
745 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
746 wq = MLX5_ADDR_OF(rqc, rqc, wq);
747
748 memcpy(rqc, param->rqc, sizeof(param->rqc));
749
750 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
751 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
752 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
753 MLX5_ADAPTER_PAGE_SHIFT);
754 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
755
756 mlx5_fill_page_array(&rq->wq_ctrl.buf,
757 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
758
759 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
760
761 kvfree(in);
762
763 return err;
764 }
765
766 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
767 int next_state)
768 {
769 struct mlx5e_channel *c = rq->channel;
770 struct mlx5_core_dev *mdev = c->mdev;
771
772 void *in;
773 void *rqc;
774 int inlen;
775 int err;
776
777 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
778 in = kvzalloc(inlen, GFP_KERNEL);
779 if (!in)
780 return -ENOMEM;
781
782 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
783
784 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
785 MLX5_SET(rqc, rqc, state, next_state);
786
787 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
788
789 kvfree(in);
790
791 return err;
792 }
793
794 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
795 {
796 struct mlx5e_channel *c = rq->channel;
797 struct mlx5e_priv *priv = c->priv;
798 struct mlx5_core_dev *mdev = priv->mdev;
799
800 void *in;
801 void *rqc;
802 int inlen;
803 int err;
804
805 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
806 in = kvzalloc(inlen, GFP_KERNEL);
807 if (!in)
808 return -ENOMEM;
809
810 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
811
812 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
813 MLX5_SET64(modify_rq_in, in, modify_bitmask,
814 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
815 MLX5_SET(rqc, rqc, scatter_fcs, enable);
816 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
817
818 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
819
820 kvfree(in);
821
822 return err;
823 }
824
825 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
826 {
827 struct mlx5e_channel *c = rq->channel;
828 struct mlx5_core_dev *mdev = c->mdev;
829 void *in;
830 void *rqc;
831 int inlen;
832 int err;
833
834 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
835 in = kvzalloc(inlen, GFP_KERNEL);
836 if (!in)
837 return -ENOMEM;
838
839 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
840
841 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
842 MLX5_SET64(modify_rq_in, in, modify_bitmask,
843 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
844 MLX5_SET(rqc, rqc, vsd, vsd);
845 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
846
847 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
848
849 kvfree(in);
850
851 return err;
852 }
853
854 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
855 {
856 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
857 }
858
859 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
860 {
861 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
862 struct mlx5e_channel *c = rq->channel;
863
864 struct mlx5_wq_ll *wq = &rq->wq;
865 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
866
867 while (time_before(jiffies, exp_time)) {
868 if (wq->cur_sz >= min_wqes)
869 return 0;
870
871 msleep(20);
872 }
873
874 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
875 rq->rqn, wq->cur_sz, min_wqes);
876 return -ETIMEDOUT;
877 }
878
879 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
880 {
881 struct mlx5_wq_ll *wq = &rq->wq;
882 struct mlx5e_rx_wqe *wqe;
883 __be16 wqe_ix_be;
884 u16 wqe_ix;
885
886 /* UMR WQE (if in progress) is always at wq->head */
887 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
888 rq->mpwqe.umr_in_progress)
889 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
890
891 while (!mlx5_wq_ll_is_empty(wq)) {
892 wqe_ix_be = *wq->tail_next;
893 wqe_ix = be16_to_cpu(wqe_ix_be);
894 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
895 rq->dealloc_wqe(rq, wqe_ix);
896 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
897 &wqe->next.next_wqe_index);
898 }
899
900 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
901 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
902 * but yet to be re-posted.
903 */
904 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
905
906 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
907 rq->dealloc_wqe(rq, wqe_ix);
908 }
909 }
910
911 static int mlx5e_open_rq(struct mlx5e_channel *c,
912 struct mlx5e_params *params,
913 struct mlx5e_rq_param *param,
914 struct mlx5e_rq *rq)
915 {
916 int err;
917
918 err = mlx5e_alloc_rq(c, params, param, rq);
919 if (err)
920 return err;
921
922 err = mlx5e_create_rq(rq, param);
923 if (err)
924 goto err_free_rq;
925
926 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
927 if (err)
928 goto err_destroy_rq;
929
930 if (params->rx_am_enabled)
931 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
932
933 return 0;
934
935 err_destroy_rq:
936 mlx5e_destroy_rq(rq);
937 err_free_rq:
938 mlx5e_free_rq(rq);
939
940 return err;
941 }
942
943 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
944 {
945 struct mlx5e_icosq *sq = &rq->channel->icosq;
946 u16 pi = sq->pc & sq->wq.sz_m1;
947 struct mlx5e_tx_wqe *nopwqe;
948
949 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
950 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
951 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
952 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
953 }
954
955 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
956 {
957 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
958 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
959 }
960
961 static void mlx5e_close_rq(struct mlx5e_rq *rq)
962 {
963 cancel_work_sync(&rq->am.work);
964 mlx5e_destroy_rq(rq);
965 mlx5e_free_rx_descs(rq);
966 mlx5e_free_rq(rq);
967 }
968
969 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
970 {
971 kfree(sq->db.di);
972 }
973
974 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
975 {
976 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
977
978 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
979 GFP_KERNEL, numa);
980 if (!sq->db.di) {
981 mlx5e_free_xdpsq_db(sq);
982 return -ENOMEM;
983 }
984
985 return 0;
986 }
987
988 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
989 struct mlx5e_params *params,
990 struct mlx5e_sq_param *param,
991 struct mlx5e_xdpsq *sq)
992 {
993 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
994 struct mlx5_core_dev *mdev = c->mdev;
995 int err;
996
997 sq->pdev = c->pdev;
998 sq->mkey_be = c->mkey_be;
999 sq->channel = c;
1000 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1001 sq->min_inline_mode = params->tx_min_inline_mode;
1002
1003 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1004 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1005 if (err)
1006 return err;
1007 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1008
1009 err = mlx5e_alloc_xdpsq_db(sq, mlx5e_get_node(c->priv, c->ix));
1010 if (err)
1011 goto err_sq_wq_destroy;
1012
1013 return 0;
1014
1015 err_sq_wq_destroy:
1016 mlx5_wq_destroy(&sq->wq_ctrl);
1017
1018 return err;
1019 }
1020
1021 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1022 {
1023 mlx5e_free_xdpsq_db(sq);
1024 mlx5_wq_destroy(&sq->wq_ctrl);
1025 }
1026
1027 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1028 {
1029 kfree(sq->db.ico_wqe);
1030 }
1031
1032 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1033 {
1034 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1035
1036 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1037 GFP_KERNEL, numa);
1038 if (!sq->db.ico_wqe)
1039 return -ENOMEM;
1040
1041 return 0;
1042 }
1043
1044 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1045 struct mlx5e_sq_param *param,
1046 struct mlx5e_icosq *sq)
1047 {
1048 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1049 struct mlx5_core_dev *mdev = c->mdev;
1050 int err;
1051
1052 sq->mkey_be = c->mkey_be;
1053 sq->channel = c;
1054 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1055
1056 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1057 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1058 if (err)
1059 return err;
1060 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1061
1062 err = mlx5e_alloc_icosq_db(sq, mlx5e_get_node(c->priv, c->ix));
1063 if (err)
1064 goto err_sq_wq_destroy;
1065
1066 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
1067
1068 return 0;
1069
1070 err_sq_wq_destroy:
1071 mlx5_wq_destroy(&sq->wq_ctrl);
1072
1073 return err;
1074 }
1075
1076 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1077 {
1078 mlx5e_free_icosq_db(sq);
1079 mlx5_wq_destroy(&sq->wq_ctrl);
1080 }
1081
1082 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1083 {
1084 kfree(sq->db.wqe_info);
1085 kfree(sq->db.dma_fifo);
1086 }
1087
1088 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1089 {
1090 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1091 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1092
1093 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1094 GFP_KERNEL, numa);
1095 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1096 GFP_KERNEL, numa);
1097 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1098 mlx5e_free_txqsq_db(sq);
1099 return -ENOMEM;
1100 }
1101
1102 sq->dma_fifo_mask = df_sz - 1;
1103
1104 return 0;
1105 }
1106
1107 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1108 int txq_ix,
1109 struct mlx5e_params *params,
1110 struct mlx5e_sq_param *param,
1111 struct mlx5e_txqsq *sq)
1112 {
1113 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1114 struct mlx5_core_dev *mdev = c->mdev;
1115 int err;
1116
1117 sq->pdev = c->pdev;
1118 sq->tstamp = c->tstamp;
1119 sq->clock = &mdev->clock;
1120 sq->mkey_be = c->mkey_be;
1121 sq->channel = c;
1122 sq->txq_ix = txq_ix;
1123 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1124 sq->max_inline = params->tx_max_inline;
1125 sq->min_inline_mode = params->tx_min_inline_mode;
1126 if (MLX5_IPSEC_DEV(c->priv->mdev))
1127 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1128
1129 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1130 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1131 if (err)
1132 return err;
1133 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1134
1135 err = mlx5e_alloc_txqsq_db(sq, mlx5e_get_node(c->priv, c->ix));
1136 if (err)
1137 goto err_sq_wq_destroy;
1138
1139 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1140
1141 return 0;
1142
1143 err_sq_wq_destroy:
1144 mlx5_wq_destroy(&sq->wq_ctrl);
1145
1146 return err;
1147 }
1148
1149 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1150 {
1151 mlx5e_free_txqsq_db(sq);
1152 mlx5_wq_destroy(&sq->wq_ctrl);
1153 }
1154
1155 struct mlx5e_create_sq_param {
1156 struct mlx5_wq_ctrl *wq_ctrl;
1157 u32 cqn;
1158 u32 tisn;
1159 u8 tis_lst_sz;
1160 u8 min_inline_mode;
1161 };
1162
1163 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1164 struct mlx5e_sq_param *param,
1165 struct mlx5e_create_sq_param *csp,
1166 u32 *sqn)
1167 {
1168 void *in;
1169 void *sqc;
1170 void *wq;
1171 int inlen;
1172 int err;
1173
1174 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1175 sizeof(u64) * csp->wq_ctrl->buf.npages;
1176 in = kvzalloc(inlen, GFP_KERNEL);
1177 if (!in)
1178 return -ENOMEM;
1179
1180 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1181 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1182
1183 memcpy(sqc, param->sqc, sizeof(param->sqc));
1184 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1185 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1186 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1187
1188 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1189 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1190
1191 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1192
1193 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1194 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1195 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1196 MLX5_ADAPTER_PAGE_SHIFT);
1197 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1198
1199 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1200
1201 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1202
1203 kvfree(in);
1204
1205 return err;
1206 }
1207
1208 struct mlx5e_modify_sq_param {
1209 int curr_state;
1210 int next_state;
1211 bool rl_update;
1212 int rl_index;
1213 };
1214
1215 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1216 struct mlx5e_modify_sq_param *p)
1217 {
1218 void *in;
1219 void *sqc;
1220 int inlen;
1221 int err;
1222
1223 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1224 in = kvzalloc(inlen, GFP_KERNEL);
1225 if (!in)
1226 return -ENOMEM;
1227
1228 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1229
1230 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1231 MLX5_SET(sqc, sqc, state, p->next_state);
1232 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1233 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1234 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1235 }
1236
1237 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1238
1239 kvfree(in);
1240
1241 return err;
1242 }
1243
1244 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1245 {
1246 mlx5_core_destroy_sq(mdev, sqn);
1247 }
1248
1249 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1250 struct mlx5e_sq_param *param,
1251 struct mlx5e_create_sq_param *csp,
1252 u32 *sqn)
1253 {
1254 struct mlx5e_modify_sq_param msp = {0};
1255 int err;
1256
1257 err = mlx5e_create_sq(mdev, param, csp, sqn);
1258 if (err)
1259 return err;
1260
1261 msp.curr_state = MLX5_SQC_STATE_RST;
1262 msp.next_state = MLX5_SQC_STATE_RDY;
1263 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1264 if (err)
1265 mlx5e_destroy_sq(mdev, *sqn);
1266
1267 return err;
1268 }
1269
1270 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1271 struct mlx5e_txqsq *sq, u32 rate);
1272
1273 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1274 u32 tisn,
1275 int txq_ix,
1276 struct mlx5e_params *params,
1277 struct mlx5e_sq_param *param,
1278 struct mlx5e_txqsq *sq)
1279 {
1280 struct mlx5e_create_sq_param csp = {};
1281 u32 tx_rate;
1282 int err;
1283
1284 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1285 if (err)
1286 return err;
1287
1288 csp.tisn = tisn;
1289 csp.tis_lst_sz = 1;
1290 csp.cqn = sq->cq.mcq.cqn;
1291 csp.wq_ctrl = &sq->wq_ctrl;
1292 csp.min_inline_mode = sq->min_inline_mode;
1293 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1294 if (err)
1295 goto err_free_txqsq;
1296
1297 tx_rate = c->priv->tx_rates[sq->txq_ix];
1298 if (tx_rate)
1299 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1300
1301 return 0;
1302
1303 err_free_txqsq:
1304 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1305 mlx5e_free_txqsq(sq);
1306
1307 return err;
1308 }
1309
1310 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1311 {
1312 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1313 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1314 netdev_tx_reset_queue(sq->txq);
1315 netif_tx_start_queue(sq->txq);
1316 }
1317
1318 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1319 {
1320 __netif_tx_lock_bh(txq);
1321 netif_tx_stop_queue(txq);
1322 __netif_tx_unlock_bh(txq);
1323 }
1324
1325 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1326 {
1327 struct mlx5e_channel *c = sq->channel;
1328
1329 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1330 /* prevent netif_tx_wake_queue */
1331 napi_synchronize(&c->napi);
1332
1333 netif_tx_disable_queue(sq->txq);
1334
1335 /* last doorbell out, godspeed .. */
1336 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1337 struct mlx5e_tx_wqe *nop;
1338
1339 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1340 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1341 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1342 }
1343 }
1344
1345 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1346 {
1347 struct mlx5e_channel *c = sq->channel;
1348 struct mlx5_core_dev *mdev = c->mdev;
1349
1350 mlx5e_destroy_sq(mdev, sq->sqn);
1351 if (sq->rate_limit)
1352 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1353 mlx5e_free_txqsq_descs(sq);
1354 mlx5e_free_txqsq(sq);
1355 }
1356
1357 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1358 struct mlx5e_params *params,
1359 struct mlx5e_sq_param *param,
1360 struct mlx5e_icosq *sq)
1361 {
1362 struct mlx5e_create_sq_param csp = {};
1363 int err;
1364
1365 err = mlx5e_alloc_icosq(c, param, sq);
1366 if (err)
1367 return err;
1368
1369 csp.cqn = sq->cq.mcq.cqn;
1370 csp.wq_ctrl = &sq->wq_ctrl;
1371 csp.min_inline_mode = params->tx_min_inline_mode;
1372 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1373 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1374 if (err)
1375 goto err_free_icosq;
1376
1377 return 0;
1378
1379 err_free_icosq:
1380 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1381 mlx5e_free_icosq(sq);
1382
1383 return err;
1384 }
1385
1386 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1387 {
1388 struct mlx5e_channel *c = sq->channel;
1389
1390 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1391 napi_synchronize(&c->napi);
1392
1393 mlx5e_destroy_sq(c->mdev, sq->sqn);
1394 mlx5e_free_icosq(sq);
1395 }
1396
1397 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1398 struct mlx5e_params *params,
1399 struct mlx5e_sq_param *param,
1400 struct mlx5e_xdpsq *sq)
1401 {
1402 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1403 struct mlx5e_create_sq_param csp = {};
1404 unsigned int inline_hdr_sz = 0;
1405 int err;
1406 int i;
1407
1408 err = mlx5e_alloc_xdpsq(c, params, param, sq);
1409 if (err)
1410 return err;
1411
1412 csp.tis_lst_sz = 1;
1413 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1414 csp.cqn = sq->cq.mcq.cqn;
1415 csp.wq_ctrl = &sq->wq_ctrl;
1416 csp.min_inline_mode = sq->min_inline_mode;
1417 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1418 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1419 if (err)
1420 goto err_free_xdpsq;
1421
1422 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1423 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1424 ds_cnt++;
1425 }
1426
1427 /* Pre initialize fixed WQE fields */
1428 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1429 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1430 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1431 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1432 struct mlx5_wqe_data_seg *dseg;
1433
1434 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1435 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1436
1437 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1438 dseg->lkey = sq->mkey_be;
1439 }
1440
1441 return 0;
1442
1443 err_free_xdpsq:
1444 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1445 mlx5e_free_xdpsq(sq);
1446
1447 return err;
1448 }
1449
1450 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1451 {
1452 struct mlx5e_channel *c = sq->channel;
1453
1454 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1455 napi_synchronize(&c->napi);
1456
1457 mlx5e_destroy_sq(c->mdev, sq->sqn);
1458 mlx5e_free_xdpsq_descs(sq);
1459 mlx5e_free_xdpsq(sq);
1460 }
1461
1462 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1463 struct mlx5e_cq_param *param,
1464 struct mlx5e_cq *cq)
1465 {
1466 struct mlx5_core_cq *mcq = &cq->mcq;
1467 int eqn_not_used;
1468 unsigned int irqn;
1469 int err;
1470 u32 i;
1471
1472 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1473 &cq->wq_ctrl);
1474 if (err)
1475 return err;
1476
1477 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1478
1479 mcq->cqe_sz = 64;
1480 mcq->set_ci_db = cq->wq_ctrl.db.db;
1481 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1482 *mcq->set_ci_db = 0;
1483 *mcq->arm_db = 0;
1484 mcq->vector = param->eq_ix;
1485 mcq->comp = mlx5e_completion_event;
1486 mcq->event = mlx5e_cq_error_event;
1487 mcq->irqn = irqn;
1488
1489 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1490 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1491
1492 cqe->op_own = 0xf1;
1493 }
1494
1495 cq->mdev = mdev;
1496
1497 return 0;
1498 }
1499
1500 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1501 struct mlx5e_cq_param *param,
1502 struct mlx5e_cq *cq)
1503 {
1504 struct mlx5_core_dev *mdev = c->priv->mdev;
1505 int err;
1506
1507 param->wq.buf_numa_node = mlx5e_get_node(c->priv, c->ix);
1508 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1509 param->eq_ix = c->ix;
1510
1511 err = mlx5e_alloc_cq_common(mdev, param, cq);
1512
1513 cq->napi = &c->napi;
1514 cq->channel = c;
1515
1516 return err;
1517 }
1518
1519 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1520 {
1521 mlx5_cqwq_destroy(&cq->wq_ctrl);
1522 }
1523
1524 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1525 {
1526 struct mlx5_core_dev *mdev = cq->mdev;
1527 struct mlx5_core_cq *mcq = &cq->mcq;
1528
1529 void *in;
1530 void *cqc;
1531 int inlen;
1532 unsigned int irqn_not_used;
1533 int eqn;
1534 int err;
1535
1536 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1537 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1538 in = kvzalloc(inlen, GFP_KERNEL);
1539 if (!in)
1540 return -ENOMEM;
1541
1542 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1543
1544 memcpy(cqc, param->cqc, sizeof(param->cqc));
1545
1546 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1547 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1548
1549 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1550
1551 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1552 MLX5_SET(cqc, cqc, c_eqn, eqn);
1553 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1554 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1555 MLX5_ADAPTER_PAGE_SHIFT);
1556 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1557
1558 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1559
1560 kvfree(in);
1561
1562 if (err)
1563 return err;
1564
1565 mlx5e_cq_arm(cq);
1566
1567 return 0;
1568 }
1569
1570 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1571 {
1572 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1573 }
1574
1575 static int mlx5e_open_cq(struct mlx5e_channel *c,
1576 struct mlx5e_cq_moder moder,
1577 struct mlx5e_cq_param *param,
1578 struct mlx5e_cq *cq)
1579 {
1580 struct mlx5_core_dev *mdev = c->mdev;
1581 int err;
1582
1583 err = mlx5e_alloc_cq(c, param, cq);
1584 if (err)
1585 return err;
1586
1587 err = mlx5e_create_cq(cq, param);
1588 if (err)
1589 goto err_free_cq;
1590
1591 if (MLX5_CAP_GEN(mdev, cq_moderation))
1592 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1593 return 0;
1594
1595 err_free_cq:
1596 mlx5e_free_cq(cq);
1597
1598 return err;
1599 }
1600
1601 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1602 {
1603 mlx5e_destroy_cq(cq);
1604 mlx5e_free_cq(cq);
1605 }
1606
1607 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1608 struct mlx5e_params *params,
1609 struct mlx5e_channel_param *cparam)
1610 {
1611 int err;
1612 int tc;
1613
1614 for (tc = 0; tc < c->num_tc; tc++) {
1615 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1616 &cparam->tx_cq, &c->sq[tc].cq);
1617 if (err)
1618 goto err_close_tx_cqs;
1619 }
1620
1621 return 0;
1622
1623 err_close_tx_cqs:
1624 for (tc--; tc >= 0; tc--)
1625 mlx5e_close_cq(&c->sq[tc].cq);
1626
1627 return err;
1628 }
1629
1630 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1631 {
1632 int tc;
1633
1634 for (tc = 0; tc < c->num_tc; tc++)
1635 mlx5e_close_cq(&c->sq[tc].cq);
1636 }
1637
1638 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1639 struct mlx5e_params *params,
1640 struct mlx5e_channel_param *cparam)
1641 {
1642 int err;
1643 int tc;
1644
1645 for (tc = 0; tc < params->num_tc; tc++) {
1646 int txq_ix = c->ix + tc * params->num_channels;
1647
1648 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1649 params, &cparam->sq, &c->sq[tc]);
1650 if (err)
1651 goto err_close_sqs;
1652 }
1653
1654 return 0;
1655
1656 err_close_sqs:
1657 for (tc--; tc >= 0; tc--)
1658 mlx5e_close_txqsq(&c->sq[tc]);
1659
1660 return err;
1661 }
1662
1663 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1664 {
1665 int tc;
1666
1667 for (tc = 0; tc < c->num_tc; tc++)
1668 mlx5e_close_txqsq(&c->sq[tc]);
1669 }
1670
1671 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1672 struct mlx5e_txqsq *sq, u32 rate)
1673 {
1674 struct mlx5e_priv *priv = netdev_priv(dev);
1675 struct mlx5_core_dev *mdev = priv->mdev;
1676 struct mlx5e_modify_sq_param msp = {0};
1677 u16 rl_index = 0;
1678 int err;
1679
1680 if (rate == sq->rate_limit)
1681 /* nothing to do */
1682 return 0;
1683
1684 if (sq->rate_limit)
1685 /* remove current rl index to free space to next ones */
1686 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1687
1688 sq->rate_limit = 0;
1689
1690 if (rate) {
1691 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1692 if (err) {
1693 netdev_err(dev, "Failed configuring rate %u: %d\n",
1694 rate, err);
1695 return err;
1696 }
1697 }
1698
1699 msp.curr_state = MLX5_SQC_STATE_RDY;
1700 msp.next_state = MLX5_SQC_STATE_RDY;
1701 msp.rl_index = rl_index;
1702 msp.rl_update = true;
1703 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1704 if (err) {
1705 netdev_err(dev, "Failed configuring rate %u: %d\n",
1706 rate, err);
1707 /* remove the rate from the table */
1708 if (rate)
1709 mlx5_rl_remove_rate(mdev, rate);
1710 return err;
1711 }
1712
1713 sq->rate_limit = rate;
1714 return 0;
1715 }
1716
1717 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1718 {
1719 struct mlx5e_priv *priv = netdev_priv(dev);
1720 struct mlx5_core_dev *mdev = priv->mdev;
1721 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1722 int err = 0;
1723
1724 if (!mlx5_rl_is_supported(mdev)) {
1725 netdev_err(dev, "Rate limiting is not supported on this device\n");
1726 return -EINVAL;
1727 }
1728
1729 /* rate is given in Mb/sec, HW config is in Kb/sec */
1730 rate = rate << 10;
1731
1732 /* Check whether rate in valid range, 0 is always valid */
1733 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1734 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1735 return -ERANGE;
1736 }
1737
1738 mutex_lock(&priv->state_lock);
1739 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1740 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1741 if (!err)
1742 priv->tx_rates[index] = rate;
1743 mutex_unlock(&priv->state_lock);
1744
1745 return err;
1746 }
1747
1748 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1749 struct mlx5e_params *params,
1750 struct mlx5e_channel_param *cparam,
1751 struct mlx5e_channel **cp)
1752 {
1753 struct mlx5e_cq_moder icocq_moder = {0, 0};
1754 struct net_device *netdev = priv->netdev;
1755 struct mlx5e_channel *c;
1756 unsigned int irq;
1757 int err;
1758 int eqn;
1759
1760 c = kzalloc_node(sizeof(*c), GFP_KERNEL, mlx5e_get_node(priv, ix));
1761 if (!c)
1762 return -ENOMEM;
1763
1764 c->priv = priv;
1765 c->mdev = priv->mdev;
1766 c->tstamp = &priv->tstamp;
1767 c->ix = ix;
1768 c->pdev = &priv->mdev->pdev->dev;
1769 c->netdev = priv->netdev;
1770 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1771 c->num_tc = params->num_tc;
1772 c->xdp = !!params->xdp_prog;
1773
1774 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1775 c->irq_desc = irq_to_desc(irq);
1776
1777 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1778
1779 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1780 if (err)
1781 goto err_napi_del;
1782
1783 err = mlx5e_open_tx_cqs(c, params, cparam);
1784 if (err)
1785 goto err_close_icosq_cq;
1786
1787 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1788 if (err)
1789 goto err_close_tx_cqs;
1790
1791 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1792 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1793 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1794 if (err)
1795 goto err_close_rx_cq;
1796
1797 napi_enable(&c->napi);
1798
1799 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1800 if (err)
1801 goto err_disable_napi;
1802
1803 err = mlx5e_open_sqs(c, params, cparam);
1804 if (err)
1805 goto err_close_icosq;
1806
1807 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1808 if (err)
1809 goto err_close_sqs;
1810
1811 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1812 if (err)
1813 goto err_close_xdp_sq;
1814
1815 *cp = c;
1816
1817 return 0;
1818 err_close_xdp_sq:
1819 if (c->xdp)
1820 mlx5e_close_xdpsq(&c->rq.xdpsq);
1821
1822 err_close_sqs:
1823 mlx5e_close_sqs(c);
1824
1825 err_close_icosq:
1826 mlx5e_close_icosq(&c->icosq);
1827
1828 err_disable_napi:
1829 napi_disable(&c->napi);
1830 if (c->xdp)
1831 mlx5e_close_cq(&c->rq.xdpsq.cq);
1832
1833 err_close_rx_cq:
1834 mlx5e_close_cq(&c->rq.cq);
1835
1836 err_close_tx_cqs:
1837 mlx5e_close_tx_cqs(c);
1838
1839 err_close_icosq_cq:
1840 mlx5e_close_cq(&c->icosq.cq);
1841
1842 err_napi_del:
1843 netif_napi_del(&c->napi);
1844 kfree(c);
1845
1846 return err;
1847 }
1848
1849 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1850 {
1851 int tc;
1852
1853 for (tc = 0; tc < c->num_tc; tc++)
1854 mlx5e_activate_txqsq(&c->sq[tc]);
1855 mlx5e_activate_rq(&c->rq);
1856 netif_set_xps_queue(c->netdev,
1857 mlx5_get_vector_affinity(c->priv->mdev, c->ix), c->ix);
1858 }
1859
1860 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1861 {
1862 int tc;
1863
1864 mlx5e_deactivate_rq(&c->rq);
1865 for (tc = 0; tc < c->num_tc; tc++)
1866 mlx5e_deactivate_txqsq(&c->sq[tc]);
1867 }
1868
1869 static void mlx5e_close_channel(struct mlx5e_channel *c)
1870 {
1871 mlx5e_close_rq(&c->rq);
1872 if (c->xdp)
1873 mlx5e_close_xdpsq(&c->rq.xdpsq);
1874 mlx5e_close_sqs(c);
1875 mlx5e_close_icosq(&c->icosq);
1876 napi_disable(&c->napi);
1877 if (c->xdp)
1878 mlx5e_close_cq(&c->rq.xdpsq.cq);
1879 mlx5e_close_cq(&c->rq.cq);
1880 mlx5e_close_tx_cqs(c);
1881 mlx5e_close_cq(&c->icosq.cq);
1882 netif_napi_del(&c->napi);
1883
1884 kfree(c);
1885 }
1886
1887 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1888 struct mlx5e_params *params,
1889 struct mlx5e_rq_param *param)
1890 {
1891 void *rqc = param->rqc;
1892 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1893
1894 switch (params->rq_wq_type) {
1895 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1896 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1897 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
1898 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1899 break;
1900 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1901 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1902 }
1903
1904 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1905 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1906 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
1907 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1908 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1909 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
1910 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
1911
1912 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1913 param->wq.linear = 1;
1914 }
1915
1916 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1917 {
1918 void *rqc = param->rqc;
1919 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1920
1921 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1922 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1923 }
1924
1925 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1926 struct mlx5e_sq_param *param)
1927 {
1928 void *sqc = param->sqc;
1929 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1930
1931 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1932 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1933
1934 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1935 }
1936
1937 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1938 struct mlx5e_params *params,
1939 struct mlx5e_sq_param *param)
1940 {
1941 void *sqc = param->sqc;
1942 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1943
1944 mlx5e_build_sq_param_common(priv, param);
1945 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1946 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1947 }
1948
1949 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1950 struct mlx5e_cq_param *param)
1951 {
1952 void *cqc = param->cqc;
1953
1954 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1955 }
1956
1957 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1958 struct mlx5e_params *params,
1959 struct mlx5e_cq_param *param)
1960 {
1961 void *cqc = param->cqc;
1962 u8 log_cq_size;
1963
1964 switch (params->rq_wq_type) {
1965 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1966 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
1967 break;
1968 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1969 log_cq_size = params->log_rq_size;
1970 }
1971
1972 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1973 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1974 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1975 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1976 }
1977
1978 mlx5e_build_common_cq_param(priv, param);
1979 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
1980 }
1981
1982 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1983 struct mlx5e_params *params,
1984 struct mlx5e_cq_param *param)
1985 {
1986 void *cqc = param->cqc;
1987
1988 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1989
1990 mlx5e_build_common_cq_param(priv, param);
1991 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
1992 }
1993
1994 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1995 u8 log_wq_size,
1996 struct mlx5e_cq_param *param)
1997 {
1998 void *cqc = param->cqc;
1999
2000 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2001
2002 mlx5e_build_common_cq_param(priv, param);
2003
2004 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2005 }
2006
2007 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2008 u8 log_wq_size,
2009 struct mlx5e_sq_param *param)
2010 {
2011 void *sqc = param->sqc;
2012 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2013
2014 mlx5e_build_sq_param_common(priv, param);
2015
2016 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2017 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2018 }
2019
2020 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2021 struct mlx5e_params *params,
2022 struct mlx5e_sq_param *param)
2023 {
2024 void *sqc = param->sqc;
2025 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2026
2027 mlx5e_build_sq_param_common(priv, param);
2028 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2029 }
2030
2031 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2032 struct mlx5e_params *params,
2033 struct mlx5e_channel_param *cparam)
2034 {
2035 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2036
2037 mlx5e_build_rq_param(priv, params, &cparam->rq);
2038 mlx5e_build_sq_param(priv, params, &cparam->sq);
2039 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2040 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2041 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2042 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2043 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2044 }
2045
2046 int mlx5e_open_channels(struct mlx5e_priv *priv,
2047 struct mlx5e_channels *chs)
2048 {
2049 struct mlx5e_channel_param *cparam;
2050 int err = -ENOMEM;
2051 int i;
2052
2053 chs->num = chs->params.num_channels;
2054
2055 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2056 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2057 if (!chs->c || !cparam)
2058 goto err_free;
2059
2060 mlx5e_build_channel_param(priv, &chs->params, cparam);
2061 for (i = 0; i < chs->num; i++) {
2062 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2063 if (err)
2064 goto err_close_channels;
2065 }
2066
2067 kfree(cparam);
2068 return 0;
2069
2070 err_close_channels:
2071 for (i--; i >= 0; i--)
2072 mlx5e_close_channel(chs->c[i]);
2073
2074 err_free:
2075 kfree(chs->c);
2076 kfree(cparam);
2077 chs->num = 0;
2078 return err;
2079 }
2080
2081 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2082 {
2083 int i;
2084
2085 for (i = 0; i < chs->num; i++)
2086 mlx5e_activate_channel(chs->c[i]);
2087 }
2088
2089 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2090 {
2091 int err = 0;
2092 int i;
2093
2094 for (i = 0; i < chs->num; i++) {
2095 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2096 if (err)
2097 break;
2098 }
2099
2100 return err;
2101 }
2102
2103 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2104 {
2105 int i;
2106
2107 for (i = 0; i < chs->num; i++)
2108 mlx5e_deactivate_channel(chs->c[i]);
2109 }
2110
2111 void mlx5e_close_channels(struct mlx5e_channels *chs)
2112 {
2113 int i;
2114
2115 for (i = 0; i < chs->num; i++)
2116 mlx5e_close_channel(chs->c[i]);
2117
2118 kfree(chs->c);
2119 chs->num = 0;
2120 }
2121
2122 static int
2123 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2124 {
2125 struct mlx5_core_dev *mdev = priv->mdev;
2126 void *rqtc;
2127 int inlen;
2128 int err;
2129 u32 *in;
2130 int i;
2131
2132 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2133 in = kvzalloc(inlen, GFP_KERNEL);
2134 if (!in)
2135 return -ENOMEM;
2136
2137 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2138
2139 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2140 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2141
2142 for (i = 0; i < sz; i++)
2143 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2144
2145 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2146 if (!err)
2147 rqt->enabled = true;
2148
2149 kvfree(in);
2150 return err;
2151 }
2152
2153 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2154 {
2155 rqt->enabled = false;
2156 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2157 }
2158
2159 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2160 {
2161 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2162 int err;
2163
2164 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2165 if (err)
2166 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2167 return err;
2168 }
2169
2170 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2171 {
2172 struct mlx5e_rqt *rqt;
2173 int err;
2174 int ix;
2175
2176 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2177 rqt = &priv->direct_tir[ix].rqt;
2178 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2179 if (err)
2180 goto err_destroy_rqts;
2181 }
2182
2183 return 0;
2184
2185 err_destroy_rqts:
2186 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2187 for (ix--; ix >= 0; ix--)
2188 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2189
2190 return err;
2191 }
2192
2193 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2194 {
2195 int i;
2196
2197 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2198 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2199 }
2200
2201 static int mlx5e_rx_hash_fn(int hfunc)
2202 {
2203 return (hfunc == ETH_RSS_HASH_TOP) ?
2204 MLX5_RX_HASH_FN_TOEPLITZ :
2205 MLX5_RX_HASH_FN_INVERTED_XOR8;
2206 }
2207
2208 static int mlx5e_bits_invert(unsigned long a, int size)
2209 {
2210 int inv = 0;
2211 int i;
2212
2213 for (i = 0; i < size; i++)
2214 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2215
2216 return inv;
2217 }
2218
2219 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2220 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2221 {
2222 int i;
2223
2224 for (i = 0; i < sz; i++) {
2225 u32 rqn;
2226
2227 if (rrp.is_rss) {
2228 int ix = i;
2229
2230 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2231 ix = mlx5e_bits_invert(i, ilog2(sz));
2232
2233 ix = priv->channels.params.indirection_rqt[ix];
2234 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2235 } else {
2236 rqn = rrp.rqn;
2237 }
2238 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2239 }
2240 }
2241
2242 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2243 struct mlx5e_redirect_rqt_param rrp)
2244 {
2245 struct mlx5_core_dev *mdev = priv->mdev;
2246 void *rqtc;
2247 int inlen;
2248 u32 *in;
2249 int err;
2250
2251 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2252 in = kvzalloc(inlen, GFP_KERNEL);
2253 if (!in)
2254 return -ENOMEM;
2255
2256 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2257
2258 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2259 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2260 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2261 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2262
2263 kvfree(in);
2264 return err;
2265 }
2266
2267 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2268 struct mlx5e_redirect_rqt_param rrp)
2269 {
2270 if (!rrp.is_rss)
2271 return rrp.rqn;
2272
2273 if (ix >= rrp.rss.channels->num)
2274 return priv->drop_rq.rqn;
2275
2276 return rrp.rss.channels->c[ix]->rq.rqn;
2277 }
2278
2279 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2280 struct mlx5e_redirect_rqt_param rrp)
2281 {
2282 u32 rqtn;
2283 int ix;
2284
2285 if (priv->indir_rqt.enabled) {
2286 /* RSS RQ table */
2287 rqtn = priv->indir_rqt.rqtn;
2288 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2289 }
2290
2291 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2292 struct mlx5e_redirect_rqt_param direct_rrp = {
2293 .is_rss = false,
2294 {
2295 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2296 },
2297 };
2298
2299 /* Direct RQ Tables */
2300 if (!priv->direct_tir[ix].rqt.enabled)
2301 continue;
2302
2303 rqtn = priv->direct_tir[ix].rqt.rqtn;
2304 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2305 }
2306 }
2307
2308 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2309 struct mlx5e_channels *chs)
2310 {
2311 struct mlx5e_redirect_rqt_param rrp = {
2312 .is_rss = true,
2313 {
2314 .rss = {
2315 .channels = chs,
2316 .hfunc = chs->params.rss_hfunc,
2317 }
2318 },
2319 };
2320
2321 mlx5e_redirect_rqts(priv, rrp);
2322 }
2323
2324 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2325 {
2326 struct mlx5e_redirect_rqt_param drop_rrp = {
2327 .is_rss = false,
2328 {
2329 .rqn = priv->drop_rq.rqn,
2330 },
2331 };
2332
2333 mlx5e_redirect_rqts(priv, drop_rrp);
2334 }
2335
2336 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2337 {
2338 if (!params->lro_en)
2339 return;
2340
2341 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2342
2343 MLX5_SET(tirc, tirc, lro_enable_mask,
2344 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2345 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2346 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2347 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2348 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2349 }
2350
2351 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2352 enum mlx5e_traffic_types tt,
2353 void *tirc, bool inner)
2354 {
2355 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2356 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2357
2358 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2359 MLX5_HASH_FIELD_SEL_DST_IP)
2360
2361 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2362 MLX5_HASH_FIELD_SEL_DST_IP |\
2363 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2364 MLX5_HASH_FIELD_SEL_L4_DPORT)
2365
2366 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2367 MLX5_HASH_FIELD_SEL_DST_IP |\
2368 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2369
2370 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2371 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2372 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2373 rx_hash_toeplitz_key);
2374 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2375 rx_hash_toeplitz_key);
2376
2377 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2378 memcpy(rss_key, params->toeplitz_hash_key, len);
2379 }
2380
2381 switch (tt) {
2382 case MLX5E_TT_IPV4_TCP:
2383 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2384 MLX5_L3_PROT_TYPE_IPV4);
2385 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2386 MLX5_L4_PROT_TYPE_TCP);
2387 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2388 MLX5_HASH_IP_L4PORTS);
2389 break;
2390
2391 case MLX5E_TT_IPV6_TCP:
2392 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2393 MLX5_L3_PROT_TYPE_IPV6);
2394 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2395 MLX5_L4_PROT_TYPE_TCP);
2396 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2397 MLX5_HASH_IP_L4PORTS);
2398 break;
2399
2400 case MLX5E_TT_IPV4_UDP:
2401 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2402 MLX5_L3_PROT_TYPE_IPV4);
2403 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2404 MLX5_L4_PROT_TYPE_UDP);
2405 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2406 MLX5_HASH_IP_L4PORTS);
2407 break;
2408
2409 case MLX5E_TT_IPV6_UDP:
2410 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2411 MLX5_L3_PROT_TYPE_IPV6);
2412 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2413 MLX5_L4_PROT_TYPE_UDP);
2414 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2415 MLX5_HASH_IP_L4PORTS);
2416 break;
2417
2418 case MLX5E_TT_IPV4_IPSEC_AH:
2419 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2420 MLX5_L3_PROT_TYPE_IPV4);
2421 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2422 MLX5_HASH_IP_IPSEC_SPI);
2423 break;
2424
2425 case MLX5E_TT_IPV6_IPSEC_AH:
2426 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2427 MLX5_L3_PROT_TYPE_IPV6);
2428 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2429 MLX5_HASH_IP_IPSEC_SPI);
2430 break;
2431
2432 case MLX5E_TT_IPV4_IPSEC_ESP:
2433 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2434 MLX5_L3_PROT_TYPE_IPV4);
2435 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2436 MLX5_HASH_IP_IPSEC_SPI);
2437 break;
2438
2439 case MLX5E_TT_IPV6_IPSEC_ESP:
2440 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2441 MLX5_L3_PROT_TYPE_IPV6);
2442 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2443 MLX5_HASH_IP_IPSEC_SPI);
2444 break;
2445
2446 case MLX5E_TT_IPV4:
2447 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2448 MLX5_L3_PROT_TYPE_IPV4);
2449 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2450 MLX5_HASH_IP);
2451 break;
2452
2453 case MLX5E_TT_IPV6:
2454 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2455 MLX5_L3_PROT_TYPE_IPV6);
2456 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2457 MLX5_HASH_IP);
2458 break;
2459 default:
2460 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2461 }
2462 }
2463
2464 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2465 {
2466 struct mlx5_core_dev *mdev = priv->mdev;
2467
2468 void *in;
2469 void *tirc;
2470 int inlen;
2471 int err;
2472 int tt;
2473 int ix;
2474
2475 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2476 in = kvzalloc(inlen, GFP_KERNEL);
2477 if (!in)
2478 return -ENOMEM;
2479
2480 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2481 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2482
2483 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2484
2485 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2486 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2487 inlen);
2488 if (err)
2489 goto free_in;
2490 }
2491
2492 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2493 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2494 in, inlen);
2495 if (err)
2496 goto free_in;
2497 }
2498
2499 free_in:
2500 kvfree(in);
2501
2502 return err;
2503 }
2504
2505 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2506 enum mlx5e_traffic_types tt,
2507 u32 *tirc)
2508 {
2509 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2510
2511 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2512
2513 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2514 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2515 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2516
2517 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2518 }
2519
2520 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2521 {
2522 struct mlx5_core_dev *mdev = priv->mdev;
2523 u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
2524 int err;
2525
2526 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2527 if (err)
2528 return err;
2529
2530 /* Update vport context MTU */
2531 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2532 return 0;
2533 }
2534
2535 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2536 {
2537 struct mlx5_core_dev *mdev = priv->mdev;
2538 u16 hw_mtu = 0;
2539 int err;
2540
2541 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2542 if (err || !hw_mtu) /* fallback to port oper mtu */
2543 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2544
2545 *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
2546 }
2547
2548 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2549 {
2550 struct net_device *netdev = priv->netdev;
2551 u16 mtu;
2552 int err;
2553
2554 err = mlx5e_set_mtu(priv, netdev->mtu);
2555 if (err)
2556 return err;
2557
2558 mlx5e_query_mtu(priv, &mtu);
2559 if (mtu != netdev->mtu)
2560 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2561 __func__, mtu, netdev->mtu);
2562
2563 netdev->mtu = mtu;
2564 return 0;
2565 }
2566
2567 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2568 {
2569 struct mlx5e_priv *priv = netdev_priv(netdev);
2570 int nch = priv->channels.params.num_channels;
2571 int ntc = priv->channels.params.num_tc;
2572 int tc;
2573
2574 netdev_reset_tc(netdev);
2575
2576 if (ntc == 1)
2577 return;
2578
2579 netdev_set_num_tc(netdev, ntc);
2580
2581 /* Map netdev TCs to offset 0
2582 * We have our own UP to TXQ mapping for QoS
2583 */
2584 for (tc = 0; tc < ntc; tc++)
2585 netdev_set_tc_queue(netdev, tc, nch, 0);
2586 }
2587
2588 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2589 {
2590 struct mlx5e_channel *c;
2591 struct mlx5e_txqsq *sq;
2592 int i, tc;
2593
2594 for (i = 0; i < priv->channels.num; i++)
2595 for (tc = 0; tc < priv->profile->max_tc; tc++)
2596 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2597
2598 for (i = 0; i < priv->channels.num; i++) {
2599 c = priv->channels.c[i];
2600 for (tc = 0; tc < c->num_tc; tc++) {
2601 sq = &c->sq[tc];
2602 priv->txq2sq[sq->txq_ix] = sq;
2603 }
2604 }
2605 }
2606
2607 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2608 {
2609 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2610 struct net_device *netdev = priv->netdev;
2611
2612 mlx5e_netdev_set_tcs(netdev);
2613 netif_set_real_num_tx_queues(netdev, num_txqs);
2614 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2615
2616 mlx5e_build_channels_tx_maps(priv);
2617 mlx5e_activate_channels(&priv->channels);
2618 netif_tx_start_all_queues(priv->netdev);
2619
2620 if (MLX5_VPORT_MANAGER(priv->mdev))
2621 mlx5e_add_sqs_fwd_rules(priv);
2622
2623 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2624 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2625 }
2626
2627 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2628 {
2629 mlx5e_redirect_rqts_to_drop(priv);
2630
2631 if (MLX5_VPORT_MANAGER(priv->mdev))
2632 mlx5e_remove_sqs_fwd_rules(priv);
2633
2634 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2635 * polling for inactive tx queues.
2636 */
2637 netif_tx_stop_all_queues(priv->netdev);
2638 netif_tx_disable(priv->netdev);
2639 mlx5e_deactivate_channels(&priv->channels);
2640 }
2641
2642 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2643 struct mlx5e_channels *new_chs,
2644 mlx5e_fp_hw_modify hw_modify)
2645 {
2646 struct net_device *netdev = priv->netdev;
2647 int new_num_txqs;
2648 int carrier_ok;
2649 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2650
2651 carrier_ok = netif_carrier_ok(netdev);
2652 netif_carrier_off(netdev);
2653
2654 if (new_num_txqs < netdev->real_num_tx_queues)
2655 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2656
2657 mlx5e_deactivate_priv_channels(priv);
2658 mlx5e_close_channels(&priv->channels);
2659
2660 priv->channels = *new_chs;
2661
2662 /* New channels are ready to roll, modify HW settings if needed */
2663 if (hw_modify)
2664 hw_modify(priv);
2665
2666 mlx5e_refresh_tirs(priv, false);
2667 mlx5e_activate_priv_channels(priv);
2668
2669 /* return carrier back if needed */
2670 if (carrier_ok)
2671 netif_carrier_on(netdev);
2672 }
2673
2674 void mlx5e_timestamp_set(struct mlx5e_priv *priv)
2675 {
2676 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2677 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2678 }
2679
2680 int mlx5e_open_locked(struct net_device *netdev)
2681 {
2682 struct mlx5e_priv *priv = netdev_priv(netdev);
2683 int err;
2684
2685 set_bit(MLX5E_STATE_OPENED, &priv->state);
2686
2687 err = mlx5e_open_channels(priv, &priv->channels);
2688 if (err)
2689 goto err_clear_state_opened_flag;
2690
2691 mlx5e_refresh_tirs(priv, false);
2692 mlx5e_activate_priv_channels(priv);
2693 if (priv->profile->update_carrier)
2694 priv->profile->update_carrier(priv);
2695 mlx5e_timestamp_set(priv);
2696
2697 if (priv->profile->update_stats)
2698 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2699
2700 return 0;
2701
2702 err_clear_state_opened_flag:
2703 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2704 return err;
2705 }
2706
2707 int mlx5e_open(struct net_device *netdev)
2708 {
2709 struct mlx5e_priv *priv = netdev_priv(netdev);
2710 int err;
2711
2712 mutex_lock(&priv->state_lock);
2713 err = mlx5e_open_locked(netdev);
2714 if (!err)
2715 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2716 mutex_unlock(&priv->state_lock);
2717
2718 return err;
2719 }
2720
2721 int mlx5e_close_locked(struct net_device *netdev)
2722 {
2723 struct mlx5e_priv *priv = netdev_priv(netdev);
2724
2725 /* May already be CLOSED in case a previous configuration operation
2726 * (e.g RX/TX queue size change) that involves close&open failed.
2727 */
2728 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2729 return 0;
2730
2731 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2732
2733 netif_carrier_off(priv->netdev);
2734 mlx5e_deactivate_priv_channels(priv);
2735 mlx5e_close_channels(&priv->channels);
2736
2737 return 0;
2738 }
2739
2740 int mlx5e_close(struct net_device *netdev)
2741 {
2742 struct mlx5e_priv *priv = netdev_priv(netdev);
2743 int err;
2744
2745 if (!netif_device_present(netdev))
2746 return -ENODEV;
2747
2748 mutex_lock(&priv->state_lock);
2749 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2750 err = mlx5e_close_locked(netdev);
2751 mutex_unlock(&priv->state_lock);
2752
2753 return err;
2754 }
2755
2756 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2757 struct mlx5e_rq *rq,
2758 struct mlx5e_rq_param *param)
2759 {
2760 void *rqc = param->rqc;
2761 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2762 int err;
2763
2764 param->wq.db_numa_node = param->wq.buf_numa_node;
2765
2766 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2767 &rq->wq_ctrl);
2768 if (err)
2769 return err;
2770
2771 rq->mdev = mdev;
2772
2773 return 0;
2774 }
2775
2776 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2777 struct mlx5e_cq *cq,
2778 struct mlx5e_cq_param *param)
2779 {
2780 return mlx5e_alloc_cq_common(mdev, param, cq);
2781 }
2782
2783 static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2784 struct mlx5e_rq *drop_rq)
2785 {
2786 struct mlx5e_cq_param cq_param = {};
2787 struct mlx5e_rq_param rq_param = {};
2788 struct mlx5e_cq *cq = &drop_rq->cq;
2789 int err;
2790
2791 mlx5e_build_drop_rq_param(&rq_param);
2792
2793 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2794 if (err)
2795 return err;
2796
2797 err = mlx5e_create_cq(cq, &cq_param);
2798 if (err)
2799 goto err_free_cq;
2800
2801 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2802 if (err)
2803 goto err_destroy_cq;
2804
2805 err = mlx5e_create_rq(drop_rq, &rq_param);
2806 if (err)
2807 goto err_free_rq;
2808
2809 return 0;
2810
2811 err_free_rq:
2812 mlx5e_free_rq(drop_rq);
2813
2814 err_destroy_cq:
2815 mlx5e_destroy_cq(cq);
2816
2817 err_free_cq:
2818 mlx5e_free_cq(cq);
2819
2820 return err;
2821 }
2822
2823 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2824 {
2825 mlx5e_destroy_rq(drop_rq);
2826 mlx5e_free_rq(drop_rq);
2827 mlx5e_destroy_cq(&drop_rq->cq);
2828 mlx5e_free_cq(&drop_rq->cq);
2829 }
2830
2831 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2832 u32 underlay_qpn, u32 *tisn)
2833 {
2834 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2835 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2836
2837 MLX5_SET(tisc, tisc, prio, tc << 1);
2838 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2839 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2840
2841 if (mlx5_lag_is_lacp_owner(mdev))
2842 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2843
2844 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2845 }
2846
2847 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2848 {
2849 mlx5_core_destroy_tis(mdev, tisn);
2850 }
2851
2852 int mlx5e_create_tises(struct mlx5e_priv *priv)
2853 {
2854 int err;
2855 int tc;
2856
2857 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2858 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2859 if (err)
2860 goto err_close_tises;
2861 }
2862
2863 return 0;
2864
2865 err_close_tises:
2866 for (tc--; tc >= 0; tc--)
2867 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2868
2869 return err;
2870 }
2871
2872 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2873 {
2874 int tc;
2875
2876 for (tc = 0; tc < priv->profile->max_tc; tc++)
2877 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2878 }
2879
2880 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2881 enum mlx5e_traffic_types tt,
2882 u32 *tirc)
2883 {
2884 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2885
2886 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2887
2888 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2889 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2890 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2891 }
2892
2893 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2894 {
2895 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2896
2897 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2898
2899 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2900 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2901 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2902 }
2903
2904 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2905 {
2906 struct mlx5e_tir *tir;
2907 void *tirc;
2908 int inlen;
2909 int i = 0;
2910 int err;
2911 u32 *in;
2912 int tt;
2913
2914 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2915 in = kvzalloc(inlen, GFP_KERNEL);
2916 if (!in)
2917 return -ENOMEM;
2918
2919 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2920 memset(in, 0, inlen);
2921 tir = &priv->indir_tir[tt];
2922 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2923 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2924 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2925 if (err) {
2926 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2927 goto err_destroy_inner_tirs;
2928 }
2929 }
2930
2931 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2932 goto out;
2933
2934 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2935 memset(in, 0, inlen);
2936 tir = &priv->inner_indir_tir[i];
2937 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2938 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2939 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2940 if (err) {
2941 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2942 goto err_destroy_inner_tirs;
2943 }
2944 }
2945
2946 out:
2947 kvfree(in);
2948
2949 return 0;
2950
2951 err_destroy_inner_tirs:
2952 for (i--; i >= 0; i--)
2953 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2954
2955 for (tt--; tt >= 0; tt--)
2956 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2957
2958 kvfree(in);
2959
2960 return err;
2961 }
2962
2963 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2964 {
2965 int nch = priv->profile->max_nch(priv->mdev);
2966 struct mlx5e_tir *tir;
2967 void *tirc;
2968 int inlen;
2969 int err;
2970 u32 *in;
2971 int ix;
2972
2973 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2974 in = kvzalloc(inlen, GFP_KERNEL);
2975 if (!in)
2976 return -ENOMEM;
2977
2978 for (ix = 0; ix < nch; ix++) {
2979 memset(in, 0, inlen);
2980 tir = &priv->direct_tir[ix];
2981 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2982 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2983 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2984 if (err)
2985 goto err_destroy_ch_tirs;
2986 }
2987
2988 kvfree(in);
2989
2990 return 0;
2991
2992 err_destroy_ch_tirs:
2993 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
2994 for (ix--; ix >= 0; ix--)
2995 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2996
2997 kvfree(in);
2998
2999 return err;
3000 }
3001
3002 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3003 {
3004 int i;
3005
3006 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3007 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3008
3009 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3010 return;
3011
3012 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3013 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3014 }
3015
3016 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3017 {
3018 int nch = priv->profile->max_nch(priv->mdev);
3019 int i;
3020
3021 for (i = 0; i < nch; i++)
3022 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3023 }
3024
3025 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3026 {
3027 int err = 0;
3028 int i;
3029
3030 for (i = 0; i < chs->num; i++) {
3031 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3032 if (err)
3033 return err;
3034 }
3035
3036 return 0;
3037 }
3038
3039 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3040 {
3041 int err = 0;
3042 int i;
3043
3044 for (i = 0; i < chs->num; i++) {
3045 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3046 if (err)
3047 return err;
3048 }
3049
3050 return 0;
3051 }
3052
3053 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3054 struct tc_mqprio_qopt *mqprio)
3055 {
3056 struct mlx5e_priv *priv = netdev_priv(netdev);
3057 struct mlx5e_channels new_channels = {};
3058 u8 tc = mqprio->num_tc;
3059 int err = 0;
3060
3061 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3062
3063 if (tc && tc != MLX5E_MAX_NUM_TC)
3064 return -EINVAL;
3065
3066 mutex_lock(&priv->state_lock);
3067
3068 new_channels.params = priv->channels.params;
3069 new_channels.params.num_tc = tc ? tc : 1;
3070
3071 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3072 priv->channels.params = new_channels.params;
3073 goto out;
3074 }
3075
3076 err = mlx5e_open_channels(priv, &new_channels);
3077 if (err)
3078 goto out;
3079
3080 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3081 out:
3082 mutex_unlock(&priv->state_lock);
3083 return err;
3084 }
3085
3086 #ifdef CONFIG_MLX5_ESWITCH
3087 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3088 struct tc_cls_flower_offload *cls_flower)
3089 {
3090 if (cls_flower->common.chain_index)
3091 return -EOPNOTSUPP;
3092
3093 switch (cls_flower->command) {
3094 case TC_CLSFLOWER_REPLACE:
3095 return mlx5e_configure_flower(priv, cls_flower);
3096 case TC_CLSFLOWER_DESTROY:
3097 return mlx5e_delete_flower(priv, cls_flower);
3098 case TC_CLSFLOWER_STATS:
3099 return mlx5e_stats_flower(priv, cls_flower);
3100 default:
3101 return -EOPNOTSUPP;
3102 }
3103 }
3104
3105 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3106 void *cb_priv)
3107 {
3108 struct mlx5e_priv *priv = cb_priv;
3109
3110 if (!tc_can_offload(priv->netdev))
3111 return -EOPNOTSUPP;
3112
3113 switch (type) {
3114 case TC_SETUP_CLSFLOWER:
3115 return mlx5e_setup_tc_cls_flower(priv, type_data);
3116 default:
3117 return -EOPNOTSUPP;
3118 }
3119 }
3120
3121 static int mlx5e_setup_tc_block(struct net_device *dev,
3122 struct tc_block_offload *f)
3123 {
3124 struct mlx5e_priv *priv = netdev_priv(dev);
3125
3126 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3127 return -EOPNOTSUPP;
3128
3129 switch (f->command) {
3130 case TC_BLOCK_BIND:
3131 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3132 priv, priv);
3133 case TC_BLOCK_UNBIND:
3134 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3135 priv);
3136 return 0;
3137 default:
3138 return -EOPNOTSUPP;
3139 }
3140 }
3141 #endif
3142
3143 int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3144 void *type_data)
3145 {
3146 switch (type) {
3147 #ifdef CONFIG_MLX5_ESWITCH
3148 case TC_SETUP_BLOCK:
3149 return mlx5e_setup_tc_block(dev, type_data);
3150 #endif
3151 case TC_SETUP_QDISC_MQPRIO:
3152 return mlx5e_setup_tc_mqprio(dev, type_data);
3153 default:
3154 return -EOPNOTSUPP;
3155 }
3156 }
3157
3158 static void
3159 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3160 {
3161 struct mlx5e_priv *priv = netdev_priv(dev);
3162 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3163 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3164 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3165
3166 if (mlx5e_is_uplink_rep(priv)) {
3167 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3168 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3169 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3170 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3171 } else {
3172 stats->rx_packets = sstats->rx_packets;
3173 stats->rx_bytes = sstats->rx_bytes;
3174 stats->tx_packets = sstats->tx_packets;
3175 stats->tx_bytes = sstats->tx_bytes;
3176 stats->tx_dropped = sstats->tx_queue_dropped;
3177 }
3178
3179 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3180
3181 stats->rx_length_errors =
3182 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3183 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3184 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3185 stats->rx_crc_errors =
3186 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3187 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3188 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3189 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3190 stats->rx_frame_errors;
3191 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3192
3193 /* vport multicast also counts packets that are dropped due to steering
3194 * or rx out of buffer
3195 */
3196 stats->multicast =
3197 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3198 }
3199
3200 static void mlx5e_set_rx_mode(struct net_device *dev)
3201 {
3202 struct mlx5e_priv *priv = netdev_priv(dev);
3203
3204 queue_work(priv->wq, &priv->set_rx_mode_work);
3205 }
3206
3207 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3208 {
3209 struct mlx5e_priv *priv = netdev_priv(netdev);
3210 struct sockaddr *saddr = addr;
3211
3212 if (!is_valid_ether_addr(saddr->sa_data))
3213 return -EADDRNOTAVAIL;
3214
3215 netif_addr_lock_bh(netdev);
3216 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3217 netif_addr_unlock_bh(netdev);
3218
3219 queue_work(priv->wq, &priv->set_rx_mode_work);
3220
3221 return 0;
3222 }
3223
3224 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
3225 do { \
3226 if (enable) \
3227 netdev->features |= feature; \
3228 else \
3229 netdev->features &= ~feature; \
3230 } while (0)
3231
3232 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3233
3234 static int set_feature_lro(struct net_device *netdev, bool enable)
3235 {
3236 struct mlx5e_priv *priv = netdev_priv(netdev);
3237 struct mlx5e_channels new_channels = {};
3238 int err = 0;
3239 bool reset;
3240
3241 mutex_lock(&priv->state_lock);
3242
3243 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3244 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3245
3246 new_channels.params = priv->channels.params;
3247 new_channels.params.lro_en = enable;
3248
3249 if (!reset) {
3250 priv->channels.params = new_channels.params;
3251 err = mlx5e_modify_tirs_lro(priv);
3252 goto out;
3253 }
3254
3255 err = mlx5e_open_channels(priv, &new_channels);
3256 if (err)
3257 goto out;
3258
3259 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3260 out:
3261 mutex_unlock(&priv->state_lock);
3262 return err;
3263 }
3264
3265 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3266 {
3267 struct mlx5e_priv *priv = netdev_priv(netdev);
3268
3269 if (enable)
3270 mlx5e_enable_cvlan_filter(priv);
3271 else
3272 mlx5e_disable_cvlan_filter(priv);
3273
3274 return 0;
3275 }
3276
3277 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3278 {
3279 struct mlx5e_priv *priv = netdev_priv(netdev);
3280
3281 if (!enable && mlx5e_tc_num_filters(priv)) {
3282 netdev_err(netdev,
3283 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3284 return -EINVAL;
3285 }
3286
3287 return 0;
3288 }
3289
3290 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3291 {
3292 struct mlx5e_priv *priv = netdev_priv(netdev);
3293 struct mlx5_core_dev *mdev = priv->mdev;
3294
3295 return mlx5_set_port_fcs(mdev, !enable);
3296 }
3297
3298 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3299 {
3300 struct mlx5e_priv *priv = netdev_priv(netdev);
3301 int err;
3302
3303 mutex_lock(&priv->state_lock);
3304
3305 priv->channels.params.scatter_fcs_en = enable;
3306 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3307 if (err)
3308 priv->channels.params.scatter_fcs_en = !enable;
3309
3310 mutex_unlock(&priv->state_lock);
3311
3312 return err;
3313 }
3314
3315 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3316 {
3317 struct mlx5e_priv *priv = netdev_priv(netdev);
3318 int err = 0;
3319
3320 mutex_lock(&priv->state_lock);
3321
3322 priv->channels.params.vlan_strip_disable = !enable;
3323 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3324 goto unlock;
3325
3326 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3327 if (err)
3328 priv->channels.params.vlan_strip_disable = enable;
3329
3330 unlock:
3331 mutex_unlock(&priv->state_lock);
3332
3333 return err;
3334 }
3335
3336 #ifdef CONFIG_RFS_ACCEL
3337 static int set_feature_arfs(struct net_device *netdev, bool enable)
3338 {
3339 struct mlx5e_priv *priv = netdev_priv(netdev);
3340 int err;
3341
3342 if (enable)
3343 err = mlx5e_arfs_enable(priv);
3344 else
3345 err = mlx5e_arfs_disable(priv);
3346
3347 return err;
3348 }
3349 #endif
3350
3351 static int mlx5e_handle_feature(struct net_device *netdev,
3352 netdev_features_t wanted_features,
3353 netdev_features_t feature,
3354 mlx5e_feature_handler feature_handler)
3355 {
3356 netdev_features_t changes = wanted_features ^ netdev->features;
3357 bool enable = !!(wanted_features & feature);
3358 int err;
3359
3360 if (!(changes & feature))
3361 return 0;
3362
3363 err = feature_handler(netdev, enable);
3364 if (err) {
3365 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3366 enable ? "Enable" : "Disable", &feature, err);
3367 return err;
3368 }
3369
3370 MLX5E_SET_FEATURE(netdev, feature, enable);
3371 return 0;
3372 }
3373
3374 static int mlx5e_set_features(struct net_device *netdev,
3375 netdev_features_t features)
3376 {
3377 int err;
3378
3379 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3380 set_feature_lro);
3381 err |= mlx5e_handle_feature(netdev, features,
3382 NETIF_F_HW_VLAN_CTAG_FILTER,
3383 set_feature_cvlan_filter);
3384 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3385 set_feature_tc_num_filters);
3386 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3387 set_feature_rx_all);
3388 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3389 set_feature_rx_fcs);
3390 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3391 set_feature_rx_vlan);
3392 #ifdef CONFIG_RFS_ACCEL
3393 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3394 set_feature_arfs);
3395 #endif
3396
3397 return err ? -EINVAL : 0;
3398 }
3399
3400 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3401 netdev_features_t features)
3402 {
3403 struct mlx5e_priv *priv = netdev_priv(netdev);
3404
3405 mutex_lock(&priv->state_lock);
3406 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3407 /* HW strips the outer C-tag header, this is a problem
3408 * for S-tag traffic.
3409 */
3410 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3411 if (!priv->channels.params.vlan_strip_disable)
3412 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3413 }
3414 mutex_unlock(&priv->state_lock);
3415
3416 return features;
3417 }
3418
3419 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3420 {
3421 struct mlx5e_priv *priv = netdev_priv(netdev);
3422 struct mlx5e_channels new_channels = {};
3423 int curr_mtu;
3424 int err = 0;
3425 bool reset;
3426
3427 mutex_lock(&priv->state_lock);
3428
3429 reset = !priv->channels.params.lro_en &&
3430 (priv->channels.params.rq_wq_type !=
3431 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3432
3433 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3434
3435 curr_mtu = netdev->mtu;
3436 netdev->mtu = new_mtu;
3437
3438 if (!reset) {
3439 mlx5e_set_dev_port_mtu(priv);
3440 goto out;
3441 }
3442
3443 new_channels.params = priv->channels.params;
3444 err = mlx5e_open_channels(priv, &new_channels);
3445 if (err) {
3446 netdev->mtu = curr_mtu;
3447 goto out;
3448 }
3449
3450 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3451
3452 out:
3453 mutex_unlock(&priv->state_lock);
3454 return err;
3455 }
3456
3457 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3458 {
3459 struct hwtstamp_config config;
3460 int err;
3461
3462 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3463 return -EOPNOTSUPP;
3464
3465 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3466 return -EFAULT;
3467
3468 /* TX HW timestamp */
3469 switch (config.tx_type) {
3470 case HWTSTAMP_TX_OFF:
3471 case HWTSTAMP_TX_ON:
3472 break;
3473 default:
3474 return -ERANGE;
3475 }
3476
3477 mutex_lock(&priv->state_lock);
3478 /* RX HW timestamp */
3479 switch (config.rx_filter) {
3480 case HWTSTAMP_FILTER_NONE:
3481 /* Reset CQE compression to Admin default */
3482 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3483 break;
3484 case HWTSTAMP_FILTER_ALL:
3485 case HWTSTAMP_FILTER_SOME:
3486 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3487 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3488 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3489 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3490 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3491 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3492 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3493 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3494 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3495 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3496 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3497 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3498 case HWTSTAMP_FILTER_NTP_ALL:
3499 /* Disable CQE compression */
3500 netdev_warn(priv->netdev, "Disabling cqe compression");
3501 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3502 if (err) {
3503 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3504 mutex_unlock(&priv->state_lock);
3505 return err;
3506 }
3507 config.rx_filter = HWTSTAMP_FILTER_ALL;
3508 break;
3509 default:
3510 mutex_unlock(&priv->state_lock);
3511 return -ERANGE;
3512 }
3513
3514 memcpy(&priv->tstamp, &config, sizeof(config));
3515 mutex_unlock(&priv->state_lock);
3516
3517 return copy_to_user(ifr->ifr_data, &config,
3518 sizeof(config)) ? -EFAULT : 0;
3519 }
3520
3521 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3522 {
3523 struct hwtstamp_config *cfg = &priv->tstamp;
3524
3525 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3526 return -EOPNOTSUPP;
3527
3528 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3529 }
3530
3531 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3532 {
3533 struct mlx5e_priv *priv = netdev_priv(dev);
3534
3535 switch (cmd) {
3536 case SIOCSHWTSTAMP:
3537 return mlx5e_hwstamp_set(priv, ifr);
3538 case SIOCGHWTSTAMP:
3539 return mlx5e_hwstamp_get(priv, ifr);
3540 default:
3541 return -EOPNOTSUPP;
3542 }
3543 }
3544
3545 #ifdef CONFIG_MLX5_ESWITCH
3546 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3547 {
3548 struct mlx5e_priv *priv = netdev_priv(dev);
3549 struct mlx5_core_dev *mdev = priv->mdev;
3550
3551 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3552 }
3553
3554 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3555 __be16 vlan_proto)
3556 {
3557 struct mlx5e_priv *priv = netdev_priv(dev);
3558 struct mlx5_core_dev *mdev = priv->mdev;
3559
3560 if (vlan_proto != htons(ETH_P_8021Q))
3561 return -EPROTONOSUPPORT;
3562
3563 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3564 vlan, qos);
3565 }
3566
3567 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3568 {
3569 struct mlx5e_priv *priv = netdev_priv(dev);
3570 struct mlx5_core_dev *mdev = priv->mdev;
3571
3572 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3573 }
3574
3575 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3576 {
3577 struct mlx5e_priv *priv = netdev_priv(dev);
3578 struct mlx5_core_dev *mdev = priv->mdev;
3579
3580 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3581 }
3582
3583 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3584 int max_tx_rate)
3585 {
3586 struct mlx5e_priv *priv = netdev_priv(dev);
3587 struct mlx5_core_dev *mdev = priv->mdev;
3588
3589 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3590 max_tx_rate, min_tx_rate);
3591 }
3592
3593 static int mlx5_vport_link2ifla(u8 esw_link)
3594 {
3595 switch (esw_link) {
3596 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3597 return IFLA_VF_LINK_STATE_DISABLE;
3598 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3599 return IFLA_VF_LINK_STATE_ENABLE;
3600 }
3601 return IFLA_VF_LINK_STATE_AUTO;
3602 }
3603
3604 static int mlx5_ifla_link2vport(u8 ifla_link)
3605 {
3606 switch (ifla_link) {
3607 case IFLA_VF_LINK_STATE_DISABLE:
3608 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3609 case IFLA_VF_LINK_STATE_ENABLE:
3610 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3611 }
3612 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3613 }
3614
3615 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3616 int link_state)
3617 {
3618 struct mlx5e_priv *priv = netdev_priv(dev);
3619 struct mlx5_core_dev *mdev = priv->mdev;
3620
3621 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3622 mlx5_ifla_link2vport(link_state));
3623 }
3624
3625 static int mlx5e_get_vf_config(struct net_device *dev,
3626 int vf, struct ifla_vf_info *ivi)
3627 {
3628 struct mlx5e_priv *priv = netdev_priv(dev);
3629 struct mlx5_core_dev *mdev = priv->mdev;
3630 int err;
3631
3632 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3633 if (err)
3634 return err;
3635 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3636 return 0;
3637 }
3638
3639 static int mlx5e_get_vf_stats(struct net_device *dev,
3640 int vf, struct ifla_vf_stats *vf_stats)
3641 {
3642 struct mlx5e_priv *priv = netdev_priv(dev);
3643 struct mlx5_core_dev *mdev = priv->mdev;
3644
3645 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3646 vf_stats);
3647 }
3648 #endif
3649
3650 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3651 struct udp_tunnel_info *ti)
3652 {
3653 struct mlx5e_priv *priv = netdev_priv(netdev);
3654
3655 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3656 return;
3657
3658 if (!mlx5e_vxlan_allowed(priv->mdev))
3659 return;
3660
3661 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3662 }
3663
3664 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3665 struct udp_tunnel_info *ti)
3666 {
3667 struct mlx5e_priv *priv = netdev_priv(netdev);
3668
3669 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3670 return;
3671
3672 if (!mlx5e_vxlan_allowed(priv->mdev))
3673 return;
3674
3675 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3676 }
3677
3678 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3679 struct sk_buff *skb,
3680 netdev_features_t features)
3681 {
3682 struct udphdr *udph;
3683 u8 proto;
3684 u16 port;
3685
3686 switch (vlan_get_protocol(skb)) {
3687 case htons(ETH_P_IP):
3688 proto = ip_hdr(skb)->protocol;
3689 break;
3690 case htons(ETH_P_IPV6):
3691 proto = ipv6_hdr(skb)->nexthdr;
3692 break;
3693 default:
3694 goto out;
3695 }
3696
3697 switch (proto) {
3698 case IPPROTO_GRE:
3699 return features;
3700 case IPPROTO_UDP:
3701 udph = udp_hdr(skb);
3702 port = be16_to_cpu(udph->dest);
3703
3704 /* Verify if UDP port is being offloaded by HW */
3705 if (mlx5e_vxlan_lookup_port(priv, port))
3706 return features;
3707 }
3708
3709 out:
3710 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3711 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3712 }
3713
3714 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3715 struct net_device *netdev,
3716 netdev_features_t features)
3717 {
3718 struct mlx5e_priv *priv = netdev_priv(netdev);
3719
3720 features = vlan_features_check(skb, features);
3721 features = vxlan_features_check(skb, features);
3722
3723 #ifdef CONFIG_MLX5_EN_IPSEC
3724 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3725 return features;
3726 #endif
3727
3728 /* Validate if the tunneled packet is being offloaded by HW */
3729 if (skb->encapsulation &&
3730 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3731 return mlx5e_tunnel_features_check(priv, skb, features);
3732
3733 return features;
3734 }
3735
3736 static void mlx5e_tx_timeout(struct net_device *dev)
3737 {
3738 struct mlx5e_priv *priv = netdev_priv(dev);
3739 bool sched_work = false;
3740 int i;
3741
3742 netdev_err(dev, "TX timeout detected\n");
3743
3744 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3745 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3746
3747 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3748 continue;
3749 sched_work = true;
3750 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3751 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3752 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3753 }
3754
3755 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3756 schedule_work(&priv->tx_timeout_work);
3757 }
3758
3759 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3760 {
3761 struct mlx5e_priv *priv = netdev_priv(netdev);
3762 struct bpf_prog *old_prog;
3763 int err = 0;
3764 bool reset, was_opened;
3765 int i;
3766
3767 mutex_lock(&priv->state_lock);
3768
3769 if ((netdev->features & NETIF_F_LRO) && prog) {
3770 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3771 err = -EINVAL;
3772 goto unlock;
3773 }
3774
3775 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3776 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3777 err = -EINVAL;
3778 goto unlock;
3779 }
3780
3781 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3782 /* no need for full reset when exchanging programs */
3783 reset = (!priv->channels.params.xdp_prog || !prog);
3784
3785 if (was_opened && reset)
3786 mlx5e_close_locked(netdev);
3787 if (was_opened && !reset) {
3788 /* num_channels is invariant here, so we can take the
3789 * batched reference right upfront.
3790 */
3791 prog = bpf_prog_add(prog, priv->channels.num);
3792 if (IS_ERR(prog)) {
3793 err = PTR_ERR(prog);
3794 goto unlock;
3795 }
3796 }
3797
3798 /* exchange programs, extra prog reference we got from caller
3799 * as long as we don't fail from this point onwards.
3800 */
3801 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3802 if (old_prog)
3803 bpf_prog_put(old_prog);
3804
3805 if (reset) /* change RQ type according to priv->xdp_prog */
3806 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
3807
3808 if (was_opened && reset)
3809 mlx5e_open_locked(netdev);
3810
3811 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3812 goto unlock;
3813
3814 /* exchanging programs w/o reset, we update ref counts on behalf
3815 * of the channels RQs here.
3816 */
3817 for (i = 0; i < priv->channels.num; i++) {
3818 struct mlx5e_channel *c = priv->channels.c[i];
3819
3820 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3821 napi_synchronize(&c->napi);
3822 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3823
3824 old_prog = xchg(&c->rq.xdp_prog, prog);
3825
3826 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3827 /* napi_schedule in case we have missed anything */
3828 napi_schedule(&c->napi);
3829
3830 if (old_prog)
3831 bpf_prog_put(old_prog);
3832 }
3833
3834 unlock:
3835 mutex_unlock(&priv->state_lock);
3836 return err;
3837 }
3838
3839 static u32 mlx5e_xdp_query(struct net_device *dev)
3840 {
3841 struct mlx5e_priv *priv = netdev_priv(dev);
3842 const struct bpf_prog *xdp_prog;
3843 u32 prog_id = 0;
3844
3845 mutex_lock(&priv->state_lock);
3846 xdp_prog = priv->channels.params.xdp_prog;
3847 if (xdp_prog)
3848 prog_id = xdp_prog->aux->id;
3849 mutex_unlock(&priv->state_lock);
3850
3851 return prog_id;
3852 }
3853
3854 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3855 {
3856 switch (xdp->command) {
3857 case XDP_SETUP_PROG:
3858 return mlx5e_xdp_set(dev, xdp->prog);
3859 case XDP_QUERY_PROG:
3860 xdp->prog_id = mlx5e_xdp_query(dev);
3861 xdp->prog_attached = !!xdp->prog_id;
3862 return 0;
3863 default:
3864 return -EINVAL;
3865 }
3866 }
3867
3868 #ifdef CONFIG_NET_POLL_CONTROLLER
3869 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3870 * reenabling interrupts.
3871 */
3872 static void mlx5e_netpoll(struct net_device *dev)
3873 {
3874 struct mlx5e_priv *priv = netdev_priv(dev);
3875 struct mlx5e_channels *chs = &priv->channels;
3876
3877 int i;
3878
3879 for (i = 0; i < chs->num; i++)
3880 napi_schedule(&chs->c[i]->napi);
3881 }
3882 #endif
3883
3884 static const struct net_device_ops mlx5e_netdev_ops = {
3885 .ndo_open = mlx5e_open,
3886 .ndo_stop = mlx5e_close,
3887 .ndo_start_xmit = mlx5e_xmit,
3888 .ndo_setup_tc = mlx5e_setup_tc,
3889 .ndo_select_queue = mlx5e_select_queue,
3890 .ndo_get_stats64 = mlx5e_get_stats,
3891 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3892 .ndo_set_mac_address = mlx5e_set_mac,
3893 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3894 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3895 .ndo_set_features = mlx5e_set_features,
3896 .ndo_fix_features = mlx5e_fix_features,
3897 .ndo_change_mtu = mlx5e_change_mtu,
3898 .ndo_do_ioctl = mlx5e_ioctl,
3899 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3900 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3901 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3902 .ndo_features_check = mlx5e_features_check,
3903 #ifdef CONFIG_RFS_ACCEL
3904 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3905 #endif
3906 .ndo_tx_timeout = mlx5e_tx_timeout,
3907 .ndo_bpf = mlx5e_xdp,
3908 #ifdef CONFIG_NET_POLL_CONTROLLER
3909 .ndo_poll_controller = mlx5e_netpoll,
3910 #endif
3911 #ifdef CONFIG_MLX5_ESWITCH
3912 /* SRIOV E-Switch NDOs */
3913 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3914 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
3915 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
3916 .ndo_set_vf_trust = mlx5e_set_vf_trust,
3917 .ndo_set_vf_rate = mlx5e_set_vf_rate,
3918 .ndo_get_vf_config = mlx5e_get_vf_config,
3919 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3920 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3921 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3922 .ndo_get_offload_stats = mlx5e_get_offload_stats,
3923 #endif
3924 };
3925
3926 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3927 {
3928 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3929 return -EOPNOTSUPP;
3930 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3931 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3932 !MLX5_CAP_ETH(mdev, csum_cap) ||
3933 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3934 !MLX5_CAP_ETH(mdev, vlan_cap) ||
3935 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3936 MLX5_CAP_FLOWTABLE(mdev,
3937 flow_table_properties_nic_receive.max_ft_level)
3938 < 3) {
3939 mlx5_core_warn(mdev,
3940 "Not creating net device, some required device capabilities are missing\n");
3941 return -EOPNOTSUPP;
3942 }
3943 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3944 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3945 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3946 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
3947
3948 return 0;
3949 }
3950
3951 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3952 {
3953 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3954
3955 return bf_buf_size -
3956 sizeof(struct mlx5e_tx_wqe) +
3957 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3958 }
3959
3960 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
3961 int num_channels)
3962 {
3963 int i;
3964
3965 for (i = 0; i < len; i++)
3966 indirection_rqt[i] = i % num_channels;
3967 }
3968
3969 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3970 {
3971 enum pcie_link_width width;
3972 enum pci_bus_speed speed;
3973 int err = 0;
3974
3975 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3976 if (err)
3977 return err;
3978
3979 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3980 return -EINVAL;
3981
3982 switch (speed) {
3983 case PCIE_SPEED_2_5GT:
3984 *pci_bw = 2500 * width;
3985 break;
3986 case PCIE_SPEED_5_0GT:
3987 *pci_bw = 5000 * width;
3988 break;
3989 case PCIE_SPEED_8_0GT:
3990 *pci_bw = 8000 * width;
3991 break;
3992 default:
3993 return -EINVAL;
3994 }
3995
3996 return 0;
3997 }
3998
3999 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
4000 {
4001 return (link_speed && pci_bw &&
4002 (pci_bw < 40000) && (pci_bw < link_speed));
4003 }
4004
4005 static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
4006 {
4007 return !(link_speed && pci_bw &&
4008 (pci_bw <= 16000) && (pci_bw < link_speed));
4009 }
4010
4011 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4012 {
4013 params->tx_cq_moderation.cq_period_mode = cq_period_mode;
4014
4015 params->tx_cq_moderation.pkts =
4016 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4017 params->tx_cq_moderation.usec =
4018 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4019
4020 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4021 params->tx_cq_moderation.usec =
4022 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4023
4024 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4025 params->tx_cq_moderation.cq_period_mode ==
4026 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4027 }
4028
4029 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4030 {
4031 params->rx_cq_moderation.cq_period_mode = cq_period_mode;
4032
4033 params->rx_cq_moderation.pkts =
4034 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4035 params->rx_cq_moderation.usec =
4036 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4037
4038 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4039 params->rx_cq_moderation.usec =
4040 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4041
4042 if (params->rx_am_enabled)
4043 params->rx_cq_moderation =
4044 mlx5e_am_get_def_profile(cq_period_mode);
4045
4046 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4047 params->rx_cq_moderation.cq_period_mode ==
4048 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4049 }
4050
4051 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4052 {
4053 int i;
4054
4055 /* The supported periods are organized in ascending order */
4056 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4057 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4058 break;
4059
4060 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4061 }
4062
4063 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4064 struct mlx5e_params *params,
4065 u16 max_channels)
4066 {
4067 u8 cq_period_mode = 0;
4068 u32 link_speed = 0;
4069 u32 pci_bw = 0;
4070
4071 params->num_channels = max_channels;
4072 params->num_tc = 1;
4073
4074 mlx5e_get_max_linkspeed(mdev, &link_speed);
4075 mlx5e_get_pci_bw(mdev, &pci_bw);
4076 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
4077 link_speed, pci_bw);
4078
4079 /* SQ */
4080 params->log_sq_size = is_kdump_kernel() ?
4081 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4082 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4083
4084 /* set CQE compression */
4085 params->rx_cqe_compress_def = false;
4086 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4087 MLX5_CAP_GEN(mdev, vport_group_manager))
4088 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
4089
4090 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4091
4092 /* RQ */
4093 mlx5e_set_rq_params(mdev, params);
4094
4095 /* HW LRO */
4096
4097 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4098 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4099 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
4100 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4101
4102 /* CQ moderation params */
4103 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4104 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4105 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4106 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4107 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
4108 mlx5e_set_tx_cq_mode_params(params, cq_period_mode);
4109
4110 /* TX inline */
4111 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
4112 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4113
4114 /* RSS */
4115 params->rss_hfunc = ETH_RSS_HASH_XOR;
4116 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4117 mlx5e_build_default_indir_rqt(params->indirection_rqt,
4118 MLX5E_INDIR_RQT_SIZE, max_channels);
4119 }
4120
4121 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4122 struct net_device *netdev,
4123 const struct mlx5e_profile *profile,
4124 void *ppriv)
4125 {
4126 struct mlx5e_priv *priv = netdev_priv(netdev);
4127
4128 priv->mdev = mdev;
4129 priv->netdev = netdev;
4130 priv->profile = profile;
4131 priv->ppriv = ppriv;
4132 priv->msglevel = MLX5E_MSG_LEVEL;
4133 priv->hard_mtu = MLX5E_ETH_HARD_MTU;
4134
4135 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
4136
4137 mutex_init(&priv->state_lock);
4138
4139 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4140 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4141 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4142 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4143 }
4144
4145 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4146 {
4147 struct mlx5e_priv *priv = netdev_priv(netdev);
4148
4149 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4150 if (is_zero_ether_addr(netdev->dev_addr) &&
4151 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4152 eth_hw_addr_random(netdev);
4153 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4154 }
4155 }
4156
4157 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4158 static const struct switchdev_ops mlx5e_switchdev_ops = {
4159 .switchdev_port_attr_get = mlx5e_attr_get,
4160 };
4161 #endif
4162
4163 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4164 {
4165 struct mlx5e_priv *priv = netdev_priv(netdev);
4166 struct mlx5_core_dev *mdev = priv->mdev;
4167 bool fcs_supported;
4168 bool fcs_enabled;
4169
4170 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4171
4172 netdev->netdev_ops = &mlx5e_netdev_ops;
4173
4174 #ifdef CONFIG_MLX5_CORE_EN_DCB
4175 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4176 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4177 #endif
4178
4179 netdev->watchdog_timeo = 15 * HZ;
4180
4181 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4182
4183 netdev->vlan_features |= NETIF_F_SG;
4184 netdev->vlan_features |= NETIF_F_IP_CSUM;
4185 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4186 netdev->vlan_features |= NETIF_F_GRO;
4187 netdev->vlan_features |= NETIF_F_TSO;
4188 netdev->vlan_features |= NETIF_F_TSO6;
4189 netdev->vlan_features |= NETIF_F_RXCSUM;
4190 netdev->vlan_features |= NETIF_F_RXHASH;
4191
4192 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4193 netdev->vlan_features |= NETIF_F_LRO;
4194
4195 netdev->hw_features = netdev->vlan_features;
4196 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4197 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4198 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4199 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4200
4201 if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4202 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4203 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4204 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4205 netdev->hw_enc_features |= NETIF_F_TSO;
4206 netdev->hw_enc_features |= NETIF_F_TSO6;
4207 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4208 }
4209
4210 if (mlx5e_vxlan_allowed(mdev)) {
4211 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4212 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4213 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4214 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4215 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4216 }
4217
4218 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4219 netdev->hw_features |= NETIF_F_GSO_GRE |
4220 NETIF_F_GSO_GRE_CSUM;
4221 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4222 NETIF_F_GSO_GRE_CSUM;
4223 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4224 NETIF_F_GSO_GRE_CSUM;
4225 }
4226
4227 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4228
4229 if (fcs_supported)
4230 netdev->hw_features |= NETIF_F_RXALL;
4231
4232 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4233 netdev->hw_features |= NETIF_F_RXFCS;
4234
4235 netdev->features = netdev->hw_features;
4236 if (!priv->channels.params.lro_en)
4237 netdev->features &= ~NETIF_F_LRO;
4238
4239 if (fcs_enabled)
4240 netdev->features &= ~NETIF_F_RXALL;
4241
4242 if (!priv->channels.params.scatter_fcs_en)
4243 netdev->features &= ~NETIF_F_RXFCS;
4244
4245 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4246 if (FT_CAP(flow_modify_en) &&
4247 FT_CAP(modify_root) &&
4248 FT_CAP(identified_miss_table_mode) &&
4249 FT_CAP(flow_table_modify)) {
4250 netdev->hw_features |= NETIF_F_HW_TC;
4251 #ifdef CONFIG_RFS_ACCEL
4252 netdev->hw_features |= NETIF_F_NTUPLE;
4253 #endif
4254 }
4255
4256 netdev->features |= NETIF_F_HIGHDMA;
4257 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4258
4259 netdev->priv_flags |= IFF_UNICAST_FLT;
4260
4261 mlx5e_set_netdev_dev_addr(netdev);
4262
4263 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4264 if (MLX5_VPORT_MANAGER(mdev))
4265 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4266 #endif
4267
4268 mlx5e_ipsec_build_netdev(priv);
4269 }
4270
4271 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4272 {
4273 struct mlx5_core_dev *mdev = priv->mdev;
4274 int err;
4275
4276 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4277 if (err) {
4278 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4279 priv->q_counter = 0;
4280 }
4281 }
4282
4283 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4284 {
4285 if (!priv->q_counter)
4286 return;
4287
4288 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4289 }
4290
4291 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4292 struct net_device *netdev,
4293 const struct mlx5e_profile *profile,
4294 void *ppriv)
4295 {
4296 struct mlx5e_priv *priv = netdev_priv(netdev);
4297 int err;
4298
4299 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4300 err = mlx5e_ipsec_init(priv);
4301 if (err)
4302 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4303 mlx5e_build_nic_netdev(netdev);
4304 mlx5e_vxlan_init(priv);
4305 }
4306
4307 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4308 {
4309 mlx5e_ipsec_cleanup(priv);
4310 mlx5e_vxlan_cleanup(priv);
4311
4312 if (priv->channels.params.xdp_prog)
4313 bpf_prog_put(priv->channels.params.xdp_prog);
4314 }
4315
4316 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4317 {
4318 struct mlx5_core_dev *mdev = priv->mdev;
4319 int err;
4320
4321 err = mlx5e_create_indirect_rqt(priv);
4322 if (err)
4323 return err;
4324
4325 err = mlx5e_create_direct_rqts(priv);
4326 if (err)
4327 goto err_destroy_indirect_rqts;
4328
4329 err = mlx5e_create_indirect_tirs(priv);
4330 if (err)
4331 goto err_destroy_direct_rqts;
4332
4333 err = mlx5e_create_direct_tirs(priv);
4334 if (err)
4335 goto err_destroy_indirect_tirs;
4336
4337 err = mlx5e_create_flow_steering(priv);
4338 if (err) {
4339 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4340 goto err_destroy_direct_tirs;
4341 }
4342
4343 err = mlx5e_tc_init(priv);
4344 if (err)
4345 goto err_destroy_flow_steering;
4346
4347 return 0;
4348
4349 err_destroy_flow_steering:
4350 mlx5e_destroy_flow_steering(priv);
4351 err_destroy_direct_tirs:
4352 mlx5e_destroy_direct_tirs(priv);
4353 err_destroy_indirect_tirs:
4354 mlx5e_destroy_indirect_tirs(priv);
4355 err_destroy_direct_rqts:
4356 mlx5e_destroy_direct_rqts(priv);
4357 err_destroy_indirect_rqts:
4358 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4359 return err;
4360 }
4361
4362 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4363 {
4364 mlx5e_tc_cleanup(priv);
4365 mlx5e_destroy_flow_steering(priv);
4366 mlx5e_destroy_direct_tirs(priv);
4367 mlx5e_destroy_indirect_tirs(priv);
4368 mlx5e_destroy_direct_rqts(priv);
4369 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4370 }
4371
4372 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4373 {
4374 int err;
4375
4376 err = mlx5e_create_tises(priv);
4377 if (err) {
4378 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4379 return err;
4380 }
4381
4382 #ifdef CONFIG_MLX5_CORE_EN_DCB
4383 mlx5e_dcbnl_initialize(priv);
4384 #endif
4385 return 0;
4386 }
4387
4388 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4389 {
4390 struct net_device *netdev = priv->netdev;
4391 struct mlx5_core_dev *mdev = priv->mdev;
4392 u16 max_mtu;
4393
4394 mlx5e_init_l2_addr(priv);
4395
4396 /* Marking the link as currently not needed by the Driver */
4397 if (!netif_running(netdev))
4398 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4399
4400 /* MTU range: 68 - hw-specific max */
4401 netdev->min_mtu = ETH_MIN_MTU;
4402 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4403 netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
4404 mlx5e_set_dev_port_mtu(priv);
4405
4406 mlx5_lag_add(mdev, netdev);
4407
4408 mlx5e_enable_async_events(priv);
4409
4410 if (MLX5_VPORT_MANAGER(priv->mdev))
4411 mlx5e_register_vport_reps(priv);
4412
4413 if (netdev->reg_state != NETREG_REGISTERED)
4414 return;
4415 #ifdef CONFIG_MLX5_CORE_EN_DCB
4416 mlx5e_dcbnl_init_app(priv);
4417 #endif
4418 /* Device already registered: sync netdev system state */
4419 if (mlx5e_vxlan_allowed(mdev)) {
4420 rtnl_lock();
4421 udp_tunnel_get_rx_info(netdev);
4422 rtnl_unlock();
4423 }
4424
4425 queue_work(priv->wq, &priv->set_rx_mode_work);
4426
4427 rtnl_lock();
4428 if (netif_running(netdev))
4429 mlx5e_open(netdev);
4430 netif_device_attach(netdev);
4431 rtnl_unlock();
4432 }
4433
4434 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4435 {
4436 struct mlx5_core_dev *mdev = priv->mdev;
4437
4438 #ifdef CONFIG_MLX5_CORE_EN_DCB
4439 if (priv->netdev->reg_state == NETREG_REGISTERED)
4440 mlx5e_dcbnl_delete_app(priv);
4441 #endif
4442
4443 rtnl_lock();
4444 if (netif_running(priv->netdev))
4445 mlx5e_close(priv->netdev);
4446 netif_device_detach(priv->netdev);
4447 rtnl_unlock();
4448
4449 queue_work(priv->wq, &priv->set_rx_mode_work);
4450
4451 if (MLX5_VPORT_MANAGER(priv->mdev))
4452 mlx5e_unregister_vport_reps(priv);
4453
4454 mlx5e_disable_async_events(priv);
4455 mlx5_lag_remove(mdev);
4456 }
4457
4458 static const struct mlx5e_profile mlx5e_nic_profile = {
4459 .init = mlx5e_nic_init,
4460 .cleanup = mlx5e_nic_cleanup,
4461 .init_rx = mlx5e_init_nic_rx,
4462 .cleanup_rx = mlx5e_cleanup_nic_rx,
4463 .init_tx = mlx5e_init_nic_tx,
4464 .cleanup_tx = mlx5e_cleanup_nic_tx,
4465 .enable = mlx5e_nic_enable,
4466 .disable = mlx5e_nic_disable,
4467 .update_stats = mlx5e_update_ndo_stats,
4468 .max_nch = mlx5e_get_max_num_channels,
4469 .update_carrier = mlx5e_update_carrier,
4470 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4471 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4472 .max_tc = MLX5E_MAX_NUM_TC,
4473 };
4474
4475 /* mlx5e generic netdev management API (move to en_common.c) */
4476
4477 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4478 const struct mlx5e_profile *profile,
4479 void *ppriv)
4480 {
4481 int nch = profile->max_nch(mdev);
4482 struct net_device *netdev;
4483 struct mlx5e_priv *priv;
4484
4485 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4486 nch * profile->max_tc,
4487 nch);
4488 if (!netdev) {
4489 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4490 return NULL;
4491 }
4492
4493 #ifdef CONFIG_RFS_ACCEL
4494 netdev->rx_cpu_rmap = mdev->rmap;
4495 #endif
4496
4497 profile->init(mdev, netdev, profile, ppriv);
4498
4499 netif_carrier_off(netdev);
4500
4501 priv = netdev_priv(netdev);
4502
4503 priv->wq = create_singlethread_workqueue("mlx5e");
4504 if (!priv->wq)
4505 goto err_cleanup_nic;
4506
4507 return netdev;
4508
4509 err_cleanup_nic:
4510 if (profile->cleanup)
4511 profile->cleanup(priv);
4512 free_netdev(netdev);
4513
4514 return NULL;
4515 }
4516
4517 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4518 {
4519 struct mlx5_core_dev *mdev = priv->mdev;
4520 const struct mlx5e_profile *profile;
4521 int err;
4522
4523 profile = priv->profile;
4524 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4525
4526 err = profile->init_tx(priv);
4527 if (err)
4528 goto out;
4529
4530 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
4531 if (err) {
4532 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4533 goto err_cleanup_tx;
4534 }
4535
4536 err = profile->init_rx(priv);
4537 if (err)
4538 goto err_close_drop_rq;
4539
4540 mlx5e_create_q_counter(priv);
4541
4542 if (profile->enable)
4543 profile->enable(priv);
4544
4545 return 0;
4546
4547 err_close_drop_rq:
4548 mlx5e_close_drop_rq(&priv->drop_rq);
4549
4550 err_cleanup_tx:
4551 profile->cleanup_tx(priv);
4552
4553 out:
4554 return err;
4555 }
4556
4557 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4558 {
4559 const struct mlx5e_profile *profile = priv->profile;
4560
4561 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4562
4563 if (profile->disable)
4564 profile->disable(priv);
4565 flush_workqueue(priv->wq);
4566
4567 mlx5e_destroy_q_counter(priv);
4568 profile->cleanup_rx(priv);
4569 mlx5e_close_drop_rq(&priv->drop_rq);
4570 profile->cleanup_tx(priv);
4571 cancel_delayed_work_sync(&priv->update_stats_work);
4572 }
4573
4574 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4575 {
4576 const struct mlx5e_profile *profile = priv->profile;
4577 struct net_device *netdev = priv->netdev;
4578
4579 destroy_workqueue(priv->wq);
4580 if (profile->cleanup)
4581 profile->cleanup(priv);
4582 free_netdev(netdev);
4583 }
4584
4585 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4586 * hardware contexts and to connect it to the current netdev.
4587 */
4588 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4589 {
4590 struct mlx5e_priv *priv = vpriv;
4591 struct net_device *netdev = priv->netdev;
4592 int err;
4593
4594 if (netif_device_present(netdev))
4595 return 0;
4596
4597 err = mlx5e_create_mdev_resources(mdev);
4598 if (err)
4599 return err;
4600
4601 err = mlx5e_attach_netdev(priv);
4602 if (err) {
4603 mlx5e_destroy_mdev_resources(mdev);
4604 return err;
4605 }
4606
4607 return 0;
4608 }
4609
4610 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4611 {
4612 struct mlx5e_priv *priv = vpriv;
4613 struct net_device *netdev = priv->netdev;
4614
4615 if (!netif_device_present(netdev))
4616 return;
4617
4618 mlx5e_detach_netdev(priv);
4619 mlx5e_destroy_mdev_resources(mdev);
4620 }
4621
4622 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4623 {
4624 struct net_device *netdev;
4625 void *rpriv = NULL;
4626 void *priv;
4627 int err;
4628
4629 err = mlx5e_check_required_hca_cap(mdev);
4630 if (err)
4631 return NULL;
4632
4633 #ifdef CONFIG_MLX5_ESWITCH
4634 if (MLX5_VPORT_MANAGER(mdev)) {
4635 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4636 if (!rpriv) {
4637 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4638 return NULL;
4639 }
4640 }
4641 #endif
4642
4643 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4644 if (!netdev) {
4645 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4646 goto err_free_rpriv;
4647 }
4648
4649 priv = netdev_priv(netdev);
4650
4651 err = mlx5e_attach(mdev, priv);
4652 if (err) {
4653 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4654 goto err_destroy_netdev;
4655 }
4656
4657 err = register_netdev(netdev);
4658 if (err) {
4659 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4660 goto err_detach;
4661 }
4662
4663 #ifdef CONFIG_MLX5_CORE_EN_DCB
4664 mlx5e_dcbnl_init_app(priv);
4665 #endif
4666 return priv;
4667
4668 err_detach:
4669 mlx5e_detach(mdev, priv);
4670 err_destroy_netdev:
4671 mlx5e_destroy_netdev(priv);
4672 err_free_rpriv:
4673 kfree(rpriv);
4674 return NULL;
4675 }
4676
4677 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4678 {
4679 struct mlx5e_priv *priv = vpriv;
4680 void *ppriv = priv->ppriv;
4681
4682 #ifdef CONFIG_MLX5_CORE_EN_DCB
4683 mlx5e_dcbnl_delete_app(priv);
4684 #endif
4685 unregister_netdev(priv->netdev);
4686 mlx5e_detach(mdev, vpriv);
4687 mlx5e_destroy_netdev(priv);
4688 kfree(ppriv);
4689 }
4690
4691 static void *mlx5e_get_netdev(void *vpriv)
4692 {
4693 struct mlx5e_priv *priv = vpriv;
4694
4695 return priv->netdev;
4696 }
4697
4698 static struct mlx5_interface mlx5e_interface = {
4699 .add = mlx5e_add,
4700 .remove = mlx5e_remove,
4701 .attach = mlx5e_attach,
4702 .detach = mlx5e_detach,
4703 .event = mlx5e_async_event,
4704 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4705 .get_dev = mlx5e_get_netdev,
4706 };
4707
4708 void mlx5e_init(void)
4709 {
4710 mlx5e_ipsec_build_inverse_table();
4711 mlx5e_build_ptys2ethtool_map();
4712 mlx5_register_interface(&mlx5e_interface);
4713 }
4714
4715 void mlx5e_cleanup(void)
4716 {
4717 mlx5_unregister_interface(&mlx5e_interface);
4718 }
Ubuntu Focal Linux kernel mirror