2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
42 #include "en_accel/ipsec.h"
43 #include "en_accel/ipsec_rxtx.h"
44 #include "accel/ipsec.h"
47 struct mlx5e_rq_param
{
48 u32 rqc
[MLX5_ST_SZ_DW(rqc
)];
49 struct mlx5_wq_param wq
;
52 struct mlx5e_sq_param
{
53 u32 sqc
[MLX5_ST_SZ_DW(sqc
)];
54 struct mlx5_wq_param wq
;
57 struct mlx5e_cq_param
{
58 u32 cqc
[MLX5_ST_SZ_DW(cqc
)];
59 struct mlx5_wq_param wq
;
64 struct mlx5e_channel_param
{
65 struct mlx5e_rq_param rq
;
66 struct mlx5e_sq_param sq
;
67 struct mlx5e_sq_param xdp_sq
;
68 struct mlx5e_sq_param icosq
;
69 struct mlx5e_cq_param rx_cq
;
70 struct mlx5e_cq_param tx_cq
;
71 struct mlx5e_cq_param icosq_cq
;
74 static int mlx5e_get_node(struct mlx5e_priv
*priv
, int ix
)
76 return pci_irq_get_node(priv
->mdev
->pdev
, MLX5_EQ_VEC_COMP_BASE
+ ix
);
79 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev
*mdev
)
81 return MLX5_CAP_GEN(mdev
, striding_rq
) &&
82 MLX5_CAP_GEN(mdev
, umr_ptr_rlky
) &&
83 MLX5_CAP_ETH(mdev
, reg_umr_sq
);
86 void mlx5e_set_rq_type_params(struct mlx5_core_dev
*mdev
,
87 struct mlx5e_params
*params
, u8 rq_type
)
89 params
->rq_wq_type
= rq_type
;
90 params
->lro_wqe_sz
= MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ
;
91 switch (params
->rq_wq_type
) {
92 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
93 params
->log_rq_size
= is_kdump_kernel() ?
94 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW
:
95 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW
;
96 params
->mpwqe_log_stride_sz
=
97 MLX5E_GET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_COMPRESS
) ?
98 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev
) :
99 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev
);
100 params
->mpwqe_log_num_strides
= MLX5_MPWRQ_LOG_WQE_SZ
-
101 params
->mpwqe_log_stride_sz
;
103 default: /* MLX5_WQ_TYPE_LINKED_LIST */
104 params
->log_rq_size
= is_kdump_kernel() ?
105 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE
:
106 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE
;
107 params
->rq_headroom
= params
->xdp_prog
?
108 XDP_PACKET_HEADROOM
: MLX5_RX_HEADROOM
;
109 params
->rq_headroom
+= NET_IP_ALIGN
;
111 /* Extra room needed for build_skb */
112 params
->lro_wqe_sz
-= params
->rq_headroom
+
113 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
116 mlx5_core_info(mdev
, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
117 params
->rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
,
118 BIT(params
->log_rq_size
),
119 BIT(params
->mpwqe_log_stride_sz
),
120 MLX5E_GET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_COMPRESS
));
123 static void mlx5e_set_rq_params(struct mlx5_core_dev
*mdev
, struct mlx5e_params
*params
)
125 u8 rq_type
= mlx5e_check_fragmented_striding_rq_cap(mdev
) &&
126 !params
->xdp_prog
&& !MLX5_IPSEC_DEV(mdev
) ?
127 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
128 MLX5_WQ_TYPE_LINKED_LIST
;
129 mlx5e_set_rq_type_params(mdev
, params
, rq_type
);
132 static void mlx5e_update_carrier(struct mlx5e_priv
*priv
)
134 struct mlx5_core_dev
*mdev
= priv
->mdev
;
137 port_state
= mlx5_query_vport_state(mdev
,
138 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT
,
141 if (port_state
== VPORT_STATE_UP
) {
142 netdev_info(priv
->netdev
, "Link up\n");
143 netif_carrier_on(priv
->netdev
);
145 netdev_info(priv
->netdev
, "Link down\n");
146 netif_carrier_off(priv
->netdev
);
150 static void mlx5e_update_carrier_work(struct work_struct
*work
)
152 struct mlx5e_priv
*priv
= container_of(work
, struct mlx5e_priv
,
153 update_carrier_work
);
155 mutex_lock(&priv
->state_lock
);
156 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
157 if (priv
->profile
->update_carrier
)
158 priv
->profile
->update_carrier(priv
);
159 mutex_unlock(&priv
->state_lock
);
162 static void mlx5e_tx_timeout_work(struct work_struct
*work
)
164 struct mlx5e_priv
*priv
= container_of(work
, struct mlx5e_priv
,
169 mutex_lock(&priv
->state_lock
);
170 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
172 mlx5e_close_locked(priv
->netdev
);
173 err
= mlx5e_open_locked(priv
->netdev
);
175 netdev_err(priv
->netdev
, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
178 mutex_unlock(&priv
->state_lock
);
182 static void mlx5e_update_sw_counters(struct mlx5e_priv
*priv
)
184 struct mlx5e_sw_stats temp
, *s
= &temp
;
185 struct mlx5e_rq_stats
*rq_stats
;
186 struct mlx5e_sq_stats
*sq_stats
;
187 u64 tx_offload_none
= 0;
190 memset(s
, 0, sizeof(*s
));
191 for (i
= 0; i
< priv
->channels
.num
; i
++) {
192 struct mlx5e_channel
*c
= priv
->channels
.c
[i
];
194 rq_stats
= &c
->rq
.stats
;
196 s
->rx_packets
+= rq_stats
->packets
;
197 s
->rx_bytes
+= rq_stats
->bytes
;
198 s
->rx_lro_packets
+= rq_stats
->lro_packets
;
199 s
->rx_lro_bytes
+= rq_stats
->lro_bytes
;
200 s
->rx_csum_none
+= rq_stats
->csum_none
;
201 s
->rx_csum_complete
+= rq_stats
->csum_complete
;
202 s
->rx_csum_unnecessary_inner
+= rq_stats
->csum_unnecessary_inner
;
203 s
->rx_xdp_drop
+= rq_stats
->xdp_drop
;
204 s
->rx_xdp_tx
+= rq_stats
->xdp_tx
;
205 s
->rx_xdp_tx_full
+= rq_stats
->xdp_tx_full
;
206 s
->rx_wqe_err
+= rq_stats
->wqe_err
;
207 s
->rx_mpwqe_filler
+= rq_stats
->mpwqe_filler
;
208 s
->rx_buff_alloc_err
+= rq_stats
->buff_alloc_err
;
209 s
->rx_cqe_compress_blks
+= rq_stats
->cqe_compress_blks
;
210 s
->rx_cqe_compress_pkts
+= rq_stats
->cqe_compress_pkts
;
211 s
->rx_page_reuse
+= rq_stats
->page_reuse
;
212 s
->rx_cache_reuse
+= rq_stats
->cache_reuse
;
213 s
->rx_cache_full
+= rq_stats
->cache_full
;
214 s
->rx_cache_empty
+= rq_stats
->cache_empty
;
215 s
->rx_cache_busy
+= rq_stats
->cache_busy
;
216 s
->rx_cache_waive
+= rq_stats
->cache_waive
;
218 for (j
= 0; j
< priv
->channels
.params
.num_tc
; j
++) {
219 sq_stats
= &c
->sq
[j
].stats
;
221 s
->tx_packets
+= sq_stats
->packets
;
222 s
->tx_bytes
+= sq_stats
->bytes
;
223 s
->tx_tso_packets
+= sq_stats
->tso_packets
;
224 s
->tx_tso_bytes
+= sq_stats
->tso_bytes
;
225 s
->tx_tso_inner_packets
+= sq_stats
->tso_inner_packets
;
226 s
->tx_tso_inner_bytes
+= sq_stats
->tso_inner_bytes
;
227 s
->tx_queue_stopped
+= sq_stats
->stopped
;
228 s
->tx_queue_wake
+= sq_stats
->wake
;
229 s
->tx_queue_dropped
+= sq_stats
->dropped
;
230 s
->tx_xmit_more
+= sq_stats
->xmit_more
;
231 s
->tx_csum_partial_inner
+= sq_stats
->csum_partial_inner
;
232 tx_offload_none
+= sq_stats
->csum_none
;
236 /* Update calculated offload counters */
237 s
->tx_csum_partial
= s
->tx_packets
- tx_offload_none
- s
->tx_csum_partial_inner
;
238 s
->rx_csum_unnecessary
= s
->rx_packets
- s
->rx_csum_none
- s
->rx_csum_complete
;
240 s
->link_down_events_phy
= MLX5_GET(ppcnt_reg
,
241 priv
->stats
.pport
.phy_counters
,
242 counter_set
.phys_layer_cntrs
.link_down_events
);
243 memcpy(&priv
->stats
.sw
, s
, sizeof(*s
));
246 static void mlx5e_update_vport_counters(struct mlx5e_priv
*priv
)
248 int outlen
= MLX5_ST_SZ_BYTES(query_vport_counter_out
);
249 u32
*out
= (u32
*)priv
->stats
.vport
.query_vport_out
;
250 u32 in
[MLX5_ST_SZ_DW(query_vport_counter_in
)] = {0};
251 struct mlx5_core_dev
*mdev
= priv
->mdev
;
253 MLX5_SET(query_vport_counter_in
, in
, opcode
,
254 MLX5_CMD_OP_QUERY_VPORT_COUNTER
);
255 MLX5_SET(query_vport_counter_in
, in
, op_mod
, 0);
256 MLX5_SET(query_vport_counter_in
, in
, other_vport
, 0);
258 mlx5_cmd_exec(mdev
, in
, sizeof(in
), out
, outlen
);
261 static void mlx5e_update_pport_counters(struct mlx5e_priv
*priv
, bool full
)
263 struct mlx5e_pport_stats
*pstats
= &priv
->stats
.pport
;
264 struct mlx5_core_dev
*mdev
= priv
->mdev
;
265 u32 in
[MLX5_ST_SZ_DW(ppcnt_reg
)] = {0};
266 int sz
= MLX5_ST_SZ_BYTES(ppcnt_reg
);
270 MLX5_SET(ppcnt_reg
, in
, local_port
, 1);
272 out
= pstats
->IEEE_802_3_counters
;
273 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_IEEE_802_3_COUNTERS_GROUP
);
274 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
279 out
= pstats
->RFC_2863_counters
;
280 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2863_COUNTERS_GROUP
);
281 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
283 out
= pstats
->RFC_2819_counters
;
284 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2819_COUNTERS_GROUP
);
285 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
287 out
= pstats
->phy_counters
;
288 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP
);
289 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
291 if (MLX5_CAP_PCAM_FEATURE(mdev
, ppcnt_statistical_group
)) {
292 out
= pstats
->phy_statistical_counters
;
293 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP
);
294 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
297 if (MLX5_CAP_PCAM_FEATURE(mdev
, rx_buffer_fullness_counters
)) {
298 out
= pstats
->eth_ext_counters
;
299 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP
);
300 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
303 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PER_PRIORITY_COUNTERS_GROUP
);
304 for (prio
= 0; prio
< NUM_PPORT_PRIO
; prio
++) {
305 out
= pstats
->per_prio_counters
[prio
];
306 MLX5_SET(ppcnt_reg
, in
, prio_tc
, prio
);
307 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
,
308 MLX5_REG_PPCNT
, 0, 0);
312 static void mlx5e_update_q_counter(struct mlx5e_priv
*priv
)
314 struct mlx5e_qcounter_stats
*qcnt
= &priv
->stats
.qcnt
;
315 u32 out
[MLX5_ST_SZ_DW(query_q_counter_out
)];
318 if (!priv
->q_counter
)
321 err
= mlx5_core_query_q_counter(priv
->mdev
, priv
->q_counter
, 0, out
, sizeof(out
));
325 qcnt
->rx_out_of_buffer
= MLX5_GET(query_q_counter_out
, out
, out_of_buffer
);
328 static void mlx5e_update_pcie_counters(struct mlx5e_priv
*priv
)
330 struct mlx5e_pcie_stats
*pcie_stats
= &priv
->stats
.pcie
;
331 struct mlx5_core_dev
*mdev
= priv
->mdev
;
332 u32 in
[MLX5_ST_SZ_DW(mpcnt_reg
)] = {0};
333 int sz
= MLX5_ST_SZ_BYTES(mpcnt_reg
);
336 if (!MLX5_CAP_MCAM_FEATURE(mdev
, pcie_performance_group
))
339 out
= pcie_stats
->pcie_perf_counters
;
340 MLX5_SET(mpcnt_reg
, in
, grp
, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP
);
341 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_MPCNT
, 0, 0);
344 void mlx5e_update_stats(struct mlx5e_priv
*priv
, bool full
)
347 mlx5e_update_pcie_counters(priv
);
348 mlx5e_ipsec_update_stats(priv
);
350 mlx5e_update_pport_counters(priv
, full
);
351 mlx5e_update_vport_counters(priv
);
352 mlx5e_update_q_counter(priv
);
353 mlx5e_update_sw_counters(priv
);
356 static void mlx5e_update_ndo_stats(struct mlx5e_priv
*priv
)
358 mlx5e_update_stats(priv
, false);
361 void mlx5e_update_stats_work(struct work_struct
*work
)
363 struct delayed_work
*dwork
= to_delayed_work(work
);
364 struct mlx5e_priv
*priv
= container_of(dwork
, struct mlx5e_priv
,
366 mutex_lock(&priv
->state_lock
);
367 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
)) {
368 priv
->profile
->update_stats(priv
);
369 queue_delayed_work(priv
->wq
, dwork
,
370 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL
));
372 mutex_unlock(&priv
->state_lock
);
375 static void mlx5e_async_event(struct mlx5_core_dev
*mdev
, void *vpriv
,
376 enum mlx5_dev_event event
, unsigned long param
)
378 struct mlx5e_priv
*priv
= vpriv
;
379 struct ptp_clock_event ptp_event
;
380 struct mlx5_eqe
*eqe
= NULL
;
382 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
))
386 case MLX5_DEV_EVENT_PORT_UP
:
387 case MLX5_DEV_EVENT_PORT_DOWN
:
388 queue_work(priv
->wq
, &priv
->update_carrier_work
);
390 case MLX5_DEV_EVENT_PPS
:
391 eqe
= (struct mlx5_eqe
*)param
;
392 ptp_event
.index
= eqe
->data
.pps
.pin
;
393 ptp_event
.timestamp
=
394 timecounter_cyc2time(&priv
->tstamp
.clock
,
395 be64_to_cpu(eqe
->data
.pps
.time_stamp
));
396 mlx5e_pps_event_handler(vpriv
, &ptp_event
);
403 static void mlx5e_enable_async_events(struct mlx5e_priv
*priv
)
405 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
);
408 static void mlx5e_disable_async_events(struct mlx5e_priv
*priv
)
410 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
);
411 synchronize_irq(pci_irq_vector(priv
->mdev
->pdev
, MLX5_EQ_VEC_ASYNC
));
414 static inline int mlx5e_get_wqe_mtt_sz(void)
416 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
417 * To avoid copying garbage after the mtt array, we allocate
420 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE
* sizeof(__be64
),
421 MLX5_UMR_MTT_ALIGNMENT
);
424 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq
*rq
,
425 struct mlx5e_icosq
*sq
,
426 struct mlx5e_umr_wqe
*wqe
,
429 struct mlx5_wqe_ctrl_seg
*cseg
= &wqe
->ctrl
;
430 struct mlx5_wqe_umr_ctrl_seg
*ucseg
= &wqe
->uctrl
;
431 struct mlx5_wqe_data_seg
*dseg
= &wqe
->data
;
432 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[ix
];
433 u8 ds_cnt
= DIV_ROUND_UP(sizeof(*wqe
), MLX5_SEND_WQE_DS
);
434 u32 umr_wqe_mtt_offset
= mlx5e_get_wqe_mtt_offset(rq
, ix
);
436 cseg
->qpn_ds
= cpu_to_be32((sq
->sqn
<< MLX5_WQE_CTRL_QPN_SHIFT
) |
438 cseg
->fm_ce_se
= MLX5_WQE_CTRL_CQ_UPDATE
;
439 cseg
->imm
= rq
->mkey_be
;
441 ucseg
->flags
= MLX5_UMR_TRANSLATION_OFFSET_EN
;
442 ucseg
->xlt_octowords
=
443 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE
));
444 ucseg
->bsf_octowords
=
445 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset
));
446 ucseg
->mkey_mask
= cpu_to_be64(MLX5_MKEY_MASK_FREE
);
448 dseg
->lkey
= sq
->mkey_be
;
449 dseg
->addr
= cpu_to_be64(wi
->umr
.mtt_addr
);
452 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq
*rq
,
453 struct mlx5e_channel
*c
)
455 int wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
456 int mtt_sz
= mlx5e_get_wqe_mtt_sz();
457 int mtt_alloc
= mtt_sz
+ MLX5_UMR_ALIGN
- 1;
458 int node
= mlx5e_get_node(c
->priv
, c
->ix
);
461 rq
->mpwqe
.info
= kzalloc_node(wq_sz
* sizeof(*rq
->mpwqe
.info
),
466 /* We allocate more than mtt_sz as we will align the pointer */
467 rq
->mpwqe
.mtt_no_align
= kzalloc_node(mtt_alloc
* wq_sz
,
469 if (unlikely(!rq
->mpwqe
.mtt_no_align
))
470 goto err_free_wqe_info
;
472 for (i
= 0; i
< wq_sz
; i
++) {
473 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[i
];
475 wi
->umr
.mtt
= PTR_ALIGN(rq
->mpwqe
.mtt_no_align
+ i
* mtt_alloc
,
477 wi
->umr
.mtt_addr
= dma_map_single(c
->pdev
, wi
->umr
.mtt
, mtt_sz
,
479 if (unlikely(dma_mapping_error(c
->pdev
, wi
->umr
.mtt_addr
)))
482 mlx5e_build_umr_wqe(rq
, &c
->icosq
, &wi
->umr
.wqe
, i
);
489 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[i
];
491 dma_unmap_single(c
->pdev
, wi
->umr
.mtt_addr
, mtt_sz
,
494 kfree(rq
->mpwqe
.mtt_no_align
);
496 kfree(rq
->mpwqe
.info
);
502 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq
*rq
)
504 int wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
505 int mtt_sz
= mlx5e_get_wqe_mtt_sz();
508 for (i
= 0; i
< wq_sz
; i
++) {
509 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[i
];
511 dma_unmap_single(rq
->pdev
, wi
->umr
.mtt_addr
, mtt_sz
,
514 kfree(rq
->mpwqe
.mtt_no_align
);
515 kfree(rq
->mpwqe
.info
);
518 static int mlx5e_create_umr_mkey(struct mlx5_core_dev
*mdev
,
519 u64 npages
, u8 page_shift
,
520 struct mlx5_core_mkey
*umr_mkey
)
522 int inlen
= MLX5_ST_SZ_BYTES(create_mkey_in
);
527 if (!MLX5E_VALID_NUM_MTTS(npages
))
530 in
= kvzalloc(inlen
, GFP_KERNEL
);
534 mkc
= MLX5_ADDR_OF(create_mkey_in
, in
, memory_key_mkey_entry
);
536 MLX5_SET(mkc
, mkc
, free
, 1);
537 MLX5_SET(mkc
, mkc
, umr_en
, 1);
538 MLX5_SET(mkc
, mkc
, lw
, 1);
539 MLX5_SET(mkc
, mkc
, lr
, 1);
540 MLX5_SET(mkc
, mkc
, access_mode
, MLX5_MKC_ACCESS_MODE_MTT
);
542 MLX5_SET(mkc
, mkc
, qpn
, 0xffffff);
543 MLX5_SET(mkc
, mkc
, pd
, mdev
->mlx5e_res
.pdn
);
544 MLX5_SET64(mkc
, mkc
, len
, npages
<< page_shift
);
545 MLX5_SET(mkc
, mkc
, translations_octword_size
,
546 MLX5_MTT_OCTW(npages
));
547 MLX5_SET(mkc
, mkc
, log_page_size
, page_shift
);
549 err
= mlx5_core_create_mkey(mdev
, umr_mkey
, in
, inlen
);
555 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev
*mdev
, struct mlx5e_rq
*rq
)
557 u64 num_mtts
= MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq
->wq
));
559 return mlx5e_create_umr_mkey(mdev
, num_mtts
, PAGE_SHIFT
, &rq
->umr_mkey
);
562 static int mlx5e_alloc_rq(struct mlx5e_channel
*c
,
563 struct mlx5e_params
*params
,
564 struct mlx5e_rq_param
*rqp
,
567 struct mlx5_core_dev
*mdev
= c
->mdev
;
568 void *rqc
= rqp
->rqc
;
569 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
576 rqp
->wq
.db_numa_node
= mlx5e_get_node(c
->priv
, c
->ix
);
578 err
= mlx5_wq_ll_create(mdev
, &rqp
->wq
, rqc_wq
, &rq
->wq
,
583 rq
->wq
.db
= &rq
->wq
.db
[MLX5_RCV_DBR
];
585 wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
587 rq
->wq_type
= params
->rq_wq_type
;
589 rq
->netdev
= c
->netdev
;
590 rq
->tstamp
= c
->tstamp
;
595 rq
->xdp_prog
= params
->xdp_prog
? bpf_prog_inc(params
->xdp_prog
) : NULL
;
596 if (IS_ERR(rq
->xdp_prog
)) {
597 err
= PTR_ERR(rq
->xdp_prog
);
599 goto err_rq_wq_destroy
;
602 rq
->buff
.map_dir
= rq
->xdp_prog
? DMA_BIDIRECTIONAL
: DMA_FROM_DEVICE
;
603 rq
->buff
.headroom
= params
->rq_headroom
;
605 switch (rq
->wq_type
) {
606 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
608 rq
->post_wqes
= mlx5e_post_rx_mpwqes
;
609 rq
->dealloc_wqe
= mlx5e_dealloc_rx_mpwqe
;
611 rq
->handle_rx_cqe
= c
->priv
->profile
->rx_handlers
.handle_rx_cqe_mpwqe
;
612 #ifdef CONFIG_MLX5_EN_IPSEC
613 if (MLX5_IPSEC_DEV(mdev
)) {
615 netdev_err(c
->netdev
, "MPWQE RQ with IPSec offload not supported\n");
616 goto err_rq_wq_destroy
;
619 if (!rq
->handle_rx_cqe
) {
621 netdev_err(c
->netdev
, "RX handler of MPWQE RQ is not set, err %d\n", err
);
622 goto err_rq_wq_destroy
;
625 rq
->mpwqe
.log_stride_sz
= params
->mpwqe_log_stride_sz
;
626 rq
->mpwqe
.num_strides
= BIT(params
->mpwqe_log_num_strides
);
628 byte_count
= rq
->mpwqe
.num_strides
<< rq
->mpwqe
.log_stride_sz
;
630 err
= mlx5e_create_rq_umr_mkey(mdev
, rq
);
632 goto err_rq_wq_destroy
;
633 rq
->mkey_be
= cpu_to_be32(rq
->umr_mkey
.key
);
635 err
= mlx5e_rq_alloc_mpwqe_info(rq
, c
);
637 goto err_destroy_umr_mkey
;
639 default: /* MLX5_WQ_TYPE_LINKED_LIST */
641 kzalloc_node(wq_sz
* sizeof(*rq
->wqe
.frag_info
),
643 mlx5e_get_node(c
->priv
, c
->ix
));
644 if (!rq
->wqe
.frag_info
) {
646 goto err_rq_wq_destroy
;
648 rq
->post_wqes
= mlx5e_post_rx_wqes
;
649 rq
->dealloc_wqe
= mlx5e_dealloc_rx_wqe
;
651 #ifdef CONFIG_MLX5_EN_IPSEC
653 rq
->handle_rx_cqe
= mlx5e_ipsec_handle_rx_cqe
;
656 rq
->handle_rx_cqe
= c
->priv
->profile
->rx_handlers
.handle_rx_cqe
;
657 if (!rq
->handle_rx_cqe
) {
658 kfree(rq
->wqe
.frag_info
);
660 netdev_err(c
->netdev
, "RX handler of RQ is not set, err %d\n", err
);
661 goto err_rq_wq_destroy
;
664 byte_count
= params
->lro_en
?
666 MLX5E_SW2HW_MTU(c
->priv
, c
->netdev
->mtu
);
667 #ifdef CONFIG_MLX5_EN_IPSEC
668 if (MLX5_IPSEC_DEV(mdev
))
669 byte_count
+= MLX5E_METADATA_ETHER_LEN
;
671 rq
->wqe
.page_reuse
= !params
->xdp_prog
&& !params
->lro_en
;
673 /* calc the required page order */
674 rq
->wqe
.frag_sz
= MLX5_SKB_FRAG_SZ(rq
->buff
.headroom
+ byte_count
);
675 npages
= DIV_ROUND_UP(rq
->wqe
.frag_sz
, PAGE_SIZE
);
676 rq
->buff
.page_order
= order_base_2(npages
);
678 byte_count
|= MLX5_HW_START_PADDING
;
679 rq
->mkey_be
= c
->mkey_be
;
682 for (i
= 0; i
< wq_sz
; i
++) {
683 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, i
);
685 if (rq
->wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
) {
686 u64 dma_offset
= (u64
)mlx5e_get_wqe_mtt_offset(rq
, i
) << PAGE_SHIFT
;
688 wqe
->data
.addr
= cpu_to_be64(dma_offset
);
691 wqe
->data
.byte_count
= cpu_to_be32(byte_count
);
692 wqe
->data
.lkey
= rq
->mkey_be
;
695 INIT_WORK(&rq
->am
.work
, mlx5e_rx_am_work
);
696 rq
->am
.mode
= params
->rx_cq_period_mode
;
697 rq
->page_cache
.head
= 0;
698 rq
->page_cache
.tail
= 0;
702 err_destroy_umr_mkey
:
703 mlx5_core_destroy_mkey(mdev
, &rq
->umr_mkey
);
707 bpf_prog_put(rq
->xdp_prog
);
708 mlx5_wq_destroy(&rq
->wq_ctrl
);
713 static void mlx5e_free_rq(struct mlx5e_rq
*rq
)
718 bpf_prog_put(rq
->xdp_prog
);
720 switch (rq
->wq_type
) {
721 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
722 mlx5e_rq_free_mpwqe_info(rq
);
723 mlx5_core_destroy_mkey(rq
->mdev
, &rq
->umr_mkey
);
725 default: /* MLX5_WQ_TYPE_LINKED_LIST */
726 kfree(rq
->wqe
.frag_info
);
729 for (i
= rq
->page_cache
.head
; i
!= rq
->page_cache
.tail
;
730 i
= (i
+ 1) & (MLX5E_CACHE_SIZE
- 1)) {
731 struct mlx5e_dma_info
*dma_info
= &rq
->page_cache
.page_cache
[i
];
733 mlx5e_page_release(rq
, dma_info
, false);
735 mlx5_wq_destroy(&rq
->wq_ctrl
);
738 static int mlx5e_create_rq(struct mlx5e_rq
*rq
,
739 struct mlx5e_rq_param
*param
)
741 struct mlx5_core_dev
*mdev
= rq
->mdev
;
749 inlen
= MLX5_ST_SZ_BYTES(create_rq_in
) +
750 sizeof(u64
) * rq
->wq_ctrl
.buf
.npages
;
751 in
= kvzalloc(inlen
, GFP_KERNEL
);
755 rqc
= MLX5_ADDR_OF(create_rq_in
, in
, ctx
);
756 wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
758 memcpy(rqc
, param
->rqc
, sizeof(param
->rqc
));
760 MLX5_SET(rqc
, rqc
, cqn
, rq
->cq
.mcq
.cqn
);
761 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RST
);
762 MLX5_SET(wq
, wq
, log_wq_pg_sz
, rq
->wq_ctrl
.buf
.page_shift
-
763 MLX5_ADAPTER_PAGE_SHIFT
);
764 MLX5_SET64(wq
, wq
, dbr_addr
, rq
->wq_ctrl
.db
.dma
);
766 mlx5_fill_page_array(&rq
->wq_ctrl
.buf
,
767 (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
769 err
= mlx5_core_create_rq(mdev
, in
, inlen
, &rq
->rqn
);
776 static int mlx5e_modify_rq_state(struct mlx5e_rq
*rq
, int curr_state
,
779 struct mlx5e_channel
*c
= rq
->channel
;
780 struct mlx5_core_dev
*mdev
= c
->mdev
;
787 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
788 in
= kvzalloc(inlen
, GFP_KERNEL
);
792 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
794 MLX5_SET(modify_rq_in
, in
, rq_state
, curr_state
);
795 MLX5_SET(rqc
, rqc
, state
, next_state
);
797 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
804 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq
*rq
, bool enable
)
806 struct mlx5e_channel
*c
= rq
->channel
;
807 struct mlx5e_priv
*priv
= c
->priv
;
808 struct mlx5_core_dev
*mdev
= priv
->mdev
;
815 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
816 in
= kvzalloc(inlen
, GFP_KERNEL
);
820 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
822 MLX5_SET(modify_rq_in
, in
, rq_state
, MLX5_RQC_STATE_RDY
);
823 MLX5_SET64(modify_rq_in
, in
, modify_bitmask
,
824 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS
);
825 MLX5_SET(rqc
, rqc
, scatter_fcs
, enable
);
826 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RDY
);
828 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
835 static int mlx5e_modify_rq_vsd(struct mlx5e_rq
*rq
, bool vsd
)
837 struct mlx5e_channel
*c
= rq
->channel
;
838 struct mlx5_core_dev
*mdev
= c
->mdev
;
844 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
845 in
= kvzalloc(inlen
, GFP_KERNEL
);
849 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
851 MLX5_SET(modify_rq_in
, in
, rq_state
, MLX5_RQC_STATE_RDY
);
852 MLX5_SET64(modify_rq_in
, in
, modify_bitmask
,
853 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD
);
854 MLX5_SET(rqc
, rqc
, vsd
, vsd
);
855 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RDY
);
857 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
864 static void mlx5e_destroy_rq(struct mlx5e_rq
*rq
)
866 mlx5_core_destroy_rq(rq
->mdev
, rq
->rqn
);
869 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq
*rq
)
871 unsigned long exp_time
= jiffies
+ msecs_to_jiffies(20000);
872 struct mlx5e_channel
*c
= rq
->channel
;
874 struct mlx5_wq_ll
*wq
= &rq
->wq
;
875 u16 min_wqes
= mlx5_min_rx_wqes(rq
->wq_type
, mlx5_wq_ll_get_size(wq
));
877 while (time_before(jiffies
, exp_time
)) {
878 if (wq
->cur_sz
>= min_wqes
)
884 netdev_warn(c
->netdev
, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
885 rq
->rqn
, wq
->cur_sz
, min_wqes
);
889 static void mlx5e_free_rx_descs(struct mlx5e_rq
*rq
)
891 struct mlx5_wq_ll
*wq
= &rq
->wq
;
892 struct mlx5e_rx_wqe
*wqe
;
896 /* UMR WQE (if in progress) is always at wq->head */
897 if (rq
->wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
&&
898 rq
->mpwqe
.umr_in_progress
)
899 mlx5e_free_rx_mpwqe(rq
, &rq
->mpwqe
.info
[wq
->head
]);
901 while (!mlx5_wq_ll_is_empty(wq
)) {
902 wqe_ix_be
= *wq
->tail_next
;
903 wqe_ix
= be16_to_cpu(wqe_ix_be
);
904 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_ix
);
905 rq
->dealloc_wqe(rq
, wqe_ix
);
906 mlx5_wq_ll_pop(&rq
->wq
, wqe_ix_be
,
907 &wqe
->next
.next_wqe_index
);
910 if (rq
->wq_type
== MLX5_WQ_TYPE_LINKED_LIST
&& rq
->wqe
.page_reuse
) {
911 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
912 * but yet to be re-posted.
914 int wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
916 for (wqe_ix
= 0; wqe_ix
< wq_sz
; wqe_ix
++)
917 rq
->dealloc_wqe(rq
, wqe_ix
);
921 static int mlx5e_open_rq(struct mlx5e_channel
*c
,
922 struct mlx5e_params
*params
,
923 struct mlx5e_rq_param
*param
,
928 err
= mlx5e_alloc_rq(c
, params
, param
, rq
);
932 err
= mlx5e_create_rq(rq
, param
);
936 err
= mlx5e_modify_rq_state(rq
, MLX5_RQC_STATE_RST
, MLX5_RQC_STATE_RDY
);
940 if (params
->rx_am_enabled
)
941 c
->rq
.state
|= BIT(MLX5E_RQ_STATE_AM
);
946 mlx5e_destroy_rq(rq
);
953 static void mlx5e_activate_rq(struct mlx5e_rq
*rq
)
955 struct mlx5e_icosq
*sq
= &rq
->channel
->icosq
;
956 u16 pi
= sq
->pc
& sq
->wq
.sz_m1
;
957 struct mlx5e_tx_wqe
*nopwqe
;
959 set_bit(MLX5E_RQ_STATE_ENABLED
, &rq
->state
);
960 sq
->db
.ico_wqe
[pi
].opcode
= MLX5_OPCODE_NOP
;
961 nopwqe
= mlx5e_post_nop(&sq
->wq
, sq
->sqn
, &sq
->pc
);
962 mlx5e_notify_hw(&sq
->wq
, sq
->pc
, sq
->uar_map
, &nopwqe
->ctrl
);
965 static void mlx5e_deactivate_rq(struct mlx5e_rq
*rq
)
967 clear_bit(MLX5E_RQ_STATE_ENABLED
, &rq
->state
);
968 napi_synchronize(&rq
->channel
->napi
); /* prevent mlx5e_post_rx_wqes */
971 static void mlx5e_close_rq(struct mlx5e_rq
*rq
)
973 cancel_work_sync(&rq
->am
.work
);
974 mlx5e_destroy_rq(rq
);
975 mlx5e_free_rx_descs(rq
);
979 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq
*sq
)
984 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq
*sq
, int numa
)
986 int wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
988 sq
->db
.di
= kzalloc_node(sizeof(*sq
->db
.di
) * wq_sz
,
991 mlx5e_free_xdpsq_db(sq
);
998 static int mlx5e_alloc_xdpsq(struct mlx5e_channel
*c
,
999 struct mlx5e_params
*params
,
1000 struct mlx5e_sq_param
*param
,
1001 struct mlx5e_xdpsq
*sq
)
1003 void *sqc_wq
= MLX5_ADDR_OF(sqc
, param
->sqc
, wq
);
1004 struct mlx5_core_dev
*mdev
= c
->mdev
;
1008 sq
->mkey_be
= c
->mkey_be
;
1010 sq
->uar_map
= mdev
->mlx5e_res
.bfreg
.map
;
1011 sq
->min_inline_mode
= params
->tx_min_inline_mode
;
1013 param
->wq
.db_numa_node
= mlx5e_get_node(c
->priv
, c
->ix
);
1014 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
, &sq
->wq_ctrl
);
1017 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
1019 err
= mlx5e_alloc_xdpsq_db(sq
, mlx5e_get_node(c
->priv
, c
->ix
));
1021 goto err_sq_wq_destroy
;
1026 mlx5_wq_destroy(&sq
->wq_ctrl
);
1031 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq
*sq
)
1033 mlx5e_free_xdpsq_db(sq
);
1034 mlx5_wq_destroy(&sq
->wq_ctrl
);
1037 static void mlx5e_free_icosq_db(struct mlx5e_icosq
*sq
)
1039 kfree(sq
->db
.ico_wqe
);
1042 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq
*sq
, int numa
)
1044 u8 wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
1046 sq
->db
.ico_wqe
= kzalloc_node(sizeof(*sq
->db
.ico_wqe
) * wq_sz
,
1048 if (!sq
->db
.ico_wqe
)
1054 static int mlx5e_alloc_icosq(struct mlx5e_channel
*c
,
1055 struct mlx5e_sq_param
*param
,
1056 struct mlx5e_icosq
*sq
)
1058 void *sqc_wq
= MLX5_ADDR_OF(sqc
, param
->sqc
, wq
);
1059 struct mlx5_core_dev
*mdev
= c
->mdev
;
1062 sq
->mkey_be
= c
->mkey_be
;
1064 sq
->uar_map
= mdev
->mlx5e_res
.bfreg
.map
;
1066 param
->wq
.db_numa_node
= mlx5e_get_node(c
->priv
, c
->ix
);
1067 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
, &sq
->wq_ctrl
);
1070 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
1072 err
= mlx5e_alloc_icosq_db(sq
, mlx5e_get_node(c
->priv
, c
->ix
));
1074 goto err_sq_wq_destroy
;
1076 sq
->edge
= (sq
->wq
.sz_m1
+ 1) - MLX5E_ICOSQ_MAX_WQEBBS
;
1081 mlx5_wq_destroy(&sq
->wq_ctrl
);
1086 static void mlx5e_free_icosq(struct mlx5e_icosq
*sq
)
1088 mlx5e_free_icosq_db(sq
);
1089 mlx5_wq_destroy(&sq
->wq_ctrl
);
1092 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq
*sq
)
1094 kfree(sq
->db
.wqe_info
);
1095 kfree(sq
->db
.dma_fifo
);
1098 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq
*sq
, int numa
)
1100 int wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
1101 int df_sz
= wq_sz
* MLX5_SEND_WQEBB_NUM_DS
;
1103 sq
->db
.dma_fifo
= kzalloc_node(df_sz
* sizeof(*sq
->db
.dma_fifo
),
1105 sq
->db
.wqe_info
= kzalloc_node(wq_sz
* sizeof(*sq
->db
.wqe_info
),
1107 if (!sq
->db
.dma_fifo
|| !sq
->db
.wqe_info
) {
1108 mlx5e_free_txqsq_db(sq
);
1112 sq
->dma_fifo_mask
= df_sz
- 1;
1117 static int mlx5e_alloc_txqsq(struct mlx5e_channel
*c
,
1119 struct mlx5e_params
*params
,
1120 struct mlx5e_sq_param
*param
,
1121 struct mlx5e_txqsq
*sq
)
1123 void *sqc_wq
= MLX5_ADDR_OF(sqc
, param
->sqc
, wq
);
1124 struct mlx5_core_dev
*mdev
= c
->mdev
;
1128 sq
->tstamp
= c
->tstamp
;
1129 sq
->mkey_be
= c
->mkey_be
;
1131 sq
->txq_ix
= txq_ix
;
1132 sq
->uar_map
= mdev
->mlx5e_res
.bfreg
.map
;
1133 sq
->max_inline
= params
->tx_max_inline
;
1134 sq
->min_inline_mode
= params
->tx_min_inline_mode
;
1135 if (MLX5_IPSEC_DEV(c
->priv
->mdev
))
1136 set_bit(MLX5E_SQ_STATE_IPSEC
, &sq
->state
);
1138 param
->wq
.db_numa_node
= mlx5e_get_node(c
->priv
, c
->ix
);
1139 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
, &sq
->wq_ctrl
);
1142 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
1144 err
= mlx5e_alloc_txqsq_db(sq
, mlx5e_get_node(c
->priv
, c
->ix
));
1146 goto err_sq_wq_destroy
;
1148 sq
->edge
= (sq
->wq
.sz_m1
+ 1) - MLX5_SEND_WQE_MAX_WQEBBS
;
1153 mlx5_wq_destroy(&sq
->wq_ctrl
);
1158 static void mlx5e_free_txqsq(struct mlx5e_txqsq
*sq
)
1160 mlx5e_free_txqsq_db(sq
);
1161 mlx5_wq_destroy(&sq
->wq_ctrl
);
1164 struct mlx5e_create_sq_param
{
1165 struct mlx5_wq_ctrl
*wq_ctrl
;
1172 static int mlx5e_create_sq(struct mlx5_core_dev
*mdev
,
1173 struct mlx5e_sq_param
*param
,
1174 struct mlx5e_create_sq_param
*csp
,
1183 inlen
= MLX5_ST_SZ_BYTES(create_sq_in
) +
1184 sizeof(u64
) * csp
->wq_ctrl
->buf
.npages
;
1185 in
= kvzalloc(inlen
, GFP_KERNEL
);
1189 sqc
= MLX5_ADDR_OF(create_sq_in
, in
, ctx
);
1190 wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1192 memcpy(sqc
, param
->sqc
, sizeof(param
->sqc
));
1193 MLX5_SET(sqc
, sqc
, tis_lst_sz
, csp
->tis_lst_sz
);
1194 MLX5_SET(sqc
, sqc
, tis_num_0
, csp
->tisn
);
1195 MLX5_SET(sqc
, sqc
, cqn
, csp
->cqn
);
1197 if (MLX5_CAP_ETH(mdev
, wqe_inline_mode
) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT
)
1198 MLX5_SET(sqc
, sqc
, min_wqe_inline_mode
, csp
->min_inline_mode
);
1200 MLX5_SET(sqc
, sqc
, state
, MLX5_SQC_STATE_RST
);
1202 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
1203 MLX5_SET(wq
, wq
, uar_page
, mdev
->mlx5e_res
.bfreg
.index
);
1204 MLX5_SET(wq
, wq
, log_wq_pg_sz
, csp
->wq_ctrl
->buf
.page_shift
-
1205 MLX5_ADAPTER_PAGE_SHIFT
);
1206 MLX5_SET64(wq
, wq
, dbr_addr
, csp
->wq_ctrl
->db
.dma
);
1208 mlx5_fill_page_array(&csp
->wq_ctrl
->buf
, (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
1210 err
= mlx5_core_create_sq(mdev
, in
, inlen
, sqn
);
1217 struct mlx5e_modify_sq_param
{
1224 static int mlx5e_modify_sq(struct mlx5_core_dev
*mdev
, u32 sqn
,
1225 struct mlx5e_modify_sq_param
*p
)
1232 inlen
= MLX5_ST_SZ_BYTES(modify_sq_in
);
1233 in
= kvzalloc(inlen
, GFP_KERNEL
);
1237 sqc
= MLX5_ADDR_OF(modify_sq_in
, in
, ctx
);
1239 MLX5_SET(modify_sq_in
, in
, sq_state
, p
->curr_state
);
1240 MLX5_SET(sqc
, sqc
, state
, p
->next_state
);
1241 if (p
->rl_update
&& p
->next_state
== MLX5_SQC_STATE_RDY
) {
1242 MLX5_SET64(modify_sq_in
, in
, modify_bitmask
, 1);
1243 MLX5_SET(sqc
, sqc
, packet_pacing_rate_limit_index
, p
->rl_index
);
1246 err
= mlx5_core_modify_sq(mdev
, sqn
, in
, inlen
);
1253 static void mlx5e_destroy_sq(struct mlx5_core_dev
*mdev
, u32 sqn
)
1255 mlx5_core_destroy_sq(mdev
, sqn
);
1258 static int mlx5e_create_sq_rdy(struct mlx5_core_dev
*mdev
,
1259 struct mlx5e_sq_param
*param
,
1260 struct mlx5e_create_sq_param
*csp
,
1263 struct mlx5e_modify_sq_param msp
= {0};
1266 err
= mlx5e_create_sq(mdev
, param
, csp
, sqn
);
1270 msp
.curr_state
= MLX5_SQC_STATE_RST
;
1271 msp
.next_state
= MLX5_SQC_STATE_RDY
;
1272 err
= mlx5e_modify_sq(mdev
, *sqn
, &msp
);
1274 mlx5e_destroy_sq(mdev
, *sqn
);
1279 static int mlx5e_set_sq_maxrate(struct net_device
*dev
,
1280 struct mlx5e_txqsq
*sq
, u32 rate
);
1282 static int mlx5e_open_txqsq(struct mlx5e_channel
*c
,
1285 struct mlx5e_params
*params
,
1286 struct mlx5e_sq_param
*param
,
1287 struct mlx5e_txqsq
*sq
)
1289 struct mlx5e_create_sq_param csp
= {};
1293 err
= mlx5e_alloc_txqsq(c
, txq_ix
, params
, param
, sq
);
1299 csp
.cqn
= sq
->cq
.mcq
.cqn
;
1300 csp
.wq_ctrl
= &sq
->wq_ctrl
;
1301 csp
.min_inline_mode
= sq
->min_inline_mode
;
1302 err
= mlx5e_create_sq_rdy(c
->mdev
, param
, &csp
, &sq
->sqn
);
1304 goto err_free_txqsq
;
1306 tx_rate
= c
->priv
->tx_rates
[sq
->txq_ix
];
1308 mlx5e_set_sq_maxrate(c
->netdev
, sq
, tx_rate
);
1313 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1314 mlx5e_free_txqsq(sq
);
1319 static void mlx5e_activate_txqsq(struct mlx5e_txqsq
*sq
)
1321 sq
->txq
= netdev_get_tx_queue(sq
->channel
->netdev
, sq
->txq_ix
);
1322 set_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1323 netdev_tx_reset_queue(sq
->txq
);
1324 netif_tx_start_queue(sq
->txq
);
1327 static inline void netif_tx_disable_queue(struct netdev_queue
*txq
)
1329 __netif_tx_lock_bh(txq
);
1330 netif_tx_stop_queue(txq
);
1331 __netif_tx_unlock_bh(txq
);
1334 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq
*sq
)
1336 struct mlx5e_channel
*c
= sq
->channel
;
1338 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1339 /* prevent netif_tx_wake_queue */
1340 napi_synchronize(&c
->napi
);
1342 netif_tx_disable_queue(sq
->txq
);
1344 /* last doorbell out, godspeed .. */
1345 if (mlx5e_wqc_has_room_for(&sq
->wq
, sq
->cc
, sq
->pc
, 1)) {
1346 struct mlx5e_tx_wqe
*nop
;
1348 sq
->db
.wqe_info
[(sq
->pc
& sq
->wq
.sz_m1
)].skb
= NULL
;
1349 nop
= mlx5e_post_nop(&sq
->wq
, sq
->sqn
, &sq
->pc
);
1350 mlx5e_notify_hw(&sq
->wq
, sq
->pc
, sq
->uar_map
, &nop
->ctrl
);
1354 static void mlx5e_close_txqsq(struct mlx5e_txqsq
*sq
)
1356 struct mlx5e_channel
*c
= sq
->channel
;
1357 struct mlx5_core_dev
*mdev
= c
->mdev
;
1359 mlx5e_destroy_sq(mdev
, sq
->sqn
);
1361 mlx5_rl_remove_rate(mdev
, sq
->rate_limit
);
1362 mlx5e_free_txqsq_descs(sq
);
1363 mlx5e_free_txqsq(sq
);
1366 static int mlx5e_open_icosq(struct mlx5e_channel
*c
,
1367 struct mlx5e_params
*params
,
1368 struct mlx5e_sq_param
*param
,
1369 struct mlx5e_icosq
*sq
)
1371 struct mlx5e_create_sq_param csp
= {};
1374 err
= mlx5e_alloc_icosq(c
, param
, sq
);
1378 csp
.cqn
= sq
->cq
.mcq
.cqn
;
1379 csp
.wq_ctrl
= &sq
->wq_ctrl
;
1380 csp
.min_inline_mode
= params
->tx_min_inline_mode
;
1381 set_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1382 err
= mlx5e_create_sq_rdy(c
->mdev
, param
, &csp
, &sq
->sqn
);
1384 goto err_free_icosq
;
1389 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1390 mlx5e_free_icosq(sq
);
1395 static void mlx5e_close_icosq(struct mlx5e_icosq
*sq
)
1397 struct mlx5e_channel
*c
= sq
->channel
;
1399 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1400 napi_synchronize(&c
->napi
);
1402 mlx5e_destroy_sq(c
->mdev
, sq
->sqn
);
1403 mlx5e_free_icosq(sq
);
1406 static int mlx5e_open_xdpsq(struct mlx5e_channel
*c
,
1407 struct mlx5e_params
*params
,
1408 struct mlx5e_sq_param
*param
,
1409 struct mlx5e_xdpsq
*sq
)
1411 unsigned int ds_cnt
= MLX5E_XDP_TX_DS_COUNT
;
1412 struct mlx5e_create_sq_param csp
= {};
1413 unsigned int inline_hdr_sz
= 0;
1417 err
= mlx5e_alloc_xdpsq(c
, params
, param
, sq
);
1422 csp
.tisn
= c
->priv
->tisn
[0]; /* tc = 0 */
1423 csp
.cqn
= sq
->cq
.mcq
.cqn
;
1424 csp
.wq_ctrl
= &sq
->wq_ctrl
;
1425 csp
.min_inline_mode
= sq
->min_inline_mode
;
1426 set_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1427 err
= mlx5e_create_sq_rdy(c
->mdev
, param
, &csp
, &sq
->sqn
);
1429 goto err_free_xdpsq
;
1431 if (sq
->min_inline_mode
!= MLX5_INLINE_MODE_NONE
) {
1432 inline_hdr_sz
= MLX5E_XDP_MIN_INLINE
;
1436 /* Pre initialize fixed WQE fields */
1437 for (i
= 0; i
< mlx5_wq_cyc_get_size(&sq
->wq
); i
++) {
1438 struct mlx5e_tx_wqe
*wqe
= mlx5_wq_cyc_get_wqe(&sq
->wq
, i
);
1439 struct mlx5_wqe_ctrl_seg
*cseg
= &wqe
->ctrl
;
1440 struct mlx5_wqe_eth_seg
*eseg
= &wqe
->eth
;
1441 struct mlx5_wqe_data_seg
*dseg
;
1443 cseg
->qpn_ds
= cpu_to_be32((sq
->sqn
<< 8) | ds_cnt
);
1444 eseg
->inline_hdr
.sz
= cpu_to_be16(inline_hdr_sz
);
1446 dseg
= (struct mlx5_wqe_data_seg
*)cseg
+ (ds_cnt
- 1);
1447 dseg
->lkey
= sq
->mkey_be
;
1453 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1454 mlx5e_free_xdpsq(sq
);
1459 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq
*sq
)
1461 struct mlx5e_channel
*c
= sq
->channel
;
1463 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1464 napi_synchronize(&c
->napi
);
1466 mlx5e_destroy_sq(c
->mdev
, sq
->sqn
);
1467 mlx5e_free_xdpsq_descs(sq
);
1468 mlx5e_free_xdpsq(sq
);
1471 static int mlx5e_alloc_cq_common(struct mlx5_core_dev
*mdev
,
1472 struct mlx5e_cq_param
*param
,
1473 struct mlx5e_cq
*cq
)
1475 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
1481 err
= mlx5_cqwq_create(mdev
, ¶m
->wq
, param
->cqc
, &cq
->wq
,
1486 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn_not_used
, &irqn
);
1489 mcq
->set_ci_db
= cq
->wq_ctrl
.db
.db
;
1490 mcq
->arm_db
= cq
->wq_ctrl
.db
.db
+ 1;
1491 *mcq
->set_ci_db
= 0;
1493 mcq
->vector
= param
->eq_ix
;
1494 mcq
->comp
= mlx5e_completion_event
;
1495 mcq
->event
= mlx5e_cq_error_event
;
1498 for (i
= 0; i
< mlx5_cqwq_get_size(&cq
->wq
); i
++) {
1499 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, i
);
1509 static int mlx5e_alloc_cq(struct mlx5e_channel
*c
,
1510 struct mlx5e_cq_param
*param
,
1511 struct mlx5e_cq
*cq
)
1513 struct mlx5_core_dev
*mdev
= c
->priv
->mdev
;
1516 param
->wq
.buf_numa_node
= mlx5e_get_node(c
->priv
, c
->ix
);
1517 param
->wq
.db_numa_node
= mlx5e_get_node(c
->priv
, c
->ix
);
1518 param
->eq_ix
= c
->ix
;
1520 err
= mlx5e_alloc_cq_common(mdev
, param
, cq
);
1522 cq
->napi
= &c
->napi
;
1528 static void mlx5e_free_cq(struct mlx5e_cq
*cq
)
1530 mlx5_cqwq_destroy(&cq
->wq_ctrl
);
1533 static int mlx5e_create_cq(struct mlx5e_cq
*cq
, struct mlx5e_cq_param
*param
)
1535 struct mlx5_core_dev
*mdev
= cq
->mdev
;
1536 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
1541 unsigned int irqn_not_used
;
1545 inlen
= MLX5_ST_SZ_BYTES(create_cq_in
) +
1546 sizeof(u64
) * cq
->wq_ctrl
.frag_buf
.npages
;
1547 in
= kvzalloc(inlen
, GFP_KERNEL
);
1551 cqc
= MLX5_ADDR_OF(create_cq_in
, in
, cq_context
);
1553 memcpy(cqc
, param
->cqc
, sizeof(param
->cqc
));
1555 mlx5_fill_page_frag_array(&cq
->wq_ctrl
.frag_buf
,
1556 (__be64
*)MLX5_ADDR_OF(create_cq_in
, in
, pas
));
1558 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn
, &irqn_not_used
);
1560 MLX5_SET(cqc
, cqc
, cq_period_mode
, param
->cq_period_mode
);
1561 MLX5_SET(cqc
, cqc
, c_eqn
, eqn
);
1562 MLX5_SET(cqc
, cqc
, uar_page
, mdev
->priv
.uar
->index
);
1563 MLX5_SET(cqc
, cqc
, log_page_size
, cq
->wq_ctrl
.frag_buf
.page_shift
-
1564 MLX5_ADAPTER_PAGE_SHIFT
);
1565 MLX5_SET64(cqc
, cqc
, dbr_addr
, cq
->wq_ctrl
.db
.dma
);
1567 err
= mlx5_core_create_cq(mdev
, mcq
, in
, inlen
);
1579 static void mlx5e_destroy_cq(struct mlx5e_cq
*cq
)
1581 mlx5_core_destroy_cq(cq
->mdev
, &cq
->mcq
);
1584 static int mlx5e_open_cq(struct mlx5e_channel
*c
,
1585 struct mlx5e_cq_moder moder
,
1586 struct mlx5e_cq_param
*param
,
1587 struct mlx5e_cq
*cq
)
1589 struct mlx5_core_dev
*mdev
= c
->mdev
;
1592 err
= mlx5e_alloc_cq(c
, param
, cq
);
1596 err
= mlx5e_create_cq(cq
, param
);
1600 if (MLX5_CAP_GEN(mdev
, cq_moderation
))
1601 mlx5_core_modify_cq_moderation(mdev
, &cq
->mcq
, moder
.usec
, moder
.pkts
);
1610 static void mlx5e_close_cq(struct mlx5e_cq
*cq
)
1612 mlx5e_destroy_cq(cq
);
1616 static int mlx5e_open_tx_cqs(struct mlx5e_channel
*c
,
1617 struct mlx5e_params
*params
,
1618 struct mlx5e_channel_param
*cparam
)
1623 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
1624 err
= mlx5e_open_cq(c
, params
->tx_cq_moderation
,
1625 &cparam
->tx_cq
, &c
->sq
[tc
].cq
);
1627 goto err_close_tx_cqs
;
1633 for (tc
--; tc
>= 0; tc
--)
1634 mlx5e_close_cq(&c
->sq
[tc
].cq
);
1639 static void mlx5e_close_tx_cqs(struct mlx5e_channel
*c
)
1643 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1644 mlx5e_close_cq(&c
->sq
[tc
].cq
);
1647 static int mlx5e_open_sqs(struct mlx5e_channel
*c
,
1648 struct mlx5e_params
*params
,
1649 struct mlx5e_channel_param
*cparam
)
1654 for (tc
= 0; tc
< params
->num_tc
; tc
++) {
1655 int txq_ix
= c
->ix
+ tc
* params
->num_channels
;
1657 err
= mlx5e_open_txqsq(c
, c
->priv
->tisn
[tc
], txq_ix
,
1658 params
, &cparam
->sq
, &c
->sq
[tc
]);
1666 for (tc
--; tc
>= 0; tc
--)
1667 mlx5e_close_txqsq(&c
->sq
[tc
]);
1672 static void mlx5e_close_sqs(struct mlx5e_channel
*c
)
1676 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1677 mlx5e_close_txqsq(&c
->sq
[tc
]);
1680 static int mlx5e_set_sq_maxrate(struct net_device
*dev
,
1681 struct mlx5e_txqsq
*sq
, u32 rate
)
1683 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1684 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1685 struct mlx5e_modify_sq_param msp
= {0};
1689 if (rate
== sq
->rate_limit
)
1694 /* remove current rl index to free space to next ones */
1695 mlx5_rl_remove_rate(mdev
, sq
->rate_limit
);
1700 err
= mlx5_rl_add_rate(mdev
, rate
, &rl_index
);
1702 netdev_err(dev
, "Failed configuring rate %u: %d\n",
1708 msp
.curr_state
= MLX5_SQC_STATE_RDY
;
1709 msp
.next_state
= MLX5_SQC_STATE_RDY
;
1710 msp
.rl_index
= rl_index
;
1711 msp
.rl_update
= true;
1712 err
= mlx5e_modify_sq(mdev
, sq
->sqn
, &msp
);
1714 netdev_err(dev
, "Failed configuring rate %u: %d\n",
1716 /* remove the rate from the table */
1718 mlx5_rl_remove_rate(mdev
, rate
);
1722 sq
->rate_limit
= rate
;
1726 static int mlx5e_set_tx_maxrate(struct net_device
*dev
, int index
, u32 rate
)
1728 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1729 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1730 struct mlx5e_txqsq
*sq
= priv
->txq2sq
[index
];
1733 if (!mlx5_rl_is_supported(mdev
)) {
1734 netdev_err(dev
, "Rate limiting is not supported on this device\n");
1738 /* rate is given in Mb/sec, HW config is in Kb/sec */
1741 /* Check whether rate in valid range, 0 is always valid */
1742 if (rate
&& !mlx5_rl_is_in_range(mdev
, rate
)) {
1743 netdev_err(dev
, "TX rate %u, is not in range\n", rate
);
1747 mutex_lock(&priv
->state_lock
);
1748 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
1749 err
= mlx5e_set_sq_maxrate(dev
, sq
, rate
);
1751 priv
->tx_rates
[index
] = rate
;
1752 mutex_unlock(&priv
->state_lock
);
1757 static int mlx5e_open_channel(struct mlx5e_priv
*priv
, int ix
,
1758 struct mlx5e_params
*params
,
1759 struct mlx5e_channel_param
*cparam
,
1760 struct mlx5e_channel
**cp
)
1762 struct mlx5e_cq_moder icocq_moder
= {0, 0};
1763 struct net_device
*netdev
= priv
->netdev
;
1764 struct mlx5e_channel
*c
;
1769 c
= kzalloc_node(sizeof(*c
), GFP_KERNEL
, mlx5e_get_node(priv
, ix
));
1774 c
->mdev
= priv
->mdev
;
1775 c
->tstamp
= &priv
->tstamp
;
1777 c
->pdev
= &priv
->mdev
->pdev
->dev
;
1778 c
->netdev
= priv
->netdev
;
1779 c
->mkey_be
= cpu_to_be32(priv
->mdev
->mlx5e_res
.mkey
.key
);
1780 c
->num_tc
= params
->num_tc
;
1781 c
->xdp
= !!params
->xdp_prog
;
1783 mlx5_vector2eqn(priv
->mdev
, ix
, &eqn
, &irq
);
1784 c
->irq_desc
= irq_to_desc(irq
);
1786 netif_napi_add(netdev
, &c
->napi
, mlx5e_napi_poll
, 64);
1788 err
= mlx5e_open_cq(c
, icocq_moder
, &cparam
->icosq_cq
, &c
->icosq
.cq
);
1792 err
= mlx5e_open_tx_cqs(c
, params
, cparam
);
1794 goto err_close_icosq_cq
;
1796 err
= mlx5e_open_cq(c
, params
->rx_cq_moderation
, &cparam
->rx_cq
, &c
->rq
.cq
);
1798 goto err_close_tx_cqs
;
1800 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1801 err
= c
->xdp
? mlx5e_open_cq(c
, params
->tx_cq_moderation
,
1802 &cparam
->tx_cq
, &c
->rq
.xdpsq
.cq
) : 0;
1804 goto err_close_rx_cq
;
1806 napi_enable(&c
->napi
);
1808 err
= mlx5e_open_icosq(c
, params
, &cparam
->icosq
, &c
->icosq
);
1810 goto err_disable_napi
;
1812 err
= mlx5e_open_sqs(c
, params
, cparam
);
1814 goto err_close_icosq
;
1816 err
= c
->xdp
? mlx5e_open_xdpsq(c
, params
, &cparam
->xdp_sq
, &c
->rq
.xdpsq
) : 0;
1820 err
= mlx5e_open_rq(c
, params
, &cparam
->rq
, &c
->rq
);
1822 goto err_close_xdp_sq
;
1829 mlx5e_close_xdpsq(&c
->rq
.xdpsq
);
1835 mlx5e_close_icosq(&c
->icosq
);
1838 napi_disable(&c
->napi
);
1840 mlx5e_close_cq(&c
->rq
.xdpsq
.cq
);
1843 mlx5e_close_cq(&c
->rq
.cq
);
1846 mlx5e_close_tx_cqs(c
);
1849 mlx5e_close_cq(&c
->icosq
.cq
);
1852 netif_napi_del(&c
->napi
);
1858 static void mlx5e_activate_channel(struct mlx5e_channel
*c
)
1862 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1863 mlx5e_activate_txqsq(&c
->sq
[tc
]);
1864 mlx5e_activate_rq(&c
->rq
);
1865 netif_set_xps_queue(c
->netdev
,
1866 mlx5_get_vector_affinity(c
->priv
->mdev
, c
->ix
), c
->ix
);
1869 static void mlx5e_deactivate_channel(struct mlx5e_channel
*c
)
1873 mlx5e_deactivate_rq(&c
->rq
);
1874 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1875 mlx5e_deactivate_txqsq(&c
->sq
[tc
]);
1878 static void mlx5e_close_channel(struct mlx5e_channel
*c
)
1880 mlx5e_close_rq(&c
->rq
);
1882 mlx5e_close_xdpsq(&c
->rq
.xdpsq
);
1884 mlx5e_close_icosq(&c
->icosq
);
1885 napi_disable(&c
->napi
);
1887 mlx5e_close_cq(&c
->rq
.xdpsq
.cq
);
1888 mlx5e_close_cq(&c
->rq
.cq
);
1889 mlx5e_close_tx_cqs(c
);
1890 mlx5e_close_cq(&c
->icosq
.cq
);
1891 netif_napi_del(&c
->napi
);
1896 static void mlx5e_build_rq_param(struct mlx5e_priv
*priv
,
1897 struct mlx5e_params
*params
,
1898 struct mlx5e_rq_param
*param
)
1900 void *rqc
= param
->rqc
;
1901 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1903 switch (params
->rq_wq_type
) {
1904 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
1905 MLX5_SET(wq
, wq
, log_wqe_num_of_strides
, params
->mpwqe_log_num_strides
- 9);
1906 MLX5_SET(wq
, wq
, log_wqe_stride_size
, params
->mpwqe_log_stride_sz
- 6);
1907 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
);
1909 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1910 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1913 MLX5_SET(wq
, wq
, end_padding_mode
, MLX5_WQ_END_PAD_MODE_ALIGN
);
1914 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1915 MLX5_SET(wq
, wq
, log_wq_sz
, params
->log_rq_size
);
1916 MLX5_SET(wq
, wq
, pd
, priv
->mdev
->mlx5e_res
.pdn
);
1917 MLX5_SET(rqc
, rqc
, counter_set_id
, priv
->q_counter
);
1918 MLX5_SET(rqc
, rqc
, vsd
, params
->vlan_strip_disable
);
1919 MLX5_SET(rqc
, rqc
, scatter_fcs
, params
->scatter_fcs_en
);
1921 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1922 param
->wq
.linear
= 1;
1925 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param
*param
)
1927 void *rqc
= param
->rqc
;
1928 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1930 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1931 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1934 static void mlx5e_build_sq_param_common(struct mlx5e_priv
*priv
,
1935 struct mlx5e_sq_param
*param
)
1937 void *sqc
= param
->sqc
;
1938 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1940 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(MLX5_SEND_WQE_BB
));
1941 MLX5_SET(wq
, wq
, pd
, priv
->mdev
->mlx5e_res
.pdn
);
1943 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1946 static void mlx5e_build_sq_param(struct mlx5e_priv
*priv
,
1947 struct mlx5e_params
*params
,
1948 struct mlx5e_sq_param
*param
)
1950 void *sqc
= param
->sqc
;
1951 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1953 mlx5e_build_sq_param_common(priv
, param
);
1954 MLX5_SET(wq
, wq
, log_wq_sz
, params
->log_sq_size
);
1955 MLX5_SET(sqc
, sqc
, allow_swp
, !!MLX5_IPSEC_DEV(priv
->mdev
));
1958 static void mlx5e_build_common_cq_param(struct mlx5e_priv
*priv
,
1959 struct mlx5e_cq_param
*param
)
1961 void *cqc
= param
->cqc
;
1963 MLX5_SET(cqc
, cqc
, uar_page
, priv
->mdev
->priv
.uar
->index
);
1966 static void mlx5e_build_rx_cq_param(struct mlx5e_priv
*priv
,
1967 struct mlx5e_params
*params
,
1968 struct mlx5e_cq_param
*param
)
1970 void *cqc
= param
->cqc
;
1973 switch (params
->rq_wq_type
) {
1974 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
1975 log_cq_size
= params
->log_rq_size
+ params
->mpwqe_log_num_strides
;
1977 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1978 log_cq_size
= params
->log_rq_size
;
1981 MLX5_SET(cqc
, cqc
, log_cq_size
, log_cq_size
);
1982 if (MLX5E_GET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_COMPRESS
)) {
1983 MLX5_SET(cqc
, cqc
, mini_cqe_res_format
, MLX5_CQE_FORMAT_CSUM
);
1984 MLX5_SET(cqc
, cqc
, cqe_comp_en
, 1);
1987 mlx5e_build_common_cq_param(priv
, param
);
1988 param
->cq_period_mode
= params
->rx_cq_period_mode
;
1991 static void mlx5e_build_tx_cq_param(struct mlx5e_priv
*priv
,
1992 struct mlx5e_params
*params
,
1993 struct mlx5e_cq_param
*param
)
1995 void *cqc
= param
->cqc
;
1997 MLX5_SET(cqc
, cqc
, log_cq_size
, params
->log_sq_size
);
1999 mlx5e_build_common_cq_param(priv
, param
);
2001 param
->cq_period_mode
= MLX5_CQ_PERIOD_MODE_START_FROM_EQE
;
2004 static void mlx5e_build_ico_cq_param(struct mlx5e_priv
*priv
,
2006 struct mlx5e_cq_param
*param
)
2008 void *cqc
= param
->cqc
;
2010 MLX5_SET(cqc
, cqc
, log_cq_size
, log_wq_size
);
2012 mlx5e_build_common_cq_param(priv
, param
);
2014 param
->cq_period_mode
= MLX5_CQ_PERIOD_MODE_START_FROM_EQE
;
2017 static void mlx5e_build_icosq_param(struct mlx5e_priv
*priv
,
2019 struct mlx5e_sq_param
*param
)
2021 void *sqc
= param
->sqc
;
2022 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
2024 mlx5e_build_sq_param_common(priv
, param
);
2026 MLX5_SET(wq
, wq
, log_wq_sz
, log_wq_size
);
2027 MLX5_SET(sqc
, sqc
, reg_umr
, MLX5_CAP_ETH(priv
->mdev
, reg_umr_sq
));
2030 static void mlx5e_build_xdpsq_param(struct mlx5e_priv
*priv
,
2031 struct mlx5e_params
*params
,
2032 struct mlx5e_sq_param
*param
)
2034 void *sqc
= param
->sqc
;
2035 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
2037 mlx5e_build_sq_param_common(priv
, param
);
2038 MLX5_SET(wq
, wq
, log_wq_sz
, params
->log_sq_size
);
2041 static void mlx5e_build_channel_param(struct mlx5e_priv
*priv
,
2042 struct mlx5e_params
*params
,
2043 struct mlx5e_channel_param
*cparam
)
2045 u8 icosq_log_wq_sz
= MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE
;
2047 mlx5e_build_rq_param(priv
, params
, &cparam
->rq
);
2048 mlx5e_build_sq_param(priv
, params
, &cparam
->sq
);
2049 mlx5e_build_xdpsq_param(priv
, params
, &cparam
->xdp_sq
);
2050 mlx5e_build_icosq_param(priv
, icosq_log_wq_sz
, &cparam
->icosq
);
2051 mlx5e_build_rx_cq_param(priv
, params
, &cparam
->rx_cq
);
2052 mlx5e_build_tx_cq_param(priv
, params
, &cparam
->tx_cq
);
2053 mlx5e_build_ico_cq_param(priv
, icosq_log_wq_sz
, &cparam
->icosq_cq
);
2056 int mlx5e_open_channels(struct mlx5e_priv
*priv
,
2057 struct mlx5e_channels
*chs
)
2059 struct mlx5e_channel_param
*cparam
;
2063 chs
->num
= chs
->params
.num_channels
;
2065 chs
->c
= kcalloc(chs
->num
, sizeof(struct mlx5e_channel
*), GFP_KERNEL
);
2066 cparam
= kzalloc(sizeof(struct mlx5e_channel_param
), GFP_KERNEL
);
2067 if (!chs
->c
|| !cparam
)
2070 mlx5e_build_channel_param(priv
, &chs
->params
, cparam
);
2071 for (i
= 0; i
< chs
->num
; i
++) {
2072 err
= mlx5e_open_channel(priv
, i
, &chs
->params
, cparam
, &chs
->c
[i
]);
2074 goto err_close_channels
;
2081 for (i
--; i
>= 0; i
--)
2082 mlx5e_close_channel(chs
->c
[i
]);
2091 static void mlx5e_activate_channels(struct mlx5e_channels
*chs
)
2095 for (i
= 0; i
< chs
->num
; i
++)
2096 mlx5e_activate_channel(chs
->c
[i
]);
2099 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels
*chs
)
2104 for (i
= 0; i
< chs
->num
; i
++) {
2105 err
= mlx5e_wait_for_min_rx_wqes(&chs
->c
[i
]->rq
);
2113 static void mlx5e_deactivate_channels(struct mlx5e_channels
*chs
)
2117 for (i
= 0; i
< chs
->num
; i
++)
2118 mlx5e_deactivate_channel(chs
->c
[i
]);
2121 void mlx5e_close_channels(struct mlx5e_channels
*chs
)
2125 for (i
= 0; i
< chs
->num
; i
++)
2126 mlx5e_close_channel(chs
->c
[i
]);
2133 mlx5e_create_rqt(struct mlx5e_priv
*priv
, int sz
, struct mlx5e_rqt
*rqt
)
2135 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2142 inlen
= MLX5_ST_SZ_BYTES(create_rqt_in
) + sizeof(u32
) * sz
;
2143 in
= kvzalloc(inlen
, GFP_KERNEL
);
2147 rqtc
= MLX5_ADDR_OF(create_rqt_in
, in
, rqt_context
);
2149 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
2150 MLX5_SET(rqtc
, rqtc
, rqt_max_size
, sz
);
2152 for (i
= 0; i
< sz
; i
++)
2153 MLX5_SET(rqtc
, rqtc
, rq_num
[i
], priv
->drop_rq
.rqn
);
2155 err
= mlx5_core_create_rqt(mdev
, in
, inlen
, &rqt
->rqtn
);
2157 rqt
->enabled
= true;
2163 void mlx5e_destroy_rqt(struct mlx5e_priv
*priv
, struct mlx5e_rqt
*rqt
)
2165 rqt
->enabled
= false;
2166 mlx5_core_destroy_rqt(priv
->mdev
, rqt
->rqtn
);
2169 int mlx5e_create_indirect_rqt(struct mlx5e_priv
*priv
)
2171 struct mlx5e_rqt
*rqt
= &priv
->indir_rqt
;
2174 err
= mlx5e_create_rqt(priv
, MLX5E_INDIR_RQT_SIZE
, rqt
);
2176 mlx5_core_warn(priv
->mdev
, "create indirect rqts failed, %d\n", err
);
2180 int mlx5e_create_direct_rqts(struct mlx5e_priv
*priv
)
2182 struct mlx5e_rqt
*rqt
;
2186 for (ix
= 0; ix
< priv
->profile
->max_nch(priv
->mdev
); ix
++) {
2187 rqt
= &priv
->direct_tir
[ix
].rqt
;
2188 err
= mlx5e_create_rqt(priv
, 1 /*size */, rqt
);
2190 goto err_destroy_rqts
;
2196 mlx5_core_warn(priv
->mdev
, "create direct rqts failed, %d\n", err
);
2197 for (ix
--; ix
>= 0; ix
--)
2198 mlx5e_destroy_rqt(priv
, &priv
->direct_tir
[ix
].rqt
);
2203 void mlx5e_destroy_direct_rqts(struct mlx5e_priv
*priv
)
2207 for (i
= 0; i
< priv
->profile
->max_nch(priv
->mdev
); i
++)
2208 mlx5e_destroy_rqt(priv
, &priv
->direct_tir
[i
].rqt
);
2211 static int mlx5e_rx_hash_fn(int hfunc
)
2213 return (hfunc
== ETH_RSS_HASH_TOP
) ?
2214 MLX5_RX_HASH_FN_TOEPLITZ
:
2215 MLX5_RX_HASH_FN_INVERTED_XOR8
;
2218 static int mlx5e_bits_invert(unsigned long a
, int size
)
2223 for (i
= 0; i
< size
; i
++)
2224 inv
|= (test_bit(size
- i
- 1, &a
) ? 1 : 0) << i
;
2229 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv
*priv
, int sz
,
2230 struct mlx5e_redirect_rqt_param rrp
, void *rqtc
)
2234 for (i
= 0; i
< sz
; i
++) {
2240 if (rrp
.rss
.hfunc
== ETH_RSS_HASH_XOR
)
2241 ix
= mlx5e_bits_invert(i
, ilog2(sz
));
2243 ix
= priv
->channels
.params
.indirection_rqt
[ix
];
2244 rqn
= rrp
.rss
.channels
->c
[ix
]->rq
.rqn
;
2248 MLX5_SET(rqtc
, rqtc
, rq_num
[i
], rqn
);
2252 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, u32 rqtn
, int sz
,
2253 struct mlx5e_redirect_rqt_param rrp
)
2255 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2261 inlen
= MLX5_ST_SZ_BYTES(modify_rqt_in
) + sizeof(u32
) * sz
;
2262 in
= kvzalloc(inlen
, GFP_KERNEL
);
2266 rqtc
= MLX5_ADDR_OF(modify_rqt_in
, in
, ctx
);
2268 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
2269 MLX5_SET(modify_rqt_in
, in
, bitmask
.rqn_list
, 1);
2270 mlx5e_fill_rqt_rqns(priv
, sz
, rrp
, rqtc
);
2271 err
= mlx5_core_modify_rqt(mdev
, rqtn
, in
, inlen
);
2277 static u32
mlx5e_get_direct_rqn(struct mlx5e_priv
*priv
, int ix
,
2278 struct mlx5e_redirect_rqt_param rrp
)
2283 if (ix
>= rrp
.rss
.channels
->num
)
2284 return priv
->drop_rq
.rqn
;
2286 return rrp
.rss
.channels
->c
[ix
]->rq
.rqn
;
2289 static void mlx5e_redirect_rqts(struct mlx5e_priv
*priv
,
2290 struct mlx5e_redirect_rqt_param rrp
)
2295 if (priv
->indir_rqt
.enabled
) {
2297 rqtn
= priv
->indir_rqt
.rqtn
;
2298 mlx5e_redirect_rqt(priv
, rqtn
, MLX5E_INDIR_RQT_SIZE
, rrp
);
2301 for (ix
= 0; ix
< priv
->profile
->max_nch(priv
->mdev
); ix
++) {
2302 struct mlx5e_redirect_rqt_param direct_rrp
= {
2305 .rqn
= mlx5e_get_direct_rqn(priv
, ix
, rrp
)
2309 /* Direct RQ Tables */
2310 if (!priv
->direct_tir
[ix
].rqt
.enabled
)
2313 rqtn
= priv
->direct_tir
[ix
].rqt
.rqtn
;
2314 mlx5e_redirect_rqt(priv
, rqtn
, 1, direct_rrp
);
2318 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv
*priv
,
2319 struct mlx5e_channels
*chs
)
2321 struct mlx5e_redirect_rqt_param rrp
= {
2326 .hfunc
= chs
->params
.rss_hfunc
,
2331 mlx5e_redirect_rqts(priv
, rrp
);
2334 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv
*priv
)
2336 struct mlx5e_redirect_rqt_param drop_rrp
= {
2339 .rqn
= priv
->drop_rq
.rqn
,
2343 mlx5e_redirect_rqts(priv
, drop_rrp
);
2346 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params
*params
, void *tirc
)
2348 if (!params
->lro_en
)
2351 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2353 MLX5_SET(tirc
, tirc
, lro_enable_mask
,
2354 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
|
2355 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
);
2356 MLX5_SET(tirc
, tirc
, lro_max_ip_payload_size
,
2357 (params
->lro_wqe_sz
- ROUGH_MAX_L2_L3_HDR_SZ
) >> 8);
2358 MLX5_SET(tirc
, tirc
, lro_timeout_period_usecs
, params
->lro_timeout
);
2361 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params
*params
,
2362 enum mlx5e_traffic_types tt
,
2363 void *tirc
, bool inner
)
2365 void *hfso
= inner
? MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_inner
) :
2366 MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_outer
);
2368 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2369 MLX5_HASH_FIELD_SEL_DST_IP)
2371 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2372 MLX5_HASH_FIELD_SEL_DST_IP |\
2373 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2374 MLX5_HASH_FIELD_SEL_L4_DPORT)
2376 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2377 MLX5_HASH_FIELD_SEL_DST_IP |\
2378 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2380 MLX5_SET(tirc
, tirc
, rx_hash_fn
, mlx5e_rx_hash_fn(params
->rss_hfunc
));
2381 if (params
->rss_hfunc
== ETH_RSS_HASH_TOP
) {
2382 void *rss_key
= MLX5_ADDR_OF(tirc
, tirc
,
2383 rx_hash_toeplitz_key
);
2384 size_t len
= MLX5_FLD_SZ_BYTES(tirc
,
2385 rx_hash_toeplitz_key
);
2387 MLX5_SET(tirc
, tirc
, rx_hash_symmetric
, 1);
2388 memcpy(rss_key
, params
->toeplitz_hash_key
, len
);
2392 case MLX5E_TT_IPV4_TCP
:
2393 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2394 MLX5_L3_PROT_TYPE_IPV4
);
2395 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2396 MLX5_L4_PROT_TYPE_TCP
);
2397 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2398 MLX5_HASH_IP_L4PORTS
);
2401 case MLX5E_TT_IPV6_TCP
:
2402 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2403 MLX5_L3_PROT_TYPE_IPV6
);
2404 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2405 MLX5_L4_PROT_TYPE_TCP
);
2406 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2407 MLX5_HASH_IP_L4PORTS
);
2410 case MLX5E_TT_IPV4_UDP
:
2411 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2412 MLX5_L3_PROT_TYPE_IPV4
);
2413 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2414 MLX5_L4_PROT_TYPE_UDP
);
2415 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2416 MLX5_HASH_IP_L4PORTS
);
2419 case MLX5E_TT_IPV6_UDP
:
2420 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2421 MLX5_L3_PROT_TYPE_IPV6
);
2422 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2423 MLX5_L4_PROT_TYPE_UDP
);
2424 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2425 MLX5_HASH_IP_L4PORTS
);
2428 case MLX5E_TT_IPV4_IPSEC_AH
:
2429 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2430 MLX5_L3_PROT_TYPE_IPV4
);
2431 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2432 MLX5_HASH_IP_IPSEC_SPI
);
2435 case MLX5E_TT_IPV6_IPSEC_AH
:
2436 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2437 MLX5_L3_PROT_TYPE_IPV6
);
2438 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2439 MLX5_HASH_IP_IPSEC_SPI
);
2442 case MLX5E_TT_IPV4_IPSEC_ESP
:
2443 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2444 MLX5_L3_PROT_TYPE_IPV4
);
2445 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2446 MLX5_HASH_IP_IPSEC_SPI
);
2449 case MLX5E_TT_IPV6_IPSEC_ESP
:
2450 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2451 MLX5_L3_PROT_TYPE_IPV6
);
2452 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2453 MLX5_HASH_IP_IPSEC_SPI
);
2457 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2458 MLX5_L3_PROT_TYPE_IPV4
);
2459 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2464 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2465 MLX5_L3_PROT_TYPE_IPV6
);
2466 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2470 WARN_ONCE(true, "%s: bad traffic type!\n", __func__
);
2474 static int mlx5e_modify_tirs_lro(struct mlx5e_priv
*priv
)
2476 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2485 inlen
= MLX5_ST_SZ_BYTES(modify_tir_in
);
2486 in
= kvzalloc(inlen
, GFP_KERNEL
);
2490 MLX5_SET(modify_tir_in
, in
, bitmask
.lro
, 1);
2491 tirc
= MLX5_ADDR_OF(modify_tir_in
, in
, ctx
);
2493 mlx5e_build_tir_ctx_lro(&priv
->channels
.params
, tirc
);
2495 for (tt
= 0; tt
< MLX5E_NUM_INDIR_TIRS
; tt
++) {
2496 err
= mlx5_core_modify_tir(mdev
, priv
->indir_tir
[tt
].tirn
, in
,
2502 for (ix
= 0; ix
< priv
->profile
->max_nch(priv
->mdev
); ix
++) {
2503 err
= mlx5_core_modify_tir(mdev
, priv
->direct_tir
[ix
].tirn
,
2515 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv
*priv
,
2516 enum mlx5e_traffic_types tt
,
2519 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->mdev
->mlx5e_res
.td
.tdn
);
2521 mlx5e_build_tir_ctx_lro(&priv
->channels
.params
, tirc
);
2523 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
2524 MLX5_SET(tirc
, tirc
, indirect_table
, priv
->indir_rqt
.rqtn
);
2525 MLX5_SET(tirc
, tirc
, tunneled_offload_en
, 0x1);
2527 mlx5e_build_indir_tir_ctx_hash(&priv
->channels
.params
, tt
, tirc
, true);
2530 static int mlx5e_set_mtu(struct mlx5e_priv
*priv
, u16 mtu
)
2532 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2533 u16 hw_mtu
= MLX5E_SW2HW_MTU(priv
, mtu
);
2536 err
= mlx5_set_port_mtu(mdev
, hw_mtu
, 1);
2540 /* Update vport context MTU */
2541 mlx5_modify_nic_vport_mtu(mdev
, hw_mtu
);
2545 static void mlx5e_query_mtu(struct mlx5e_priv
*priv
, u16
*mtu
)
2547 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2551 err
= mlx5_query_nic_vport_mtu(mdev
, &hw_mtu
);
2552 if (err
|| !hw_mtu
) /* fallback to port oper mtu */
2553 mlx5_query_port_oper_mtu(mdev
, &hw_mtu
, 1);
2555 *mtu
= MLX5E_HW2SW_MTU(priv
, hw_mtu
);
2558 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv
*priv
)
2560 struct net_device
*netdev
= priv
->netdev
;
2564 err
= mlx5e_set_mtu(priv
, netdev
->mtu
);
2568 mlx5e_query_mtu(priv
, &mtu
);
2569 if (mtu
!= netdev
->mtu
)
2570 netdev_warn(netdev
, "%s: VPort MTU %d is different than netdev mtu %d\n",
2571 __func__
, mtu
, netdev
->mtu
);
2577 static void mlx5e_netdev_set_tcs(struct net_device
*netdev
)
2579 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2580 int nch
= priv
->channels
.params
.num_channels
;
2581 int ntc
= priv
->channels
.params
.num_tc
;
2584 netdev_reset_tc(netdev
);
2589 netdev_set_num_tc(netdev
, ntc
);
2591 /* Map netdev TCs to offset 0
2592 * We have our own UP to TXQ mapping for QoS
2594 for (tc
= 0; tc
< ntc
; tc
++)
2595 netdev_set_tc_queue(netdev
, tc
, nch
, 0);
2598 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv
*priv
)
2600 struct mlx5e_channel
*c
;
2601 struct mlx5e_txqsq
*sq
;
2604 for (i
= 0; i
< priv
->channels
.num
; i
++)
2605 for (tc
= 0; tc
< priv
->profile
->max_tc
; tc
++)
2606 priv
->channel_tc2txq
[i
][tc
] = i
+ tc
* priv
->channels
.num
;
2608 for (i
= 0; i
< priv
->channels
.num
; i
++) {
2609 c
= priv
->channels
.c
[i
];
2610 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
2612 priv
->txq2sq
[sq
->txq_ix
] = sq
;
2617 void mlx5e_activate_priv_channels(struct mlx5e_priv
*priv
)
2619 int num_txqs
= priv
->channels
.num
* priv
->channels
.params
.num_tc
;
2620 struct net_device
*netdev
= priv
->netdev
;
2622 mlx5e_netdev_set_tcs(netdev
);
2623 netif_set_real_num_tx_queues(netdev
, num_txqs
);
2624 netif_set_real_num_rx_queues(netdev
, priv
->channels
.num
);
2626 mlx5e_build_channels_tx_maps(priv
);
2627 mlx5e_activate_channels(&priv
->channels
);
2628 netif_tx_start_all_queues(priv
->netdev
);
2630 if (MLX5_VPORT_MANAGER(priv
->mdev
))
2631 mlx5e_add_sqs_fwd_rules(priv
);
2633 mlx5e_wait_channels_min_rx_wqes(&priv
->channels
);
2634 mlx5e_redirect_rqts_to_channels(priv
, &priv
->channels
);
2637 void mlx5e_deactivate_priv_channels(struct mlx5e_priv
*priv
)
2639 mlx5e_redirect_rqts_to_drop(priv
);
2641 if (MLX5_VPORT_MANAGER(priv
->mdev
))
2642 mlx5e_remove_sqs_fwd_rules(priv
);
2644 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2645 * polling for inactive tx queues.
2647 netif_tx_stop_all_queues(priv
->netdev
);
2648 netif_tx_disable(priv
->netdev
);
2649 mlx5e_deactivate_channels(&priv
->channels
);
2652 void mlx5e_switch_priv_channels(struct mlx5e_priv
*priv
,
2653 struct mlx5e_channels
*new_chs
,
2654 mlx5e_fp_hw_modify hw_modify
)
2656 struct net_device
*netdev
= priv
->netdev
;
2659 new_num_txqs
= new_chs
->num
* new_chs
->params
.num_tc
;
2661 carrier_ok
= netif_carrier_ok(netdev
);
2662 netif_carrier_off(netdev
);
2664 if (new_num_txqs
< netdev
->real_num_tx_queues
)
2665 netif_set_real_num_tx_queues(netdev
, new_num_txqs
);
2667 mlx5e_deactivate_priv_channels(priv
);
2668 mlx5e_close_channels(&priv
->channels
);
2670 priv
->channels
= *new_chs
;
2672 /* New channels are ready to roll, modify HW settings if needed */
2676 mlx5e_refresh_tirs(priv
, false);
2677 mlx5e_activate_priv_channels(priv
);
2679 /* return carrier back if needed */
2681 netif_carrier_on(netdev
);
2684 int mlx5e_open_locked(struct net_device
*netdev
)
2686 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2689 set_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2691 err
= mlx5e_open_channels(priv
, &priv
->channels
);
2693 goto err_clear_state_opened_flag
;
2695 mlx5e_refresh_tirs(priv
, false);
2696 mlx5e_activate_priv_channels(priv
);
2697 if (priv
->profile
->update_carrier
)
2698 priv
->profile
->update_carrier(priv
);
2699 mlx5e_timestamp_init(priv
);
2701 if (priv
->profile
->update_stats
)
2702 queue_delayed_work(priv
->wq
, &priv
->update_stats_work
, 0);
2706 err_clear_state_opened_flag
:
2707 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2711 int mlx5e_open(struct net_device
*netdev
)
2713 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2716 mutex_lock(&priv
->state_lock
);
2717 err
= mlx5e_open_locked(netdev
);
2719 mlx5_set_port_admin_status(priv
->mdev
, MLX5_PORT_UP
);
2720 mutex_unlock(&priv
->state_lock
);
2725 int mlx5e_close_locked(struct net_device
*netdev
)
2727 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2729 /* May already be CLOSED in case a previous configuration operation
2730 * (e.g RX/TX queue size change) that involves close&open failed.
2732 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
2735 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2737 mlx5e_timestamp_cleanup(priv
);
2738 netif_carrier_off(priv
->netdev
);
2739 mlx5e_deactivate_priv_channels(priv
);
2740 mlx5e_close_channels(&priv
->channels
);
2745 int mlx5e_close(struct net_device
*netdev
)
2747 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2750 if (!netif_device_present(netdev
))
2753 mutex_lock(&priv
->state_lock
);
2754 mlx5_set_port_admin_status(priv
->mdev
, MLX5_PORT_DOWN
);
2755 err
= mlx5e_close_locked(netdev
);
2756 mutex_unlock(&priv
->state_lock
);
2761 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev
*mdev
,
2762 struct mlx5e_rq
*rq
,
2763 struct mlx5e_rq_param
*param
)
2765 void *rqc
= param
->rqc
;
2766 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
2769 param
->wq
.db_numa_node
= param
->wq
.buf_numa_node
;
2771 err
= mlx5_wq_ll_create(mdev
, ¶m
->wq
, rqc_wq
, &rq
->wq
,
2781 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev
*mdev
,
2782 struct mlx5e_cq
*cq
,
2783 struct mlx5e_cq_param
*param
)
2785 return mlx5e_alloc_cq_common(mdev
, param
, cq
);
2788 static int mlx5e_open_drop_rq(struct mlx5_core_dev
*mdev
,
2789 struct mlx5e_rq
*drop_rq
)
2791 struct mlx5e_cq_param cq_param
= {};
2792 struct mlx5e_rq_param rq_param
= {};
2793 struct mlx5e_cq
*cq
= &drop_rq
->cq
;
2796 mlx5e_build_drop_rq_param(&rq_param
);
2798 err
= mlx5e_alloc_drop_cq(mdev
, cq
, &cq_param
);
2802 err
= mlx5e_create_cq(cq
, &cq_param
);
2806 err
= mlx5e_alloc_drop_rq(mdev
, drop_rq
, &rq_param
);
2808 goto err_destroy_cq
;
2810 err
= mlx5e_create_rq(drop_rq
, &rq_param
);
2817 mlx5e_free_rq(drop_rq
);
2820 mlx5e_destroy_cq(cq
);
2828 static void mlx5e_close_drop_rq(struct mlx5e_rq
*drop_rq
)
2830 mlx5e_destroy_rq(drop_rq
);
2831 mlx5e_free_rq(drop_rq
);
2832 mlx5e_destroy_cq(&drop_rq
->cq
);
2833 mlx5e_free_cq(&drop_rq
->cq
);
2836 int mlx5e_create_tis(struct mlx5_core_dev
*mdev
, int tc
,
2837 u32 underlay_qpn
, u32
*tisn
)
2839 u32 in
[MLX5_ST_SZ_DW(create_tis_in
)] = {0};
2840 void *tisc
= MLX5_ADDR_OF(create_tis_in
, in
, ctx
);
2842 MLX5_SET(tisc
, tisc
, prio
, tc
<< 1);
2843 MLX5_SET(tisc
, tisc
, underlay_qpn
, underlay_qpn
);
2844 MLX5_SET(tisc
, tisc
, transport_domain
, mdev
->mlx5e_res
.td
.tdn
);
2846 if (mlx5_lag_is_lacp_owner(mdev
))
2847 MLX5_SET(tisc
, tisc
, strict_lag_tx_port_affinity
, 1);
2849 return mlx5_core_create_tis(mdev
, in
, sizeof(in
), tisn
);
2852 void mlx5e_destroy_tis(struct mlx5_core_dev
*mdev
, u32 tisn
)
2854 mlx5_core_destroy_tis(mdev
, tisn
);
2857 int mlx5e_create_tises(struct mlx5e_priv
*priv
)
2862 for (tc
= 0; tc
< priv
->profile
->max_tc
; tc
++) {
2863 err
= mlx5e_create_tis(priv
->mdev
, tc
, 0, &priv
->tisn
[tc
]);
2865 goto err_close_tises
;
2871 for (tc
--; tc
>= 0; tc
--)
2872 mlx5e_destroy_tis(priv
->mdev
, priv
->tisn
[tc
]);
2877 void mlx5e_cleanup_nic_tx(struct mlx5e_priv
*priv
)
2881 for (tc
= 0; tc
< priv
->profile
->max_tc
; tc
++)
2882 mlx5e_destroy_tis(priv
->mdev
, priv
->tisn
[tc
]);
2885 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv
*priv
,
2886 enum mlx5e_traffic_types tt
,
2889 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->mdev
->mlx5e_res
.td
.tdn
);
2891 mlx5e_build_tir_ctx_lro(&priv
->channels
.params
, tirc
);
2893 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
2894 MLX5_SET(tirc
, tirc
, indirect_table
, priv
->indir_rqt
.rqtn
);
2895 mlx5e_build_indir_tir_ctx_hash(&priv
->channels
.params
, tt
, tirc
, false);
2898 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv
*priv
, u32 rqtn
, u32
*tirc
)
2900 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->mdev
->mlx5e_res
.td
.tdn
);
2902 mlx5e_build_tir_ctx_lro(&priv
->channels
.params
, tirc
);
2904 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
2905 MLX5_SET(tirc
, tirc
, indirect_table
, rqtn
);
2906 MLX5_SET(tirc
, tirc
, rx_hash_fn
, MLX5_RX_HASH_FN_INVERTED_XOR8
);
2909 int mlx5e_create_indirect_tirs(struct mlx5e_priv
*priv
)
2911 struct mlx5e_tir
*tir
;
2919 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
2920 in
= kvzalloc(inlen
, GFP_KERNEL
);
2924 for (tt
= 0; tt
< MLX5E_NUM_INDIR_TIRS
; tt
++) {
2925 memset(in
, 0, inlen
);
2926 tir
= &priv
->indir_tir
[tt
];
2927 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
2928 mlx5e_build_indir_tir_ctx(priv
, tt
, tirc
);
2929 err
= mlx5e_create_tir(priv
->mdev
, tir
, in
, inlen
);
2931 mlx5_core_warn(priv
->mdev
, "create indirect tirs failed, %d\n", err
);
2932 goto err_destroy_inner_tirs
;
2936 if (!mlx5e_tunnel_inner_ft_supported(priv
->mdev
))
2939 for (i
= 0; i
< MLX5E_NUM_INDIR_TIRS
; i
++) {
2940 memset(in
, 0, inlen
);
2941 tir
= &priv
->inner_indir_tir
[i
];
2942 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
2943 mlx5e_build_inner_indir_tir_ctx(priv
, i
, tirc
);
2944 err
= mlx5e_create_tir(priv
->mdev
, tir
, in
, inlen
);
2946 mlx5_core_warn(priv
->mdev
, "create inner indirect tirs failed, %d\n", err
);
2947 goto err_destroy_inner_tirs
;
2956 err_destroy_inner_tirs
:
2957 for (i
--; i
>= 0; i
--)
2958 mlx5e_destroy_tir(priv
->mdev
, &priv
->inner_indir_tir
[i
]);
2960 for (tt
--; tt
>= 0; tt
--)
2961 mlx5e_destroy_tir(priv
->mdev
, &priv
->indir_tir
[tt
]);
2968 int mlx5e_create_direct_tirs(struct mlx5e_priv
*priv
)
2970 int nch
= priv
->profile
->max_nch(priv
->mdev
);
2971 struct mlx5e_tir
*tir
;
2978 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
2979 in
= kvzalloc(inlen
, GFP_KERNEL
);
2983 for (ix
= 0; ix
< nch
; ix
++) {
2984 memset(in
, 0, inlen
);
2985 tir
= &priv
->direct_tir
[ix
];
2986 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
2987 mlx5e_build_direct_tir_ctx(priv
, priv
->direct_tir
[ix
].rqt
.rqtn
, tirc
);
2988 err
= mlx5e_create_tir(priv
->mdev
, tir
, in
, inlen
);
2990 goto err_destroy_ch_tirs
;
2997 err_destroy_ch_tirs
:
2998 mlx5_core_warn(priv
->mdev
, "create direct tirs failed, %d\n", err
);
2999 for (ix
--; ix
>= 0; ix
--)
3000 mlx5e_destroy_tir(priv
->mdev
, &priv
->direct_tir
[ix
]);
3007 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv
*priv
)
3011 for (i
= 0; i
< MLX5E_NUM_INDIR_TIRS
; i
++)
3012 mlx5e_destroy_tir(priv
->mdev
, &priv
->indir_tir
[i
]);
3014 if (!mlx5e_tunnel_inner_ft_supported(priv
->mdev
))
3017 for (i
= 0; i
< MLX5E_NUM_INDIR_TIRS
; i
++)
3018 mlx5e_destroy_tir(priv
->mdev
, &priv
->inner_indir_tir
[i
]);
3021 void mlx5e_destroy_direct_tirs(struct mlx5e_priv
*priv
)
3023 int nch
= priv
->profile
->max_nch(priv
->mdev
);
3026 for (i
= 0; i
< nch
; i
++)
3027 mlx5e_destroy_tir(priv
->mdev
, &priv
->direct_tir
[i
]);
3030 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels
*chs
, bool enable
)
3035 for (i
= 0; i
< chs
->num
; i
++) {
3036 err
= mlx5e_modify_rq_scatter_fcs(&chs
->c
[i
]->rq
, enable
);
3044 static int mlx5e_modify_channels_vsd(struct mlx5e_channels
*chs
, bool vsd
)
3049 for (i
= 0; i
< chs
->num
; i
++) {
3050 err
= mlx5e_modify_rq_vsd(&chs
->c
[i
]->rq
, vsd
);
3058 static int mlx5e_setup_tc_mqprio(struct net_device
*netdev
,
3059 struct tc_mqprio_qopt
*mqprio
)
3061 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3062 struct mlx5e_channels new_channels
= {};
3063 u8 tc
= mqprio
->num_tc
;
3066 mqprio
->hw
= TC_MQPRIO_HW_OFFLOAD_TCS
;
3068 if (tc
&& tc
!= MLX5E_MAX_NUM_TC
)
3071 mutex_lock(&priv
->state_lock
);
3073 new_channels
.params
= priv
->channels
.params
;
3074 new_channels
.params
.num_tc
= tc
? tc
: 1;
3076 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
)) {
3077 priv
->channels
.params
= new_channels
.params
;
3081 err
= mlx5e_open_channels(priv
, &new_channels
);
3085 mlx5e_switch_priv_channels(priv
, &new_channels
, NULL
);
3087 mutex_unlock(&priv
->state_lock
);
3091 #ifdef CONFIG_MLX5_ESWITCH
3092 static int mlx5e_setup_tc_cls_flower(struct net_device
*dev
,
3093 struct tc_cls_flower_offload
*cls_flower
)
3095 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3097 if (!is_classid_clsact_ingress(cls_flower
->common
.classid
) ||
3098 cls_flower
->common
.chain_index
)
3101 switch (cls_flower
->command
) {
3102 case TC_CLSFLOWER_REPLACE
:
3103 return mlx5e_configure_flower(priv
, cls_flower
);
3104 case TC_CLSFLOWER_DESTROY
:
3105 return mlx5e_delete_flower(priv
, cls_flower
);
3106 case TC_CLSFLOWER_STATS
:
3107 return mlx5e_stats_flower(priv
, cls_flower
);
3114 static int mlx5e_setup_tc(struct net_device
*dev
, enum tc_setup_type type
,
3118 #ifdef CONFIG_MLX5_ESWITCH
3119 case TC_SETUP_CLSFLOWER
:
3120 return mlx5e_setup_tc_cls_flower(dev
, type_data
);
3122 case TC_SETUP_MQPRIO
:
3123 return mlx5e_setup_tc_mqprio(dev
, type_data
);
3130 mlx5e_get_stats(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
3132 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3133 struct mlx5e_sw_stats
*sstats
= &priv
->stats
.sw
;
3134 struct mlx5e_vport_stats
*vstats
= &priv
->stats
.vport
;
3135 struct mlx5e_pport_stats
*pstats
= &priv
->stats
.pport
;
3137 if (mlx5e_is_uplink_rep(priv
)) {
3138 stats
->rx_packets
= PPORT_802_3_GET(pstats
, a_frames_received_ok
);
3139 stats
->rx_bytes
= PPORT_802_3_GET(pstats
, a_octets_received_ok
);
3140 stats
->tx_packets
= PPORT_802_3_GET(pstats
, a_frames_transmitted_ok
);
3141 stats
->tx_bytes
= PPORT_802_3_GET(pstats
, a_octets_transmitted_ok
);
3143 stats
->rx_packets
= sstats
->rx_packets
;
3144 stats
->rx_bytes
= sstats
->rx_bytes
;
3145 stats
->tx_packets
= sstats
->tx_packets
;
3146 stats
->tx_bytes
= sstats
->tx_bytes
;
3147 stats
->tx_dropped
= sstats
->tx_queue_dropped
;
3150 stats
->rx_dropped
= priv
->stats
.qcnt
.rx_out_of_buffer
;
3152 stats
->rx_length_errors
=
3153 PPORT_802_3_GET(pstats
, a_in_range_length_errors
) +
3154 PPORT_802_3_GET(pstats
, a_out_of_range_length_field
) +
3155 PPORT_802_3_GET(pstats
, a_frame_too_long_errors
);
3156 stats
->rx_crc_errors
=
3157 PPORT_802_3_GET(pstats
, a_frame_check_sequence_errors
);
3158 stats
->rx_frame_errors
= PPORT_802_3_GET(pstats
, a_alignment_errors
);
3159 stats
->tx_aborted_errors
= PPORT_2863_GET(pstats
, if_out_discards
);
3160 stats
->rx_errors
= stats
->rx_length_errors
+ stats
->rx_crc_errors
+
3161 stats
->rx_frame_errors
;
3162 stats
->tx_errors
= stats
->tx_aborted_errors
+ stats
->tx_carrier_errors
;
3164 /* vport multicast also counts packets that are dropped due to steering
3165 * or rx out of buffer
3168 VPORT_COUNTER_GET(vstats
, received_eth_multicast
.packets
);
3171 static void mlx5e_set_rx_mode(struct net_device
*dev
)
3173 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3175 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
3178 static int mlx5e_set_mac(struct net_device
*netdev
, void *addr
)
3180 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3181 struct sockaddr
*saddr
= addr
;
3183 if (!is_valid_ether_addr(saddr
->sa_data
))
3184 return -EADDRNOTAVAIL
;
3186 netif_addr_lock_bh(netdev
);
3187 ether_addr_copy(netdev
->dev_addr
, saddr
->sa_data
);
3188 netif_addr_unlock_bh(netdev
);
3190 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
3195 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
3198 netdev->features |= feature; \
3200 netdev->features &= ~feature; \
3203 typedef int (*mlx5e_feature_handler
)(struct net_device
*netdev
, bool enable
);
3205 static int set_feature_lro(struct net_device
*netdev
, bool enable
)
3207 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3208 struct mlx5e_channels new_channels
= {};
3212 mutex_lock(&priv
->state_lock
);
3214 reset
= (priv
->channels
.params
.rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST
);
3215 reset
= reset
&& test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
3217 new_channels
.params
= priv
->channels
.params
;
3218 new_channels
.params
.lro_en
= enable
;
3221 priv
->channels
.params
= new_channels
.params
;
3222 err
= mlx5e_modify_tirs_lro(priv
);
3226 err
= mlx5e_open_channels(priv
, &new_channels
);
3230 mlx5e_switch_priv_channels(priv
, &new_channels
, mlx5e_modify_tirs_lro
);
3232 mutex_unlock(&priv
->state_lock
);
3236 static int set_feature_vlan_filter(struct net_device
*netdev
, bool enable
)
3238 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3241 mlx5e_enable_vlan_filter(priv
);
3243 mlx5e_disable_vlan_filter(priv
);
3248 static int set_feature_tc_num_filters(struct net_device
*netdev
, bool enable
)
3250 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3252 if (!enable
&& mlx5e_tc_num_filters(priv
)) {
3254 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3261 static int set_feature_rx_all(struct net_device
*netdev
, bool enable
)
3263 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3264 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3266 return mlx5_set_port_fcs(mdev
, !enable
);
3269 static int set_feature_rx_fcs(struct net_device
*netdev
, bool enable
)
3271 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3274 mutex_lock(&priv
->state_lock
);
3276 priv
->channels
.params
.scatter_fcs_en
= enable
;
3277 err
= mlx5e_modify_channels_scatter_fcs(&priv
->channels
, enable
);
3279 priv
->channels
.params
.scatter_fcs_en
= !enable
;
3281 mutex_unlock(&priv
->state_lock
);
3286 static int set_feature_rx_vlan(struct net_device
*netdev
, bool enable
)
3288 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3291 mutex_lock(&priv
->state_lock
);
3293 priv
->channels
.params
.vlan_strip_disable
= !enable
;
3294 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
3297 err
= mlx5e_modify_channels_vsd(&priv
->channels
, !enable
);
3299 priv
->channels
.params
.vlan_strip_disable
= enable
;
3302 mutex_unlock(&priv
->state_lock
);
3307 #ifdef CONFIG_RFS_ACCEL
3308 static int set_feature_arfs(struct net_device
*netdev
, bool enable
)
3310 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3314 err
= mlx5e_arfs_enable(priv
);
3316 err
= mlx5e_arfs_disable(priv
);
3322 static int mlx5e_handle_feature(struct net_device
*netdev
,
3323 netdev_features_t wanted_features
,
3324 netdev_features_t feature
,
3325 mlx5e_feature_handler feature_handler
)
3327 netdev_features_t changes
= wanted_features
^ netdev
->features
;
3328 bool enable
= !!(wanted_features
& feature
);
3331 if (!(changes
& feature
))
3334 err
= feature_handler(netdev
, enable
);
3336 netdev_err(netdev
, "%s feature 0x%llx failed err %d\n",
3337 enable
? "Enable" : "Disable", feature
, err
);
3341 MLX5E_SET_FEATURE(netdev
, feature
, enable
);
3345 static int mlx5e_set_features(struct net_device
*netdev
,
3346 netdev_features_t features
)
3350 err
= mlx5e_handle_feature(netdev
, features
, NETIF_F_LRO
,
3352 err
|= mlx5e_handle_feature(netdev
, features
,
3353 NETIF_F_HW_VLAN_CTAG_FILTER
,
3354 set_feature_vlan_filter
);
3355 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_HW_TC
,
3356 set_feature_tc_num_filters
);
3357 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_RXALL
,
3358 set_feature_rx_all
);
3359 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_RXFCS
,
3360 set_feature_rx_fcs
);
3361 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_HW_VLAN_CTAG_RX
,
3362 set_feature_rx_vlan
);
3363 #ifdef CONFIG_RFS_ACCEL
3364 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_NTUPLE
,
3368 return err
? -EINVAL
: 0;
3371 static int mlx5e_change_mtu(struct net_device
*netdev
, int new_mtu
)
3373 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3374 struct mlx5e_channels new_channels
= {};
3379 mutex_lock(&priv
->state_lock
);
3381 reset
= !priv
->channels
.params
.lro_en
&&
3382 (priv
->channels
.params
.rq_wq_type
!=
3383 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
);
3385 reset
= reset
&& test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
3387 curr_mtu
= netdev
->mtu
;
3388 netdev
->mtu
= new_mtu
;
3391 mlx5e_set_dev_port_mtu(priv
);
3395 new_channels
.params
= priv
->channels
.params
;
3396 err
= mlx5e_open_channels(priv
, &new_channels
);
3398 netdev
->mtu
= curr_mtu
;
3402 mlx5e_switch_priv_channels(priv
, &new_channels
, mlx5e_set_dev_port_mtu
);
3405 mutex_unlock(&priv
->state_lock
);
3409 static int mlx5e_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3411 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3415 return mlx5e_hwstamp_set(priv
, ifr
);
3417 return mlx5e_hwstamp_get(priv
, ifr
);
3423 #ifdef CONFIG_MLX5_ESWITCH
3424 static int mlx5e_set_vf_mac(struct net_device
*dev
, int vf
, u8
*mac
)
3426 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3427 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3429 return mlx5_eswitch_set_vport_mac(mdev
->priv
.eswitch
, vf
+ 1, mac
);
3432 static int mlx5e_set_vf_vlan(struct net_device
*dev
, int vf
, u16 vlan
, u8 qos
,
3435 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3436 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3438 if (vlan_proto
!= htons(ETH_P_8021Q
))
3439 return -EPROTONOSUPPORT
;
3441 return mlx5_eswitch_set_vport_vlan(mdev
->priv
.eswitch
, vf
+ 1,
3445 static int mlx5e_set_vf_spoofchk(struct net_device
*dev
, int vf
, bool setting
)
3447 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3448 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3450 return mlx5_eswitch_set_vport_spoofchk(mdev
->priv
.eswitch
, vf
+ 1, setting
);
3453 static int mlx5e_set_vf_trust(struct net_device
*dev
, int vf
, bool setting
)
3455 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3456 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3458 return mlx5_eswitch_set_vport_trust(mdev
->priv
.eswitch
, vf
+ 1, setting
);
3461 static int mlx5e_set_vf_rate(struct net_device
*dev
, int vf
, int min_tx_rate
,
3464 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3465 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3467 return mlx5_eswitch_set_vport_rate(mdev
->priv
.eswitch
, vf
+ 1,
3468 max_tx_rate
, min_tx_rate
);
3471 static int mlx5_vport_link2ifla(u8 esw_link
)
3474 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN
:
3475 return IFLA_VF_LINK_STATE_DISABLE
;
3476 case MLX5_ESW_VPORT_ADMIN_STATE_UP
:
3477 return IFLA_VF_LINK_STATE_ENABLE
;
3479 return IFLA_VF_LINK_STATE_AUTO
;
3482 static int mlx5_ifla_link2vport(u8 ifla_link
)
3484 switch (ifla_link
) {
3485 case IFLA_VF_LINK_STATE_DISABLE
:
3486 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN
;
3487 case IFLA_VF_LINK_STATE_ENABLE
:
3488 return MLX5_ESW_VPORT_ADMIN_STATE_UP
;
3490 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO
;
3493 static int mlx5e_set_vf_link_state(struct net_device
*dev
, int vf
,
3496 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3497 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3499 return mlx5_eswitch_set_vport_state(mdev
->priv
.eswitch
, vf
+ 1,
3500 mlx5_ifla_link2vport(link_state
));
3503 static int mlx5e_get_vf_config(struct net_device
*dev
,
3504 int vf
, struct ifla_vf_info
*ivi
)
3506 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3507 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3510 err
= mlx5_eswitch_get_vport_config(mdev
->priv
.eswitch
, vf
+ 1, ivi
);
3513 ivi
->linkstate
= mlx5_vport_link2ifla(ivi
->linkstate
);
3517 static int mlx5e_get_vf_stats(struct net_device
*dev
,
3518 int vf
, struct ifla_vf_stats
*vf_stats
)
3520 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3521 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3523 return mlx5_eswitch_get_vport_stats(mdev
->priv
.eswitch
, vf
+ 1,
3528 static void mlx5e_add_vxlan_port(struct net_device
*netdev
,
3529 struct udp_tunnel_info
*ti
)
3531 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3533 if (ti
->type
!= UDP_TUNNEL_TYPE_VXLAN
)
3536 if (!mlx5e_vxlan_allowed(priv
->mdev
))
3539 mlx5e_vxlan_queue_work(priv
, ti
->sa_family
, be16_to_cpu(ti
->port
), 1);
3542 static void mlx5e_del_vxlan_port(struct net_device
*netdev
,
3543 struct udp_tunnel_info
*ti
)
3545 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3547 if (ti
->type
!= UDP_TUNNEL_TYPE_VXLAN
)
3550 if (!mlx5e_vxlan_allowed(priv
->mdev
))
3553 mlx5e_vxlan_queue_work(priv
, ti
->sa_family
, be16_to_cpu(ti
->port
), 0);
3556 static netdev_features_t
mlx5e_tunnel_features_check(struct mlx5e_priv
*priv
,
3557 struct sk_buff
*skb
,
3558 netdev_features_t features
)
3560 struct udphdr
*udph
;
3564 switch (vlan_get_protocol(skb
)) {
3565 case htons(ETH_P_IP
):
3566 proto
= ip_hdr(skb
)->protocol
;
3568 case htons(ETH_P_IPV6
):
3569 proto
= ipv6_hdr(skb
)->nexthdr
;
3579 udph
= udp_hdr(skb
);
3580 port
= be16_to_cpu(udph
->dest
);
3582 /* Verify if UDP port is being offloaded by HW */
3583 if (mlx5e_vxlan_lookup_port(priv
, port
))
3588 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3589 return features
& ~(NETIF_F_CSUM_MASK
| NETIF_F_GSO_MASK
);
3592 static netdev_features_t
mlx5e_features_check(struct sk_buff
*skb
,
3593 struct net_device
*netdev
,
3594 netdev_features_t features
)
3596 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3598 features
= vlan_features_check(skb
, features
);
3599 features
= vxlan_features_check(skb
, features
);
3601 #ifdef CONFIG_MLX5_EN_IPSEC
3602 if (mlx5e_ipsec_feature_check(skb
, netdev
, features
))
3606 /* Validate if the tunneled packet is being offloaded by HW */
3607 if (skb
->encapsulation
&&
3608 (features
& NETIF_F_CSUM_MASK
|| features
& NETIF_F_GSO_MASK
))
3609 return mlx5e_tunnel_features_check(priv
, skb
, features
);
3614 static void mlx5e_tx_timeout(struct net_device
*dev
)
3616 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3617 bool sched_work
= false;
3620 netdev_err(dev
, "TX timeout detected\n");
3622 for (i
= 0; i
< priv
->channels
.num
* priv
->channels
.params
.num_tc
; i
++) {
3623 struct mlx5e_txqsq
*sq
= priv
->txq2sq
[i
];
3625 if (!netif_xmit_stopped(netdev_get_tx_queue(dev
, i
)))
3628 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
3629 netdev_err(dev
, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3630 i
, sq
->sqn
, sq
->cq
.mcq
.cqn
, sq
->cc
, sq
->pc
);
3633 if (sched_work
&& test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
3634 schedule_work(&priv
->tx_timeout_work
);
3637 static int mlx5e_xdp_set(struct net_device
*netdev
, struct bpf_prog
*prog
)
3639 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3640 struct bpf_prog
*old_prog
;
3642 bool reset
, was_opened
;
3645 mutex_lock(&priv
->state_lock
);
3647 if ((netdev
->features
& NETIF_F_LRO
) && prog
) {
3648 netdev_warn(netdev
, "can't set XDP while LRO is on, disable LRO first\n");
3653 if ((netdev
->features
& NETIF_F_HW_ESP
) && prog
) {
3654 netdev_warn(netdev
, "can't set XDP with IPSec offload\n");
3659 was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
3660 /* no need for full reset when exchanging programs */
3661 reset
= (!priv
->channels
.params
.xdp_prog
|| !prog
);
3663 if (was_opened
&& reset
)
3664 mlx5e_close_locked(netdev
);
3665 if (was_opened
&& !reset
) {
3666 /* num_channels is invariant here, so we can take the
3667 * batched reference right upfront.
3669 prog
= bpf_prog_add(prog
, priv
->channels
.num
);
3671 err
= PTR_ERR(prog
);
3676 /* exchange programs, extra prog reference we got from caller
3677 * as long as we don't fail from this point onwards.
3679 old_prog
= xchg(&priv
->channels
.params
.xdp_prog
, prog
);
3681 bpf_prog_put(old_prog
);
3683 if (reset
) /* change RQ type according to priv->xdp_prog */
3684 mlx5e_set_rq_params(priv
->mdev
, &priv
->channels
.params
);
3686 if (was_opened
&& reset
)
3687 mlx5e_open_locked(netdev
);
3689 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
) || reset
)
3692 /* exchanging programs w/o reset, we update ref counts on behalf
3693 * of the channels RQs here.
3695 for (i
= 0; i
< priv
->channels
.num
; i
++) {
3696 struct mlx5e_channel
*c
= priv
->channels
.c
[i
];
3698 clear_bit(MLX5E_RQ_STATE_ENABLED
, &c
->rq
.state
);
3699 napi_synchronize(&c
->napi
);
3700 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3702 old_prog
= xchg(&c
->rq
.xdp_prog
, prog
);
3704 set_bit(MLX5E_RQ_STATE_ENABLED
, &c
->rq
.state
);
3705 /* napi_schedule in case we have missed anything */
3706 napi_schedule(&c
->napi
);
3709 bpf_prog_put(old_prog
);
3713 mutex_unlock(&priv
->state_lock
);
3717 static u32
mlx5e_xdp_query(struct net_device
*dev
)
3719 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3720 const struct bpf_prog
*xdp_prog
;
3723 mutex_lock(&priv
->state_lock
);
3724 xdp_prog
= priv
->channels
.params
.xdp_prog
;
3726 prog_id
= xdp_prog
->aux
->id
;
3727 mutex_unlock(&priv
->state_lock
);
3732 static int mlx5e_xdp(struct net_device
*dev
, struct netdev_xdp
*xdp
)
3734 switch (xdp
->command
) {
3735 case XDP_SETUP_PROG
:
3736 return mlx5e_xdp_set(dev
, xdp
->prog
);
3737 case XDP_QUERY_PROG
:
3738 xdp
->prog_id
= mlx5e_xdp_query(dev
);
3739 xdp
->prog_attached
= !!xdp
->prog_id
;
3746 #ifdef CONFIG_NET_POLL_CONTROLLER
3747 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3748 * reenabling interrupts.
3750 static void mlx5e_netpoll(struct net_device
*dev
)
3752 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3753 struct mlx5e_channels
*chs
= &priv
->channels
;
3757 for (i
= 0; i
< chs
->num
; i
++)
3758 napi_schedule(&chs
->c
[i
]->napi
);
3762 static const struct net_device_ops mlx5e_netdev_ops
= {
3763 .ndo_open
= mlx5e_open
,
3764 .ndo_stop
= mlx5e_close
,
3765 .ndo_start_xmit
= mlx5e_xmit
,
3766 .ndo_setup_tc
= mlx5e_setup_tc
,
3767 .ndo_select_queue
= mlx5e_select_queue
,
3768 .ndo_get_stats64
= mlx5e_get_stats
,
3769 .ndo_set_rx_mode
= mlx5e_set_rx_mode
,
3770 .ndo_set_mac_address
= mlx5e_set_mac
,
3771 .ndo_vlan_rx_add_vid
= mlx5e_vlan_rx_add_vid
,
3772 .ndo_vlan_rx_kill_vid
= mlx5e_vlan_rx_kill_vid
,
3773 .ndo_set_features
= mlx5e_set_features
,
3774 .ndo_change_mtu
= mlx5e_change_mtu
,
3775 .ndo_do_ioctl
= mlx5e_ioctl
,
3776 .ndo_set_tx_maxrate
= mlx5e_set_tx_maxrate
,
3777 .ndo_udp_tunnel_add
= mlx5e_add_vxlan_port
,
3778 .ndo_udp_tunnel_del
= mlx5e_del_vxlan_port
,
3779 .ndo_features_check
= mlx5e_features_check
,
3780 #ifdef CONFIG_RFS_ACCEL
3781 .ndo_rx_flow_steer
= mlx5e_rx_flow_steer
,
3783 .ndo_tx_timeout
= mlx5e_tx_timeout
,
3784 .ndo_xdp
= mlx5e_xdp
,
3785 #ifdef CONFIG_NET_POLL_CONTROLLER
3786 .ndo_poll_controller
= mlx5e_netpoll
,
3788 #ifdef CONFIG_MLX5_ESWITCH
3789 /* SRIOV E-Switch NDOs */
3790 .ndo_set_vf_mac
= mlx5e_set_vf_mac
,
3791 .ndo_set_vf_vlan
= mlx5e_set_vf_vlan
,
3792 .ndo_set_vf_spoofchk
= mlx5e_set_vf_spoofchk
,
3793 .ndo_set_vf_trust
= mlx5e_set_vf_trust
,
3794 .ndo_set_vf_rate
= mlx5e_set_vf_rate
,
3795 .ndo_get_vf_config
= mlx5e_get_vf_config
,
3796 .ndo_set_vf_link_state
= mlx5e_set_vf_link_state
,
3797 .ndo_get_vf_stats
= mlx5e_get_vf_stats
,
3798 .ndo_has_offload_stats
= mlx5e_has_offload_stats
,
3799 .ndo_get_offload_stats
= mlx5e_get_offload_stats
,
3803 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev
*mdev
)
3805 if (MLX5_CAP_GEN(mdev
, port_type
) != MLX5_CAP_PORT_TYPE_ETH
)
3807 if (!MLX5_CAP_GEN(mdev
, eth_net_offloads
) ||
3808 !MLX5_CAP_GEN(mdev
, nic_flow_table
) ||
3809 !MLX5_CAP_ETH(mdev
, csum_cap
) ||
3810 !MLX5_CAP_ETH(mdev
, max_lso_cap
) ||
3811 !MLX5_CAP_ETH(mdev
, vlan_cap
) ||
3812 !MLX5_CAP_ETH(mdev
, rss_ind_tbl_cap
) ||
3813 MLX5_CAP_FLOWTABLE(mdev
,
3814 flow_table_properties_nic_receive
.max_ft_level
)
3816 mlx5_core_warn(mdev
,
3817 "Not creating net device, some required device capabilities are missing\n");
3820 if (!MLX5_CAP_ETH(mdev
, self_lb_en_modifiable
))
3821 mlx5_core_warn(mdev
, "Self loop back prevention is not supported\n");
3822 if (!MLX5_CAP_GEN(mdev
, cq_moderation
))
3823 mlx5_core_warn(mdev
, "CQ moderation is not supported\n");
3828 u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev
*mdev
)
3830 int bf_buf_size
= (1 << MLX5_CAP_GEN(mdev
, log_bf_reg_size
)) / 2;
3832 return bf_buf_size
-
3833 sizeof(struct mlx5e_tx_wqe
) +
3834 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3837 void mlx5e_build_default_indir_rqt(u32
*indirection_rqt
, int len
,
3842 for (i
= 0; i
< len
; i
++)
3843 indirection_rqt
[i
] = i
% num_channels
;
3846 static int mlx5e_get_pci_bw(struct mlx5_core_dev
*mdev
, u32
*pci_bw
)
3848 enum pcie_link_width width
;
3849 enum pci_bus_speed speed
;
3852 err
= pcie_get_minimum_link(mdev
->pdev
, &speed
, &width
);
3856 if (speed
== PCI_SPEED_UNKNOWN
|| width
== PCIE_LNK_WIDTH_UNKNOWN
)
3860 case PCIE_SPEED_2_5GT
:
3861 *pci_bw
= 2500 * width
;
3863 case PCIE_SPEED_5_0GT
:
3864 *pci_bw
= 5000 * width
;
3866 case PCIE_SPEED_8_0GT
:
3867 *pci_bw
= 8000 * width
;
3876 static bool cqe_compress_heuristic(u32 link_speed
, u32 pci_bw
)
3878 return (link_speed
&& pci_bw
&&
3879 (pci_bw
< 40000) && (pci_bw
< link_speed
));
3882 static bool hw_lro_heuristic(u32 link_speed
, u32 pci_bw
)
3884 return !(link_speed
&& pci_bw
&&
3885 (pci_bw
<= 16000) && (pci_bw
< link_speed
));
3888 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params
*params
, u8 cq_period_mode
)
3890 params
->rx_cq_period_mode
= cq_period_mode
;
3892 params
->rx_cq_moderation
.pkts
=
3893 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS
;
3894 params
->rx_cq_moderation
.usec
=
3895 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC
;
3897 if (cq_period_mode
== MLX5_CQ_PERIOD_MODE_START_FROM_CQE
)
3898 params
->rx_cq_moderation
.usec
=
3899 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE
;
3901 if (params
->rx_am_enabled
)
3902 params
->rx_cq_moderation
=
3903 mlx5e_am_get_def_profile(params
->rx_cq_period_mode
);
3905 MLX5E_SET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_BASED_MODER
,
3906 params
->rx_cq_period_mode
== MLX5_CQ_PERIOD_MODE_START_FROM_CQE
);
3909 u32
mlx5e_choose_lro_timeout(struct mlx5_core_dev
*mdev
, u32 wanted_timeout
)
3913 /* The supported periods are organized in ascending order */
3914 for (i
= 0; i
< MLX5E_LRO_TIMEOUT_ARR_SIZE
- 1; i
++)
3915 if (MLX5_CAP_ETH(mdev
, lro_timer_supported_periods
[i
]) >= wanted_timeout
)
3918 return MLX5_CAP_ETH(mdev
, lro_timer_supported_periods
[i
]);
3921 void mlx5e_build_nic_params(struct mlx5_core_dev
*mdev
,
3922 struct mlx5e_params
*params
,
3925 u8 cq_period_mode
= 0;
3929 params
->num_channels
= max_channels
;
3932 mlx5e_get_max_linkspeed(mdev
, &link_speed
);
3933 mlx5e_get_pci_bw(mdev
, &pci_bw
);
3934 mlx5_core_dbg(mdev
, "Max link speed = %d, PCI BW = %d\n",
3935 link_speed
, pci_bw
);
3938 params
->log_sq_size
= is_kdump_kernel() ?
3939 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE
:
3940 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE
;
3942 /* set CQE compression */
3943 params
->rx_cqe_compress_def
= false;
3944 if (MLX5_CAP_GEN(mdev
, cqe_compression
) &&
3945 MLX5_CAP_GEN(mdev
, vport_group_manager
))
3946 params
->rx_cqe_compress_def
= cqe_compress_heuristic(link_speed
, pci_bw
);
3948 MLX5E_SET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_COMPRESS
, params
->rx_cqe_compress_def
);
3951 mlx5e_set_rq_params(mdev
, params
);
3955 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
3956 if (params
->rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
)
3957 params
->lro_en
= hw_lro_heuristic(link_speed
, pci_bw
);
3958 params
->lro_timeout
= mlx5e_choose_lro_timeout(mdev
, MLX5E_DEFAULT_LRO_TIMEOUT
);
3960 /* CQ moderation params */
3961 cq_period_mode
= MLX5_CAP_GEN(mdev
, cq_period_start_from_cqe
) ?
3962 MLX5_CQ_PERIOD_MODE_START_FROM_CQE
:
3963 MLX5_CQ_PERIOD_MODE_START_FROM_EQE
;
3964 params
->rx_am_enabled
= MLX5_CAP_GEN(mdev
, cq_moderation
);
3965 mlx5e_set_rx_cq_mode_params(params
, cq_period_mode
);
3967 params
->tx_cq_moderation
.usec
= MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC
;
3968 params
->tx_cq_moderation
.pkts
= MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS
;
3971 params
->tx_max_inline
= mlx5e_get_max_inline_cap(mdev
);
3972 mlx5_query_min_inline(mdev
, ¶ms
->tx_min_inline_mode
);
3973 if (params
->tx_min_inline_mode
== MLX5_INLINE_MODE_NONE
&&
3974 !MLX5_CAP_ETH(mdev
, wqe_vlan_insert
))
3975 params
->tx_min_inline_mode
= MLX5_INLINE_MODE_L2
;
3978 params
->rss_hfunc
= ETH_RSS_HASH_XOR
;
3979 netdev_rss_key_fill(params
->toeplitz_hash_key
, sizeof(params
->toeplitz_hash_key
));
3980 mlx5e_build_default_indir_rqt(params
->indirection_rqt
,
3981 MLX5E_INDIR_RQT_SIZE
, max_channels
);
3984 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev
*mdev
,
3985 struct net_device
*netdev
,
3986 const struct mlx5e_profile
*profile
,
3989 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3992 priv
->netdev
= netdev
;
3993 priv
->profile
= profile
;
3994 priv
->ppriv
= ppriv
;
3995 priv
->hard_mtu
= MLX5E_ETH_HARD_MTU
;
3997 mlx5e_build_nic_params(mdev
, &priv
->channels
.params
, profile
->max_nch(mdev
));
3999 mutex_init(&priv
->state_lock
);
4001 INIT_WORK(&priv
->update_carrier_work
, mlx5e_update_carrier_work
);
4002 INIT_WORK(&priv
->set_rx_mode_work
, mlx5e_set_rx_mode_work
);
4003 INIT_WORK(&priv
->tx_timeout_work
, mlx5e_tx_timeout_work
);
4004 INIT_DELAYED_WORK(&priv
->update_stats_work
, mlx5e_update_stats_work
);
4007 static void mlx5e_set_netdev_dev_addr(struct net_device
*netdev
)
4009 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
4011 mlx5_query_nic_vport_mac_address(priv
->mdev
, 0, netdev
->dev_addr
);
4012 if (is_zero_ether_addr(netdev
->dev_addr
) &&
4013 !MLX5_CAP_GEN(priv
->mdev
, vport_group_manager
)) {
4014 eth_hw_addr_random(netdev
);
4015 mlx5_core_info(priv
->mdev
, "Assigned random MAC address %pM\n", netdev
->dev_addr
);
4019 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4020 static const struct switchdev_ops mlx5e_switchdev_ops
= {
4021 .switchdev_port_attr_get
= mlx5e_attr_get
,
4025 static void mlx5e_build_nic_netdev(struct net_device
*netdev
)
4027 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
4028 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4032 SET_NETDEV_DEV(netdev
, &mdev
->pdev
->dev
);
4034 netdev
->netdev_ops
= &mlx5e_netdev_ops
;
4036 #ifdef CONFIG_MLX5_CORE_EN_DCB
4037 if (MLX5_CAP_GEN(mdev
, vport_group_manager
) && MLX5_CAP_GEN(mdev
, qos
))
4038 netdev
->dcbnl_ops
= &mlx5e_dcbnl_ops
;
4041 netdev
->watchdog_timeo
= 15 * HZ
;
4043 netdev
->ethtool_ops
= &mlx5e_ethtool_ops
;
4045 netdev
->vlan_features
|= NETIF_F_SG
;
4046 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
4047 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
4048 netdev
->vlan_features
|= NETIF_F_GRO
;
4049 netdev
->vlan_features
|= NETIF_F_TSO
;
4050 netdev
->vlan_features
|= NETIF_F_TSO6
;
4051 netdev
->vlan_features
|= NETIF_F_RXCSUM
;
4052 netdev
->vlan_features
|= NETIF_F_RXHASH
;
4054 if (!!MLX5_CAP_ETH(mdev
, lro_cap
))
4055 netdev
->vlan_features
|= NETIF_F_LRO
;
4057 netdev
->hw_features
= netdev
->vlan_features
;
4058 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_TX
;
4059 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
;
4060 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
4062 if (mlx5e_vxlan_allowed(mdev
) || MLX5_CAP_ETH(mdev
, tunnel_stateless_gre
)) {
4063 netdev
->hw_features
|= NETIF_F_GSO_PARTIAL
;
4064 netdev
->hw_enc_features
|= NETIF_F_IP_CSUM
;
4065 netdev
->hw_enc_features
|= NETIF_F_IPV6_CSUM
;
4066 netdev
->hw_enc_features
|= NETIF_F_TSO
;
4067 netdev
->hw_enc_features
|= NETIF_F_TSO6
;
4068 netdev
->hw_enc_features
|= NETIF_F_GSO_PARTIAL
;
4071 if (mlx5e_vxlan_allowed(mdev
)) {
4072 netdev
->hw_features
|= NETIF_F_GSO_UDP_TUNNEL
|
4073 NETIF_F_GSO_UDP_TUNNEL_CSUM
;
4074 netdev
->hw_enc_features
|= NETIF_F_GSO_UDP_TUNNEL
|
4075 NETIF_F_GSO_UDP_TUNNEL_CSUM
;
4076 netdev
->gso_partial_features
= NETIF_F_GSO_UDP_TUNNEL_CSUM
;
4079 if (MLX5_CAP_ETH(mdev
, tunnel_stateless_gre
)) {
4080 netdev
->hw_features
|= NETIF_F_GSO_GRE
|
4081 NETIF_F_GSO_GRE_CSUM
;
4082 netdev
->hw_enc_features
|= NETIF_F_GSO_GRE
|
4083 NETIF_F_GSO_GRE_CSUM
;
4084 netdev
->gso_partial_features
|= NETIF_F_GSO_GRE
|
4085 NETIF_F_GSO_GRE_CSUM
;
4088 mlx5_query_port_fcs(mdev
, &fcs_supported
, &fcs_enabled
);
4091 netdev
->hw_features
|= NETIF_F_RXALL
;
4093 if (MLX5_CAP_ETH(mdev
, scatter_fcs
))
4094 netdev
->hw_features
|= NETIF_F_RXFCS
;
4096 netdev
->features
= netdev
->hw_features
;
4097 if (!priv
->channels
.params
.lro_en
)
4098 netdev
->features
&= ~NETIF_F_LRO
;
4101 netdev
->features
&= ~NETIF_F_RXALL
;
4103 if (!priv
->channels
.params
.scatter_fcs_en
)
4104 netdev
->features
&= ~NETIF_F_RXFCS
;
4106 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4107 if (FT_CAP(flow_modify_en
) &&
4108 FT_CAP(modify_root
) &&
4109 FT_CAP(identified_miss_table_mode
) &&
4110 FT_CAP(flow_table_modify
)) {
4111 netdev
->hw_features
|= NETIF_F_HW_TC
;
4112 #ifdef CONFIG_RFS_ACCEL
4113 netdev
->hw_features
|= NETIF_F_NTUPLE
;
4117 netdev
->features
|= NETIF_F_HIGHDMA
;
4119 netdev
->priv_flags
|= IFF_UNICAST_FLT
;
4121 mlx5e_set_netdev_dev_addr(netdev
);
4123 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4124 if (MLX5_VPORT_MANAGER(mdev
))
4125 netdev
->switchdev_ops
= &mlx5e_switchdev_ops
;
4128 mlx5e_ipsec_build_netdev(priv
);
4131 static void mlx5e_create_q_counter(struct mlx5e_priv
*priv
)
4133 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4136 err
= mlx5_core_alloc_q_counter(mdev
, &priv
->q_counter
);
4138 mlx5_core_warn(mdev
, "alloc queue counter failed, %d\n", err
);
4139 priv
->q_counter
= 0;
4143 static void mlx5e_destroy_q_counter(struct mlx5e_priv
*priv
)
4145 if (!priv
->q_counter
)
4148 mlx5_core_dealloc_q_counter(priv
->mdev
, priv
->q_counter
);
4151 static void mlx5e_nic_init(struct mlx5_core_dev
*mdev
,
4152 struct net_device
*netdev
,
4153 const struct mlx5e_profile
*profile
,
4156 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
4159 mlx5e_build_nic_netdev_priv(mdev
, netdev
, profile
, ppriv
);
4160 err
= mlx5e_ipsec_init(priv
);
4162 mlx5_core_err(mdev
, "IPSec initialization failed, %d\n", err
);
4163 mlx5e_build_nic_netdev(netdev
);
4164 mlx5e_vxlan_init(priv
);
4167 static void mlx5e_nic_cleanup(struct mlx5e_priv
*priv
)
4169 mlx5e_ipsec_cleanup(priv
);
4170 mlx5e_vxlan_cleanup(priv
);
4172 if (priv
->channels
.params
.xdp_prog
)
4173 bpf_prog_put(priv
->channels
.params
.xdp_prog
);
4176 static int mlx5e_init_nic_rx(struct mlx5e_priv
*priv
)
4178 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4181 err
= mlx5e_create_indirect_rqt(priv
);
4185 err
= mlx5e_create_direct_rqts(priv
);
4187 goto err_destroy_indirect_rqts
;
4189 err
= mlx5e_create_indirect_tirs(priv
);
4191 goto err_destroy_direct_rqts
;
4193 err
= mlx5e_create_direct_tirs(priv
);
4195 goto err_destroy_indirect_tirs
;
4197 err
= mlx5e_create_flow_steering(priv
);
4199 mlx5_core_warn(mdev
, "create flow steering failed, %d\n", err
);
4200 goto err_destroy_direct_tirs
;
4203 err
= mlx5e_tc_init(priv
);
4205 goto err_destroy_flow_steering
;
4209 err_destroy_flow_steering
:
4210 mlx5e_destroy_flow_steering(priv
);
4211 err_destroy_direct_tirs
:
4212 mlx5e_destroy_direct_tirs(priv
);
4213 err_destroy_indirect_tirs
:
4214 mlx5e_destroy_indirect_tirs(priv
);
4215 err_destroy_direct_rqts
:
4216 mlx5e_destroy_direct_rqts(priv
);
4217 err_destroy_indirect_rqts
:
4218 mlx5e_destroy_rqt(priv
, &priv
->indir_rqt
);
4222 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv
*priv
)
4224 mlx5e_tc_cleanup(priv
);
4225 mlx5e_destroy_flow_steering(priv
);
4226 mlx5e_destroy_direct_tirs(priv
);
4227 mlx5e_destroy_indirect_tirs(priv
);
4228 mlx5e_destroy_direct_rqts(priv
);
4229 mlx5e_destroy_rqt(priv
, &priv
->indir_rqt
);
4232 static int mlx5e_init_nic_tx(struct mlx5e_priv
*priv
)
4236 err
= mlx5e_create_tises(priv
);
4238 mlx5_core_warn(priv
->mdev
, "create tises failed, %d\n", err
);
4242 #ifdef CONFIG_MLX5_CORE_EN_DCB
4243 mlx5e_dcbnl_initialize(priv
);
4248 static void mlx5e_nic_enable(struct mlx5e_priv
*priv
)
4250 struct net_device
*netdev
= priv
->netdev
;
4251 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4254 mlx5e_init_l2_addr(priv
);
4256 /* Marking the link as currently not needed by the Driver */
4257 if (!netif_running(netdev
))
4258 mlx5_set_port_admin_status(mdev
, MLX5_PORT_DOWN
);
4260 /* MTU range: 68 - hw-specific max */
4261 netdev
->min_mtu
= ETH_MIN_MTU
;
4262 mlx5_query_port_max_mtu(priv
->mdev
, &max_mtu
, 1);
4263 netdev
->max_mtu
= MLX5E_HW2SW_MTU(priv
, max_mtu
);
4264 mlx5e_set_dev_port_mtu(priv
);
4266 mlx5_lag_add(mdev
, netdev
);
4268 mlx5e_enable_async_events(priv
);
4270 if (MLX5_VPORT_MANAGER(priv
->mdev
))
4271 mlx5e_register_vport_reps(priv
);
4273 if (netdev
->reg_state
!= NETREG_REGISTERED
)
4276 /* Device already registered: sync netdev system state */
4277 if (mlx5e_vxlan_allowed(mdev
)) {
4279 udp_tunnel_get_rx_info(netdev
);
4283 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
4286 if (netif_running(netdev
))
4288 netif_device_attach(netdev
);
4292 static void mlx5e_nic_disable(struct mlx5e_priv
*priv
)
4294 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4297 if (netif_running(priv
->netdev
))
4298 mlx5e_close(priv
->netdev
);
4299 netif_device_detach(priv
->netdev
);
4302 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
4304 if (MLX5_VPORT_MANAGER(priv
->mdev
))
4305 mlx5e_unregister_vport_reps(priv
);
4307 mlx5e_disable_async_events(priv
);
4308 mlx5_lag_remove(mdev
);
4311 static const struct mlx5e_profile mlx5e_nic_profile
= {
4312 .init
= mlx5e_nic_init
,
4313 .cleanup
= mlx5e_nic_cleanup
,
4314 .init_rx
= mlx5e_init_nic_rx
,
4315 .cleanup_rx
= mlx5e_cleanup_nic_rx
,
4316 .init_tx
= mlx5e_init_nic_tx
,
4317 .cleanup_tx
= mlx5e_cleanup_nic_tx
,
4318 .enable
= mlx5e_nic_enable
,
4319 .disable
= mlx5e_nic_disable
,
4320 .update_stats
= mlx5e_update_ndo_stats
,
4321 .max_nch
= mlx5e_get_max_num_channels
,
4322 .update_carrier
= mlx5e_update_carrier
,
4323 .rx_handlers
.handle_rx_cqe
= mlx5e_handle_rx_cqe
,
4324 .rx_handlers
.handle_rx_cqe_mpwqe
= mlx5e_handle_rx_cqe_mpwrq
,
4325 .max_tc
= MLX5E_MAX_NUM_TC
,
4328 /* mlx5e generic netdev management API (move to en_common.c) */
4330 struct net_device
*mlx5e_create_netdev(struct mlx5_core_dev
*mdev
,
4331 const struct mlx5e_profile
*profile
,
4334 int nch
= profile
->max_nch(mdev
);
4335 struct net_device
*netdev
;
4336 struct mlx5e_priv
*priv
;
4338 netdev
= alloc_etherdev_mqs(sizeof(struct mlx5e_priv
),
4339 nch
* profile
->max_tc
,
4342 mlx5_core_err(mdev
, "alloc_etherdev_mqs() failed\n");
4346 #ifdef CONFIG_RFS_ACCEL
4347 netdev
->rx_cpu_rmap
= mdev
->rmap
;
4350 profile
->init(mdev
, netdev
, profile
, ppriv
);
4352 netif_carrier_off(netdev
);
4354 priv
= netdev_priv(netdev
);
4356 priv
->wq
= create_singlethread_workqueue("mlx5e");
4358 goto err_cleanup_nic
;
4363 if (profile
->cleanup
)
4364 profile
->cleanup(priv
);
4365 free_netdev(netdev
);
4370 int mlx5e_attach_netdev(struct mlx5e_priv
*priv
)
4372 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4373 const struct mlx5e_profile
*profile
;
4376 profile
= priv
->profile
;
4377 clear_bit(MLX5E_STATE_DESTROYING
, &priv
->state
);
4379 err
= profile
->init_tx(priv
);
4383 err
= mlx5e_open_drop_rq(mdev
, &priv
->drop_rq
);
4385 mlx5_core_err(mdev
, "open drop rq failed, %d\n", err
);
4386 goto err_cleanup_tx
;
4389 err
= profile
->init_rx(priv
);
4391 goto err_close_drop_rq
;
4393 mlx5e_create_q_counter(priv
);
4395 if (profile
->enable
)
4396 profile
->enable(priv
);
4401 mlx5e_close_drop_rq(&priv
->drop_rq
);
4404 profile
->cleanup_tx(priv
);
4410 void mlx5e_detach_netdev(struct mlx5e_priv
*priv
)
4412 const struct mlx5e_profile
*profile
= priv
->profile
;
4414 set_bit(MLX5E_STATE_DESTROYING
, &priv
->state
);
4416 if (profile
->disable
)
4417 profile
->disable(priv
);
4418 flush_workqueue(priv
->wq
);
4420 mlx5e_destroy_q_counter(priv
);
4421 profile
->cleanup_rx(priv
);
4422 mlx5e_close_drop_rq(&priv
->drop_rq
);
4423 profile
->cleanup_tx(priv
);
4424 cancel_delayed_work_sync(&priv
->update_stats_work
);
4427 void mlx5e_destroy_netdev(struct mlx5e_priv
*priv
)
4429 const struct mlx5e_profile
*profile
= priv
->profile
;
4430 struct net_device
*netdev
= priv
->netdev
;
4432 destroy_workqueue(priv
->wq
);
4433 if (profile
->cleanup
)
4434 profile
->cleanup(priv
);
4435 free_netdev(netdev
);
4438 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4439 * hardware contexts and to connect it to the current netdev.
4441 static int mlx5e_attach(struct mlx5_core_dev
*mdev
, void *vpriv
)
4443 struct mlx5e_priv
*priv
= vpriv
;
4444 struct net_device
*netdev
= priv
->netdev
;
4447 if (netif_device_present(netdev
))
4450 err
= mlx5e_create_mdev_resources(mdev
);
4454 err
= mlx5e_attach_netdev(priv
);
4456 mlx5e_destroy_mdev_resources(mdev
);
4463 static void mlx5e_detach(struct mlx5_core_dev
*mdev
, void *vpriv
)
4465 struct mlx5e_priv
*priv
= vpriv
;
4466 struct net_device
*netdev
= priv
->netdev
;
4468 if (!netif_device_present(netdev
))
4471 mlx5e_detach_netdev(priv
);
4472 mlx5e_destroy_mdev_resources(mdev
);
4475 static void *mlx5e_add(struct mlx5_core_dev
*mdev
)
4477 struct net_device
*netdev
;
4482 err
= mlx5e_check_required_hca_cap(mdev
);
4486 #ifdef CONFIG_MLX5_ESWITCH
4487 if (MLX5_VPORT_MANAGER(mdev
)) {
4488 rpriv
= mlx5e_alloc_nic_rep_priv(mdev
);
4490 mlx5_core_warn(mdev
, "Failed to alloc NIC rep priv data\n");
4496 netdev
= mlx5e_create_netdev(mdev
, &mlx5e_nic_profile
, rpriv
);
4498 mlx5_core_err(mdev
, "mlx5e_create_netdev failed\n");
4499 goto err_free_rpriv
;
4502 priv
= netdev_priv(netdev
);
4504 err
= mlx5e_attach(mdev
, priv
);
4506 mlx5_core_err(mdev
, "mlx5e_attach failed, %d\n", err
);
4507 goto err_destroy_netdev
;
4510 err
= register_netdev(netdev
);
4512 mlx5_core_err(mdev
, "register_netdev failed, %d\n", err
);
4519 mlx5e_detach(mdev
, priv
);
4521 mlx5e_destroy_netdev(priv
);
4527 static void mlx5e_remove(struct mlx5_core_dev
*mdev
, void *vpriv
)
4529 struct mlx5e_priv
*priv
= vpriv
;
4530 void *ppriv
= priv
->ppriv
;
4532 unregister_netdev(priv
->netdev
);
4533 mlx5e_detach(mdev
, vpriv
);
4534 mlx5e_destroy_netdev(priv
);
4538 static void *mlx5e_get_netdev(void *vpriv
)
4540 struct mlx5e_priv
*priv
= vpriv
;
4542 return priv
->netdev
;
4545 static struct mlx5_interface mlx5e_interface
= {
4547 .remove
= mlx5e_remove
,
4548 .attach
= mlx5e_attach
,
4549 .detach
= mlx5e_detach
,
4550 .event
= mlx5e_async_event
,
4551 .protocol
= MLX5_INTERFACE_PROTOCOL_ETH
,
4552 .get_dev
= mlx5e_get_netdev
,
4555 void mlx5e_init(void)
4557 mlx5e_ipsec_build_inverse_table();
4558 mlx5e_build_ptys2ethtool_map();
4559 mlx5_register_interface(&mlx5e_interface
);
4562 void mlx5e_cleanup(void)
4564 mlx5_unregister_interface(&mlx5e_interface
);