]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/net/ethernet/mellanox/mlx5/core/en_main.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include "eswitch.h"
39 #include "en.h"
40 #include "en_tc.h"
41 #include "en_rep.h"
42 #include "en_accel/ipsec.h"
43 #include "en_accel/ipsec_rxtx.h"
44 #include "accel/ipsec.h"
45 #include "vxlan.h"
46
47 struct mlx5e_rq_param {
48 u32 rqc[MLX5_ST_SZ_DW(rqc)];
49 struct mlx5_wq_param wq;
50 };
51
52 struct mlx5e_sq_param {
53 u32 sqc[MLX5_ST_SZ_DW(sqc)];
54 struct mlx5_wq_param wq;
55 };
56
57 struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
61 u8 cq_period_mode;
62 };
63
64 struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
67 struct mlx5e_sq_param xdp_sq;
68 struct mlx5e_sq_param icosq;
69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
71 struct mlx5e_cq_param icosq_cq;
72 };
73
74 static int mlx5e_get_node(struct mlx5e_priv *priv, int ix)
75 {
76 return pci_irq_get_node(priv->mdev->pdev, MLX5_EQ_VEC_COMP_BASE + ix);
77 }
78
79 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
80 {
81 return MLX5_CAP_GEN(mdev, striding_rq) &&
82 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
83 MLX5_CAP_ETH(mdev, reg_umr_sq);
84 }
85
86 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
87 struct mlx5e_params *params, u8 rq_type)
88 {
89 params->rq_wq_type = rq_type;
90 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
91 switch (params->rq_wq_type) {
92 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
93 params->log_rq_size = is_kdump_kernel() ?
94 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
95 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
96 params->mpwqe_log_stride_sz =
97 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
98 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
99 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
100 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
101 params->mpwqe_log_stride_sz;
102 break;
103 default: /* MLX5_WQ_TYPE_LINKED_LIST */
104 params->log_rq_size = is_kdump_kernel() ?
105 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
106 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
107 params->rq_headroom = params->xdp_prog ?
108 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
109 params->rq_headroom += NET_IP_ALIGN;
110
111 /* Extra room needed for build_skb */
112 params->lro_wqe_sz -= params->rq_headroom +
113 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
114 }
115
116 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
117 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
118 BIT(params->log_rq_size),
119 BIT(params->mpwqe_log_stride_sz),
120 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
121 }
122
123 static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
124 {
125 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
126 !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
127 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
128 MLX5_WQ_TYPE_LINKED_LIST;
129 mlx5e_set_rq_type_params(mdev, params, rq_type);
130 }
131
132 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
133 {
134 struct mlx5_core_dev *mdev = priv->mdev;
135 u8 port_state;
136
137 port_state = mlx5_query_vport_state(mdev,
138 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
139 0);
140
141 if (port_state == VPORT_STATE_UP) {
142 netdev_info(priv->netdev, "Link up\n");
143 netif_carrier_on(priv->netdev);
144 } else {
145 netdev_info(priv->netdev, "Link down\n");
146 netif_carrier_off(priv->netdev);
147 }
148 }
149
150 static void mlx5e_update_carrier_work(struct work_struct *work)
151 {
152 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
153 update_carrier_work);
154
155 mutex_lock(&priv->state_lock);
156 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
157 if (priv->profile->update_carrier)
158 priv->profile->update_carrier(priv);
159 mutex_unlock(&priv->state_lock);
160 }
161
162 static void mlx5e_tx_timeout_work(struct work_struct *work)
163 {
164 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
165 tx_timeout_work);
166 int err;
167
168 rtnl_lock();
169 mutex_lock(&priv->state_lock);
170 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
171 goto unlock;
172 mlx5e_close_locked(priv->netdev);
173 err = mlx5e_open_locked(priv->netdev);
174 if (err)
175 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
176 err);
177 unlock:
178 mutex_unlock(&priv->state_lock);
179 rtnl_unlock();
180 }
181
182 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
183 {
184 struct mlx5e_sw_stats temp, *s = &temp;
185 struct mlx5e_rq_stats *rq_stats;
186 struct mlx5e_sq_stats *sq_stats;
187 u64 tx_offload_none = 0;
188 int i, j;
189
190 memset(s, 0, sizeof(*s));
191 for (i = 0; i < priv->channels.num; i++) {
192 struct mlx5e_channel *c = priv->channels.c[i];
193
194 rq_stats = &c->rq.stats;
195
196 s->rx_packets += rq_stats->packets;
197 s->rx_bytes += rq_stats->bytes;
198 s->rx_lro_packets += rq_stats->lro_packets;
199 s->rx_lro_bytes += rq_stats->lro_bytes;
200 s->rx_csum_none += rq_stats->csum_none;
201 s->rx_csum_complete += rq_stats->csum_complete;
202 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
203 s->rx_xdp_drop += rq_stats->xdp_drop;
204 s->rx_xdp_tx += rq_stats->xdp_tx;
205 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
206 s->rx_wqe_err += rq_stats->wqe_err;
207 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
208 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
209 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
210 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
211 s->rx_page_reuse += rq_stats->page_reuse;
212 s->rx_cache_reuse += rq_stats->cache_reuse;
213 s->rx_cache_full += rq_stats->cache_full;
214 s->rx_cache_empty += rq_stats->cache_empty;
215 s->rx_cache_busy += rq_stats->cache_busy;
216 s->rx_cache_waive += rq_stats->cache_waive;
217
218 for (j = 0; j < priv->channels.params.num_tc; j++) {
219 sq_stats = &c->sq[j].stats;
220
221 s->tx_packets += sq_stats->packets;
222 s->tx_bytes += sq_stats->bytes;
223 s->tx_tso_packets += sq_stats->tso_packets;
224 s->tx_tso_bytes += sq_stats->tso_bytes;
225 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
226 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
227 s->tx_queue_stopped += sq_stats->stopped;
228 s->tx_queue_wake += sq_stats->wake;
229 s->tx_queue_dropped += sq_stats->dropped;
230 s->tx_xmit_more += sq_stats->xmit_more;
231 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
232 tx_offload_none += sq_stats->csum_none;
233 }
234 }
235
236 /* Update calculated offload counters */
237 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
238 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
239
240 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
241 priv->stats.pport.phy_counters,
242 counter_set.phys_layer_cntrs.link_down_events);
243 memcpy(&priv->stats.sw, s, sizeof(*s));
244 }
245
246 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
247 {
248 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
249 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
250 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
251 struct mlx5_core_dev *mdev = priv->mdev;
252
253 MLX5_SET(query_vport_counter_in, in, opcode,
254 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
255 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
256 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
257
258 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
259 }
260
261 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
262 {
263 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
264 struct mlx5_core_dev *mdev = priv->mdev;
265 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
266 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
267 int prio;
268 void *out;
269
270 MLX5_SET(ppcnt_reg, in, local_port, 1);
271
272 out = pstats->IEEE_802_3_counters;
273 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
274 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
275
276 if (!full)
277 return;
278
279 out = pstats->RFC_2863_counters;
280 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
281 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
282
283 out = pstats->RFC_2819_counters;
284 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
285 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
286
287 out = pstats->phy_counters;
288 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
289 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
290
291 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
292 out = pstats->phy_statistical_counters;
293 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
294 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
295 }
296
297 if (MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) {
298 out = pstats->eth_ext_counters;
299 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
300 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
301 }
302
303 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
304 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
305 out = pstats->per_prio_counters[prio];
306 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
307 mlx5_core_access_reg(mdev, in, sz, out, sz,
308 MLX5_REG_PPCNT, 0, 0);
309 }
310 }
311
312 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
313 {
314 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
315 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
316 int err;
317
318 if (!priv->q_counter)
319 return;
320
321 err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
322 if (err)
323 return;
324
325 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
326 }
327
328 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
329 {
330 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
331 struct mlx5_core_dev *mdev = priv->mdev;
332 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
333 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
334 void *out;
335
336 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
337 return;
338
339 out = pcie_stats->pcie_perf_counters;
340 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
341 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
342 }
343
344 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
345 {
346 if (full) {
347 mlx5e_update_pcie_counters(priv);
348 mlx5e_ipsec_update_stats(priv);
349 }
350 mlx5e_update_pport_counters(priv, full);
351 mlx5e_update_vport_counters(priv);
352 mlx5e_update_q_counter(priv);
353 mlx5e_update_sw_counters(priv);
354 }
355
356 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
357 {
358 mlx5e_update_stats(priv, false);
359 }
360
361 void mlx5e_update_stats_work(struct work_struct *work)
362 {
363 struct delayed_work *dwork = to_delayed_work(work);
364 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
365 update_stats_work);
366 mutex_lock(&priv->state_lock);
367 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
368 priv->profile->update_stats(priv);
369 queue_delayed_work(priv->wq, dwork,
370 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
371 }
372 mutex_unlock(&priv->state_lock);
373 }
374
375 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
376 enum mlx5_dev_event event, unsigned long param)
377 {
378 struct mlx5e_priv *priv = vpriv;
379 struct ptp_clock_event ptp_event;
380 struct mlx5_eqe *eqe = NULL;
381
382 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
383 return;
384
385 switch (event) {
386 case MLX5_DEV_EVENT_PORT_UP:
387 case MLX5_DEV_EVENT_PORT_DOWN:
388 queue_work(priv->wq, &priv->update_carrier_work);
389 break;
390 case MLX5_DEV_EVENT_PPS:
391 eqe = (struct mlx5_eqe *)param;
392 ptp_event.index = eqe->data.pps.pin;
393 ptp_event.timestamp =
394 timecounter_cyc2time(&priv->tstamp.clock,
395 be64_to_cpu(eqe->data.pps.time_stamp));
396 mlx5e_pps_event_handler(vpriv, &ptp_event);
397 break;
398 default:
399 break;
400 }
401 }
402
403 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
404 {
405 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
406 }
407
408 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
409 {
410 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
411 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
412 }
413
414 static inline int mlx5e_get_wqe_mtt_sz(void)
415 {
416 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
417 * To avoid copying garbage after the mtt array, we allocate
418 * a little more.
419 */
420 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
421 MLX5_UMR_MTT_ALIGNMENT);
422 }
423
424 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
425 struct mlx5e_icosq *sq,
426 struct mlx5e_umr_wqe *wqe,
427 u16 ix)
428 {
429 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
430 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
431 struct mlx5_wqe_data_seg *dseg = &wqe->data;
432 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
433 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
434 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
435
436 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
437 ds_cnt);
438 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
439 cseg->imm = rq->mkey_be;
440
441 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
442 ucseg->xlt_octowords =
443 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
444 ucseg->bsf_octowords =
445 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
446 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
447
448 dseg->lkey = sq->mkey_be;
449 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
450 }
451
452 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
453 struct mlx5e_channel *c)
454 {
455 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
456 int mtt_sz = mlx5e_get_wqe_mtt_sz();
457 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
458 int node = mlx5e_get_node(c->priv, c->ix);
459 int i;
460
461 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
462 GFP_KERNEL, node);
463 if (!rq->mpwqe.info)
464 goto err_out;
465
466 /* We allocate more than mtt_sz as we will align the pointer */
467 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz,
468 GFP_KERNEL, node);
469 if (unlikely(!rq->mpwqe.mtt_no_align))
470 goto err_free_wqe_info;
471
472 for (i = 0; i < wq_sz; i++) {
473 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
474
475 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
476 MLX5_UMR_ALIGN);
477 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
478 PCI_DMA_TODEVICE);
479 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
480 goto err_unmap_mtts;
481
482 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
483 }
484
485 return 0;
486
487 err_unmap_mtts:
488 while (--i >= 0) {
489 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
490
491 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
492 PCI_DMA_TODEVICE);
493 }
494 kfree(rq->mpwqe.mtt_no_align);
495 err_free_wqe_info:
496 kfree(rq->mpwqe.info);
497
498 err_out:
499 return -ENOMEM;
500 }
501
502 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
503 {
504 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
505 int mtt_sz = mlx5e_get_wqe_mtt_sz();
506 int i;
507
508 for (i = 0; i < wq_sz; i++) {
509 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
510
511 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
512 PCI_DMA_TODEVICE);
513 }
514 kfree(rq->mpwqe.mtt_no_align);
515 kfree(rq->mpwqe.info);
516 }
517
518 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
519 u64 npages, u8 page_shift,
520 struct mlx5_core_mkey *umr_mkey)
521 {
522 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
523 void *mkc;
524 u32 *in;
525 int err;
526
527 if (!MLX5E_VALID_NUM_MTTS(npages))
528 return -EINVAL;
529
530 in = kvzalloc(inlen, GFP_KERNEL);
531 if (!in)
532 return -ENOMEM;
533
534 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
535
536 MLX5_SET(mkc, mkc, free, 1);
537 MLX5_SET(mkc, mkc, umr_en, 1);
538 MLX5_SET(mkc, mkc, lw, 1);
539 MLX5_SET(mkc, mkc, lr, 1);
540 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
541
542 MLX5_SET(mkc, mkc, qpn, 0xffffff);
543 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
544 MLX5_SET64(mkc, mkc, len, npages << page_shift);
545 MLX5_SET(mkc, mkc, translations_octword_size,
546 MLX5_MTT_OCTW(npages));
547 MLX5_SET(mkc, mkc, log_page_size, page_shift);
548
549 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
550
551 kvfree(in);
552 return err;
553 }
554
555 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
556 {
557 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
558
559 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
560 }
561
562 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
563 struct mlx5e_params *params,
564 struct mlx5e_rq_param *rqp,
565 struct mlx5e_rq *rq)
566 {
567 struct mlx5_core_dev *mdev = c->mdev;
568 void *rqc = rqp->rqc;
569 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
570 u32 byte_count;
571 int npages;
572 int wq_sz;
573 int err;
574 int i;
575
576 rqp->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
577
578 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
579 &rq->wq_ctrl);
580 if (err)
581 return err;
582
583 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
584
585 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
586
587 rq->wq_type = params->rq_wq_type;
588 rq->pdev = c->pdev;
589 rq->netdev = c->netdev;
590 rq->tstamp = c->tstamp;
591 rq->channel = c;
592 rq->ix = c->ix;
593 rq->mdev = mdev;
594
595 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
596 if (IS_ERR(rq->xdp_prog)) {
597 err = PTR_ERR(rq->xdp_prog);
598 rq->xdp_prog = NULL;
599 goto err_rq_wq_destroy;
600 }
601
602 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
603 rq->buff.headroom = params->rq_headroom;
604
605 switch (rq->wq_type) {
606 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
607
608 rq->post_wqes = mlx5e_post_rx_mpwqes;
609 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
610
611 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
612 #ifdef CONFIG_MLX5_EN_IPSEC
613 if (MLX5_IPSEC_DEV(mdev)) {
614 err = -EINVAL;
615 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
616 goto err_rq_wq_destroy;
617 }
618 #endif
619 if (!rq->handle_rx_cqe) {
620 err = -EINVAL;
621 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
622 goto err_rq_wq_destroy;
623 }
624
625 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
626 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
627
628 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
629
630 err = mlx5e_create_rq_umr_mkey(mdev, rq);
631 if (err)
632 goto err_rq_wq_destroy;
633 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
634
635 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
636 if (err)
637 goto err_destroy_umr_mkey;
638 break;
639 default: /* MLX5_WQ_TYPE_LINKED_LIST */
640 rq->wqe.frag_info =
641 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
642 GFP_KERNEL,
643 mlx5e_get_node(c->priv, c->ix));
644 if (!rq->wqe.frag_info) {
645 err = -ENOMEM;
646 goto err_rq_wq_destroy;
647 }
648 rq->post_wqes = mlx5e_post_rx_wqes;
649 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
650
651 #ifdef CONFIG_MLX5_EN_IPSEC
652 if (c->priv->ipsec)
653 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
654 else
655 #endif
656 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
657 if (!rq->handle_rx_cqe) {
658 kfree(rq->wqe.frag_info);
659 err = -EINVAL;
660 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
661 goto err_rq_wq_destroy;
662 }
663
664 byte_count = params->lro_en ?
665 params->lro_wqe_sz :
666 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
667 #ifdef CONFIG_MLX5_EN_IPSEC
668 if (MLX5_IPSEC_DEV(mdev))
669 byte_count += MLX5E_METADATA_ETHER_LEN;
670 #endif
671 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
672
673 /* calc the required page order */
674 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
675 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
676 rq->buff.page_order = order_base_2(npages);
677
678 byte_count |= MLX5_HW_START_PADDING;
679 rq->mkey_be = c->mkey_be;
680 }
681
682 for (i = 0; i < wq_sz; i++) {
683 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
684
685 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
686 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
687
688 wqe->data.addr = cpu_to_be64(dma_offset);
689 }
690
691 wqe->data.byte_count = cpu_to_be32(byte_count);
692 wqe->data.lkey = rq->mkey_be;
693 }
694
695 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
696 rq->am.mode = params->rx_cq_period_mode;
697 rq->page_cache.head = 0;
698 rq->page_cache.tail = 0;
699
700 return 0;
701
702 err_destroy_umr_mkey:
703 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
704
705 err_rq_wq_destroy:
706 if (rq->xdp_prog)
707 bpf_prog_put(rq->xdp_prog);
708 mlx5_wq_destroy(&rq->wq_ctrl);
709
710 return err;
711 }
712
713 static void mlx5e_free_rq(struct mlx5e_rq *rq)
714 {
715 int i;
716
717 if (rq->xdp_prog)
718 bpf_prog_put(rq->xdp_prog);
719
720 switch (rq->wq_type) {
721 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
722 mlx5e_rq_free_mpwqe_info(rq);
723 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
724 break;
725 default: /* MLX5_WQ_TYPE_LINKED_LIST */
726 kfree(rq->wqe.frag_info);
727 }
728
729 for (i = rq->page_cache.head; i != rq->page_cache.tail;
730 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
731 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
732
733 mlx5e_page_release(rq, dma_info, false);
734 }
735 mlx5_wq_destroy(&rq->wq_ctrl);
736 }
737
738 static int mlx5e_create_rq(struct mlx5e_rq *rq,
739 struct mlx5e_rq_param *param)
740 {
741 struct mlx5_core_dev *mdev = rq->mdev;
742
743 void *in;
744 void *rqc;
745 void *wq;
746 int inlen;
747 int err;
748
749 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
750 sizeof(u64) * rq->wq_ctrl.buf.npages;
751 in = kvzalloc(inlen, GFP_KERNEL);
752 if (!in)
753 return -ENOMEM;
754
755 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
756 wq = MLX5_ADDR_OF(rqc, rqc, wq);
757
758 memcpy(rqc, param->rqc, sizeof(param->rqc));
759
760 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
761 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
762 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
763 MLX5_ADAPTER_PAGE_SHIFT);
764 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
765
766 mlx5_fill_page_array(&rq->wq_ctrl.buf,
767 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
768
769 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
770
771 kvfree(in);
772
773 return err;
774 }
775
776 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
777 int next_state)
778 {
779 struct mlx5e_channel *c = rq->channel;
780 struct mlx5_core_dev *mdev = c->mdev;
781
782 void *in;
783 void *rqc;
784 int inlen;
785 int err;
786
787 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
788 in = kvzalloc(inlen, GFP_KERNEL);
789 if (!in)
790 return -ENOMEM;
791
792 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
793
794 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
795 MLX5_SET(rqc, rqc, state, next_state);
796
797 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
798
799 kvfree(in);
800
801 return err;
802 }
803
804 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
805 {
806 struct mlx5e_channel *c = rq->channel;
807 struct mlx5e_priv *priv = c->priv;
808 struct mlx5_core_dev *mdev = priv->mdev;
809
810 void *in;
811 void *rqc;
812 int inlen;
813 int err;
814
815 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
816 in = kvzalloc(inlen, GFP_KERNEL);
817 if (!in)
818 return -ENOMEM;
819
820 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
821
822 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
823 MLX5_SET64(modify_rq_in, in, modify_bitmask,
824 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
825 MLX5_SET(rqc, rqc, scatter_fcs, enable);
826 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
827
828 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
829
830 kvfree(in);
831
832 return err;
833 }
834
835 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
836 {
837 struct mlx5e_channel *c = rq->channel;
838 struct mlx5_core_dev *mdev = c->mdev;
839 void *in;
840 void *rqc;
841 int inlen;
842 int err;
843
844 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
845 in = kvzalloc(inlen, GFP_KERNEL);
846 if (!in)
847 return -ENOMEM;
848
849 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
850
851 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
852 MLX5_SET64(modify_rq_in, in, modify_bitmask,
853 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
854 MLX5_SET(rqc, rqc, vsd, vsd);
855 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
856
857 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
858
859 kvfree(in);
860
861 return err;
862 }
863
864 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
865 {
866 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
867 }
868
869 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
870 {
871 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
872 struct mlx5e_channel *c = rq->channel;
873
874 struct mlx5_wq_ll *wq = &rq->wq;
875 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
876
877 while (time_before(jiffies, exp_time)) {
878 if (wq->cur_sz >= min_wqes)
879 return 0;
880
881 msleep(20);
882 }
883
884 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
885 rq->rqn, wq->cur_sz, min_wqes);
886 return -ETIMEDOUT;
887 }
888
889 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
890 {
891 struct mlx5_wq_ll *wq = &rq->wq;
892 struct mlx5e_rx_wqe *wqe;
893 __be16 wqe_ix_be;
894 u16 wqe_ix;
895
896 /* UMR WQE (if in progress) is always at wq->head */
897 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
898 rq->mpwqe.umr_in_progress)
899 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
900
901 while (!mlx5_wq_ll_is_empty(wq)) {
902 wqe_ix_be = *wq->tail_next;
903 wqe_ix = be16_to_cpu(wqe_ix_be);
904 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
905 rq->dealloc_wqe(rq, wqe_ix);
906 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
907 &wqe->next.next_wqe_index);
908 }
909
910 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
911 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
912 * but yet to be re-posted.
913 */
914 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
915
916 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
917 rq->dealloc_wqe(rq, wqe_ix);
918 }
919 }
920
921 static int mlx5e_open_rq(struct mlx5e_channel *c,
922 struct mlx5e_params *params,
923 struct mlx5e_rq_param *param,
924 struct mlx5e_rq *rq)
925 {
926 int err;
927
928 err = mlx5e_alloc_rq(c, params, param, rq);
929 if (err)
930 return err;
931
932 err = mlx5e_create_rq(rq, param);
933 if (err)
934 goto err_free_rq;
935
936 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
937 if (err)
938 goto err_destroy_rq;
939
940 if (params->rx_am_enabled)
941 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
942
943 return 0;
944
945 err_destroy_rq:
946 mlx5e_destroy_rq(rq);
947 err_free_rq:
948 mlx5e_free_rq(rq);
949
950 return err;
951 }
952
953 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
954 {
955 struct mlx5e_icosq *sq = &rq->channel->icosq;
956 u16 pi = sq->pc & sq->wq.sz_m1;
957 struct mlx5e_tx_wqe *nopwqe;
958
959 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
960 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
961 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
962 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
963 }
964
965 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
966 {
967 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
968 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
969 }
970
971 static void mlx5e_close_rq(struct mlx5e_rq *rq)
972 {
973 cancel_work_sync(&rq->am.work);
974 mlx5e_destroy_rq(rq);
975 mlx5e_free_rx_descs(rq);
976 mlx5e_free_rq(rq);
977 }
978
979 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
980 {
981 kfree(sq->db.di);
982 }
983
984 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
985 {
986 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
987
988 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
989 GFP_KERNEL, numa);
990 if (!sq->db.di) {
991 mlx5e_free_xdpsq_db(sq);
992 return -ENOMEM;
993 }
994
995 return 0;
996 }
997
998 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
999 struct mlx5e_params *params,
1000 struct mlx5e_sq_param *param,
1001 struct mlx5e_xdpsq *sq)
1002 {
1003 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1004 struct mlx5_core_dev *mdev = c->mdev;
1005 int err;
1006
1007 sq->pdev = c->pdev;
1008 sq->mkey_be = c->mkey_be;
1009 sq->channel = c;
1010 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1011 sq->min_inline_mode = params->tx_min_inline_mode;
1012
1013 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1014 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1015 if (err)
1016 return err;
1017 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1018
1019 err = mlx5e_alloc_xdpsq_db(sq, mlx5e_get_node(c->priv, c->ix));
1020 if (err)
1021 goto err_sq_wq_destroy;
1022
1023 return 0;
1024
1025 err_sq_wq_destroy:
1026 mlx5_wq_destroy(&sq->wq_ctrl);
1027
1028 return err;
1029 }
1030
1031 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1032 {
1033 mlx5e_free_xdpsq_db(sq);
1034 mlx5_wq_destroy(&sq->wq_ctrl);
1035 }
1036
1037 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1038 {
1039 kfree(sq->db.ico_wqe);
1040 }
1041
1042 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1043 {
1044 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1045
1046 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1047 GFP_KERNEL, numa);
1048 if (!sq->db.ico_wqe)
1049 return -ENOMEM;
1050
1051 return 0;
1052 }
1053
1054 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1055 struct mlx5e_sq_param *param,
1056 struct mlx5e_icosq *sq)
1057 {
1058 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1059 struct mlx5_core_dev *mdev = c->mdev;
1060 int err;
1061
1062 sq->mkey_be = c->mkey_be;
1063 sq->channel = c;
1064 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1065
1066 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1067 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1068 if (err)
1069 return err;
1070 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1071
1072 err = mlx5e_alloc_icosq_db(sq, mlx5e_get_node(c->priv, c->ix));
1073 if (err)
1074 goto err_sq_wq_destroy;
1075
1076 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
1077
1078 return 0;
1079
1080 err_sq_wq_destroy:
1081 mlx5_wq_destroy(&sq->wq_ctrl);
1082
1083 return err;
1084 }
1085
1086 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1087 {
1088 mlx5e_free_icosq_db(sq);
1089 mlx5_wq_destroy(&sq->wq_ctrl);
1090 }
1091
1092 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1093 {
1094 kfree(sq->db.wqe_info);
1095 kfree(sq->db.dma_fifo);
1096 }
1097
1098 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1099 {
1100 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1101 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1102
1103 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1104 GFP_KERNEL, numa);
1105 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1106 GFP_KERNEL, numa);
1107 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1108 mlx5e_free_txqsq_db(sq);
1109 return -ENOMEM;
1110 }
1111
1112 sq->dma_fifo_mask = df_sz - 1;
1113
1114 return 0;
1115 }
1116
1117 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1118 int txq_ix,
1119 struct mlx5e_params *params,
1120 struct mlx5e_sq_param *param,
1121 struct mlx5e_txqsq *sq)
1122 {
1123 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1124 struct mlx5_core_dev *mdev = c->mdev;
1125 int err;
1126
1127 sq->pdev = c->pdev;
1128 sq->tstamp = c->tstamp;
1129 sq->mkey_be = c->mkey_be;
1130 sq->channel = c;
1131 sq->txq_ix = txq_ix;
1132 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1133 sq->max_inline = params->tx_max_inline;
1134 sq->min_inline_mode = params->tx_min_inline_mode;
1135 if (MLX5_IPSEC_DEV(c->priv->mdev))
1136 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1137
1138 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1139 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1140 if (err)
1141 return err;
1142 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1143
1144 err = mlx5e_alloc_txqsq_db(sq, mlx5e_get_node(c->priv, c->ix));
1145 if (err)
1146 goto err_sq_wq_destroy;
1147
1148 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1149
1150 return 0;
1151
1152 err_sq_wq_destroy:
1153 mlx5_wq_destroy(&sq->wq_ctrl);
1154
1155 return err;
1156 }
1157
1158 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1159 {
1160 mlx5e_free_txqsq_db(sq);
1161 mlx5_wq_destroy(&sq->wq_ctrl);
1162 }
1163
1164 struct mlx5e_create_sq_param {
1165 struct mlx5_wq_ctrl *wq_ctrl;
1166 u32 cqn;
1167 u32 tisn;
1168 u8 tis_lst_sz;
1169 u8 min_inline_mode;
1170 };
1171
1172 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1173 struct mlx5e_sq_param *param,
1174 struct mlx5e_create_sq_param *csp,
1175 u32 *sqn)
1176 {
1177 void *in;
1178 void *sqc;
1179 void *wq;
1180 int inlen;
1181 int err;
1182
1183 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1184 sizeof(u64) * csp->wq_ctrl->buf.npages;
1185 in = kvzalloc(inlen, GFP_KERNEL);
1186 if (!in)
1187 return -ENOMEM;
1188
1189 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1190 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1191
1192 memcpy(sqc, param->sqc, sizeof(param->sqc));
1193 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1194 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1195 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1196
1197 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1198 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1199
1200 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1201
1202 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1203 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1204 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1205 MLX5_ADAPTER_PAGE_SHIFT);
1206 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1207
1208 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1209
1210 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1211
1212 kvfree(in);
1213
1214 return err;
1215 }
1216
1217 struct mlx5e_modify_sq_param {
1218 int curr_state;
1219 int next_state;
1220 bool rl_update;
1221 int rl_index;
1222 };
1223
1224 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1225 struct mlx5e_modify_sq_param *p)
1226 {
1227 void *in;
1228 void *sqc;
1229 int inlen;
1230 int err;
1231
1232 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1233 in = kvzalloc(inlen, GFP_KERNEL);
1234 if (!in)
1235 return -ENOMEM;
1236
1237 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1238
1239 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1240 MLX5_SET(sqc, sqc, state, p->next_state);
1241 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1242 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1243 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1244 }
1245
1246 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1247
1248 kvfree(in);
1249
1250 return err;
1251 }
1252
1253 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1254 {
1255 mlx5_core_destroy_sq(mdev, sqn);
1256 }
1257
1258 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1259 struct mlx5e_sq_param *param,
1260 struct mlx5e_create_sq_param *csp,
1261 u32 *sqn)
1262 {
1263 struct mlx5e_modify_sq_param msp = {0};
1264 int err;
1265
1266 err = mlx5e_create_sq(mdev, param, csp, sqn);
1267 if (err)
1268 return err;
1269
1270 msp.curr_state = MLX5_SQC_STATE_RST;
1271 msp.next_state = MLX5_SQC_STATE_RDY;
1272 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1273 if (err)
1274 mlx5e_destroy_sq(mdev, *sqn);
1275
1276 return err;
1277 }
1278
1279 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1280 struct mlx5e_txqsq *sq, u32 rate);
1281
1282 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1283 u32 tisn,
1284 int txq_ix,
1285 struct mlx5e_params *params,
1286 struct mlx5e_sq_param *param,
1287 struct mlx5e_txqsq *sq)
1288 {
1289 struct mlx5e_create_sq_param csp = {};
1290 u32 tx_rate;
1291 int err;
1292
1293 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1294 if (err)
1295 return err;
1296
1297 csp.tisn = tisn;
1298 csp.tis_lst_sz = 1;
1299 csp.cqn = sq->cq.mcq.cqn;
1300 csp.wq_ctrl = &sq->wq_ctrl;
1301 csp.min_inline_mode = sq->min_inline_mode;
1302 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1303 if (err)
1304 goto err_free_txqsq;
1305
1306 tx_rate = c->priv->tx_rates[sq->txq_ix];
1307 if (tx_rate)
1308 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1309
1310 return 0;
1311
1312 err_free_txqsq:
1313 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1314 mlx5e_free_txqsq(sq);
1315
1316 return err;
1317 }
1318
1319 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1320 {
1321 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1322 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1323 netdev_tx_reset_queue(sq->txq);
1324 netif_tx_start_queue(sq->txq);
1325 }
1326
1327 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1328 {
1329 __netif_tx_lock_bh(txq);
1330 netif_tx_stop_queue(txq);
1331 __netif_tx_unlock_bh(txq);
1332 }
1333
1334 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1335 {
1336 struct mlx5e_channel *c = sq->channel;
1337
1338 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1339 /* prevent netif_tx_wake_queue */
1340 napi_synchronize(&c->napi);
1341
1342 netif_tx_disable_queue(sq->txq);
1343
1344 /* last doorbell out, godspeed .. */
1345 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1346 struct mlx5e_tx_wqe *nop;
1347
1348 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1349 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1350 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1351 }
1352 }
1353
1354 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1355 {
1356 struct mlx5e_channel *c = sq->channel;
1357 struct mlx5_core_dev *mdev = c->mdev;
1358
1359 mlx5e_destroy_sq(mdev, sq->sqn);
1360 if (sq->rate_limit)
1361 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1362 mlx5e_free_txqsq_descs(sq);
1363 mlx5e_free_txqsq(sq);
1364 }
1365
1366 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1367 struct mlx5e_params *params,
1368 struct mlx5e_sq_param *param,
1369 struct mlx5e_icosq *sq)
1370 {
1371 struct mlx5e_create_sq_param csp = {};
1372 int err;
1373
1374 err = mlx5e_alloc_icosq(c, param, sq);
1375 if (err)
1376 return err;
1377
1378 csp.cqn = sq->cq.mcq.cqn;
1379 csp.wq_ctrl = &sq->wq_ctrl;
1380 csp.min_inline_mode = params->tx_min_inline_mode;
1381 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1382 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1383 if (err)
1384 goto err_free_icosq;
1385
1386 return 0;
1387
1388 err_free_icosq:
1389 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1390 mlx5e_free_icosq(sq);
1391
1392 return err;
1393 }
1394
1395 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1396 {
1397 struct mlx5e_channel *c = sq->channel;
1398
1399 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1400 napi_synchronize(&c->napi);
1401
1402 mlx5e_destroy_sq(c->mdev, sq->sqn);
1403 mlx5e_free_icosq(sq);
1404 }
1405
1406 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1407 struct mlx5e_params *params,
1408 struct mlx5e_sq_param *param,
1409 struct mlx5e_xdpsq *sq)
1410 {
1411 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1412 struct mlx5e_create_sq_param csp = {};
1413 unsigned int inline_hdr_sz = 0;
1414 int err;
1415 int i;
1416
1417 err = mlx5e_alloc_xdpsq(c, params, param, sq);
1418 if (err)
1419 return err;
1420
1421 csp.tis_lst_sz = 1;
1422 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1423 csp.cqn = sq->cq.mcq.cqn;
1424 csp.wq_ctrl = &sq->wq_ctrl;
1425 csp.min_inline_mode = sq->min_inline_mode;
1426 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1427 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1428 if (err)
1429 goto err_free_xdpsq;
1430
1431 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1432 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1433 ds_cnt++;
1434 }
1435
1436 /* Pre initialize fixed WQE fields */
1437 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1438 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1439 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1440 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1441 struct mlx5_wqe_data_seg *dseg;
1442
1443 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1444 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1445
1446 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1447 dseg->lkey = sq->mkey_be;
1448 }
1449
1450 return 0;
1451
1452 err_free_xdpsq:
1453 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1454 mlx5e_free_xdpsq(sq);
1455
1456 return err;
1457 }
1458
1459 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1460 {
1461 struct mlx5e_channel *c = sq->channel;
1462
1463 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1464 napi_synchronize(&c->napi);
1465
1466 mlx5e_destroy_sq(c->mdev, sq->sqn);
1467 mlx5e_free_xdpsq_descs(sq);
1468 mlx5e_free_xdpsq(sq);
1469 }
1470
1471 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1472 struct mlx5e_cq_param *param,
1473 struct mlx5e_cq *cq)
1474 {
1475 struct mlx5_core_cq *mcq = &cq->mcq;
1476 int eqn_not_used;
1477 unsigned int irqn;
1478 int err;
1479 u32 i;
1480
1481 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1482 &cq->wq_ctrl);
1483 if (err)
1484 return err;
1485
1486 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1487
1488 mcq->cqe_sz = 64;
1489 mcq->set_ci_db = cq->wq_ctrl.db.db;
1490 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1491 *mcq->set_ci_db = 0;
1492 *mcq->arm_db = 0;
1493 mcq->vector = param->eq_ix;
1494 mcq->comp = mlx5e_completion_event;
1495 mcq->event = mlx5e_cq_error_event;
1496 mcq->irqn = irqn;
1497
1498 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1499 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1500
1501 cqe->op_own = 0xf1;
1502 }
1503
1504 cq->mdev = mdev;
1505
1506 return 0;
1507 }
1508
1509 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1510 struct mlx5e_cq_param *param,
1511 struct mlx5e_cq *cq)
1512 {
1513 struct mlx5_core_dev *mdev = c->priv->mdev;
1514 int err;
1515
1516 param->wq.buf_numa_node = mlx5e_get_node(c->priv, c->ix);
1517 param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);
1518 param->eq_ix = c->ix;
1519
1520 err = mlx5e_alloc_cq_common(mdev, param, cq);
1521
1522 cq->napi = &c->napi;
1523 cq->channel = c;
1524
1525 return err;
1526 }
1527
1528 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1529 {
1530 mlx5_cqwq_destroy(&cq->wq_ctrl);
1531 }
1532
1533 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1534 {
1535 struct mlx5_core_dev *mdev = cq->mdev;
1536 struct mlx5_core_cq *mcq = &cq->mcq;
1537
1538 void *in;
1539 void *cqc;
1540 int inlen;
1541 unsigned int irqn_not_used;
1542 int eqn;
1543 int err;
1544
1545 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1546 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1547 in = kvzalloc(inlen, GFP_KERNEL);
1548 if (!in)
1549 return -ENOMEM;
1550
1551 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1552
1553 memcpy(cqc, param->cqc, sizeof(param->cqc));
1554
1555 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1556 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1557
1558 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1559
1560 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1561 MLX5_SET(cqc, cqc, c_eqn, eqn);
1562 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1563 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1564 MLX5_ADAPTER_PAGE_SHIFT);
1565 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1566
1567 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1568
1569 kvfree(in);
1570
1571 if (err)
1572 return err;
1573
1574 mlx5e_cq_arm(cq);
1575
1576 return 0;
1577 }
1578
1579 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1580 {
1581 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1582 }
1583
1584 static int mlx5e_open_cq(struct mlx5e_channel *c,
1585 struct mlx5e_cq_moder moder,
1586 struct mlx5e_cq_param *param,
1587 struct mlx5e_cq *cq)
1588 {
1589 struct mlx5_core_dev *mdev = c->mdev;
1590 int err;
1591
1592 err = mlx5e_alloc_cq(c, param, cq);
1593 if (err)
1594 return err;
1595
1596 err = mlx5e_create_cq(cq, param);
1597 if (err)
1598 goto err_free_cq;
1599
1600 if (MLX5_CAP_GEN(mdev, cq_moderation))
1601 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1602 return 0;
1603
1604 err_free_cq:
1605 mlx5e_free_cq(cq);
1606
1607 return err;
1608 }
1609
1610 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1611 {
1612 mlx5e_destroy_cq(cq);
1613 mlx5e_free_cq(cq);
1614 }
1615
1616 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1617 struct mlx5e_params *params,
1618 struct mlx5e_channel_param *cparam)
1619 {
1620 int err;
1621 int tc;
1622
1623 for (tc = 0; tc < c->num_tc; tc++) {
1624 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1625 &cparam->tx_cq, &c->sq[tc].cq);
1626 if (err)
1627 goto err_close_tx_cqs;
1628 }
1629
1630 return 0;
1631
1632 err_close_tx_cqs:
1633 for (tc--; tc >= 0; tc--)
1634 mlx5e_close_cq(&c->sq[tc].cq);
1635
1636 return err;
1637 }
1638
1639 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1640 {
1641 int tc;
1642
1643 for (tc = 0; tc < c->num_tc; tc++)
1644 mlx5e_close_cq(&c->sq[tc].cq);
1645 }
1646
1647 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1648 struct mlx5e_params *params,
1649 struct mlx5e_channel_param *cparam)
1650 {
1651 int err;
1652 int tc;
1653
1654 for (tc = 0; tc < params->num_tc; tc++) {
1655 int txq_ix = c->ix + tc * params->num_channels;
1656
1657 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1658 params, &cparam->sq, &c->sq[tc]);
1659 if (err)
1660 goto err_close_sqs;
1661 }
1662
1663 return 0;
1664
1665 err_close_sqs:
1666 for (tc--; tc >= 0; tc--)
1667 mlx5e_close_txqsq(&c->sq[tc]);
1668
1669 return err;
1670 }
1671
1672 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1673 {
1674 int tc;
1675
1676 for (tc = 0; tc < c->num_tc; tc++)
1677 mlx5e_close_txqsq(&c->sq[tc]);
1678 }
1679
1680 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1681 struct mlx5e_txqsq *sq, u32 rate)
1682 {
1683 struct mlx5e_priv *priv = netdev_priv(dev);
1684 struct mlx5_core_dev *mdev = priv->mdev;
1685 struct mlx5e_modify_sq_param msp = {0};
1686 u16 rl_index = 0;
1687 int err;
1688
1689 if (rate == sq->rate_limit)
1690 /* nothing to do */
1691 return 0;
1692
1693 if (sq->rate_limit)
1694 /* remove current rl index to free space to next ones */
1695 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1696
1697 sq->rate_limit = 0;
1698
1699 if (rate) {
1700 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1701 if (err) {
1702 netdev_err(dev, "Failed configuring rate %u: %d\n",
1703 rate, err);
1704 return err;
1705 }
1706 }
1707
1708 msp.curr_state = MLX5_SQC_STATE_RDY;
1709 msp.next_state = MLX5_SQC_STATE_RDY;
1710 msp.rl_index = rl_index;
1711 msp.rl_update = true;
1712 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1713 if (err) {
1714 netdev_err(dev, "Failed configuring rate %u: %d\n",
1715 rate, err);
1716 /* remove the rate from the table */
1717 if (rate)
1718 mlx5_rl_remove_rate(mdev, rate);
1719 return err;
1720 }
1721
1722 sq->rate_limit = rate;
1723 return 0;
1724 }
1725
1726 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1727 {
1728 struct mlx5e_priv *priv = netdev_priv(dev);
1729 struct mlx5_core_dev *mdev = priv->mdev;
1730 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1731 int err = 0;
1732
1733 if (!mlx5_rl_is_supported(mdev)) {
1734 netdev_err(dev, "Rate limiting is not supported on this device\n");
1735 return -EINVAL;
1736 }
1737
1738 /* rate is given in Mb/sec, HW config is in Kb/sec */
1739 rate = rate << 10;
1740
1741 /* Check whether rate in valid range, 0 is always valid */
1742 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1743 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1744 return -ERANGE;
1745 }
1746
1747 mutex_lock(&priv->state_lock);
1748 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1749 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1750 if (!err)
1751 priv->tx_rates[index] = rate;
1752 mutex_unlock(&priv->state_lock);
1753
1754 return err;
1755 }
1756
1757 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1758 struct mlx5e_params *params,
1759 struct mlx5e_channel_param *cparam,
1760 struct mlx5e_channel **cp)
1761 {
1762 struct mlx5e_cq_moder icocq_moder = {0, 0};
1763 struct net_device *netdev = priv->netdev;
1764 struct mlx5e_channel *c;
1765 unsigned int irq;
1766 int err;
1767 int eqn;
1768
1769 c = kzalloc_node(sizeof(*c), GFP_KERNEL, mlx5e_get_node(priv, ix));
1770 if (!c)
1771 return -ENOMEM;
1772
1773 c->priv = priv;
1774 c->mdev = priv->mdev;
1775 c->tstamp = &priv->tstamp;
1776 c->ix = ix;
1777 c->pdev = &priv->mdev->pdev->dev;
1778 c->netdev = priv->netdev;
1779 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1780 c->num_tc = params->num_tc;
1781 c->xdp = !!params->xdp_prog;
1782
1783 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1784 c->irq_desc = irq_to_desc(irq);
1785
1786 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1787
1788 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1789 if (err)
1790 goto err_napi_del;
1791
1792 err = mlx5e_open_tx_cqs(c, params, cparam);
1793 if (err)
1794 goto err_close_icosq_cq;
1795
1796 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1797 if (err)
1798 goto err_close_tx_cqs;
1799
1800 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1801 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1802 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1803 if (err)
1804 goto err_close_rx_cq;
1805
1806 napi_enable(&c->napi);
1807
1808 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1809 if (err)
1810 goto err_disable_napi;
1811
1812 err = mlx5e_open_sqs(c, params, cparam);
1813 if (err)
1814 goto err_close_icosq;
1815
1816 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1817 if (err)
1818 goto err_close_sqs;
1819
1820 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1821 if (err)
1822 goto err_close_xdp_sq;
1823
1824 *cp = c;
1825
1826 return 0;
1827 err_close_xdp_sq:
1828 if (c->xdp)
1829 mlx5e_close_xdpsq(&c->rq.xdpsq);
1830
1831 err_close_sqs:
1832 mlx5e_close_sqs(c);
1833
1834 err_close_icosq:
1835 mlx5e_close_icosq(&c->icosq);
1836
1837 err_disable_napi:
1838 napi_disable(&c->napi);
1839 if (c->xdp)
1840 mlx5e_close_cq(&c->rq.xdpsq.cq);
1841
1842 err_close_rx_cq:
1843 mlx5e_close_cq(&c->rq.cq);
1844
1845 err_close_tx_cqs:
1846 mlx5e_close_tx_cqs(c);
1847
1848 err_close_icosq_cq:
1849 mlx5e_close_cq(&c->icosq.cq);
1850
1851 err_napi_del:
1852 netif_napi_del(&c->napi);
1853 kfree(c);
1854
1855 return err;
1856 }
1857
1858 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1859 {
1860 int tc;
1861
1862 for (tc = 0; tc < c->num_tc; tc++)
1863 mlx5e_activate_txqsq(&c->sq[tc]);
1864 mlx5e_activate_rq(&c->rq);
1865 netif_set_xps_queue(c->netdev,
1866 mlx5_get_vector_affinity(c->priv->mdev, c->ix), c->ix);
1867 }
1868
1869 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1870 {
1871 int tc;
1872
1873 mlx5e_deactivate_rq(&c->rq);
1874 for (tc = 0; tc < c->num_tc; tc++)
1875 mlx5e_deactivate_txqsq(&c->sq[tc]);
1876 }
1877
1878 static void mlx5e_close_channel(struct mlx5e_channel *c)
1879 {
1880 mlx5e_close_rq(&c->rq);
1881 if (c->xdp)
1882 mlx5e_close_xdpsq(&c->rq.xdpsq);
1883 mlx5e_close_sqs(c);
1884 mlx5e_close_icosq(&c->icosq);
1885 napi_disable(&c->napi);
1886 if (c->xdp)
1887 mlx5e_close_cq(&c->rq.xdpsq.cq);
1888 mlx5e_close_cq(&c->rq.cq);
1889 mlx5e_close_tx_cqs(c);
1890 mlx5e_close_cq(&c->icosq.cq);
1891 netif_napi_del(&c->napi);
1892
1893 kfree(c);
1894 }
1895
1896 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1897 struct mlx5e_params *params,
1898 struct mlx5e_rq_param *param)
1899 {
1900 void *rqc = param->rqc;
1901 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1902
1903 switch (params->rq_wq_type) {
1904 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1905 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1906 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
1907 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1908 break;
1909 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1910 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1911 }
1912
1913 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1914 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1915 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
1916 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1917 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1918 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
1919 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
1920
1921 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1922 param->wq.linear = 1;
1923 }
1924
1925 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1926 {
1927 void *rqc = param->rqc;
1928 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1929
1930 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1931 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1932 }
1933
1934 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1935 struct mlx5e_sq_param *param)
1936 {
1937 void *sqc = param->sqc;
1938 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1939
1940 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1941 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1942
1943 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1944 }
1945
1946 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1947 struct mlx5e_params *params,
1948 struct mlx5e_sq_param *param)
1949 {
1950 void *sqc = param->sqc;
1951 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1952
1953 mlx5e_build_sq_param_common(priv, param);
1954 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1955 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1956 }
1957
1958 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1959 struct mlx5e_cq_param *param)
1960 {
1961 void *cqc = param->cqc;
1962
1963 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1964 }
1965
1966 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1967 struct mlx5e_params *params,
1968 struct mlx5e_cq_param *param)
1969 {
1970 void *cqc = param->cqc;
1971 u8 log_cq_size;
1972
1973 switch (params->rq_wq_type) {
1974 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1975 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
1976 break;
1977 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1978 log_cq_size = params->log_rq_size;
1979 }
1980
1981 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1982 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1983 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1984 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1985 }
1986
1987 mlx5e_build_common_cq_param(priv, param);
1988 param->cq_period_mode = params->rx_cq_period_mode;
1989 }
1990
1991 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1992 struct mlx5e_params *params,
1993 struct mlx5e_cq_param *param)
1994 {
1995 void *cqc = param->cqc;
1996
1997 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1998
1999 mlx5e_build_common_cq_param(priv, param);
2000
2001 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2002 }
2003
2004 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2005 u8 log_wq_size,
2006 struct mlx5e_cq_param *param)
2007 {
2008 void *cqc = param->cqc;
2009
2010 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2011
2012 mlx5e_build_common_cq_param(priv, param);
2013
2014 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2015 }
2016
2017 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2018 u8 log_wq_size,
2019 struct mlx5e_sq_param *param)
2020 {
2021 void *sqc = param->sqc;
2022 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2023
2024 mlx5e_build_sq_param_common(priv, param);
2025
2026 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2027 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2028 }
2029
2030 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2031 struct mlx5e_params *params,
2032 struct mlx5e_sq_param *param)
2033 {
2034 void *sqc = param->sqc;
2035 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2036
2037 mlx5e_build_sq_param_common(priv, param);
2038 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2039 }
2040
2041 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2042 struct mlx5e_params *params,
2043 struct mlx5e_channel_param *cparam)
2044 {
2045 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2046
2047 mlx5e_build_rq_param(priv, params, &cparam->rq);
2048 mlx5e_build_sq_param(priv, params, &cparam->sq);
2049 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2050 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2051 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2052 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2053 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2054 }
2055
2056 int mlx5e_open_channels(struct mlx5e_priv *priv,
2057 struct mlx5e_channels *chs)
2058 {
2059 struct mlx5e_channel_param *cparam;
2060 int err = -ENOMEM;
2061 int i;
2062
2063 chs->num = chs->params.num_channels;
2064
2065 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2066 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2067 if (!chs->c || !cparam)
2068 goto err_free;
2069
2070 mlx5e_build_channel_param(priv, &chs->params, cparam);
2071 for (i = 0; i < chs->num; i++) {
2072 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2073 if (err)
2074 goto err_close_channels;
2075 }
2076
2077 kfree(cparam);
2078 return 0;
2079
2080 err_close_channels:
2081 for (i--; i >= 0; i--)
2082 mlx5e_close_channel(chs->c[i]);
2083
2084 err_free:
2085 kfree(chs->c);
2086 kfree(cparam);
2087 chs->num = 0;
2088 return err;
2089 }
2090
2091 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2092 {
2093 int i;
2094
2095 for (i = 0; i < chs->num; i++)
2096 mlx5e_activate_channel(chs->c[i]);
2097 }
2098
2099 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2100 {
2101 int err = 0;
2102 int i;
2103
2104 for (i = 0; i < chs->num; i++) {
2105 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2106 if (err)
2107 break;
2108 }
2109
2110 return err;
2111 }
2112
2113 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2114 {
2115 int i;
2116
2117 for (i = 0; i < chs->num; i++)
2118 mlx5e_deactivate_channel(chs->c[i]);
2119 }
2120
2121 void mlx5e_close_channels(struct mlx5e_channels *chs)
2122 {
2123 int i;
2124
2125 for (i = 0; i < chs->num; i++)
2126 mlx5e_close_channel(chs->c[i]);
2127
2128 kfree(chs->c);
2129 chs->num = 0;
2130 }
2131
2132 static int
2133 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2134 {
2135 struct mlx5_core_dev *mdev = priv->mdev;
2136 void *rqtc;
2137 int inlen;
2138 int err;
2139 u32 *in;
2140 int i;
2141
2142 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2143 in = kvzalloc(inlen, GFP_KERNEL);
2144 if (!in)
2145 return -ENOMEM;
2146
2147 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2148
2149 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2150 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2151
2152 for (i = 0; i < sz; i++)
2153 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2154
2155 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2156 if (!err)
2157 rqt->enabled = true;
2158
2159 kvfree(in);
2160 return err;
2161 }
2162
2163 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2164 {
2165 rqt->enabled = false;
2166 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2167 }
2168
2169 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2170 {
2171 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2172 int err;
2173
2174 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2175 if (err)
2176 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2177 return err;
2178 }
2179
2180 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2181 {
2182 struct mlx5e_rqt *rqt;
2183 int err;
2184 int ix;
2185
2186 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2187 rqt = &priv->direct_tir[ix].rqt;
2188 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2189 if (err)
2190 goto err_destroy_rqts;
2191 }
2192
2193 return 0;
2194
2195 err_destroy_rqts:
2196 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2197 for (ix--; ix >= 0; ix--)
2198 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2199
2200 return err;
2201 }
2202
2203 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2204 {
2205 int i;
2206
2207 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2208 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2209 }
2210
2211 static int mlx5e_rx_hash_fn(int hfunc)
2212 {
2213 return (hfunc == ETH_RSS_HASH_TOP) ?
2214 MLX5_RX_HASH_FN_TOEPLITZ :
2215 MLX5_RX_HASH_FN_INVERTED_XOR8;
2216 }
2217
2218 static int mlx5e_bits_invert(unsigned long a, int size)
2219 {
2220 int inv = 0;
2221 int i;
2222
2223 for (i = 0; i < size; i++)
2224 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2225
2226 return inv;
2227 }
2228
2229 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2230 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2231 {
2232 int i;
2233
2234 for (i = 0; i < sz; i++) {
2235 u32 rqn;
2236
2237 if (rrp.is_rss) {
2238 int ix = i;
2239
2240 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2241 ix = mlx5e_bits_invert(i, ilog2(sz));
2242
2243 ix = priv->channels.params.indirection_rqt[ix];
2244 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2245 } else {
2246 rqn = rrp.rqn;
2247 }
2248 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2249 }
2250 }
2251
2252 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2253 struct mlx5e_redirect_rqt_param rrp)
2254 {
2255 struct mlx5_core_dev *mdev = priv->mdev;
2256 void *rqtc;
2257 int inlen;
2258 u32 *in;
2259 int err;
2260
2261 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2262 in = kvzalloc(inlen, GFP_KERNEL);
2263 if (!in)
2264 return -ENOMEM;
2265
2266 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2267
2268 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2269 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2270 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2271 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2272
2273 kvfree(in);
2274 return err;
2275 }
2276
2277 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2278 struct mlx5e_redirect_rqt_param rrp)
2279 {
2280 if (!rrp.is_rss)
2281 return rrp.rqn;
2282
2283 if (ix >= rrp.rss.channels->num)
2284 return priv->drop_rq.rqn;
2285
2286 return rrp.rss.channels->c[ix]->rq.rqn;
2287 }
2288
2289 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2290 struct mlx5e_redirect_rqt_param rrp)
2291 {
2292 u32 rqtn;
2293 int ix;
2294
2295 if (priv->indir_rqt.enabled) {
2296 /* RSS RQ table */
2297 rqtn = priv->indir_rqt.rqtn;
2298 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2299 }
2300
2301 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2302 struct mlx5e_redirect_rqt_param direct_rrp = {
2303 .is_rss = false,
2304 {
2305 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2306 },
2307 };
2308
2309 /* Direct RQ Tables */
2310 if (!priv->direct_tir[ix].rqt.enabled)
2311 continue;
2312
2313 rqtn = priv->direct_tir[ix].rqt.rqtn;
2314 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2315 }
2316 }
2317
2318 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2319 struct mlx5e_channels *chs)
2320 {
2321 struct mlx5e_redirect_rqt_param rrp = {
2322 .is_rss = true,
2323 {
2324 .rss = {
2325 .channels = chs,
2326 .hfunc = chs->params.rss_hfunc,
2327 }
2328 },
2329 };
2330
2331 mlx5e_redirect_rqts(priv, rrp);
2332 }
2333
2334 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2335 {
2336 struct mlx5e_redirect_rqt_param drop_rrp = {
2337 .is_rss = false,
2338 {
2339 .rqn = priv->drop_rq.rqn,
2340 },
2341 };
2342
2343 mlx5e_redirect_rqts(priv, drop_rrp);
2344 }
2345
2346 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2347 {
2348 if (!params->lro_en)
2349 return;
2350
2351 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2352
2353 MLX5_SET(tirc, tirc, lro_enable_mask,
2354 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2355 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2356 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2357 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2358 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2359 }
2360
2361 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2362 enum mlx5e_traffic_types tt,
2363 void *tirc, bool inner)
2364 {
2365 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2366 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2367
2368 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2369 MLX5_HASH_FIELD_SEL_DST_IP)
2370
2371 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2372 MLX5_HASH_FIELD_SEL_DST_IP |\
2373 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2374 MLX5_HASH_FIELD_SEL_L4_DPORT)
2375
2376 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2377 MLX5_HASH_FIELD_SEL_DST_IP |\
2378 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2379
2380 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2381 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2382 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2383 rx_hash_toeplitz_key);
2384 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2385 rx_hash_toeplitz_key);
2386
2387 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2388 memcpy(rss_key, params->toeplitz_hash_key, len);
2389 }
2390
2391 switch (tt) {
2392 case MLX5E_TT_IPV4_TCP:
2393 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2394 MLX5_L3_PROT_TYPE_IPV4);
2395 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2396 MLX5_L4_PROT_TYPE_TCP);
2397 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2398 MLX5_HASH_IP_L4PORTS);
2399 break;
2400
2401 case MLX5E_TT_IPV6_TCP:
2402 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2403 MLX5_L3_PROT_TYPE_IPV6);
2404 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2405 MLX5_L4_PROT_TYPE_TCP);
2406 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2407 MLX5_HASH_IP_L4PORTS);
2408 break;
2409
2410 case MLX5E_TT_IPV4_UDP:
2411 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2412 MLX5_L3_PROT_TYPE_IPV4);
2413 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2414 MLX5_L4_PROT_TYPE_UDP);
2415 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2416 MLX5_HASH_IP_L4PORTS);
2417 break;
2418
2419 case MLX5E_TT_IPV6_UDP:
2420 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2421 MLX5_L3_PROT_TYPE_IPV6);
2422 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2423 MLX5_L4_PROT_TYPE_UDP);
2424 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2425 MLX5_HASH_IP_L4PORTS);
2426 break;
2427
2428 case MLX5E_TT_IPV4_IPSEC_AH:
2429 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2430 MLX5_L3_PROT_TYPE_IPV4);
2431 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2432 MLX5_HASH_IP_IPSEC_SPI);
2433 break;
2434
2435 case MLX5E_TT_IPV6_IPSEC_AH:
2436 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2437 MLX5_L3_PROT_TYPE_IPV6);
2438 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2439 MLX5_HASH_IP_IPSEC_SPI);
2440 break;
2441
2442 case MLX5E_TT_IPV4_IPSEC_ESP:
2443 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2444 MLX5_L3_PROT_TYPE_IPV4);
2445 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2446 MLX5_HASH_IP_IPSEC_SPI);
2447 break;
2448
2449 case MLX5E_TT_IPV6_IPSEC_ESP:
2450 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2451 MLX5_L3_PROT_TYPE_IPV6);
2452 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2453 MLX5_HASH_IP_IPSEC_SPI);
2454 break;
2455
2456 case MLX5E_TT_IPV4:
2457 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2458 MLX5_L3_PROT_TYPE_IPV4);
2459 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2460 MLX5_HASH_IP);
2461 break;
2462
2463 case MLX5E_TT_IPV6:
2464 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2465 MLX5_L3_PROT_TYPE_IPV6);
2466 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2467 MLX5_HASH_IP);
2468 break;
2469 default:
2470 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2471 }
2472 }
2473
2474 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2475 {
2476 struct mlx5_core_dev *mdev = priv->mdev;
2477
2478 void *in;
2479 void *tirc;
2480 int inlen;
2481 int err;
2482 int tt;
2483 int ix;
2484
2485 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2486 in = kvzalloc(inlen, GFP_KERNEL);
2487 if (!in)
2488 return -ENOMEM;
2489
2490 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2491 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2492
2493 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2494
2495 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2496 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2497 inlen);
2498 if (err)
2499 goto free_in;
2500 }
2501
2502 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2503 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2504 in, inlen);
2505 if (err)
2506 goto free_in;
2507 }
2508
2509 free_in:
2510 kvfree(in);
2511
2512 return err;
2513 }
2514
2515 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2516 enum mlx5e_traffic_types tt,
2517 u32 *tirc)
2518 {
2519 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2520
2521 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2522
2523 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2524 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2525 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2526
2527 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2528 }
2529
2530 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2531 {
2532 struct mlx5_core_dev *mdev = priv->mdev;
2533 u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
2534 int err;
2535
2536 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2537 if (err)
2538 return err;
2539
2540 /* Update vport context MTU */
2541 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2542 return 0;
2543 }
2544
2545 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2546 {
2547 struct mlx5_core_dev *mdev = priv->mdev;
2548 u16 hw_mtu = 0;
2549 int err;
2550
2551 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2552 if (err || !hw_mtu) /* fallback to port oper mtu */
2553 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2554
2555 *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
2556 }
2557
2558 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2559 {
2560 struct net_device *netdev = priv->netdev;
2561 u16 mtu;
2562 int err;
2563
2564 err = mlx5e_set_mtu(priv, netdev->mtu);
2565 if (err)
2566 return err;
2567
2568 mlx5e_query_mtu(priv, &mtu);
2569 if (mtu != netdev->mtu)
2570 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2571 __func__, mtu, netdev->mtu);
2572
2573 netdev->mtu = mtu;
2574 return 0;
2575 }
2576
2577 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2578 {
2579 struct mlx5e_priv *priv = netdev_priv(netdev);
2580 int nch = priv->channels.params.num_channels;
2581 int ntc = priv->channels.params.num_tc;
2582 int tc;
2583
2584 netdev_reset_tc(netdev);
2585
2586 if (ntc == 1)
2587 return;
2588
2589 netdev_set_num_tc(netdev, ntc);
2590
2591 /* Map netdev TCs to offset 0
2592 * We have our own UP to TXQ mapping for QoS
2593 */
2594 for (tc = 0; tc < ntc; tc++)
2595 netdev_set_tc_queue(netdev, tc, nch, 0);
2596 }
2597
2598 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2599 {
2600 struct mlx5e_channel *c;
2601 struct mlx5e_txqsq *sq;
2602 int i, tc;
2603
2604 for (i = 0; i < priv->channels.num; i++)
2605 for (tc = 0; tc < priv->profile->max_tc; tc++)
2606 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2607
2608 for (i = 0; i < priv->channels.num; i++) {
2609 c = priv->channels.c[i];
2610 for (tc = 0; tc < c->num_tc; tc++) {
2611 sq = &c->sq[tc];
2612 priv->txq2sq[sq->txq_ix] = sq;
2613 }
2614 }
2615 }
2616
2617 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2618 {
2619 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2620 struct net_device *netdev = priv->netdev;
2621
2622 mlx5e_netdev_set_tcs(netdev);
2623 netif_set_real_num_tx_queues(netdev, num_txqs);
2624 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2625
2626 mlx5e_build_channels_tx_maps(priv);
2627 mlx5e_activate_channels(&priv->channels);
2628 netif_tx_start_all_queues(priv->netdev);
2629
2630 if (MLX5_VPORT_MANAGER(priv->mdev))
2631 mlx5e_add_sqs_fwd_rules(priv);
2632
2633 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2634 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2635 }
2636
2637 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2638 {
2639 mlx5e_redirect_rqts_to_drop(priv);
2640
2641 if (MLX5_VPORT_MANAGER(priv->mdev))
2642 mlx5e_remove_sqs_fwd_rules(priv);
2643
2644 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2645 * polling for inactive tx queues.
2646 */
2647 netif_tx_stop_all_queues(priv->netdev);
2648 netif_tx_disable(priv->netdev);
2649 mlx5e_deactivate_channels(&priv->channels);
2650 }
2651
2652 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2653 struct mlx5e_channels *new_chs,
2654 mlx5e_fp_hw_modify hw_modify)
2655 {
2656 struct net_device *netdev = priv->netdev;
2657 int new_num_txqs;
2658 int carrier_ok;
2659 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2660
2661 carrier_ok = netif_carrier_ok(netdev);
2662 netif_carrier_off(netdev);
2663
2664 if (new_num_txqs < netdev->real_num_tx_queues)
2665 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2666
2667 mlx5e_deactivate_priv_channels(priv);
2668 mlx5e_close_channels(&priv->channels);
2669
2670 priv->channels = *new_chs;
2671
2672 /* New channels are ready to roll, modify HW settings if needed */
2673 if (hw_modify)
2674 hw_modify(priv);
2675
2676 mlx5e_refresh_tirs(priv, false);
2677 mlx5e_activate_priv_channels(priv);
2678
2679 /* return carrier back if needed */
2680 if (carrier_ok)
2681 netif_carrier_on(netdev);
2682 }
2683
2684 int mlx5e_open_locked(struct net_device *netdev)
2685 {
2686 struct mlx5e_priv *priv = netdev_priv(netdev);
2687 int err;
2688
2689 set_bit(MLX5E_STATE_OPENED, &priv->state);
2690
2691 err = mlx5e_open_channels(priv, &priv->channels);
2692 if (err)
2693 goto err_clear_state_opened_flag;
2694
2695 mlx5e_refresh_tirs(priv, false);
2696 mlx5e_activate_priv_channels(priv);
2697 if (priv->profile->update_carrier)
2698 priv->profile->update_carrier(priv);
2699 mlx5e_timestamp_init(priv);
2700
2701 if (priv->profile->update_stats)
2702 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2703
2704 return 0;
2705
2706 err_clear_state_opened_flag:
2707 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2708 return err;
2709 }
2710
2711 int mlx5e_open(struct net_device *netdev)
2712 {
2713 struct mlx5e_priv *priv = netdev_priv(netdev);
2714 int err;
2715
2716 mutex_lock(&priv->state_lock);
2717 err = mlx5e_open_locked(netdev);
2718 if (!err)
2719 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2720 mutex_unlock(&priv->state_lock);
2721
2722 return err;
2723 }
2724
2725 int mlx5e_close_locked(struct net_device *netdev)
2726 {
2727 struct mlx5e_priv *priv = netdev_priv(netdev);
2728
2729 /* May already be CLOSED in case a previous configuration operation
2730 * (e.g RX/TX queue size change) that involves close&open failed.
2731 */
2732 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2733 return 0;
2734
2735 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2736
2737 mlx5e_timestamp_cleanup(priv);
2738 netif_carrier_off(priv->netdev);
2739 mlx5e_deactivate_priv_channels(priv);
2740 mlx5e_close_channels(&priv->channels);
2741
2742 return 0;
2743 }
2744
2745 int mlx5e_close(struct net_device *netdev)
2746 {
2747 struct mlx5e_priv *priv = netdev_priv(netdev);
2748 int err;
2749
2750 if (!netif_device_present(netdev))
2751 return -ENODEV;
2752
2753 mutex_lock(&priv->state_lock);
2754 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2755 err = mlx5e_close_locked(netdev);
2756 mutex_unlock(&priv->state_lock);
2757
2758 return err;
2759 }
2760
2761 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2762 struct mlx5e_rq *rq,
2763 struct mlx5e_rq_param *param)
2764 {
2765 void *rqc = param->rqc;
2766 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2767 int err;
2768
2769 param->wq.db_numa_node = param->wq.buf_numa_node;
2770
2771 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2772 &rq->wq_ctrl);
2773 if (err)
2774 return err;
2775
2776 rq->mdev = mdev;
2777
2778 return 0;
2779 }
2780
2781 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2782 struct mlx5e_cq *cq,
2783 struct mlx5e_cq_param *param)
2784 {
2785 return mlx5e_alloc_cq_common(mdev, param, cq);
2786 }
2787
2788 static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2789 struct mlx5e_rq *drop_rq)
2790 {
2791 struct mlx5e_cq_param cq_param = {};
2792 struct mlx5e_rq_param rq_param = {};
2793 struct mlx5e_cq *cq = &drop_rq->cq;
2794 int err;
2795
2796 mlx5e_build_drop_rq_param(&rq_param);
2797
2798 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2799 if (err)
2800 return err;
2801
2802 err = mlx5e_create_cq(cq, &cq_param);
2803 if (err)
2804 goto err_free_cq;
2805
2806 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2807 if (err)
2808 goto err_destroy_cq;
2809
2810 err = mlx5e_create_rq(drop_rq, &rq_param);
2811 if (err)
2812 goto err_free_rq;
2813
2814 return 0;
2815
2816 err_free_rq:
2817 mlx5e_free_rq(drop_rq);
2818
2819 err_destroy_cq:
2820 mlx5e_destroy_cq(cq);
2821
2822 err_free_cq:
2823 mlx5e_free_cq(cq);
2824
2825 return err;
2826 }
2827
2828 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2829 {
2830 mlx5e_destroy_rq(drop_rq);
2831 mlx5e_free_rq(drop_rq);
2832 mlx5e_destroy_cq(&drop_rq->cq);
2833 mlx5e_free_cq(&drop_rq->cq);
2834 }
2835
2836 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2837 u32 underlay_qpn, u32 *tisn)
2838 {
2839 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2840 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2841
2842 MLX5_SET(tisc, tisc, prio, tc << 1);
2843 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2844 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2845
2846 if (mlx5_lag_is_lacp_owner(mdev))
2847 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2848
2849 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2850 }
2851
2852 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2853 {
2854 mlx5_core_destroy_tis(mdev, tisn);
2855 }
2856
2857 int mlx5e_create_tises(struct mlx5e_priv *priv)
2858 {
2859 int err;
2860 int tc;
2861
2862 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2863 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2864 if (err)
2865 goto err_close_tises;
2866 }
2867
2868 return 0;
2869
2870 err_close_tises:
2871 for (tc--; tc >= 0; tc--)
2872 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2873
2874 return err;
2875 }
2876
2877 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2878 {
2879 int tc;
2880
2881 for (tc = 0; tc < priv->profile->max_tc; tc++)
2882 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2883 }
2884
2885 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2886 enum mlx5e_traffic_types tt,
2887 u32 *tirc)
2888 {
2889 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2890
2891 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2892
2893 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2894 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2895 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2896 }
2897
2898 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2899 {
2900 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2901
2902 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2903
2904 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2905 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2906 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2907 }
2908
2909 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2910 {
2911 struct mlx5e_tir *tir;
2912 void *tirc;
2913 int inlen;
2914 int i = 0;
2915 int err;
2916 u32 *in;
2917 int tt;
2918
2919 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2920 in = kvzalloc(inlen, GFP_KERNEL);
2921 if (!in)
2922 return -ENOMEM;
2923
2924 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2925 memset(in, 0, inlen);
2926 tir = &priv->indir_tir[tt];
2927 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2928 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2929 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2930 if (err) {
2931 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2932 goto err_destroy_inner_tirs;
2933 }
2934 }
2935
2936 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2937 goto out;
2938
2939 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2940 memset(in, 0, inlen);
2941 tir = &priv->inner_indir_tir[i];
2942 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2943 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2944 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2945 if (err) {
2946 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2947 goto err_destroy_inner_tirs;
2948 }
2949 }
2950
2951 out:
2952 kvfree(in);
2953
2954 return 0;
2955
2956 err_destroy_inner_tirs:
2957 for (i--; i >= 0; i--)
2958 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2959
2960 for (tt--; tt >= 0; tt--)
2961 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2962
2963 kvfree(in);
2964
2965 return err;
2966 }
2967
2968 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2969 {
2970 int nch = priv->profile->max_nch(priv->mdev);
2971 struct mlx5e_tir *tir;
2972 void *tirc;
2973 int inlen;
2974 int err;
2975 u32 *in;
2976 int ix;
2977
2978 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2979 in = kvzalloc(inlen, GFP_KERNEL);
2980 if (!in)
2981 return -ENOMEM;
2982
2983 for (ix = 0; ix < nch; ix++) {
2984 memset(in, 0, inlen);
2985 tir = &priv->direct_tir[ix];
2986 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2987 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2988 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2989 if (err)
2990 goto err_destroy_ch_tirs;
2991 }
2992
2993 kvfree(in);
2994
2995 return 0;
2996
2997 err_destroy_ch_tirs:
2998 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
2999 for (ix--; ix >= 0; ix--)
3000 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3001
3002 kvfree(in);
3003
3004 return err;
3005 }
3006
3007 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3008 {
3009 int i;
3010
3011 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3012 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3013
3014 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3015 return;
3016
3017 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3018 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3019 }
3020
3021 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3022 {
3023 int nch = priv->profile->max_nch(priv->mdev);
3024 int i;
3025
3026 for (i = 0; i < nch; i++)
3027 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3028 }
3029
3030 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3031 {
3032 int err = 0;
3033 int i;
3034
3035 for (i = 0; i < chs->num; i++) {
3036 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3037 if (err)
3038 return err;
3039 }
3040
3041 return 0;
3042 }
3043
3044 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3045 {
3046 int err = 0;
3047 int i;
3048
3049 for (i = 0; i < chs->num; i++) {
3050 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3051 if (err)
3052 return err;
3053 }
3054
3055 return 0;
3056 }
3057
3058 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3059 struct tc_mqprio_qopt *mqprio)
3060 {
3061 struct mlx5e_priv *priv = netdev_priv(netdev);
3062 struct mlx5e_channels new_channels = {};
3063 u8 tc = mqprio->num_tc;
3064 int err = 0;
3065
3066 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3067
3068 if (tc && tc != MLX5E_MAX_NUM_TC)
3069 return -EINVAL;
3070
3071 mutex_lock(&priv->state_lock);
3072
3073 new_channels.params = priv->channels.params;
3074 new_channels.params.num_tc = tc ? tc : 1;
3075
3076 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3077 priv->channels.params = new_channels.params;
3078 goto out;
3079 }
3080
3081 err = mlx5e_open_channels(priv, &new_channels);
3082 if (err)
3083 goto out;
3084
3085 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3086 out:
3087 mutex_unlock(&priv->state_lock);
3088 return err;
3089 }
3090
3091 #ifdef CONFIG_MLX5_ESWITCH
3092 static int mlx5e_setup_tc_cls_flower(struct net_device *dev,
3093 struct tc_cls_flower_offload *cls_flower)
3094 {
3095 struct mlx5e_priv *priv = netdev_priv(dev);
3096
3097 if (!is_classid_clsact_ingress(cls_flower->common.classid) ||
3098 cls_flower->common.chain_index)
3099 return -EOPNOTSUPP;
3100
3101 switch (cls_flower->command) {
3102 case TC_CLSFLOWER_REPLACE:
3103 return mlx5e_configure_flower(priv, cls_flower);
3104 case TC_CLSFLOWER_DESTROY:
3105 return mlx5e_delete_flower(priv, cls_flower);
3106 case TC_CLSFLOWER_STATS:
3107 return mlx5e_stats_flower(priv, cls_flower);
3108 default:
3109 return -EOPNOTSUPP;
3110 }
3111 }
3112 #endif
3113
3114 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3115 void *type_data)
3116 {
3117 switch (type) {
3118 #ifdef CONFIG_MLX5_ESWITCH
3119 case TC_SETUP_CLSFLOWER:
3120 return mlx5e_setup_tc_cls_flower(dev, type_data);
3121 #endif
3122 case TC_SETUP_MQPRIO:
3123 return mlx5e_setup_tc_mqprio(dev, type_data);
3124 default:
3125 return -EOPNOTSUPP;
3126 }
3127 }
3128
3129 static void
3130 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3131 {
3132 struct mlx5e_priv *priv = netdev_priv(dev);
3133 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3134 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3135 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3136
3137 if (mlx5e_is_uplink_rep(priv)) {
3138 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3139 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3140 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3141 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3142 } else {
3143 stats->rx_packets = sstats->rx_packets;
3144 stats->rx_bytes = sstats->rx_bytes;
3145 stats->tx_packets = sstats->tx_packets;
3146 stats->tx_bytes = sstats->tx_bytes;
3147 stats->tx_dropped = sstats->tx_queue_dropped;
3148 }
3149
3150 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3151
3152 stats->rx_length_errors =
3153 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3154 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3155 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3156 stats->rx_crc_errors =
3157 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3158 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3159 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3160 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3161 stats->rx_frame_errors;
3162 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3163
3164 /* vport multicast also counts packets that are dropped due to steering
3165 * or rx out of buffer
3166 */
3167 stats->multicast =
3168 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3169 }
3170
3171 static void mlx5e_set_rx_mode(struct net_device *dev)
3172 {
3173 struct mlx5e_priv *priv = netdev_priv(dev);
3174
3175 queue_work(priv->wq, &priv->set_rx_mode_work);
3176 }
3177
3178 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3179 {
3180 struct mlx5e_priv *priv = netdev_priv(netdev);
3181 struct sockaddr *saddr = addr;
3182
3183 if (!is_valid_ether_addr(saddr->sa_data))
3184 return -EADDRNOTAVAIL;
3185
3186 netif_addr_lock_bh(netdev);
3187 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3188 netif_addr_unlock_bh(netdev);
3189
3190 queue_work(priv->wq, &priv->set_rx_mode_work);
3191
3192 return 0;
3193 }
3194
3195 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
3196 do { \
3197 if (enable) \
3198 netdev->features |= feature; \
3199 else \
3200 netdev->features &= ~feature; \
3201 } while (0)
3202
3203 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3204
3205 static int set_feature_lro(struct net_device *netdev, bool enable)
3206 {
3207 struct mlx5e_priv *priv = netdev_priv(netdev);
3208 struct mlx5e_channels new_channels = {};
3209 int err = 0;
3210 bool reset;
3211
3212 mutex_lock(&priv->state_lock);
3213
3214 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3215 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3216
3217 new_channels.params = priv->channels.params;
3218 new_channels.params.lro_en = enable;
3219
3220 if (!reset) {
3221 priv->channels.params = new_channels.params;
3222 err = mlx5e_modify_tirs_lro(priv);
3223 goto out;
3224 }
3225
3226 err = mlx5e_open_channels(priv, &new_channels);
3227 if (err)
3228 goto out;
3229
3230 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3231 out:
3232 mutex_unlock(&priv->state_lock);
3233 return err;
3234 }
3235
3236 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3237 {
3238 struct mlx5e_priv *priv = netdev_priv(netdev);
3239
3240 if (enable)
3241 mlx5e_enable_vlan_filter(priv);
3242 else
3243 mlx5e_disable_vlan_filter(priv);
3244
3245 return 0;
3246 }
3247
3248 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3249 {
3250 struct mlx5e_priv *priv = netdev_priv(netdev);
3251
3252 if (!enable && mlx5e_tc_num_filters(priv)) {
3253 netdev_err(netdev,
3254 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3255 return -EINVAL;
3256 }
3257
3258 return 0;
3259 }
3260
3261 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3262 {
3263 struct mlx5e_priv *priv = netdev_priv(netdev);
3264 struct mlx5_core_dev *mdev = priv->mdev;
3265
3266 return mlx5_set_port_fcs(mdev, !enable);
3267 }
3268
3269 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3270 {
3271 struct mlx5e_priv *priv = netdev_priv(netdev);
3272 int err;
3273
3274 mutex_lock(&priv->state_lock);
3275
3276 priv->channels.params.scatter_fcs_en = enable;
3277 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3278 if (err)
3279 priv->channels.params.scatter_fcs_en = !enable;
3280
3281 mutex_unlock(&priv->state_lock);
3282
3283 return err;
3284 }
3285
3286 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3287 {
3288 struct mlx5e_priv *priv = netdev_priv(netdev);
3289 int err = 0;
3290
3291 mutex_lock(&priv->state_lock);
3292
3293 priv->channels.params.vlan_strip_disable = !enable;
3294 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3295 goto unlock;
3296
3297 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3298 if (err)
3299 priv->channels.params.vlan_strip_disable = enable;
3300
3301 unlock:
3302 mutex_unlock(&priv->state_lock);
3303
3304 return err;
3305 }
3306
3307 #ifdef CONFIG_RFS_ACCEL
3308 static int set_feature_arfs(struct net_device *netdev, bool enable)
3309 {
3310 struct mlx5e_priv *priv = netdev_priv(netdev);
3311 int err;
3312
3313 if (enable)
3314 err = mlx5e_arfs_enable(priv);
3315 else
3316 err = mlx5e_arfs_disable(priv);
3317
3318 return err;
3319 }
3320 #endif
3321
3322 static int mlx5e_handle_feature(struct net_device *netdev,
3323 netdev_features_t wanted_features,
3324 netdev_features_t feature,
3325 mlx5e_feature_handler feature_handler)
3326 {
3327 netdev_features_t changes = wanted_features ^ netdev->features;
3328 bool enable = !!(wanted_features & feature);
3329 int err;
3330
3331 if (!(changes & feature))
3332 return 0;
3333
3334 err = feature_handler(netdev, enable);
3335 if (err) {
3336 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
3337 enable ? "Enable" : "Disable", feature, err);
3338 return err;
3339 }
3340
3341 MLX5E_SET_FEATURE(netdev, feature, enable);
3342 return 0;
3343 }
3344
3345 static int mlx5e_set_features(struct net_device *netdev,
3346 netdev_features_t features)
3347 {
3348 int err;
3349
3350 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3351 set_feature_lro);
3352 err |= mlx5e_handle_feature(netdev, features,
3353 NETIF_F_HW_VLAN_CTAG_FILTER,
3354 set_feature_vlan_filter);
3355 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3356 set_feature_tc_num_filters);
3357 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3358 set_feature_rx_all);
3359 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3360 set_feature_rx_fcs);
3361 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3362 set_feature_rx_vlan);
3363 #ifdef CONFIG_RFS_ACCEL
3364 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3365 set_feature_arfs);
3366 #endif
3367
3368 return err ? -EINVAL : 0;
3369 }
3370
3371 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3372 {
3373 struct mlx5e_priv *priv = netdev_priv(netdev);
3374 struct mlx5e_channels new_channels = {};
3375 int curr_mtu;
3376 int err = 0;
3377 bool reset;
3378
3379 mutex_lock(&priv->state_lock);
3380
3381 reset = !priv->channels.params.lro_en &&
3382 (priv->channels.params.rq_wq_type !=
3383 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3384
3385 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3386
3387 curr_mtu = netdev->mtu;
3388 netdev->mtu = new_mtu;
3389
3390 if (!reset) {
3391 mlx5e_set_dev_port_mtu(priv);
3392 goto out;
3393 }
3394
3395 new_channels.params = priv->channels.params;
3396 err = mlx5e_open_channels(priv, &new_channels);
3397 if (err) {
3398 netdev->mtu = curr_mtu;
3399 goto out;
3400 }
3401
3402 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3403
3404 out:
3405 mutex_unlock(&priv->state_lock);
3406 return err;
3407 }
3408
3409 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3410 {
3411 struct mlx5e_priv *priv = netdev_priv(dev);
3412
3413 switch (cmd) {
3414 case SIOCSHWTSTAMP:
3415 return mlx5e_hwstamp_set(priv, ifr);
3416 case SIOCGHWTSTAMP:
3417 return mlx5e_hwstamp_get(priv, ifr);
3418 default:
3419 return -EOPNOTSUPP;
3420 }
3421 }
3422
3423 #ifdef CONFIG_MLX5_ESWITCH
3424 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3425 {
3426 struct mlx5e_priv *priv = netdev_priv(dev);
3427 struct mlx5_core_dev *mdev = priv->mdev;
3428
3429 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3430 }
3431
3432 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3433 __be16 vlan_proto)
3434 {
3435 struct mlx5e_priv *priv = netdev_priv(dev);
3436 struct mlx5_core_dev *mdev = priv->mdev;
3437
3438 if (vlan_proto != htons(ETH_P_8021Q))
3439 return -EPROTONOSUPPORT;
3440
3441 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3442 vlan, qos);
3443 }
3444
3445 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3446 {
3447 struct mlx5e_priv *priv = netdev_priv(dev);
3448 struct mlx5_core_dev *mdev = priv->mdev;
3449
3450 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3451 }
3452
3453 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3454 {
3455 struct mlx5e_priv *priv = netdev_priv(dev);
3456 struct mlx5_core_dev *mdev = priv->mdev;
3457
3458 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3459 }
3460
3461 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3462 int max_tx_rate)
3463 {
3464 struct mlx5e_priv *priv = netdev_priv(dev);
3465 struct mlx5_core_dev *mdev = priv->mdev;
3466
3467 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3468 max_tx_rate, min_tx_rate);
3469 }
3470
3471 static int mlx5_vport_link2ifla(u8 esw_link)
3472 {
3473 switch (esw_link) {
3474 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3475 return IFLA_VF_LINK_STATE_DISABLE;
3476 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3477 return IFLA_VF_LINK_STATE_ENABLE;
3478 }
3479 return IFLA_VF_LINK_STATE_AUTO;
3480 }
3481
3482 static int mlx5_ifla_link2vport(u8 ifla_link)
3483 {
3484 switch (ifla_link) {
3485 case IFLA_VF_LINK_STATE_DISABLE:
3486 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3487 case IFLA_VF_LINK_STATE_ENABLE:
3488 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3489 }
3490 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3491 }
3492
3493 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3494 int link_state)
3495 {
3496 struct mlx5e_priv *priv = netdev_priv(dev);
3497 struct mlx5_core_dev *mdev = priv->mdev;
3498
3499 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3500 mlx5_ifla_link2vport(link_state));
3501 }
3502
3503 static int mlx5e_get_vf_config(struct net_device *dev,
3504 int vf, struct ifla_vf_info *ivi)
3505 {
3506 struct mlx5e_priv *priv = netdev_priv(dev);
3507 struct mlx5_core_dev *mdev = priv->mdev;
3508 int err;
3509
3510 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3511 if (err)
3512 return err;
3513 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3514 return 0;
3515 }
3516
3517 static int mlx5e_get_vf_stats(struct net_device *dev,
3518 int vf, struct ifla_vf_stats *vf_stats)
3519 {
3520 struct mlx5e_priv *priv = netdev_priv(dev);
3521 struct mlx5_core_dev *mdev = priv->mdev;
3522
3523 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3524 vf_stats);
3525 }
3526 #endif
3527
3528 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3529 struct udp_tunnel_info *ti)
3530 {
3531 struct mlx5e_priv *priv = netdev_priv(netdev);
3532
3533 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3534 return;
3535
3536 if (!mlx5e_vxlan_allowed(priv->mdev))
3537 return;
3538
3539 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3540 }
3541
3542 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3543 struct udp_tunnel_info *ti)
3544 {
3545 struct mlx5e_priv *priv = netdev_priv(netdev);
3546
3547 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3548 return;
3549
3550 if (!mlx5e_vxlan_allowed(priv->mdev))
3551 return;
3552
3553 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3554 }
3555
3556 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3557 struct sk_buff *skb,
3558 netdev_features_t features)
3559 {
3560 struct udphdr *udph;
3561 u8 proto;
3562 u16 port;
3563
3564 switch (vlan_get_protocol(skb)) {
3565 case htons(ETH_P_IP):
3566 proto = ip_hdr(skb)->protocol;
3567 break;
3568 case htons(ETH_P_IPV6):
3569 proto = ipv6_hdr(skb)->nexthdr;
3570 break;
3571 default:
3572 goto out;
3573 }
3574
3575 switch (proto) {
3576 case IPPROTO_GRE:
3577 return features;
3578 case IPPROTO_UDP:
3579 udph = udp_hdr(skb);
3580 port = be16_to_cpu(udph->dest);
3581
3582 /* Verify if UDP port is being offloaded by HW */
3583 if (mlx5e_vxlan_lookup_port(priv, port))
3584 return features;
3585 }
3586
3587 out:
3588 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3589 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3590 }
3591
3592 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3593 struct net_device *netdev,
3594 netdev_features_t features)
3595 {
3596 struct mlx5e_priv *priv = netdev_priv(netdev);
3597
3598 features = vlan_features_check(skb, features);
3599 features = vxlan_features_check(skb, features);
3600
3601 #ifdef CONFIG_MLX5_EN_IPSEC
3602 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3603 return features;
3604 #endif
3605
3606 /* Validate if the tunneled packet is being offloaded by HW */
3607 if (skb->encapsulation &&
3608 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3609 return mlx5e_tunnel_features_check(priv, skb, features);
3610
3611 return features;
3612 }
3613
3614 static void mlx5e_tx_timeout(struct net_device *dev)
3615 {
3616 struct mlx5e_priv *priv = netdev_priv(dev);
3617 bool sched_work = false;
3618 int i;
3619
3620 netdev_err(dev, "TX timeout detected\n");
3621
3622 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3623 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3624
3625 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3626 continue;
3627 sched_work = true;
3628 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3629 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3630 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3631 }
3632
3633 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3634 schedule_work(&priv->tx_timeout_work);
3635 }
3636
3637 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3638 {
3639 struct mlx5e_priv *priv = netdev_priv(netdev);
3640 struct bpf_prog *old_prog;
3641 int err = 0;
3642 bool reset, was_opened;
3643 int i;
3644
3645 mutex_lock(&priv->state_lock);
3646
3647 if ((netdev->features & NETIF_F_LRO) && prog) {
3648 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3649 err = -EINVAL;
3650 goto unlock;
3651 }
3652
3653 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3654 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3655 err = -EINVAL;
3656 goto unlock;
3657 }
3658
3659 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3660 /* no need for full reset when exchanging programs */
3661 reset = (!priv->channels.params.xdp_prog || !prog);
3662
3663 if (was_opened && reset)
3664 mlx5e_close_locked(netdev);
3665 if (was_opened && !reset) {
3666 /* num_channels is invariant here, so we can take the
3667 * batched reference right upfront.
3668 */
3669 prog = bpf_prog_add(prog, priv->channels.num);
3670 if (IS_ERR(prog)) {
3671 err = PTR_ERR(prog);
3672 goto unlock;
3673 }
3674 }
3675
3676 /* exchange programs, extra prog reference we got from caller
3677 * as long as we don't fail from this point onwards.
3678 */
3679 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3680 if (old_prog)
3681 bpf_prog_put(old_prog);
3682
3683 if (reset) /* change RQ type according to priv->xdp_prog */
3684 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
3685
3686 if (was_opened && reset)
3687 mlx5e_open_locked(netdev);
3688
3689 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3690 goto unlock;
3691
3692 /* exchanging programs w/o reset, we update ref counts on behalf
3693 * of the channels RQs here.
3694 */
3695 for (i = 0; i < priv->channels.num; i++) {
3696 struct mlx5e_channel *c = priv->channels.c[i];
3697
3698 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3699 napi_synchronize(&c->napi);
3700 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3701
3702 old_prog = xchg(&c->rq.xdp_prog, prog);
3703
3704 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3705 /* napi_schedule in case we have missed anything */
3706 napi_schedule(&c->napi);
3707
3708 if (old_prog)
3709 bpf_prog_put(old_prog);
3710 }
3711
3712 unlock:
3713 mutex_unlock(&priv->state_lock);
3714 return err;
3715 }
3716
3717 static u32 mlx5e_xdp_query(struct net_device *dev)
3718 {
3719 struct mlx5e_priv *priv = netdev_priv(dev);
3720 const struct bpf_prog *xdp_prog;
3721 u32 prog_id = 0;
3722
3723 mutex_lock(&priv->state_lock);
3724 xdp_prog = priv->channels.params.xdp_prog;
3725 if (xdp_prog)
3726 prog_id = xdp_prog->aux->id;
3727 mutex_unlock(&priv->state_lock);
3728
3729 return prog_id;
3730 }
3731
3732 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3733 {
3734 switch (xdp->command) {
3735 case XDP_SETUP_PROG:
3736 return mlx5e_xdp_set(dev, xdp->prog);
3737 case XDP_QUERY_PROG:
3738 xdp->prog_id = mlx5e_xdp_query(dev);
3739 xdp->prog_attached = !!xdp->prog_id;
3740 return 0;
3741 default:
3742 return -EINVAL;
3743 }
3744 }
3745
3746 #ifdef CONFIG_NET_POLL_CONTROLLER
3747 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3748 * reenabling interrupts.
3749 */
3750 static void mlx5e_netpoll(struct net_device *dev)
3751 {
3752 struct mlx5e_priv *priv = netdev_priv(dev);
3753 struct mlx5e_channels *chs = &priv->channels;
3754
3755 int i;
3756
3757 for (i = 0; i < chs->num; i++)
3758 napi_schedule(&chs->c[i]->napi);
3759 }
3760 #endif
3761
3762 static const struct net_device_ops mlx5e_netdev_ops = {
3763 .ndo_open = mlx5e_open,
3764 .ndo_stop = mlx5e_close,
3765 .ndo_start_xmit = mlx5e_xmit,
3766 .ndo_setup_tc = mlx5e_setup_tc,
3767 .ndo_select_queue = mlx5e_select_queue,
3768 .ndo_get_stats64 = mlx5e_get_stats,
3769 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3770 .ndo_set_mac_address = mlx5e_set_mac,
3771 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3772 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3773 .ndo_set_features = mlx5e_set_features,
3774 .ndo_change_mtu = mlx5e_change_mtu,
3775 .ndo_do_ioctl = mlx5e_ioctl,
3776 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3777 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3778 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3779 .ndo_features_check = mlx5e_features_check,
3780 #ifdef CONFIG_RFS_ACCEL
3781 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3782 #endif
3783 .ndo_tx_timeout = mlx5e_tx_timeout,
3784 .ndo_xdp = mlx5e_xdp,
3785 #ifdef CONFIG_NET_POLL_CONTROLLER
3786 .ndo_poll_controller = mlx5e_netpoll,
3787 #endif
3788 #ifdef CONFIG_MLX5_ESWITCH
3789 /* SRIOV E-Switch NDOs */
3790 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3791 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
3792 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
3793 .ndo_set_vf_trust = mlx5e_set_vf_trust,
3794 .ndo_set_vf_rate = mlx5e_set_vf_rate,
3795 .ndo_get_vf_config = mlx5e_get_vf_config,
3796 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3797 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3798 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3799 .ndo_get_offload_stats = mlx5e_get_offload_stats,
3800 #endif
3801 };
3802
3803 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3804 {
3805 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3806 return -EOPNOTSUPP;
3807 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3808 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3809 !MLX5_CAP_ETH(mdev, csum_cap) ||
3810 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3811 !MLX5_CAP_ETH(mdev, vlan_cap) ||
3812 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3813 MLX5_CAP_FLOWTABLE(mdev,
3814 flow_table_properties_nic_receive.max_ft_level)
3815 < 3) {
3816 mlx5_core_warn(mdev,
3817 "Not creating net device, some required device capabilities are missing\n");
3818 return -EOPNOTSUPP;
3819 }
3820 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3821 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3822 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3823 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
3824
3825 return 0;
3826 }
3827
3828 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3829 {
3830 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3831
3832 return bf_buf_size -
3833 sizeof(struct mlx5e_tx_wqe) +
3834 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3835 }
3836
3837 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
3838 int num_channels)
3839 {
3840 int i;
3841
3842 for (i = 0; i < len; i++)
3843 indirection_rqt[i] = i % num_channels;
3844 }
3845
3846 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3847 {
3848 enum pcie_link_width width;
3849 enum pci_bus_speed speed;
3850 int err = 0;
3851
3852 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3853 if (err)
3854 return err;
3855
3856 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3857 return -EINVAL;
3858
3859 switch (speed) {
3860 case PCIE_SPEED_2_5GT:
3861 *pci_bw = 2500 * width;
3862 break;
3863 case PCIE_SPEED_5_0GT:
3864 *pci_bw = 5000 * width;
3865 break;
3866 case PCIE_SPEED_8_0GT:
3867 *pci_bw = 8000 * width;
3868 break;
3869 default:
3870 return -EINVAL;
3871 }
3872
3873 return 0;
3874 }
3875
3876 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3877 {
3878 return (link_speed && pci_bw &&
3879 (pci_bw < 40000) && (pci_bw < link_speed));
3880 }
3881
3882 static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
3883 {
3884 return !(link_speed && pci_bw &&
3885 (pci_bw <= 16000) && (pci_bw < link_speed));
3886 }
3887
3888 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3889 {
3890 params->rx_cq_period_mode = cq_period_mode;
3891
3892 params->rx_cq_moderation.pkts =
3893 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3894 params->rx_cq_moderation.usec =
3895 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3896
3897 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3898 params->rx_cq_moderation.usec =
3899 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3900
3901 if (params->rx_am_enabled)
3902 params->rx_cq_moderation =
3903 mlx5e_am_get_def_profile(params->rx_cq_period_mode);
3904
3905 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3906 params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3907 }
3908
3909 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3910 {
3911 int i;
3912
3913 /* The supported periods are organized in ascending order */
3914 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3915 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3916 break;
3917
3918 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3919 }
3920
3921 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3922 struct mlx5e_params *params,
3923 u16 max_channels)
3924 {
3925 u8 cq_period_mode = 0;
3926 u32 link_speed = 0;
3927 u32 pci_bw = 0;
3928
3929 params->num_channels = max_channels;
3930 params->num_tc = 1;
3931
3932 mlx5e_get_max_linkspeed(mdev, &link_speed);
3933 mlx5e_get_pci_bw(mdev, &pci_bw);
3934 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3935 link_speed, pci_bw);
3936
3937 /* SQ */
3938 params->log_sq_size = is_kdump_kernel() ?
3939 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3940 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3941
3942 /* set CQE compression */
3943 params->rx_cqe_compress_def = false;
3944 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3945 MLX5_CAP_GEN(mdev, vport_group_manager))
3946 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
3947
3948 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3949
3950 /* RQ */
3951 mlx5e_set_rq_params(mdev, params);
3952
3953 /* HW LRO */
3954
3955 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
3956 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3957 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
3958 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3959
3960 /* CQ moderation params */
3961 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3962 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3963 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3964 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3965 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
3966
3967 params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3968 params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3969
3970 /* TX inline */
3971 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3972 mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
3973 if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
3974 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
3975 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
3976
3977 /* RSS */
3978 params->rss_hfunc = ETH_RSS_HASH_XOR;
3979 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3980 mlx5e_build_default_indir_rqt(params->indirection_rqt,
3981 MLX5E_INDIR_RQT_SIZE, max_channels);
3982 }
3983
3984 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3985 struct net_device *netdev,
3986 const struct mlx5e_profile *profile,
3987 void *ppriv)
3988 {
3989 struct mlx5e_priv *priv = netdev_priv(netdev);
3990
3991 priv->mdev = mdev;
3992 priv->netdev = netdev;
3993 priv->profile = profile;
3994 priv->ppriv = ppriv;
3995 priv->hard_mtu = MLX5E_ETH_HARD_MTU;
3996
3997 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
3998
3999 mutex_init(&priv->state_lock);
4000
4001 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4002 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4003 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4004 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4005 }
4006
4007 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4008 {
4009 struct mlx5e_priv *priv = netdev_priv(netdev);
4010
4011 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4012 if (is_zero_ether_addr(netdev->dev_addr) &&
4013 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4014 eth_hw_addr_random(netdev);
4015 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4016 }
4017 }
4018
4019 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4020 static const struct switchdev_ops mlx5e_switchdev_ops = {
4021 .switchdev_port_attr_get = mlx5e_attr_get,
4022 };
4023 #endif
4024
4025 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4026 {
4027 struct mlx5e_priv *priv = netdev_priv(netdev);
4028 struct mlx5_core_dev *mdev = priv->mdev;
4029 bool fcs_supported;
4030 bool fcs_enabled;
4031
4032 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4033
4034 netdev->netdev_ops = &mlx5e_netdev_ops;
4035
4036 #ifdef CONFIG_MLX5_CORE_EN_DCB
4037 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4038 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4039 #endif
4040
4041 netdev->watchdog_timeo = 15 * HZ;
4042
4043 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4044
4045 netdev->vlan_features |= NETIF_F_SG;
4046 netdev->vlan_features |= NETIF_F_IP_CSUM;
4047 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4048 netdev->vlan_features |= NETIF_F_GRO;
4049 netdev->vlan_features |= NETIF_F_TSO;
4050 netdev->vlan_features |= NETIF_F_TSO6;
4051 netdev->vlan_features |= NETIF_F_RXCSUM;
4052 netdev->vlan_features |= NETIF_F_RXHASH;
4053
4054 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4055 netdev->vlan_features |= NETIF_F_LRO;
4056
4057 netdev->hw_features = netdev->vlan_features;
4058 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4059 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4060 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4061
4062 if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4063 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4064 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4065 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4066 netdev->hw_enc_features |= NETIF_F_TSO;
4067 netdev->hw_enc_features |= NETIF_F_TSO6;
4068 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4069 }
4070
4071 if (mlx5e_vxlan_allowed(mdev)) {
4072 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4073 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4074 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4075 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4076 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4077 }
4078
4079 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4080 netdev->hw_features |= NETIF_F_GSO_GRE |
4081 NETIF_F_GSO_GRE_CSUM;
4082 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4083 NETIF_F_GSO_GRE_CSUM;
4084 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4085 NETIF_F_GSO_GRE_CSUM;
4086 }
4087
4088 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4089
4090 if (fcs_supported)
4091 netdev->hw_features |= NETIF_F_RXALL;
4092
4093 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4094 netdev->hw_features |= NETIF_F_RXFCS;
4095
4096 netdev->features = netdev->hw_features;
4097 if (!priv->channels.params.lro_en)
4098 netdev->features &= ~NETIF_F_LRO;
4099
4100 if (fcs_enabled)
4101 netdev->features &= ~NETIF_F_RXALL;
4102
4103 if (!priv->channels.params.scatter_fcs_en)
4104 netdev->features &= ~NETIF_F_RXFCS;
4105
4106 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4107 if (FT_CAP(flow_modify_en) &&
4108 FT_CAP(modify_root) &&
4109 FT_CAP(identified_miss_table_mode) &&
4110 FT_CAP(flow_table_modify)) {
4111 netdev->hw_features |= NETIF_F_HW_TC;
4112 #ifdef CONFIG_RFS_ACCEL
4113 netdev->hw_features |= NETIF_F_NTUPLE;
4114 #endif
4115 }
4116
4117 netdev->features |= NETIF_F_HIGHDMA;
4118
4119 netdev->priv_flags |= IFF_UNICAST_FLT;
4120
4121 mlx5e_set_netdev_dev_addr(netdev);
4122
4123 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4124 if (MLX5_VPORT_MANAGER(mdev))
4125 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4126 #endif
4127
4128 mlx5e_ipsec_build_netdev(priv);
4129 }
4130
4131 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4132 {
4133 struct mlx5_core_dev *mdev = priv->mdev;
4134 int err;
4135
4136 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4137 if (err) {
4138 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4139 priv->q_counter = 0;
4140 }
4141 }
4142
4143 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4144 {
4145 if (!priv->q_counter)
4146 return;
4147
4148 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4149 }
4150
4151 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4152 struct net_device *netdev,
4153 const struct mlx5e_profile *profile,
4154 void *ppriv)
4155 {
4156 struct mlx5e_priv *priv = netdev_priv(netdev);
4157 int err;
4158
4159 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4160 err = mlx5e_ipsec_init(priv);
4161 if (err)
4162 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4163 mlx5e_build_nic_netdev(netdev);
4164 mlx5e_vxlan_init(priv);
4165 }
4166
4167 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4168 {
4169 mlx5e_ipsec_cleanup(priv);
4170 mlx5e_vxlan_cleanup(priv);
4171
4172 if (priv->channels.params.xdp_prog)
4173 bpf_prog_put(priv->channels.params.xdp_prog);
4174 }
4175
4176 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4177 {
4178 struct mlx5_core_dev *mdev = priv->mdev;
4179 int err;
4180
4181 err = mlx5e_create_indirect_rqt(priv);
4182 if (err)
4183 return err;
4184
4185 err = mlx5e_create_direct_rqts(priv);
4186 if (err)
4187 goto err_destroy_indirect_rqts;
4188
4189 err = mlx5e_create_indirect_tirs(priv);
4190 if (err)
4191 goto err_destroy_direct_rqts;
4192
4193 err = mlx5e_create_direct_tirs(priv);
4194 if (err)
4195 goto err_destroy_indirect_tirs;
4196
4197 err = mlx5e_create_flow_steering(priv);
4198 if (err) {
4199 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4200 goto err_destroy_direct_tirs;
4201 }
4202
4203 err = mlx5e_tc_init(priv);
4204 if (err)
4205 goto err_destroy_flow_steering;
4206
4207 return 0;
4208
4209 err_destroy_flow_steering:
4210 mlx5e_destroy_flow_steering(priv);
4211 err_destroy_direct_tirs:
4212 mlx5e_destroy_direct_tirs(priv);
4213 err_destroy_indirect_tirs:
4214 mlx5e_destroy_indirect_tirs(priv);
4215 err_destroy_direct_rqts:
4216 mlx5e_destroy_direct_rqts(priv);
4217 err_destroy_indirect_rqts:
4218 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4219 return err;
4220 }
4221
4222 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4223 {
4224 mlx5e_tc_cleanup(priv);
4225 mlx5e_destroy_flow_steering(priv);
4226 mlx5e_destroy_direct_tirs(priv);
4227 mlx5e_destroy_indirect_tirs(priv);
4228 mlx5e_destroy_direct_rqts(priv);
4229 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4230 }
4231
4232 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4233 {
4234 int err;
4235
4236 err = mlx5e_create_tises(priv);
4237 if (err) {
4238 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4239 return err;
4240 }
4241
4242 #ifdef CONFIG_MLX5_CORE_EN_DCB
4243 mlx5e_dcbnl_initialize(priv);
4244 #endif
4245 return 0;
4246 }
4247
4248 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4249 {
4250 struct net_device *netdev = priv->netdev;
4251 struct mlx5_core_dev *mdev = priv->mdev;
4252 u16 max_mtu;
4253
4254 mlx5e_init_l2_addr(priv);
4255
4256 /* Marking the link as currently not needed by the Driver */
4257 if (!netif_running(netdev))
4258 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4259
4260 /* MTU range: 68 - hw-specific max */
4261 netdev->min_mtu = ETH_MIN_MTU;
4262 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4263 netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
4264 mlx5e_set_dev_port_mtu(priv);
4265
4266 mlx5_lag_add(mdev, netdev);
4267
4268 mlx5e_enable_async_events(priv);
4269
4270 if (MLX5_VPORT_MANAGER(priv->mdev))
4271 mlx5e_register_vport_reps(priv);
4272
4273 if (netdev->reg_state != NETREG_REGISTERED)
4274 return;
4275
4276 /* Device already registered: sync netdev system state */
4277 if (mlx5e_vxlan_allowed(mdev)) {
4278 rtnl_lock();
4279 udp_tunnel_get_rx_info(netdev);
4280 rtnl_unlock();
4281 }
4282
4283 queue_work(priv->wq, &priv->set_rx_mode_work);
4284
4285 rtnl_lock();
4286 if (netif_running(netdev))
4287 mlx5e_open(netdev);
4288 netif_device_attach(netdev);
4289 rtnl_unlock();
4290 }
4291
4292 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4293 {
4294 struct mlx5_core_dev *mdev = priv->mdev;
4295
4296 rtnl_lock();
4297 if (netif_running(priv->netdev))
4298 mlx5e_close(priv->netdev);
4299 netif_device_detach(priv->netdev);
4300 rtnl_unlock();
4301
4302 queue_work(priv->wq, &priv->set_rx_mode_work);
4303
4304 if (MLX5_VPORT_MANAGER(priv->mdev))
4305 mlx5e_unregister_vport_reps(priv);
4306
4307 mlx5e_disable_async_events(priv);
4308 mlx5_lag_remove(mdev);
4309 }
4310
4311 static const struct mlx5e_profile mlx5e_nic_profile = {
4312 .init = mlx5e_nic_init,
4313 .cleanup = mlx5e_nic_cleanup,
4314 .init_rx = mlx5e_init_nic_rx,
4315 .cleanup_rx = mlx5e_cleanup_nic_rx,
4316 .init_tx = mlx5e_init_nic_tx,
4317 .cleanup_tx = mlx5e_cleanup_nic_tx,
4318 .enable = mlx5e_nic_enable,
4319 .disable = mlx5e_nic_disable,
4320 .update_stats = mlx5e_update_ndo_stats,
4321 .max_nch = mlx5e_get_max_num_channels,
4322 .update_carrier = mlx5e_update_carrier,
4323 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4324 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4325 .max_tc = MLX5E_MAX_NUM_TC,
4326 };
4327
4328 /* mlx5e generic netdev management API (move to en_common.c) */
4329
4330 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4331 const struct mlx5e_profile *profile,
4332 void *ppriv)
4333 {
4334 int nch = profile->max_nch(mdev);
4335 struct net_device *netdev;
4336 struct mlx5e_priv *priv;
4337
4338 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4339 nch * profile->max_tc,
4340 nch);
4341 if (!netdev) {
4342 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4343 return NULL;
4344 }
4345
4346 #ifdef CONFIG_RFS_ACCEL
4347 netdev->rx_cpu_rmap = mdev->rmap;
4348 #endif
4349
4350 profile->init(mdev, netdev, profile, ppriv);
4351
4352 netif_carrier_off(netdev);
4353
4354 priv = netdev_priv(netdev);
4355
4356 priv->wq = create_singlethread_workqueue("mlx5e");
4357 if (!priv->wq)
4358 goto err_cleanup_nic;
4359
4360 return netdev;
4361
4362 err_cleanup_nic:
4363 if (profile->cleanup)
4364 profile->cleanup(priv);
4365 free_netdev(netdev);
4366
4367 return NULL;
4368 }
4369
4370 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4371 {
4372 struct mlx5_core_dev *mdev = priv->mdev;
4373 const struct mlx5e_profile *profile;
4374 int err;
4375
4376 profile = priv->profile;
4377 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4378
4379 err = profile->init_tx(priv);
4380 if (err)
4381 goto out;
4382
4383 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
4384 if (err) {
4385 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4386 goto err_cleanup_tx;
4387 }
4388
4389 err = profile->init_rx(priv);
4390 if (err)
4391 goto err_close_drop_rq;
4392
4393 mlx5e_create_q_counter(priv);
4394
4395 if (profile->enable)
4396 profile->enable(priv);
4397
4398 return 0;
4399
4400 err_close_drop_rq:
4401 mlx5e_close_drop_rq(&priv->drop_rq);
4402
4403 err_cleanup_tx:
4404 profile->cleanup_tx(priv);
4405
4406 out:
4407 return err;
4408 }
4409
4410 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4411 {
4412 const struct mlx5e_profile *profile = priv->profile;
4413
4414 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4415
4416 if (profile->disable)
4417 profile->disable(priv);
4418 flush_workqueue(priv->wq);
4419
4420 mlx5e_destroy_q_counter(priv);
4421 profile->cleanup_rx(priv);
4422 mlx5e_close_drop_rq(&priv->drop_rq);
4423 profile->cleanup_tx(priv);
4424 cancel_delayed_work_sync(&priv->update_stats_work);
4425 }
4426
4427 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4428 {
4429 const struct mlx5e_profile *profile = priv->profile;
4430 struct net_device *netdev = priv->netdev;
4431
4432 destroy_workqueue(priv->wq);
4433 if (profile->cleanup)
4434 profile->cleanup(priv);
4435 free_netdev(netdev);
4436 }
4437
4438 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4439 * hardware contexts and to connect it to the current netdev.
4440 */
4441 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4442 {
4443 struct mlx5e_priv *priv = vpriv;
4444 struct net_device *netdev = priv->netdev;
4445 int err;
4446
4447 if (netif_device_present(netdev))
4448 return 0;
4449
4450 err = mlx5e_create_mdev_resources(mdev);
4451 if (err)
4452 return err;
4453
4454 err = mlx5e_attach_netdev(priv);
4455 if (err) {
4456 mlx5e_destroy_mdev_resources(mdev);
4457 return err;
4458 }
4459
4460 return 0;
4461 }
4462
4463 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4464 {
4465 struct mlx5e_priv *priv = vpriv;
4466 struct net_device *netdev = priv->netdev;
4467
4468 if (!netif_device_present(netdev))
4469 return;
4470
4471 mlx5e_detach_netdev(priv);
4472 mlx5e_destroy_mdev_resources(mdev);
4473 }
4474
4475 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4476 {
4477 struct net_device *netdev;
4478 void *rpriv = NULL;
4479 void *priv;
4480 int err;
4481
4482 err = mlx5e_check_required_hca_cap(mdev);
4483 if (err)
4484 return NULL;
4485
4486 #ifdef CONFIG_MLX5_ESWITCH
4487 if (MLX5_VPORT_MANAGER(mdev)) {
4488 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4489 if (!rpriv) {
4490 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4491 return NULL;
4492 }
4493 }
4494 #endif
4495
4496 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4497 if (!netdev) {
4498 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4499 goto err_free_rpriv;
4500 }
4501
4502 priv = netdev_priv(netdev);
4503
4504 err = mlx5e_attach(mdev, priv);
4505 if (err) {
4506 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4507 goto err_destroy_netdev;
4508 }
4509
4510 err = register_netdev(netdev);
4511 if (err) {
4512 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4513 goto err_detach;
4514 }
4515
4516 return priv;
4517
4518 err_detach:
4519 mlx5e_detach(mdev, priv);
4520 err_destroy_netdev:
4521 mlx5e_destroy_netdev(priv);
4522 err_free_rpriv:
4523 kfree(rpriv);
4524 return NULL;
4525 }
4526
4527 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4528 {
4529 struct mlx5e_priv *priv = vpriv;
4530 void *ppriv = priv->ppriv;
4531
4532 unregister_netdev(priv->netdev);
4533 mlx5e_detach(mdev, vpriv);
4534 mlx5e_destroy_netdev(priv);
4535 kfree(ppriv);
4536 }
4537
4538 static void *mlx5e_get_netdev(void *vpriv)
4539 {
4540 struct mlx5e_priv *priv = vpriv;
4541
4542 return priv->netdev;
4543 }
4544
4545 static struct mlx5_interface mlx5e_interface = {
4546 .add = mlx5e_add,
4547 .remove = mlx5e_remove,
4548 .attach = mlx5e_attach,
4549 .detach = mlx5e_detach,
4550 .event = mlx5e_async_event,
4551 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4552 .get_dev = mlx5e_get_netdev,
4553 };
4554
4555 void mlx5e_init(void)
4556 {
4557 mlx5e_ipsec_build_inverse_table();
4558 mlx5e_build_ptys2ethtool_map();
4559 mlx5_register_interface(&mlx5e_interface);
4560 }
4561
4562 void mlx5e_cleanup(void)
4563 {
4564 mlx5_unregister_interface(&mlx5e_interface);
4565 }
ubuntu-bionic-kernel mirror