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Merge remote-tracking branch 'regulator/fix/max77802' into regulator-linus
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_rx.c
1 /*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/prefetch.h>
34 #include <linux/ip.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/bpf_trace.h>
38 #include <net/busy_poll.h>
39 #include "en.h"
40 #include "en_tc.h"
41 #include "eswitch.h"
42 #include "en_rep.h"
43 #include "ipoib.h"
44
45 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
46 {
47 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
48 }
49
50 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
51 void *data)
52 {
53 u32 ci = cqcc & cq->wq.sz_m1;
54
55 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
56 }
57
58 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
59 struct mlx5e_cq *cq, u32 cqcc)
60 {
61 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
62 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
63 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
64 rq->stats.cqe_compress_blks++;
65 }
66
67 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
68 {
69 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
70 cq->mini_arr_idx = 0;
71 }
72
73 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
74 {
75 u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
76 u32 wq_sz = 1 << cq->wq.log_sz;
77 u32 ci = cqcc & cq->wq.sz_m1;
78 u32 ci_top = min_t(u32, wq_sz, ci + n);
79
80 for (; ci < ci_top; ci++, n--) {
81 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
82
83 cqe->op_own = op_own;
84 }
85
86 if (unlikely(ci == wq_sz)) {
87 op_own = !op_own;
88 for (ci = 0; ci < n; ci++) {
89 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
90
91 cqe->op_own = op_own;
92 }
93 }
94 }
95
96 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
97 struct mlx5e_cq *cq, u32 cqcc)
98 {
99 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
100 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
101 cq->title.op_own &= 0xf0;
102 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz);
103 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
104
105 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
106 cq->decmprs_wqe_counter +=
107 mpwrq_get_cqe_consumed_strides(&cq->title);
108 else
109 cq->decmprs_wqe_counter =
110 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1;
111 }
112
113 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
114 struct mlx5e_cq *cq, u32 cqcc)
115 {
116 mlx5e_decompress_cqe(rq, cq, cqcc);
117 cq->title.rss_hash_type = 0;
118 cq->title.rss_hash_result = 0;
119 }
120
121 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
122 struct mlx5e_cq *cq,
123 int update_owner_only,
124 int budget_rem)
125 {
126 u32 cqcc = cq->wq.cc + update_owner_only;
127 u32 cqe_count;
128 u32 i;
129
130 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
131
132 for (i = update_owner_only; i < cqe_count;
133 i++, cq->mini_arr_idx++, cqcc++) {
134 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
135 mlx5e_read_mini_arr_slot(cq, cqcc);
136
137 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
138 rq->handle_rx_cqe(rq, &cq->title);
139 }
140 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
141 cq->wq.cc = cqcc;
142 cq->decmprs_left -= cqe_count;
143 rq->stats.cqe_compress_pkts += cqe_count;
144
145 return cqe_count;
146 }
147
148 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
149 struct mlx5e_cq *cq,
150 int budget_rem)
151 {
152 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
153 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
154 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
155 rq->handle_rx_cqe(rq, &cq->title);
156 cq->mini_arr_idx++;
157
158 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
159 }
160
161 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
162
163 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
164 struct mlx5e_dma_info *dma_info)
165 {
166 struct mlx5e_page_cache *cache = &rq->page_cache;
167 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
168
169 if (tail_next == cache->head) {
170 rq->stats.cache_full++;
171 return false;
172 }
173
174 if (unlikely(page_is_pfmemalloc(dma_info->page)))
175 return false;
176
177 cache->page_cache[cache->tail] = *dma_info;
178 cache->tail = tail_next;
179 return true;
180 }
181
182 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
183 struct mlx5e_dma_info *dma_info)
184 {
185 struct mlx5e_page_cache *cache = &rq->page_cache;
186
187 if (unlikely(cache->head == cache->tail)) {
188 rq->stats.cache_empty++;
189 return false;
190 }
191
192 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
193 rq->stats.cache_busy++;
194 return false;
195 }
196
197 *dma_info = cache->page_cache[cache->head];
198 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
199 rq->stats.cache_reuse++;
200
201 dma_sync_single_for_device(rq->pdev, dma_info->addr,
202 RQ_PAGE_SIZE(rq),
203 DMA_FROM_DEVICE);
204 return true;
205 }
206
207 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
208 struct mlx5e_dma_info *dma_info)
209 {
210 struct page *page;
211
212 if (mlx5e_rx_cache_get(rq, dma_info))
213 return 0;
214
215 page = dev_alloc_pages(rq->buff.page_order);
216 if (unlikely(!page))
217 return -ENOMEM;
218
219 dma_info->page = page;
220 dma_info->addr = dma_map_page(rq->pdev, page, 0,
221 RQ_PAGE_SIZE(rq), rq->buff.map_dir);
222 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
223 put_page(page);
224 return -ENOMEM;
225 }
226
227 return 0;
228 }
229
230 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
231 bool recycle)
232 {
233 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
234 return;
235
236 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
237 rq->buff.map_dir);
238 put_page(dma_info->page);
239 }
240
241 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
242 {
243 struct mlx5e_dma_info *di = &rq->dma_info[ix];
244
245 if (unlikely(mlx5e_page_alloc_mapped(rq, di)))
246 return -ENOMEM;
247
248 wqe->data.addr = cpu_to_be64(di->addr + rq->rx_headroom);
249 return 0;
250 }
251
252 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
253 {
254 struct mlx5e_dma_info *di = &rq->dma_info[ix];
255
256 mlx5e_page_release(rq, di, true);
257 }
258
259 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
260 {
261 return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
262 }
263
264 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
265 struct sk_buff *skb,
266 struct mlx5e_mpw_info *wi,
267 u32 page_idx, u32 frag_offset,
268 u32 len)
269 {
270 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz);
271
272 dma_sync_single_for_cpu(rq->pdev,
273 wi->umr.dma_info[page_idx].addr + frag_offset,
274 len, DMA_FROM_DEVICE);
275 wi->skbs_frags[page_idx]++;
276 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
277 wi->umr.dma_info[page_idx].page, frag_offset,
278 len, truesize);
279 }
280
281 static inline void
282 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
283 struct sk_buff *skb,
284 struct mlx5e_mpw_info *wi,
285 u32 page_idx, u32 offset,
286 u32 headlen)
287 {
288 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
289 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
290 unsigned int len;
291
292 /* Aligning len to sizeof(long) optimizes memcpy performance */
293 len = ALIGN(headlen_pg, sizeof(long));
294 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
295 DMA_FROM_DEVICE);
296 skb_copy_to_linear_data_offset(skb, 0,
297 page_address(dma_info->page) + offset,
298 len);
299 if (unlikely(offset + headlen > PAGE_SIZE)) {
300 dma_info++;
301 headlen_pg = len;
302 len = ALIGN(headlen - headlen_pg, sizeof(long));
303 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
304 DMA_FROM_DEVICE);
305 skb_copy_to_linear_data_offset(skb, headlen_pg,
306 page_address(dma_info->page),
307 len);
308 }
309 }
310
311 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
312 {
313 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
314 struct mlx5e_icosq *sq = &rq->channel->icosq;
315 struct mlx5_wq_cyc *wq = &sq->wq;
316 struct mlx5e_umr_wqe *wqe;
317 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
318 u16 pi;
319
320 /* fill sq edge with nops to avoid wqe wrap around */
321 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
322 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
323 sq->db.ico_wqe[pi].num_wqebbs = 1;
324 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
325 }
326
327 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
328 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe));
329 wqe->ctrl.opmod_idx_opcode =
330 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
331 MLX5_OPCODE_UMR);
332
333 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
334 sq->db.ico_wqe[pi].num_wqebbs = num_wqebbs;
335 sq->pc += num_wqebbs;
336 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl);
337 }
338
339 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq,
340 struct mlx5e_rx_wqe *wqe,
341 u16 ix)
342 {
343 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
344 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, ix) << PAGE_SHIFT;
345 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
346 int err;
347 int i;
348
349 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
350 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
351
352 err = mlx5e_page_alloc_mapped(rq, dma_info);
353 if (unlikely(err))
354 goto err_unmap;
355 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
356 page_ref_add(dma_info->page, pg_strides);
357 wi->skbs_frags[i] = 0;
358 }
359
360 wi->consumed_strides = 0;
361 wqe->data.addr = cpu_to_be64(dma_offset);
362
363 return 0;
364
365 err_unmap:
366 while (--i >= 0) {
367 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
368
369 page_ref_sub(dma_info->page, pg_strides);
370 mlx5e_page_release(rq, dma_info, true);
371 }
372
373 return err;
374 }
375
376 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
377 {
378 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
379 int i;
380
381 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
382 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
383
384 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]);
385 mlx5e_page_release(rq, dma_info, true);
386 }
387 }
388
389 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
390 {
391 struct mlx5_wq_ll *wq = &rq->wq;
392 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
393
394 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
395
396 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) {
397 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
398 return;
399 }
400
401 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
402
403 /* ensure wqes are visible to device before updating doorbell record */
404 dma_wmb();
405
406 mlx5_wq_ll_update_db_record(wq);
407 }
408
409 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
410 {
411 int err;
412
413 err = mlx5e_alloc_rx_umr_mpwqe(rq, wqe, ix);
414 if (unlikely(err))
415 return err;
416 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
417 mlx5e_post_umr_wqe(rq, ix);
418 return -EBUSY;
419 }
420
421 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
422 {
423 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
424
425 mlx5e_free_rx_mpwqe(rq, wi);
426 }
427
428 #define RQ_CANNOT_POST(rq) \
429 (!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state) || \
430 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
431
432 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
433 {
434 struct mlx5_wq_ll *wq = &rq->wq;
435
436 if (unlikely(RQ_CANNOT_POST(rq)))
437 return false;
438
439 while (!mlx5_wq_ll_is_full(wq)) {
440 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
441 int err;
442
443 err = rq->alloc_wqe(rq, wqe, wq->head);
444 if (err == -EBUSY)
445 return true;
446 if (unlikely(err)) {
447 rq->stats.buff_alloc_err++;
448 break;
449 }
450
451 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
452 }
453
454 /* ensure wqes are visible to device before updating doorbell record */
455 dma_wmb();
456
457 mlx5_wq_ll_update_db_record(wq);
458
459 return !mlx5_wq_ll_is_full(wq);
460 }
461
462 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
463 u32 cqe_bcnt)
464 {
465 struct ethhdr *eth = (struct ethhdr *)(skb->data);
466 struct iphdr *ipv4;
467 struct ipv6hdr *ipv6;
468 struct tcphdr *tcp;
469 int network_depth = 0;
470 __be16 proto;
471 u16 tot_len;
472
473 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
474 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) ||
475 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type));
476
477 skb->mac_len = ETH_HLEN;
478 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
479
480 ipv4 = (struct iphdr *)(skb->data + network_depth);
481 ipv6 = (struct ipv6hdr *)(skb->data + network_depth);
482 tot_len = cqe_bcnt - network_depth;
483
484 if (proto == htons(ETH_P_IP)) {
485 tcp = (struct tcphdr *)(skb->data + network_depth +
486 sizeof(struct iphdr));
487 ipv6 = NULL;
488 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
489 } else {
490 tcp = (struct tcphdr *)(skb->data + network_depth +
491 sizeof(struct ipv6hdr));
492 ipv4 = NULL;
493 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
494 }
495
496 if (get_cqe_lro_tcppsh(cqe))
497 tcp->psh = 1;
498
499 if (tcp_ack) {
500 tcp->ack = 1;
501 tcp->ack_seq = cqe->lro_ack_seq_num;
502 tcp->window = cqe->lro_tcp_win;
503 }
504
505 if (ipv4) {
506 ipv4->ttl = cqe->lro_min_ttl;
507 ipv4->tot_len = cpu_to_be16(tot_len);
508 ipv4->check = 0;
509 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
510 ipv4->ihl);
511 } else {
512 ipv6->hop_limit = cqe->lro_min_ttl;
513 ipv6->payload_len = cpu_to_be16(tot_len -
514 sizeof(struct ipv6hdr));
515 }
516 }
517
518 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
519 struct sk_buff *skb)
520 {
521 u8 cht = cqe->rss_hash_type;
522 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
523 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
524 PKT_HASH_TYPE_NONE;
525 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
526 }
527
528 static inline bool is_first_ethertype_ip(struct sk_buff *skb)
529 {
530 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
531
532 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
533 }
534
535 static inline void mlx5e_handle_csum(struct net_device *netdev,
536 struct mlx5_cqe64 *cqe,
537 struct mlx5e_rq *rq,
538 struct sk_buff *skb,
539 bool lro)
540 {
541 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
542 goto csum_none;
543
544 if (lro) {
545 skb->ip_summed = CHECKSUM_UNNECESSARY;
546 return;
547 }
548
549 if (is_first_ethertype_ip(skb)) {
550 skb->ip_summed = CHECKSUM_COMPLETE;
551 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
552 rq->stats.csum_complete++;
553 return;
554 }
555
556 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
557 (cqe->hds_ip_ext & CQE_L4_OK))) {
558 skb->ip_summed = CHECKSUM_UNNECESSARY;
559 if (cqe_is_tunneled(cqe)) {
560 skb->csum_level = 1;
561 skb->encapsulation = 1;
562 rq->stats.csum_unnecessary_inner++;
563 }
564 return;
565 }
566 csum_none:
567 skb->ip_summed = CHECKSUM_NONE;
568 rq->stats.csum_none++;
569 }
570
571 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
572 u32 cqe_bcnt,
573 struct mlx5e_rq *rq,
574 struct sk_buff *skb)
575 {
576 struct net_device *netdev = rq->netdev;
577 struct mlx5e_tstamp *tstamp = rq->tstamp;
578 int lro_num_seg;
579
580 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
581 if (lro_num_seg > 1) {
582 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
583 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
584 /* Subtract one since we already counted this as one
585 * "regular" packet in mlx5e_complete_rx_cqe()
586 */
587 rq->stats.packets += lro_num_seg - 1;
588 rq->stats.lro_packets++;
589 rq->stats.lro_bytes += cqe_bcnt;
590 }
591
592 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
593 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
594
595 skb_record_rx_queue(skb, rq->ix);
596
597 if (likely(netdev->features & NETIF_F_RXHASH))
598 mlx5e_skb_set_hash(cqe, skb);
599
600 if (cqe_has_vlan(cqe))
601 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
602 be16_to_cpu(cqe->vlan_info));
603
604 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
605
606 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
607 skb->protocol = eth_type_trans(skb, netdev);
608 }
609
610 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
611 struct mlx5_cqe64 *cqe,
612 u32 cqe_bcnt,
613 struct sk_buff *skb)
614 {
615 rq->stats.packets++;
616 rq->stats.bytes += cqe_bcnt;
617 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
618 }
619
620 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
621 {
622 struct mlx5_wq_cyc *wq = &sq->wq;
623 struct mlx5e_tx_wqe *wqe;
624 u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */
625
626 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
627
628 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
629 }
630
631 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
632 struct mlx5e_dma_info *di,
633 const struct xdp_buff *xdp)
634 {
635 struct mlx5e_xdpsq *sq = &rq->xdpsq;
636 struct mlx5_wq_cyc *wq = &sq->wq;
637 u16 pi = sq->pc & wq->sz_m1;
638 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
639
640 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
641 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
642 struct mlx5_wqe_data_seg *dseg;
643
644 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
645 dma_addr_t dma_addr = di->addr + data_offset;
646 unsigned int dma_len = xdp->data_end - xdp->data;
647
648 prefetchw(wqe);
649
650 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE ||
651 MLX5E_SW2HW_MTU(rq->netdev->mtu) < dma_len)) {
652 rq->stats.xdp_drop++;
653 mlx5e_page_release(rq, di, true);
654 return false;
655 }
656
657 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
658 if (sq->db.doorbell) {
659 /* SQ is full, ring doorbell */
660 mlx5e_xmit_xdp_doorbell(sq);
661 sq->db.doorbell = false;
662 }
663 rq->stats.xdp_tx_full++;
664 mlx5e_page_release(rq, di, true);
665 return false;
666 }
667
668 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
669
670 cseg->fm_ce_se = 0;
671
672 dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
673
674 /* copy the inline part if required */
675 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
676 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
677 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
678 dma_len -= MLX5E_XDP_MIN_INLINE;
679 dma_addr += MLX5E_XDP_MIN_INLINE;
680 dseg++;
681 }
682
683 /* write the dma part */
684 dseg->addr = cpu_to_be64(dma_addr);
685 dseg->byte_count = cpu_to_be32(dma_len);
686
687 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
688
689 sq->db.di[pi] = *di;
690 sq->pc++;
691
692 sq->db.doorbell = true;
693 rq->stats.xdp_tx++;
694 return true;
695 }
696
697 /* returns true if packet was consumed by xdp */
698 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq,
699 struct mlx5e_dma_info *di,
700 void *va, u16 *rx_headroom, u32 *len)
701 {
702 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
703 struct xdp_buff xdp;
704 u32 act;
705
706 if (!prog)
707 return false;
708
709 xdp.data = va + *rx_headroom;
710 xdp.data_end = xdp.data + *len;
711 xdp.data_hard_start = va;
712
713 act = bpf_prog_run_xdp(prog, &xdp);
714 switch (act) {
715 case XDP_PASS:
716 *rx_headroom = xdp.data - xdp.data_hard_start;
717 *len = xdp.data_end - xdp.data;
718 return false;
719 case XDP_TX:
720 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
721 trace_xdp_exception(rq->netdev, prog, act);
722 return true;
723 default:
724 bpf_warn_invalid_xdp_action(act);
725 case XDP_ABORTED:
726 trace_xdp_exception(rq->netdev, prog, act);
727 case XDP_DROP:
728 rq->stats.xdp_drop++;
729 mlx5e_page_release(rq, di, true);
730 return true;
731 }
732 }
733
734 static inline
735 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
736 u16 wqe_counter, u32 cqe_bcnt)
737 {
738 struct mlx5e_dma_info *di;
739 struct sk_buff *skb;
740 void *va, *data;
741 u16 rx_headroom = rq->rx_headroom;
742 bool consumed;
743
744 di = &rq->dma_info[wqe_counter];
745 va = page_address(di->page);
746 data = va + rx_headroom;
747
748 dma_sync_single_range_for_cpu(rq->pdev,
749 di->addr,
750 rx_headroom,
751 rq->buff.wqe_sz,
752 DMA_FROM_DEVICE);
753 prefetch(data);
754
755 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
756 rq->stats.wqe_err++;
757 mlx5e_page_release(rq, di, true);
758 return NULL;
759 }
760
761 rcu_read_lock();
762 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
763 rcu_read_unlock();
764 if (consumed)
765 return NULL; /* page/packet was consumed by XDP */
766
767 skb = build_skb(va, RQ_PAGE_SIZE(rq));
768 if (unlikely(!skb)) {
769 rq->stats.buff_alloc_err++;
770 mlx5e_page_release(rq, di, true);
771 return NULL;
772 }
773
774 /* queue up for recycling ..*/
775 page_ref_inc(di->page);
776 mlx5e_page_release(rq, di, true);
777
778 skb_reserve(skb, rx_headroom);
779 skb_put(skb, cqe_bcnt);
780
781 return skb;
782 }
783
784 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
785 {
786 struct mlx5e_rx_wqe *wqe;
787 __be16 wqe_counter_be;
788 struct sk_buff *skb;
789 u16 wqe_counter;
790 u32 cqe_bcnt;
791
792 wqe_counter_be = cqe->wqe_counter;
793 wqe_counter = be16_to_cpu(wqe_counter_be);
794 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
795 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
796
797 skb = skb_from_cqe(rq, cqe, wqe_counter, cqe_bcnt);
798 if (!skb)
799 goto wq_ll_pop;
800
801 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
802 napi_gro_receive(rq->cq.napi, skb);
803
804 wq_ll_pop:
805 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
806 &wqe->next.next_wqe_index);
807 }
808
809 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
810 {
811 struct net_device *netdev = rq->netdev;
812 struct mlx5e_priv *priv = netdev_priv(netdev);
813 struct mlx5e_rep_priv *rpriv = priv->ppriv;
814 struct mlx5_eswitch_rep *rep = rpriv->rep;
815 struct mlx5e_rx_wqe *wqe;
816 struct sk_buff *skb;
817 __be16 wqe_counter_be;
818 u16 wqe_counter;
819 u32 cqe_bcnt;
820
821 wqe_counter_be = cqe->wqe_counter;
822 wqe_counter = be16_to_cpu(wqe_counter_be);
823 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
824 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
825
826 skb = skb_from_cqe(rq, cqe, wqe_counter, cqe_bcnt);
827 if (!skb)
828 goto wq_ll_pop;
829
830 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
831
832 if (rep->vlan && skb_vlan_tag_present(skb))
833 skb_vlan_pop(skb);
834
835 napi_gro_receive(rq->cq.napi, skb);
836
837 wq_ll_pop:
838 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
839 &wqe->next.next_wqe_index);
840 }
841
842 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
843 struct mlx5_cqe64 *cqe,
844 struct mlx5e_mpw_info *wi,
845 u32 cqe_bcnt,
846 struct sk_buff *skb)
847 {
848 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
849 u32 wqe_offset = stride_ix * rq->mpwqe_stride_sz;
850 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
851 u32 page_idx = wqe_offset >> PAGE_SHIFT;
852 u32 head_page_idx = page_idx;
853 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
854 u32 frag_offset = head_offset + headlen;
855 u16 byte_cnt = cqe_bcnt - headlen;
856
857 if (unlikely(frag_offset >= PAGE_SIZE)) {
858 page_idx++;
859 frag_offset -= PAGE_SIZE;
860 }
861
862 while (byte_cnt) {
863 u32 pg_consumed_bytes =
864 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
865
866 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
867 pg_consumed_bytes);
868 byte_cnt -= pg_consumed_bytes;
869 frag_offset = 0;
870 page_idx++;
871 }
872 /* copy header */
873 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
874 head_offset, headlen);
875 /* skb linear part was allocated with headlen and aligned to long */
876 skb->tail += headlen;
877 skb->len += headlen;
878 }
879
880 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
881 {
882 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
883 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
884 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
885 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
886 struct sk_buff *skb;
887 u16 cqe_bcnt;
888
889 wi->consumed_strides += cstrides;
890
891 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
892 rq->stats.wqe_err++;
893 goto mpwrq_cqe_out;
894 }
895
896 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
897 rq->stats.mpwqe_filler++;
898 goto mpwrq_cqe_out;
899 }
900
901 skb = napi_alloc_skb(rq->cq.napi,
902 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
903 sizeof(long)));
904 if (unlikely(!skb)) {
905 rq->stats.buff_alloc_err++;
906 goto mpwrq_cqe_out;
907 }
908
909 prefetchw(skb->data);
910 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
911
912 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
913 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
914 napi_gro_receive(rq->cq.napi, skb);
915
916 mpwrq_cqe_out:
917 if (likely(wi->consumed_strides < rq->mpwqe_num_strides))
918 return;
919
920 mlx5e_free_rx_mpwqe(rq, wi);
921 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
922 }
923
924 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
925 {
926 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
927 struct mlx5e_xdpsq *xdpsq = &rq->xdpsq;
928 int work_done = 0;
929
930 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
931 return 0;
932
933 if (cq->decmprs_left)
934 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
935
936 for (; work_done < budget; work_done++) {
937 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq);
938
939 if (!cqe)
940 break;
941
942 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
943 work_done +=
944 mlx5e_decompress_cqes_start(rq, cq,
945 budget - work_done);
946 continue;
947 }
948
949 mlx5_cqwq_pop(&cq->wq);
950
951 rq->handle_rx_cqe(rq, cqe);
952 }
953
954 if (xdpsq->db.doorbell) {
955 mlx5e_xmit_xdp_doorbell(xdpsq);
956 xdpsq->db.doorbell = false;
957 }
958
959 mlx5_cqwq_update_db_record(&cq->wq);
960
961 /* ensure cq space is freed before enabling more cqes */
962 wmb();
963
964 return work_done;
965 }
966
967 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
968 {
969 struct mlx5e_xdpsq *sq;
970 struct mlx5e_rq *rq;
971 u16 sqcc;
972 int i;
973
974 sq = container_of(cq, struct mlx5e_xdpsq, cq);
975
976 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
977 return false;
978
979 rq = container_of(sq, struct mlx5e_rq, xdpsq);
980
981 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
982 * otherwise a cq overrun may occur
983 */
984 sqcc = sq->cc;
985
986 for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) {
987 struct mlx5_cqe64 *cqe;
988 u16 wqe_counter;
989 bool last_wqe;
990
991 cqe = mlx5e_get_cqe(cq);
992 if (!cqe)
993 break;
994
995 mlx5_cqwq_pop(&cq->wq);
996
997 wqe_counter = be16_to_cpu(cqe->wqe_counter);
998
999 do {
1000 struct mlx5e_dma_info *di;
1001 u16 ci;
1002
1003 last_wqe = (sqcc == wqe_counter);
1004
1005 ci = sqcc & sq->wq.sz_m1;
1006 di = &sq->db.di[ci];
1007
1008 sqcc++;
1009 /* Recycle RX page */
1010 mlx5e_page_release(rq, di, true);
1011 } while (!last_wqe);
1012 }
1013
1014 mlx5_cqwq_update_db_record(&cq->wq);
1015
1016 /* ensure cq space is freed before enabling more cqes */
1017 wmb();
1018
1019 sq->cc = sqcc;
1020 return (i == MLX5E_TX_CQ_POLL_BUDGET);
1021 }
1022
1023 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1024 {
1025 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1026 struct mlx5e_dma_info *di;
1027 u16 ci;
1028
1029 while (sq->cc != sq->pc) {
1030 ci = sq->cc & sq->wq.sz_m1;
1031 di = &sq->db.di[ci];
1032 sq->cc++;
1033
1034 mlx5e_page_release(rq, di, false);
1035 }
1036 }
1037
1038 #ifdef CONFIG_MLX5_CORE_IPOIB
1039
1040 #define MLX5_IB_GRH_DGID_OFFSET 24
1041 #define MLX5_IB_GRH_BYTES 40
1042 #define MLX5_IPOIB_ENCAP_LEN 4
1043 #define MLX5_GID_SIZE 16
1044 #define MLX5_IPOIB_PSEUDO_LEN 20
1045 #define MLX5_IPOIB_HARD_LEN (MLX5_IPOIB_PSEUDO_LEN + MLX5_IPOIB_ENCAP_LEN)
1046
1047 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1048 struct mlx5_cqe64 *cqe,
1049 u32 cqe_bcnt,
1050 struct sk_buff *skb)
1051 {
1052 struct net_device *netdev = rq->netdev;
1053 char *pseudo_header;
1054 u8 *dgid;
1055 u8 g;
1056
1057 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1058 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1059 if ((!g) || dgid[0] != 0xff)
1060 skb->pkt_type = PACKET_HOST;
1061 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1062 skb->pkt_type = PACKET_BROADCAST;
1063 else
1064 skb->pkt_type = PACKET_MULTICAST;
1065
1066 /* TODO: IB/ipoib: Allow mcast packets from other VFs
1067 * 68996a6e760e5c74654723eeb57bf65628ae87f4
1068 */
1069
1070 skb_pull(skb, MLX5_IB_GRH_BYTES);
1071
1072 skb->protocol = *((__be16 *)(skb->data));
1073
1074 skb->ip_summed = CHECKSUM_COMPLETE;
1075 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1076
1077 skb_record_rx_queue(skb, rq->ix);
1078
1079 if (likely(netdev->features & NETIF_F_RXHASH))
1080 mlx5e_skb_set_hash(cqe, skb);
1081
1082 /* 20 bytes of ipoib header and 4 for encap existing */
1083 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1084 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1085 skb_reset_mac_header(skb);
1086 skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1087
1088 skb->dev = netdev;
1089
1090 rq->stats.csum_complete++;
1091 rq->stats.packets++;
1092 rq->stats.bytes += cqe_bcnt;
1093 }
1094
1095 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1096 {
1097 struct mlx5e_rx_wqe *wqe;
1098 __be16 wqe_counter_be;
1099 struct sk_buff *skb;
1100 u16 wqe_counter;
1101 u32 cqe_bcnt;
1102
1103 wqe_counter_be = cqe->wqe_counter;
1104 wqe_counter = be16_to_cpu(wqe_counter_be);
1105 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1106 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1107
1108 skb = skb_from_cqe(rq, cqe, wqe_counter, cqe_bcnt);
1109 if (!skb)
1110 goto wq_ll_pop;
1111
1112 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1113 napi_gro_receive(rq->cq.napi, skb);
1114
1115 wq_ll_pop:
1116 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1117 &wqe->next.next_wqe_index);
1118 }
1119
1120 #endif /* CONFIG_MLX5_CORE_IPOIB */
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