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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_rx.c
1 /*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/ip.h>
34 #include <linux/ipv6.h>
35 #include <linux/tcp.h>
36 #include <net/busy_poll.h>
37 #include "en.h"
38 #include "en_tc.h"
39
40 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
41 {
42 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
43 }
44
45 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
46 void *data)
47 {
48 u32 ci = cqcc & cq->wq.sz_m1;
49
50 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
51 }
52
53 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
54 struct mlx5e_cq *cq, u32 cqcc)
55 {
56 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
57 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
58 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
59 rq->stats.cqe_compress_blks++;
60 }
61
62 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
63 {
64 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
65 cq->mini_arr_idx = 0;
66 }
67
68 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
69 {
70 u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
71 u32 wq_sz = 1 << cq->wq.log_sz;
72 u32 ci = cqcc & cq->wq.sz_m1;
73 u32 ci_top = min_t(u32, wq_sz, ci + n);
74
75 for (; ci < ci_top; ci++, n--) {
76 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
77
78 cqe->op_own = op_own;
79 }
80
81 if (unlikely(ci == wq_sz)) {
82 op_own = !op_own;
83 for (ci = 0; ci < n; ci++) {
84 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
85
86 cqe->op_own = op_own;
87 }
88 }
89 }
90
91 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
92 struct mlx5e_cq *cq, u32 cqcc)
93 {
94 u16 wqe_cnt_step;
95
96 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
97 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
98 cq->title.op_own &= 0xf0;
99 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz);
100 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
101
102 wqe_cnt_step =
103 rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
104 mpwrq_get_cqe_consumed_strides(&cq->title) : 1;
105 cq->decmprs_wqe_counter =
106 (cq->decmprs_wqe_counter + wqe_cnt_step) & rq->wq.sz_m1;
107 }
108
109 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
110 struct mlx5e_cq *cq, u32 cqcc)
111 {
112 mlx5e_decompress_cqe(rq, cq, cqcc);
113 cq->title.rss_hash_type = 0;
114 cq->title.rss_hash_result = 0;
115 }
116
117 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
118 struct mlx5e_cq *cq,
119 int update_owner_only,
120 int budget_rem)
121 {
122 u32 cqcc = cq->wq.cc + update_owner_only;
123 u32 cqe_count;
124 u32 i;
125
126 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
127
128 for (i = update_owner_only; i < cqe_count;
129 i++, cq->mini_arr_idx++, cqcc++) {
130 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
131 mlx5e_read_mini_arr_slot(cq, cqcc);
132
133 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
134 rq->handle_rx_cqe(rq, &cq->title);
135 }
136 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
137 cq->wq.cc = cqcc;
138 cq->decmprs_left -= cqe_count;
139 rq->stats.cqe_compress_pkts += cqe_count;
140
141 return cqe_count;
142 }
143
144 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
145 struct mlx5e_cq *cq,
146 int budget_rem)
147 {
148 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
149 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
150 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
151 rq->handle_rx_cqe(rq, &cq->title);
152 cq->mini_arr_idx++;
153
154 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
155 }
156
157 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val)
158 {
159 bool was_opened;
160
161 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
162 return;
163
164 mutex_lock(&priv->state_lock);
165
166 if (priv->params.rx_cqe_compress == val)
167 goto unlock;
168
169 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
170 if (was_opened)
171 mlx5e_close_locked(priv->netdev);
172
173 priv->params.rx_cqe_compress = val;
174
175 if (was_opened)
176 mlx5e_open_locked(priv->netdev);
177
178 unlock:
179 mutex_unlock(&priv->state_lock);
180 }
181
182 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
183 {
184 struct sk_buff *skb;
185 dma_addr_t dma_addr;
186
187 skb = napi_alloc_skb(rq->cq.napi, rq->wqe_sz);
188 if (unlikely(!skb))
189 return -ENOMEM;
190
191 dma_addr = dma_map_single(rq->pdev,
192 /* hw start padding */
193 skb->data,
194 /* hw end padding */
195 rq->wqe_sz,
196 DMA_FROM_DEVICE);
197
198 if (unlikely(dma_mapping_error(rq->pdev, dma_addr)))
199 goto err_free_skb;
200
201 *((dma_addr_t *)skb->cb) = dma_addr;
202 wqe->data.addr = cpu_to_be64(dma_addr);
203 wqe->data.lkey = rq->mkey_be;
204
205 rq->skb[ix] = skb;
206
207 return 0;
208
209 err_free_skb:
210 dev_kfree_skb(skb);
211
212 return -ENOMEM;
213 }
214
215 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
216 {
217 struct sk_buff *skb = rq->skb[ix];
218
219 if (skb) {
220 rq->skb[ix] = NULL;
221 dma_unmap_single(rq->pdev,
222 *((dma_addr_t *)skb->cb),
223 rq->wqe_sz,
224 DMA_FROM_DEVICE);
225 dev_kfree_skb(skb);
226 }
227 }
228
229 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
230 {
231 return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
232 }
233
234 static inline void
235 mlx5e_dma_pre_sync_linear_mpwqe(struct device *pdev,
236 struct mlx5e_mpw_info *wi,
237 u32 wqe_offset, u32 len)
238 {
239 dma_sync_single_for_cpu(pdev, wi->dma_info.addr + wqe_offset,
240 len, DMA_FROM_DEVICE);
241 }
242
243 static inline void
244 mlx5e_dma_pre_sync_fragmented_mpwqe(struct device *pdev,
245 struct mlx5e_mpw_info *wi,
246 u32 wqe_offset, u32 len)
247 {
248 /* No dma pre sync for fragmented MPWQE */
249 }
250
251 static inline void
252 mlx5e_add_skb_frag_linear_mpwqe(struct mlx5e_rq *rq,
253 struct sk_buff *skb,
254 struct mlx5e_mpw_info *wi,
255 u32 page_idx, u32 frag_offset,
256 u32 len)
257 {
258 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz);
259
260 wi->skbs_frags[page_idx]++;
261 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
262 &wi->dma_info.page[page_idx], frag_offset,
263 len, truesize);
264 }
265
266 static inline void
267 mlx5e_add_skb_frag_fragmented_mpwqe(struct mlx5e_rq *rq,
268 struct sk_buff *skb,
269 struct mlx5e_mpw_info *wi,
270 u32 page_idx, u32 frag_offset,
271 u32 len)
272 {
273 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz);
274
275 dma_sync_single_for_cpu(rq->pdev,
276 wi->umr.dma_info[page_idx].addr + frag_offset,
277 len, DMA_FROM_DEVICE);
278 wi->skbs_frags[page_idx]++;
279 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
280 wi->umr.dma_info[page_idx].page, frag_offset,
281 len, truesize);
282 }
283
284 static inline void
285 mlx5e_copy_skb_header_linear_mpwqe(struct device *pdev,
286 struct sk_buff *skb,
287 struct mlx5e_mpw_info *wi,
288 u32 page_idx, u32 offset,
289 u32 headlen)
290 {
291 struct page *page = &wi->dma_info.page[page_idx];
292
293 skb_copy_to_linear_data(skb, page_address(page) + offset,
294 ALIGN(headlen, sizeof(long)));
295 }
296
297 static inline void
298 mlx5e_copy_skb_header_fragmented_mpwqe(struct device *pdev,
299 struct sk_buff *skb,
300 struct mlx5e_mpw_info *wi,
301 u32 page_idx, u32 offset,
302 u32 headlen)
303 {
304 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
305 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
306 unsigned int len;
307
308 /* Aligning len to sizeof(long) optimizes memcpy performance */
309 len = ALIGN(headlen_pg, sizeof(long));
310 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
311 DMA_FROM_DEVICE);
312 skb_copy_to_linear_data_offset(skb, 0,
313 page_address(dma_info->page) + offset,
314 len);
315 if (unlikely(offset + headlen > PAGE_SIZE)) {
316 dma_info++;
317 headlen_pg = len;
318 len = ALIGN(headlen - headlen_pg, sizeof(long));
319 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
320 DMA_FROM_DEVICE);
321 skb_copy_to_linear_data_offset(skb, headlen_pg,
322 page_address(dma_info->page),
323 len);
324 }
325 }
326
327 static u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
328 {
329 return rq->mpwqe_mtt_offset +
330 wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
331 }
332
333 static void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
334 struct mlx5e_sq *sq,
335 struct mlx5e_umr_wqe *wqe,
336 u16 ix)
337 {
338 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
339 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
340 struct mlx5_wqe_data_seg *dseg = &wqe->data;
341 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
342 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
343 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
344
345 memset(wqe, 0, sizeof(*wqe));
346 cseg->opmod_idx_opcode =
347 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
348 MLX5_OPCODE_UMR);
349 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
350 ds_cnt);
351 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
352 cseg->imm = rq->umr_mkey_be;
353
354 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
355 ucseg->klm_octowords =
356 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
357 ucseg->bsf_octowords =
358 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
359 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
360
361 dseg->lkey = sq->mkey_be;
362 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
363 }
364
365 static void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
366 {
367 struct mlx5e_sq *sq = &rq->channel->icosq;
368 struct mlx5_wq_cyc *wq = &sq->wq;
369 struct mlx5e_umr_wqe *wqe;
370 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
371 u16 pi;
372
373 /* fill sq edge with nops to avoid wqe wrap around */
374 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
375 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
376 sq->ico_wqe_info[pi].num_wqebbs = 1;
377 mlx5e_send_nop(sq, true);
378 }
379
380 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
381 mlx5e_build_umr_wqe(rq, sq, wqe, ix);
382 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_UMR;
383 sq->ico_wqe_info[pi].num_wqebbs = num_wqebbs;
384 sq->pc += num_wqebbs;
385 mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
386 }
387
388 static inline int mlx5e_get_wqe_mtt_sz(void)
389 {
390 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
391 * To avoid copying garbage after the mtt array, we allocate
392 * a little more.
393 */
394 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
395 MLX5_UMR_MTT_ALIGNMENT);
396 }
397
398 static int mlx5e_alloc_and_map_page(struct mlx5e_rq *rq,
399 struct mlx5e_mpw_info *wi,
400 int i)
401 {
402 struct page *page;
403
404 page = dev_alloc_page();
405 if (unlikely(!page))
406 return -ENOMEM;
407
408 wi->umr.dma_info[i].page = page;
409 wi->umr.dma_info[i].addr = dma_map_page(rq->pdev, page, 0, PAGE_SIZE,
410 PCI_DMA_FROMDEVICE);
411 if (unlikely(dma_mapping_error(rq->pdev, wi->umr.dma_info[i].addr))) {
412 put_page(page);
413 return -ENOMEM;
414 }
415 wi->umr.mtt[i] = cpu_to_be64(wi->umr.dma_info[i].addr | MLX5_EN_WR);
416
417 return 0;
418 }
419
420 static int mlx5e_alloc_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
421 struct mlx5e_rx_wqe *wqe,
422 u16 ix)
423 {
424 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
425 int mtt_sz = mlx5e_get_wqe_mtt_sz();
426 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, ix) << PAGE_SHIFT;
427 int i;
428
429 wi->umr.dma_info = kmalloc(sizeof(*wi->umr.dma_info) *
430 MLX5_MPWRQ_PAGES_PER_WQE,
431 GFP_ATOMIC);
432 if (unlikely(!wi->umr.dma_info))
433 goto err_out;
434
435 /* We allocate more than mtt_sz as we will align the pointer */
436 wi->umr.mtt_no_align = kzalloc(mtt_sz + MLX5_UMR_ALIGN - 1,
437 GFP_ATOMIC);
438 if (unlikely(!wi->umr.mtt_no_align))
439 goto err_free_umr;
440
441 wi->umr.mtt = PTR_ALIGN(wi->umr.mtt_no_align, MLX5_UMR_ALIGN);
442 wi->umr.mtt_addr = dma_map_single(rq->pdev, wi->umr.mtt, mtt_sz,
443 PCI_DMA_TODEVICE);
444 if (unlikely(dma_mapping_error(rq->pdev, wi->umr.mtt_addr)))
445 goto err_free_mtt;
446
447 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
448 if (unlikely(mlx5e_alloc_and_map_page(rq, wi, i)))
449 goto err_unmap;
450 page_ref_add(wi->umr.dma_info[i].page,
451 mlx5e_mpwqe_strides_per_page(rq));
452 wi->skbs_frags[i] = 0;
453 }
454
455 wi->consumed_strides = 0;
456 wi->dma_pre_sync = mlx5e_dma_pre_sync_fragmented_mpwqe;
457 wi->add_skb_frag = mlx5e_add_skb_frag_fragmented_mpwqe;
458 wi->copy_skb_header = mlx5e_copy_skb_header_fragmented_mpwqe;
459 wi->free_wqe = mlx5e_free_rx_fragmented_mpwqe;
460 wqe->data.lkey = rq->umr_mkey_be;
461 wqe->data.addr = cpu_to_be64(dma_offset);
462
463 return 0;
464
465 err_unmap:
466 while (--i >= 0) {
467 dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE,
468 PCI_DMA_FROMDEVICE);
469 page_ref_sub(wi->umr.dma_info[i].page,
470 mlx5e_mpwqe_strides_per_page(rq));
471 put_page(wi->umr.dma_info[i].page);
472 }
473 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, PCI_DMA_TODEVICE);
474
475 err_free_mtt:
476 kfree(wi->umr.mtt_no_align);
477
478 err_free_umr:
479 kfree(wi->umr.dma_info);
480
481 err_out:
482 return -ENOMEM;
483 }
484
485 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
486 struct mlx5e_mpw_info *wi)
487 {
488 int mtt_sz = mlx5e_get_wqe_mtt_sz();
489 int i;
490
491 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
492 dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE,
493 PCI_DMA_FROMDEVICE);
494 page_ref_sub(wi->umr.dma_info[i].page,
495 mlx5e_mpwqe_strides_per_page(rq) - wi->skbs_frags[i]);
496 put_page(wi->umr.dma_info[i].page);
497 }
498 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, PCI_DMA_TODEVICE);
499 kfree(wi->umr.mtt_no_align);
500 kfree(wi->umr.dma_info);
501 }
502
503 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq)
504 {
505 struct mlx5_wq_ll *wq = &rq->wq;
506 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
507
508 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
509
510 if (unlikely(test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state))) {
511 mlx5e_free_rx_fragmented_mpwqe(rq, &rq->wqe_info[wq->head]);
512 return;
513 }
514
515 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
516 rq->stats.mpwqe_frag++;
517
518 /* ensure wqes are visible to device before updating doorbell record */
519 dma_wmb();
520
521 mlx5_wq_ll_update_db_record(wq);
522 }
523
524 static int mlx5e_alloc_rx_linear_mpwqe(struct mlx5e_rq *rq,
525 struct mlx5e_rx_wqe *wqe,
526 u16 ix)
527 {
528 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
529 gfp_t gfp_mask;
530 int i;
531
532 gfp_mask = GFP_ATOMIC | __GFP_COLD | __GFP_MEMALLOC;
533 wi->dma_info.page = alloc_pages_node(NUMA_NO_NODE, gfp_mask,
534 MLX5_MPWRQ_WQE_PAGE_ORDER);
535 if (unlikely(!wi->dma_info.page))
536 return -ENOMEM;
537
538 wi->dma_info.addr = dma_map_page(rq->pdev, wi->dma_info.page, 0,
539 rq->wqe_sz, PCI_DMA_FROMDEVICE);
540 if (unlikely(dma_mapping_error(rq->pdev, wi->dma_info.addr))) {
541 put_page(wi->dma_info.page);
542 return -ENOMEM;
543 }
544
545 /* We split the high-order page into order-0 ones and manage their
546 * reference counter to minimize the memory held by small skb fragments
547 */
548 split_page(wi->dma_info.page, MLX5_MPWRQ_WQE_PAGE_ORDER);
549 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
550 page_ref_add(&wi->dma_info.page[i],
551 mlx5e_mpwqe_strides_per_page(rq));
552 wi->skbs_frags[i] = 0;
553 }
554
555 wi->consumed_strides = 0;
556 wi->dma_pre_sync = mlx5e_dma_pre_sync_linear_mpwqe;
557 wi->add_skb_frag = mlx5e_add_skb_frag_linear_mpwqe;
558 wi->copy_skb_header = mlx5e_copy_skb_header_linear_mpwqe;
559 wi->free_wqe = mlx5e_free_rx_linear_mpwqe;
560 wqe->data.lkey = rq->mkey_be;
561 wqe->data.addr = cpu_to_be64(wi->dma_info.addr);
562
563 return 0;
564 }
565
566 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
567 struct mlx5e_mpw_info *wi)
568 {
569 int i;
570
571 dma_unmap_page(rq->pdev, wi->dma_info.addr, rq->wqe_sz,
572 PCI_DMA_FROMDEVICE);
573 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
574 page_ref_sub(&wi->dma_info.page[i],
575 mlx5e_mpwqe_strides_per_page(rq) - wi->skbs_frags[i]);
576 put_page(&wi->dma_info.page[i]);
577 }
578 }
579
580 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
581 {
582 int err;
583
584 err = mlx5e_alloc_rx_linear_mpwqe(rq, wqe, ix);
585 if (unlikely(err)) {
586 err = mlx5e_alloc_rx_fragmented_mpwqe(rq, wqe, ix);
587 if (unlikely(err))
588 return err;
589 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
590 mlx5e_post_umr_wqe(rq, ix);
591 return -EBUSY;
592 }
593
594 return 0;
595 }
596
597 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
598 {
599 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix];
600
601 wi->free_wqe(rq, wi);
602 }
603
604 #define RQ_CANNOT_POST(rq) \
605 (test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state) || \
606 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
607
608 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
609 {
610 struct mlx5_wq_ll *wq = &rq->wq;
611
612 if (unlikely(RQ_CANNOT_POST(rq)))
613 return false;
614
615 while (!mlx5_wq_ll_is_full(wq)) {
616 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
617 int err;
618
619 err = rq->alloc_wqe(rq, wqe, wq->head);
620 if (unlikely(err)) {
621 if (err != -EBUSY)
622 rq->stats.buff_alloc_err++;
623 break;
624 }
625
626 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
627 }
628
629 /* ensure wqes are visible to device before updating doorbell record */
630 dma_wmb();
631
632 mlx5_wq_ll_update_db_record(wq);
633
634 return !mlx5_wq_ll_is_full(wq);
635 }
636
637 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
638 u32 cqe_bcnt)
639 {
640 struct ethhdr *eth = (struct ethhdr *)(skb->data);
641 struct iphdr *ipv4;
642 struct ipv6hdr *ipv6;
643 struct tcphdr *tcp;
644 int network_depth = 0;
645 __be16 proto;
646 u16 tot_len;
647
648 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
649 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) ||
650 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type));
651
652 skb->mac_len = ETH_HLEN;
653 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
654
655 ipv4 = (struct iphdr *)(skb->data + network_depth);
656 ipv6 = (struct ipv6hdr *)(skb->data + network_depth);
657 tot_len = cqe_bcnt - network_depth;
658
659 if (proto == htons(ETH_P_IP)) {
660 tcp = (struct tcphdr *)(skb->data + network_depth +
661 sizeof(struct iphdr));
662 ipv6 = NULL;
663 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
664 } else {
665 tcp = (struct tcphdr *)(skb->data + network_depth +
666 sizeof(struct ipv6hdr));
667 ipv4 = NULL;
668 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
669 }
670
671 if (get_cqe_lro_tcppsh(cqe))
672 tcp->psh = 1;
673
674 if (tcp_ack) {
675 tcp->ack = 1;
676 tcp->ack_seq = cqe->lro_ack_seq_num;
677 tcp->window = cqe->lro_tcp_win;
678 }
679
680 if (ipv4) {
681 ipv4->ttl = cqe->lro_min_ttl;
682 ipv4->tot_len = cpu_to_be16(tot_len);
683 ipv4->check = 0;
684 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
685 ipv4->ihl);
686 } else {
687 ipv6->hop_limit = cqe->lro_min_ttl;
688 ipv6->payload_len = cpu_to_be16(tot_len -
689 sizeof(struct ipv6hdr));
690 }
691 }
692
693 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
694 struct sk_buff *skb)
695 {
696 u8 cht = cqe->rss_hash_type;
697 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
698 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
699 PKT_HASH_TYPE_NONE;
700 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
701 }
702
703 static inline bool is_first_ethertype_ip(struct sk_buff *skb)
704 {
705 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
706
707 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
708 }
709
710 static inline void mlx5e_handle_csum(struct net_device *netdev,
711 struct mlx5_cqe64 *cqe,
712 struct mlx5e_rq *rq,
713 struct sk_buff *skb,
714 bool lro)
715 {
716 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
717 goto csum_none;
718
719 if (lro) {
720 skb->ip_summed = CHECKSUM_UNNECESSARY;
721 return;
722 }
723
724 if (is_first_ethertype_ip(skb)) {
725 skb->ip_summed = CHECKSUM_COMPLETE;
726 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
727 rq->stats.csum_complete++;
728 return;
729 }
730
731 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
732 (cqe->hds_ip_ext & CQE_L4_OK))) {
733 skb->ip_summed = CHECKSUM_UNNECESSARY;
734 if (cqe_is_tunneled(cqe)) {
735 skb->csum_level = 1;
736 skb->encapsulation = 1;
737 rq->stats.csum_unnecessary_inner++;
738 }
739 return;
740 }
741 csum_none:
742 skb->ip_summed = CHECKSUM_NONE;
743 rq->stats.csum_none++;
744 }
745
746 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
747 u32 cqe_bcnt,
748 struct mlx5e_rq *rq,
749 struct sk_buff *skb)
750 {
751 struct net_device *netdev = rq->netdev;
752 struct mlx5e_tstamp *tstamp = rq->tstamp;
753 int lro_num_seg;
754
755 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
756 if (lro_num_seg > 1) {
757 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
758 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
759 rq->stats.lro_packets++;
760 rq->stats.lro_bytes += cqe_bcnt;
761 }
762
763 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
764 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
765
766 skb_record_rx_queue(skb, rq->ix);
767
768 if (likely(netdev->features & NETIF_F_RXHASH))
769 mlx5e_skb_set_hash(cqe, skb);
770
771 if (cqe_has_vlan(cqe))
772 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
773 be16_to_cpu(cqe->vlan_info));
774
775 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
776
777 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
778 skb->protocol = eth_type_trans(skb, netdev);
779 }
780
781 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
782 struct mlx5_cqe64 *cqe,
783 u32 cqe_bcnt,
784 struct sk_buff *skb)
785 {
786 rq->stats.packets++;
787 rq->stats.bytes += cqe_bcnt;
788 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
789 napi_gro_receive(rq->cq.napi, skb);
790 }
791
792 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
793 {
794 struct mlx5e_rx_wqe *wqe;
795 struct sk_buff *skb;
796 __be16 wqe_counter_be;
797 u16 wqe_counter;
798 u32 cqe_bcnt;
799
800 wqe_counter_be = cqe->wqe_counter;
801 wqe_counter = be16_to_cpu(wqe_counter_be);
802 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
803 skb = rq->skb[wqe_counter];
804 prefetch(skb->data);
805 rq->skb[wqe_counter] = NULL;
806
807 dma_unmap_single(rq->pdev,
808 *((dma_addr_t *)skb->cb),
809 rq->wqe_sz,
810 DMA_FROM_DEVICE);
811
812 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
813 rq->stats.wqe_err++;
814 dev_kfree_skb(skb);
815 goto wq_ll_pop;
816 }
817
818 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
819 skb_put(skb, cqe_bcnt);
820
821 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
822
823 wq_ll_pop:
824 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
825 &wqe->next.next_wqe_index);
826 }
827
828 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
829 struct mlx5_cqe64 *cqe,
830 struct mlx5e_mpw_info *wi,
831 u32 cqe_bcnt,
832 struct sk_buff *skb)
833 {
834 u32 consumed_bytes = ALIGN(cqe_bcnt, rq->mpwqe_stride_sz);
835 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
836 u32 wqe_offset = stride_ix * rq->mpwqe_stride_sz;
837 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
838 u32 page_idx = wqe_offset >> PAGE_SHIFT;
839 u32 head_page_idx = page_idx;
840 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
841 u32 frag_offset = head_offset + headlen;
842 u16 byte_cnt = cqe_bcnt - headlen;
843
844 if (unlikely(frag_offset >= PAGE_SIZE)) {
845 page_idx++;
846 frag_offset -= PAGE_SIZE;
847 }
848 wi->dma_pre_sync(rq->pdev, wi, wqe_offset, consumed_bytes);
849
850 while (byte_cnt) {
851 u32 pg_consumed_bytes =
852 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
853
854 wi->add_skb_frag(rq, skb, wi, page_idx, frag_offset,
855 pg_consumed_bytes);
856 byte_cnt -= pg_consumed_bytes;
857 frag_offset = 0;
858 page_idx++;
859 }
860 /* copy header */
861 wi->copy_skb_header(rq->pdev, skb, wi, head_page_idx, head_offset,
862 headlen);
863 /* skb linear part was allocated with headlen and aligned to long */
864 skb->tail += headlen;
865 skb->len += headlen;
866 }
867
868 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
869 {
870 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
871 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
872 struct mlx5e_mpw_info *wi = &rq->wqe_info[wqe_id];
873 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
874 struct sk_buff *skb;
875 u16 cqe_bcnt;
876
877 wi->consumed_strides += cstrides;
878
879 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
880 rq->stats.wqe_err++;
881 goto mpwrq_cqe_out;
882 }
883
884 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
885 rq->stats.mpwqe_filler++;
886 goto mpwrq_cqe_out;
887 }
888
889 skb = napi_alloc_skb(rq->cq.napi,
890 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
891 sizeof(long)));
892 if (unlikely(!skb)) {
893 rq->stats.buff_alloc_err++;
894 goto mpwrq_cqe_out;
895 }
896
897 prefetch(skb->data);
898 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
899
900 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
901 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
902
903 mpwrq_cqe_out:
904 if (likely(wi->consumed_strides < rq->mpwqe_num_strides))
905 return;
906
907 wi->free_wqe(rq, wi);
908 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
909 }
910
911 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
912 {
913 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
914 int work_done = 0;
915
916 if (unlikely(test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state)))
917 return 0;
918
919 if (cq->decmprs_left)
920 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
921
922 for (; work_done < budget; work_done++) {
923 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq);
924
925 if (!cqe)
926 break;
927
928 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
929 work_done +=
930 mlx5e_decompress_cqes_start(rq, cq,
931 budget - work_done);
932 continue;
933 }
934
935 mlx5_cqwq_pop(&cq->wq);
936
937 rq->handle_rx_cqe(rq, cqe);
938 }
939
940 mlx5_cqwq_update_db_record(&cq->wq);
941
942 /* ensure cq space is freed before enabling more cqes */
943 wmb();
944
945 return work_done;
946 }
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