drivers/net/ethernet/mellanox/mlx5/core/en_stats.h

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __MLX5_EN_STATS_H__
  33 #define __MLX5_EN_STATS_H__
  34
  35 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
  36         (*(u64 *)((char *)ptr + dsc[i].offset))
  37 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
  38         be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
  39 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
  40         (*(u32 *)((char *)ptr + dsc[i].offset))
  41 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
  42         be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
  43
  44 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
  45 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
  46 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
  47
  48 struct counter_desc {
  49         char            format[ETH_GSTRING_LEN];
  50         size_t          offset; /* Byte offset */
  51 };
  52
  53 struct mlx5e_sw_stats {
  54         u64 rx_packets;
  55         u64 rx_bytes;
  56         u64 tx_packets;
  57         u64 tx_bytes;
  58         u64 tx_tso_packets;
  59         u64 tx_tso_bytes;
  60         u64 tx_tso_inner_packets;
  61         u64 tx_tso_inner_bytes;
  62         u64 tx_added_vlan_packets;
  63         u64 rx_lro_packets;
  64         u64 rx_lro_bytes;
  65         u64 rx_ecn_mark;
  66         u64 rx_removed_vlan_packets;
  67         u64 rx_csum_unnecessary;
  68         u64 rx_csum_none;
  69         u64 rx_csum_complete;
  70         u64 rx_csum_complete_tail;
  71         u64 rx_csum_complete_tail_slow;
  72         u64 rx_csum_unnecessary_inner;
  73         u64 rx_xdp_drop;
  74         u64 rx_xdp_tx;
  75         u64 rx_xdp_tx_full;
  76         u64 tx_csum_none;
  77         u64 tx_csum_partial;
  78         u64 tx_csum_partial_inner;
  79         u64 tx_queue_stopped;
  80         u64 tx_queue_wake;
  81         u64 tx_queue_dropped;
  82         u64 tx_xmit_more;
  83         u64 rx_wqe_err;
  84         u64 rx_mpwqe_filler;
  85         u64 rx_buff_alloc_err;
  86         u64 rx_cqe_compress_blks;
  87         u64 rx_cqe_compress_pkts;
  88         u64 rx_page_reuse;
  89         u64 rx_cache_reuse;
  90         u64 rx_cache_full;
  91         u64 rx_cache_empty;
  92         u64 rx_cache_busy;
  93         u64 rx_cache_waive;
  94
  95         /* Special handling counters */
  96         u64 link_down_events_phy;
  97 };
  98
  99 struct mlx5e_qcounter_stats {
 100         u32 rx_out_of_buffer;
 101 };
 102
 103 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
 104                                                 vstats->query_vport_out, c)
 105
 106 struct mlx5e_vport_stats {
 107         __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
 108 };
 109
 110 #define PPORT_802_3_GET(pstats, c) \
 111         MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
 112                    counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
 113 #define PPORT_2863_GET(pstats, c) \
 114         MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
 115                    counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
 116 #define PPORT_2819_GET(pstats, c) \
 117         MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
 118                    counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
 119 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \
 120         MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
 121                    counter_set.phys_layer_statistical_cntrs.c##_high)
 122 #define PPORT_PER_PRIO_GET(pstats, prio, c) \
 123         MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
 124                    counter_set.eth_per_prio_grp_data_layout.c##_high)
 125 #define NUM_PPORT_PRIO                          8
 126 #define PPORT_ETH_EXT_GET(pstats, c) \
 127         MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
 128                    counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
 129
 130 struct mlx5e_pport_stats {
 131         __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
 132         __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
 133         __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
 134         __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
 135         __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
 136         __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
 137         __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
 138 };
 139
 140 #define PCIE_PERF_GET(pcie_stats, c) \
 141         MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
 142                  counter_set.pcie_perf_cntrs_grp_data_layout.c)
 143
 144 #define PCIE_PERF_GET64(pcie_stats, c) \
 145         MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
 146                    counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
 147
 148 struct mlx5e_pcie_stats {
 149         __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
 150 };
 151
 152 struct mlx5e_rq_stats {
 153         u64 packets;
 154         u64 bytes;
 155         u64 csum_complete;
 156         u64 csum_complete_tail;
 157         u64 csum_complete_tail_slow;
 158         u64 csum_unnecessary;
 159         u64 csum_unnecessary_inner;
 160         u64 csum_none;
 161         u64 lro_packets;
 162         u64 lro_bytes;
 163         u64 ecn_mark;
 164         u64 removed_vlan_packets;
 165         u64 xdp_drop;
 166         u64 xdp_tx;
 167         u64 xdp_tx_full;
 168         u64 wqe_err;
 169         u64 mpwqe_filler;
 170         u64 buff_alloc_err;
 171         u64 cqe_compress_blks;
 172         u64 cqe_compress_pkts;
 173         u64 page_reuse;
 174         u64 cache_reuse;
 175         u64 cache_full;
 176         u64 cache_empty;
 177         u64 cache_busy;
 178         u64 cache_waive;
 179 };
 180
 181 struct mlx5e_sq_stats {
 182         /* commonly accessed in data path */
 183         u64 packets;
 184         u64 bytes;
 185         u64 xmit_more;
 186         u64 tso_packets;
 187         u64 tso_bytes;
 188         u64 tso_inner_packets;
 189         u64 tso_inner_bytes;
 190         u64 csum_partial;
 191         u64 csum_partial_inner;
 192         u64 added_vlan_packets;
 193         u64 nop;
 194         /* less likely accessed in data path */
 195         u64 csum_none;
 196         u64 stopped;
 197         u64 wake;
 198         u64 dropped;
 199 };
 200
 201 struct mlx5e_stats {
 202         struct mlx5e_sw_stats sw;
 203         struct mlx5e_qcounter_stats qcnt;
 204         struct mlx5e_vport_stats vport;
 205         struct mlx5e_pport_stats pport;
 206         struct rtnl_link_stats64 vf_vport;
 207         struct mlx5e_pcie_stats pcie;
 208 };
 209
 210 struct mlx5e_priv;
 211 struct mlx5e_stats_grp {
 212         int (*get_num_stats)(struct mlx5e_priv *priv);
 213         int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx);
 214         int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx);
 215 };
 216
 217 extern const struct mlx5e_stats_grp mlx5e_stats_grps[];
 218 extern const int mlx5e_num_stats_grps;
 219
 220 #endif /* __MLX5_EN_STATS_H__ */