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1 /*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <net/flow_dissector.h>
34 #include <net/sch_generic.h>
35 #include <net/pkt_cls.h>
36 #include <net/tc_act/tc_gact.h>
37 #include <net/tc_act/tc_skbedit.h>
38 #include <linux/mlx5/fs.h>
39 #include <linux/mlx5/device.h>
40 #include <linux/rhashtable.h>
41 #include <linux/refcount.h>
42 #include <linux/completion.h>
43 #include <net/tc_act/tc_mirred.h>
44 #include <net/tc_act/tc_vlan.h>
45 #include <net/tc_act/tc_tunnel_key.h>
46 #include <net/tc_act/tc_pedit.h>
47 #include <net/tc_act/tc_csum.h>
48 #include <net/arp.h>
49 #include <net/ipv6_stubs.h>
50 #include "en.h"
51 #include "en_rep.h"
52 #include "en_tc.h"
53 #include "eswitch.h"
54 #include "eswitch_offloads_chains.h"
55 #include "fs_core.h"
56 #include "en/port.h"
57 #include "en/tc_tun.h"
58 #include "en/mapping.h"
59 #include "en/tc_ct.h"
60 #include "lib/devcom.h"
61 #include "lib/geneve.h"
62 #include "diag/en_tc_tracepoint.h"
63
64 #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
65
66 struct mlx5_nic_flow_attr {
67 u32 action;
68 u32 flow_tag;
69 struct mlx5_modify_hdr *modify_hdr;
70 u32 hairpin_tirn;
71 u8 match_level;
72 struct mlx5_flow_table *hairpin_ft;
73 struct mlx5_fc *counter;
74 };
75
76 #define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
77
78 enum {
79 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
80 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
81 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
82 MLX5E_TC_FLOW_FLAG_FT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
83 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
84 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
85 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
86 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
87 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
88 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
89 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
90 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
91 MLX5E_TC_FLOW_FLAG_CT = MLX5E_TC_FLOW_BASE + 7,
92 };
93
94 #define MLX5E_TC_MAX_SPLITS 1
95
96 /* Helper struct for accessing a struct containing list_head array.
97 * Containing struct
98 * |- Helper array
99 * [0] Helper item 0
100 * |- list_head item 0
101 * |- index (0)
102 * [1] Helper item 1
103 * |- list_head item 1
104 * |- index (1)
105 * To access the containing struct from one of the list_head items:
106 * 1. Get the helper item from the list_head item using
107 * helper item =
108 * container_of(list_head item, helper struct type, list_head field)
109 * 2. Get the contining struct from the helper item and its index in the array:
110 * containing struct =
111 * container_of(helper item, containing struct type, helper field[index])
112 */
113 struct encap_flow_item {
114 struct mlx5e_encap_entry *e; /* attached encap instance */
115 struct list_head list;
116 int index;
117 };
118
119 struct mlx5e_tc_flow {
120 struct rhash_head node;
121 struct mlx5e_priv *priv;
122 u64 cookie;
123 unsigned long flags;
124 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
125 /* Flow can be associated with multiple encap IDs.
126 * The number of encaps is bounded by the number of supported
127 * destinations.
128 */
129 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
130 struct mlx5e_tc_flow *peer_flow;
131 struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
132 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
133 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
134 struct list_head hairpin; /* flows sharing the same hairpin */
135 struct list_head peer; /* flows with peer flow */
136 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
137 int tmp_efi_index;
138 struct list_head tmp_list; /* temporary flow list used by neigh update */
139 refcount_t refcnt;
140 struct rcu_head rcu_head;
141 struct completion init_done;
142 int tunnel_id; /* the mapped tunnel id of this flow */
143
144 union {
145 struct mlx5_esw_flow_attr esw_attr[0];
146 struct mlx5_nic_flow_attr nic_attr[0];
147 };
148 };
149
150 struct mlx5e_tc_flow_parse_attr {
151 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
152 struct net_device *filter_dev;
153 struct mlx5_flow_spec spec;
154 struct mlx5e_tc_mod_hdr_acts mod_hdr_acts;
155 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
156 };
157
158 #define MLX5E_TC_TABLE_NUM_GROUPS 4
159 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
160
161 struct tunnel_match_key {
162 struct flow_dissector_key_control enc_control;
163 struct flow_dissector_key_keyid enc_key_id;
164 struct flow_dissector_key_ports enc_tp;
165 struct flow_dissector_key_ip enc_ip;
166 union {
167 struct flow_dissector_key_ipv4_addrs enc_ipv4;
168 struct flow_dissector_key_ipv6_addrs enc_ipv6;
169 };
170
171 int filter_ifindex;
172 };
173
174 /* Tunnel_id mapping is TUNNEL_INFO_BITS + ENC_OPTS_BITS.
175 * Upper TUNNEL_INFO_BITS for general tunnel info.
176 * Lower ENC_OPTS_BITS bits for enc_opts.
177 */
178 #define TUNNEL_INFO_BITS 6
179 #define TUNNEL_INFO_BITS_MASK GENMASK(TUNNEL_INFO_BITS - 1, 0)
180 #define ENC_OPTS_BITS 2
181 #define ENC_OPTS_BITS_MASK GENMASK(ENC_OPTS_BITS - 1, 0)
182 #define TUNNEL_ID_BITS (TUNNEL_INFO_BITS + ENC_OPTS_BITS)
183 #define TUNNEL_ID_MASK GENMASK(TUNNEL_ID_BITS - 1, 0)
184
185 struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
186 [CHAIN_TO_REG] = {
187 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
188 .moffset = 0,
189 .mlen = 2,
190 },
191 [TUNNEL_TO_REG] = {
192 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
193 .moffset = 3,
194 .mlen = 1,
195 .soffset = MLX5_BYTE_OFF(fte_match_param,
196 misc_parameters_2.metadata_reg_c_1),
197 },
198 [ZONE_TO_REG] = zone_to_reg_ct,
199 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
200 [MARK_TO_REG] = mark_to_reg_ct,
201 [LABELS_TO_REG] = labels_to_reg_ct,
202 [FTEID_TO_REG] = fteid_to_reg_ct,
203 [TUPLEID_TO_REG] = tupleid_to_reg_ct,
204 };
205
206 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
207
208 void
209 mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
210 enum mlx5e_tc_attr_to_reg type,
211 u32 data,
212 u32 mask)
213 {
214 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
215 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
216 void *headers_c = spec->match_criteria;
217 void *headers_v = spec->match_value;
218 void *fmask, *fval;
219
220 fmask = headers_c + soffset;
221 fval = headers_v + soffset;
222
223 mask = cpu_to_be32(mask) >> (32 - (match_len * 8));
224 data = cpu_to_be32(data) >> (32 - (match_len * 8));
225
226 memcpy(fmask, &mask, match_len);
227 memcpy(fval, &data, match_len);
228
229 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
230 }
231
232 int
233 mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
234 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
235 enum mlx5e_tc_attr_to_reg type,
236 u32 data)
237 {
238 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
239 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
240 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
241 char *modact;
242 int err;
243
244 err = alloc_mod_hdr_actions(mdev, MLX5_FLOW_NAMESPACE_FDB,
245 mod_hdr_acts);
246 if (err)
247 return err;
248
249 modact = mod_hdr_acts->actions +
250 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
251
252 /* Firmware has 5bit length field and 0 means 32bits */
253 if (mlen == 4)
254 mlen = 0;
255
256 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
257 MLX5_SET(set_action_in, modact, field, mfield);
258 MLX5_SET(set_action_in, modact, offset, moffset * 8);
259 MLX5_SET(set_action_in, modact, length, mlen * 8);
260 MLX5_SET(set_action_in, modact, data, data);
261 mod_hdr_acts->num_actions++;
262
263 return 0;
264 }
265
266 struct mlx5e_hairpin {
267 struct mlx5_hairpin *pair;
268
269 struct mlx5_core_dev *func_mdev;
270 struct mlx5e_priv *func_priv;
271 u32 tdn;
272 u32 tirn;
273
274 int num_channels;
275 struct mlx5e_rqt indir_rqt;
276 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
277 struct mlx5e_ttc_table ttc;
278 };
279
280 struct mlx5e_hairpin_entry {
281 /* a node of a hash table which keeps all the hairpin entries */
282 struct hlist_node hairpin_hlist;
283
284 /* protects flows list */
285 spinlock_t flows_lock;
286 /* flows sharing the same hairpin */
287 struct list_head flows;
288 /* hpe's that were not fully initialized when dead peer update event
289 * function traversed them.
290 */
291 struct list_head dead_peer_wait_list;
292
293 u16 peer_vhca_id;
294 u8 prio;
295 struct mlx5e_hairpin *hp;
296 refcount_t refcnt;
297 struct completion res_ready;
298 };
299
300 struct mod_hdr_key {
301 int num_actions;
302 void *actions;
303 };
304
305 struct mlx5e_mod_hdr_entry {
306 /* a node of a hash table which keeps all the mod_hdr entries */
307 struct hlist_node mod_hdr_hlist;
308
309 /* protects flows list */
310 spinlock_t flows_lock;
311 /* flows sharing the same mod_hdr entry */
312 struct list_head flows;
313
314 struct mod_hdr_key key;
315
316 struct mlx5_modify_hdr *modify_hdr;
317
318 refcount_t refcnt;
319 struct completion res_ready;
320 int compl_result;
321 };
322
323 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
324 struct mlx5e_tc_flow *flow);
325
326 static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
327 {
328 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
329 return ERR_PTR(-EINVAL);
330 return flow;
331 }
332
333 static void mlx5e_flow_put(struct mlx5e_priv *priv,
334 struct mlx5e_tc_flow *flow)
335 {
336 if (refcount_dec_and_test(&flow->refcnt)) {
337 mlx5e_tc_del_flow(priv, flow);
338 kfree_rcu(flow, rcu_head);
339 }
340 }
341
342 static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
343 {
344 /* Complete all memory stores before setting bit. */
345 smp_mb__before_atomic();
346 set_bit(flag, &flow->flags);
347 }
348
349 #define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
350
351 static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
352 unsigned long flag)
353 {
354 /* test_and_set_bit() provides all necessary barriers */
355 return test_and_set_bit(flag, &flow->flags);
356 }
357
358 #define flow_flag_test_and_set(flow, flag) \
359 __flow_flag_test_and_set(flow, \
360 MLX5E_TC_FLOW_FLAG_##flag)
361
362 static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
363 {
364 /* Complete all memory stores before clearing bit. */
365 smp_mb__before_atomic();
366 clear_bit(flag, &flow->flags);
367 }
368
369 #define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
370 MLX5E_TC_FLOW_FLAG_##flag)
371
372 static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
373 {
374 bool ret = test_bit(flag, &flow->flags);
375
376 /* Read fields of flow structure only after checking flags. */
377 smp_mb__after_atomic();
378 return ret;
379 }
380
381 #define flow_flag_test(flow, flag) __flow_flag_test(flow, \
382 MLX5E_TC_FLOW_FLAG_##flag)
383
384 static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
385 {
386 return flow_flag_test(flow, ESWITCH);
387 }
388
389 static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
390 {
391 return flow_flag_test(flow, FT);
392 }
393
394 static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
395 {
396 return flow_flag_test(flow, OFFLOADED);
397 }
398
399 static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
400 {
401 return jhash(key->actions,
402 key->num_actions * MLX5_MH_ACT_SZ, 0);
403 }
404
405 static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
406 struct mod_hdr_key *b)
407 {
408 if (a->num_actions != b->num_actions)
409 return 1;
410
411 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
412 }
413
414 static struct mod_hdr_tbl *
415 get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
416 {
417 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
418
419 return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
420 &priv->fs.tc.mod_hdr;
421 }
422
423 static struct mlx5e_mod_hdr_entry *
424 mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
425 {
426 struct mlx5e_mod_hdr_entry *mh, *found = NULL;
427
428 hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
429 if (!cmp_mod_hdr_info(&mh->key, key)) {
430 refcount_inc(&mh->refcnt);
431 found = mh;
432 break;
433 }
434 }
435
436 return found;
437 }
438
439 static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
440 struct mlx5e_mod_hdr_entry *mh,
441 int namespace)
442 {
443 struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace);
444
445 if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock))
446 return;
447 hash_del(&mh->mod_hdr_hlist);
448 mutex_unlock(&tbl->lock);
449
450 WARN_ON(!list_empty(&mh->flows));
451 if (mh->compl_result > 0)
452 mlx5_modify_header_dealloc(priv->mdev, mh->modify_hdr);
453
454 kfree(mh);
455 }
456
457 static int get_flow_name_space(struct mlx5e_tc_flow *flow)
458 {
459 return mlx5e_is_eswitch_flow(flow) ?
460 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
461 }
462 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
463 struct mlx5e_tc_flow *flow,
464 struct mlx5e_tc_flow_parse_attr *parse_attr)
465 {
466 int num_actions, actions_size, namespace, err;
467 struct mlx5e_mod_hdr_entry *mh;
468 struct mod_hdr_tbl *tbl;
469 struct mod_hdr_key key;
470 u32 hash_key;
471
472 num_actions = parse_attr->mod_hdr_acts.num_actions;
473 actions_size = MLX5_MH_ACT_SZ * num_actions;
474
475 key.actions = parse_attr->mod_hdr_acts.actions;
476 key.num_actions = num_actions;
477
478 hash_key = hash_mod_hdr_info(&key);
479
480 namespace = get_flow_name_space(flow);
481 tbl = get_mod_hdr_table(priv, namespace);
482
483 mutex_lock(&tbl->lock);
484 mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
485 if (mh) {
486 mutex_unlock(&tbl->lock);
487 wait_for_completion(&mh->res_ready);
488
489 if (mh->compl_result < 0) {
490 err = -EREMOTEIO;
491 goto attach_header_err;
492 }
493 goto attach_flow;
494 }
495
496 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
497 if (!mh) {
498 mutex_unlock(&tbl->lock);
499 return -ENOMEM;
500 }
501
502 mh->key.actions = (void *)mh + sizeof(*mh);
503 memcpy(mh->key.actions, key.actions, actions_size);
504 mh->key.num_actions = num_actions;
505 spin_lock_init(&mh->flows_lock);
506 INIT_LIST_HEAD(&mh->flows);
507 refcount_set(&mh->refcnt, 1);
508 init_completion(&mh->res_ready);
509
510 hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
511 mutex_unlock(&tbl->lock);
512
513 mh->modify_hdr = mlx5_modify_header_alloc(priv->mdev, namespace,
514 mh->key.num_actions,
515 mh->key.actions);
516 if (IS_ERR(mh->modify_hdr)) {
517 err = PTR_ERR(mh->modify_hdr);
518 mh->compl_result = err;
519 goto alloc_header_err;
520 }
521 mh->compl_result = 1;
522 complete_all(&mh->res_ready);
523
524 attach_flow:
525 flow->mh = mh;
526 spin_lock(&mh->flows_lock);
527 list_add(&flow->mod_hdr, &mh->flows);
528 spin_unlock(&mh->flows_lock);
529 if (mlx5e_is_eswitch_flow(flow))
530 flow->esw_attr->modify_hdr = mh->modify_hdr;
531 else
532 flow->nic_attr->modify_hdr = mh->modify_hdr;
533
534 return 0;
535
536 alloc_header_err:
537 complete_all(&mh->res_ready);
538 attach_header_err:
539 mlx5e_mod_hdr_put(priv, mh, namespace);
540 return err;
541 }
542
543 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
544 struct mlx5e_tc_flow *flow)
545 {
546 /* flow wasn't fully initialized */
547 if (!flow->mh)
548 return;
549
550 spin_lock(&flow->mh->flows_lock);
551 list_del(&flow->mod_hdr);
552 spin_unlock(&flow->mh->flows_lock);
553
554 mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow));
555 flow->mh = NULL;
556 }
557
558 static
559 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
560 {
561 struct net_device *netdev;
562 struct mlx5e_priv *priv;
563
564 netdev = __dev_get_by_index(net, ifindex);
565 priv = netdev_priv(netdev);
566 return priv->mdev;
567 }
568
569 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
570 {
571 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
572 void *tirc;
573 int err;
574
575 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
576 if (err)
577 goto alloc_tdn_err;
578
579 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
580
581 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
582 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
583 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
584
585 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
586 if (err)
587 goto create_tir_err;
588
589 return 0;
590
591 create_tir_err:
592 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
593 alloc_tdn_err:
594 return err;
595 }
596
597 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
598 {
599 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
600 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
601 }
602
603 static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
604 {
605 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
606 struct mlx5e_priv *priv = hp->func_priv;
607 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
608
609 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
610 hp->num_channels);
611
612 for (i = 0; i < sz; i++) {
613 ix = i;
614 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
615 ix = mlx5e_bits_invert(i, ilog2(sz));
616 ix = indirection_rqt[ix];
617 rqn = hp->pair->rqn[ix];
618 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
619 }
620 }
621
622 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
623 {
624 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
625 struct mlx5e_priv *priv = hp->func_priv;
626 struct mlx5_core_dev *mdev = priv->mdev;
627 void *rqtc;
628 u32 *in;
629
630 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
631 in = kvzalloc(inlen, GFP_KERNEL);
632 if (!in)
633 return -ENOMEM;
634
635 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
636
637 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
638 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
639
640 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
641
642 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
643 if (!err)
644 hp->indir_rqt.enabled = true;
645
646 kvfree(in);
647 return err;
648 }
649
650 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
651 {
652 struct mlx5e_priv *priv = hp->func_priv;
653 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
654 int tt, i, err;
655 void *tirc;
656
657 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
658 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
659
660 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
661 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
662
663 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
664 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
665 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
666 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
667
668 err = mlx5_core_create_tir(hp->func_mdev, in,
669 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
670 if (err) {
671 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
672 goto err_destroy_tirs;
673 }
674 }
675 return 0;
676
677 err_destroy_tirs:
678 for (i = 0; i < tt; i++)
679 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
680 return err;
681 }
682
683 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
684 {
685 int tt;
686
687 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
688 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
689 }
690
691 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
692 struct ttc_params *ttc_params)
693 {
694 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
695 int tt;
696
697 memset(ttc_params, 0, sizeof(*ttc_params));
698
699 ttc_params->any_tt_tirn = hp->tirn;
700
701 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
702 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
703
704 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
705 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
706 ft_attr->prio = MLX5E_TC_PRIO;
707 }
708
709 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
710 {
711 struct mlx5e_priv *priv = hp->func_priv;
712 struct ttc_params ttc_params;
713 int err;
714
715 err = mlx5e_hairpin_create_indirect_rqt(hp);
716 if (err)
717 return err;
718
719 err = mlx5e_hairpin_create_indirect_tirs(hp);
720 if (err)
721 goto err_create_indirect_tirs;
722
723 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
724 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
725 if (err)
726 goto err_create_ttc_table;
727
728 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
729 hp->num_channels, hp->ttc.ft.t->id);
730
731 return 0;
732
733 err_create_ttc_table:
734 mlx5e_hairpin_destroy_indirect_tirs(hp);
735 err_create_indirect_tirs:
736 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
737
738 return err;
739 }
740
741 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
742 {
743 struct mlx5e_priv *priv = hp->func_priv;
744
745 mlx5e_destroy_ttc_table(priv, &hp->ttc);
746 mlx5e_hairpin_destroy_indirect_tirs(hp);
747 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
748 }
749
750 static struct mlx5e_hairpin *
751 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
752 int peer_ifindex)
753 {
754 struct mlx5_core_dev *func_mdev, *peer_mdev;
755 struct mlx5e_hairpin *hp;
756 struct mlx5_hairpin *pair;
757 int err;
758
759 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
760 if (!hp)
761 return ERR_PTR(-ENOMEM);
762
763 func_mdev = priv->mdev;
764 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
765
766 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
767 if (IS_ERR(pair)) {
768 err = PTR_ERR(pair);
769 goto create_pair_err;
770 }
771 hp->pair = pair;
772 hp->func_mdev = func_mdev;
773 hp->func_priv = priv;
774 hp->num_channels = params->num_channels;
775
776 err = mlx5e_hairpin_create_transport(hp);
777 if (err)
778 goto create_transport_err;
779
780 if (hp->num_channels > 1) {
781 err = mlx5e_hairpin_rss_init(hp);
782 if (err)
783 goto rss_init_err;
784 }
785
786 return hp;
787
788 rss_init_err:
789 mlx5e_hairpin_destroy_transport(hp);
790 create_transport_err:
791 mlx5_core_hairpin_destroy(hp->pair);
792 create_pair_err:
793 kfree(hp);
794 return ERR_PTR(err);
795 }
796
797 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
798 {
799 if (hp->num_channels > 1)
800 mlx5e_hairpin_rss_cleanup(hp);
801 mlx5e_hairpin_destroy_transport(hp);
802 mlx5_core_hairpin_destroy(hp->pair);
803 kvfree(hp);
804 }
805
806 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
807 {
808 return (peer_vhca_id << 16 | prio);
809 }
810
811 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
812 u16 peer_vhca_id, u8 prio)
813 {
814 struct mlx5e_hairpin_entry *hpe;
815 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
816
817 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
818 hairpin_hlist, hash_key) {
819 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
820 refcount_inc(&hpe->refcnt);
821 return hpe;
822 }
823 }
824
825 return NULL;
826 }
827
828 static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
829 struct mlx5e_hairpin_entry *hpe)
830 {
831 /* no more hairpin flows for us, release the hairpin pair */
832 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
833 return;
834 hash_del(&hpe->hairpin_hlist);
835 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
836
837 if (!IS_ERR_OR_NULL(hpe->hp)) {
838 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
839 dev_name(hpe->hp->pair->peer_mdev->device));
840
841 mlx5e_hairpin_destroy(hpe->hp);
842 }
843
844 WARN_ON(!list_empty(&hpe->flows));
845 kfree(hpe);
846 }
847
848 #define UNKNOWN_MATCH_PRIO 8
849
850 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
851 struct mlx5_flow_spec *spec, u8 *match_prio,
852 struct netlink_ext_ack *extack)
853 {
854 void *headers_c, *headers_v;
855 u8 prio_val, prio_mask = 0;
856 bool vlan_present;
857
858 #ifdef CONFIG_MLX5_CORE_EN_DCB
859 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
860 NL_SET_ERR_MSG_MOD(extack,
861 "only PCP trust state supported for hairpin");
862 return -EOPNOTSUPP;
863 }
864 #endif
865 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
866 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
867
868 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
869 if (vlan_present) {
870 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
871 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
872 }
873
874 if (!vlan_present || !prio_mask) {
875 prio_val = UNKNOWN_MATCH_PRIO;
876 } else if (prio_mask != 0x7) {
877 NL_SET_ERR_MSG_MOD(extack,
878 "masked priority match not supported for hairpin");
879 return -EOPNOTSUPP;
880 }
881
882 *match_prio = prio_val;
883 return 0;
884 }
885
886 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
887 struct mlx5e_tc_flow *flow,
888 struct mlx5e_tc_flow_parse_attr *parse_attr,
889 struct netlink_ext_ack *extack)
890 {
891 int peer_ifindex = parse_attr->mirred_ifindex[0];
892 struct mlx5_hairpin_params params;
893 struct mlx5_core_dev *peer_mdev;
894 struct mlx5e_hairpin_entry *hpe;
895 struct mlx5e_hairpin *hp;
896 u64 link_speed64;
897 u32 link_speed;
898 u8 match_prio;
899 u16 peer_id;
900 int err;
901
902 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
903 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
904 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
905 return -EOPNOTSUPP;
906 }
907
908 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
909 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
910 extack);
911 if (err)
912 return err;
913
914 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
915 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
916 if (hpe) {
917 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
918 wait_for_completion(&hpe->res_ready);
919
920 if (IS_ERR(hpe->hp)) {
921 err = -EREMOTEIO;
922 goto out_err;
923 }
924 goto attach_flow;
925 }
926
927 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
928 if (!hpe) {
929 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
930 return -ENOMEM;
931 }
932
933 spin_lock_init(&hpe->flows_lock);
934 INIT_LIST_HEAD(&hpe->flows);
935 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
936 hpe->peer_vhca_id = peer_id;
937 hpe->prio = match_prio;
938 refcount_set(&hpe->refcnt, 1);
939 init_completion(&hpe->res_ready);
940
941 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
942 hash_hairpin_info(peer_id, match_prio));
943 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
944
945 params.log_data_size = 15;
946 params.log_data_size = min_t(u8, params.log_data_size,
947 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
948 params.log_data_size = max_t(u8, params.log_data_size,
949 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
950
951 params.log_num_packets = params.log_data_size -
952 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
953 params.log_num_packets = min_t(u8, params.log_num_packets,
954 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
955
956 params.q_counter = priv->q_counter;
957 /* set hairpin pair per each 50Gbs share of the link */
958 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
959 link_speed = max_t(u32, link_speed, 50000);
960 link_speed64 = link_speed;
961 do_div(link_speed64, 50000);
962 params.num_channels = link_speed64;
963
964 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
965 hpe->hp = hp;
966 complete_all(&hpe->res_ready);
967 if (IS_ERR(hp)) {
968 err = PTR_ERR(hp);
969 goto out_err;
970 }
971
972 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
973 hp->tirn, hp->pair->rqn[0],
974 dev_name(hp->pair->peer_mdev->device),
975 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
976
977 attach_flow:
978 if (hpe->hp->num_channels > 1) {
979 flow_flag_set(flow, HAIRPIN_RSS);
980 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
981 } else {
982 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
983 }
984
985 flow->hpe = hpe;
986 spin_lock(&hpe->flows_lock);
987 list_add(&flow->hairpin, &hpe->flows);
988 spin_unlock(&hpe->flows_lock);
989
990 return 0;
991
992 out_err:
993 mlx5e_hairpin_put(priv, hpe);
994 return err;
995 }
996
997 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
998 struct mlx5e_tc_flow *flow)
999 {
1000 /* flow wasn't fully initialized */
1001 if (!flow->hpe)
1002 return;
1003
1004 spin_lock(&flow->hpe->flows_lock);
1005 list_del(&flow->hairpin);
1006 spin_unlock(&flow->hpe->flows_lock);
1007
1008 mlx5e_hairpin_put(priv, flow->hpe);
1009 flow->hpe = NULL;
1010 }
1011
1012 static int
1013 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1014 struct mlx5e_tc_flow_parse_attr *parse_attr,
1015 struct mlx5e_tc_flow *flow,
1016 struct netlink_ext_ack *extack)
1017 {
1018 struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
1019 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
1020 struct mlx5_core_dev *dev = priv->mdev;
1021 struct mlx5_flow_destination dest[2] = {};
1022 struct mlx5_flow_act flow_act = {
1023 .action = attr->action,
1024 .flags = FLOW_ACT_NO_APPEND,
1025 };
1026 struct mlx5_fc *counter = NULL;
1027 int err, dest_ix = 0;
1028
1029 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1030 flow_context->flow_tag = attr->flow_tag;
1031
1032 if (flow_flag_test(flow, HAIRPIN)) {
1033 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1034 if (err)
1035 return err;
1036
1037 if (flow_flag_test(flow, HAIRPIN_RSS)) {
1038 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1039 dest[dest_ix].ft = attr->hairpin_ft;
1040 } else {
1041 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1042 dest[dest_ix].tir_num = attr->hairpin_tirn;
1043 }
1044 dest_ix++;
1045 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1046 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1047 dest[dest_ix].ft = priv->fs.vlan.ft.t;
1048 dest_ix++;
1049 }
1050
1051 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1052 counter = mlx5_fc_create(dev, true);
1053 if (IS_ERR(counter))
1054 return PTR_ERR(counter);
1055
1056 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
1057 dest[dest_ix].counter_id = mlx5_fc_id(counter);
1058 dest_ix++;
1059 attr->counter = counter;
1060 }
1061
1062 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1063 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1064 flow_act.modify_hdr = attr->modify_hdr;
1065 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1066 if (err)
1067 return err;
1068 }
1069
1070 mutex_lock(&priv->fs.tc.t_lock);
1071 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
1072 struct mlx5_flow_table_attr ft_attr = {};
1073 int tc_grp_size, tc_tbl_size, tc_num_grps;
1074 u32 max_flow_counter;
1075
1076 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
1077 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
1078
1079 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
1080
1081 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
1082 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
1083 tc_num_grps = MLX5E_TC_TABLE_NUM_GROUPS;
1084
1085 ft_attr.prio = MLX5E_TC_PRIO;
1086 ft_attr.max_fte = tc_tbl_size;
1087 ft_attr.level = MLX5E_TC_FT_LEVEL;
1088 ft_attr.autogroup.max_num_groups = tc_num_grps;
1089 priv->fs.tc.t =
1090 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
1091 &ft_attr);
1092 if (IS_ERR(priv->fs.tc.t)) {
1093 mutex_unlock(&priv->fs.tc.t_lock);
1094 NL_SET_ERR_MSG_MOD(extack,
1095 "Failed to create tc offload table\n");
1096 netdev_err(priv->netdev,
1097 "Failed to create tc offload table\n");
1098 return PTR_ERR(priv->fs.tc.t);
1099 }
1100 }
1101
1102 if (attr->match_level != MLX5_MATCH_NONE)
1103 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
1104
1105 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
1106 &flow_act, dest, dest_ix);
1107 mutex_unlock(&priv->fs.tc.t_lock);
1108
1109 return PTR_ERR_OR_ZERO(flow->rule[0]);
1110 }
1111
1112 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1113 struct mlx5e_tc_flow *flow)
1114 {
1115 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
1116 struct mlx5_fc *counter = NULL;
1117
1118 counter = attr->counter;
1119 if (!IS_ERR_OR_NULL(flow->rule[0]))
1120 mlx5_del_flow_rules(flow->rule[0]);
1121 mlx5_fc_destroy(priv->mdev, counter);
1122
1123 mutex_lock(&priv->fs.tc.t_lock);
1124 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
1125 mlx5_destroy_flow_table(priv->fs.tc.t);
1126 priv->fs.tc.t = NULL;
1127 }
1128 mutex_unlock(&priv->fs.tc.t_lock);
1129
1130 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1131 mlx5e_detach_mod_hdr(priv, flow);
1132
1133 if (flow_flag_test(flow, HAIRPIN))
1134 mlx5e_hairpin_flow_del(priv, flow);
1135 }
1136
1137 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1138 struct mlx5e_tc_flow *flow, int out_index);
1139
1140 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1141 struct mlx5e_tc_flow *flow,
1142 struct net_device *mirred_dev,
1143 int out_index,
1144 struct netlink_ext_ack *extack,
1145 struct net_device **encap_dev,
1146 bool *encap_valid);
1147
1148 static struct mlx5_flow_handle *
1149 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1150 struct mlx5e_tc_flow *flow,
1151 struct mlx5_flow_spec *spec,
1152 struct mlx5_esw_flow_attr *attr)
1153 {
1154 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1155 struct mlx5_flow_handle *rule;
1156
1157 if (flow_flag_test(flow, CT)) {
1158 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1159
1160 return mlx5_tc_ct_flow_offload(flow->priv, flow, spec, attr,
1161 mod_hdr_acts);
1162 }
1163
1164 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1165 if (IS_ERR(rule))
1166 return rule;
1167
1168 if (attr->split_count) {
1169 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1170 if (IS_ERR(flow->rule[1])) {
1171 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1172 return flow->rule[1];
1173 }
1174 }
1175
1176 return rule;
1177 }
1178
1179 static void
1180 mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1181 struct mlx5e_tc_flow *flow,
1182 struct mlx5_esw_flow_attr *attr)
1183 {
1184 flow_flag_clear(flow, OFFLOADED);
1185
1186 if (flow_flag_test(flow, CT)) {
1187 mlx5_tc_ct_delete_flow(flow->priv, flow, attr);
1188 return;
1189 }
1190
1191 if (attr->split_count)
1192 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1193
1194 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1195 }
1196
1197 static struct mlx5_flow_handle *
1198 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1199 struct mlx5e_tc_flow *flow,
1200 struct mlx5_flow_spec *spec)
1201 {
1202 struct mlx5_esw_flow_attr slow_attr;
1203 struct mlx5_flow_handle *rule;
1204
1205 memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1206 slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1207 slow_attr.split_count = 0;
1208 slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1209
1210 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, &slow_attr);
1211 if (!IS_ERR(rule))
1212 flow_flag_set(flow, SLOW);
1213
1214 return rule;
1215 }
1216
1217 static void
1218 mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1219 struct mlx5e_tc_flow *flow)
1220 {
1221 struct mlx5_esw_flow_attr slow_attr;
1222
1223 memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1224 slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1225 slow_attr.split_count = 0;
1226 slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1227 mlx5e_tc_unoffload_fdb_rules(esw, flow, &slow_attr);
1228 flow_flag_clear(flow, SLOW);
1229 }
1230
1231 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1232 * function.
1233 */
1234 static void unready_flow_add(struct mlx5e_tc_flow *flow,
1235 struct list_head *unready_flows)
1236 {
1237 flow_flag_set(flow, NOT_READY);
1238 list_add_tail(&flow->unready, unready_flows);
1239 }
1240
1241 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1242 * function.
1243 */
1244 static void unready_flow_del(struct mlx5e_tc_flow *flow)
1245 {
1246 list_del(&flow->unready);
1247 flow_flag_clear(flow, NOT_READY);
1248 }
1249
1250 static void add_unready_flow(struct mlx5e_tc_flow *flow)
1251 {
1252 struct mlx5_rep_uplink_priv *uplink_priv;
1253 struct mlx5e_rep_priv *rpriv;
1254 struct mlx5_eswitch *esw;
1255
1256 esw = flow->priv->mdev->priv.eswitch;
1257 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1258 uplink_priv = &rpriv->uplink_priv;
1259
1260 mutex_lock(&uplink_priv->unready_flows_lock);
1261 unready_flow_add(flow, &uplink_priv->unready_flows);
1262 mutex_unlock(&uplink_priv->unready_flows_lock);
1263 }
1264
1265 static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1266 {
1267 struct mlx5_rep_uplink_priv *uplink_priv;
1268 struct mlx5e_rep_priv *rpriv;
1269 struct mlx5_eswitch *esw;
1270
1271 esw = flow->priv->mdev->priv.eswitch;
1272 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1273 uplink_priv = &rpriv->uplink_priv;
1274
1275 mutex_lock(&uplink_priv->unready_flows_lock);
1276 unready_flow_del(flow);
1277 mutex_unlock(&uplink_priv->unready_flows_lock);
1278 }
1279
1280 static int
1281 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1282 struct mlx5e_tc_flow *flow,
1283 struct netlink_ext_ack *extack)
1284 {
1285 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1286 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1287 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1288 struct net_device *out_dev, *encap_dev = NULL;
1289 struct mlx5_fc *counter = NULL;
1290 struct mlx5e_rep_priv *rpriv;
1291 struct mlx5e_priv *out_priv;
1292 bool encap_valid = true;
1293 u32 max_prio, max_chain;
1294 int err = 0;
1295 int out_index;
1296
1297 if (!mlx5_esw_chains_prios_supported(esw) && attr->prio != 1) {
1298 NL_SET_ERR_MSG_MOD(extack,
1299 "E-switch priorities unsupported, upgrade FW");
1300 return -EOPNOTSUPP;
1301 }
1302
1303 /* We check chain range only for tc flows.
1304 * For ft flows, we checked attr->chain was originally 0 and set it to
1305 * FDB_FT_CHAIN which is outside tc range.
1306 * See mlx5e_rep_setup_ft_cb().
1307 */
1308 max_chain = mlx5_esw_chains_get_chain_range(esw);
1309 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
1310 NL_SET_ERR_MSG_MOD(extack,
1311 "Requested chain is out of supported range");
1312 return -EOPNOTSUPP;
1313 }
1314
1315 max_prio = mlx5_esw_chains_get_prio_range(esw);
1316 if (attr->prio > max_prio) {
1317 NL_SET_ERR_MSG_MOD(extack,
1318 "Requested priority is out of supported range");
1319 return -EOPNOTSUPP;
1320 }
1321
1322 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1323 int mirred_ifindex;
1324
1325 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1326 continue;
1327
1328 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
1329 out_dev = __dev_get_by_index(dev_net(priv->netdev),
1330 mirred_ifindex);
1331 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
1332 extack, &encap_dev, &encap_valid);
1333 if (err)
1334 return err;
1335
1336 out_priv = netdev_priv(encap_dev);
1337 rpriv = out_priv->ppriv;
1338 attr->dests[out_index].rep = rpriv->rep;
1339 attr->dests[out_index].mdev = out_priv->mdev;
1340 }
1341
1342 err = mlx5_eswitch_add_vlan_action(esw, attr);
1343 if (err)
1344 return err;
1345
1346 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1347 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1348 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1349 if (err)
1350 return err;
1351 }
1352
1353 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1354 counter = mlx5_fc_create(attr->counter_dev, true);
1355 if (IS_ERR(counter))
1356 return PTR_ERR(counter);
1357
1358 attr->counter = counter;
1359 }
1360
1361 /* we get here if one of the following takes place:
1362 * (1) there's no error
1363 * (2) there's an encap action and we don't have valid neigh
1364 */
1365 if (!encap_valid)
1366 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
1367 else
1368 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
1369
1370 if (IS_ERR(flow->rule[0]))
1371 return PTR_ERR(flow->rule[0]);
1372 else
1373 flow_flag_set(flow, OFFLOADED);
1374
1375 return 0;
1376 }
1377
1378 static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1379 {
1380 struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1381 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1382 spec->match_value,
1383 misc_parameters_3);
1384 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1385 headers_v,
1386 geneve_tlv_option_0_data);
1387
1388 return !!geneve_tlv_opt_0_data;
1389 }
1390
1391 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1392 struct mlx5e_tc_flow *flow)
1393 {
1394 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1395 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1396 int out_index;
1397
1398 mlx5e_put_flow_tunnel_id(flow);
1399
1400 if (flow_flag_test(flow, NOT_READY)) {
1401 remove_unready_flow(flow);
1402 kvfree(attr->parse_attr);
1403 return;
1404 }
1405
1406 if (mlx5e_is_offloaded_flow(flow)) {
1407 if (flow_flag_test(flow, SLOW))
1408 mlx5e_tc_unoffload_from_slow_path(esw, flow);
1409 else
1410 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1411 }
1412
1413 if (mlx5_flow_has_geneve_opt(flow))
1414 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1415
1416 mlx5_eswitch_del_vlan_action(esw, attr);
1417
1418 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1419 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
1420 mlx5e_detach_encap(priv, flow, out_index);
1421 kfree(attr->parse_attr->tun_info[out_index]);
1422 }
1423 kvfree(attr->parse_attr);
1424
1425 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1426 mlx5e_detach_mod_hdr(priv, flow);
1427
1428 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1429 mlx5_fc_destroy(attr->counter_dev, attr->counter);
1430 }
1431
1432 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1433 struct mlx5e_encap_entry *e,
1434 struct list_head *flow_list)
1435 {
1436 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1437 struct mlx5_esw_flow_attr *esw_attr;
1438 struct mlx5_flow_handle *rule;
1439 struct mlx5_flow_spec *spec;
1440 struct mlx5e_tc_flow *flow;
1441 int err;
1442
1443 e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1444 e->reformat_type,
1445 e->encap_size, e->encap_header,
1446 MLX5_FLOW_NAMESPACE_FDB);
1447 if (IS_ERR(e->pkt_reformat)) {
1448 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1449 PTR_ERR(e->pkt_reformat));
1450 return;
1451 }
1452 e->flags |= MLX5_ENCAP_ENTRY_VALID;
1453 mlx5e_rep_queue_neigh_stats_work(priv);
1454
1455 list_for_each_entry(flow, flow_list, tmp_list) {
1456 bool all_flow_encaps_valid = true;
1457 int i;
1458
1459 if (!mlx5e_is_offloaded_flow(flow))
1460 continue;
1461 esw_attr = flow->esw_attr;
1462 spec = &esw_attr->parse_attr->spec;
1463
1464 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
1465 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1466 /* Flow can be associated with multiple encap entries.
1467 * Before offloading the flow verify that all of them have
1468 * a valid neighbour.
1469 */
1470 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1471 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1472 continue;
1473 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1474 all_flow_encaps_valid = false;
1475 break;
1476 }
1477 }
1478 /* Do not offload flows with unresolved neighbors */
1479 if (!all_flow_encaps_valid)
1480 continue;
1481 /* update from slow path rule to encap rule */
1482 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1483 if (IS_ERR(rule)) {
1484 err = PTR_ERR(rule);
1485 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1486 err);
1487 continue;
1488 }
1489
1490 mlx5e_tc_unoffload_from_slow_path(esw, flow);
1491 flow->rule[0] = rule;
1492 /* was unset when slow path rule removed */
1493 flow_flag_set(flow, OFFLOADED);
1494 }
1495 }
1496
1497 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1498 struct mlx5e_encap_entry *e,
1499 struct list_head *flow_list)
1500 {
1501 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1502 struct mlx5_flow_handle *rule;
1503 struct mlx5_flow_spec *spec;
1504 struct mlx5e_tc_flow *flow;
1505 int err;
1506
1507 list_for_each_entry(flow, flow_list, tmp_list) {
1508 if (!mlx5e_is_offloaded_flow(flow))
1509 continue;
1510 spec = &flow->esw_attr->parse_attr->spec;
1511
1512 /* update from encap rule to slow path rule */
1513 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);
1514 /* mark the flow's encap dest as non-valid */
1515 flow->esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
1516
1517 if (IS_ERR(rule)) {
1518 err = PTR_ERR(rule);
1519 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1520 err);
1521 continue;
1522 }
1523
1524 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1525 flow->rule[0] = rule;
1526 /* was unset when fast path rule removed */
1527 flow_flag_set(flow, OFFLOADED);
1528 }
1529
1530 /* we know that the encap is valid */
1531 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1532 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
1533 }
1534
1535 static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1536 {
1537 if (mlx5e_is_eswitch_flow(flow))
1538 return flow->esw_attr->counter;
1539 else
1540 return flow->nic_attr->counter;
1541 }
1542
1543 /* Takes reference to all flows attached to encap and adds the flows to
1544 * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1545 */
1546 void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1547 {
1548 struct encap_flow_item *efi;
1549 struct mlx5e_tc_flow *flow;
1550
1551 list_for_each_entry(efi, &e->flows, list) {
1552 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1553 if (IS_ERR(mlx5e_flow_get(flow)))
1554 continue;
1555 wait_for_completion(&flow->init_done);
1556
1557 flow->tmp_efi_index = efi->index;
1558 list_add(&flow->tmp_list, flow_list);
1559 }
1560 }
1561
1562 /* Iterate over tmp_list of flows attached to flow_list head. */
1563 void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
1564 {
1565 struct mlx5e_tc_flow *flow, *tmp;
1566
1567 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1568 mlx5e_flow_put(priv, flow);
1569 }
1570
1571 static struct mlx5e_encap_entry *
1572 mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1573 struct mlx5e_encap_entry *e)
1574 {
1575 struct mlx5e_encap_entry *next = NULL;
1576
1577 retry:
1578 rcu_read_lock();
1579
1580 /* find encap with non-zero reference counter value */
1581 for (next = e ?
1582 list_next_or_null_rcu(&nhe->encap_list,
1583 &e->encap_list,
1584 struct mlx5e_encap_entry,
1585 encap_list) :
1586 list_first_or_null_rcu(&nhe->encap_list,
1587 struct mlx5e_encap_entry,
1588 encap_list);
1589 next;
1590 next = list_next_or_null_rcu(&nhe->encap_list,
1591 &next->encap_list,
1592 struct mlx5e_encap_entry,
1593 encap_list))
1594 if (mlx5e_encap_take(next))
1595 break;
1596
1597 rcu_read_unlock();
1598
1599 /* release starting encap */
1600 if (e)
1601 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1602 if (!next)
1603 return next;
1604
1605 /* wait for encap to be fully initialized */
1606 wait_for_completion(&next->res_ready);
1607 /* continue searching if encap entry is not in valid state after completion */
1608 if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1609 e = next;
1610 goto retry;
1611 }
1612
1613 return next;
1614 }
1615
1616 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1617 {
1618 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1619 struct mlx5e_encap_entry *e = NULL;
1620 struct mlx5e_tc_flow *flow;
1621 struct mlx5_fc *counter;
1622 struct neigh_table *tbl;
1623 bool neigh_used = false;
1624 struct neighbour *n;
1625 u64 lastuse;
1626
1627 if (m_neigh->family == AF_INET)
1628 tbl = &arp_tbl;
1629 #if IS_ENABLED(CONFIG_IPV6)
1630 else if (m_neigh->family == AF_INET6)
1631 tbl = ipv6_stub->nd_tbl;
1632 #endif
1633 else
1634 return;
1635
1636 /* mlx5e_get_next_valid_encap() releases previous encap before returning
1637 * next one.
1638 */
1639 while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
1640 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
1641 struct encap_flow_item *efi, *tmp;
1642 struct mlx5_eswitch *esw;
1643 LIST_HEAD(flow_list);
1644
1645 esw = priv->mdev->priv.eswitch;
1646 mutex_lock(&esw->offloads.encap_tbl_lock);
1647 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
1648 flow = container_of(efi, struct mlx5e_tc_flow,
1649 encaps[efi->index]);
1650 if (IS_ERR(mlx5e_flow_get(flow)))
1651 continue;
1652 list_add(&flow->tmp_list, &flow_list);
1653
1654 if (mlx5e_is_offloaded_flow(flow)) {
1655 counter = mlx5e_tc_get_counter(flow);
1656 lastuse = mlx5_fc_query_lastuse(counter);
1657 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1658 neigh_used = true;
1659 break;
1660 }
1661 }
1662 }
1663 mutex_unlock(&esw->offloads.encap_tbl_lock);
1664
1665 mlx5e_put_encap_flow_list(priv, &flow_list);
1666 if (neigh_used) {
1667 /* release current encap before breaking the loop */
1668 mlx5e_encap_put(priv, e);
1669 break;
1670 }
1671 }
1672
1673 trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1674
1675 if (neigh_used) {
1676 nhe->reported_lastuse = jiffies;
1677
1678 /* find the relevant neigh according to the cached device and
1679 * dst ip pair
1680 */
1681 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
1682 if (!n)
1683 return;
1684
1685 neigh_event_send(n, NULL);
1686 neigh_release(n);
1687 }
1688 }
1689
1690 static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1691 {
1692 WARN_ON(!list_empty(&e->flows));
1693
1694 if (e->compl_result > 0) {
1695 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1696
1697 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1698 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
1699 }
1700
1701 kfree(e->tun_info);
1702 kfree(e->encap_header);
1703 kfree_rcu(e, rcu);
1704 }
1705
1706 void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1707 {
1708 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1709
1710 if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1711 return;
1712 hash_del_rcu(&e->encap_hlist);
1713 mutex_unlock(&esw->offloads.encap_tbl_lock);
1714
1715 mlx5e_encap_dealloc(priv, e);
1716 }
1717
1718 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1719 struct mlx5e_tc_flow *flow, int out_index)
1720 {
1721 struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1722 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1723
1724 /* flow wasn't fully initialized */
1725 if (!e)
1726 return;
1727
1728 mutex_lock(&esw->offloads.encap_tbl_lock);
1729 list_del(&flow->encaps[out_index].list);
1730 flow->encaps[out_index].e = NULL;
1731 if (!refcount_dec_and_test(&e->refcnt)) {
1732 mutex_unlock(&esw->offloads.encap_tbl_lock);
1733 return;
1734 }
1735 hash_del_rcu(&e->encap_hlist);
1736 mutex_unlock(&esw->offloads.encap_tbl_lock);
1737
1738 mlx5e_encap_dealloc(priv, e);
1739 }
1740
1741 static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1742 {
1743 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1744
1745 if (!flow_flag_test(flow, ESWITCH) ||
1746 !flow_flag_test(flow, DUP))
1747 return;
1748
1749 mutex_lock(&esw->offloads.peer_mutex);
1750 list_del(&flow->peer);
1751 mutex_unlock(&esw->offloads.peer_mutex);
1752
1753 flow_flag_clear(flow, DUP);
1754
1755 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1756 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1757 kfree(flow->peer_flow);
1758 }
1759
1760 flow->peer_flow = NULL;
1761 }
1762
1763 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1764 {
1765 struct mlx5_core_dev *dev = flow->priv->mdev;
1766 struct mlx5_devcom *devcom = dev->priv.devcom;
1767 struct mlx5_eswitch *peer_esw;
1768
1769 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1770 if (!peer_esw)
1771 return;
1772
1773 __mlx5e_tc_del_fdb_peer_flow(flow);
1774 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1775 }
1776
1777 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
1778 struct mlx5e_tc_flow *flow)
1779 {
1780 if (mlx5e_is_eswitch_flow(flow)) {
1781 mlx5e_tc_del_fdb_peer_flow(flow);
1782 mlx5e_tc_del_fdb_flow(priv, flow);
1783 } else {
1784 mlx5e_tc_del_nic_flow(priv, flow);
1785 }
1786 }
1787
1788 static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1789 {
1790 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1791 struct flow_action *flow_action = &rule->action;
1792 const struct flow_action_entry *act;
1793 int i;
1794
1795 flow_action_for_each(i, act, flow_action) {
1796 switch (act->id) {
1797 case FLOW_ACTION_GOTO:
1798 return true;
1799 default:
1800 continue;
1801 }
1802 }
1803
1804 return false;
1805 }
1806
1807 static int
1808 enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1809 struct flow_dissector_key_enc_opts *opts,
1810 struct netlink_ext_ack *extack,
1811 bool *dont_care)
1812 {
1813 struct geneve_opt *opt;
1814 int off = 0;
1815
1816 *dont_care = true;
1817
1818 while (opts->len > off) {
1819 opt = (struct geneve_opt *)&opts->data[off];
1820
1821 if (!(*dont_care) || opt->opt_class || opt->type ||
1822 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1823 *dont_care = false;
1824
1825 if (opt->opt_class != U16_MAX ||
1826 opt->type != U8_MAX ||
1827 memchr_inv(opt->opt_data, 0xFF,
1828 opt->length * 4)) {
1829 NL_SET_ERR_MSG(extack,
1830 "Partial match of tunnel options in chain > 0 isn't supported");
1831 netdev_warn(priv->netdev,
1832 "Partial match of tunnel options in chain > 0 isn't supported");
1833 return -EOPNOTSUPP;
1834 }
1835 }
1836
1837 off += sizeof(struct geneve_opt) + opt->length * 4;
1838 }
1839
1840 return 0;
1841 }
1842
1843 #define COPY_DISSECTOR(rule, diss_key, dst)\
1844 ({ \
1845 struct flow_rule *__rule = (rule);\
1846 typeof(dst) __dst = dst;\
1847 \
1848 memcpy(__dst,\
1849 skb_flow_dissector_target(__rule->match.dissector,\
1850 diss_key,\
1851 __rule->match.key),\
1852 sizeof(*__dst));\
1853 })
1854
1855 static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1856 struct mlx5e_tc_flow *flow,
1857 struct flow_cls_offload *f,
1858 struct net_device *filter_dev)
1859 {
1860 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1861 struct netlink_ext_ack *extack = f->common.extack;
1862 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1863 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1864 struct flow_match_enc_opts enc_opts_match;
1865 struct mlx5_rep_uplink_priv *uplink_priv;
1866 struct mlx5e_rep_priv *uplink_rpriv;
1867 struct tunnel_match_key tunnel_key;
1868 bool enc_opts_is_dont_care = true;
1869 u32 tun_id, enc_opts_id = 0;
1870 struct mlx5_eswitch *esw;
1871 u32 value, mask;
1872 int err;
1873
1874 esw = priv->mdev->priv.eswitch;
1875 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1876 uplink_priv = &uplink_rpriv->uplink_priv;
1877
1878 memset(&tunnel_key, 0, sizeof(tunnel_key));
1879 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1880 &tunnel_key.enc_control);
1881 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1882 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1883 &tunnel_key.enc_ipv4);
1884 else
1885 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1886 &tunnel_key.enc_ipv6);
1887 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1888 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1889 &tunnel_key.enc_tp);
1890 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1891 &tunnel_key.enc_key_id);
1892 tunnel_key.filter_ifindex = filter_dev->ifindex;
1893
1894 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1895 if (err)
1896 return err;
1897
1898 flow_rule_match_enc_opts(rule, &enc_opts_match);
1899 err = enc_opts_is_dont_care_or_full_match(priv,
1900 enc_opts_match.mask,
1901 extack,
1902 &enc_opts_is_dont_care);
1903 if (err)
1904 goto err_enc_opts;
1905
1906 if (!enc_opts_is_dont_care) {
1907 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
1908 enc_opts_match.key, &enc_opts_id);
1909 if (err)
1910 goto err_enc_opts;
1911 }
1912
1913 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1914 mask = enc_opts_id ? TUNNEL_ID_MASK :
1915 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
1916
1917 if (attr->chain) {
1918 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1919 TUNNEL_TO_REG, value, mask);
1920 } else {
1921 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1922 err = mlx5e_tc_match_to_reg_set(priv->mdev,
1923 mod_hdr_acts,
1924 TUNNEL_TO_REG, value);
1925 if (err)
1926 goto err_set;
1927
1928 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1929 }
1930
1931 flow->tunnel_id = value;
1932 return 0;
1933
1934 err_set:
1935 if (enc_opts_id)
1936 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1937 enc_opts_id);
1938 err_enc_opts:
1939 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1940 return err;
1941 }
1942
1943 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1944 {
1945 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1946 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1947 struct mlx5_rep_uplink_priv *uplink_priv;
1948 struct mlx5e_rep_priv *uplink_rpriv;
1949 struct mlx5_eswitch *esw;
1950
1951 esw = flow->priv->mdev->priv.eswitch;
1952 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1953 uplink_priv = &uplink_rpriv->uplink_priv;
1954
1955 if (tun_id)
1956 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1957 if (enc_opts_id)
1958 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1959 enc_opts_id);
1960 }
1961
1962 u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1963 {
1964 return flow->tunnel_id;
1965 }
1966
1967 static int parse_tunnel_attr(struct mlx5e_priv *priv,
1968 struct mlx5e_tc_flow *flow,
1969 struct mlx5_flow_spec *spec,
1970 struct flow_cls_offload *f,
1971 struct net_device *filter_dev,
1972 u8 *match_level,
1973 bool *match_inner)
1974 {
1975 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1976 struct netlink_ext_ack *extack = f->common.extack;
1977 bool needs_mapping, sets_mapping;
1978 int err;
1979
1980 if (!mlx5e_is_eswitch_flow(flow))
1981 return -EOPNOTSUPP;
1982
1983 needs_mapping = !!flow->esw_attr->chain;
1984 sets_mapping = !flow->esw_attr->chain && flow_has_tc_fwd_action(f);
1985 *match_inner = !needs_mapping;
1986
1987 if ((needs_mapping || sets_mapping) &&
1988 !mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1989 NL_SET_ERR_MSG(extack,
1990 "Chains on tunnel devices isn't supported without register metadata support");
1991 netdev_warn(priv->netdev,
1992 "Chains on tunnel devices isn't supported without register metadata support");
1993 return -EOPNOTSUPP;
1994 }
1995
1996 if (!flow->esw_attr->chain) {
1997 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1998 match_level);
1999 if (err) {
2000 NL_SET_ERR_MSG_MOD(extack,
2001 "Failed to parse tunnel attributes");
2002 netdev_warn(priv->netdev,
2003 "Failed to parse tunnel attributes");
2004 return err;
2005 }
2006
2007 flow->esw_attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2008 }
2009
2010 if (!needs_mapping && !sets_mapping)
2011 return 0;
2012
2013 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
2014 }
2015
2016 static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
2017 {
2018 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2019 inner_headers);
2020 }
2021
2022 static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
2023 {
2024 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2025 inner_headers);
2026 }
2027
2028 static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2029 {
2030 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2031 outer_headers);
2032 }
2033
2034 static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2035 {
2036 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2037 outer_headers);
2038 }
2039
2040 static void *get_match_headers_value(u32 flags,
2041 struct mlx5_flow_spec *spec)
2042 {
2043 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2044 get_match_inner_headers_value(spec) :
2045 get_match_outer_headers_value(spec);
2046 }
2047
2048 static void *get_match_headers_criteria(u32 flags,
2049 struct mlx5_flow_spec *spec)
2050 {
2051 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2052 get_match_inner_headers_criteria(spec) :
2053 get_match_outer_headers_criteria(spec);
2054 }
2055
2056 static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2057 struct flow_cls_offload *f)
2058 {
2059 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2060 struct netlink_ext_ack *extack = f->common.extack;
2061 struct net_device *ingress_dev;
2062 struct flow_match_meta match;
2063
2064 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2065 return 0;
2066
2067 flow_rule_match_meta(rule, &match);
2068 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2069 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
2070 return -EINVAL;
2071 }
2072
2073 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2074 match.key->ingress_ifindex);
2075 if (!ingress_dev) {
2076 NL_SET_ERR_MSG_MOD(extack,
2077 "Can't find the ingress port to match on");
2078 return -EINVAL;
2079 }
2080
2081 if (ingress_dev != filter_dev) {
2082 NL_SET_ERR_MSG_MOD(extack,
2083 "Can't match on the ingress filter port");
2084 return -EINVAL;
2085 }
2086
2087 return 0;
2088 }
2089
2090 static int __parse_cls_flower(struct mlx5e_priv *priv,
2091 struct mlx5e_tc_flow *flow,
2092 struct mlx5_flow_spec *spec,
2093 struct flow_cls_offload *f,
2094 struct net_device *filter_dev,
2095 u8 *inner_match_level, u8 *outer_match_level)
2096 {
2097 struct netlink_ext_ack *extack = f->common.extack;
2098 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2099 outer_headers);
2100 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2101 outer_headers);
2102 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2103 misc_parameters);
2104 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2105 misc_parameters);
2106 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2107 struct flow_dissector *dissector = rule->match.dissector;
2108 u16 addr_type = 0;
2109 u8 ip_proto = 0;
2110 u8 *match_level;
2111 int err;
2112
2113 match_level = outer_match_level;
2114
2115 if (dissector->used_keys &
2116 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2117 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
2118 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2119 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2120 BIT(FLOW_DISSECTOR_KEY_VLAN) |
2121 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
2122 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2123 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
2124 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2125 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2126 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2127 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2128 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
2129 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
2130 BIT(FLOW_DISSECTOR_KEY_TCP) |
2131 BIT(FLOW_DISSECTOR_KEY_IP) |
2132 BIT(FLOW_DISSECTOR_KEY_CT) |
2133 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
2134 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
2135 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
2136 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
2137 dissector->used_keys);
2138 return -EOPNOTSUPP;
2139 }
2140
2141 if (mlx5e_get_tc_tun(filter_dev)) {
2142 bool match_inner = false;
2143
2144 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2145 outer_match_level, &match_inner);
2146 if (err)
2147 return err;
2148
2149 if (match_inner) {
2150 /* header pointers should point to the inner headers
2151 * if the packet was decapsulated already.
2152 * outer headers are set by parse_tunnel_attr.
2153 */
2154 match_level = inner_match_level;
2155 headers_c = get_match_inner_headers_criteria(spec);
2156 headers_v = get_match_inner_headers_value(spec);
2157 }
2158 }
2159
2160 err = mlx5e_flower_parse_meta(filter_dev, f);
2161 if (err)
2162 return err;
2163
2164 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2165 struct flow_match_basic match;
2166
2167 flow_rule_match_basic(rule, &match);
2168 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
2169 ntohs(match.mask->n_proto));
2170 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
2171 ntohs(match.key->n_proto));
2172
2173 if (match.mask->n_proto)
2174 *match_level = MLX5_MATCH_L2;
2175 }
2176 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2177 is_vlan_dev(filter_dev)) {
2178 struct flow_dissector_key_vlan filter_dev_mask;
2179 struct flow_dissector_key_vlan filter_dev_key;
2180 struct flow_match_vlan match;
2181
2182 if (is_vlan_dev(filter_dev)) {
2183 match.key = &filter_dev_key;
2184 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2185 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2186 match.key->vlan_priority = 0;
2187 match.mask = &filter_dev_mask;
2188 memset(match.mask, 0xff, sizeof(*match.mask));
2189 match.mask->vlan_priority = 0;
2190 } else {
2191 flow_rule_match_vlan(rule, &match);
2192 }
2193 if (match.mask->vlan_id ||
2194 match.mask->vlan_priority ||
2195 match.mask->vlan_tpid) {
2196 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2197 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2198 svlan_tag, 1);
2199 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2200 svlan_tag, 1);
2201 } else {
2202 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2203 cvlan_tag, 1);
2204 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2205 cvlan_tag, 1);
2206 }
2207
2208 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2209 match.mask->vlan_id);
2210 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2211 match.key->vlan_id);
2212
2213 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2214 match.mask->vlan_priority);
2215 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2216 match.key->vlan_priority);
2217
2218 *match_level = MLX5_MATCH_L2;
2219 }
2220 } else if (*match_level != MLX5_MATCH_NONE) {
2221 /* cvlan_tag enabled in match criteria and
2222 * disabled in match value means both S & C tags
2223 * don't exist (untagged of both)
2224 */
2225 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
2226 *match_level = MLX5_MATCH_L2;
2227 }
2228
2229 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2230 struct flow_match_vlan match;
2231
2232 flow_rule_match_cvlan(rule, &match);
2233 if (match.mask->vlan_id ||
2234 match.mask->vlan_priority ||
2235 match.mask->vlan_tpid) {
2236 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2237 MLX5_SET(fte_match_set_misc, misc_c,
2238 outer_second_svlan_tag, 1);
2239 MLX5_SET(fte_match_set_misc, misc_v,
2240 outer_second_svlan_tag, 1);
2241 } else {
2242 MLX5_SET(fte_match_set_misc, misc_c,
2243 outer_second_cvlan_tag, 1);
2244 MLX5_SET(fte_match_set_misc, misc_v,
2245 outer_second_cvlan_tag, 1);
2246 }
2247
2248 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
2249 match.mask->vlan_id);
2250 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
2251 match.key->vlan_id);
2252 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
2253 match.mask->vlan_priority);
2254 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
2255 match.key->vlan_priority);
2256
2257 *match_level = MLX5_MATCH_L2;
2258 }
2259 }
2260
2261 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2262 struct flow_match_eth_addrs match;
2263
2264 flow_rule_match_eth_addrs(rule, &match);
2265 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2266 dmac_47_16),
2267 match.mask->dst);
2268 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2269 dmac_47_16),
2270 match.key->dst);
2271
2272 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2273 smac_47_16),
2274 match.mask->src);
2275 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2276 smac_47_16),
2277 match.key->src);
2278
2279 if (!is_zero_ether_addr(match.mask->src) ||
2280 !is_zero_ether_addr(match.mask->dst))
2281 *match_level = MLX5_MATCH_L2;
2282 }
2283
2284 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2285 struct flow_match_control match;
2286
2287 flow_rule_match_control(rule, &match);
2288 addr_type = match.key->addr_type;
2289
2290 /* the HW doesn't support frag first/later */
2291 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
2292 return -EOPNOTSUPP;
2293
2294 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
2295 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2296 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
2297 match.key->flags & FLOW_DIS_IS_FRAGMENT);
2298
2299 /* the HW doesn't need L3 inline to match on frag=no */
2300 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
2301 *match_level = MLX5_MATCH_L2;
2302 /* *** L2 attributes parsing up to here *** */
2303 else
2304 *match_level = MLX5_MATCH_L3;
2305 }
2306 }
2307
2308 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2309 struct flow_match_basic match;
2310
2311 flow_rule_match_basic(rule, &match);
2312 ip_proto = match.key->ip_proto;
2313
2314 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2315 match.mask->ip_proto);
2316 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2317 match.key->ip_proto);
2318
2319 if (match.mask->ip_proto)
2320 *match_level = MLX5_MATCH_L3;
2321 }
2322
2323 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
2324 struct flow_match_ipv4_addrs match;
2325
2326 flow_rule_match_ipv4_addrs(rule, &match);
2327 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2328 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2329 &match.mask->src, sizeof(match.mask->src));
2330 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2331 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2332 &match.key->src, sizeof(match.key->src));
2333 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2334 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2335 &match.mask->dst, sizeof(match.mask->dst));
2336 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2337 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2338 &match.key->dst, sizeof(match.key->dst));
2339
2340 if (match.mask->src || match.mask->dst)
2341 *match_level = MLX5_MATCH_L3;
2342 }
2343
2344 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
2345 struct flow_match_ipv6_addrs match;
2346
2347 flow_rule_match_ipv6_addrs(rule, &match);
2348 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2349 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2350 &match.mask->src, sizeof(match.mask->src));
2351 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2352 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2353 &match.key->src, sizeof(match.key->src));
2354
2355 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2356 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2357 &match.mask->dst, sizeof(match.mask->dst));
2358 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2359 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2360 &match.key->dst, sizeof(match.key->dst));
2361
2362 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2363 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
2364 *match_level = MLX5_MATCH_L3;
2365 }
2366
2367 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2368 struct flow_match_ip match;
2369
2370 flow_rule_match_ip(rule, &match);
2371 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2372 match.mask->tos & 0x3);
2373 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2374 match.key->tos & 0x3);
2375
2376 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2377 match.mask->tos >> 2);
2378 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2379 match.key->tos >> 2);
2380
2381 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2382 match.mask->ttl);
2383 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2384 match.key->ttl);
2385
2386 if (match.mask->ttl &&
2387 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
2388 ft_field_support.outer_ipv4_ttl)) {
2389 NL_SET_ERR_MSG_MOD(extack,
2390 "Matching on TTL is not supported");
2391 return -EOPNOTSUPP;
2392 }
2393
2394 if (match.mask->tos || match.mask->ttl)
2395 *match_level = MLX5_MATCH_L3;
2396 }
2397
2398 /* *** L3 attributes parsing up to here *** */
2399
2400 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2401 struct flow_match_ports match;
2402
2403 flow_rule_match_ports(rule, &match);
2404 switch (ip_proto) {
2405 case IPPROTO_TCP:
2406 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2407 tcp_sport, ntohs(match.mask->src));
2408 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2409 tcp_sport, ntohs(match.key->src));
2410
2411 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2412 tcp_dport, ntohs(match.mask->dst));
2413 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2414 tcp_dport, ntohs(match.key->dst));
2415 break;
2416
2417 case IPPROTO_UDP:
2418 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2419 udp_sport, ntohs(match.mask->src));
2420 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2421 udp_sport, ntohs(match.key->src));
2422
2423 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2424 udp_dport, ntohs(match.mask->dst));
2425 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2426 udp_dport, ntohs(match.key->dst));
2427 break;
2428 default:
2429 NL_SET_ERR_MSG_MOD(extack,
2430 "Only UDP and TCP transports are supported for L4 matching");
2431 netdev_err(priv->netdev,
2432 "Only UDP and TCP transport are supported\n");
2433 return -EINVAL;
2434 }
2435
2436 if (match.mask->src || match.mask->dst)
2437 *match_level = MLX5_MATCH_L4;
2438 }
2439
2440 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2441 struct flow_match_tcp match;
2442
2443 flow_rule_match_tcp(rule, &match);
2444 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
2445 ntohs(match.mask->flags));
2446 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
2447 ntohs(match.key->flags));
2448
2449 if (match.mask->flags)
2450 *match_level = MLX5_MATCH_L4;
2451 }
2452
2453 return 0;
2454 }
2455
2456 static int parse_cls_flower(struct mlx5e_priv *priv,
2457 struct mlx5e_tc_flow *flow,
2458 struct mlx5_flow_spec *spec,
2459 struct flow_cls_offload *f,
2460 struct net_device *filter_dev)
2461 {
2462 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
2463 struct netlink_ext_ack *extack = f->common.extack;
2464 struct mlx5_core_dev *dev = priv->mdev;
2465 struct mlx5_eswitch *esw = dev->priv.eswitch;
2466 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2467 struct mlx5_eswitch_rep *rep;
2468 bool is_eswitch_flow;
2469 int err;
2470
2471 inner_match_level = MLX5_MATCH_NONE;
2472 outer_match_level = MLX5_MATCH_NONE;
2473
2474 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2475 &inner_match_level, &outer_match_level);
2476 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2477 outer_match_level : inner_match_level;
2478
2479 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2480 if (!err && is_eswitch_flow) {
2481 rep = rpriv->rep;
2482 if (rep->vport != MLX5_VPORT_UPLINK &&
2483 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
2484 esw->offloads.inline_mode < non_tunnel_match_level)) {
2485 NL_SET_ERR_MSG_MOD(extack,
2486 "Flow is not offloaded due to min inline setting");
2487 netdev_warn(priv->netdev,
2488 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
2489 non_tunnel_match_level, esw->offloads.inline_mode);
2490 return -EOPNOTSUPP;
2491 }
2492 }
2493
2494 if (is_eswitch_flow) {
2495 flow->esw_attr->inner_match_level = inner_match_level;
2496 flow->esw_attr->outer_match_level = outer_match_level;
2497 } else {
2498 flow->nic_attr->match_level = non_tunnel_match_level;
2499 }
2500
2501 return err;
2502 }
2503
2504 struct pedit_headers {
2505 struct ethhdr eth;
2506 struct vlan_hdr vlan;
2507 struct iphdr ip4;
2508 struct ipv6hdr ip6;
2509 struct tcphdr tcp;
2510 struct udphdr udp;
2511 };
2512
2513 struct pedit_headers_action {
2514 struct pedit_headers vals;
2515 struct pedit_headers masks;
2516 u32 pedits;
2517 };
2518
2519 static int pedit_header_offsets[] = {
2520 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2521 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2522 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2523 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2524 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
2525 };
2526
2527 #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2528
2529 static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
2530 struct pedit_headers_action *hdrs)
2531 {
2532 u32 *curr_pmask, *curr_pval;
2533
2534 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2535 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
2536
2537 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2538 goto out_err;
2539
2540 *curr_pmask |= mask;
2541 *curr_pval |= (val & mask);
2542
2543 return 0;
2544
2545 out_err:
2546 return -EOPNOTSUPP;
2547 }
2548
2549 struct mlx5_fields {
2550 u8 field;
2551 u8 field_bsize;
2552 u32 field_mask;
2553 u32 offset;
2554 u32 match_offset;
2555 };
2556
2557 #define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2558 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
2559 offsetof(struct pedit_headers, field) + (off), \
2560 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2561
2562 /* masked values are the same and there are no rewrites that do not have a
2563 * match.
2564 */
2565 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2566 type matchmaskx = *(type *)(matchmaskp); \
2567 type matchvalx = *(type *)(matchvalp); \
2568 type maskx = *(type *)(maskp); \
2569 type valx = *(type *)(valp); \
2570 \
2571 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2572 matchmaskx)); \
2573 })
2574
2575 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
2576 void *matchmaskp, u8 bsize)
2577 {
2578 bool same = false;
2579
2580 switch (bsize) {
2581 case 8:
2582 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
2583 break;
2584 case 16:
2585 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
2586 break;
2587 case 32:
2588 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
2589 break;
2590 }
2591
2592 return same;
2593 }
2594
2595 static struct mlx5_fields fields[] = {
2596 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2597 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2598 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2599 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2600 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2601 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2602
2603 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
2604 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2605 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2606 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2607
2608 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
2609 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
2610 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
2611 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
2612 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
2613 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
2614 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
2615 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
2616 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
2617 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
2618 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
2619 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
2620 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
2621 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
2622 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
2623 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
2624 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
2625
2626 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2627 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2628 /* in linux iphdr tcp_flags is 8 bits long */
2629 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
2630
2631 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2632 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
2633 };
2634
2635 static int offload_pedit_fields(struct mlx5e_priv *priv,
2636 int namespace,
2637 struct pedit_headers_action *hdrs,
2638 struct mlx5e_tc_flow_parse_attr *parse_attr,
2639 u32 *action_flags,
2640 struct netlink_ext_ack *extack)
2641 {
2642 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2643 int i, action_size, first, last, next_z;
2644 void *headers_c, *headers_v, *action, *vals_p;
2645 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
2646 struct mlx5e_tc_mod_hdr_acts *mod_acts;
2647 struct mlx5_fields *f;
2648 unsigned long mask;
2649 __be32 mask_be32;
2650 __be16 mask_be16;
2651 int err;
2652 u8 cmd;
2653
2654 mod_acts = &parse_attr->mod_hdr_acts;
2655 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2656 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
2657
2658 set_masks = &hdrs[0].masks;
2659 add_masks = &hdrs[1].masks;
2660 set_vals = &hdrs[0].vals;
2661 add_vals = &hdrs[1].vals;
2662
2663 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2664
2665 for (i = 0; i < ARRAY_SIZE(fields); i++) {
2666 bool skip;
2667
2668 f = &fields[i];
2669 /* avoid seeing bits set from previous iterations */
2670 s_mask = 0;
2671 a_mask = 0;
2672
2673 s_masks_p = (void *)set_masks + f->offset;
2674 a_masks_p = (void *)add_masks + f->offset;
2675
2676 s_mask = *s_masks_p & f->field_mask;
2677 a_mask = *a_masks_p & f->field_mask;
2678
2679 if (!s_mask && !a_mask) /* nothing to offload here */
2680 continue;
2681
2682 if (s_mask && a_mask) {
2683 NL_SET_ERR_MSG_MOD(extack,
2684 "can't set and add to the same HW field");
2685 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2686 return -EOPNOTSUPP;
2687 }
2688
2689 skip = false;
2690 if (s_mask) {
2691 void *match_mask = headers_c + f->match_offset;
2692 void *match_val = headers_v + f->match_offset;
2693
2694 cmd = MLX5_ACTION_TYPE_SET;
2695 mask = s_mask;
2696 vals_p = (void *)set_vals + f->offset;
2697 /* don't rewrite if we have a match on the same value */
2698 if (cmp_val_mask(vals_p, s_masks_p, match_val,
2699 match_mask, f->field_bsize))
2700 skip = true;
2701 /* clear to denote we consumed this field */
2702 *s_masks_p &= ~f->field_mask;
2703 } else {
2704 cmd = MLX5_ACTION_TYPE_ADD;
2705 mask = a_mask;
2706 vals_p = (void *)add_vals + f->offset;
2707 /* add 0 is no change */
2708 if ((*(u32 *)vals_p & f->field_mask) == 0)
2709 skip = true;
2710 /* clear to denote we consumed this field */
2711 *a_masks_p &= ~f->field_mask;
2712 }
2713 if (skip)
2714 continue;
2715
2716 if (f->field_bsize == 32) {
2717 mask_be32 = *(__be32 *)&mask;
2718 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2719 } else if (f->field_bsize == 16) {
2720 mask_be16 = *(__be16 *)&mask;
2721 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2722 }
2723
2724 first = find_first_bit(&mask, f->field_bsize);
2725 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2726 last = find_last_bit(&mask, f->field_bsize);
2727 if (first < next_z && next_z < last) {
2728 NL_SET_ERR_MSG_MOD(extack,
2729 "rewrite of few sub-fields isn't supported");
2730 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2731 mask);
2732 return -EOPNOTSUPP;
2733 }
2734
2735 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2736 if (err) {
2737 NL_SET_ERR_MSG_MOD(extack,
2738 "too many pedit actions, can't offload");
2739 mlx5_core_warn(priv->mdev,
2740 "mlx5: parsed %d pedit actions, can't do more\n",
2741 mod_acts->num_actions);
2742 return err;
2743 }
2744
2745 action = mod_acts->actions +
2746 (mod_acts->num_actions * action_size);
2747 MLX5_SET(set_action_in, action, action_type, cmd);
2748 MLX5_SET(set_action_in, action, field, f->field);
2749
2750 if (cmd == MLX5_ACTION_TYPE_SET) {
2751 int start;
2752
2753 /* if field is bit sized it can start not from first bit */
2754 start = find_first_bit((unsigned long *)&f->field_mask,
2755 f->field_bsize);
2756
2757 MLX5_SET(set_action_in, action, offset, first - start);
2758 /* length is num of bits to be written, zero means length of 32 */
2759 MLX5_SET(set_action_in, action, length, (last - first + 1));
2760 }
2761
2762 if (f->field_bsize == 32)
2763 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
2764 else if (f->field_bsize == 16)
2765 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
2766 else if (f->field_bsize == 8)
2767 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
2768
2769 ++mod_acts->num_actions;
2770 }
2771
2772 return 0;
2773 }
2774
2775 static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2776 int namespace)
2777 {
2778 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2779 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2780 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2781 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2782 }
2783
2784 int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2785 int namespace,
2786 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2787 {
2788 int action_size, new_num_actions, max_hw_actions;
2789 size_t new_sz, old_sz;
2790 void *ret;
2791
2792 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2793 return 0;
2794
2795 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2796
2797 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2798 namespace);
2799 new_num_actions = min(max_hw_actions,
2800 mod_hdr_acts->actions ?
2801 mod_hdr_acts->max_actions * 2 : 1);
2802 if (mod_hdr_acts->max_actions == new_num_actions)
2803 return -ENOSPC;
2804
2805 new_sz = action_size * new_num_actions;
2806 old_sz = mod_hdr_acts->max_actions * action_size;
2807 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2808 if (!ret)
2809 return -ENOMEM;
2810
2811 memset(ret + old_sz, 0, new_sz - old_sz);
2812 mod_hdr_acts->actions = ret;
2813 mod_hdr_acts->max_actions = new_num_actions;
2814
2815 return 0;
2816 }
2817
2818 void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2819 {
2820 kfree(mod_hdr_acts->actions);
2821 mod_hdr_acts->actions = NULL;
2822 mod_hdr_acts->num_actions = 0;
2823 mod_hdr_acts->max_actions = 0;
2824 }
2825
2826 static const struct pedit_headers zero_masks = {};
2827
2828 static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2829 const struct flow_action_entry *act, int namespace,
2830 struct pedit_headers_action *hdrs,
2831 struct netlink_ext_ack *extack)
2832 {
2833 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2834 int err = -EOPNOTSUPP;
2835 u32 mask, val, offset;
2836 u8 htype;
2837
2838 htype = act->mangle.htype;
2839 err = -EOPNOTSUPP; /* can't be all optimistic */
2840
2841 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2842 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2843 goto out_err;
2844 }
2845
2846 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2847 NL_SET_ERR_MSG_MOD(extack,
2848 "The pedit offload action is not supported");
2849 goto out_err;
2850 }
2851
2852 mask = act->mangle.mask;
2853 val = act->mangle.val;
2854 offset = act->mangle.offset;
2855
2856 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2857 if (err)
2858 goto out_err;
2859
2860 hdrs[cmd].pedits++;
2861
2862 return 0;
2863 out_err:
2864 return err;
2865 }
2866
2867 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2868 struct mlx5e_tc_flow_parse_attr *parse_attr,
2869 struct pedit_headers_action *hdrs,
2870 u32 *action_flags,
2871 struct netlink_ext_ack *extack)
2872 {
2873 struct pedit_headers *cmd_masks;
2874 int err;
2875 u8 cmd;
2876
2877 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2878 action_flags, extack);
2879 if (err < 0)
2880 goto out_dealloc_parsed_actions;
2881
2882 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2883 cmd_masks = &hdrs[cmd].masks;
2884 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
2885 NL_SET_ERR_MSG_MOD(extack,
2886 "attempt to offload an unsupported field");
2887 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
2888 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2889 16, 1, cmd_masks, sizeof(zero_masks), true);
2890 err = -EOPNOTSUPP;
2891 goto out_dealloc_parsed_actions;
2892 }
2893 }
2894
2895 return 0;
2896
2897 out_dealloc_parsed_actions:
2898 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
2899 return err;
2900 }
2901
2902 static bool csum_offload_supported(struct mlx5e_priv *priv,
2903 u32 action,
2904 u32 update_flags,
2905 struct netlink_ext_ack *extack)
2906 {
2907 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2908 TCA_CSUM_UPDATE_FLAG_UDP;
2909
2910 /* The HW recalcs checksums only if re-writing headers */
2911 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
2912 NL_SET_ERR_MSG_MOD(extack,
2913 "TC csum action is only offloaded with pedit");
2914 netdev_warn(priv->netdev,
2915 "TC csum action is only offloaded with pedit\n");
2916 return false;
2917 }
2918
2919 if (update_flags & ~prot_flags) {
2920 NL_SET_ERR_MSG_MOD(extack,
2921 "can't offload TC csum action for some header/s");
2922 netdev_warn(priv->netdev,
2923 "can't offload TC csum action for some header/s - flags %#x\n",
2924 update_flags);
2925 return false;
2926 }
2927
2928 return true;
2929 }
2930
2931 struct ip_ttl_word {
2932 __u8 ttl;
2933 __u8 protocol;
2934 __sum16 check;
2935 };
2936
2937 struct ipv6_hoplimit_word {
2938 __be16 payload_len;
2939 __u8 nexthdr;
2940 __u8 hop_limit;
2941 };
2942
2943 static int is_action_keys_supported(const struct flow_action_entry *act,
2944 bool ct_flow, bool *modify_ip_header,
2945 struct netlink_ext_ack *extack)
2946 {
2947 u32 mask, offset;
2948 u8 htype;
2949
2950 htype = act->mangle.htype;
2951 offset = act->mangle.offset;
2952 mask = ~act->mangle.mask;
2953 /* For IPv4 & IPv6 header check 4 byte word,
2954 * to determine that modified fields
2955 * are NOT ttl & hop_limit only.
2956 */
2957 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2958 struct ip_ttl_word *ttl_word =
2959 (struct ip_ttl_word *)&mask;
2960
2961 if (offset != offsetof(struct iphdr, ttl) ||
2962 ttl_word->protocol ||
2963 ttl_word->check) {
2964 *modify_ip_header = true;
2965 }
2966
2967 if (ct_flow && offset >= offsetof(struct iphdr, saddr)) {
2968 NL_SET_ERR_MSG_MOD(extack,
2969 "can't offload re-write of ipv4 address with action ct");
2970 return -EOPNOTSUPP;
2971 }
2972 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2973 struct ipv6_hoplimit_word *hoplimit_word =
2974 (struct ipv6_hoplimit_word *)&mask;
2975
2976 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2977 hoplimit_word->payload_len ||
2978 hoplimit_word->nexthdr) {
2979 *modify_ip_header = true;
2980 }
2981
2982 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr)) {
2983 NL_SET_ERR_MSG_MOD(extack,
2984 "can't offload re-write of ipv6 address with action ct");
2985 return -EOPNOTSUPP;
2986 }
2987 } else if (ct_flow && (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
2988 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP)) {
2989 NL_SET_ERR_MSG_MOD(extack,
2990 "can't offload re-write of transport header ports with action ct");
2991 return -EOPNOTSUPP;
2992 }
2993
2994 return 0;
2995 }
2996
2997 static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
2998 struct flow_action *flow_action,
2999 u32 actions, bool ct_flow,
3000 struct netlink_ext_ack *extack)
3001 {
3002 const struct flow_action_entry *act;
3003 bool modify_ip_header;
3004 void *headers_v;
3005 u16 ethertype;
3006 u8 ip_proto;
3007 int i, err;
3008
3009 headers_v = get_match_headers_value(actions, spec);
3010 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3011
3012 /* for non-IP we only re-write MACs, so we're okay */
3013 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
3014 goto out_ok;
3015
3016 modify_ip_header = false;
3017 flow_action_for_each(i, act, flow_action) {
3018 if (act->id != FLOW_ACTION_MANGLE &&
3019 act->id != FLOW_ACTION_ADD)
3020 continue;
3021
3022 err = is_action_keys_supported(act, ct_flow,
3023 &modify_ip_header, extack);
3024 if (err)
3025 return err;
3026 }
3027
3028 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
3029 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3030 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
3031 NL_SET_ERR_MSG_MOD(extack,
3032 "can't offload re-write of non TCP/UDP");
3033 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
3034 return false;
3035 }
3036
3037 out_ok:
3038 return true;
3039 }
3040
3041 static bool actions_match_supported(struct mlx5e_priv *priv,
3042 struct flow_action *flow_action,
3043 struct mlx5e_tc_flow_parse_attr *parse_attr,
3044 struct mlx5e_tc_flow *flow,
3045 struct netlink_ext_ack *extack)
3046 {
3047 struct net_device *filter_dev = parse_attr->filter_dev;
3048 bool drop_action, pop_action, ct_flow;
3049 u32 actions;
3050
3051 ct_flow = flow_flag_test(flow, CT);
3052 if (mlx5e_is_eswitch_flow(flow)) {
3053 actions = flow->esw_attr->action;
3054
3055 if (flow->esw_attr->split_count && ct_flow) {
3056 /* All registers used by ct are cleared when using
3057 * split rules.
3058 */
3059 NL_SET_ERR_MSG_MOD(extack,
3060 "Can't offload mirroring with action ct");
3061 return -EOPNOTSUPP;
3062 }
3063 } else {
3064 actions = flow->nic_attr->action;
3065 }
3066
3067 drop_action = actions & MLX5_FLOW_CONTEXT_ACTION_DROP;
3068 pop_action = actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3069
3070 if (flow_flag_test(flow, EGRESS) && !drop_action) {
3071 /* We only support filters on tunnel device, or on vlan
3072 * devices if they have pop/drop action
3073 */
3074 if (!mlx5e_get_tc_tun(filter_dev) ||
3075 (is_vlan_dev(filter_dev) && !pop_action))
3076 return false;
3077 }
3078
3079 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3080 return modify_header_match_supported(&parse_attr->spec,
3081 flow_action, actions,
3082 ct_flow, extack);
3083
3084 return true;
3085 }
3086
3087 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3088 {
3089 struct mlx5_core_dev *fmdev, *pmdev;
3090 u64 fsystem_guid, psystem_guid;
3091
3092 fmdev = priv->mdev;
3093 pmdev = peer_priv->mdev;
3094
3095 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3096 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
3097
3098 return (fsystem_guid == psystem_guid);
3099 }
3100
3101 static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3102 const struct flow_action_entry *act,
3103 struct mlx5e_tc_flow_parse_attr *parse_attr,
3104 struct pedit_headers_action *hdrs,
3105 u32 *action, struct netlink_ext_ack *extack)
3106 {
3107 u16 mask16 = VLAN_VID_MASK;
3108 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3109 const struct flow_action_entry pedit_act = {
3110 .id = FLOW_ACTION_MANGLE,
3111 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3112 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3113 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3114 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3115 };
3116 u8 match_prio_mask, match_prio_val;
3117 void *headers_c, *headers_v;
3118 int err;
3119
3120 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3121 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3122
3123 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3124 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3125 NL_SET_ERR_MSG_MOD(extack,
3126 "VLAN rewrite action must have VLAN protocol match");
3127 return -EOPNOTSUPP;
3128 }
3129
3130 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3131 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3132 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3133 NL_SET_ERR_MSG_MOD(extack,
3134 "Changing VLAN prio is not supported");
3135 return -EOPNOTSUPP;
3136 }
3137
3138 err = parse_tc_pedit_action(priv, &pedit_act, namespace, hdrs, NULL);
3139 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3140
3141 return err;
3142 }
3143
3144 static int
3145 add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3146 struct mlx5e_tc_flow_parse_attr *parse_attr,
3147 struct pedit_headers_action *hdrs,
3148 u32 *action, struct netlink_ext_ack *extack)
3149 {
3150 const struct flow_action_entry prio_tag_act = {
3151 .vlan.vid = 0,
3152 .vlan.prio =
3153 MLX5_GET(fte_match_set_lyr_2_4,
3154 get_match_headers_value(*action,
3155 &parse_attr->spec),
3156 first_prio) &
3157 MLX5_GET(fte_match_set_lyr_2_4,
3158 get_match_headers_criteria(*action,
3159 &parse_attr->spec),
3160 first_prio),
3161 };
3162
3163 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3164 &prio_tag_act, parse_attr, hdrs, action,
3165 extack);
3166 }
3167
3168 static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3169 struct flow_action *flow_action,
3170 struct mlx5e_tc_flow_parse_attr *parse_attr,
3171 struct mlx5e_tc_flow *flow,
3172 struct netlink_ext_ack *extack)
3173 {
3174 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
3175 struct pedit_headers_action hdrs[2] = {};
3176 const struct flow_action_entry *act;
3177 u32 action = 0;
3178 int err, i;
3179
3180 if (!flow_action_has_entries(flow_action))
3181 return -EINVAL;
3182
3183 if (!flow_action_hw_stats_types_check(flow_action, extack,
3184 FLOW_ACTION_HW_STATS_TYPE_DELAYED_BIT))
3185 return -EOPNOTSUPP;
3186
3187 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
3188
3189 flow_action_for_each(i, act, flow_action) {
3190 switch (act->id) {
3191 case FLOW_ACTION_ACCEPT:
3192 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3193 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3194 break;
3195 case FLOW_ACTION_DROP:
3196 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3197 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3198 flow_table_properties_nic_receive.flow_counter))
3199 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3200 break;
3201 case FLOW_ACTION_MANGLE:
3202 case FLOW_ACTION_ADD:
3203 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
3204 hdrs, extack);
3205 if (err)
3206 return err;
3207
3208 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
3209 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3210 break;
3211 case FLOW_ACTION_VLAN_MANGLE:
3212 err = add_vlan_rewrite_action(priv,
3213 MLX5_FLOW_NAMESPACE_KERNEL,
3214 act, parse_attr, hdrs,
3215 &action, extack);
3216 if (err)
3217 return err;
3218
3219 break;
3220 case FLOW_ACTION_CSUM:
3221 if (csum_offload_supported(priv, action,
3222 act->csum_flags,
3223 extack))
3224 break;
3225
3226 return -EOPNOTSUPP;
3227 case FLOW_ACTION_REDIRECT: {
3228 struct net_device *peer_dev = act->dev;
3229
3230 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3231 same_hw_devs(priv, netdev_priv(peer_dev))) {
3232 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
3233 flow_flag_set(flow, HAIRPIN);
3234 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3235 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3236 } else {
3237 NL_SET_ERR_MSG_MOD(extack,
3238 "device is not on same HW, can't offload");
3239 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3240 peer_dev->name);
3241 return -EINVAL;
3242 }
3243 }
3244 break;
3245 case FLOW_ACTION_MARK: {
3246 u32 mark = act->mark;
3247
3248 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
3249 NL_SET_ERR_MSG_MOD(extack,
3250 "Bad flow mark - only 16 bit is supported");
3251 return -EINVAL;
3252 }
3253
3254 attr->flow_tag = mark;
3255 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3256 }
3257 break;
3258 default:
3259 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3260 return -EOPNOTSUPP;
3261 }
3262 }
3263
3264 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3265 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3266 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
3267 parse_attr, hdrs, &action, extack);
3268 if (err)
3269 return err;
3270 /* in case all pedit actions are skipped, remove the MOD_HDR
3271 * flag.
3272 */
3273 if (parse_attr->mod_hdr_acts.num_actions == 0) {
3274 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3275 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
3276 }
3277 }
3278
3279 attr->action = action;
3280 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
3281 return -EOPNOTSUPP;
3282
3283 return 0;
3284 }
3285
3286 struct encap_key {
3287 const struct ip_tunnel_key *ip_tun_key;
3288 struct mlx5e_tc_tunnel *tc_tunnel;
3289 };
3290
3291 static inline int cmp_encap_info(struct encap_key *a,
3292 struct encap_key *b)
3293 {
3294 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
3295 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
3296 }
3297
3298 static inline int hash_encap_info(struct encap_key *key)
3299 {
3300 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
3301 key->tc_tunnel->tunnel_type);
3302 }
3303
3304
3305 static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
3306 struct net_device *peer_netdev)
3307 {
3308 struct mlx5e_priv *peer_priv;
3309
3310 peer_priv = netdev_priv(peer_netdev);
3311
3312 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
3313 mlx5e_eswitch_rep(priv->netdev) &&
3314 mlx5e_eswitch_rep(peer_netdev) &&
3315 same_hw_devs(priv, peer_priv));
3316 }
3317
3318
3319
3320 bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3321 {
3322 return refcount_inc_not_zero(&e->refcnt);
3323 }
3324
3325 static struct mlx5e_encap_entry *
3326 mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3327 uintptr_t hash_key)
3328 {
3329 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3330 struct mlx5e_encap_entry *e;
3331 struct encap_key e_key;
3332
3333 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3334 encap_hlist, hash_key) {
3335 e_key.ip_tun_key = &e->tun_info->key;
3336 e_key.tc_tunnel = e->tunnel;
3337 if (!cmp_encap_info(&e_key, key) &&
3338 mlx5e_encap_take(e))
3339 return e;
3340 }
3341
3342 return NULL;
3343 }
3344
3345 static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3346 {
3347 size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3348
3349 return kmemdup(tun_info, tun_size, GFP_KERNEL);
3350 }
3351
3352 static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3353 struct mlx5e_tc_flow *flow,
3354 int out_index,
3355 struct mlx5e_encap_entry *e,
3356 struct netlink_ext_ack *extack)
3357 {
3358 int i;
3359
3360 for (i = 0; i < out_index; i++) {
3361 if (flow->encaps[i].e != e)
3362 continue;
3363 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3364 netdev_err(priv->netdev, "can't duplicate encap action\n");
3365 return true;
3366 }
3367
3368 return false;
3369 }
3370
3371 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
3372 struct mlx5e_tc_flow *flow,
3373 struct net_device *mirred_dev,
3374 int out_index,
3375 struct netlink_ext_ack *extack,
3376 struct net_device **encap_dev,
3377 bool *encap_valid)
3378 {
3379 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3380 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3381 struct mlx5e_tc_flow_parse_attr *parse_attr;
3382 const struct ip_tunnel_info *tun_info;
3383 struct encap_key key;
3384 struct mlx5e_encap_entry *e;
3385 unsigned short family;
3386 uintptr_t hash_key;
3387 int err = 0;
3388
3389 parse_attr = attr->parse_attr;
3390 tun_info = parse_attr->tun_info[out_index];
3391 family = ip_tunnel_info_af(tun_info);
3392 key.ip_tun_key = &tun_info->key;
3393 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
3394 if (!key.tc_tunnel) {
3395 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3396 return -EOPNOTSUPP;
3397 }
3398
3399 hash_key = hash_encap_info(&key);
3400
3401 mutex_lock(&esw->offloads.encap_tbl_lock);
3402 e = mlx5e_encap_get(priv, &key, hash_key);
3403
3404 /* must verify if encap is valid or not */
3405 if (e) {
3406 /* Check that entry was not already attached to this flow */
3407 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3408 err = -EOPNOTSUPP;
3409 goto out_err;
3410 }
3411
3412 mutex_unlock(&esw->offloads.encap_tbl_lock);
3413 wait_for_completion(&e->res_ready);
3414
3415 /* Protect against concurrent neigh update. */
3416 mutex_lock(&esw->offloads.encap_tbl_lock);
3417 if (e->compl_result < 0) {
3418 err = -EREMOTEIO;
3419 goto out_err;
3420 }
3421 goto attach_flow;
3422 }
3423
3424 e = kzalloc(sizeof(*e), GFP_KERNEL);
3425 if (!e) {
3426 err = -ENOMEM;
3427 goto out_err;
3428 }
3429
3430 refcount_set(&e->refcnt, 1);
3431 init_completion(&e->res_ready);
3432
3433 tun_info = dup_tun_info(tun_info);
3434 if (!tun_info) {
3435 err = -ENOMEM;
3436 goto out_err_init;
3437 }
3438 e->tun_info = tun_info;
3439 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
3440 if (err)
3441 goto out_err_init;
3442
3443 INIT_LIST_HEAD(&e->flows);
3444 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3445 mutex_unlock(&esw->offloads.encap_tbl_lock);
3446
3447 if (family == AF_INET)
3448 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
3449 else if (family == AF_INET6)
3450 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
3451
3452 /* Protect against concurrent neigh update. */
3453 mutex_lock(&esw->offloads.encap_tbl_lock);
3454 complete_all(&e->res_ready);
3455 if (err) {
3456 e->compl_result = err;
3457 goto out_err;
3458 }
3459 e->compl_result = 1;
3460
3461 attach_flow:
3462 flow->encaps[out_index].e = e;
3463 list_add(&flow->encaps[out_index].list, &e->flows);
3464 flow->encaps[out_index].index = out_index;
3465 *encap_dev = e->out_dev;
3466 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
3467 attr->dests[out_index].pkt_reformat = e->pkt_reformat;
3468 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
3469 *encap_valid = true;
3470 } else {
3471 *encap_valid = false;
3472 }
3473 mutex_unlock(&esw->offloads.encap_tbl_lock);
3474
3475 return err;
3476
3477 out_err:
3478 mutex_unlock(&esw->offloads.encap_tbl_lock);
3479 if (e)
3480 mlx5e_encap_put(priv, e);
3481 return err;
3482
3483 out_err_init:
3484 mutex_unlock(&esw->offloads.encap_tbl_lock);
3485 kfree(tun_info);
3486 kfree(e);
3487 return err;
3488 }
3489
3490 static int parse_tc_vlan_action(struct mlx5e_priv *priv,
3491 const struct flow_action_entry *act,
3492 struct mlx5_esw_flow_attr *attr,
3493 u32 *action)
3494 {
3495 u8 vlan_idx = attr->total_vlan;
3496
3497 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3498 return -EOPNOTSUPP;
3499
3500 switch (act->id) {
3501 case FLOW_ACTION_VLAN_POP:
3502 if (vlan_idx) {
3503 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3504 MLX5_FS_VLAN_DEPTH))
3505 return -EOPNOTSUPP;
3506
3507 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3508 } else {
3509 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3510 }
3511 break;
3512 case FLOW_ACTION_VLAN_PUSH:
3513 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3514 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3515 attr->vlan_proto[vlan_idx] = act->vlan.proto;
3516 if (!attr->vlan_proto[vlan_idx])
3517 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3518
3519 if (vlan_idx) {
3520 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3521 MLX5_FS_VLAN_DEPTH))
3522 return -EOPNOTSUPP;
3523
3524 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3525 } else {
3526 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
3527 (act->vlan.proto != htons(ETH_P_8021Q) ||
3528 act->vlan.prio))
3529 return -EOPNOTSUPP;
3530
3531 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
3532 }
3533 break;
3534 default:
3535 return -EINVAL;
3536 }
3537
3538 attr->total_vlan = vlan_idx + 1;
3539
3540 return 0;
3541 }
3542
3543 static int add_vlan_push_action(struct mlx5e_priv *priv,
3544 struct mlx5_esw_flow_attr *attr,
3545 struct net_device **out_dev,
3546 u32 *action)
3547 {
3548 struct net_device *vlan_dev = *out_dev;
3549 struct flow_action_entry vlan_act = {
3550 .id = FLOW_ACTION_VLAN_PUSH,
3551 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3552 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3553 .vlan.prio = 0,
3554 };
3555 int err;
3556
3557 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3558 if (err)
3559 return err;
3560
3561 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3562 dev_get_iflink(vlan_dev));
3563 if (is_vlan_dev(*out_dev))
3564 err = add_vlan_push_action(priv, attr, out_dev, action);
3565
3566 return err;
3567 }
3568
3569 static int add_vlan_pop_action(struct mlx5e_priv *priv,
3570 struct mlx5_esw_flow_attr *attr,
3571 u32 *action)
3572 {
3573 int nest_level = attr->parse_attr->filter_dev->lower_level;
3574 struct flow_action_entry vlan_act = {
3575 .id = FLOW_ACTION_VLAN_POP,
3576 };
3577 int err = 0;
3578
3579 while (nest_level--) {
3580 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3581 if (err)
3582 return err;
3583 }
3584
3585 return err;
3586 }
3587
3588 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3589 struct net_device *out_dev)
3590 {
3591 if (is_merged_eswitch_dev(priv, out_dev))
3592 return true;
3593
3594 return mlx5e_eswitch_rep(out_dev) &&
3595 same_hw_devs(priv, netdev_priv(out_dev));
3596 }
3597
3598 static bool is_duplicated_output_device(struct net_device *dev,
3599 struct net_device *out_dev,
3600 int *ifindexes, int if_count,
3601 struct netlink_ext_ack *extack)
3602 {
3603 int i;
3604
3605 for (i = 0; i < if_count; i++) {
3606 if (ifindexes[i] == out_dev->ifindex) {
3607 NL_SET_ERR_MSG_MOD(extack,
3608 "can't duplicate output to same device");
3609 netdev_err(dev, "can't duplicate output to same device: %s\n",
3610 out_dev->name);
3611 return true;
3612 }
3613 }
3614
3615 return false;
3616 }
3617
3618 static int mlx5_validate_goto_chain(struct mlx5_eswitch *esw,
3619 struct mlx5e_tc_flow *flow,
3620 const struct flow_action_entry *act,
3621 u32 actions,
3622 struct netlink_ext_ack *extack)
3623 {
3624 u32 max_chain = mlx5_esw_chains_get_chain_range(esw);
3625 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3626 bool ft_flow = mlx5e_is_ft_flow(flow);
3627 u32 dest_chain = act->chain_index;
3628
3629 if (ft_flow) {
3630 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3631 return -EOPNOTSUPP;
3632 }
3633
3634 if (!mlx5_esw_chains_backwards_supported(esw) &&
3635 dest_chain <= attr->chain) {
3636 NL_SET_ERR_MSG_MOD(extack,
3637 "Goto lower numbered chain isn't supported");
3638 return -EOPNOTSUPP;
3639 }
3640 if (dest_chain > max_chain) {
3641 NL_SET_ERR_MSG_MOD(extack,
3642 "Requested destination chain is out of supported range");
3643 return -EOPNOTSUPP;
3644 }
3645
3646 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3647 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3648 !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat_and_fwd_to_table)) {
3649 NL_SET_ERR_MSG_MOD(extack,
3650 "Goto chain is not allowed if action has reformat or decap");
3651 return -EOPNOTSUPP;
3652 }
3653
3654 return 0;
3655 }
3656
3657 static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3658 struct flow_action *flow_action,
3659 struct mlx5e_tc_flow *flow,
3660 struct netlink_ext_ack *extack)
3661 {
3662 struct pedit_headers_action hdrs[2] = {};
3663 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3664 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3665 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3666 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3667 const struct ip_tunnel_info *info = NULL;
3668 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
3669 bool ft_flow = mlx5e_is_ft_flow(flow);
3670 const struct flow_action_entry *act;
3671 bool encap = false, decap = false;
3672 u32 action = attr->action;
3673 int err, i, if_count = 0;
3674
3675 if (!flow_action_has_entries(flow_action))
3676 return -EINVAL;
3677
3678 if (!flow_action_hw_stats_types_check(flow_action, extack,
3679 FLOW_ACTION_HW_STATS_TYPE_DELAYED_BIT))
3680 return -EOPNOTSUPP;
3681
3682 flow_action_for_each(i, act, flow_action) {
3683 switch (act->id) {
3684 case FLOW_ACTION_DROP:
3685 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3686 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3687 break;
3688 case FLOW_ACTION_MANGLE:
3689 case FLOW_ACTION_ADD:
3690 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
3691 hdrs, extack);
3692 if (err)
3693 return err;
3694
3695 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3696 attr->split_count = attr->out_count;
3697 break;
3698 case FLOW_ACTION_CSUM:
3699 if (csum_offload_supported(priv, action,
3700 act->csum_flags, extack))
3701 break;
3702
3703 return -EOPNOTSUPP;
3704 case FLOW_ACTION_REDIRECT:
3705 case FLOW_ACTION_MIRRED: {
3706 struct mlx5e_priv *out_priv;
3707 struct net_device *out_dev;
3708
3709 out_dev = act->dev;
3710 if (!out_dev) {
3711 /* out_dev is NULL when filters with
3712 * non-existing mirred device are replayed to
3713 * the driver.
3714 */
3715 return -EINVAL;
3716 }
3717
3718 if (ft_flow && out_dev == priv->netdev) {
3719 /* Ignore forward to self rules generated
3720 * by adding both mlx5 devs to the flow table
3721 * block on a normal nft offload setup.
3722 */
3723 return -EOPNOTSUPP;
3724 }
3725
3726 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
3727 NL_SET_ERR_MSG_MOD(extack,
3728 "can't support more output ports, can't offload forwarding");
3729 netdev_warn(priv->netdev,
3730 "can't support more than %d output ports, can't offload forwarding\n",
3731 attr->out_count);
3732 return -EOPNOTSUPP;
3733 }
3734
3735 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3736 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3737 if (encap) {
3738 parse_attr->mirred_ifindex[attr->out_count] =
3739 out_dev->ifindex;
3740 parse_attr->tun_info[attr->out_count] = dup_tun_info(info);
3741 if (!parse_attr->tun_info[attr->out_count])
3742 return -ENOMEM;
3743 encap = false;
3744 attr->dests[attr->out_count].flags |=
3745 MLX5_ESW_DEST_ENCAP;
3746 attr->out_count++;
3747 /* attr->dests[].rep is resolved when we
3748 * handle encap
3749 */
3750 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
3751 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3752 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
3753 struct net_device *uplink_upper;
3754 struct mlx5e_rep_priv *rep_priv;
3755
3756 if (is_duplicated_output_device(priv->netdev,
3757 out_dev,
3758 ifindexes,
3759 if_count,
3760 extack))
3761 return -EOPNOTSUPP;
3762
3763 ifindexes[if_count] = out_dev->ifindex;
3764 if_count++;
3765
3766 rcu_read_lock();
3767 uplink_upper =
3768 netdev_master_upper_dev_get_rcu(uplink_dev);
3769 if (uplink_upper &&
3770 netif_is_lag_master(uplink_upper) &&
3771 uplink_upper == out_dev)
3772 out_dev = uplink_dev;
3773 rcu_read_unlock();
3774
3775 if (is_vlan_dev(out_dev)) {
3776 err = add_vlan_push_action(priv, attr,
3777 &out_dev,
3778 &action);
3779 if (err)
3780 return err;
3781 }
3782
3783 if (is_vlan_dev(parse_attr->filter_dev)) {
3784 err = add_vlan_pop_action(priv, attr,
3785 &action);
3786 if (err)
3787 return err;
3788 }
3789
3790 /* Don't allow forwarding between uplink.
3791 *
3792 * Input vport was stored esw_attr->in_rep.
3793 * In LAG case, *priv* is the private data of
3794 * uplink which may be not the input vport.
3795 */
3796 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3797 if (mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3798 mlx5e_eswitch_uplink_rep(out_dev)) {
3799 NL_SET_ERR_MSG_MOD(extack,
3800 "devices are both uplink, can't offload forwarding");
3801 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3802 priv->netdev->name, out_dev->name);
3803 return -EOPNOTSUPP;
3804 }
3805
3806 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3807 NL_SET_ERR_MSG_MOD(extack,
3808 "devices are not on same switch HW, can't offload forwarding");
3809 netdev_warn(priv->netdev,
3810 "devices %s %s not on same switch HW, can't offload forwarding\n",
3811 priv->netdev->name,
3812 out_dev->name);
3813 return -EOPNOTSUPP;
3814 }
3815
3816 out_priv = netdev_priv(out_dev);
3817 rpriv = out_priv->ppriv;
3818 attr->dests[attr->out_count].rep = rpriv->rep;
3819 attr->dests[attr->out_count].mdev = out_priv->mdev;
3820 attr->out_count++;
3821 } else if (parse_attr->filter_dev != priv->netdev) {
3822 /* All mlx5 devices are called to configure
3823 * high level device filters. Therefore, the
3824 * *attempt* to install a filter on invalid
3825 * eswitch should not trigger an explicit error
3826 */
3827 return -EINVAL;
3828 } else {
3829 NL_SET_ERR_MSG_MOD(extack,
3830 "devices are not on same switch HW, can't offload forwarding");
3831 netdev_warn(priv->netdev,
3832 "devices %s %s not on same switch HW, can't offload forwarding\n",
3833 priv->netdev->name,
3834 out_dev->name);
3835 return -EINVAL;
3836 }
3837 }
3838 break;
3839 case FLOW_ACTION_TUNNEL_ENCAP:
3840 info = act->tunnel;
3841 if (info)
3842 encap = true;
3843 else
3844 return -EOPNOTSUPP;
3845
3846 break;
3847 case FLOW_ACTION_VLAN_PUSH:
3848 case FLOW_ACTION_VLAN_POP:
3849 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3850 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3851 /* Replace vlan pop+push with vlan modify */
3852 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3853 err = add_vlan_rewrite_action(priv,
3854 MLX5_FLOW_NAMESPACE_FDB,
3855 act, parse_attr, hdrs,
3856 &action, extack);
3857 } else {
3858 err = parse_tc_vlan_action(priv, act, attr, &action);
3859 }
3860 if (err)
3861 return err;
3862
3863 attr->split_count = attr->out_count;
3864 break;
3865 case FLOW_ACTION_VLAN_MANGLE:
3866 err = add_vlan_rewrite_action(priv,
3867 MLX5_FLOW_NAMESPACE_FDB,
3868 act, parse_attr, hdrs,
3869 &action, extack);
3870 if (err)
3871 return err;
3872
3873 attr->split_count = attr->out_count;
3874 break;
3875 case FLOW_ACTION_TUNNEL_DECAP:
3876 decap = true;
3877 break;
3878 case FLOW_ACTION_GOTO:
3879 err = mlx5_validate_goto_chain(esw, flow, act, action,
3880 extack);
3881 if (err)
3882 return err;
3883
3884 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3885 attr->dest_chain = act->chain_index;
3886 break;
3887 case FLOW_ACTION_CT:
3888 err = mlx5_tc_ct_parse_action(priv, attr, act, extack);
3889 if (err)
3890 return err;
3891
3892 flow_flag_set(flow, CT);
3893 break;
3894 default:
3895 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3896 return -EOPNOTSUPP;
3897 }
3898 }
3899
3900 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3901 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3902 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3903 * tag rewrite.
3904 */
3905 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3906 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3907 &action, extack);
3908 if (err)
3909 return err;
3910 }
3911
3912 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3913 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3914 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3915 parse_attr, hdrs, &action, extack);
3916 if (err)
3917 return err;
3918 /* in case all pedit actions are skipped, remove the MOD_HDR
3919 * flag. we might have set split_count either by pedit or
3920 * pop/push. if there is no pop/push either, reset it too.
3921 */
3922 if (parse_attr->mod_hdr_acts.num_actions == 0) {
3923 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3924 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
3925 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3926 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3927 attr->split_count = 0;
3928 }
3929 }
3930
3931 attr->action = action;
3932 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
3933 return -EOPNOTSUPP;
3934
3935 if (attr->dest_chain) {
3936 if (decap) {
3937 /* It can be supported if we'll create a mapping for
3938 * the tunnel device only (without tunnel), and set
3939 * this tunnel id with this decap flow.
3940 *
3941 * On restore (miss), we'll just set this saved tunnel
3942 * device.
3943 */
3944
3945 NL_SET_ERR_MSG(extack,
3946 "Decap with goto isn't supported");
3947 netdev_warn(priv->netdev,
3948 "Decap with goto isn't supported");
3949 return -EOPNOTSUPP;
3950 }
3951
3952 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3953 NL_SET_ERR_MSG_MOD(extack,
3954 "Mirroring goto chain rules isn't supported");
3955 return -EOPNOTSUPP;
3956 }
3957 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3958 }
3959
3960 if (!(attr->action &
3961 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
3962 NL_SET_ERR_MSG_MOD(extack,
3963 "Rule must have at least one forward/drop action");
3964 return -EOPNOTSUPP;
3965 }
3966
3967 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3968 NL_SET_ERR_MSG_MOD(extack,
3969 "current firmware doesn't support split rule for port mirroring");
3970 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3971 return -EOPNOTSUPP;
3972 }
3973
3974 return 0;
3975 }
3976
3977 static void get_flags(int flags, unsigned long *flow_flags)
3978 {
3979 unsigned long __flow_flags = 0;
3980
3981 if (flags & MLX5_TC_FLAG(INGRESS))
3982 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3983 if (flags & MLX5_TC_FLAG(EGRESS))
3984 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
3985
3986 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3987 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3988 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3989 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
3990 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
3991 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
3992
3993 *flow_flags = __flow_flags;
3994 }
3995
3996 static const struct rhashtable_params tc_ht_params = {
3997 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3998 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3999 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4000 .automatic_shrinking = true,
4001 };
4002
4003 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4004 unsigned long flags)
4005 {
4006 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4007 struct mlx5e_rep_priv *uplink_rpriv;
4008
4009 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
4010 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
4011 return &uplink_rpriv->uplink_priv.tc_ht;
4012 } else /* NIC offload */
4013 return &priv->fs.tc.ht;
4014 }
4015
4016 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4017 {
4018 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
4019 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
4020 flow_flag_test(flow, INGRESS);
4021 bool act_is_encap = !!(attr->action &
4022 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
4023 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
4024 MLX5_DEVCOM_ESW_OFFLOADS);
4025
4026 if (!esw_paired)
4027 return false;
4028
4029 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
4030 mlx5_lag_is_multipath(attr->in_mdev)) &&
4031 (is_rep_ingress || act_is_encap))
4032 return true;
4033
4034 return false;
4035 }
4036
4037 static int
4038 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
4039 struct flow_cls_offload *f, unsigned long flow_flags,
4040 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4041 struct mlx5e_tc_flow **__flow)
4042 {
4043 struct mlx5e_tc_flow_parse_attr *parse_attr;
4044 struct mlx5e_tc_flow *flow;
4045 int out_index, err;
4046
4047 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
4048 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
4049 if (!parse_attr || !flow) {
4050 err = -ENOMEM;
4051 goto err_free;
4052 }
4053
4054 flow->cookie = f->cookie;
4055 flow->flags = flow_flags;
4056 flow->priv = priv;
4057 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4058 INIT_LIST_HEAD(&flow->encaps[out_index].list);
4059 INIT_LIST_HEAD(&flow->mod_hdr);
4060 INIT_LIST_HEAD(&flow->hairpin);
4061 refcount_set(&flow->refcnt, 1);
4062 init_completion(&flow->init_done);
4063
4064 *__flow = flow;
4065 *__parse_attr = parse_attr;
4066
4067 return 0;
4068
4069 err_free:
4070 kfree(flow);
4071 kvfree(parse_attr);
4072 return err;
4073 }
4074
4075 static void
4076 mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
4077 struct mlx5e_priv *priv,
4078 struct mlx5e_tc_flow_parse_attr *parse_attr,
4079 struct flow_cls_offload *f,
4080 struct mlx5_eswitch_rep *in_rep,
4081 struct mlx5_core_dev *in_mdev)
4082 {
4083 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4084
4085 esw_attr->parse_attr = parse_attr;
4086 esw_attr->chain = f->common.chain_index;
4087 esw_attr->prio = f->common.prio;
4088
4089 esw_attr->in_rep = in_rep;
4090 esw_attr->in_mdev = in_mdev;
4091
4092 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4093 MLX5_COUNTER_SOURCE_ESWITCH)
4094 esw_attr->counter_dev = in_mdev;
4095 else
4096 esw_attr->counter_dev = priv->mdev;
4097 }
4098
4099 static struct mlx5e_tc_flow *
4100 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4101 struct flow_cls_offload *f,
4102 unsigned long flow_flags,
4103 struct net_device *filter_dev,
4104 struct mlx5_eswitch_rep *in_rep,
4105 struct mlx5_core_dev *in_mdev)
4106 {
4107 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4108 struct netlink_ext_ack *extack = f->common.extack;
4109 struct mlx5e_tc_flow_parse_attr *parse_attr;
4110 struct mlx5e_tc_flow *flow;
4111 int attr_size, err;
4112
4113 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4114 attr_size = sizeof(struct mlx5_esw_flow_attr);
4115 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4116 &parse_attr, &flow);
4117 if (err)
4118 goto out;
4119
4120 parse_attr->filter_dev = filter_dev;
4121 mlx5e_flow_esw_attr_init(flow->esw_attr,
4122 priv, parse_attr,
4123 f, in_rep, in_mdev);
4124
4125 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4126 f, filter_dev);
4127 if (err)
4128 goto err_free;
4129
4130 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4131 if (err)
4132 goto err_free;
4133
4134 err = mlx5_tc_ct_parse_match(priv, &parse_attr->spec, f, extack);
4135 if (err)
4136 goto err_free;
4137
4138 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
4139 complete_all(&flow->init_done);
4140 if (err) {
4141 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4142 goto err_free;
4143
4144 add_unready_flow(flow);
4145 }
4146
4147 return flow;
4148
4149 err_free:
4150 mlx5e_flow_put(priv, flow);
4151 out:
4152 return ERR_PTR(err);
4153 }
4154
4155 static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
4156 struct mlx5e_tc_flow *flow,
4157 unsigned long flow_flags)
4158 {
4159 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4160 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
4161 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4162 struct mlx5e_tc_flow_parse_attr *parse_attr;
4163 struct mlx5e_rep_priv *peer_urpriv;
4164 struct mlx5e_tc_flow *peer_flow;
4165 struct mlx5_core_dev *in_mdev;
4166 int err = 0;
4167
4168 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4169 if (!peer_esw)
4170 return -ENODEV;
4171
4172 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4173 peer_priv = netdev_priv(peer_urpriv->netdev);
4174
4175 /* in_mdev is assigned of which the packet originated from.
4176 * So packets redirected to uplink use the same mdev of the
4177 * original flow and packets redirected from uplink use the
4178 * peer mdev.
4179 */
4180 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
4181 in_mdev = peer_priv->mdev;
4182 else
4183 in_mdev = priv->mdev;
4184
4185 parse_attr = flow->esw_attr->parse_attr;
4186 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
4187 parse_attr->filter_dev,
4188 flow->esw_attr->in_rep, in_mdev);
4189 if (IS_ERR(peer_flow)) {
4190 err = PTR_ERR(peer_flow);
4191 goto out;
4192 }
4193
4194 flow->peer_flow = peer_flow;
4195 flow_flag_set(flow, DUP);
4196 mutex_lock(&esw->offloads.peer_mutex);
4197 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4198 mutex_unlock(&esw->offloads.peer_mutex);
4199
4200 out:
4201 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4202 return err;
4203 }
4204
4205 static int
4206 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4207 struct flow_cls_offload *f,
4208 unsigned long flow_flags,
4209 struct net_device *filter_dev,
4210 struct mlx5e_tc_flow **__flow)
4211 {
4212 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4213 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4214 struct mlx5_core_dev *in_mdev = priv->mdev;
4215 struct mlx5e_tc_flow *flow;
4216 int err;
4217
4218 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4219 in_mdev);
4220 if (IS_ERR(flow))
4221 return PTR_ERR(flow);
4222
4223 if (is_peer_flow_needed(flow)) {
4224 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
4225 if (err) {
4226 mlx5e_tc_del_fdb_flow(priv, flow);
4227 goto out;
4228 }
4229 }
4230
4231 *__flow = flow;
4232
4233 return 0;
4234
4235 out:
4236 return err;
4237 }
4238
4239 static int
4240 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
4241 struct flow_cls_offload *f,
4242 unsigned long flow_flags,
4243 struct net_device *filter_dev,
4244 struct mlx5e_tc_flow **__flow)
4245 {
4246 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4247 struct netlink_ext_ack *extack = f->common.extack;
4248 struct mlx5e_tc_flow_parse_attr *parse_attr;
4249 struct mlx5e_tc_flow *flow;
4250 int attr_size, err;
4251
4252 /* multi-chain not supported for NIC rules */
4253 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4254 return -EOPNOTSUPP;
4255
4256 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4257 attr_size = sizeof(struct mlx5_nic_flow_attr);
4258 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4259 &parse_attr, &flow);
4260 if (err)
4261 goto out;
4262
4263 parse_attr->filter_dev = filter_dev;
4264 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4265 f, filter_dev);
4266 if (err)
4267 goto err_free;
4268
4269 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
4270 if (err)
4271 goto err_free;
4272
4273 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4274 if (err)
4275 goto err_free;
4276
4277 flow_flag_set(flow, OFFLOADED);
4278 kvfree(parse_attr);
4279 *__flow = flow;
4280
4281 return 0;
4282
4283 err_free:
4284 mlx5e_flow_put(priv, flow);
4285 kvfree(parse_attr);
4286 out:
4287 return err;
4288 }
4289
4290 static int
4291 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
4292 struct flow_cls_offload *f,
4293 unsigned long flags,
4294 struct net_device *filter_dev,
4295 struct mlx5e_tc_flow **flow)
4296 {
4297 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4298 unsigned long flow_flags;
4299 int err;
4300
4301 get_flags(flags, &flow_flags);
4302
4303 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4304 return -EOPNOTSUPP;
4305
4306 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
4307 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4308 filter_dev, flow);
4309 else
4310 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4311 filter_dev, flow);
4312
4313 return err;
4314 }
4315
4316 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
4317 struct flow_cls_offload *f, unsigned long flags)
4318 {
4319 struct netlink_ext_ack *extack = f->common.extack;
4320 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4321 struct mlx5e_tc_flow *flow;
4322 int err = 0;
4323
4324 rcu_read_lock();
4325 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4326 rcu_read_unlock();
4327 if (flow) {
4328 NL_SET_ERR_MSG_MOD(extack,
4329 "flow cookie already exists, ignoring");
4330 netdev_warn_once(priv->netdev,
4331 "flow cookie %lx already exists, ignoring\n",
4332 f->cookie);
4333 err = -EEXIST;
4334 goto out;
4335 }
4336
4337 trace_mlx5e_configure_flower(f);
4338 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
4339 if (err)
4340 goto out;
4341
4342 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
4343 if (err)
4344 goto err_free;
4345
4346 return 0;
4347
4348 err_free:
4349 mlx5e_flow_put(priv, flow);
4350 out:
4351 return err;
4352 }
4353
4354 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4355 {
4356 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4357 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
4358
4359 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4360 flow_flag_test(flow, EGRESS) == dir_egress;
4361 }
4362
4363 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
4364 struct flow_cls_offload *f, unsigned long flags)
4365 {
4366 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4367 struct mlx5e_tc_flow *flow;
4368 int err;
4369
4370 rcu_read_lock();
4371 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4372 if (!flow || !same_flow_direction(flow, flags)) {
4373 err = -EINVAL;
4374 goto errout;
4375 }
4376
4377 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4378 * set.
4379 */
4380 if (flow_flag_test_and_set(flow, DELETED)) {
4381 err = -EINVAL;
4382 goto errout;
4383 }
4384 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
4385 rcu_read_unlock();
4386
4387 trace_mlx5e_delete_flower(f);
4388 mlx5e_flow_put(priv, flow);
4389
4390 return 0;
4391
4392 errout:
4393 rcu_read_unlock();
4394 return err;
4395 }
4396
4397 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
4398 struct flow_cls_offload *f, unsigned long flags)
4399 {
4400 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4401 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4402 struct mlx5_eswitch *peer_esw;
4403 struct mlx5e_tc_flow *flow;
4404 struct mlx5_fc *counter;
4405 u64 lastuse = 0;
4406 u64 packets = 0;
4407 u64 bytes = 0;
4408 int err = 0;
4409
4410 rcu_read_lock();
4411 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4412 tc_ht_params));
4413 rcu_read_unlock();
4414 if (IS_ERR(flow))
4415 return PTR_ERR(flow);
4416
4417 if (!same_flow_direction(flow, flags)) {
4418 err = -EINVAL;
4419 goto errout;
4420 }
4421
4422 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
4423 counter = mlx5e_tc_get_counter(flow);
4424 if (!counter)
4425 goto errout;
4426
4427 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4428 }
4429
4430 /* Under multipath it's possible for one rule to be currently
4431 * un-offloaded while the other rule is offloaded.
4432 */
4433 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4434 if (!peer_esw)
4435 goto out;
4436
4437 if (flow_flag_test(flow, DUP) &&
4438 flow_flag_test(flow->peer_flow, OFFLOADED)) {
4439 u64 bytes2;
4440 u64 packets2;
4441 u64 lastuse2;
4442
4443 counter = mlx5e_tc_get_counter(flow->peer_flow);
4444 if (!counter)
4445 goto no_peer_counter;
4446 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4447
4448 bytes += bytes2;
4449 packets += packets2;
4450 lastuse = max_t(u64, lastuse, lastuse2);
4451 }
4452
4453 no_peer_counter:
4454 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4455 out:
4456 flow_stats_update(&f->stats, bytes, packets, lastuse);
4457 trace_mlx5e_stats_flower(f);
4458 errout:
4459 mlx5e_flow_put(priv, flow);
4460 return err;
4461 }
4462
4463 static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
4464 struct netlink_ext_ack *extack)
4465 {
4466 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4467 struct mlx5_eswitch *esw;
4468 u16 vport_num;
4469 u32 rate_mbps;
4470 int err;
4471
4472 vport_num = rpriv->rep->vport;
4473 if (vport_num >= MLX5_VPORT_ECPF) {
4474 NL_SET_ERR_MSG_MOD(extack,
4475 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4476 return -EOPNOTSUPP;
4477 }
4478
4479 esw = priv->mdev->priv.eswitch;
4480 /* rate is given in bytes/sec.
4481 * First convert to bits/sec and then round to the nearest mbit/secs.
4482 * mbit means million bits.
4483 * Moreover, if rate is non zero we choose to configure to a minimum of
4484 * 1 mbit/sec.
4485 */
4486 rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
4487 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4488 if (err)
4489 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4490
4491 return err;
4492 }
4493
4494 static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4495 struct flow_action *flow_action,
4496 struct netlink_ext_ack *extack)
4497 {
4498 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4499 const struct flow_action_entry *act;
4500 int err;
4501 int i;
4502
4503 if (!flow_action_has_entries(flow_action)) {
4504 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4505 return -EINVAL;
4506 }
4507
4508 if (!flow_offload_has_one_action(flow_action)) {
4509 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4510 return -EOPNOTSUPP;
4511 }
4512
4513 if (!flow_action_basic_hw_stats_types_check(flow_action, extack))
4514 return -EOPNOTSUPP;
4515
4516 flow_action_for_each(i, act, flow_action) {
4517 switch (act->id) {
4518 case FLOW_ACTION_POLICE:
4519 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4520 if (err)
4521 return err;
4522
4523 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4524 break;
4525 default:
4526 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4527 return -EOPNOTSUPP;
4528 }
4529 }
4530
4531 return 0;
4532 }
4533
4534 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4535 struct tc_cls_matchall_offload *ma)
4536 {
4537 struct netlink_ext_ack *extack = ma->common.extack;
4538
4539 if (ma->common.prio != 1) {
4540 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4541 return -EINVAL;
4542 }
4543
4544 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4545 }
4546
4547 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4548 struct tc_cls_matchall_offload *ma)
4549 {
4550 struct netlink_ext_ack *extack = ma->common.extack;
4551
4552 return apply_police_params(priv, 0, extack);
4553 }
4554
4555 void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4556 struct tc_cls_matchall_offload *ma)
4557 {
4558 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4559 struct rtnl_link_stats64 cur_stats;
4560 u64 dbytes;
4561 u64 dpkts;
4562
4563 cur_stats = priv->stats.vf_vport;
4564 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4565 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4566 rpriv->prev_vf_vport_stats = cur_stats;
4567 flow_stats_update(&ma->stats, dpkts, dbytes, jiffies);
4568 }
4569
4570 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4571 struct mlx5e_priv *peer_priv)
4572 {
4573 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
4574 struct mlx5e_hairpin_entry *hpe, *tmp;
4575 LIST_HEAD(init_wait_list);
4576 u16 peer_vhca_id;
4577 int bkt;
4578
4579 if (!same_hw_devs(priv, peer_priv))
4580 return;
4581
4582 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4583
4584 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
4585 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4586 if (refcount_inc_not_zero(&hpe->refcnt))
4587 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4588 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4589
4590 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4591 wait_for_completion(&hpe->res_ready);
4592 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4593 hpe->hp->pair->peer_gone = true;
4594
4595 mlx5e_hairpin_put(priv, hpe);
4596 }
4597 }
4598
4599 static int mlx5e_tc_netdev_event(struct notifier_block *this,
4600 unsigned long event, void *ptr)
4601 {
4602 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4603 struct mlx5e_flow_steering *fs;
4604 struct mlx5e_priv *peer_priv;
4605 struct mlx5e_tc_table *tc;
4606 struct mlx5e_priv *priv;
4607
4608 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4609 event != NETDEV_UNREGISTER ||
4610 ndev->reg_state == NETREG_REGISTERED)
4611 return NOTIFY_DONE;
4612
4613 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4614 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4615 priv = container_of(fs, struct mlx5e_priv, fs);
4616 peer_priv = netdev_priv(ndev);
4617 if (priv == peer_priv ||
4618 !(priv->netdev->features & NETIF_F_HW_TC))
4619 return NOTIFY_DONE;
4620
4621 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4622
4623 return NOTIFY_DONE;
4624 }
4625
4626 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
4627 {
4628 struct mlx5e_tc_table *tc = &priv->fs.tc;
4629 int err;
4630
4631 mutex_init(&tc->t_lock);
4632 mutex_init(&tc->mod_hdr.lock);
4633 hash_init(tc->mod_hdr.hlist);
4634 mutex_init(&tc->hairpin_tbl_lock);
4635 hash_init(tc->hairpin_tbl);
4636
4637 err = rhashtable_init(&tc->ht, &tc_ht_params);
4638 if (err)
4639 return err;
4640
4641 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
4642 err = register_netdevice_notifier_dev_net(priv->netdev,
4643 &tc->netdevice_nb,
4644 &tc->netdevice_nn);
4645 if (err) {
4646 tc->netdevice_nb.notifier_call = NULL;
4647 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
4648 }
4649
4650 return err;
4651 }
4652
4653 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4654 {
4655 struct mlx5e_tc_flow *flow = ptr;
4656 struct mlx5e_priv *priv = flow->priv;
4657
4658 mlx5e_tc_del_flow(priv, flow);
4659 kfree(flow);
4660 }
4661
4662 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
4663 {
4664 struct mlx5e_tc_table *tc = &priv->fs.tc;
4665
4666 if (tc->netdevice_nb.notifier_call)
4667 unregister_netdevice_notifier_dev_net(priv->netdev,
4668 &tc->netdevice_nb,
4669 &tc->netdevice_nn);
4670
4671 mutex_destroy(&tc->mod_hdr.lock);
4672 mutex_destroy(&tc->hairpin_tbl_lock);
4673
4674 rhashtable_destroy(&tc->ht);
4675
4676 if (!IS_ERR_OR_NULL(tc->t)) {
4677 mlx5_destroy_flow_table(tc->t);
4678 tc->t = NULL;
4679 }
4680 mutex_destroy(&tc->t_lock);
4681 }
4682
4683 int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4684 {
4685 const size_t sz_enc_opts = sizeof(struct flow_dissector_key_enc_opts);
4686 struct mlx5_rep_uplink_priv *uplink_priv;
4687 struct mlx5e_rep_priv *priv;
4688 struct mapping_ctx *mapping;
4689 int err;
4690
4691 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
4692 priv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4693
4694 err = mlx5_tc_ct_init(uplink_priv);
4695 if (err)
4696 goto err_ct;
4697
4698 mapping = mapping_create(sizeof(struct tunnel_match_key),
4699 TUNNEL_INFO_BITS_MASK, true);
4700 if (IS_ERR(mapping)) {
4701 err = PTR_ERR(mapping);
4702 goto err_tun_mapping;
4703 }
4704 uplink_priv->tunnel_mapping = mapping;
4705
4706 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK, true);
4707 if (IS_ERR(mapping)) {
4708 err = PTR_ERR(mapping);
4709 goto err_enc_opts_mapping;
4710 }
4711 uplink_priv->tunnel_enc_opts_mapping = mapping;
4712
4713 err = rhashtable_init(tc_ht, &tc_ht_params);
4714 if (err)
4715 goto err_ht_init;
4716
4717 return err;
4718
4719 err_ht_init:
4720 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4721 err_enc_opts_mapping:
4722 mapping_destroy(uplink_priv->tunnel_mapping);
4723 err_tun_mapping:
4724 mlx5_tc_ct_clean(uplink_priv);
4725 err_ct:
4726 netdev_warn(priv->netdev,
4727 "Failed to initialize tc (eswitch), err: %d", err);
4728 return err;
4729 }
4730
4731 void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4732 {
4733 struct mlx5_rep_uplink_priv *uplink_priv;
4734
4735 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4736
4737 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
4738 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4739 mapping_destroy(uplink_priv->tunnel_mapping);
4740
4741 mlx5_tc_ct_clean(uplink_priv);
4742 }
4743
4744 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
4745 {
4746 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4747
4748 return atomic_read(&tc_ht->nelems);
4749 }
4750
4751 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4752 {
4753 struct mlx5e_tc_flow *flow, *tmp;
4754
4755 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4756 __mlx5e_tc_del_fdb_peer_flow(flow);
4757 }
4758
4759 void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4760 {
4761 struct mlx5_rep_uplink_priv *rpriv =
4762 container_of(work, struct mlx5_rep_uplink_priv,
4763 reoffload_flows_work);
4764 struct mlx5e_tc_flow *flow, *tmp;
4765
4766 mutex_lock(&rpriv->unready_flows_lock);
4767 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4768 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
4769 unready_flow_del(flow);
4770 }
4771 mutex_unlock(&rpriv->unready_flows_lock);
4772 }
4773
4774 #if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
4775 static bool mlx5e_restore_tunnel(struct mlx5e_priv *priv, struct sk_buff *skb,
4776 struct mlx5e_tc_update_priv *tc_priv,
4777 u32 tunnel_id)
4778 {
4779 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4780 struct flow_dissector_key_enc_opts enc_opts = {};
4781 struct mlx5_rep_uplink_priv *uplink_priv;
4782 struct mlx5e_rep_priv *uplink_rpriv;
4783 struct metadata_dst *tun_dst;
4784 struct tunnel_match_key key;
4785 u32 tun_id, enc_opts_id;
4786 struct net_device *dev;
4787 int err;
4788
4789 enc_opts_id = tunnel_id & ENC_OPTS_BITS_MASK;
4790 tun_id = tunnel_id >> ENC_OPTS_BITS;
4791
4792 if (!tun_id)
4793 return true;
4794
4795 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
4796 uplink_priv = &uplink_rpriv->uplink_priv;
4797
4798 err = mapping_find(uplink_priv->tunnel_mapping, tun_id, &key);
4799 if (err) {
4800 WARN_ON_ONCE(true);
4801 netdev_dbg(priv->netdev,
4802 "Couldn't find tunnel for tun_id: %d, err: %d\n",
4803 tun_id, err);
4804 return false;
4805 }
4806
4807 if (enc_opts_id) {
4808 err = mapping_find(uplink_priv->tunnel_enc_opts_mapping,
4809 enc_opts_id, &enc_opts);
4810 if (err) {
4811 netdev_dbg(priv->netdev,
4812 "Couldn't find tunnel (opts) for tun_id: %d, err: %d\n",
4813 enc_opts_id, err);
4814 return false;
4815 }
4816 }
4817
4818 tun_dst = tun_rx_dst(enc_opts.len);
4819 if (!tun_dst) {
4820 WARN_ON_ONCE(true);
4821 return false;
4822 }
4823
4824 ip_tunnel_key_init(&tun_dst->u.tun_info.key,
4825 key.enc_ipv4.src, key.enc_ipv4.dst,
4826 key.enc_ip.tos, key.enc_ip.ttl,
4827 0, /* label */
4828 key.enc_tp.src, key.enc_tp.dst,
4829 key32_to_tunnel_id(key.enc_key_id.keyid),
4830 TUNNEL_KEY);
4831
4832 if (enc_opts.len)
4833 ip_tunnel_info_opts_set(&tun_dst->u.tun_info, enc_opts.data,
4834 enc_opts.len, enc_opts.dst_opt_type);
4835
4836 skb_dst_set(skb, (struct dst_entry *)tun_dst);
4837 dev = dev_get_by_index(&init_net, key.filter_ifindex);
4838 if (!dev) {
4839 netdev_dbg(priv->netdev,
4840 "Couldn't find tunnel device with ifindex: %d\n",
4841 key.filter_ifindex);
4842 return false;
4843 }
4844
4845 /* Set tun_dev so we do dev_put() after datapath */
4846 tc_priv->tun_dev = dev;
4847
4848 skb->dev = dev;
4849
4850 return true;
4851 }
4852 #endif /* CONFIG_NET_TC_SKB_EXT */
4853
4854 bool mlx5e_tc_rep_update_skb(struct mlx5_cqe64 *cqe,
4855 struct sk_buff *skb,
4856 struct mlx5e_tc_update_priv *tc_priv)
4857 {
4858 #if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
4859 u32 chain = 0, reg_c0, reg_c1, tunnel_id, tuple_id;
4860 struct mlx5_rep_uplink_priv *uplink_priv;
4861 struct mlx5e_rep_priv *uplink_rpriv;
4862 struct tc_skb_ext *tc_skb_ext;
4863 struct mlx5_eswitch *esw;
4864 struct mlx5e_priv *priv;
4865 int tunnel_moffset;
4866 int err;
4867
4868 reg_c0 = (be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK);
4869 if (reg_c0 == MLX5_FS_DEFAULT_FLOW_TAG)
4870 reg_c0 = 0;
4871 reg_c1 = be32_to_cpu(cqe->imm_inval_pkey);
4872
4873 if (!reg_c0)
4874 return true;
4875
4876 priv = netdev_priv(skb->dev);
4877 esw = priv->mdev->priv.eswitch;
4878
4879 err = mlx5_eswitch_get_chain_for_tag(esw, reg_c0, &chain);
4880 if (err) {
4881 netdev_dbg(priv->netdev,
4882 "Couldn't find chain for chain tag: %d, err: %d\n",
4883 reg_c0, err);
4884 return false;
4885 }
4886
4887 if (chain) {
4888 tc_skb_ext = skb_ext_add(skb, TC_SKB_EXT);
4889 if (!tc_skb_ext) {
4890 WARN_ON(1);
4891 return false;
4892 }
4893
4894 tc_skb_ext->chain = chain;
4895
4896 tuple_id = reg_c1 & TUPLE_ID_MAX;
4897
4898 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
4899 uplink_priv = &uplink_rpriv->uplink_priv;
4900 if (!mlx5e_tc_ct_restore_flow(uplink_priv, skb, tuple_id))
4901 return false;
4902 }
4903
4904 tunnel_moffset = mlx5e_tc_attr_to_reg_mappings[TUNNEL_TO_REG].moffset;
4905 tunnel_id = reg_c1 >> (8 * tunnel_moffset);
4906 return mlx5e_restore_tunnel(priv, skb, tc_priv, tunnel_id);
4907 #endif /* CONFIG_NET_TC_SKB_EXT */
4908
4909 return true;
4910 }
4911
4912 void mlx5_tc_rep_post_napi_receive(struct mlx5e_tc_update_priv *tc_priv)
4913 {
4914 if (tc_priv->tun_dev)
4915 dev_put(tc_priv->tun_dev);
4916 }