drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include "en.h"
  34
  35 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq)
  36 {
  37         struct mlx5_cqwq *wq = &cq->wq;
  38         u32 ci = mlx5_cqwq_get_ci(wq);
  39         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
  40         int cqe_ownership_bit = cqe->op_own & MLX5_CQE_OWNER_MASK;
  41         int sw_ownership_val = mlx5_cqwq_get_wrap_cnt(wq) & 1;
  42
  43         if (cqe_ownership_bit != sw_ownership_val)
  44                 return NULL;
  45
  46         /* ensure cqe content is read after cqe ownership bit */
  47         rmb();
  48
  49         return cqe;
  50 }
  51
  52 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
  53 {
  54         struct mlx5_wq_cyc *wq;
  55         struct mlx5_cqe64 *cqe;
  56         struct mlx5e_sq *sq;
  57         u16 sqcc;
  58
  59         cqe = mlx5e_get_cqe(cq);
  60         if (likely(!cqe))
  61                 return;
  62
  63         sq = container_of(cq, struct mlx5e_sq, cq);
  64         wq = &sq->wq;
  65
  66         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
  67          * otherwise a cq overrun may occur
  68          */
  69         sqcc = sq->cc;
  70
  71         do {
  72                 u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;
  73                 struct mlx5e_ico_wqe_info *icowi = &sq->ico_wqe_info[ci];
  74
  75                 mlx5_cqwq_pop(&cq->wq);
  76                 sqcc += icowi->num_wqebbs;
  77
  78                 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
  79                         WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n",
  80                                   cqe->op_own);
  81                         break;
  82                 }
  83
  84                 switch (icowi->opcode) {
  85                 case MLX5_OPCODE_NOP:
  86                         break;
  87                 case MLX5_OPCODE_UMR:
  88                         mlx5e_post_rx_fragmented_mpwqe(&sq->channel->rq);
  89                         break;
  90                 default:
  91                         WARN_ONCE(true,
  92                                   "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n",
  93                                   icowi->opcode);
  94                 }
  95
  96         } while ((cqe = mlx5e_get_cqe(cq)));
  97
  98         mlx5_cqwq_update_db_record(&cq->wq);
  99
 100         /* ensure cq space is freed before enabling more cqes */
 101         wmb();
 102
 103         sq->cc = sqcc;
 104 }
 105
 106 int mlx5e_napi_poll(struct napi_struct *napi, int budget)
 107 {
 108         struct mlx5e_channel *c = container_of(napi, struct mlx5e_channel,
 109                                                napi);
 110         bool busy = false;
 111         int work_done;
 112         int i;
 113
 114         clear_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
 115
 116         for (i = 0; i < c->num_tc; i++)
 117                 busy |= mlx5e_poll_tx_cq(&c->sq[i].cq, budget);
 118
 119         work_done = mlx5e_poll_rx_cq(&c->rq.cq, budget);
 120         busy |= work_done == budget;
 121
 122         mlx5e_poll_ico_cq(&c->icosq.cq);
 123
 124         busy |= mlx5e_post_rx_wqes(&c->rq);
 125
 126         if (busy)
 127                 return budget;
 128
 129         napi_complete_done(napi, work_done);
 130
 131         /* avoid losing completion event during/after polling cqs */
 132         if (test_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags)) {
 133                 napi_schedule(napi);
 134                 return work_done;
 135         }
 136
 137         for (i = 0; i < c->num_tc; i++)
 138                 mlx5e_cq_arm(&c->sq[i].cq);
 139
 140         if (test_bit(MLX5E_RQ_STATE_AM, &c->rq.state))
 141                 mlx5e_rx_am(&c->rq);
 142
 143         mlx5e_cq_arm(&c->rq.cq);
 144         mlx5e_cq_arm(&c->icosq.cq);
 145
 146         return work_done;
 147 }
 148
 149 void mlx5e_completion_event(struct mlx5_core_cq *mcq)
 150 {
 151         struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
 152
 153         cq->event_ctr++;
 154         set_bit(MLX5E_CHANNEL_NAPI_SCHED, &cq->channel->flags);
 155         napi_schedule(cq->napi);
 156 }
 157
 158 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event)
 159 {
 160         struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
 161         struct mlx5e_channel *c = cq->channel;
 162         struct mlx5e_priv *priv = c->priv;
 163         struct net_device *netdev = priv->netdev;
 164
 165         netdev_err(netdev, "%s: cqn=0x%.6x event=0x%.2x\n",
 166                    __func__, mcq->cqn, event);
 167 }