drivers/net/ethernet/mellanox/mlx5/core/eq.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/interrupt.h>
  34 #include <linux/module.h>
  35 #include <linux/mlx5/driver.h>
  36 #include <linux/mlx5/cmd.h>
  37 #include "mlx5_core.h"
  38 #ifdef CONFIG_MLX5_CORE_EN
  39 #include "eswitch.h"
  40 #endif
  41
  42 enum {
  43         MLX5_EQE_SIZE           = sizeof(struct mlx5_eqe),
  44         MLX5_EQE_OWNER_INIT_VAL = 0x1,
  45 };
  46
  47 enum {
  48         MLX5_EQ_STATE_ARMED             = 0x9,
  49         MLX5_EQ_STATE_FIRED             = 0xa,
  50         MLX5_EQ_STATE_ALWAYS_ARMED      = 0xb,
  51 };
  52
  53 enum {
  54         MLX5_NUM_SPARE_EQE      = 0x80,
  55         MLX5_NUM_ASYNC_EQE      = 0x100,
  56         MLX5_NUM_CMD_EQE        = 32,
  57 };
  58
  59 enum {
  60         MLX5_EQ_DOORBEL_OFFSET  = 0x40,
  61 };
  62
  63 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG)           | \
  64                                (1ull << MLX5_EVENT_TYPE_COMM_EST)           | \
  65                                (1ull << MLX5_EVENT_TYPE_SQ_DRAINED)         | \
  66                                (1ull << MLX5_EVENT_TYPE_CQ_ERROR)           | \
  67                                (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR)     | \
  68                                (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED)    | \
  69                                (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
  70                                (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR)    | \
  71                                (1ull << MLX5_EVENT_TYPE_PORT_CHANGE)        | \
  72                                (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR)    | \
  73                                (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE)       | \
  74                                (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
  75
  76 struct map_eq_in {
  77         u64     mask;
  78         u32     reserved;
  79         u32     unmap_eqn;
  80 };
  81
  82 struct cre_des_eq {
  83         u8      reserved[15];
  84         u8      eqn;
  85 };
  86
  87 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
  88 {
  89         u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
  90         u32 in[MLX5_ST_SZ_DW(destroy_eq_in)]   = {0};
  91         int err;
  92
  93         MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
  94         MLX5_SET(destroy_eq_in, in, eq_number, eqn);
  95
  96         err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
  97         return err ? : mlx5_cmd_status_to_err_v2(out);
  98
  99 }
 100
 101 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
 102 {
 103         return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
 104 }
 105
 106 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
 107 {
 108         struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
 109
 110         return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
 111 }
 112
 113 static const char *eqe_type_str(u8 type)
 114 {
 115         switch (type) {
 116         case MLX5_EVENT_TYPE_COMP:
 117                 return "MLX5_EVENT_TYPE_COMP";
 118         case MLX5_EVENT_TYPE_PATH_MIG:
 119                 return "MLX5_EVENT_TYPE_PATH_MIG";
 120         case MLX5_EVENT_TYPE_COMM_EST:
 121                 return "MLX5_EVENT_TYPE_COMM_EST";
 122         case MLX5_EVENT_TYPE_SQ_DRAINED:
 123                 return "MLX5_EVENT_TYPE_SQ_DRAINED";
 124         case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 125                 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
 126         case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
 127                 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
 128         case MLX5_EVENT_TYPE_CQ_ERROR:
 129                 return "MLX5_EVENT_TYPE_CQ_ERROR";
 130         case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 131                 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
 132         case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 133                 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
 134         case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 135                 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
 136         case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 137                 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
 138         case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
 139                 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
 140         case MLX5_EVENT_TYPE_INTERNAL_ERROR:
 141                 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
 142         case MLX5_EVENT_TYPE_PORT_CHANGE:
 143                 return "MLX5_EVENT_TYPE_PORT_CHANGE";
 144         case MLX5_EVENT_TYPE_GPIO_EVENT:
 145                 return "MLX5_EVENT_TYPE_GPIO_EVENT";
 146         case MLX5_EVENT_TYPE_REMOTE_CONFIG:
 147                 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
 148         case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
 149                 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
 150         case MLX5_EVENT_TYPE_STALL_EVENT:
 151                 return "MLX5_EVENT_TYPE_STALL_EVENT";
 152         case MLX5_EVENT_TYPE_CMD:
 153                 return "MLX5_EVENT_TYPE_CMD";
 154         case MLX5_EVENT_TYPE_PAGE_REQUEST:
 155                 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
 156         case MLX5_EVENT_TYPE_PAGE_FAULT:
 157                 return "MLX5_EVENT_TYPE_PAGE_FAULT";
 158         default:
 159                 return "Unrecognized event";
 160         }
 161 }
 162
 163 static enum mlx5_dev_event port_subtype_event(u8 subtype)
 164 {
 165         switch (subtype) {
 166         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 167                 return MLX5_DEV_EVENT_PORT_DOWN;
 168         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 169                 return MLX5_DEV_EVENT_PORT_UP;
 170         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
 171                 return MLX5_DEV_EVENT_PORT_INITIALIZED;
 172         case MLX5_PORT_CHANGE_SUBTYPE_LID:
 173                 return MLX5_DEV_EVENT_LID_CHANGE;
 174         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
 175                 return MLX5_DEV_EVENT_PKEY_CHANGE;
 176         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
 177                 return MLX5_DEV_EVENT_GUID_CHANGE;
 178         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
 179                 return MLX5_DEV_EVENT_CLIENT_REREG;
 180         }
 181         return -1;
 182 }
 183
 184 static void eq_update_ci(struct mlx5_eq *eq, int arm)
 185 {
 186         __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
 187         u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
 188         __raw_writel((__force u32) cpu_to_be32(val), addr);
 189         /* We still want ordering, just not swabbing, so add a barrier */
 190         mb();
 191 }
 192
 193 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
 194 {
 195         struct mlx5_eqe *eqe;
 196         int eqes_found = 0;
 197         int set_ci = 0;
 198         u32 cqn = -1;
 199         u32 rsn;
 200         u8 port;
 201
 202         while ((eqe = next_eqe_sw(eq))) {
 203                 /*
 204                  * Make sure we read EQ entry contents after we've
 205                  * checked the ownership bit.
 206                  */
 207                 dma_rmb();
 208
 209                 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
 210                               eq->eqn, eqe_type_str(eqe->type));
 211                 switch (eqe->type) {
 212                 case MLX5_EVENT_TYPE_COMP:
 213                         cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
 214                         mlx5_cq_completion(dev, cqn);
 215                         break;
 216
 217                 case MLX5_EVENT_TYPE_PATH_MIG:
 218                 case MLX5_EVENT_TYPE_COMM_EST:
 219                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 220                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 221                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 222                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 223                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 224                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 225                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
 226                         rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
 227                         mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
 228                                       eqe_type_str(eqe->type), eqe->type, rsn);
 229                         mlx5_rsc_event(dev, rsn, eqe->type);
 230                         break;
 231
 232                 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
 233                 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
 234                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
 235                         mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
 236                                       eqe_type_str(eqe->type), eqe->type, rsn);
 237                         mlx5_srq_event(dev, rsn, eqe->type);
 238                         break;
 239
 240                 case MLX5_EVENT_TYPE_CMD:
 241                         mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector));
 242                         break;
 243
 244                 case MLX5_EVENT_TYPE_PORT_CHANGE:
 245                         port = (eqe->data.port.port >> 4) & 0xf;
 246                         switch (eqe->sub_type) {
 247                         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 248                         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 249                         case MLX5_PORT_CHANGE_SUBTYPE_LID:
 250                         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
 251                         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
 252                         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
 253                         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
 254                                 if (dev->event)
 255                                         dev->event(dev, port_subtype_event(eqe->sub_type),
 256                                                    (unsigned long)port);
 257                                 break;
 258                         default:
 259                                 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
 260                                                port, eqe->sub_type);
 261                         }
 262                         break;
 263                 case MLX5_EVENT_TYPE_CQ_ERROR:
 264                         cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
 265                         mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
 266                                        cqn, eqe->data.cq_err.syndrome);
 267                         mlx5_cq_event(dev, cqn, eqe->type);
 268                         break;
 269
 270                 case MLX5_EVENT_TYPE_PAGE_REQUEST:
 271                         {
 272                                 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
 273                                 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
 274
 275                                 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
 276                                               func_id, npages);
 277                                 mlx5_core_req_pages_handler(dev, func_id, npages);
 278                         }
 279                         break;
 280
 281 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 282                 case MLX5_EVENT_TYPE_PAGE_FAULT:
 283                         mlx5_eq_pagefault(dev, eqe);
 284                         break;
 285 #endif
 286
 287 #ifdef CONFIG_MLX5_CORE_EN
 288                 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
 289                         mlx5_eswitch_vport_event(dev->priv.eswitch, eqe);
 290                         break;
 291 #endif
 292                 default:
 293                         mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
 294                                        eqe->type, eq->eqn);
 295                         break;
 296                 }
 297
 298                 ++eq->cons_index;
 299                 eqes_found = 1;
 300                 ++set_ci;
 301
 302                 /* The HCA will think the queue has overflowed if we
 303                  * don't tell it we've been processing events.  We
 304                  * create our EQs with MLX5_NUM_SPARE_EQE extra
 305                  * entries, so we must update our consumer index at
 306                  * least that often.
 307                  */
 308                 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
 309                         eq_update_ci(eq, 0);
 310                         set_ci = 0;
 311                 }
 312         }
 313
 314         eq_update_ci(eq, 1);
 315
 316         if (cqn != -1)
 317                 tasklet_schedule(&eq->tasklet_ctx.task);
 318
 319         return eqes_found;
 320 }
 321
 322 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
 323 {
 324         struct mlx5_eq *eq = eq_ptr;
 325         struct mlx5_core_dev *dev = eq->dev;
 326
 327         mlx5_eq_int(dev, eq);
 328
 329         /* MSI-X vectors always belong to us */
 330         return IRQ_HANDLED;
 331 }
 332
 333 static void init_eq_buf(struct mlx5_eq *eq)
 334 {
 335         struct mlx5_eqe *eqe;
 336         int i;
 337
 338         for (i = 0; i < eq->nent; i++) {
 339                 eqe = get_eqe(eq, i);
 340                 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
 341         }
 342 }
 343
 344 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
 345                        int nent, u64 mask, const char *name, struct mlx5_uar *uar)
 346 {
 347         u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
 348         struct mlx5_priv *priv = &dev->priv;
 349         __be64 *pas;
 350         void *eqc;
 351         int inlen;
 352         u32 *in;
 353         int err;
 354
 355         eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
 356         eq->cons_index = 0;
 357         err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
 358         if (err)
 359                 return err;
 360
 361         init_eq_buf(eq);
 362
 363         inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
 364                 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
 365
 366         in = mlx5_vzalloc(inlen);
 367         if (!in) {
 368                 err = -ENOMEM;
 369                 goto err_buf;
 370         }
 371
 372         pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
 373         mlx5_fill_page_array(&eq->buf, pas);
 374
 375         MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
 376         MLX5_SET64(create_eq_in, in, event_bitmask, mask);
 377
 378         eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
 379         MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
 380         MLX5_SET(eqc, eqc, uar_page, uar->index);
 381         MLX5_SET(eqc, eqc, intr, vecidx);
 382         MLX5_SET(eqc, eqc, log_page_size,
 383                  eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 384
 385         err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
 386         err = err ? : mlx5_cmd_status_to_err_v2(out);
 387         if (err)
 388                 goto err_in;
 389
 390         snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
 391                  name, pci_name(dev->pdev));
 392
 393         eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
 394         eq->irqn = priv->msix_arr[vecidx].vector;
 395         eq->dev = dev;
 396         eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;
 397         err = request_irq(eq->irqn, mlx5_msix_handler, 0,
 398                           priv->irq_info[vecidx].name, eq);
 399         if (err)
 400                 goto err_eq;
 401
 402         err = mlx5_debug_eq_add(dev, eq);
 403         if (err)
 404                 goto err_irq;
 405
 406         INIT_LIST_HEAD(&eq->tasklet_ctx.list);
 407         INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
 408         spin_lock_init(&eq->tasklet_ctx.lock);
 409         tasklet_init(&eq->tasklet_ctx.task, mlx5_cq_tasklet_cb,
 410                      (unsigned long)&eq->tasklet_ctx);
 411
 412         /* EQs are created in ARMED state
 413          */
 414         eq_update_ci(eq, 1);
 415
 416         kvfree(in);
 417         return 0;
 418
 419 err_irq:
 420         free_irq(priv->msix_arr[vecidx].vector, eq);
 421
 422 err_eq:
 423         mlx5_cmd_destroy_eq(dev, eq->eqn);
 424
 425 err_in:
 426         kvfree(in);
 427
 428 err_buf:
 429         mlx5_buf_free(dev, &eq->buf);
 430         return err;
 431 }
 432 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
 433
 434 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
 435 {
 436         int err;
 437
 438         mlx5_debug_eq_remove(dev, eq);
 439         free_irq(eq->irqn, eq);
 440         err = mlx5_cmd_destroy_eq(dev, eq->eqn);
 441         if (err)
 442                 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
 443                                eq->eqn);
 444         synchronize_irq(eq->irqn);
 445         tasklet_disable(&eq->tasklet_ctx.task);
 446         mlx5_buf_free(dev, &eq->buf);
 447
 448         return err;
 449 }
 450 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
 451
 452 u32 mlx5_get_msix_vec(struct mlx5_core_dev *dev, int vecidx)
 453 {
 454         return dev->priv.msix_arr[MLX5_EQ_VEC_ASYNC].vector;
 455 }
 456
 457 int mlx5_eq_init(struct mlx5_core_dev *dev)
 458 {
 459         int err;
 460
 461         spin_lock_init(&dev->priv.eq_table.lock);
 462
 463         err = mlx5_eq_debugfs_init(dev);
 464
 465         return err;
 466 }
 467
 468
 469 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
 470 {
 471         mlx5_eq_debugfs_cleanup(dev);
 472 }
 473
 474 int mlx5_start_eqs(struct mlx5_core_dev *dev)
 475 {
 476         struct mlx5_eq_table *table = &dev->priv.eq_table;
 477         u32 async_event_mask = MLX5_ASYNC_EVENT_MASK;
 478         int err;
 479
 480         if (MLX5_CAP_GEN(dev, pg))
 481                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PAGE_FAULT);
 482
 483         if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
 484             MLX5_CAP_GEN(dev, vport_group_manager) &&
 485             mlx5_core_is_pf(dev))
 486                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
 487
 488         err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
 489                                  MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
 490                                  "mlx5_cmd_eq", &dev->priv.uuari.uars[0]);
 491         if (err) {
 492                 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
 493                 return err;
 494         }
 495
 496         mlx5_cmd_use_events(dev);
 497
 498         err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
 499                                  MLX5_NUM_ASYNC_EQE, async_event_mask,
 500                                  "mlx5_async_eq", &dev->priv.uuari.uars[0]);
 501         if (err) {
 502                 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
 503                 goto err1;
 504         }
 505
 506         err = mlx5_create_map_eq(dev, &table->pages_eq,
 507                                  MLX5_EQ_VEC_PAGES,
 508                                  /* TODO: sriov max_vf + */ 1,
 509                                  1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
 510                                  &dev->priv.uuari.uars[0]);
 511         if (err) {
 512                 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
 513                 goto err2;
 514         }
 515
 516         return err;
 517
 518 err2:
 519         mlx5_destroy_unmap_eq(dev, &table->async_eq);
 520
 521 err1:
 522         mlx5_cmd_use_polling(dev);
 523         mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
 524         return err;
 525 }
 526
 527 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
 528 {
 529         struct mlx5_eq_table *table = &dev->priv.eq_table;
 530         int err;
 531
 532         err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
 533         if (err)
 534                 return err;
 535
 536         mlx5_destroy_unmap_eq(dev, &table->async_eq);
 537         mlx5_cmd_use_polling(dev);
 538
 539         err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
 540         if (err)
 541                 mlx5_cmd_use_events(dev);
 542
 543         return err;
 544 }
 545
 546 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
 547                        u32 *out, int outlen)
 548 {
 549         u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0};
 550         int err;
 551
 552         MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ);
 553         MLX5_SET(query_eq_in, in, eq_number, eq->eqn);
 554
 555         err = mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
 556         return err ? : mlx5_cmd_status_to_err_v2(out);
 557 }
 558 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);