2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_FPGA_H__
34 #define __MLX5_FPGA_H__
36 #include <linux/mlx5/driver.h>
38 enum mlx5_fpga_device_id
{
39 MLX5_FPGA_DEVICE_UNKNOWN
= 0,
40 MLX5_FPGA_DEVICE_KU040
= 1,
41 MLX5_FPGA_DEVICE_KU060
= 2,
42 MLX5_FPGA_DEVICE_KU060_2
= 3,
45 enum mlx5_fpga_image
{
46 MLX5_FPGA_IMAGE_USER
= 0,
47 MLX5_FPGA_IMAGE_FACTORY
,
50 enum mlx5_fpga_status
{
51 MLX5_FPGA_STATUS_SUCCESS
= 0,
52 MLX5_FPGA_STATUS_FAILURE
= 1,
53 MLX5_FPGA_STATUS_IN_PROGRESS
= 2,
54 MLX5_FPGA_STATUS_NONE
= 0xFFFF,
57 struct mlx5_fpga_query
{
58 enum mlx5_fpga_image admin_image
;
59 enum mlx5_fpga_image oper_image
;
60 enum mlx5_fpga_status status
;
63 enum mlx5_fpga_qpc_field_select
{
64 MLX5_FPGA_QPC_STATE
= BIT(0),
67 struct mlx5_fpga_qp_counters
{
75 int mlx5_fpga_caps(struct mlx5_core_dev
*dev
);
76 int mlx5_fpga_query(struct mlx5_core_dev
*dev
, struct mlx5_fpga_query
*query
);
77 int mlx5_fpga_ctrl_op(struct mlx5_core_dev
*dev
, u8 op
);
78 int mlx5_fpga_access_reg(struct mlx5_core_dev
*dev
, u8 size
, u64 addr
,
79 void *buf
, bool write
);
80 int mlx5_fpga_sbu_caps(struct mlx5_core_dev
*dev
, void *caps
, int size
);
82 int mlx5_fpga_create_qp(struct mlx5_core_dev
*dev
, void *fpga_qpc
,
84 int mlx5_fpga_modify_qp(struct mlx5_core_dev
*dev
, u32 fpga_qpn
,
85 enum mlx5_fpga_qpc_field_select fields
, void *fpga_qpc
);
86 int mlx5_fpga_query_qp(struct mlx5_core_dev
*dev
, u32 fpga_qpn
, void *fpga_qpc
);
87 int mlx5_fpga_query_qp_counters(struct mlx5_core_dev
*dev
, u32 fpga_qpn
,
88 bool clear
, struct mlx5_fpga_qp_counters
*data
);
89 int mlx5_fpga_destroy_qp(struct mlx5_core_dev
*dev
, u32 fpga_qpn
);
91 #endif /* __MLX5_FPGA_H__ */