2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/mlx5/mlx5_ifc.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
56 #ifdef CONFIG_MLX5_CORE_EN
60 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
61 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
62 MODULE_LICENSE("Dual BSD/GPL");
63 MODULE_VERSION(DRIVER_VERSION
);
65 unsigned int mlx5_core_debug_mask
;
66 module_param_named(debug_mask
, mlx5_core_debug_mask
, uint
, 0644);
67 MODULE_PARM_DESC(debug_mask
, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
69 #define MLX5_DEFAULT_PROF 2
70 static unsigned int prof_sel
= MLX5_DEFAULT_PROF
;
71 module_param_named(prof_sel
, prof_sel
, uint
, 0444);
72 MODULE_PARM_DESC(prof_sel
, "profile selector. Valid range 0 - 2");
75 MLX5_ATOMIC_REQ_MODE_BE
= 0x0,
76 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
= 0x1,
79 static struct mlx5_profile profile
[] = {
84 .mask
= MLX5_PROF_MASK_QP_SIZE
,
88 .mask
= MLX5_PROF_MASK_QP_SIZE
|
89 MLX5_PROF_MASK_MR_CACHE
,
178 #define FW_INIT_TIMEOUT_MILI 2000
179 #define FW_INIT_WAIT_MS 2
181 static int wait_fw_init(struct mlx5_core_dev
*dev
, u32 max_wait_mili
)
183 unsigned long end
= jiffies
+ msecs_to_jiffies(max_wait_mili
);
186 while (fw_initializing(dev
)) {
187 if (time_after(jiffies
, end
)) {
191 msleep(FW_INIT_WAIT_MS
);
197 static void mlx5_set_driver_version(struct mlx5_core_dev
*dev
)
199 int driver_ver_sz
= MLX5_FLD_SZ_BYTES(set_driver_version_in
,
201 u8 in
[MLX5_ST_SZ_BYTES(set_driver_version_in
)] = {0};
202 u8 out
[MLX5_ST_SZ_BYTES(set_driver_version_out
)] = {0};
203 int remaining_size
= driver_ver_sz
;
206 if (!MLX5_CAP_GEN(dev
, driver_version
))
209 string
= MLX5_ADDR_OF(set_driver_version_in
, in
, driver_version
);
211 strncpy(string
, "Linux", remaining_size
);
213 remaining_size
= max_t(int, 0, driver_ver_sz
- strlen(string
));
214 strncat(string
, ",", remaining_size
);
216 remaining_size
= max_t(int, 0, driver_ver_sz
- strlen(string
));
217 strncat(string
, DRIVER_NAME
, remaining_size
);
219 remaining_size
= max_t(int, 0, driver_ver_sz
- strlen(string
));
220 strncat(string
, ",", remaining_size
);
222 remaining_size
= max_t(int, 0, driver_ver_sz
- strlen(string
));
223 strncat(string
, DRIVER_VERSION
, remaining_size
);
226 MLX5_SET(set_driver_version_in
, in
, opcode
,
227 MLX5_CMD_OP_SET_DRIVER_VERSION
);
229 mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, sizeof(out
));
232 static int set_dma_caps(struct pci_dev
*pdev
)
236 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
238 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask\n");
239 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
241 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting\n");
246 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
249 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
250 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
253 "Can't set consistent PCI DMA mask, aborting\n");
258 dma_set_max_seg_size(&pdev
->dev
, 2u * 1024 * 1024 * 1024);
262 static int mlx5_pci_enable_device(struct mlx5_core_dev
*dev
)
264 struct pci_dev
*pdev
= dev
->pdev
;
267 mutex_lock(&dev
->pci_status_mutex
);
268 if (dev
->pci_status
== MLX5_PCI_STATUS_DISABLED
) {
269 err
= pci_enable_device(pdev
);
271 dev
->pci_status
= MLX5_PCI_STATUS_ENABLED
;
273 mutex_unlock(&dev
->pci_status_mutex
);
278 static void mlx5_pci_disable_device(struct mlx5_core_dev
*dev
)
280 struct pci_dev
*pdev
= dev
->pdev
;
282 mutex_lock(&dev
->pci_status_mutex
);
283 if (dev
->pci_status
== MLX5_PCI_STATUS_ENABLED
) {
284 pci_disable_device(pdev
);
285 dev
->pci_status
= MLX5_PCI_STATUS_DISABLED
;
287 mutex_unlock(&dev
->pci_status_mutex
);
290 static int request_bar(struct pci_dev
*pdev
)
294 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
295 dev_err(&pdev
->dev
, "Missing registers BAR, aborting\n");
299 err
= pci_request_regions(pdev
, DRIVER_NAME
);
301 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
306 static void release_bar(struct pci_dev
*pdev
)
308 pci_release_regions(pdev
);
311 static int mlx5_enable_msix(struct mlx5_core_dev
*dev
)
313 struct mlx5_priv
*priv
= &dev
->priv
;
314 struct mlx5_eq_table
*table
= &priv
->eq_table
;
315 int num_eqs
= 1 << MLX5_CAP_GEN(dev
, log_max_eq
);
319 nvec
= MLX5_CAP_GEN(dev
, num_ports
) * num_online_cpus() +
320 MLX5_EQ_VEC_COMP_BASE
;
321 nvec
= min_t(int, nvec
, num_eqs
);
322 if (nvec
<= MLX5_EQ_VEC_COMP_BASE
)
325 priv
->msix_arr
= kcalloc(nvec
, sizeof(*priv
->msix_arr
), GFP_KERNEL
);
327 priv
->irq_info
= kcalloc(nvec
, sizeof(*priv
->irq_info
), GFP_KERNEL
);
328 if (!priv
->msix_arr
|| !priv
->irq_info
)
331 for (i
= 0; i
< nvec
; i
++)
332 priv
->msix_arr
[i
].entry
= i
;
334 nvec
= pci_enable_msix_range(dev
->pdev
, priv
->msix_arr
,
335 MLX5_EQ_VEC_COMP_BASE
+ 1, nvec
);
339 table
->num_comp_vectors
= nvec
- MLX5_EQ_VEC_COMP_BASE
;
344 kfree(priv
->irq_info
);
345 kfree(priv
->msix_arr
);
349 static void mlx5_disable_msix(struct mlx5_core_dev
*dev
)
351 struct mlx5_priv
*priv
= &dev
->priv
;
353 pci_disable_msix(dev
->pdev
);
354 kfree(priv
->irq_info
);
355 kfree(priv
->msix_arr
);
358 struct mlx5_reg_host_endianess
{
364 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
367 MLX5_CAP_BITS_RW_MASK
= CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM
, 2) |
368 MLX5_DEV_CAP_FLAG_DCT
,
371 static u16
to_fw_pkey_sz(struct mlx5_core_dev
*dev
, u32 size
)
387 mlx5_core_warn(dev
, "invalid pkey table size %d\n", size
);
392 static int mlx5_core_get_caps_mode(struct mlx5_core_dev
*dev
,
393 enum mlx5_cap_type cap_type
,
394 enum mlx5_cap_mode cap_mode
)
396 u8 in
[MLX5_ST_SZ_BYTES(query_hca_cap_in
)];
397 int out_sz
= MLX5_ST_SZ_BYTES(query_hca_cap_out
);
398 void *out
, *hca_caps
;
399 u16 opmod
= (cap_type
<< 1) | (cap_mode
& 0x01);
402 memset(in
, 0, sizeof(in
));
403 out
= kzalloc(out_sz
, GFP_KERNEL
);
407 MLX5_SET(query_hca_cap_in
, in
, opcode
, MLX5_CMD_OP_QUERY_HCA_CAP
);
408 MLX5_SET(query_hca_cap_in
, in
, op_mod
, opmod
);
409 err
= mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, out_sz
);
412 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
413 cap_type
, cap_mode
, err
);
417 hca_caps
= MLX5_ADDR_OF(query_hca_cap_out
, out
, capability
);
420 case HCA_CAP_OPMOD_GET_MAX
:
421 memcpy(dev
->caps
.hca_max
[cap_type
], hca_caps
,
422 MLX5_UN_SZ_BYTES(hca_cap_union
));
424 case HCA_CAP_OPMOD_GET_CUR
:
425 memcpy(dev
->caps
.hca_cur
[cap_type
], hca_caps
,
426 MLX5_UN_SZ_BYTES(hca_cap_union
));
430 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
440 int mlx5_core_get_caps(struct mlx5_core_dev
*dev
, enum mlx5_cap_type cap_type
)
444 ret
= mlx5_core_get_caps_mode(dev
, cap_type
, HCA_CAP_OPMOD_GET_CUR
);
447 return mlx5_core_get_caps_mode(dev
, cap_type
, HCA_CAP_OPMOD_GET_MAX
);
450 static int set_caps(struct mlx5_core_dev
*dev
, void *in
, int in_sz
, int opmod
)
452 u32 out
[MLX5_ST_SZ_DW(set_hca_cap_out
)] = {0};
454 MLX5_SET(set_hca_cap_in
, in
, opcode
, MLX5_CMD_OP_SET_HCA_CAP
);
455 MLX5_SET(set_hca_cap_in
, in
, op_mod
, opmod
<< 1);
456 return mlx5_cmd_exec(dev
, in
, in_sz
, out
, sizeof(out
));
459 static int handle_hca_cap_atomic(struct mlx5_core_dev
*dev
)
463 int set_sz
= MLX5_ST_SZ_BYTES(set_hca_cap_in
);
467 if (MLX5_CAP_GEN(dev
, atomic
)) {
468 err
= mlx5_core_get_caps(dev
, MLX5_CAP_ATOMIC
);
477 supported_atomic_req_8B_endianess_mode_1
);
479 if (req_endianness
!= MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
)
482 set_ctx
= kzalloc(set_sz
, GFP_KERNEL
);
486 set_hca_cap
= MLX5_ADDR_OF(set_hca_cap_in
, set_ctx
, capability
);
488 /* Set requestor to host endianness */
489 MLX5_SET(atomic_caps
, set_hca_cap
, atomic_req_8B_endianess_mode
,
490 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
);
492 err
= set_caps(dev
, set_ctx
, set_sz
, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC
);
498 static int handle_hca_cap(struct mlx5_core_dev
*dev
)
500 void *set_ctx
= NULL
;
501 struct mlx5_profile
*prof
= dev
->profile
;
503 int set_sz
= MLX5_ST_SZ_BYTES(set_hca_cap_in
);
506 set_ctx
= kzalloc(set_sz
, GFP_KERNEL
);
510 err
= mlx5_core_get_caps(dev
, MLX5_CAP_GENERAL
);
514 set_hca_cap
= MLX5_ADDR_OF(set_hca_cap_in
, set_ctx
,
516 memcpy(set_hca_cap
, dev
->caps
.hca_cur
[MLX5_CAP_GENERAL
],
517 MLX5_ST_SZ_BYTES(cmd_hca_cap
));
519 mlx5_core_dbg(dev
, "Current Pkey table size %d Setting new size %d\n",
520 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev
, pkey_table_size
)),
522 /* we limit the size of the pkey table to 128 entries for now */
523 MLX5_SET(cmd_hca_cap
, set_hca_cap
, pkey_table_size
,
524 to_fw_pkey_sz(dev
, 128));
526 /* Check log_max_qp from HCA caps to set in current profile */
527 if (MLX5_CAP_GEN_MAX(dev
, log_max_qp
) < profile
[prof_sel
].log_max_qp
) {
528 mlx5_core_warn(dev
, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
529 profile
[prof_sel
].log_max_qp
,
530 MLX5_CAP_GEN_MAX(dev
, log_max_qp
));
531 profile
[prof_sel
].log_max_qp
= MLX5_CAP_GEN_MAX(dev
, log_max_qp
);
533 if (prof
->mask
& MLX5_PROF_MASK_QP_SIZE
)
534 MLX5_SET(cmd_hca_cap
, set_hca_cap
, log_max_qp
,
537 /* disable cmdif checksum */
538 MLX5_SET(cmd_hca_cap
, set_hca_cap
, cmdif_checksum
, 0);
540 /* If the HCA supports 4K UARs use it */
541 if (MLX5_CAP_GEN_MAX(dev
, uar_4k
))
542 MLX5_SET(cmd_hca_cap
, set_hca_cap
, uar_4k
, 1);
544 MLX5_SET(cmd_hca_cap
, set_hca_cap
, log_uar_page_sz
, PAGE_SHIFT
- 12);
546 if (MLX5_CAP_GEN_MAX(dev
, cache_line_128byte
))
547 MLX5_SET(cmd_hca_cap
,
550 cache_line_size() == 128 ? 1 : 0);
552 err
= set_caps(dev
, set_ctx
, set_sz
,
553 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE
);
560 static int set_hca_ctrl(struct mlx5_core_dev
*dev
)
562 struct mlx5_reg_host_endianess he_in
;
563 struct mlx5_reg_host_endianess he_out
;
566 if (!mlx5_core_is_pf(dev
))
569 memset(&he_in
, 0, sizeof(he_in
));
570 he_in
.he
= MLX5_SET_HOST_ENDIANNESS
;
571 err
= mlx5_core_access_reg(dev
, &he_in
, sizeof(he_in
),
572 &he_out
, sizeof(he_out
),
573 MLX5_REG_HOST_ENDIANNESS
, 0, 1);
577 int mlx5_core_enable_hca(struct mlx5_core_dev
*dev
, u16 func_id
)
579 u32 out
[MLX5_ST_SZ_DW(enable_hca_out
)] = {0};
580 u32 in
[MLX5_ST_SZ_DW(enable_hca_in
)] = {0};
582 MLX5_SET(enable_hca_in
, in
, opcode
, MLX5_CMD_OP_ENABLE_HCA
);
583 MLX5_SET(enable_hca_in
, in
, function_id
, func_id
);
584 return mlx5_cmd_exec(dev
, &in
, sizeof(in
), &out
, sizeof(out
));
587 int mlx5_core_disable_hca(struct mlx5_core_dev
*dev
, u16 func_id
)
589 u32 out
[MLX5_ST_SZ_DW(disable_hca_out
)] = {0};
590 u32 in
[MLX5_ST_SZ_DW(disable_hca_in
)] = {0};
592 MLX5_SET(disable_hca_in
, in
, opcode
, MLX5_CMD_OP_DISABLE_HCA
);
593 MLX5_SET(disable_hca_in
, in
, function_id
, func_id
);
594 return mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, sizeof(out
));
597 u64
mlx5_read_internal_timer(struct mlx5_core_dev
*dev
)
599 u32 timer_h
, timer_h1
, timer_l
;
601 timer_h
= ioread32be(&dev
->iseg
->internal_timer_h
);
602 timer_l
= ioread32be(&dev
->iseg
->internal_timer_l
);
603 timer_h1
= ioread32be(&dev
->iseg
->internal_timer_h
);
604 if (timer_h
!= timer_h1
) /* wrap around */
605 timer_l
= ioread32be(&dev
->iseg
->internal_timer_l
);
607 return (u64
)timer_l
| (u64
)timer_h1
<< 32;
610 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev
*mdev
, int i
)
612 struct mlx5_priv
*priv
= &mdev
->priv
;
613 struct msix_entry
*msix
= priv
->msix_arr
;
614 int irq
= msix
[i
+ MLX5_EQ_VEC_COMP_BASE
].vector
;
617 if (!zalloc_cpumask_var(&priv
->irq_info
[i
].mask
, GFP_KERNEL
)) {
618 mlx5_core_warn(mdev
, "zalloc_cpumask_var failed");
622 cpumask_set_cpu(cpumask_local_spread(i
, priv
->numa_node
),
623 priv
->irq_info
[i
].mask
);
625 err
= irq_set_affinity_hint(irq
, priv
->irq_info
[i
].mask
);
627 mlx5_core_warn(mdev
, "irq_set_affinity_hint failed,irq 0x%.4x",
635 free_cpumask_var(priv
->irq_info
[i
].mask
);
639 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev
*mdev
, int i
)
641 struct mlx5_priv
*priv
= &mdev
->priv
;
642 struct msix_entry
*msix
= priv
->msix_arr
;
643 int irq
= msix
[i
+ MLX5_EQ_VEC_COMP_BASE
].vector
;
645 irq_set_affinity_hint(irq
, NULL
);
646 free_cpumask_var(priv
->irq_info
[i
].mask
);
649 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev
*mdev
)
654 for (i
= 0; i
< mdev
->priv
.eq_table
.num_comp_vectors
; i
++) {
655 err
= mlx5_irq_set_affinity_hint(mdev
, i
);
663 for (i
--; i
>= 0; i
--)
664 mlx5_irq_clear_affinity_hint(mdev
, i
);
669 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev
*mdev
)
673 for (i
= 0; i
< mdev
->priv
.eq_table
.num_comp_vectors
; i
++)
674 mlx5_irq_clear_affinity_hint(mdev
, i
);
677 int mlx5_vector2eqn(struct mlx5_core_dev
*dev
, int vector
, int *eqn
,
680 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
681 struct mlx5_eq
*eq
, *n
;
684 spin_lock(&table
->lock
);
685 list_for_each_entry_safe(eq
, n
, &table
->comp_eqs_list
, list
) {
686 if (eq
->index
== vector
) {
693 spin_unlock(&table
->lock
);
697 EXPORT_SYMBOL(mlx5_vector2eqn
);
699 struct mlx5_eq
*mlx5_eqn2eq(struct mlx5_core_dev
*dev
, int eqn
)
701 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
704 spin_lock(&table
->lock
);
705 list_for_each_entry(eq
, &table
->comp_eqs_list
, list
)
706 if (eq
->eqn
== eqn
) {
707 spin_unlock(&table
->lock
);
711 spin_unlock(&table
->lock
);
713 return ERR_PTR(-ENOENT
);
716 static void free_comp_eqs(struct mlx5_core_dev
*dev
)
718 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
719 struct mlx5_eq
*eq
, *n
;
721 #ifdef CONFIG_RFS_ACCEL
723 free_irq_cpu_rmap(dev
->rmap
);
727 spin_lock(&table
->lock
);
728 list_for_each_entry_safe(eq
, n
, &table
->comp_eqs_list
, list
) {
730 spin_unlock(&table
->lock
);
731 if (mlx5_destroy_unmap_eq(dev
, eq
))
732 mlx5_core_warn(dev
, "failed to destroy EQ 0x%x\n",
735 spin_lock(&table
->lock
);
737 spin_unlock(&table
->lock
);
740 static int alloc_comp_eqs(struct mlx5_core_dev
*dev
)
742 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
743 char name
[MLX5_MAX_IRQ_NAME
];
750 INIT_LIST_HEAD(&table
->comp_eqs_list
);
751 ncomp_vec
= table
->num_comp_vectors
;
752 nent
= MLX5_COMP_EQ_SIZE
;
753 #ifdef CONFIG_RFS_ACCEL
754 dev
->rmap
= alloc_irq_cpu_rmap(ncomp_vec
);
758 for (i
= 0; i
< ncomp_vec
; i
++) {
759 eq
= kzalloc(sizeof(*eq
), GFP_KERNEL
);
765 #ifdef CONFIG_RFS_ACCEL
766 irq_cpu_rmap_add(dev
->rmap
,
767 dev
->priv
.msix_arr
[i
+ MLX5_EQ_VEC_COMP_BASE
].vector
);
769 snprintf(name
, MLX5_MAX_IRQ_NAME
, "mlx5_comp%d", i
);
770 err
= mlx5_create_map_eq(dev
, eq
,
771 i
+ MLX5_EQ_VEC_COMP_BASE
, nent
, 0,
772 name
, MLX5_EQ_TYPE_COMP
);
777 mlx5_core_dbg(dev
, "allocated completion EQN %d\n", eq
->eqn
);
779 spin_lock(&table
->lock
);
780 list_add_tail(&eq
->list
, &table
->comp_eqs_list
);
781 spin_unlock(&table
->lock
);
791 static int mlx5_core_set_issi(struct mlx5_core_dev
*dev
)
793 u32 query_in
[MLX5_ST_SZ_DW(query_issi_in
)] = {0};
794 u32 query_out
[MLX5_ST_SZ_DW(query_issi_out
)] = {0};
798 MLX5_SET(query_issi_in
, query_in
, opcode
, MLX5_CMD_OP_QUERY_ISSI
);
799 err
= mlx5_cmd_exec(dev
, query_in
, sizeof(query_in
),
800 query_out
, sizeof(query_out
));
805 mlx5_cmd_mbox_status(query_out
, &status
, &syndrome
);
806 if (!status
|| syndrome
== MLX5_DRIVER_SYND
) {
807 mlx5_core_err(dev
, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
808 err
, status
, syndrome
);
812 mlx5_core_warn(dev
, "Query ISSI is not supported by FW, ISSI is 0\n");
817 sup_issi
= MLX5_GET(query_issi_out
, query_out
, supported_issi_dw0
);
819 if (sup_issi
& (1 << 1)) {
820 u32 set_in
[MLX5_ST_SZ_DW(set_issi_in
)] = {0};
821 u32 set_out
[MLX5_ST_SZ_DW(set_issi_out
)] = {0};
823 MLX5_SET(set_issi_in
, set_in
, opcode
, MLX5_CMD_OP_SET_ISSI
);
824 MLX5_SET(set_issi_in
, set_in
, current_issi
, 1);
825 err
= mlx5_cmd_exec(dev
, set_in
, sizeof(set_in
),
826 set_out
, sizeof(set_out
));
828 mlx5_core_err(dev
, "Failed to set ISSI to 1 err(%d)\n",
836 } else if (sup_issi
& (1 << 0) || !sup_issi
) {
844 static int mlx5_pci_init(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
846 struct pci_dev
*pdev
= dev
->pdev
;
849 pci_set_drvdata(dev
->pdev
, dev
);
850 strncpy(priv
->name
, dev_name(&pdev
->dev
), MLX5_MAX_NAME_LEN
);
851 priv
->name
[MLX5_MAX_NAME_LEN
- 1] = 0;
853 mutex_init(&priv
->pgdir_mutex
);
854 INIT_LIST_HEAD(&priv
->pgdir_list
);
855 spin_lock_init(&priv
->mkey_lock
);
857 mutex_init(&priv
->alloc_mutex
);
859 priv
->numa_node
= dev_to_node(&dev
->pdev
->dev
);
861 priv
->dbg_root
= debugfs_create_dir(dev_name(&pdev
->dev
), mlx5_debugfs_root
);
865 err
= mlx5_pci_enable_device(dev
);
867 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
871 err
= request_bar(pdev
);
873 dev_err(&pdev
->dev
, "error requesting BARs, aborting\n");
877 pci_set_master(pdev
);
879 err
= set_dma_caps(pdev
);
881 dev_err(&pdev
->dev
, "Failed setting DMA capabilities mask, aborting\n");
885 dev
->iseg_base
= pci_resource_start(dev
->pdev
, 0);
886 dev
->iseg
= ioremap(dev
->iseg_base
, sizeof(*dev
->iseg
));
889 dev_err(&pdev
->dev
, "Failed mapping initialization segment, aborting\n");
896 pci_clear_master(dev
->pdev
);
897 release_bar(dev
->pdev
);
899 mlx5_pci_disable_device(dev
);
902 debugfs_remove(priv
->dbg_root
);
906 static void mlx5_pci_close(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
909 pci_clear_master(dev
->pdev
);
910 release_bar(dev
->pdev
);
911 mlx5_pci_disable_device(dev
);
912 debugfs_remove(priv
->dbg_root
);
915 static int mlx5_init_once(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
917 struct pci_dev
*pdev
= dev
->pdev
;
920 err
= mlx5_query_board_id(dev
);
922 dev_err(&pdev
->dev
, "query board id failed\n");
926 err
= mlx5_eq_init(dev
);
928 dev_err(&pdev
->dev
, "failed to initialize eq\n");
932 err
= mlx5_init_cq_table(dev
);
934 dev_err(&pdev
->dev
, "failed to initialize cq table\n");
938 mlx5_init_qp_table(dev
);
940 mlx5_init_srq_table(dev
);
942 mlx5_init_mkey_table(dev
);
944 err
= mlx5_init_rl_table(dev
);
946 dev_err(&pdev
->dev
, "Failed to init rate limiting\n");
947 goto err_tables_cleanup
;
950 #ifdef CONFIG_MLX5_CORE_EN
951 err
= mlx5_eswitch_init(dev
);
953 dev_err(&pdev
->dev
, "Failed to init eswitch %d\n", err
);
958 err
= mlx5_sriov_init(dev
);
960 dev_err(&pdev
->dev
, "Failed to init sriov %d\n", err
);
961 goto err_eswitch_cleanup
;
967 #ifdef CONFIG_MLX5_CORE_EN
968 mlx5_eswitch_cleanup(dev
->priv
.eswitch
);
972 mlx5_cleanup_rl_table(dev
);
975 mlx5_cleanup_mkey_table(dev
);
976 mlx5_cleanup_srq_table(dev
);
977 mlx5_cleanup_qp_table(dev
);
978 mlx5_cleanup_cq_table(dev
);
981 mlx5_eq_cleanup(dev
);
987 static void mlx5_cleanup_once(struct mlx5_core_dev
*dev
)
989 mlx5_sriov_cleanup(dev
);
990 #ifdef CONFIG_MLX5_CORE_EN
991 mlx5_eswitch_cleanup(dev
->priv
.eswitch
);
993 mlx5_cleanup_rl_table(dev
);
994 mlx5_cleanup_mkey_table(dev
);
995 mlx5_cleanup_srq_table(dev
);
996 mlx5_cleanup_qp_table(dev
);
997 mlx5_cleanup_cq_table(dev
);
998 mlx5_eq_cleanup(dev
);
1001 static int mlx5_load_one(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
,
1004 struct pci_dev
*pdev
= dev
->pdev
;
1007 mutex_lock(&dev
->intf_state_mutex
);
1008 if (test_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
)) {
1009 dev_warn(&dev
->pdev
->dev
, "%s: interface is up, NOP\n",
1014 dev_info(&pdev
->dev
, "firmware version: %d.%d.%d\n", fw_rev_maj(dev
),
1015 fw_rev_min(dev
), fw_rev_sub(dev
));
1017 /* on load removing any previous indication of internal error, device is
1020 dev
->state
= MLX5_DEVICE_STATE_UP
;
1022 err
= mlx5_cmd_init(dev
);
1024 dev_err(&pdev
->dev
, "Failed initializing command interface, aborting\n");
1028 err
= wait_fw_init(dev
, FW_INIT_TIMEOUT_MILI
);
1030 dev_err(&dev
->pdev
->dev
, "Firmware over %d MS in initializing state, aborting\n",
1031 FW_INIT_TIMEOUT_MILI
);
1032 goto err_cmd_cleanup
;
1035 err
= mlx5_core_enable_hca(dev
, 0);
1037 dev_err(&pdev
->dev
, "enable hca failed\n");
1038 goto err_cmd_cleanup
;
1041 err
= mlx5_core_set_issi(dev
);
1043 dev_err(&pdev
->dev
, "failed to set issi\n");
1044 goto err_disable_hca
;
1047 err
= mlx5_satisfy_startup_pages(dev
, 1);
1049 dev_err(&pdev
->dev
, "failed to allocate boot pages\n");
1050 goto err_disable_hca
;
1053 err
= set_hca_ctrl(dev
);
1055 dev_err(&pdev
->dev
, "set_hca_ctrl failed\n");
1056 goto reclaim_boot_pages
;
1059 err
= handle_hca_cap(dev
);
1061 dev_err(&pdev
->dev
, "handle_hca_cap failed\n");
1062 goto reclaim_boot_pages
;
1065 err
= handle_hca_cap_atomic(dev
);
1067 dev_err(&pdev
->dev
, "handle_hca_cap_atomic failed\n");
1068 goto reclaim_boot_pages
;
1071 err
= mlx5_satisfy_startup_pages(dev
, 0);
1073 dev_err(&pdev
->dev
, "failed to allocate init pages\n");
1074 goto reclaim_boot_pages
;
1077 err
= mlx5_pagealloc_start(dev
);
1079 dev_err(&pdev
->dev
, "mlx5_pagealloc_start failed\n");
1080 goto reclaim_boot_pages
;
1083 err
= mlx5_cmd_init_hca(dev
);
1085 dev_err(&pdev
->dev
, "init hca failed\n");
1086 goto err_pagealloc_stop
;
1089 mlx5_set_driver_version(dev
);
1091 mlx5_start_health_poll(dev
);
1093 err
= mlx5_query_hca_caps(dev
);
1095 dev_err(&pdev
->dev
, "query hca failed\n");
1099 if (boot
&& mlx5_init_once(dev
, priv
)) {
1100 dev_err(&pdev
->dev
, "sw objs init failed\n");
1104 err
= mlx5_enable_msix(dev
);
1106 dev_err(&pdev
->dev
, "enable msix failed\n");
1107 goto err_cleanup_once
;
1110 dev
->priv
.uar
= mlx5_get_uars_page(dev
);
1111 if (!dev
->priv
.uar
) {
1112 dev_err(&pdev
->dev
, "Failed allocating uar, aborting\n");
1113 goto err_disable_msix
;
1116 err
= mlx5_start_eqs(dev
);
1118 dev_err(&pdev
->dev
, "Failed to start pages and async EQs\n");
1122 err
= alloc_comp_eqs(dev
);
1124 dev_err(&pdev
->dev
, "Failed to alloc completion EQs\n");
1128 err
= mlx5_irq_set_affinity_hints(dev
);
1130 dev_err(&pdev
->dev
, "Failed to alloc affinity hint cpumask\n");
1131 goto err_affinity_hints
;
1134 err
= mlx5_init_fs(dev
);
1136 dev_err(&pdev
->dev
, "Failed to init flow steering\n");
1140 #ifdef CONFIG_MLX5_CORE_EN
1141 mlx5_eswitch_attach(dev
->priv
.eswitch
);
1144 err
= mlx5_sriov_attach(dev
);
1146 dev_err(&pdev
->dev
, "sriov init failed %d\n", err
);
1150 if (mlx5_device_registered(dev
)) {
1151 mlx5_attach_device(dev
);
1153 err
= mlx5_register_device(dev
);
1155 dev_err(&pdev
->dev
, "mlx5_register_device failed %d\n", err
);
1160 clear_bit(MLX5_INTERFACE_STATE_DOWN
, &dev
->intf_state
);
1161 set_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
);
1163 mutex_unlock(&dev
->intf_state_mutex
);
1168 mlx5_sriov_detach(dev
);
1171 #ifdef CONFIG_MLX5_CORE_EN
1172 mlx5_eswitch_detach(dev
->priv
.eswitch
);
1174 mlx5_cleanup_fs(dev
);
1177 mlx5_irq_clear_affinity_hints(dev
);
1186 mlx5_put_uars_page(dev
, priv
->uar
);
1189 mlx5_disable_msix(dev
);
1193 mlx5_cleanup_once(dev
);
1196 mlx5_stop_health_poll(dev
);
1197 if (mlx5_cmd_teardown_hca(dev
)) {
1198 dev_err(&dev
->pdev
->dev
, "tear_down_hca failed, skip cleanup\n");
1203 mlx5_pagealloc_stop(dev
);
1206 mlx5_reclaim_startup_pages(dev
);
1209 mlx5_core_disable_hca(dev
, 0);
1212 mlx5_cmd_cleanup(dev
);
1215 dev
->state
= MLX5_DEVICE_STATE_INTERNAL_ERROR
;
1216 mutex_unlock(&dev
->intf_state_mutex
);
1221 static int mlx5_unload_one(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
,
1227 mlx5_drain_health_wq(dev
);
1229 mutex_lock(&dev
->intf_state_mutex
);
1230 if (test_bit(MLX5_INTERFACE_STATE_DOWN
, &dev
->intf_state
)) {
1231 dev_warn(&dev
->pdev
->dev
, "%s: interface is down, NOP\n",
1234 mlx5_cleanup_once(dev
);
1238 if (mlx5_device_registered(dev
))
1239 mlx5_detach_device(dev
);
1241 mlx5_sriov_detach(dev
);
1242 #ifdef CONFIG_MLX5_CORE_EN
1243 mlx5_eswitch_detach(dev
->priv
.eswitch
);
1245 mlx5_cleanup_fs(dev
);
1246 mlx5_irq_clear_affinity_hints(dev
);
1249 mlx5_put_uars_page(dev
, priv
->uar
);
1250 mlx5_disable_msix(dev
);
1252 mlx5_cleanup_once(dev
);
1253 mlx5_stop_health_poll(dev
);
1254 err
= mlx5_cmd_teardown_hca(dev
);
1256 dev_err(&dev
->pdev
->dev
, "tear_down_hca failed, skip cleanup\n");
1259 mlx5_pagealloc_stop(dev
);
1260 mlx5_reclaim_startup_pages(dev
);
1261 mlx5_core_disable_hca(dev
, 0);
1262 mlx5_cmd_cleanup(dev
);
1265 clear_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
);
1266 set_bit(MLX5_INTERFACE_STATE_DOWN
, &dev
->intf_state
);
1267 mutex_unlock(&dev
->intf_state_mutex
);
1271 struct mlx5_core_event_handler
{
1272 void (*event
)(struct mlx5_core_dev
*dev
,
1273 enum mlx5_dev_event event
,
1277 static const struct devlink_ops mlx5_devlink_ops
= {
1278 #ifdef CONFIG_MLX5_CORE_EN
1279 .eswitch_mode_set
= mlx5_devlink_eswitch_mode_set
,
1280 .eswitch_mode_get
= mlx5_devlink_eswitch_mode_get
,
1281 .eswitch_inline_mode_set
= mlx5_devlink_eswitch_inline_mode_set
,
1282 .eswitch_inline_mode_get
= mlx5_devlink_eswitch_inline_mode_get
,
1283 .eswitch_encap_mode_set
= mlx5_devlink_eswitch_encap_mode_set
,
1284 .eswitch_encap_mode_get
= mlx5_devlink_eswitch_encap_mode_get
,
1288 #define MLX5_IB_MOD "mlx5_ib"
1289 static int init_one(struct pci_dev
*pdev
,
1290 const struct pci_device_id
*id
)
1292 struct mlx5_core_dev
*dev
;
1293 struct devlink
*devlink
;
1294 struct mlx5_priv
*priv
;
1297 devlink
= devlink_alloc(&mlx5_devlink_ops
, sizeof(*dev
));
1299 dev_err(&pdev
->dev
, "kzalloc failed\n");
1303 dev
= devlink_priv(devlink
);
1305 priv
->pci_dev_data
= id
->driver_data
;
1307 pci_set_drvdata(pdev
, dev
);
1310 dev
->event
= mlx5_core_event
;
1311 dev
->profile
= &profile
[prof_sel
];
1313 INIT_LIST_HEAD(&priv
->ctx_list
);
1314 spin_lock_init(&priv
->ctx_lock
);
1315 mutex_init(&dev
->pci_status_mutex
);
1316 mutex_init(&dev
->intf_state_mutex
);
1318 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1319 err
= init_srcu_struct(&priv
->pfault_srcu
);
1321 dev_err(&pdev
->dev
, "init_srcu_struct failed with error code %d\n",
1326 mutex_init(&priv
->bfregs
.reg_head
.lock
);
1327 mutex_init(&priv
->bfregs
.wc_head
.lock
);
1328 INIT_LIST_HEAD(&priv
->bfregs
.reg_head
.list
);
1329 INIT_LIST_HEAD(&priv
->bfregs
.wc_head
.list
);
1331 err
= mlx5_pci_init(dev
, priv
);
1333 dev_err(&pdev
->dev
, "mlx5_pci_init failed with error code %d\n", err
);
1337 err
= mlx5_health_init(dev
);
1339 dev_err(&pdev
->dev
, "mlx5_health_init failed with error code %d\n", err
);
1343 mlx5_pagealloc_init(dev
);
1345 err
= mlx5_load_one(dev
, priv
, true);
1347 dev_err(&pdev
->dev
, "mlx5_load_one failed with error code %d\n", err
);
1351 request_module_nowait(MLX5_IB_MOD
);
1353 err
= devlink_register(devlink
, &pdev
->dev
);
1357 pci_save_state(pdev
);
1361 mlx5_unload_one(dev
, priv
, true);
1363 mlx5_pagealloc_cleanup(dev
);
1364 mlx5_health_cleanup(dev
);
1366 mlx5_pci_close(dev
, priv
);
1368 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1369 cleanup_srcu_struct(&priv
->pfault_srcu
);
1372 pci_set_drvdata(pdev
, NULL
);
1373 devlink_free(devlink
);
1378 static void remove_one(struct pci_dev
*pdev
)
1380 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1381 struct devlink
*devlink
= priv_to_devlink(dev
);
1382 struct mlx5_priv
*priv
= &dev
->priv
;
1384 devlink_unregister(devlink
);
1385 mlx5_unregister_device(dev
);
1387 if (mlx5_unload_one(dev
, priv
, true)) {
1388 dev_err(&dev
->pdev
->dev
, "mlx5_unload_one failed\n");
1389 mlx5_health_cleanup(dev
);
1393 mlx5_pagealloc_cleanup(dev
);
1394 mlx5_health_cleanup(dev
);
1395 mlx5_pci_close(dev
, priv
);
1396 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1397 cleanup_srcu_struct(&priv
->pfault_srcu
);
1399 pci_set_drvdata(pdev
, NULL
);
1400 devlink_free(devlink
);
1403 static pci_ers_result_t
mlx5_pci_err_detected(struct pci_dev
*pdev
,
1404 pci_channel_state_t state
)
1406 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1407 struct mlx5_priv
*priv
= &dev
->priv
;
1409 dev_info(&pdev
->dev
, "%s was called\n", __func__
);
1411 mlx5_enter_error_state(dev
);
1412 mlx5_unload_one(dev
, priv
, false);
1413 /* In case of kernel call drain the health wq */
1415 mlx5_drain_health_wq(dev
);
1416 mlx5_pci_disable_device(dev
);
1419 return state
== pci_channel_io_perm_failure
?
1420 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
1423 /* wait for the device to show vital signs by waiting
1424 * for the health counter to start counting.
1426 static int wait_vital(struct pci_dev
*pdev
)
1428 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1429 struct mlx5_core_health
*health
= &dev
->priv
.health
;
1430 const int niter
= 100;
1435 for (i
= 0; i
< niter
; i
++) {
1436 count
= ioread32be(health
->health_counter
);
1437 if (count
&& count
!= 0xffffffff) {
1438 if (last_count
&& last_count
!= count
) {
1439 dev_info(&pdev
->dev
, "Counter value 0x%x after %d iterations\n", count
, i
);
1450 static pci_ers_result_t
mlx5_pci_slot_reset(struct pci_dev
*pdev
)
1452 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1455 dev_info(&pdev
->dev
, "%s was called\n", __func__
);
1457 err
= mlx5_pci_enable_device(dev
);
1459 dev_err(&pdev
->dev
, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1461 return PCI_ERS_RESULT_DISCONNECT
;
1464 pci_set_master(pdev
);
1465 pci_restore_state(pdev
);
1466 pci_save_state(pdev
);
1468 if (wait_vital(pdev
)) {
1469 dev_err(&pdev
->dev
, "%s: wait_vital timed out\n", __func__
);
1470 return PCI_ERS_RESULT_DISCONNECT
;
1473 return PCI_ERS_RESULT_RECOVERED
;
1476 static void mlx5_pci_resume(struct pci_dev
*pdev
)
1478 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1479 struct mlx5_priv
*priv
= &dev
->priv
;
1482 dev_info(&pdev
->dev
, "%s was called\n", __func__
);
1484 err
= mlx5_load_one(dev
, priv
, false);
1486 dev_err(&pdev
->dev
, "%s: mlx5_load_one failed with error code: %d\n"
1489 dev_info(&pdev
->dev
, "%s: device recovered\n", __func__
);
1492 static const struct pci_error_handlers mlx5_err_handler
= {
1493 .error_detected
= mlx5_pci_err_detected
,
1494 .slot_reset
= mlx5_pci_slot_reset
,
1495 .resume
= mlx5_pci_resume
1498 static void shutdown(struct pci_dev
*pdev
)
1500 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1501 struct mlx5_priv
*priv
= &dev
->priv
;
1503 dev_info(&pdev
->dev
, "Shutdown was called\n");
1504 /* Notify mlx5 clients that the kernel is being shut down */
1505 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN
, &dev
->intf_state
);
1506 mlx5_unload_one(dev
, priv
, false);
1507 mlx5_pci_disable_device(dev
);
1510 static const struct pci_device_id mlx5_core_pci_table
[] = {
1511 { PCI_VDEVICE(MELLANOX
, 0x1011) }, /* Connect-IB */
1512 { PCI_VDEVICE(MELLANOX
, 0x1012), MLX5_PCI_DEV_IS_VF
}, /* Connect-IB VF */
1513 { PCI_VDEVICE(MELLANOX
, 0x1013) }, /* ConnectX-4 */
1514 { PCI_VDEVICE(MELLANOX
, 0x1014), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-4 VF */
1515 { PCI_VDEVICE(MELLANOX
, 0x1015) }, /* ConnectX-4LX */
1516 { PCI_VDEVICE(MELLANOX
, 0x1016), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-4LX VF */
1517 { PCI_VDEVICE(MELLANOX
, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1518 { PCI_VDEVICE(MELLANOX
, 0x1018), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-5 VF */
1519 { PCI_VDEVICE(MELLANOX
, 0x1019) }, /* ConnectX-5 Ex */
1520 { PCI_VDEVICE(MELLANOX
, 0x101a), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-5 Ex VF */
1521 { PCI_VDEVICE(MELLANOX
, 0x101b) }, /* ConnectX-6 */
1522 { PCI_VDEVICE(MELLANOX
, 0x101c), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-6 VF */
1526 MODULE_DEVICE_TABLE(pci
, mlx5_core_pci_table
);
1528 void mlx5_disable_device(struct mlx5_core_dev
*dev
)
1530 mlx5_pci_err_detected(dev
->pdev
, 0);
1533 void mlx5_recover_device(struct mlx5_core_dev
*dev
)
1535 mlx5_pci_disable_device(dev
);
1536 if (mlx5_pci_slot_reset(dev
->pdev
) == PCI_ERS_RESULT_RECOVERED
)
1537 mlx5_pci_resume(dev
->pdev
);
1540 static struct pci_driver mlx5_core_driver
= {
1541 .name
= DRIVER_NAME
,
1542 .id_table
= mlx5_core_pci_table
,
1544 .remove
= remove_one
,
1545 .shutdown
= shutdown
,
1546 .err_handler
= &mlx5_err_handler
,
1547 .sriov_configure
= mlx5_core_sriov_configure
,
1550 static void mlx5_core_verify_params(void)
1552 if (prof_sel
>= ARRAY_SIZE(profile
)) {
1553 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1555 ARRAY_SIZE(profile
) - 1,
1557 prof_sel
= MLX5_DEFAULT_PROF
;
1561 static int __init
init(void)
1565 mlx5_core_verify_params();
1566 mlx5_register_debugfs();
1568 err
= pci_register_driver(&mlx5_core_driver
);
1572 #ifdef CONFIG_MLX5_CORE_EN
1579 mlx5_unregister_debugfs();
1583 static void __exit
cleanup(void)
1585 #ifdef CONFIG_MLX5_CORE_EN
1588 pci_unregister_driver(&mlx5_core_driver
);
1589 mlx5_unregister_debugfs();
1593 module_exit(cleanup
);