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net/mlx5: Add ConnectX-5 PCIe 4.0 VF device ID
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/delay.h>
50 #include <linux/mlx5/mlx5_ifc.h>
51 #ifdef CONFIG_RFS_ACCEL
52 #include <linux/cpu_rmap.h>
53 #endif
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
56 #include "fs_core.h"
57 #ifdef CONFIG_MLX5_CORE_EN
58 #include "eswitch.h"
59 #endif
60
61 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
62 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
63 MODULE_LICENSE("Dual BSD/GPL");
64 MODULE_VERSION(DRIVER_VERSION);
65
66 int mlx5_core_debug_mask;
67 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
68 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
69
70 #define MLX5_DEFAULT_PROF 2
71 static int prof_sel = MLX5_DEFAULT_PROF;
72 module_param_named(prof_sel, prof_sel, int, 0444);
73 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
74
75 enum {
76 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
77 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
78 };
79
80 static struct mlx5_profile profile[] = {
81 [0] = {
82 .mask = 0,
83 },
84 [1] = {
85 .mask = MLX5_PROF_MASK_QP_SIZE,
86 .log_max_qp = 12,
87 },
88 [2] = {
89 .mask = MLX5_PROF_MASK_QP_SIZE |
90 MLX5_PROF_MASK_MR_CACHE,
91 .log_max_qp = 17,
92 .mr_cache[0] = {
93 .size = 500,
94 .limit = 250
95 },
96 .mr_cache[1] = {
97 .size = 500,
98 .limit = 250
99 },
100 .mr_cache[2] = {
101 .size = 500,
102 .limit = 250
103 },
104 .mr_cache[3] = {
105 .size = 500,
106 .limit = 250
107 },
108 .mr_cache[4] = {
109 .size = 500,
110 .limit = 250
111 },
112 .mr_cache[5] = {
113 .size = 500,
114 .limit = 250
115 },
116 .mr_cache[6] = {
117 .size = 500,
118 .limit = 250
119 },
120 .mr_cache[7] = {
121 .size = 500,
122 .limit = 250
123 },
124 .mr_cache[8] = {
125 .size = 500,
126 .limit = 250
127 },
128 .mr_cache[9] = {
129 .size = 500,
130 .limit = 250
131 },
132 .mr_cache[10] = {
133 .size = 500,
134 .limit = 250
135 },
136 .mr_cache[11] = {
137 .size = 500,
138 .limit = 250
139 },
140 .mr_cache[12] = {
141 .size = 64,
142 .limit = 32
143 },
144 .mr_cache[13] = {
145 .size = 32,
146 .limit = 16
147 },
148 .mr_cache[14] = {
149 .size = 16,
150 .limit = 8
151 },
152 .mr_cache[15] = {
153 .size = 8,
154 .limit = 4
155 },
156 },
157 };
158
159 #define FW_INIT_TIMEOUT_MILI 2000
160 #define FW_INIT_WAIT_MS 2
161
162 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
163 {
164 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
165 int err = 0;
166
167 while (fw_initializing(dev)) {
168 if (time_after(jiffies, end)) {
169 err = -EBUSY;
170 break;
171 }
172 msleep(FW_INIT_WAIT_MS);
173 }
174
175 return err;
176 }
177
178 static int set_dma_caps(struct pci_dev *pdev)
179 {
180 int err;
181
182 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
183 if (err) {
184 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
185 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
186 if (err) {
187 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
188 return err;
189 }
190 }
191
192 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
193 if (err) {
194 dev_warn(&pdev->dev,
195 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
196 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
197 if (err) {
198 dev_err(&pdev->dev,
199 "Can't set consistent PCI DMA mask, aborting\n");
200 return err;
201 }
202 }
203
204 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
205 return err;
206 }
207
208 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
209 {
210 struct pci_dev *pdev = dev->pdev;
211 int err = 0;
212
213 mutex_lock(&dev->pci_status_mutex);
214 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
215 err = pci_enable_device(pdev);
216 if (!err)
217 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
218 }
219 mutex_unlock(&dev->pci_status_mutex);
220
221 return err;
222 }
223
224 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
225 {
226 struct pci_dev *pdev = dev->pdev;
227
228 mutex_lock(&dev->pci_status_mutex);
229 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
230 pci_disable_device(pdev);
231 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
232 }
233 mutex_unlock(&dev->pci_status_mutex);
234 }
235
236 static int request_bar(struct pci_dev *pdev)
237 {
238 int err = 0;
239
240 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
241 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
242 return -ENODEV;
243 }
244
245 err = pci_request_regions(pdev, DRIVER_NAME);
246 if (err)
247 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
248
249 return err;
250 }
251
252 static void release_bar(struct pci_dev *pdev)
253 {
254 pci_release_regions(pdev);
255 }
256
257 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
258 {
259 struct mlx5_priv *priv = &dev->priv;
260 struct mlx5_eq_table *table = &priv->eq_table;
261 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
262 int nvec;
263 int i;
264
265 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
266 MLX5_EQ_VEC_COMP_BASE;
267 nvec = min_t(int, nvec, num_eqs);
268 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
269 return -ENOMEM;
270
271 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
272
273 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
274 if (!priv->msix_arr || !priv->irq_info)
275 goto err_free_msix;
276
277 for (i = 0; i < nvec; i++)
278 priv->msix_arr[i].entry = i;
279
280 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
281 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
282 if (nvec < 0)
283 return nvec;
284
285 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
286
287 return 0;
288
289 err_free_msix:
290 kfree(priv->irq_info);
291 kfree(priv->msix_arr);
292 return -ENOMEM;
293 }
294
295 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
296 {
297 struct mlx5_priv *priv = &dev->priv;
298
299 pci_disable_msix(dev->pdev);
300 kfree(priv->irq_info);
301 kfree(priv->msix_arr);
302 }
303
304 struct mlx5_reg_host_endianess {
305 u8 he;
306 u8 rsvd[15];
307 };
308
309
310 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
311
312 enum {
313 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
314 MLX5_DEV_CAP_FLAG_DCT,
315 };
316
317 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
318 {
319 switch (size) {
320 case 128:
321 return 0;
322 case 256:
323 return 1;
324 case 512:
325 return 2;
326 case 1024:
327 return 3;
328 case 2048:
329 return 4;
330 case 4096:
331 return 5;
332 default:
333 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
334 return 0;
335 }
336 }
337
338 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
339 enum mlx5_cap_type cap_type,
340 enum mlx5_cap_mode cap_mode)
341 {
342 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
343 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
344 void *out, *hca_caps;
345 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
346 int err;
347
348 memset(in, 0, sizeof(in));
349 out = kzalloc(out_sz, GFP_KERNEL);
350 if (!out)
351 return -ENOMEM;
352
353 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
354 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
355 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
356 if (err) {
357 mlx5_core_warn(dev,
358 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
359 cap_type, cap_mode, err);
360 goto query_ex;
361 }
362
363 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
364
365 switch (cap_mode) {
366 case HCA_CAP_OPMOD_GET_MAX:
367 memcpy(dev->hca_caps_max[cap_type], hca_caps,
368 MLX5_UN_SZ_BYTES(hca_cap_union));
369 break;
370 case HCA_CAP_OPMOD_GET_CUR:
371 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
372 MLX5_UN_SZ_BYTES(hca_cap_union));
373 break;
374 default:
375 mlx5_core_warn(dev,
376 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
377 cap_type, cap_mode);
378 err = -EINVAL;
379 break;
380 }
381 query_ex:
382 kfree(out);
383 return err;
384 }
385
386 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
387 {
388 int ret;
389
390 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
391 if (ret)
392 return ret;
393 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
394 }
395
396 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
397 {
398 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
399
400 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
401 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
402 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
403 }
404
405 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
406 {
407 void *set_ctx;
408 void *set_hca_cap;
409 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
410 int req_endianness;
411 int err;
412
413 if (MLX5_CAP_GEN(dev, atomic)) {
414 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
415 if (err)
416 return err;
417 } else {
418 return 0;
419 }
420
421 req_endianness =
422 MLX5_CAP_ATOMIC(dev,
423 supported_atomic_req_8B_endianess_mode_1);
424
425 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
426 return 0;
427
428 set_ctx = kzalloc(set_sz, GFP_KERNEL);
429 if (!set_ctx)
430 return -ENOMEM;
431
432 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
433
434 /* Set requestor to host endianness */
435 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
436 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
437
438 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
439
440 kfree(set_ctx);
441 return err;
442 }
443
444 static int handle_hca_cap(struct mlx5_core_dev *dev)
445 {
446 void *set_ctx = NULL;
447 struct mlx5_profile *prof = dev->profile;
448 int err = -ENOMEM;
449 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
450 void *set_hca_cap;
451
452 set_ctx = kzalloc(set_sz, GFP_KERNEL);
453 if (!set_ctx)
454 goto query_ex;
455
456 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
457 if (err)
458 goto query_ex;
459
460 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
461 capability);
462 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
463 MLX5_ST_SZ_BYTES(cmd_hca_cap));
464
465 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
466 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
467 128);
468 /* we limit the size of the pkey table to 128 entries for now */
469 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
470 to_fw_pkey_sz(dev, 128));
471
472 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
473 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
474 prof->log_max_qp);
475
476 /* disable cmdif checksum */
477 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
478
479 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
480
481 err = set_caps(dev, set_ctx, set_sz,
482 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
483
484 query_ex:
485 kfree(set_ctx);
486 return err;
487 }
488
489 static int set_hca_ctrl(struct mlx5_core_dev *dev)
490 {
491 struct mlx5_reg_host_endianess he_in;
492 struct mlx5_reg_host_endianess he_out;
493 int err;
494
495 if (!mlx5_core_is_pf(dev))
496 return 0;
497
498 memset(&he_in, 0, sizeof(he_in));
499 he_in.he = MLX5_SET_HOST_ENDIANNESS;
500 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
501 &he_out, sizeof(he_out),
502 MLX5_REG_HOST_ENDIANNESS, 0, 1);
503 return err;
504 }
505
506 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
507 {
508 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
509 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
510
511 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
512 MLX5_SET(enable_hca_in, in, function_id, func_id);
513 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
514 }
515
516 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
517 {
518 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
519 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
520
521 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
522 MLX5_SET(disable_hca_in, in, function_id, func_id);
523 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
524 }
525
526 cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev)
527 {
528 u32 timer_h, timer_h1, timer_l;
529
530 timer_h = ioread32be(&dev->iseg->internal_timer_h);
531 timer_l = ioread32be(&dev->iseg->internal_timer_l);
532 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
533 if (timer_h != timer_h1) /* wrap around */
534 timer_l = ioread32be(&dev->iseg->internal_timer_l);
535
536 return (cycle_t)timer_l | (cycle_t)timer_h1 << 32;
537 }
538
539 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
540 {
541 struct mlx5_priv *priv = &mdev->priv;
542 struct msix_entry *msix = priv->msix_arr;
543 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
544 int numa_node = priv->numa_node;
545 int err;
546
547 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
548 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
549 return -ENOMEM;
550 }
551
552 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
553 priv->irq_info[i].mask);
554
555 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
556 if (err) {
557 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
558 irq);
559 goto err_clear_mask;
560 }
561
562 return 0;
563
564 err_clear_mask:
565 free_cpumask_var(priv->irq_info[i].mask);
566 return err;
567 }
568
569 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
570 {
571 struct mlx5_priv *priv = &mdev->priv;
572 struct msix_entry *msix = priv->msix_arr;
573 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
574
575 irq_set_affinity_hint(irq, NULL);
576 free_cpumask_var(priv->irq_info[i].mask);
577 }
578
579 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
580 {
581 int err;
582 int i;
583
584 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
585 err = mlx5_irq_set_affinity_hint(mdev, i);
586 if (err)
587 goto err_out;
588 }
589
590 return 0;
591
592 err_out:
593 for (i--; i >= 0; i--)
594 mlx5_irq_clear_affinity_hint(mdev, i);
595
596 return err;
597 }
598
599 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
600 {
601 int i;
602
603 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
604 mlx5_irq_clear_affinity_hint(mdev, i);
605 }
606
607 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
608 unsigned int *irqn)
609 {
610 struct mlx5_eq_table *table = &dev->priv.eq_table;
611 struct mlx5_eq *eq, *n;
612 int err = -ENOENT;
613
614 spin_lock(&table->lock);
615 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
616 if (eq->index == vector) {
617 *eqn = eq->eqn;
618 *irqn = eq->irqn;
619 err = 0;
620 break;
621 }
622 }
623 spin_unlock(&table->lock);
624
625 return err;
626 }
627 EXPORT_SYMBOL(mlx5_vector2eqn);
628
629 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
630 {
631 struct mlx5_eq_table *table = &dev->priv.eq_table;
632 struct mlx5_eq *eq;
633
634 spin_lock(&table->lock);
635 list_for_each_entry(eq, &table->comp_eqs_list, list)
636 if (eq->eqn == eqn) {
637 spin_unlock(&table->lock);
638 return eq;
639 }
640
641 spin_unlock(&table->lock);
642
643 return ERR_PTR(-ENOENT);
644 }
645
646 static void free_comp_eqs(struct mlx5_core_dev *dev)
647 {
648 struct mlx5_eq_table *table = &dev->priv.eq_table;
649 struct mlx5_eq *eq, *n;
650
651 #ifdef CONFIG_RFS_ACCEL
652 if (dev->rmap) {
653 free_irq_cpu_rmap(dev->rmap);
654 dev->rmap = NULL;
655 }
656 #endif
657 spin_lock(&table->lock);
658 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
659 list_del(&eq->list);
660 spin_unlock(&table->lock);
661 if (mlx5_destroy_unmap_eq(dev, eq))
662 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
663 eq->eqn);
664 kfree(eq);
665 spin_lock(&table->lock);
666 }
667 spin_unlock(&table->lock);
668 }
669
670 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
671 {
672 struct mlx5_eq_table *table = &dev->priv.eq_table;
673 char name[MLX5_MAX_IRQ_NAME];
674 struct mlx5_eq *eq;
675 int ncomp_vec;
676 int nent;
677 int err;
678 int i;
679
680 INIT_LIST_HEAD(&table->comp_eqs_list);
681 ncomp_vec = table->num_comp_vectors;
682 nent = MLX5_COMP_EQ_SIZE;
683 #ifdef CONFIG_RFS_ACCEL
684 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
685 if (!dev->rmap)
686 return -ENOMEM;
687 #endif
688 for (i = 0; i < ncomp_vec; i++) {
689 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
690 if (!eq) {
691 err = -ENOMEM;
692 goto clean;
693 }
694
695 #ifdef CONFIG_RFS_ACCEL
696 irq_cpu_rmap_add(dev->rmap,
697 dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector);
698 #endif
699 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
700 err = mlx5_create_map_eq(dev, eq,
701 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
702 name, &dev->priv.uuari.uars[0]);
703 if (err) {
704 kfree(eq);
705 goto clean;
706 }
707 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
708 eq->index = i;
709 spin_lock(&table->lock);
710 list_add_tail(&eq->list, &table->comp_eqs_list);
711 spin_unlock(&table->lock);
712 }
713
714 return 0;
715
716 clean:
717 free_comp_eqs(dev);
718 return err;
719 }
720
721 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
722 {
723 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
724 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
725 u32 sup_issi;
726 int err;
727
728 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
729 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
730 query_out, sizeof(query_out));
731 if (err) {
732 u32 syndrome;
733 u8 status;
734
735 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
736 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
737 pr_debug("Only ISSI 0 is supported\n");
738 return 0;
739 }
740
741 pr_err("failed to query ISSI err(%d)\n", err);
742 return err;
743 }
744
745 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
746
747 if (sup_issi & (1 << 1)) {
748 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
749 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
750
751 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
752 MLX5_SET(set_issi_in, set_in, current_issi, 1);
753 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
754 set_out, sizeof(set_out));
755 if (err) {
756 pr_err("failed to set ISSI=1 err(%d)\n", err);
757 return err;
758 }
759
760 dev->issi = 1;
761
762 return 0;
763 } else if (sup_issi & (1 << 0) || !sup_issi) {
764 return 0;
765 }
766
767 return -ENOTSUPP;
768 }
769
770
771 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
772 {
773 struct pci_dev *pdev = dev->pdev;
774 int err = 0;
775
776 pci_set_drvdata(dev->pdev, dev);
777 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
778 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
779
780 mutex_init(&priv->pgdir_mutex);
781 INIT_LIST_HEAD(&priv->pgdir_list);
782 spin_lock_init(&priv->mkey_lock);
783
784 mutex_init(&priv->alloc_mutex);
785
786 priv->numa_node = dev_to_node(&dev->pdev->dev);
787
788 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
789 if (!priv->dbg_root)
790 return -ENOMEM;
791
792 err = mlx5_pci_enable_device(dev);
793 if (err) {
794 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
795 goto err_dbg;
796 }
797
798 err = request_bar(pdev);
799 if (err) {
800 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
801 goto err_disable;
802 }
803
804 pci_set_master(pdev);
805
806 err = set_dma_caps(pdev);
807 if (err) {
808 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
809 goto err_clr_master;
810 }
811
812 dev->iseg_base = pci_resource_start(dev->pdev, 0);
813 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
814 if (!dev->iseg) {
815 err = -ENOMEM;
816 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
817 goto err_clr_master;
818 }
819
820 return 0;
821
822 err_clr_master:
823 pci_clear_master(dev->pdev);
824 release_bar(dev->pdev);
825 err_disable:
826 mlx5_pci_disable_device(dev);
827
828 err_dbg:
829 debugfs_remove(priv->dbg_root);
830 return err;
831 }
832
833 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
834 {
835 iounmap(dev->iseg);
836 pci_clear_master(dev->pdev);
837 release_bar(dev->pdev);
838 mlx5_pci_disable_device(dev);
839 debugfs_remove(priv->dbg_root);
840 }
841
842 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
843 {
844 struct pci_dev *pdev = dev->pdev;
845 int err;
846
847 err = mlx5_query_hca_caps(dev);
848 if (err) {
849 dev_err(&pdev->dev, "query hca failed\n");
850 goto out;
851 }
852
853 err = mlx5_query_board_id(dev);
854 if (err) {
855 dev_err(&pdev->dev, "query board id failed\n");
856 goto out;
857 }
858
859 err = mlx5_eq_init(dev);
860 if (err) {
861 dev_err(&pdev->dev, "failed to initialize eq\n");
862 goto out;
863 }
864
865 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
866
867 err = mlx5_init_cq_table(dev);
868 if (err) {
869 dev_err(&pdev->dev, "failed to initialize cq table\n");
870 goto err_eq_cleanup;
871 }
872
873 mlx5_init_qp_table(dev);
874
875 mlx5_init_srq_table(dev);
876
877 mlx5_init_mkey_table(dev);
878
879 err = mlx5_init_rl_table(dev);
880 if (err) {
881 dev_err(&pdev->dev, "Failed to init rate limiting\n");
882 goto err_tables_cleanup;
883 }
884
885 #ifdef CONFIG_MLX5_CORE_EN
886 err = mlx5_eswitch_init(dev);
887 if (err) {
888 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
889 goto err_rl_cleanup;
890 }
891 #endif
892
893 err = mlx5_sriov_init(dev);
894 if (err) {
895 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
896 goto err_eswitch_cleanup;
897 }
898
899 return 0;
900
901 err_eswitch_cleanup:
902 #ifdef CONFIG_MLX5_CORE_EN
903 mlx5_eswitch_cleanup(dev->priv.eswitch);
904
905 err_rl_cleanup:
906 #endif
907 mlx5_cleanup_rl_table(dev);
908
909 err_tables_cleanup:
910 mlx5_cleanup_mkey_table(dev);
911 mlx5_cleanup_srq_table(dev);
912 mlx5_cleanup_qp_table(dev);
913 mlx5_cleanup_cq_table(dev);
914
915 err_eq_cleanup:
916 mlx5_eq_cleanup(dev);
917
918 out:
919 return err;
920 }
921
922 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
923 {
924 mlx5_sriov_cleanup(dev);
925 #ifdef CONFIG_MLX5_CORE_EN
926 mlx5_eswitch_cleanup(dev->priv.eswitch);
927 #endif
928 mlx5_cleanup_rl_table(dev);
929 mlx5_cleanup_mkey_table(dev);
930 mlx5_cleanup_srq_table(dev);
931 mlx5_cleanup_qp_table(dev);
932 mlx5_cleanup_cq_table(dev);
933 mlx5_eq_cleanup(dev);
934 }
935
936 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
937 bool boot)
938 {
939 struct pci_dev *pdev = dev->pdev;
940 int err;
941
942 mutex_lock(&dev->intf_state_mutex);
943 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
944 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
945 __func__);
946 goto out;
947 }
948
949 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
950 fw_rev_min(dev), fw_rev_sub(dev));
951
952 /* on load removing any previous indication of internal error, device is
953 * up
954 */
955 dev->state = MLX5_DEVICE_STATE_UP;
956
957 err = mlx5_cmd_init(dev);
958 if (err) {
959 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
960 goto out_err;
961 }
962
963 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
964 if (err) {
965 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
966 FW_INIT_TIMEOUT_MILI);
967 goto out_err;
968 }
969
970 err = mlx5_core_enable_hca(dev, 0);
971 if (err) {
972 dev_err(&pdev->dev, "enable hca failed\n");
973 goto err_cmd_cleanup;
974 }
975
976 err = mlx5_core_set_issi(dev);
977 if (err) {
978 dev_err(&pdev->dev, "failed to set issi\n");
979 goto err_disable_hca;
980 }
981
982 err = mlx5_satisfy_startup_pages(dev, 1);
983 if (err) {
984 dev_err(&pdev->dev, "failed to allocate boot pages\n");
985 goto err_disable_hca;
986 }
987
988 err = set_hca_ctrl(dev);
989 if (err) {
990 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
991 goto reclaim_boot_pages;
992 }
993
994 err = handle_hca_cap(dev);
995 if (err) {
996 dev_err(&pdev->dev, "handle_hca_cap failed\n");
997 goto reclaim_boot_pages;
998 }
999
1000 err = handle_hca_cap_atomic(dev);
1001 if (err) {
1002 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1003 goto reclaim_boot_pages;
1004 }
1005
1006 err = mlx5_satisfy_startup_pages(dev, 0);
1007 if (err) {
1008 dev_err(&pdev->dev, "failed to allocate init pages\n");
1009 goto reclaim_boot_pages;
1010 }
1011
1012 err = mlx5_pagealloc_start(dev);
1013 if (err) {
1014 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1015 goto reclaim_boot_pages;
1016 }
1017
1018 err = mlx5_cmd_init_hca(dev);
1019 if (err) {
1020 dev_err(&pdev->dev, "init hca failed\n");
1021 goto err_pagealloc_stop;
1022 }
1023
1024 mlx5_start_health_poll(dev);
1025
1026 if (boot && mlx5_init_once(dev, priv)) {
1027 dev_err(&pdev->dev, "sw objs init failed\n");
1028 goto err_stop_poll;
1029 }
1030
1031 err = mlx5_enable_msix(dev);
1032 if (err) {
1033 dev_err(&pdev->dev, "enable msix failed\n");
1034 goto err_cleanup_once;
1035 }
1036
1037 err = mlx5_alloc_uuars(dev, &priv->uuari);
1038 if (err) {
1039 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1040 goto err_disable_msix;
1041 }
1042
1043 err = mlx5_start_eqs(dev);
1044 if (err) {
1045 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1046 goto err_free_uar;
1047 }
1048
1049 err = alloc_comp_eqs(dev);
1050 if (err) {
1051 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1052 goto err_stop_eqs;
1053 }
1054
1055 err = mlx5_irq_set_affinity_hints(dev);
1056 if (err) {
1057 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1058 goto err_affinity_hints;
1059 }
1060
1061 err = mlx5_init_fs(dev);
1062 if (err) {
1063 dev_err(&pdev->dev, "Failed to init flow steering\n");
1064 goto err_fs;
1065 }
1066
1067 #ifdef CONFIG_MLX5_CORE_EN
1068 mlx5_eswitch_attach(dev->priv.eswitch);
1069 #endif
1070
1071 err = mlx5_sriov_attach(dev);
1072 if (err) {
1073 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1074 goto err_sriov;
1075 }
1076
1077 if (mlx5_device_registered(dev)) {
1078 mlx5_attach_device(dev);
1079 } else {
1080 err = mlx5_register_device(dev);
1081 if (err) {
1082 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1083 goto err_reg_dev;
1084 }
1085 }
1086
1087 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1088 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1089 out:
1090 mutex_unlock(&dev->intf_state_mutex);
1091
1092 return 0;
1093
1094 err_reg_dev:
1095 mlx5_sriov_detach(dev);
1096
1097 err_sriov:
1098 #ifdef CONFIG_MLX5_CORE_EN
1099 mlx5_eswitch_detach(dev->priv.eswitch);
1100 #endif
1101 mlx5_cleanup_fs(dev);
1102
1103 err_fs:
1104 mlx5_irq_clear_affinity_hints(dev);
1105
1106 err_affinity_hints:
1107 free_comp_eqs(dev);
1108
1109 err_stop_eqs:
1110 mlx5_stop_eqs(dev);
1111
1112 err_free_uar:
1113 mlx5_free_uuars(dev, &priv->uuari);
1114
1115 err_disable_msix:
1116 mlx5_disable_msix(dev);
1117
1118 err_cleanup_once:
1119 if (boot)
1120 mlx5_cleanup_once(dev);
1121
1122 err_stop_poll:
1123 mlx5_stop_health_poll(dev);
1124 if (mlx5_cmd_teardown_hca(dev)) {
1125 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1126 goto out_err;
1127 }
1128
1129 err_pagealloc_stop:
1130 mlx5_pagealloc_stop(dev);
1131
1132 reclaim_boot_pages:
1133 mlx5_reclaim_startup_pages(dev);
1134
1135 err_disable_hca:
1136 mlx5_core_disable_hca(dev, 0);
1137
1138 err_cmd_cleanup:
1139 mlx5_cmd_cleanup(dev);
1140
1141 out_err:
1142 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1143 mutex_unlock(&dev->intf_state_mutex);
1144
1145 return err;
1146 }
1147
1148 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1149 bool cleanup)
1150 {
1151 int err = 0;
1152
1153 mutex_lock(&dev->intf_state_mutex);
1154 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
1155 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1156 __func__);
1157 if (cleanup)
1158 mlx5_cleanup_once(dev);
1159 goto out;
1160 }
1161
1162 if (mlx5_device_registered(dev))
1163 mlx5_detach_device(dev);
1164
1165 mlx5_sriov_detach(dev);
1166 #ifdef CONFIG_MLX5_CORE_EN
1167 mlx5_eswitch_detach(dev->priv.eswitch);
1168 #endif
1169 mlx5_cleanup_fs(dev);
1170 mlx5_irq_clear_affinity_hints(dev);
1171 free_comp_eqs(dev);
1172 mlx5_stop_eqs(dev);
1173 mlx5_free_uuars(dev, &priv->uuari);
1174 mlx5_disable_msix(dev);
1175 if (cleanup)
1176 mlx5_cleanup_once(dev);
1177 mlx5_stop_health_poll(dev);
1178 err = mlx5_cmd_teardown_hca(dev);
1179 if (err) {
1180 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1181 goto out;
1182 }
1183 mlx5_pagealloc_stop(dev);
1184 mlx5_reclaim_startup_pages(dev);
1185 mlx5_core_disable_hca(dev, 0);
1186 mlx5_cmd_cleanup(dev);
1187
1188 out:
1189 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1190 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1191 mutex_unlock(&dev->intf_state_mutex);
1192 return err;
1193 }
1194
1195 struct mlx5_core_event_handler {
1196 void (*event)(struct mlx5_core_dev *dev,
1197 enum mlx5_dev_event event,
1198 void *data);
1199 };
1200
1201 static const struct devlink_ops mlx5_devlink_ops = {
1202 #ifdef CONFIG_MLX5_CORE_EN
1203 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1204 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1205 #endif
1206 };
1207
1208 #define MLX5_IB_MOD "mlx5_ib"
1209 static int init_one(struct pci_dev *pdev,
1210 const struct pci_device_id *id)
1211 {
1212 struct mlx5_core_dev *dev;
1213 struct devlink *devlink;
1214 struct mlx5_priv *priv;
1215 int err;
1216
1217 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1218 if (!devlink) {
1219 dev_err(&pdev->dev, "kzalloc failed\n");
1220 return -ENOMEM;
1221 }
1222
1223 dev = devlink_priv(devlink);
1224 priv = &dev->priv;
1225 priv->pci_dev_data = id->driver_data;
1226
1227 pci_set_drvdata(pdev, dev);
1228
1229 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1230 mlx5_core_warn(dev,
1231 "selected profile out of range, selecting default (%d)\n",
1232 MLX5_DEFAULT_PROF);
1233 prof_sel = MLX5_DEFAULT_PROF;
1234 }
1235 dev->profile = &profile[prof_sel];
1236 dev->pdev = pdev;
1237 dev->event = mlx5_core_event;
1238
1239 INIT_LIST_HEAD(&priv->ctx_list);
1240 spin_lock_init(&priv->ctx_lock);
1241 mutex_init(&dev->pci_status_mutex);
1242 mutex_init(&dev->intf_state_mutex);
1243 err = mlx5_pci_init(dev, priv);
1244 if (err) {
1245 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1246 goto clean_dev;
1247 }
1248
1249 err = mlx5_health_init(dev);
1250 if (err) {
1251 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1252 goto close_pci;
1253 }
1254
1255 mlx5_pagealloc_init(dev);
1256
1257 err = mlx5_load_one(dev, priv, true);
1258 if (err) {
1259 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1260 goto clean_health;
1261 }
1262
1263 err = request_module_nowait(MLX5_IB_MOD);
1264 if (err)
1265 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1266
1267 err = devlink_register(devlink, &pdev->dev);
1268 if (err)
1269 goto clean_load;
1270
1271 return 0;
1272
1273 clean_load:
1274 mlx5_unload_one(dev, priv, true);
1275 clean_health:
1276 mlx5_pagealloc_cleanup(dev);
1277 mlx5_health_cleanup(dev);
1278 close_pci:
1279 mlx5_pci_close(dev, priv);
1280 clean_dev:
1281 pci_set_drvdata(pdev, NULL);
1282 devlink_free(devlink);
1283
1284 return err;
1285 }
1286
1287 static void remove_one(struct pci_dev *pdev)
1288 {
1289 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1290 struct devlink *devlink = priv_to_devlink(dev);
1291 struct mlx5_priv *priv = &dev->priv;
1292
1293 devlink_unregister(devlink);
1294 mlx5_unregister_device(dev);
1295
1296 if (mlx5_unload_one(dev, priv, true)) {
1297 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1298 mlx5_health_cleanup(dev);
1299 return;
1300 }
1301
1302 mlx5_pagealloc_cleanup(dev);
1303 mlx5_health_cleanup(dev);
1304 mlx5_pci_close(dev, priv);
1305 pci_set_drvdata(pdev, NULL);
1306 devlink_free(devlink);
1307 }
1308
1309 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1310 pci_channel_state_t state)
1311 {
1312 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1313 struct mlx5_priv *priv = &dev->priv;
1314
1315 dev_info(&pdev->dev, "%s was called\n", __func__);
1316 mlx5_enter_error_state(dev);
1317 mlx5_unload_one(dev, priv, false);
1318 pci_save_state(pdev);
1319 mlx5_pci_disable_device(dev);
1320 return state == pci_channel_io_perm_failure ?
1321 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1322 }
1323
1324 /* wait for the device to show vital signs by waiting
1325 * for the health counter to start counting.
1326 */
1327 static int wait_vital(struct pci_dev *pdev)
1328 {
1329 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1330 struct mlx5_core_health *health = &dev->priv.health;
1331 const int niter = 100;
1332 u32 last_count = 0;
1333 u32 count;
1334 int i;
1335
1336 for (i = 0; i < niter; i++) {
1337 count = ioread32be(health->health_counter);
1338 if (count && count != 0xffffffff) {
1339 if (last_count && last_count != count) {
1340 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1341 return 0;
1342 }
1343 last_count = count;
1344 }
1345 msleep(50);
1346 }
1347
1348 return -ETIMEDOUT;
1349 }
1350
1351 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1352 {
1353 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1354 int err;
1355
1356 dev_info(&pdev->dev, "%s was called\n", __func__);
1357
1358 err = mlx5_pci_enable_device(dev);
1359 if (err) {
1360 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1361 , __func__, err);
1362 return PCI_ERS_RESULT_DISCONNECT;
1363 }
1364
1365 pci_set_master(pdev);
1366 pci_restore_state(pdev);
1367
1368 if (wait_vital(pdev)) {
1369 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1370 return PCI_ERS_RESULT_DISCONNECT;
1371 }
1372
1373 return PCI_ERS_RESULT_RECOVERED;
1374 }
1375
1376 void mlx5_disable_device(struct mlx5_core_dev *dev)
1377 {
1378 mlx5_pci_err_detected(dev->pdev, 0);
1379 }
1380
1381 static void mlx5_pci_resume(struct pci_dev *pdev)
1382 {
1383 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1384 struct mlx5_priv *priv = &dev->priv;
1385 int err;
1386
1387 dev_info(&pdev->dev, "%s was called\n", __func__);
1388
1389 err = mlx5_load_one(dev, priv, false);
1390 if (err)
1391 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1392 , __func__, err);
1393 else
1394 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1395 }
1396
1397 static const struct pci_error_handlers mlx5_err_handler = {
1398 .error_detected = mlx5_pci_err_detected,
1399 .slot_reset = mlx5_pci_slot_reset,
1400 .resume = mlx5_pci_resume
1401 };
1402
1403 static void shutdown(struct pci_dev *pdev)
1404 {
1405 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1406 struct mlx5_priv *priv = &dev->priv;
1407
1408 dev_info(&pdev->dev, "Shutdown was called\n");
1409 /* Notify mlx5 clients that the kernel is being shut down */
1410 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
1411 mlx5_unload_one(dev, priv, false);
1412 mlx5_pci_disable_device(dev);
1413 }
1414
1415 static const struct pci_device_id mlx5_core_pci_table[] = {
1416 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1417 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1418 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1419 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1420 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1421 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1422 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1423 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1424 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5, PCIe 4.0 */
1425 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5, PCIe 4.0 VF */
1426 { 0, }
1427 };
1428
1429 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1430
1431 static struct pci_driver mlx5_core_driver = {
1432 .name = DRIVER_NAME,
1433 .id_table = mlx5_core_pci_table,
1434 .probe = init_one,
1435 .remove = remove_one,
1436 .shutdown = shutdown,
1437 .err_handler = &mlx5_err_handler,
1438 .sriov_configure = mlx5_core_sriov_configure,
1439 };
1440
1441 static int __init init(void)
1442 {
1443 int err;
1444
1445 mlx5_register_debugfs();
1446
1447 err = pci_register_driver(&mlx5_core_driver);
1448 if (err)
1449 goto err_debug;
1450
1451 #ifdef CONFIG_MLX5_CORE_EN
1452 mlx5e_init();
1453 #endif
1454
1455 return 0;
1456
1457 err_debug:
1458 mlx5_unregister_debugfs();
1459 return err;
1460 }
1461
1462 static void __exit cleanup(void)
1463 {
1464 #ifdef CONFIG_MLX5_CORE_EN
1465 mlx5e_cleanup();
1466 #endif
1467 pci_unregister_driver(&mlx5_core_driver);
1468 mlx5_unregister_debugfs();
1469 }
1470
1471 module_init(init);
1472 module_exit(cleanup);
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