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Merge tag 'iio-for-4.13b' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23...
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/mlx5/mlx5_ifc.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
52 #endif
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
55 #include "fs_core.h"
56 #ifdef CONFIG_MLX5_CORE_EN
57 #include "eswitch.h"
58 #endif
59
60 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
61 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
62 MODULE_LICENSE("Dual BSD/GPL");
63 MODULE_VERSION(DRIVER_VERSION);
64
65 unsigned int mlx5_core_debug_mask;
66 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
67 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
68
69 #define MLX5_DEFAULT_PROF 2
70 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
71 module_param_named(prof_sel, prof_sel, uint, 0444);
72 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
73
74 enum {
75 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
76 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
77 };
78
79 static struct mlx5_profile profile[] = {
80 [0] = {
81 .mask = 0,
82 },
83 [1] = {
84 .mask = MLX5_PROF_MASK_QP_SIZE,
85 .log_max_qp = 12,
86 },
87 [2] = {
88 .mask = MLX5_PROF_MASK_QP_SIZE |
89 MLX5_PROF_MASK_MR_CACHE,
90 .log_max_qp = 18,
91 .mr_cache[0] = {
92 .size = 500,
93 .limit = 250
94 },
95 .mr_cache[1] = {
96 .size = 500,
97 .limit = 250
98 },
99 .mr_cache[2] = {
100 .size = 500,
101 .limit = 250
102 },
103 .mr_cache[3] = {
104 .size = 500,
105 .limit = 250
106 },
107 .mr_cache[4] = {
108 .size = 500,
109 .limit = 250
110 },
111 .mr_cache[5] = {
112 .size = 500,
113 .limit = 250
114 },
115 .mr_cache[6] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[7] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[8] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[9] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[10] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[11] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[12] = {
140 .size = 64,
141 .limit = 32
142 },
143 .mr_cache[13] = {
144 .size = 32,
145 .limit = 16
146 },
147 .mr_cache[14] = {
148 .size = 16,
149 .limit = 8
150 },
151 .mr_cache[15] = {
152 .size = 8,
153 .limit = 4
154 },
155 .mr_cache[16] = {
156 .size = 8,
157 .limit = 4
158 },
159 .mr_cache[17] = {
160 .size = 8,
161 .limit = 4
162 },
163 .mr_cache[18] = {
164 .size = 8,
165 .limit = 4
166 },
167 .mr_cache[19] = {
168 .size = 4,
169 .limit = 2
170 },
171 .mr_cache[20] = {
172 .size = 4,
173 .limit = 2
174 },
175 },
176 };
177
178 #define FW_INIT_TIMEOUT_MILI 2000
179 #define FW_INIT_WAIT_MS 2
180
181 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
182 {
183 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
184 int err = 0;
185
186 while (fw_initializing(dev)) {
187 if (time_after(jiffies, end)) {
188 err = -EBUSY;
189 break;
190 }
191 msleep(FW_INIT_WAIT_MS);
192 }
193
194 return err;
195 }
196
197 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
198 {
199 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
200 driver_version);
201 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
202 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
203 int remaining_size = driver_ver_sz;
204 char *string;
205
206 if (!MLX5_CAP_GEN(dev, driver_version))
207 return;
208
209 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
210
211 strncpy(string, "Linux", remaining_size);
212
213 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
214 strncat(string, ",", remaining_size);
215
216 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
217 strncat(string, DRIVER_NAME, remaining_size);
218
219 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
220 strncat(string, ",", remaining_size);
221
222 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
223 strncat(string, DRIVER_VERSION, remaining_size);
224
225 /*Send the command*/
226 MLX5_SET(set_driver_version_in, in, opcode,
227 MLX5_CMD_OP_SET_DRIVER_VERSION);
228
229 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
230 }
231
232 static int set_dma_caps(struct pci_dev *pdev)
233 {
234 int err;
235
236 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
237 if (err) {
238 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
239 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
240 if (err) {
241 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
242 return err;
243 }
244 }
245
246 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
247 if (err) {
248 dev_warn(&pdev->dev,
249 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
250 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
251 if (err) {
252 dev_err(&pdev->dev,
253 "Can't set consistent PCI DMA mask, aborting\n");
254 return err;
255 }
256 }
257
258 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
259 return err;
260 }
261
262 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
263 {
264 struct pci_dev *pdev = dev->pdev;
265 int err = 0;
266
267 mutex_lock(&dev->pci_status_mutex);
268 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
269 err = pci_enable_device(pdev);
270 if (!err)
271 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
272 }
273 mutex_unlock(&dev->pci_status_mutex);
274
275 return err;
276 }
277
278 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
279 {
280 struct pci_dev *pdev = dev->pdev;
281
282 mutex_lock(&dev->pci_status_mutex);
283 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
284 pci_disable_device(pdev);
285 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
286 }
287 mutex_unlock(&dev->pci_status_mutex);
288 }
289
290 static int request_bar(struct pci_dev *pdev)
291 {
292 int err = 0;
293
294 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
295 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
296 return -ENODEV;
297 }
298
299 err = pci_request_regions(pdev, DRIVER_NAME);
300 if (err)
301 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
302
303 return err;
304 }
305
306 static void release_bar(struct pci_dev *pdev)
307 {
308 pci_release_regions(pdev);
309 }
310
311 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
312 {
313 struct mlx5_priv *priv = &dev->priv;
314 struct mlx5_eq_table *table = &priv->eq_table;
315 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
316 int nvec;
317 int i;
318
319 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
320 MLX5_EQ_VEC_COMP_BASE;
321 nvec = min_t(int, nvec, num_eqs);
322 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
323 return -ENOMEM;
324
325 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
326
327 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
328 if (!priv->msix_arr || !priv->irq_info)
329 goto err_free_msix;
330
331 for (i = 0; i < nvec; i++)
332 priv->msix_arr[i].entry = i;
333
334 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
335 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
336 if (nvec < 0)
337 return nvec;
338
339 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
340
341 return 0;
342
343 err_free_msix:
344 kfree(priv->irq_info);
345 kfree(priv->msix_arr);
346 return -ENOMEM;
347 }
348
349 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
350 {
351 struct mlx5_priv *priv = &dev->priv;
352
353 pci_disable_msix(dev->pdev);
354 kfree(priv->irq_info);
355 kfree(priv->msix_arr);
356 }
357
358 struct mlx5_reg_host_endianess {
359 u8 he;
360 u8 rsvd[15];
361 };
362
363
364 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
365
366 enum {
367 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
368 MLX5_DEV_CAP_FLAG_DCT,
369 };
370
371 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
372 {
373 switch (size) {
374 case 128:
375 return 0;
376 case 256:
377 return 1;
378 case 512:
379 return 2;
380 case 1024:
381 return 3;
382 case 2048:
383 return 4;
384 case 4096:
385 return 5;
386 default:
387 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
388 return 0;
389 }
390 }
391
392 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
393 enum mlx5_cap_type cap_type,
394 enum mlx5_cap_mode cap_mode)
395 {
396 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
397 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
398 void *out, *hca_caps;
399 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
400 int err;
401
402 memset(in, 0, sizeof(in));
403 out = kzalloc(out_sz, GFP_KERNEL);
404 if (!out)
405 return -ENOMEM;
406
407 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
408 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
409 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
410 if (err) {
411 mlx5_core_warn(dev,
412 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
413 cap_type, cap_mode, err);
414 goto query_ex;
415 }
416
417 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
418
419 switch (cap_mode) {
420 case HCA_CAP_OPMOD_GET_MAX:
421 memcpy(dev->caps.hca_max[cap_type], hca_caps,
422 MLX5_UN_SZ_BYTES(hca_cap_union));
423 break;
424 case HCA_CAP_OPMOD_GET_CUR:
425 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
426 MLX5_UN_SZ_BYTES(hca_cap_union));
427 break;
428 default:
429 mlx5_core_warn(dev,
430 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
431 cap_type, cap_mode);
432 err = -EINVAL;
433 break;
434 }
435 query_ex:
436 kfree(out);
437 return err;
438 }
439
440 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
441 {
442 int ret;
443
444 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
445 if (ret)
446 return ret;
447 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
448 }
449
450 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
451 {
452 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
453
454 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
455 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
456 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
457 }
458
459 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
460 {
461 void *set_ctx;
462 void *set_hca_cap;
463 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
464 int req_endianness;
465 int err;
466
467 if (MLX5_CAP_GEN(dev, atomic)) {
468 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
469 if (err)
470 return err;
471 } else {
472 return 0;
473 }
474
475 req_endianness =
476 MLX5_CAP_ATOMIC(dev,
477 supported_atomic_req_8B_endianess_mode_1);
478
479 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
480 return 0;
481
482 set_ctx = kzalloc(set_sz, GFP_KERNEL);
483 if (!set_ctx)
484 return -ENOMEM;
485
486 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
487
488 /* Set requestor to host endianness */
489 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
490 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
491
492 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
493
494 kfree(set_ctx);
495 return err;
496 }
497
498 static int handle_hca_cap(struct mlx5_core_dev *dev)
499 {
500 void *set_ctx = NULL;
501 struct mlx5_profile *prof = dev->profile;
502 int err = -ENOMEM;
503 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
504 void *set_hca_cap;
505
506 set_ctx = kzalloc(set_sz, GFP_KERNEL);
507 if (!set_ctx)
508 goto query_ex;
509
510 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
511 if (err)
512 goto query_ex;
513
514 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
515 capability);
516 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
517 MLX5_ST_SZ_BYTES(cmd_hca_cap));
518
519 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
520 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
521 128);
522 /* we limit the size of the pkey table to 128 entries for now */
523 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
524 to_fw_pkey_sz(dev, 128));
525
526 /* Check log_max_qp from HCA caps to set in current profile */
527 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
528 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
529 profile[prof_sel].log_max_qp,
530 MLX5_CAP_GEN_MAX(dev, log_max_qp));
531 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
532 }
533 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
534 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
535 prof->log_max_qp);
536
537 /* disable cmdif checksum */
538 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
539
540 /* Enable 4K UAR only when HCA supports it and page size is bigger
541 * than 4K.
542 */
543 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
544 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
545
546 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
547
548 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
549 MLX5_SET(cmd_hca_cap,
550 set_hca_cap,
551 cache_line_128byte,
552 cache_line_size() == 128 ? 1 : 0);
553
554 err = set_caps(dev, set_ctx, set_sz,
555 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
556
557 query_ex:
558 kfree(set_ctx);
559 return err;
560 }
561
562 static int set_hca_ctrl(struct mlx5_core_dev *dev)
563 {
564 struct mlx5_reg_host_endianess he_in;
565 struct mlx5_reg_host_endianess he_out;
566 int err;
567
568 if (!mlx5_core_is_pf(dev))
569 return 0;
570
571 memset(&he_in, 0, sizeof(he_in));
572 he_in.he = MLX5_SET_HOST_ENDIANNESS;
573 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
574 &he_out, sizeof(he_out),
575 MLX5_REG_HOST_ENDIANNESS, 0, 1);
576 return err;
577 }
578
579 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
580 {
581 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
582 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
583
584 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
585 MLX5_SET(enable_hca_in, in, function_id, func_id);
586 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
587 }
588
589 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
590 {
591 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
592 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
593
594 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
595 MLX5_SET(disable_hca_in, in, function_id, func_id);
596 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
597 }
598
599 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
600 {
601 u32 timer_h, timer_h1, timer_l;
602
603 timer_h = ioread32be(&dev->iseg->internal_timer_h);
604 timer_l = ioread32be(&dev->iseg->internal_timer_l);
605 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
606 if (timer_h != timer_h1) /* wrap around */
607 timer_l = ioread32be(&dev->iseg->internal_timer_l);
608
609 return (u64)timer_l | (u64)timer_h1 << 32;
610 }
611
612 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
613 {
614 struct mlx5_priv *priv = &mdev->priv;
615 struct msix_entry *msix = priv->msix_arr;
616 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
617
618 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
619 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
620 return -ENOMEM;
621 }
622
623 cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
624 priv->irq_info[i].mask);
625
626 if (IS_ENABLED(CONFIG_SMP) &&
627 irq_set_affinity_hint(irq, priv->irq_info[i].mask))
628 mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
629
630 return 0;
631 }
632
633 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
634 {
635 struct mlx5_priv *priv = &mdev->priv;
636 struct msix_entry *msix = priv->msix_arr;
637 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
638
639 irq_set_affinity_hint(irq, NULL);
640 free_cpumask_var(priv->irq_info[i].mask);
641 }
642
643 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
644 {
645 int err;
646 int i;
647
648 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
649 err = mlx5_irq_set_affinity_hint(mdev, i);
650 if (err)
651 goto err_out;
652 }
653
654 return 0;
655
656 err_out:
657 for (i--; i >= 0; i--)
658 mlx5_irq_clear_affinity_hint(mdev, i);
659
660 return err;
661 }
662
663 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
664 {
665 int i;
666
667 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
668 mlx5_irq_clear_affinity_hint(mdev, i);
669 }
670
671 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
672 unsigned int *irqn)
673 {
674 struct mlx5_eq_table *table = &dev->priv.eq_table;
675 struct mlx5_eq *eq, *n;
676 int err = -ENOENT;
677
678 spin_lock(&table->lock);
679 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
680 if (eq->index == vector) {
681 *eqn = eq->eqn;
682 *irqn = eq->irqn;
683 err = 0;
684 break;
685 }
686 }
687 spin_unlock(&table->lock);
688
689 return err;
690 }
691 EXPORT_SYMBOL(mlx5_vector2eqn);
692
693 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
694 {
695 struct mlx5_eq_table *table = &dev->priv.eq_table;
696 struct mlx5_eq *eq;
697
698 spin_lock(&table->lock);
699 list_for_each_entry(eq, &table->comp_eqs_list, list)
700 if (eq->eqn == eqn) {
701 spin_unlock(&table->lock);
702 return eq;
703 }
704
705 spin_unlock(&table->lock);
706
707 return ERR_PTR(-ENOENT);
708 }
709
710 static void free_comp_eqs(struct mlx5_core_dev *dev)
711 {
712 struct mlx5_eq_table *table = &dev->priv.eq_table;
713 struct mlx5_eq *eq, *n;
714
715 #ifdef CONFIG_RFS_ACCEL
716 if (dev->rmap) {
717 free_irq_cpu_rmap(dev->rmap);
718 dev->rmap = NULL;
719 }
720 #endif
721 spin_lock(&table->lock);
722 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
723 list_del(&eq->list);
724 spin_unlock(&table->lock);
725 if (mlx5_destroy_unmap_eq(dev, eq))
726 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
727 eq->eqn);
728 kfree(eq);
729 spin_lock(&table->lock);
730 }
731 spin_unlock(&table->lock);
732 }
733
734 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
735 {
736 struct mlx5_eq_table *table = &dev->priv.eq_table;
737 char name[MLX5_MAX_IRQ_NAME];
738 struct mlx5_eq *eq;
739 int ncomp_vec;
740 int nent;
741 int err;
742 int i;
743
744 INIT_LIST_HEAD(&table->comp_eqs_list);
745 ncomp_vec = table->num_comp_vectors;
746 nent = MLX5_COMP_EQ_SIZE;
747 #ifdef CONFIG_RFS_ACCEL
748 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
749 if (!dev->rmap)
750 return -ENOMEM;
751 #endif
752 for (i = 0; i < ncomp_vec; i++) {
753 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
754 if (!eq) {
755 err = -ENOMEM;
756 goto clean;
757 }
758
759 #ifdef CONFIG_RFS_ACCEL
760 irq_cpu_rmap_add(dev->rmap,
761 dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector);
762 #endif
763 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
764 err = mlx5_create_map_eq(dev, eq,
765 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
766 name, MLX5_EQ_TYPE_COMP);
767 if (err) {
768 kfree(eq);
769 goto clean;
770 }
771 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
772 eq->index = i;
773 spin_lock(&table->lock);
774 list_add_tail(&eq->list, &table->comp_eqs_list);
775 spin_unlock(&table->lock);
776 }
777
778 return 0;
779
780 clean:
781 free_comp_eqs(dev);
782 return err;
783 }
784
785 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
786 {
787 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
788 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
789 u32 sup_issi;
790 int err;
791
792 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
793 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
794 query_out, sizeof(query_out));
795 if (err) {
796 u32 syndrome;
797 u8 status;
798
799 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
800 if (!status || syndrome == MLX5_DRIVER_SYND) {
801 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
802 err, status, syndrome);
803 return err;
804 }
805
806 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
807 dev->issi = 0;
808 return 0;
809 }
810
811 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
812
813 if (sup_issi & (1 << 1)) {
814 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
815 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
816
817 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
818 MLX5_SET(set_issi_in, set_in, current_issi, 1);
819 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
820 set_out, sizeof(set_out));
821 if (err) {
822 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
823 err);
824 return err;
825 }
826
827 dev->issi = 1;
828
829 return 0;
830 } else if (sup_issi & (1 << 0) || !sup_issi) {
831 return 0;
832 }
833
834 return -EOPNOTSUPP;
835 }
836
837
838 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
839 {
840 struct pci_dev *pdev = dev->pdev;
841 int err = 0;
842
843 pci_set_drvdata(dev->pdev, dev);
844 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
845 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
846
847 mutex_init(&priv->pgdir_mutex);
848 INIT_LIST_HEAD(&priv->pgdir_list);
849 spin_lock_init(&priv->mkey_lock);
850
851 mutex_init(&priv->alloc_mutex);
852
853 priv->numa_node = dev_to_node(&dev->pdev->dev);
854
855 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
856 if (!priv->dbg_root)
857 return -ENOMEM;
858
859 err = mlx5_pci_enable_device(dev);
860 if (err) {
861 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
862 goto err_dbg;
863 }
864
865 err = request_bar(pdev);
866 if (err) {
867 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
868 goto err_disable;
869 }
870
871 pci_set_master(pdev);
872
873 err = set_dma_caps(pdev);
874 if (err) {
875 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
876 goto err_clr_master;
877 }
878
879 dev->iseg_base = pci_resource_start(dev->pdev, 0);
880 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
881 if (!dev->iseg) {
882 err = -ENOMEM;
883 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
884 goto err_clr_master;
885 }
886
887 return 0;
888
889 err_clr_master:
890 pci_clear_master(dev->pdev);
891 release_bar(dev->pdev);
892 err_disable:
893 mlx5_pci_disable_device(dev);
894
895 err_dbg:
896 debugfs_remove(priv->dbg_root);
897 return err;
898 }
899
900 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
901 {
902 iounmap(dev->iseg);
903 pci_clear_master(dev->pdev);
904 release_bar(dev->pdev);
905 mlx5_pci_disable_device(dev);
906 debugfs_remove(priv->dbg_root);
907 }
908
909 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
910 {
911 struct pci_dev *pdev = dev->pdev;
912 int err;
913
914 err = mlx5_query_board_id(dev);
915 if (err) {
916 dev_err(&pdev->dev, "query board id failed\n");
917 goto out;
918 }
919
920 err = mlx5_eq_init(dev);
921 if (err) {
922 dev_err(&pdev->dev, "failed to initialize eq\n");
923 goto out;
924 }
925
926 err = mlx5_init_cq_table(dev);
927 if (err) {
928 dev_err(&pdev->dev, "failed to initialize cq table\n");
929 goto err_eq_cleanup;
930 }
931
932 mlx5_init_qp_table(dev);
933
934 mlx5_init_srq_table(dev);
935
936 mlx5_init_mkey_table(dev);
937
938 err = mlx5_init_rl_table(dev);
939 if (err) {
940 dev_err(&pdev->dev, "Failed to init rate limiting\n");
941 goto err_tables_cleanup;
942 }
943
944 #ifdef CONFIG_MLX5_CORE_EN
945 err = mlx5_eswitch_init(dev);
946 if (err) {
947 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
948 goto err_rl_cleanup;
949 }
950 #endif
951
952 err = mlx5_sriov_init(dev);
953 if (err) {
954 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
955 goto err_eswitch_cleanup;
956 }
957
958 return 0;
959
960 err_eswitch_cleanup:
961 #ifdef CONFIG_MLX5_CORE_EN
962 mlx5_eswitch_cleanup(dev->priv.eswitch);
963
964 err_rl_cleanup:
965 #endif
966 mlx5_cleanup_rl_table(dev);
967
968 err_tables_cleanup:
969 mlx5_cleanup_mkey_table(dev);
970 mlx5_cleanup_srq_table(dev);
971 mlx5_cleanup_qp_table(dev);
972 mlx5_cleanup_cq_table(dev);
973
974 err_eq_cleanup:
975 mlx5_eq_cleanup(dev);
976
977 out:
978 return err;
979 }
980
981 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
982 {
983 mlx5_sriov_cleanup(dev);
984 #ifdef CONFIG_MLX5_CORE_EN
985 mlx5_eswitch_cleanup(dev->priv.eswitch);
986 #endif
987 mlx5_cleanup_rl_table(dev);
988 mlx5_cleanup_mkey_table(dev);
989 mlx5_cleanup_srq_table(dev);
990 mlx5_cleanup_qp_table(dev);
991 mlx5_cleanup_cq_table(dev);
992 mlx5_eq_cleanup(dev);
993 }
994
995 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
996 bool boot)
997 {
998 struct pci_dev *pdev = dev->pdev;
999 int err;
1000
1001 mutex_lock(&dev->intf_state_mutex);
1002 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1003 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
1004 __func__);
1005 goto out;
1006 }
1007
1008 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1009 fw_rev_min(dev), fw_rev_sub(dev));
1010
1011 /* on load removing any previous indication of internal error, device is
1012 * up
1013 */
1014 dev->state = MLX5_DEVICE_STATE_UP;
1015
1016 err = mlx5_cmd_init(dev);
1017 if (err) {
1018 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
1019 goto out_err;
1020 }
1021
1022 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1023 if (err) {
1024 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1025 FW_INIT_TIMEOUT_MILI);
1026 goto err_cmd_cleanup;
1027 }
1028
1029 err = mlx5_core_enable_hca(dev, 0);
1030 if (err) {
1031 dev_err(&pdev->dev, "enable hca failed\n");
1032 goto err_cmd_cleanup;
1033 }
1034
1035 err = mlx5_core_set_issi(dev);
1036 if (err) {
1037 dev_err(&pdev->dev, "failed to set issi\n");
1038 goto err_disable_hca;
1039 }
1040
1041 err = mlx5_satisfy_startup_pages(dev, 1);
1042 if (err) {
1043 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1044 goto err_disable_hca;
1045 }
1046
1047 err = set_hca_ctrl(dev);
1048 if (err) {
1049 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1050 goto reclaim_boot_pages;
1051 }
1052
1053 err = handle_hca_cap(dev);
1054 if (err) {
1055 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1056 goto reclaim_boot_pages;
1057 }
1058
1059 err = handle_hca_cap_atomic(dev);
1060 if (err) {
1061 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1062 goto reclaim_boot_pages;
1063 }
1064
1065 err = mlx5_satisfy_startup_pages(dev, 0);
1066 if (err) {
1067 dev_err(&pdev->dev, "failed to allocate init pages\n");
1068 goto reclaim_boot_pages;
1069 }
1070
1071 err = mlx5_pagealloc_start(dev);
1072 if (err) {
1073 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1074 goto reclaim_boot_pages;
1075 }
1076
1077 err = mlx5_cmd_init_hca(dev);
1078 if (err) {
1079 dev_err(&pdev->dev, "init hca failed\n");
1080 goto err_pagealloc_stop;
1081 }
1082
1083 mlx5_set_driver_version(dev);
1084
1085 mlx5_start_health_poll(dev);
1086
1087 err = mlx5_query_hca_caps(dev);
1088 if (err) {
1089 dev_err(&pdev->dev, "query hca failed\n");
1090 goto err_stop_poll;
1091 }
1092
1093 if (boot && mlx5_init_once(dev, priv)) {
1094 dev_err(&pdev->dev, "sw objs init failed\n");
1095 goto err_stop_poll;
1096 }
1097
1098 err = mlx5_enable_msix(dev);
1099 if (err) {
1100 dev_err(&pdev->dev, "enable msix failed\n");
1101 goto err_cleanup_once;
1102 }
1103
1104 dev->priv.uar = mlx5_get_uars_page(dev);
1105 if (!dev->priv.uar) {
1106 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1107 goto err_disable_msix;
1108 }
1109
1110 err = mlx5_start_eqs(dev);
1111 if (err) {
1112 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1113 goto err_put_uars;
1114 }
1115
1116 err = alloc_comp_eqs(dev);
1117 if (err) {
1118 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1119 goto err_stop_eqs;
1120 }
1121
1122 err = mlx5_irq_set_affinity_hints(dev);
1123 if (err) {
1124 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1125 goto err_affinity_hints;
1126 }
1127
1128 err = mlx5_init_fs(dev);
1129 if (err) {
1130 dev_err(&pdev->dev, "Failed to init flow steering\n");
1131 goto err_fs;
1132 }
1133
1134 #ifdef CONFIG_MLX5_CORE_EN
1135 mlx5_eswitch_attach(dev->priv.eswitch);
1136 #endif
1137
1138 err = mlx5_sriov_attach(dev);
1139 if (err) {
1140 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1141 goto err_sriov;
1142 }
1143
1144 if (mlx5_device_registered(dev)) {
1145 mlx5_attach_device(dev);
1146 } else {
1147 err = mlx5_register_device(dev);
1148 if (err) {
1149 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1150 goto err_reg_dev;
1151 }
1152 }
1153
1154 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1155 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1156 out:
1157 mutex_unlock(&dev->intf_state_mutex);
1158
1159 return 0;
1160
1161 err_reg_dev:
1162 mlx5_sriov_detach(dev);
1163
1164 err_sriov:
1165 #ifdef CONFIG_MLX5_CORE_EN
1166 mlx5_eswitch_detach(dev->priv.eswitch);
1167 #endif
1168 mlx5_cleanup_fs(dev);
1169
1170 err_fs:
1171 mlx5_irq_clear_affinity_hints(dev);
1172
1173 err_affinity_hints:
1174 free_comp_eqs(dev);
1175
1176 err_stop_eqs:
1177 mlx5_stop_eqs(dev);
1178
1179 err_put_uars:
1180 mlx5_put_uars_page(dev, priv->uar);
1181
1182 err_disable_msix:
1183 mlx5_disable_msix(dev);
1184
1185 err_cleanup_once:
1186 if (boot)
1187 mlx5_cleanup_once(dev);
1188
1189 err_stop_poll:
1190 mlx5_stop_health_poll(dev);
1191 if (mlx5_cmd_teardown_hca(dev)) {
1192 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1193 goto out_err;
1194 }
1195
1196 err_pagealloc_stop:
1197 mlx5_pagealloc_stop(dev);
1198
1199 reclaim_boot_pages:
1200 mlx5_reclaim_startup_pages(dev);
1201
1202 err_disable_hca:
1203 mlx5_core_disable_hca(dev, 0);
1204
1205 err_cmd_cleanup:
1206 mlx5_cmd_cleanup(dev);
1207
1208 out_err:
1209 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1210 mutex_unlock(&dev->intf_state_mutex);
1211
1212 return err;
1213 }
1214
1215 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1216 bool cleanup)
1217 {
1218 int err = 0;
1219
1220 if (cleanup)
1221 mlx5_drain_health_wq(dev);
1222
1223 mutex_lock(&dev->intf_state_mutex);
1224 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
1225 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1226 __func__);
1227 if (cleanup)
1228 mlx5_cleanup_once(dev);
1229 goto out;
1230 }
1231
1232 if (mlx5_device_registered(dev))
1233 mlx5_detach_device(dev);
1234
1235 mlx5_sriov_detach(dev);
1236 #ifdef CONFIG_MLX5_CORE_EN
1237 mlx5_eswitch_detach(dev->priv.eswitch);
1238 #endif
1239 mlx5_cleanup_fs(dev);
1240 mlx5_irq_clear_affinity_hints(dev);
1241 free_comp_eqs(dev);
1242 mlx5_stop_eqs(dev);
1243 mlx5_put_uars_page(dev, priv->uar);
1244 mlx5_disable_msix(dev);
1245 if (cleanup)
1246 mlx5_cleanup_once(dev);
1247 mlx5_stop_health_poll(dev);
1248 err = mlx5_cmd_teardown_hca(dev);
1249 if (err) {
1250 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1251 goto out;
1252 }
1253 mlx5_pagealloc_stop(dev);
1254 mlx5_reclaim_startup_pages(dev);
1255 mlx5_core_disable_hca(dev, 0);
1256 mlx5_cmd_cleanup(dev);
1257
1258 out:
1259 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1260 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1261 mutex_unlock(&dev->intf_state_mutex);
1262 return err;
1263 }
1264
1265 struct mlx5_core_event_handler {
1266 void (*event)(struct mlx5_core_dev *dev,
1267 enum mlx5_dev_event event,
1268 void *data);
1269 };
1270
1271 static const struct devlink_ops mlx5_devlink_ops = {
1272 #ifdef CONFIG_MLX5_CORE_EN
1273 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1274 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1275 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1276 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
1277 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1278 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
1279 #endif
1280 };
1281
1282 #define MLX5_IB_MOD "mlx5_ib"
1283 static int init_one(struct pci_dev *pdev,
1284 const struct pci_device_id *id)
1285 {
1286 struct mlx5_core_dev *dev;
1287 struct devlink *devlink;
1288 struct mlx5_priv *priv;
1289 int err;
1290
1291 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1292 if (!devlink) {
1293 dev_err(&pdev->dev, "kzalloc failed\n");
1294 return -ENOMEM;
1295 }
1296
1297 dev = devlink_priv(devlink);
1298 priv = &dev->priv;
1299 priv->pci_dev_data = id->driver_data;
1300
1301 pci_set_drvdata(pdev, dev);
1302
1303 dev->pdev = pdev;
1304 dev->event = mlx5_core_event;
1305 dev->profile = &profile[prof_sel];
1306
1307 INIT_LIST_HEAD(&priv->ctx_list);
1308 spin_lock_init(&priv->ctx_lock);
1309 mutex_init(&dev->pci_status_mutex);
1310 mutex_init(&dev->intf_state_mutex);
1311
1312 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1313 err = init_srcu_struct(&priv->pfault_srcu);
1314 if (err) {
1315 dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n",
1316 err);
1317 goto clean_dev;
1318 }
1319 #endif
1320 mutex_init(&priv->bfregs.reg_head.lock);
1321 mutex_init(&priv->bfregs.wc_head.lock);
1322 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1323 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1324
1325 err = mlx5_pci_init(dev, priv);
1326 if (err) {
1327 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1328 goto clean_srcu;
1329 }
1330
1331 err = mlx5_health_init(dev);
1332 if (err) {
1333 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1334 goto close_pci;
1335 }
1336
1337 mlx5_pagealloc_init(dev);
1338
1339 err = mlx5_load_one(dev, priv, true);
1340 if (err) {
1341 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1342 goto clean_health;
1343 }
1344
1345 request_module_nowait(MLX5_IB_MOD);
1346
1347 err = devlink_register(devlink, &pdev->dev);
1348 if (err)
1349 goto clean_load;
1350
1351 pci_save_state(pdev);
1352 return 0;
1353
1354 clean_load:
1355 mlx5_unload_one(dev, priv, true);
1356 clean_health:
1357 mlx5_pagealloc_cleanup(dev);
1358 mlx5_health_cleanup(dev);
1359 close_pci:
1360 mlx5_pci_close(dev, priv);
1361 clean_srcu:
1362 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1363 cleanup_srcu_struct(&priv->pfault_srcu);
1364 clean_dev:
1365 #endif
1366 pci_set_drvdata(pdev, NULL);
1367 devlink_free(devlink);
1368
1369 return err;
1370 }
1371
1372 static void remove_one(struct pci_dev *pdev)
1373 {
1374 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1375 struct devlink *devlink = priv_to_devlink(dev);
1376 struct mlx5_priv *priv = &dev->priv;
1377
1378 devlink_unregister(devlink);
1379 mlx5_unregister_device(dev);
1380
1381 if (mlx5_unload_one(dev, priv, true)) {
1382 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1383 mlx5_health_cleanup(dev);
1384 return;
1385 }
1386
1387 mlx5_pagealloc_cleanup(dev);
1388 mlx5_health_cleanup(dev);
1389 mlx5_pci_close(dev, priv);
1390 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1391 cleanup_srcu_struct(&priv->pfault_srcu);
1392 #endif
1393 pci_set_drvdata(pdev, NULL);
1394 devlink_free(devlink);
1395 }
1396
1397 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1398 pci_channel_state_t state)
1399 {
1400 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1401 struct mlx5_priv *priv = &dev->priv;
1402
1403 dev_info(&pdev->dev, "%s was called\n", __func__);
1404
1405 mlx5_enter_error_state(dev);
1406 mlx5_unload_one(dev, priv, false);
1407 /* In case of kernel call drain the health wq */
1408 if (state) {
1409 mlx5_drain_health_wq(dev);
1410 mlx5_pci_disable_device(dev);
1411 }
1412
1413 return state == pci_channel_io_perm_failure ?
1414 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1415 }
1416
1417 /* wait for the device to show vital signs by waiting
1418 * for the health counter to start counting.
1419 */
1420 static int wait_vital(struct pci_dev *pdev)
1421 {
1422 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1423 struct mlx5_core_health *health = &dev->priv.health;
1424 const int niter = 100;
1425 u32 last_count = 0;
1426 u32 count;
1427 int i;
1428
1429 for (i = 0; i < niter; i++) {
1430 count = ioread32be(health->health_counter);
1431 if (count && count != 0xffffffff) {
1432 if (last_count && last_count != count) {
1433 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1434 return 0;
1435 }
1436 last_count = count;
1437 }
1438 msleep(50);
1439 }
1440
1441 return -ETIMEDOUT;
1442 }
1443
1444 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1445 {
1446 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1447 int err;
1448
1449 dev_info(&pdev->dev, "%s was called\n", __func__);
1450
1451 err = mlx5_pci_enable_device(dev);
1452 if (err) {
1453 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1454 , __func__, err);
1455 return PCI_ERS_RESULT_DISCONNECT;
1456 }
1457
1458 pci_set_master(pdev);
1459 pci_restore_state(pdev);
1460 pci_save_state(pdev);
1461
1462 if (wait_vital(pdev)) {
1463 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1464 return PCI_ERS_RESULT_DISCONNECT;
1465 }
1466
1467 return PCI_ERS_RESULT_RECOVERED;
1468 }
1469
1470 static void mlx5_pci_resume(struct pci_dev *pdev)
1471 {
1472 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1473 struct mlx5_priv *priv = &dev->priv;
1474 int err;
1475
1476 dev_info(&pdev->dev, "%s was called\n", __func__);
1477
1478 err = mlx5_load_one(dev, priv, false);
1479 if (err)
1480 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1481 , __func__, err);
1482 else
1483 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1484 }
1485
1486 static const struct pci_error_handlers mlx5_err_handler = {
1487 .error_detected = mlx5_pci_err_detected,
1488 .slot_reset = mlx5_pci_slot_reset,
1489 .resume = mlx5_pci_resume
1490 };
1491
1492 static void shutdown(struct pci_dev *pdev)
1493 {
1494 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1495 struct mlx5_priv *priv = &dev->priv;
1496
1497 dev_info(&pdev->dev, "Shutdown was called\n");
1498 /* Notify mlx5 clients that the kernel is being shut down */
1499 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
1500 mlx5_unload_one(dev, priv, false);
1501 mlx5_pci_disable_device(dev);
1502 }
1503
1504 static const struct pci_device_id mlx5_core_pci_table[] = {
1505 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1506 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1507 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1508 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1509 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1510 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1511 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1512 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1513 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1514 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1515 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1516 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1517 { 0, }
1518 };
1519
1520 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1521
1522 void mlx5_disable_device(struct mlx5_core_dev *dev)
1523 {
1524 mlx5_pci_err_detected(dev->pdev, 0);
1525 }
1526
1527 void mlx5_recover_device(struct mlx5_core_dev *dev)
1528 {
1529 mlx5_pci_disable_device(dev);
1530 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1531 mlx5_pci_resume(dev->pdev);
1532 }
1533
1534 static struct pci_driver mlx5_core_driver = {
1535 .name = DRIVER_NAME,
1536 .id_table = mlx5_core_pci_table,
1537 .probe = init_one,
1538 .remove = remove_one,
1539 .shutdown = shutdown,
1540 .err_handler = &mlx5_err_handler,
1541 .sriov_configure = mlx5_core_sriov_configure,
1542 };
1543
1544 static void mlx5_core_verify_params(void)
1545 {
1546 if (prof_sel >= ARRAY_SIZE(profile)) {
1547 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1548 prof_sel,
1549 ARRAY_SIZE(profile) - 1,
1550 MLX5_DEFAULT_PROF);
1551 prof_sel = MLX5_DEFAULT_PROF;
1552 }
1553 }
1554
1555 static int __init init(void)
1556 {
1557 int err;
1558
1559 mlx5_core_verify_params();
1560 mlx5_register_debugfs();
1561
1562 err = pci_register_driver(&mlx5_core_driver);
1563 if (err)
1564 goto err_debug;
1565
1566 #ifdef CONFIG_MLX5_CORE_EN
1567 mlx5e_init();
1568 #endif
1569
1570 return 0;
1571
1572 err_debug:
1573 mlx5_unregister_debugfs();
1574 return err;
1575 }
1576
1577 static void __exit cleanup(void)
1578 {
1579 #ifdef CONFIG_MLX5_CORE_EN
1580 mlx5e_cleanup();
1581 #endif
1582 pci_unregister_driver(&mlx5_core_driver);
1583 mlx5_unregister_debugfs();
1584 }
1585
1586 module_init(init);
1587 module_exit(cleanup);
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