2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
61 #include "fpga/core.h"
62 #include "fpga/ipsec.h"
63 #include "accel/ipsec.h"
64 #include "accel/tls.h"
65 #include "lib/clock.h"
66 #include "lib/vxlan.h"
67 #include "lib/geneve.h"
68 #include "lib/devcom.h"
69 #include "lib/pci_vsc.h"
70 #include "diag/fw_tracer.h"
72 #include "lib/hv_vhca.h"
74 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
75 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
76 MODULE_LICENSE("Dual BSD/GPL");
77 MODULE_VERSION(DRIVER_VERSION
);
79 unsigned int mlx5_core_debug_mask
;
80 module_param_named(debug_mask
, mlx5_core_debug_mask
, uint
, 0644);
81 MODULE_PARM_DESC(debug_mask
, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
83 #define MLX5_DEFAULT_PROF 2
84 static unsigned int prof_sel
= MLX5_DEFAULT_PROF
;
85 module_param_named(prof_sel
, prof_sel
, uint
, 0444);
86 MODULE_PARM_DESC(prof_sel
, "profile selector. Valid range 0 - 2");
88 static u32 sw_owner_id
[4];
91 MLX5_ATOMIC_REQ_MODE_BE
= 0x0,
92 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
= 0x1,
95 static struct mlx5_profile profile
[] = {
100 .mask
= MLX5_PROF_MASK_QP_SIZE
,
104 .mask
= MLX5_PROF_MASK_QP_SIZE
|
105 MLX5_PROF_MASK_MR_CACHE
,
174 #define FW_INIT_TIMEOUT_MILI 2000
175 #define FW_INIT_WAIT_MS 2
176 #define FW_PRE_INIT_TIMEOUT_MILI 120000
177 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
179 static int wait_fw_init(struct mlx5_core_dev
*dev
, u32 max_wait_mili
,
182 unsigned long warn
= jiffies
+ msecs_to_jiffies(warn_time_mili
);
183 unsigned long end
= jiffies
+ msecs_to_jiffies(max_wait_mili
);
186 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI
< FW_INIT_WARN_MESSAGE_INTERVAL
);
188 while (fw_initializing(dev
)) {
189 if (time_after(jiffies
, end
)) {
193 if (warn_time_mili
&& time_after(jiffies
, warn
)) {
194 mlx5_core_warn(dev
, "Waiting for FW initialization, timeout abort in %ds\n",
195 jiffies_to_msecs(end
- warn
) / 1000);
196 warn
= jiffies
+ msecs_to_jiffies(warn_time_mili
);
198 msleep(FW_INIT_WAIT_MS
);
204 static void mlx5_set_driver_version(struct mlx5_core_dev
*dev
)
206 int driver_ver_sz
= MLX5_FLD_SZ_BYTES(set_driver_version_in
,
208 u8 in
[MLX5_ST_SZ_BYTES(set_driver_version_in
)] = {0};
209 u8 out
[MLX5_ST_SZ_BYTES(set_driver_version_out
)] = {0};
210 int remaining_size
= driver_ver_sz
;
213 if (!MLX5_CAP_GEN(dev
, driver_version
))
216 string
= MLX5_ADDR_OF(set_driver_version_in
, in
, driver_version
);
218 strncpy(string
, "Linux", remaining_size
);
220 remaining_size
= max_t(int, 0, driver_ver_sz
- strlen(string
));
221 strncat(string
, ",", remaining_size
);
223 remaining_size
= max_t(int, 0, driver_ver_sz
- strlen(string
));
224 strncat(string
, DRIVER_NAME
, remaining_size
);
226 remaining_size
= max_t(int, 0, driver_ver_sz
- strlen(string
));
227 strncat(string
, ",", remaining_size
);
229 remaining_size
= max_t(int, 0, driver_ver_sz
- strlen(string
));
230 strncat(string
, DRIVER_VERSION
, remaining_size
);
233 MLX5_SET(set_driver_version_in
, in
, opcode
,
234 MLX5_CMD_OP_SET_DRIVER_VERSION
);
236 mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, sizeof(out
));
239 static int set_dma_caps(struct pci_dev
*pdev
)
243 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
245 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask\n");
246 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
248 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting\n");
253 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
256 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
257 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
260 "Can't set consistent PCI DMA mask, aborting\n");
265 dma_set_max_seg_size(&pdev
->dev
, 2u * 1024 * 1024 * 1024);
269 static int mlx5_pci_enable_device(struct mlx5_core_dev
*dev
)
271 struct pci_dev
*pdev
= dev
->pdev
;
274 mutex_lock(&dev
->pci_status_mutex
);
275 if (dev
->pci_status
== MLX5_PCI_STATUS_DISABLED
) {
276 err
= pci_enable_device(pdev
);
278 dev
->pci_status
= MLX5_PCI_STATUS_ENABLED
;
280 mutex_unlock(&dev
->pci_status_mutex
);
285 static void mlx5_pci_disable_device(struct mlx5_core_dev
*dev
)
287 struct pci_dev
*pdev
= dev
->pdev
;
289 mutex_lock(&dev
->pci_status_mutex
);
290 if (dev
->pci_status
== MLX5_PCI_STATUS_ENABLED
) {
291 pci_disable_device(pdev
);
292 dev
->pci_status
= MLX5_PCI_STATUS_DISABLED
;
294 mutex_unlock(&dev
->pci_status_mutex
);
297 static int request_bar(struct pci_dev
*pdev
)
301 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
302 dev_err(&pdev
->dev
, "Missing registers BAR, aborting\n");
306 err
= pci_request_regions(pdev
, DRIVER_NAME
);
308 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
313 static void release_bar(struct pci_dev
*pdev
)
315 pci_release_regions(pdev
);
318 struct mlx5_reg_host_endianness
{
323 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
326 MLX5_CAP_BITS_RW_MASK
= CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM
, 2) |
327 MLX5_DEV_CAP_FLAG_DCT
,
330 static u16
to_fw_pkey_sz(struct mlx5_core_dev
*dev
, u32 size
)
346 mlx5_core_warn(dev
, "invalid pkey table size %d\n", size
);
351 static int mlx5_core_get_caps_mode(struct mlx5_core_dev
*dev
,
352 enum mlx5_cap_type cap_type
,
353 enum mlx5_cap_mode cap_mode
)
355 u8 in
[MLX5_ST_SZ_BYTES(query_hca_cap_in
)];
356 int out_sz
= MLX5_ST_SZ_BYTES(query_hca_cap_out
);
357 void *out
, *hca_caps
;
358 u16 opmod
= (cap_type
<< 1) | (cap_mode
& 0x01);
361 memset(in
, 0, sizeof(in
));
362 out
= kzalloc(out_sz
, GFP_KERNEL
);
366 MLX5_SET(query_hca_cap_in
, in
, opcode
, MLX5_CMD_OP_QUERY_HCA_CAP
);
367 MLX5_SET(query_hca_cap_in
, in
, op_mod
, opmod
);
368 err
= mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, out_sz
);
371 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
372 cap_type
, cap_mode
, err
);
376 hca_caps
= MLX5_ADDR_OF(query_hca_cap_out
, out
, capability
);
379 case HCA_CAP_OPMOD_GET_MAX
:
380 memcpy(dev
->caps
.hca_max
[cap_type
], hca_caps
,
381 MLX5_UN_SZ_BYTES(hca_cap_union
));
383 case HCA_CAP_OPMOD_GET_CUR
:
384 memcpy(dev
->caps
.hca_cur
[cap_type
], hca_caps
,
385 MLX5_UN_SZ_BYTES(hca_cap_union
));
389 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
399 int mlx5_core_get_caps(struct mlx5_core_dev
*dev
, enum mlx5_cap_type cap_type
)
403 ret
= mlx5_core_get_caps_mode(dev
, cap_type
, HCA_CAP_OPMOD_GET_CUR
);
406 return mlx5_core_get_caps_mode(dev
, cap_type
, HCA_CAP_OPMOD_GET_MAX
);
409 static int set_caps(struct mlx5_core_dev
*dev
, void *in
, int in_sz
, int opmod
)
411 u32 out
[MLX5_ST_SZ_DW(set_hca_cap_out
)] = {0};
413 MLX5_SET(set_hca_cap_in
, in
, opcode
, MLX5_CMD_OP_SET_HCA_CAP
);
414 MLX5_SET(set_hca_cap_in
, in
, op_mod
, opmod
<< 1);
415 return mlx5_cmd_exec(dev
, in
, in_sz
, out
, sizeof(out
));
418 static int handle_hca_cap_atomic(struct mlx5_core_dev
*dev
)
422 int set_sz
= MLX5_ST_SZ_BYTES(set_hca_cap_in
);
426 if (MLX5_CAP_GEN(dev
, atomic
)) {
427 err
= mlx5_core_get_caps(dev
, MLX5_CAP_ATOMIC
);
436 supported_atomic_req_8B_endianness_mode_1
);
438 if (req_endianness
!= MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
)
441 set_ctx
= kzalloc(set_sz
, GFP_KERNEL
);
445 set_hca_cap
= MLX5_ADDR_OF(set_hca_cap_in
, set_ctx
, capability
);
447 /* Set requestor to host endianness */
448 MLX5_SET(atomic_caps
, set_hca_cap
, atomic_req_8B_endianness_mode
,
449 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
);
451 err
= set_caps(dev
, set_ctx
, set_sz
, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC
);
457 static int handle_hca_cap_odp(struct mlx5_core_dev
*dev
)
465 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING
) ||
466 !MLX5_CAP_GEN(dev
, pg
))
469 err
= mlx5_core_get_caps(dev
, MLX5_CAP_ODP
);
473 set_sz
= MLX5_ST_SZ_BYTES(set_hca_cap_in
);
474 set_ctx
= kzalloc(set_sz
, GFP_KERNEL
);
478 set_hca_cap
= MLX5_ADDR_OF(set_hca_cap_in
, set_ctx
, capability
);
479 memcpy(set_hca_cap
, dev
->caps
.hca_cur
[MLX5_CAP_ODP
],
480 MLX5_ST_SZ_BYTES(odp_cap
));
482 #define ODP_CAP_SET_MAX(dev, field) \
484 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
487 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
491 ODP_CAP_SET_MAX(dev
, ud_odp_caps
.srq_receive
);
492 ODP_CAP_SET_MAX(dev
, rc_odp_caps
.srq_receive
);
493 ODP_CAP_SET_MAX(dev
, xrc_odp_caps
.srq_receive
);
494 ODP_CAP_SET_MAX(dev
, xrc_odp_caps
.send
);
495 ODP_CAP_SET_MAX(dev
, xrc_odp_caps
.receive
);
496 ODP_CAP_SET_MAX(dev
, xrc_odp_caps
.write
);
497 ODP_CAP_SET_MAX(dev
, xrc_odp_caps
.read
);
498 ODP_CAP_SET_MAX(dev
, xrc_odp_caps
.atomic
);
499 ODP_CAP_SET_MAX(dev
, dc_odp_caps
.srq_receive
);
500 ODP_CAP_SET_MAX(dev
, dc_odp_caps
.send
);
501 ODP_CAP_SET_MAX(dev
, dc_odp_caps
.receive
);
502 ODP_CAP_SET_MAX(dev
, dc_odp_caps
.write
);
503 ODP_CAP_SET_MAX(dev
, dc_odp_caps
.read
);
504 ODP_CAP_SET_MAX(dev
, dc_odp_caps
.atomic
);
507 err
= set_caps(dev
, set_ctx
, set_sz
,
508 MLX5_SET_HCA_CAP_OP_MOD_ODP
);
515 static int handle_hca_cap(struct mlx5_core_dev
*dev
)
517 void *set_ctx
= NULL
;
518 struct mlx5_profile
*prof
= dev
->profile
;
520 int set_sz
= MLX5_ST_SZ_BYTES(set_hca_cap_in
);
523 set_ctx
= kzalloc(set_sz
, GFP_KERNEL
);
527 err
= mlx5_core_get_caps(dev
, MLX5_CAP_GENERAL
);
531 set_hca_cap
= MLX5_ADDR_OF(set_hca_cap_in
, set_ctx
,
533 memcpy(set_hca_cap
, dev
->caps
.hca_cur
[MLX5_CAP_GENERAL
],
534 MLX5_ST_SZ_BYTES(cmd_hca_cap
));
536 mlx5_core_dbg(dev
, "Current Pkey table size %d Setting new size %d\n",
537 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev
, pkey_table_size
)),
539 /* we limit the size of the pkey table to 128 entries for now */
540 MLX5_SET(cmd_hca_cap
, set_hca_cap
, pkey_table_size
,
541 to_fw_pkey_sz(dev
, 128));
543 /* Check log_max_qp from HCA caps to set in current profile */
544 if (MLX5_CAP_GEN_MAX(dev
, log_max_qp
) < profile
[prof_sel
].log_max_qp
) {
545 mlx5_core_warn(dev
, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
546 profile
[prof_sel
].log_max_qp
,
547 MLX5_CAP_GEN_MAX(dev
, log_max_qp
));
548 profile
[prof_sel
].log_max_qp
= MLX5_CAP_GEN_MAX(dev
, log_max_qp
);
550 if (prof
->mask
& MLX5_PROF_MASK_QP_SIZE
)
551 MLX5_SET(cmd_hca_cap
, set_hca_cap
, log_max_qp
,
554 /* disable cmdif checksum */
555 MLX5_SET(cmd_hca_cap
, set_hca_cap
, cmdif_checksum
, 0);
557 /* Enable 4K UAR only when HCA supports it and page size is bigger
560 if (MLX5_CAP_GEN_MAX(dev
, uar_4k
) && PAGE_SIZE
> 4096)
561 MLX5_SET(cmd_hca_cap
, set_hca_cap
, uar_4k
, 1);
563 MLX5_SET(cmd_hca_cap
, set_hca_cap
, log_uar_page_sz
, PAGE_SHIFT
- 12);
565 if (MLX5_CAP_GEN_MAX(dev
, cache_line_128byte
))
566 MLX5_SET(cmd_hca_cap
,
569 cache_line_size() >= 128 ? 1 : 0);
571 if (MLX5_CAP_GEN_MAX(dev
, dct
))
572 MLX5_SET(cmd_hca_cap
, set_hca_cap
, dct
, 1);
574 if (MLX5_CAP_GEN_MAX(dev
, num_vhca_ports
))
575 MLX5_SET(cmd_hca_cap
,
578 MLX5_CAP_GEN_MAX(dev
, num_vhca_ports
));
580 err
= set_caps(dev
, set_ctx
, set_sz
,
581 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE
);
588 static int set_hca_cap(struct mlx5_core_dev
*dev
)
592 err
= handle_hca_cap(dev
);
594 mlx5_core_err(dev
, "handle_hca_cap failed\n");
598 err
= handle_hca_cap_atomic(dev
);
600 mlx5_core_err(dev
, "handle_hca_cap_atomic failed\n");
604 err
= handle_hca_cap_odp(dev
);
606 mlx5_core_err(dev
, "handle_hca_cap_odp failed\n");
614 static int set_hca_ctrl(struct mlx5_core_dev
*dev
)
616 struct mlx5_reg_host_endianness he_in
;
617 struct mlx5_reg_host_endianness he_out
;
620 if (!mlx5_core_is_pf(dev
))
623 memset(&he_in
, 0, sizeof(he_in
));
624 he_in
.he
= MLX5_SET_HOST_ENDIANNESS
;
625 err
= mlx5_core_access_reg(dev
, &he_in
, sizeof(he_in
),
626 &he_out
, sizeof(he_out
),
627 MLX5_REG_HOST_ENDIANNESS
, 0, 1);
631 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev
*dev
)
635 /* Disable local_lb by default */
636 if (MLX5_CAP_GEN(dev
, port_type
) == MLX5_CAP_PORT_TYPE_ETH
)
637 ret
= mlx5_nic_vport_update_local_lb(dev
, false);
642 int mlx5_core_enable_hca(struct mlx5_core_dev
*dev
, u16 func_id
)
644 u32 out
[MLX5_ST_SZ_DW(enable_hca_out
)] = {0};
645 u32 in
[MLX5_ST_SZ_DW(enable_hca_in
)] = {0};
647 MLX5_SET(enable_hca_in
, in
, opcode
, MLX5_CMD_OP_ENABLE_HCA
);
648 MLX5_SET(enable_hca_in
, in
, function_id
, func_id
);
649 MLX5_SET(enable_hca_in
, in
, embedded_cpu_function
,
650 dev
->caps
.embedded_cpu
);
651 return mlx5_cmd_exec(dev
, &in
, sizeof(in
), &out
, sizeof(out
));
654 int mlx5_core_disable_hca(struct mlx5_core_dev
*dev
, u16 func_id
)
656 u32 out
[MLX5_ST_SZ_DW(disable_hca_out
)] = {0};
657 u32 in
[MLX5_ST_SZ_DW(disable_hca_in
)] = {0};
659 MLX5_SET(disable_hca_in
, in
, opcode
, MLX5_CMD_OP_DISABLE_HCA
);
660 MLX5_SET(disable_hca_in
, in
, function_id
, func_id
);
661 MLX5_SET(enable_hca_in
, in
, embedded_cpu_function
,
662 dev
->caps
.embedded_cpu
);
663 return mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, sizeof(out
));
666 u64
mlx5_read_internal_timer(struct mlx5_core_dev
*dev
,
667 struct ptp_system_timestamp
*sts
)
669 u32 timer_h
, timer_h1
, timer_l
;
671 timer_h
= ioread32be(&dev
->iseg
->internal_timer_h
);
672 ptp_read_system_prets(sts
);
673 timer_l
= ioread32be(&dev
->iseg
->internal_timer_l
);
674 ptp_read_system_postts(sts
);
675 timer_h1
= ioread32be(&dev
->iseg
->internal_timer_h
);
676 if (timer_h
!= timer_h1
) {
678 ptp_read_system_prets(sts
);
679 timer_l
= ioread32be(&dev
->iseg
->internal_timer_l
);
680 ptp_read_system_postts(sts
);
683 return (u64
)timer_l
| (u64
)timer_h1
<< 32;
686 static int mlx5_core_set_issi(struct mlx5_core_dev
*dev
)
688 u32 query_in
[MLX5_ST_SZ_DW(query_issi_in
)] = {0};
689 u32 query_out
[MLX5_ST_SZ_DW(query_issi_out
)] = {0};
693 MLX5_SET(query_issi_in
, query_in
, opcode
, MLX5_CMD_OP_QUERY_ISSI
);
694 err
= mlx5_cmd_exec(dev
, query_in
, sizeof(query_in
),
695 query_out
, sizeof(query_out
));
700 mlx5_cmd_mbox_status(query_out
, &status
, &syndrome
);
701 if (!status
|| syndrome
== MLX5_DRIVER_SYND
) {
702 mlx5_core_err(dev
, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
703 err
, status
, syndrome
);
707 mlx5_core_warn(dev
, "Query ISSI is not supported by FW, ISSI is 0\n");
712 sup_issi
= MLX5_GET(query_issi_out
, query_out
, supported_issi_dw0
);
714 if (sup_issi
& (1 << 1)) {
715 u32 set_in
[MLX5_ST_SZ_DW(set_issi_in
)] = {0};
716 u32 set_out
[MLX5_ST_SZ_DW(set_issi_out
)] = {0};
718 MLX5_SET(set_issi_in
, set_in
, opcode
, MLX5_CMD_OP_SET_ISSI
);
719 MLX5_SET(set_issi_in
, set_in
, current_issi
, 1);
720 err
= mlx5_cmd_exec(dev
, set_in
, sizeof(set_in
),
721 set_out
, sizeof(set_out
));
723 mlx5_core_err(dev
, "Failed to set ISSI to 1 err(%d)\n",
731 } else if (sup_issi
& (1 << 0) || !sup_issi
) {
738 static int mlx5_pci_init(struct mlx5_core_dev
*dev
, struct pci_dev
*pdev
,
739 const struct pci_device_id
*id
)
741 struct mlx5_priv
*priv
= &dev
->priv
;
744 mutex_init(&dev
->pci_status_mutex
);
745 pci_set_drvdata(dev
->pdev
, dev
);
747 dev
->bar_addr
= pci_resource_start(pdev
, 0);
748 priv
->numa_node
= dev_to_node(&dev
->pdev
->dev
);
750 err
= mlx5_pci_enable_device(dev
);
752 mlx5_core_err(dev
, "Cannot enable PCI device, aborting\n");
756 err
= request_bar(pdev
);
758 mlx5_core_err(dev
, "error requesting BARs, aborting\n");
762 pci_set_master(pdev
);
764 err
= set_dma_caps(pdev
);
766 mlx5_core_err(dev
, "Failed setting DMA capabilities mask, aborting\n");
770 if (pci_enable_atomic_ops_to_root(pdev
, PCI_EXP_DEVCAP2_ATOMIC_COMP32
) &&
771 pci_enable_atomic_ops_to_root(pdev
, PCI_EXP_DEVCAP2_ATOMIC_COMP64
) &&
772 pci_enable_atomic_ops_to_root(pdev
, PCI_EXP_DEVCAP2_ATOMIC_COMP128
))
773 mlx5_core_dbg(dev
, "Enabling pci atomics failed\n");
775 dev
->iseg_base
= dev
->bar_addr
;
776 dev
->iseg
= ioremap(dev
->iseg_base
, sizeof(*dev
->iseg
));
779 mlx5_core_err(dev
, "Failed mapping initialization segment, aborting\n");
783 mlx5_pci_vsc_init(dev
);
788 pci_clear_master(dev
->pdev
);
789 release_bar(dev
->pdev
);
791 mlx5_pci_disable_device(dev
);
795 static void mlx5_pci_close(struct mlx5_core_dev
*dev
)
798 pci_clear_master(dev
->pdev
);
799 release_bar(dev
->pdev
);
800 mlx5_pci_disable_device(dev
);
803 static int mlx5_init_once(struct mlx5_core_dev
*dev
)
807 dev
->priv
.devcom
= mlx5_devcom_register_device(dev
);
808 if (IS_ERR(dev
->priv
.devcom
))
809 mlx5_core_err(dev
, "failed to register with devcom (0x%p)\n",
812 err
= mlx5_query_board_id(dev
);
814 mlx5_core_err(dev
, "query board id failed\n");
818 err
= mlx5_irq_table_init(dev
);
820 mlx5_core_err(dev
, "failed to initialize irq table\n");
824 err
= mlx5_eq_table_init(dev
);
826 mlx5_core_err(dev
, "failed to initialize eq\n");
827 goto err_irq_cleanup
;
830 err
= mlx5_events_init(dev
);
832 mlx5_core_err(dev
, "failed to initialize events\n");
836 mlx5_cq_debugfs_init(dev
);
838 mlx5_init_qp_table(dev
);
840 mlx5_init_mkey_table(dev
);
842 mlx5_init_reserved_gids(dev
);
844 mlx5_init_clock(dev
);
846 dev
->vxlan
= mlx5_vxlan_create(dev
);
847 dev
->geneve
= mlx5_geneve_create(dev
);
849 err
= mlx5_init_rl_table(dev
);
851 mlx5_core_err(dev
, "Failed to init rate limiting\n");
852 goto err_tables_cleanup
;
855 err
= mlx5_mpfs_init(dev
);
857 mlx5_core_err(dev
, "Failed to init l2 table %d\n", err
);
861 err
= mlx5_sriov_init(dev
);
863 mlx5_core_err(dev
, "Failed to init sriov %d\n", err
);
864 goto err_mpfs_cleanup
;
867 err
= mlx5_eswitch_init(dev
);
869 mlx5_core_err(dev
, "Failed to init eswitch %d\n", err
);
870 goto err_sriov_cleanup
;
873 err
= mlx5_fpga_init(dev
);
875 mlx5_core_err(dev
, "Failed to init fpga device %d\n", err
);
876 goto err_eswitch_cleanup
;
879 dev
->dm
= mlx5_dm_create(dev
);
881 mlx5_core_warn(dev
, "Failed to init device memory%d\n", err
);
883 dev
->tracer
= mlx5_fw_tracer_create(dev
);
884 dev
->hv_vhca
= mlx5_hv_vhca_create(dev
);
889 mlx5_eswitch_cleanup(dev
->priv
.eswitch
);
891 mlx5_sriov_cleanup(dev
);
893 mlx5_mpfs_cleanup(dev
);
895 mlx5_cleanup_rl_table(dev
);
897 mlx5_geneve_destroy(dev
->geneve
);
898 mlx5_vxlan_destroy(dev
->vxlan
);
899 mlx5_cleanup_mkey_table(dev
);
900 mlx5_cleanup_qp_table(dev
);
901 mlx5_cq_debugfs_cleanup(dev
);
902 mlx5_events_cleanup(dev
);
904 mlx5_eq_table_cleanup(dev
);
906 mlx5_irq_table_cleanup(dev
);
908 mlx5_devcom_unregister_device(dev
->priv
.devcom
);
913 static void mlx5_cleanup_once(struct mlx5_core_dev
*dev
)
915 mlx5_hv_vhca_destroy(dev
->hv_vhca
);
916 mlx5_fw_tracer_destroy(dev
->tracer
);
917 mlx5_dm_cleanup(dev
);
918 mlx5_fpga_cleanup(dev
);
919 mlx5_eswitch_cleanup(dev
->priv
.eswitch
);
920 mlx5_sriov_cleanup(dev
);
921 mlx5_mpfs_cleanup(dev
);
922 mlx5_cleanup_rl_table(dev
);
923 mlx5_geneve_destroy(dev
->geneve
);
924 mlx5_vxlan_destroy(dev
->vxlan
);
925 mlx5_cleanup_clock(dev
);
926 mlx5_cleanup_reserved_gids(dev
);
927 mlx5_cleanup_mkey_table(dev
);
928 mlx5_cleanup_qp_table(dev
);
929 mlx5_cq_debugfs_cleanup(dev
);
930 mlx5_events_cleanup(dev
);
931 mlx5_eq_table_cleanup(dev
);
932 mlx5_irq_table_cleanup(dev
);
933 mlx5_devcom_unregister_device(dev
->priv
.devcom
);
936 static int mlx5_function_setup(struct mlx5_core_dev
*dev
, bool boot
)
940 mlx5_core_info(dev
, "firmware version: %d.%d.%d\n", fw_rev_maj(dev
),
941 fw_rev_min(dev
), fw_rev_sub(dev
));
943 /* Only PFs hold the relevant PCIe information for this query */
944 if (mlx5_core_is_pf(dev
))
945 pcie_print_link_status(dev
->pdev
);
947 /* wait for firmware to accept initialization segments configurations
949 err
= wait_fw_init(dev
, FW_PRE_INIT_TIMEOUT_MILI
, FW_INIT_WARN_MESSAGE_INTERVAL
);
951 mlx5_core_err(dev
, "Firmware over %d MS in pre-initializing state, aborting\n",
952 FW_PRE_INIT_TIMEOUT_MILI
);
956 err
= mlx5_cmd_init(dev
);
958 mlx5_core_err(dev
, "Failed initializing command interface, aborting\n");
962 err
= wait_fw_init(dev
, FW_INIT_TIMEOUT_MILI
, 0);
964 mlx5_core_err(dev
, "Firmware over %d MS in initializing state, aborting\n",
965 FW_INIT_TIMEOUT_MILI
);
966 goto err_cmd_cleanup
;
969 err
= mlx5_core_enable_hca(dev
, 0);
971 mlx5_core_err(dev
, "enable hca failed\n");
972 goto err_cmd_cleanup
;
975 err
= mlx5_core_set_issi(dev
);
977 mlx5_core_err(dev
, "failed to set issi\n");
978 goto err_disable_hca
;
981 err
= mlx5_satisfy_startup_pages(dev
, 1);
983 mlx5_core_err(dev
, "failed to allocate boot pages\n");
984 goto err_disable_hca
;
987 err
= set_hca_ctrl(dev
);
989 mlx5_core_err(dev
, "set_hca_ctrl failed\n");
990 goto reclaim_boot_pages
;
993 err
= set_hca_cap(dev
);
995 mlx5_core_err(dev
, "set_hca_cap failed\n");
996 goto reclaim_boot_pages
;
999 err
= mlx5_satisfy_startup_pages(dev
, 0);
1001 mlx5_core_err(dev
, "failed to allocate init pages\n");
1002 goto reclaim_boot_pages
;
1005 err
= mlx5_cmd_init_hca(dev
, sw_owner_id
);
1007 mlx5_core_err(dev
, "init hca failed\n");
1008 goto reclaim_boot_pages
;
1011 mlx5_set_driver_version(dev
);
1013 mlx5_start_health_poll(dev
);
1015 err
= mlx5_query_hca_caps(dev
);
1017 mlx5_core_err(dev
, "query hca failed\n");
1024 mlx5_stop_health_poll(dev
, boot
);
1026 mlx5_reclaim_startup_pages(dev
);
1028 mlx5_core_disable_hca(dev
, 0);
1030 mlx5_cmd_cleanup(dev
);
1035 static int mlx5_function_teardown(struct mlx5_core_dev
*dev
, bool boot
)
1039 mlx5_stop_health_poll(dev
, boot
);
1040 err
= mlx5_cmd_teardown_hca(dev
);
1042 mlx5_core_err(dev
, "tear_down_hca failed, skip cleanup\n");
1045 mlx5_reclaim_startup_pages(dev
);
1046 mlx5_core_disable_hca(dev
, 0);
1047 mlx5_cmd_cleanup(dev
);
1052 static int mlx5_load(struct mlx5_core_dev
*dev
)
1056 dev
->priv
.uar
= mlx5_get_uars_page(dev
);
1057 if (IS_ERR(dev
->priv
.uar
)) {
1058 mlx5_core_err(dev
, "Failed allocating uar, aborting\n");
1059 err
= PTR_ERR(dev
->priv
.uar
);
1063 mlx5_events_start(dev
);
1064 mlx5_pagealloc_start(dev
);
1066 err
= mlx5_irq_table_create(dev
);
1068 mlx5_core_err(dev
, "Failed to alloc IRQs\n");
1072 err
= mlx5_eq_table_create(dev
);
1074 mlx5_core_err(dev
, "Failed to create EQs\n");
1078 err
= mlx5_fw_tracer_init(dev
->tracer
);
1080 mlx5_core_err(dev
, "Failed to init FW tracer\n");
1084 mlx5_hv_vhca_init(dev
->hv_vhca
);
1086 err
= mlx5_fpga_device_start(dev
);
1088 mlx5_core_err(dev
, "fpga device start failed %d\n", err
);
1089 goto err_fpga_start
;
1092 err
= mlx5_accel_ipsec_init(dev
);
1094 mlx5_core_err(dev
, "IPSec device start failed %d\n", err
);
1095 goto err_ipsec_start
;
1098 err
= mlx5_accel_tls_init(dev
);
1100 mlx5_core_err(dev
, "TLS device start failed %d\n", err
);
1104 err
= mlx5_init_fs(dev
);
1106 mlx5_core_err(dev
, "Failed to init flow steering\n");
1110 err
= mlx5_core_set_hca_defaults(dev
);
1112 mlx5_core_err(dev
, "Failed to set hca defaults\n");
1116 err
= mlx5_sriov_attach(dev
);
1118 mlx5_core_err(dev
, "sriov init failed %d\n", err
);
1122 err
= mlx5_ec_init(dev
);
1124 mlx5_core_err(dev
, "Failed to init embedded CPU\n");
1131 mlx5_sriov_detach(dev
);
1133 mlx5_cleanup_fs(dev
);
1135 mlx5_accel_tls_cleanup(dev
);
1137 mlx5_accel_ipsec_cleanup(dev
);
1139 mlx5_fpga_device_stop(dev
);
1141 mlx5_hv_vhca_cleanup(dev
->hv_vhca
);
1142 mlx5_fw_tracer_cleanup(dev
->tracer
);
1144 mlx5_eq_table_destroy(dev
);
1146 mlx5_irq_table_destroy(dev
);
1148 mlx5_pagealloc_stop(dev
);
1149 mlx5_events_stop(dev
);
1150 mlx5_put_uars_page(dev
, dev
->priv
.uar
);
1154 static void mlx5_unload(struct mlx5_core_dev
*dev
)
1156 mlx5_ec_cleanup(dev
);
1157 mlx5_sriov_detach(dev
);
1158 mlx5_cleanup_fs(dev
);
1159 mlx5_accel_ipsec_cleanup(dev
);
1160 mlx5_accel_tls_cleanup(dev
);
1161 mlx5_fpga_device_stop(dev
);
1162 mlx5_hv_vhca_cleanup(dev
->hv_vhca
);
1163 mlx5_fw_tracer_cleanup(dev
->tracer
);
1164 mlx5_eq_table_destroy(dev
);
1165 mlx5_irq_table_destroy(dev
);
1166 mlx5_pagealloc_stop(dev
);
1167 mlx5_events_stop(dev
);
1168 mlx5_put_uars_page(dev
, dev
->priv
.uar
);
1171 int mlx5_load_one(struct mlx5_core_dev
*dev
, bool boot
)
1175 dev
->caps
.embedded_cpu
= mlx5_read_embedded_cpu(dev
);
1176 mutex_lock(&dev
->intf_state_mutex
);
1177 if (test_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
)) {
1178 mlx5_core_warn(dev
, "interface is up, NOP\n");
1181 /* remove any previous indication of internal error */
1182 dev
->state
= MLX5_DEVICE_STATE_UP
;
1184 err
= mlx5_function_setup(dev
, boot
);
1189 err
= mlx5_init_once(dev
);
1191 mlx5_core_err(dev
, "sw objs init failed\n");
1192 goto function_teardown
;
1196 err
= mlx5_load(dev
);
1200 if (mlx5_device_registered(dev
)) {
1201 mlx5_attach_device(dev
);
1203 err
= mlx5_register_device(dev
);
1205 mlx5_core_err(dev
, "register device failed %d\n", err
);
1210 set_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
);
1212 mutex_unlock(&dev
->intf_state_mutex
);
1220 mlx5_cleanup_once(dev
);
1222 mlx5_function_teardown(dev
, boot
);
1223 dev
->state
= MLX5_DEVICE_STATE_INTERNAL_ERROR
;
1224 mutex_unlock(&dev
->intf_state_mutex
);
1229 int mlx5_unload_one(struct mlx5_core_dev
*dev
, bool cleanup
)
1232 mlx5_unregister_device(dev
);
1233 mlx5_drain_health_wq(dev
);
1236 mutex_lock(&dev
->intf_state_mutex
);
1237 if (!test_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
)) {
1238 mlx5_core_warn(dev
, "%s: interface is down, NOP\n",
1241 mlx5_cleanup_once(dev
);
1245 clear_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
);
1247 if (mlx5_device_registered(dev
))
1248 mlx5_detach_device(dev
);
1253 mlx5_cleanup_once(dev
);
1255 mlx5_function_teardown(dev
, cleanup
);
1257 mutex_unlock(&dev
->intf_state_mutex
);
1261 static int mlx5_mdev_init(struct mlx5_core_dev
*dev
, int profile_idx
)
1263 struct mlx5_priv
*priv
= &dev
->priv
;
1266 dev
->profile
= &profile
[profile_idx
];
1268 INIT_LIST_HEAD(&priv
->ctx_list
);
1269 spin_lock_init(&priv
->ctx_lock
);
1270 mutex_init(&dev
->intf_state_mutex
);
1272 mutex_init(&priv
->bfregs
.reg_head
.lock
);
1273 mutex_init(&priv
->bfregs
.wc_head
.lock
);
1274 INIT_LIST_HEAD(&priv
->bfregs
.reg_head
.list
);
1275 INIT_LIST_HEAD(&priv
->bfregs
.wc_head
.list
);
1277 mutex_init(&priv
->alloc_mutex
);
1278 mutex_init(&priv
->pgdir_mutex
);
1279 INIT_LIST_HEAD(&priv
->pgdir_list
);
1280 spin_lock_init(&priv
->mkey_lock
);
1282 priv
->dbg_root
= debugfs_create_dir(dev_name(dev
->device
),
1284 if (!priv
->dbg_root
) {
1285 dev_err(dev
->device
, "mlx5_core: error, Cannot create debugfs dir, aborting\n");
1289 err
= mlx5_health_init(dev
);
1291 goto err_health_init
;
1293 err
= mlx5_pagealloc_init(dev
);
1295 goto err_pagealloc_init
;
1300 mlx5_health_cleanup(dev
);
1302 debugfs_remove(dev
->priv
.dbg_root
);
1307 static void mlx5_mdev_uninit(struct mlx5_core_dev
*dev
)
1309 mlx5_pagealloc_cleanup(dev
);
1310 mlx5_health_cleanup(dev
);
1311 debugfs_remove_recursive(dev
->priv
.dbg_root
);
1314 #define MLX5_IB_MOD "mlx5_ib"
1315 static int init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1317 struct mlx5_core_dev
*dev
;
1318 struct devlink
*devlink
;
1321 devlink
= mlx5_devlink_alloc();
1323 dev_err(&pdev
->dev
, "devlink alloc failed\n");
1327 dev
= devlink_priv(devlink
);
1328 dev
->device
= &pdev
->dev
;
1331 dev
->coredev_type
= id
->driver_data
& MLX5_PCI_DEV_IS_VF
?
1332 MLX5_COREDEV_VF
: MLX5_COREDEV_PF
;
1334 err
= mlx5_mdev_init(dev
, prof_sel
);
1338 err
= mlx5_pci_init(dev
, pdev
, id
);
1340 mlx5_core_err(dev
, "mlx5_pci_init failed with error code %d\n",
1345 err
= mlx5_load_one(dev
, true);
1347 mlx5_core_err(dev
, "mlx5_load_one failed with error code %d\n",
1352 request_module_nowait(MLX5_IB_MOD
);
1354 err
= mlx5_devlink_register(devlink
, &pdev
->dev
);
1358 err
= mlx5_crdump_enable(dev
);
1360 dev_err(&pdev
->dev
, "mlx5_crdump_enable failed with error code %d\n", err
);
1362 pci_save_state(pdev
);
1366 mlx5_unload_one(dev
, true);
1369 mlx5_pci_close(dev
);
1371 mlx5_mdev_uninit(dev
);
1373 mlx5_devlink_free(devlink
);
1378 static void remove_one(struct pci_dev
*pdev
)
1380 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1381 struct devlink
*devlink
= priv_to_devlink(dev
);
1383 mlx5_crdump_disable(dev
);
1384 mlx5_devlink_unregister(devlink
);
1386 if (mlx5_unload_one(dev
, true)) {
1387 mlx5_core_err(dev
, "mlx5_unload_one failed\n");
1388 mlx5_health_flush(dev
);
1392 mlx5_pci_close(dev
);
1393 mlx5_mdev_uninit(dev
);
1394 mlx5_devlink_free(devlink
);
1397 static pci_ers_result_t
mlx5_pci_err_detected(struct pci_dev
*pdev
,
1398 pci_channel_state_t state
)
1400 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1402 mlx5_core_info(dev
, "%s was called\n", __func__
);
1404 mlx5_enter_error_state(dev
, false);
1405 mlx5_error_sw_reset(dev
);
1406 mlx5_unload_one(dev
, false);
1407 mlx5_drain_health_wq(dev
);
1408 mlx5_pci_disable_device(dev
);
1410 return state
== pci_channel_io_perm_failure
?
1411 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
1414 /* wait for the device to show vital signs by waiting
1415 * for the health counter to start counting.
1417 static int wait_vital(struct pci_dev
*pdev
)
1419 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1420 struct mlx5_core_health
*health
= &dev
->priv
.health
;
1421 const int niter
= 100;
1426 for (i
= 0; i
< niter
; i
++) {
1427 count
= ioread32be(health
->health_counter
);
1428 if (count
&& count
!= 0xffffffff) {
1429 if (last_count
&& last_count
!= count
) {
1431 "wait vital counter value 0x%x after %d iterations\n",
1443 static pci_ers_result_t
mlx5_pci_slot_reset(struct pci_dev
*pdev
)
1445 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1448 mlx5_core_info(dev
, "%s was called\n", __func__
);
1450 err
= mlx5_pci_enable_device(dev
);
1452 mlx5_core_err(dev
, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1454 return PCI_ERS_RESULT_DISCONNECT
;
1457 pci_set_master(pdev
);
1458 pci_restore_state(pdev
);
1459 pci_save_state(pdev
);
1461 if (wait_vital(pdev
)) {
1462 mlx5_core_err(dev
, "%s: wait_vital timed out\n", __func__
);
1463 return PCI_ERS_RESULT_DISCONNECT
;
1466 return PCI_ERS_RESULT_RECOVERED
;
1469 static void mlx5_pci_resume(struct pci_dev
*pdev
)
1471 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1474 mlx5_core_info(dev
, "%s was called\n", __func__
);
1476 err
= mlx5_load_one(dev
, false);
1478 mlx5_core_err(dev
, "%s: mlx5_load_one failed with error code: %d\n",
1481 mlx5_core_info(dev
, "%s: device recovered\n", __func__
);
1484 static const struct pci_error_handlers mlx5_err_handler
= {
1485 .error_detected
= mlx5_pci_err_detected
,
1486 .slot_reset
= mlx5_pci_slot_reset
,
1487 .resume
= mlx5_pci_resume
1490 static int mlx5_try_fast_unload(struct mlx5_core_dev
*dev
)
1492 bool fast_teardown
= false, force_teardown
= false;
1495 fast_teardown
= MLX5_CAP_GEN(dev
, fast_teardown
);
1496 force_teardown
= MLX5_CAP_GEN(dev
, force_teardown
);
1498 mlx5_core_dbg(dev
, "force teardown firmware support=%d\n", force_teardown
);
1499 mlx5_core_dbg(dev
, "fast teardown firmware support=%d\n", fast_teardown
);
1501 if (!fast_teardown
&& !force_teardown
)
1504 if (dev
->state
== MLX5_DEVICE_STATE_INTERNAL_ERROR
) {
1505 mlx5_core_dbg(dev
, "Device in internal error state, giving up\n");
1509 /* Panic tear down fw command will stop the PCI bus communication
1510 * with the HCA, so the health polll is no longer needed.
1512 mlx5_drain_health_wq(dev
);
1513 mlx5_stop_health_poll(dev
, false);
1515 ret
= mlx5_cmd_fast_teardown_hca(dev
);
1519 ret
= mlx5_cmd_force_teardown_hca(dev
);
1523 mlx5_core_dbg(dev
, "Firmware couldn't do fast unload error: %d\n", ret
);
1524 mlx5_start_health_poll(dev
);
1528 mlx5_enter_error_state(dev
, true);
1530 /* Some platforms requiring freeing the IRQ's in the shutdown
1531 * flow. If they aren't freed they can't be allocated after
1532 * kexec. There is no need to cleanup the mlx5_core software
1535 mlx5_core_eq_free_irqs(dev
);
1540 static void shutdown(struct pci_dev
*pdev
)
1542 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1545 mlx5_core_info(dev
, "Shutdown was called\n");
1546 err
= mlx5_try_fast_unload(dev
);
1548 mlx5_unload_one(dev
, false);
1549 mlx5_pci_disable_device(dev
);
1552 static const struct pci_device_id mlx5_core_pci_table
[] = {
1553 { PCI_VDEVICE(MELLANOX
, PCI_DEVICE_ID_MELLANOX_CONNECTIB
) },
1554 { PCI_VDEVICE(MELLANOX
, 0x1012), MLX5_PCI_DEV_IS_VF
}, /* Connect-IB VF */
1555 { PCI_VDEVICE(MELLANOX
, PCI_DEVICE_ID_MELLANOX_CONNECTX4
) },
1556 { PCI_VDEVICE(MELLANOX
, 0x1014), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-4 VF */
1557 { PCI_VDEVICE(MELLANOX
, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX
) },
1558 { PCI_VDEVICE(MELLANOX
, 0x1016), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-4LX VF */
1559 { PCI_VDEVICE(MELLANOX
, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1560 { PCI_VDEVICE(MELLANOX
, 0x1018), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-5 VF */
1561 { PCI_VDEVICE(MELLANOX
, 0x1019) }, /* ConnectX-5 Ex */
1562 { PCI_VDEVICE(MELLANOX
, 0x101a), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-5 Ex VF */
1563 { PCI_VDEVICE(MELLANOX
, 0x101b) }, /* ConnectX-6 */
1564 { PCI_VDEVICE(MELLANOX
, 0x101c), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-6 VF */
1565 { PCI_VDEVICE(MELLANOX
, 0x101d) }, /* ConnectX-6 Dx */
1566 { PCI_VDEVICE(MELLANOX
, 0x101e), MLX5_PCI_DEV_IS_VF
}, /* ConnectX Family mlx5Gen Virtual Function */
1567 { PCI_VDEVICE(MELLANOX
, 0x101f) }, /* ConnectX-6 LX */
1568 { PCI_VDEVICE(MELLANOX
, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1569 { PCI_VDEVICE(MELLANOX
, 0xa2d3), MLX5_PCI_DEV_IS_VF
}, /* BlueField integrated ConnectX-5 network controller VF */
1570 { PCI_VDEVICE(MELLANOX
, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1574 MODULE_DEVICE_TABLE(pci
, mlx5_core_pci_table
);
1576 void mlx5_disable_device(struct mlx5_core_dev
*dev
)
1578 mlx5_error_sw_reset(dev
);
1579 mlx5_unload_one(dev
, false);
1582 void mlx5_recover_device(struct mlx5_core_dev
*dev
)
1584 mlx5_pci_disable_device(dev
);
1585 if (mlx5_pci_slot_reset(dev
->pdev
) == PCI_ERS_RESULT_RECOVERED
)
1586 mlx5_pci_resume(dev
->pdev
);
1589 static struct pci_driver mlx5_core_driver
= {
1590 .name
= DRIVER_NAME
,
1591 .id_table
= mlx5_core_pci_table
,
1593 .remove
= remove_one
,
1594 .shutdown
= shutdown
,
1595 .err_handler
= &mlx5_err_handler
,
1596 .sriov_configure
= mlx5_core_sriov_configure
,
1599 static void mlx5_core_verify_params(void)
1601 if (prof_sel
>= ARRAY_SIZE(profile
)) {
1602 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1604 ARRAY_SIZE(profile
) - 1,
1606 prof_sel
= MLX5_DEFAULT_PROF
;
1610 static int __init
init(void)
1614 get_random_bytes(&sw_owner_id
, sizeof(sw_owner_id
));
1616 mlx5_core_verify_params();
1617 mlx5_accel_ipsec_build_fs_cmds();
1618 mlx5_register_debugfs();
1620 err
= pci_register_driver(&mlx5_core_driver
);
1624 #ifdef CONFIG_MLX5_CORE_EN
1631 mlx5_unregister_debugfs();
1635 static void __exit
cleanup(void)
1637 #ifdef CONFIG_MLX5_CORE_EN
1640 pci_unregister_driver(&mlx5_core_driver
);
1641 mlx5_unregister_debugfs();
1645 module_exit(cleanup
);