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Merge branch 'mlx5-next' into rdma.git for-next
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
52 #endif
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
55 #include "lib/eq.h"
56 #include "fs_core.h"
57 #include "lib/mpfs.h"
58 #include "eswitch.h"
59 #include "lib/mlx5.h"
60 #include "fpga/core.h"
61 #include "fpga/ipsec.h"
62 #include "accel/ipsec.h"
63 #include "accel/tls.h"
64 #include "lib/clock.h"
65 #include "lib/vxlan.h"
66 #include "lib/devcom.h"
67 #include "diag/fw_tracer.h"
68 #include "ecpf.h"
69
70 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
71 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
72 MODULE_LICENSE("Dual BSD/GPL");
73 MODULE_VERSION(DRIVER_VERSION);
74
75 unsigned int mlx5_core_debug_mask;
76 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
77 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
78
79 #define MLX5_DEFAULT_PROF 2
80 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
81 module_param_named(prof_sel, prof_sel, uint, 0444);
82 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
83
84 static u32 sw_owner_id[4];
85
86 enum {
87 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
88 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
89 };
90
91 static struct mlx5_profile profile[] = {
92 [0] = {
93 .mask = 0,
94 },
95 [1] = {
96 .mask = MLX5_PROF_MASK_QP_SIZE,
97 .log_max_qp = 12,
98 },
99 [2] = {
100 .mask = MLX5_PROF_MASK_QP_SIZE |
101 MLX5_PROF_MASK_MR_CACHE,
102 .log_max_qp = 18,
103 .mr_cache[0] = {
104 .size = 500,
105 .limit = 250
106 },
107 .mr_cache[1] = {
108 .size = 500,
109 .limit = 250
110 },
111 .mr_cache[2] = {
112 .size = 500,
113 .limit = 250
114 },
115 .mr_cache[3] = {
116 .size = 500,
117 .limit = 250
118 },
119 .mr_cache[4] = {
120 .size = 500,
121 .limit = 250
122 },
123 .mr_cache[5] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[6] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[7] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[8] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[9] = {
140 .size = 500,
141 .limit = 250
142 },
143 .mr_cache[10] = {
144 .size = 500,
145 .limit = 250
146 },
147 .mr_cache[11] = {
148 .size = 500,
149 .limit = 250
150 },
151 .mr_cache[12] = {
152 .size = 64,
153 .limit = 32
154 },
155 .mr_cache[13] = {
156 .size = 32,
157 .limit = 16
158 },
159 .mr_cache[14] = {
160 .size = 16,
161 .limit = 8
162 },
163 .mr_cache[15] = {
164 .size = 8,
165 .limit = 4
166 },
167 .mr_cache[16] = {
168 .size = 8,
169 .limit = 4
170 },
171 .mr_cache[17] = {
172 .size = 8,
173 .limit = 4
174 },
175 .mr_cache[18] = {
176 .size = 8,
177 .limit = 4
178 },
179 .mr_cache[19] = {
180 .size = 4,
181 .limit = 2
182 },
183 .mr_cache[20] = {
184 .size = 4,
185 .limit = 2
186 },
187 },
188 };
189
190 #define FW_INIT_TIMEOUT_MILI 2000
191 #define FW_INIT_WAIT_MS 2
192 #define FW_PRE_INIT_TIMEOUT_MILI 10000
193
194 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
195 {
196 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
197 int err = 0;
198
199 while (fw_initializing(dev)) {
200 if (time_after(jiffies, end)) {
201 err = -EBUSY;
202 break;
203 }
204 msleep(FW_INIT_WAIT_MS);
205 }
206
207 return err;
208 }
209
210 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
211 {
212 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
213 driver_version);
214 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
215 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
216 int remaining_size = driver_ver_sz;
217 char *string;
218
219 if (!MLX5_CAP_GEN(dev, driver_version))
220 return;
221
222 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
223
224 strncpy(string, "Linux", remaining_size);
225
226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
227 strncat(string, ",", remaining_size);
228
229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
230 strncat(string, DRIVER_NAME, remaining_size);
231
232 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
233 strncat(string, ",", remaining_size);
234
235 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
236 strncat(string, DRIVER_VERSION, remaining_size);
237
238 /*Send the command*/
239 MLX5_SET(set_driver_version_in, in, opcode,
240 MLX5_CMD_OP_SET_DRIVER_VERSION);
241
242 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
243 }
244
245 static int set_dma_caps(struct pci_dev *pdev)
246 {
247 int err;
248
249 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
250 if (err) {
251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
252 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
253 if (err) {
254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
255 return err;
256 }
257 }
258
259 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
260 if (err) {
261 dev_warn(&pdev->dev,
262 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
263 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
264 if (err) {
265 dev_err(&pdev->dev,
266 "Can't set consistent PCI DMA mask, aborting\n");
267 return err;
268 }
269 }
270
271 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
272 return err;
273 }
274
275 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
276 {
277 struct pci_dev *pdev = dev->pdev;
278 int err = 0;
279
280 mutex_lock(&dev->pci_status_mutex);
281 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
282 err = pci_enable_device(pdev);
283 if (!err)
284 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
285 }
286 mutex_unlock(&dev->pci_status_mutex);
287
288 return err;
289 }
290
291 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
292 {
293 struct pci_dev *pdev = dev->pdev;
294
295 mutex_lock(&dev->pci_status_mutex);
296 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
297 pci_disable_device(pdev);
298 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
299 }
300 mutex_unlock(&dev->pci_status_mutex);
301 }
302
303 static int request_bar(struct pci_dev *pdev)
304 {
305 int err = 0;
306
307 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
308 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
309 return -ENODEV;
310 }
311
312 err = pci_request_regions(pdev, DRIVER_NAME);
313 if (err)
314 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
315
316 return err;
317 }
318
319 static void release_bar(struct pci_dev *pdev)
320 {
321 pci_release_regions(pdev);
322 }
323
324 struct mlx5_reg_host_endianness {
325 u8 he;
326 u8 rsvd[15];
327 };
328
329 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
330
331 enum {
332 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
333 MLX5_DEV_CAP_FLAG_DCT,
334 };
335
336 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
337 {
338 switch (size) {
339 case 128:
340 return 0;
341 case 256:
342 return 1;
343 case 512:
344 return 2;
345 case 1024:
346 return 3;
347 case 2048:
348 return 4;
349 case 4096:
350 return 5;
351 default:
352 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
353 return 0;
354 }
355 }
356
357 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
358 enum mlx5_cap_type cap_type,
359 enum mlx5_cap_mode cap_mode)
360 {
361 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
362 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
363 void *out, *hca_caps;
364 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
365 int err;
366
367 memset(in, 0, sizeof(in));
368 out = kzalloc(out_sz, GFP_KERNEL);
369 if (!out)
370 return -ENOMEM;
371
372 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
373 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
374 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
375 if (err) {
376 mlx5_core_warn(dev,
377 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
378 cap_type, cap_mode, err);
379 goto query_ex;
380 }
381
382 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
383
384 switch (cap_mode) {
385 case HCA_CAP_OPMOD_GET_MAX:
386 memcpy(dev->caps.hca_max[cap_type], hca_caps,
387 MLX5_UN_SZ_BYTES(hca_cap_union));
388 break;
389 case HCA_CAP_OPMOD_GET_CUR:
390 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
391 MLX5_UN_SZ_BYTES(hca_cap_union));
392 break;
393 default:
394 mlx5_core_warn(dev,
395 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
396 cap_type, cap_mode);
397 err = -EINVAL;
398 break;
399 }
400 query_ex:
401 kfree(out);
402 return err;
403 }
404
405 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
406 {
407 int ret;
408
409 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
410 if (ret)
411 return ret;
412 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
413 }
414
415 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
416 {
417 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
418
419 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
420 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
421 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
422 }
423
424 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
425 {
426 void *set_ctx;
427 void *set_hca_cap;
428 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
429 int req_endianness;
430 int err;
431
432 if (MLX5_CAP_GEN(dev, atomic)) {
433 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
434 if (err)
435 return err;
436 } else {
437 return 0;
438 }
439
440 req_endianness =
441 MLX5_CAP_ATOMIC(dev,
442 supported_atomic_req_8B_endianness_mode_1);
443
444 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
445 return 0;
446
447 set_ctx = kzalloc(set_sz, GFP_KERNEL);
448 if (!set_ctx)
449 return -ENOMEM;
450
451 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
452
453 /* Set requestor to host endianness */
454 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
455 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
456
457 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
458
459 kfree(set_ctx);
460 return err;
461 }
462
463 static int handle_hca_cap_odp(struct mlx5_core_dev *dev)
464 {
465 void *set_hca_cap;
466 void *set_ctx;
467 int set_sz;
468 bool do_set = false;
469 int err;
470
471 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
472 !MLX5_CAP_GEN(dev, pg))
473 return 0;
474
475 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
476 if (err)
477 return err;
478
479 set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
480 set_ctx = kzalloc(set_sz, GFP_KERNEL);
481 if (!set_ctx)
482 return -ENOMEM;
483
484 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
485 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP],
486 MLX5_ST_SZ_BYTES(odp_cap));
487
488 #define ODP_CAP_SET_MAX(dev, field) \
489 do { \
490 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
491 if (_res) { \
492 do_set = true; \
493 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
494 } \
495 } while (0)
496
497 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
498 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
499 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
500 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
501 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
502 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
503 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
504 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
505
506 if (do_set)
507 err = set_caps(dev, set_ctx, set_sz,
508 MLX5_SET_HCA_CAP_OP_MOD_ODP);
509
510 kfree(set_ctx);
511
512 return err;
513 }
514
515 static int handle_hca_cap(struct mlx5_core_dev *dev)
516 {
517 void *set_ctx = NULL;
518 struct mlx5_profile *prof = dev->profile;
519 int err = -ENOMEM;
520 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
521 void *set_hca_cap;
522
523 set_ctx = kzalloc(set_sz, GFP_KERNEL);
524 if (!set_ctx)
525 goto query_ex;
526
527 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
528 if (err)
529 goto query_ex;
530
531 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
532 capability);
533 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
534 MLX5_ST_SZ_BYTES(cmd_hca_cap));
535
536 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
537 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
538 128);
539 /* we limit the size of the pkey table to 128 entries for now */
540 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
541 to_fw_pkey_sz(dev, 128));
542
543 /* Check log_max_qp from HCA caps to set in current profile */
544 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
545 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
546 profile[prof_sel].log_max_qp,
547 MLX5_CAP_GEN_MAX(dev, log_max_qp));
548 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
549 }
550 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
551 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
552 prof->log_max_qp);
553
554 /* disable cmdif checksum */
555 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
556
557 /* Enable 4K UAR only when HCA supports it and page size is bigger
558 * than 4K.
559 */
560 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
561 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
562
563 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
564
565 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
566 MLX5_SET(cmd_hca_cap,
567 set_hca_cap,
568 cache_line_128byte,
569 cache_line_size() >= 128 ? 1 : 0);
570
571 if (MLX5_CAP_GEN_MAX(dev, dct))
572 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
573
574 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
575 MLX5_SET(cmd_hca_cap,
576 set_hca_cap,
577 num_vhca_ports,
578 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
579
580 err = set_caps(dev, set_ctx, set_sz,
581 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
582
583 query_ex:
584 kfree(set_ctx);
585 return err;
586 }
587
588 static int set_hca_cap(struct mlx5_core_dev *dev)
589 {
590 int err;
591
592 err = handle_hca_cap(dev);
593 if (err) {
594 mlx5_core_err(dev, "handle_hca_cap failed\n");
595 goto out;
596 }
597
598 err = handle_hca_cap_atomic(dev);
599 if (err) {
600 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
601 goto out;
602 }
603
604 err = handle_hca_cap_odp(dev);
605 if (err) {
606 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
607 goto out;
608 }
609
610 out:
611 return err;
612 }
613
614 static int set_hca_ctrl(struct mlx5_core_dev *dev)
615 {
616 struct mlx5_reg_host_endianness he_in;
617 struct mlx5_reg_host_endianness he_out;
618 int err;
619
620 if (!mlx5_core_is_pf(dev))
621 return 0;
622
623 memset(&he_in, 0, sizeof(he_in));
624 he_in.he = MLX5_SET_HOST_ENDIANNESS;
625 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
626 &he_out, sizeof(he_out),
627 MLX5_REG_HOST_ENDIANNESS, 0, 1);
628 return err;
629 }
630
631 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
632 {
633 int ret = 0;
634
635 /* Disable local_lb by default */
636 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
637 ret = mlx5_nic_vport_update_local_lb(dev, false);
638
639 return ret;
640 }
641
642 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
643 {
644 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
645 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
646
647 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
648 MLX5_SET(enable_hca_in, in, function_id, func_id);
649 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
650 dev->caps.embedded_cpu);
651 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
652 }
653
654 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
655 {
656 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
657 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
658
659 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
660 MLX5_SET(disable_hca_in, in, function_id, func_id);
661 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
662 dev->caps.embedded_cpu);
663 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
664 }
665
666 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
667 struct ptp_system_timestamp *sts)
668 {
669 u32 timer_h, timer_h1, timer_l;
670
671 timer_h = ioread32be(&dev->iseg->internal_timer_h);
672 ptp_read_system_prets(sts);
673 timer_l = ioread32be(&dev->iseg->internal_timer_l);
674 ptp_read_system_postts(sts);
675 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
676 if (timer_h != timer_h1) {
677 /* wrap around */
678 ptp_read_system_prets(sts);
679 timer_l = ioread32be(&dev->iseg->internal_timer_l);
680 ptp_read_system_postts(sts);
681 }
682
683 return (u64)timer_l | (u64)timer_h1 << 32;
684 }
685
686 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
687 {
688 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
689 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
690 u32 sup_issi;
691 int err;
692
693 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
694 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
695 query_out, sizeof(query_out));
696 if (err) {
697 u32 syndrome;
698 u8 status;
699
700 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
701 if (!status || syndrome == MLX5_DRIVER_SYND) {
702 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
703 err, status, syndrome);
704 return err;
705 }
706
707 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
708 dev->issi = 0;
709 return 0;
710 }
711
712 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
713
714 if (sup_issi & (1 << 1)) {
715 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
716 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
717
718 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
719 MLX5_SET(set_issi_in, set_in, current_issi, 1);
720 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
721 set_out, sizeof(set_out));
722 if (err) {
723 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
724 err);
725 return err;
726 }
727
728 dev->issi = 1;
729
730 return 0;
731 } else if (sup_issi & (1 << 0) || !sup_issi) {
732 return 0;
733 }
734
735 return -EOPNOTSUPP;
736 }
737
738 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
739 const struct pci_device_id *id)
740 {
741 struct mlx5_priv *priv = &dev->priv;
742 int err = 0;
743
744 dev->pdev = pdev;
745 priv->pci_dev_data = id->driver_data;
746
747 pci_set_drvdata(dev->pdev, dev);
748
749 dev->bar_addr = pci_resource_start(pdev, 0);
750 priv->numa_node = dev_to_node(&dev->pdev->dev);
751
752 err = mlx5_pci_enable_device(dev);
753 if (err) {
754 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
755 return err;
756 }
757
758 err = request_bar(pdev);
759 if (err) {
760 mlx5_core_err(dev, "error requesting BARs, aborting\n");
761 goto err_disable;
762 }
763
764 pci_set_master(pdev);
765
766 err = set_dma_caps(pdev);
767 if (err) {
768 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
769 goto err_clr_master;
770 }
771
772 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
773 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
774 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
775 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
776
777 dev->iseg_base = dev->bar_addr;
778 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
779 if (!dev->iseg) {
780 err = -ENOMEM;
781 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
782 goto err_clr_master;
783 }
784
785 return 0;
786
787 err_clr_master:
788 pci_clear_master(dev->pdev);
789 release_bar(dev->pdev);
790 err_disable:
791 mlx5_pci_disable_device(dev);
792 return err;
793 }
794
795 static void mlx5_pci_close(struct mlx5_core_dev *dev)
796 {
797 iounmap(dev->iseg);
798 pci_clear_master(dev->pdev);
799 release_bar(dev->pdev);
800 mlx5_pci_disable_device(dev);
801 }
802
803 static int mlx5_init_once(struct mlx5_core_dev *dev)
804 {
805 int err;
806
807 dev->priv.devcom = mlx5_devcom_register_device(dev);
808 if (IS_ERR(dev->priv.devcom))
809 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
810 dev->priv.devcom);
811
812 err = mlx5_query_board_id(dev);
813 if (err) {
814 mlx5_core_err(dev, "query board id failed\n");
815 goto err_devcom;
816 }
817
818 err = mlx5_eq_table_init(dev);
819 if (err) {
820 mlx5_core_err(dev, "failed to initialize eq\n");
821 goto err_devcom;
822 }
823
824 err = mlx5_events_init(dev);
825 if (err) {
826 mlx5_core_err(dev, "failed to initialize events\n");
827 goto err_eq_cleanup;
828 }
829
830 err = mlx5_cq_debugfs_init(dev);
831 if (err) {
832 mlx5_core_err(dev, "failed to initialize cq debugfs\n");
833 goto err_events_cleanup;
834 }
835
836 mlx5_init_qp_table(dev);
837
838 mlx5_init_mkey_table(dev);
839
840 mlx5_init_reserved_gids(dev);
841
842 mlx5_init_clock(dev);
843
844 dev->vxlan = mlx5_vxlan_create(dev);
845
846 err = mlx5_init_rl_table(dev);
847 if (err) {
848 mlx5_core_err(dev, "Failed to init rate limiting\n");
849 goto err_tables_cleanup;
850 }
851
852 err = mlx5_mpfs_init(dev);
853 if (err) {
854 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
855 goto err_rl_cleanup;
856 }
857
858 err = mlx5_eswitch_init(dev);
859 if (err) {
860 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
861 goto err_mpfs_cleanup;
862 }
863
864 err = mlx5_sriov_init(dev);
865 if (err) {
866 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
867 goto err_eswitch_cleanup;
868 }
869
870 err = mlx5_fpga_init(dev);
871 if (err) {
872 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
873 goto err_sriov_cleanup;
874 }
875
876 dev->tracer = mlx5_fw_tracer_create(dev);
877
878 return 0;
879
880 err_sriov_cleanup:
881 mlx5_sriov_cleanup(dev);
882 err_eswitch_cleanup:
883 mlx5_eswitch_cleanup(dev->priv.eswitch);
884 err_mpfs_cleanup:
885 mlx5_mpfs_cleanup(dev);
886 err_rl_cleanup:
887 mlx5_cleanup_rl_table(dev);
888 err_tables_cleanup:
889 mlx5_vxlan_destroy(dev->vxlan);
890 mlx5_cleanup_mkey_table(dev);
891 mlx5_cleanup_qp_table(dev);
892 mlx5_cq_debugfs_cleanup(dev);
893 err_events_cleanup:
894 mlx5_events_cleanup(dev);
895 err_eq_cleanup:
896 mlx5_eq_table_cleanup(dev);
897 err_devcom:
898 mlx5_devcom_unregister_device(dev->priv.devcom);
899
900 return err;
901 }
902
903 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
904 {
905 mlx5_fw_tracer_destroy(dev->tracer);
906 mlx5_fpga_cleanup(dev);
907 mlx5_sriov_cleanup(dev);
908 mlx5_eswitch_cleanup(dev->priv.eswitch);
909 mlx5_mpfs_cleanup(dev);
910 mlx5_cleanup_rl_table(dev);
911 mlx5_vxlan_destroy(dev->vxlan);
912 mlx5_cleanup_clock(dev);
913 mlx5_cleanup_reserved_gids(dev);
914 mlx5_cleanup_mkey_table(dev);
915 mlx5_cleanup_qp_table(dev);
916 mlx5_cq_debugfs_cleanup(dev);
917 mlx5_events_cleanup(dev);
918 mlx5_eq_table_cleanup(dev);
919 mlx5_devcom_unregister_device(dev->priv.devcom);
920 }
921
922 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
923 {
924 int err;
925
926 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
927 fw_rev_min(dev), fw_rev_sub(dev));
928
929 /* Only PFs hold the relevant PCIe information for this query */
930 if (mlx5_core_is_pf(dev))
931 pcie_print_link_status(dev->pdev);
932
933 /* wait for firmware to accept initialization segments configurations
934 */
935 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
936 if (err) {
937 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n",
938 FW_PRE_INIT_TIMEOUT_MILI);
939 return err;
940 }
941
942 err = mlx5_cmd_init(dev);
943 if (err) {
944 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
945 return err;
946 }
947
948 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
949 if (err) {
950 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n",
951 FW_INIT_TIMEOUT_MILI);
952 goto err_cmd_cleanup;
953 }
954
955 err = mlx5_core_enable_hca(dev, 0);
956 if (err) {
957 mlx5_core_err(dev, "enable hca failed\n");
958 goto err_cmd_cleanup;
959 }
960
961 err = mlx5_core_set_issi(dev);
962 if (err) {
963 mlx5_core_err(dev, "failed to set issi\n");
964 goto err_disable_hca;
965 }
966
967 err = mlx5_satisfy_startup_pages(dev, 1);
968 if (err) {
969 mlx5_core_err(dev, "failed to allocate boot pages\n");
970 goto err_disable_hca;
971 }
972
973 err = set_hca_ctrl(dev);
974 if (err) {
975 mlx5_core_err(dev, "set_hca_ctrl failed\n");
976 goto reclaim_boot_pages;
977 }
978
979 err = set_hca_cap(dev);
980 if (err) {
981 mlx5_core_err(dev, "set_hca_cap failed\n");
982 goto reclaim_boot_pages;
983 }
984
985 err = mlx5_satisfy_startup_pages(dev, 0);
986 if (err) {
987 mlx5_core_err(dev, "failed to allocate init pages\n");
988 goto reclaim_boot_pages;
989 }
990
991 err = mlx5_cmd_init_hca(dev, sw_owner_id);
992 if (err) {
993 mlx5_core_err(dev, "init hca failed\n");
994 goto reclaim_boot_pages;
995 }
996
997 mlx5_set_driver_version(dev);
998
999 mlx5_start_health_poll(dev);
1000
1001 err = mlx5_query_hca_caps(dev);
1002 if (err) {
1003 mlx5_core_err(dev, "query hca failed\n");
1004 goto stop_health;
1005 }
1006
1007 return 0;
1008
1009 stop_health:
1010 mlx5_stop_health_poll(dev, boot);
1011 reclaim_boot_pages:
1012 mlx5_reclaim_startup_pages(dev);
1013 err_disable_hca:
1014 mlx5_core_disable_hca(dev, 0);
1015 err_cmd_cleanup:
1016 mlx5_cmd_cleanup(dev);
1017
1018 return err;
1019 }
1020
1021 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1022 {
1023 int err;
1024
1025 mlx5_stop_health_poll(dev, boot);
1026 err = mlx5_cmd_teardown_hca(dev);
1027 if (err) {
1028 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1029 return err;
1030 }
1031 mlx5_reclaim_startup_pages(dev);
1032 mlx5_core_disable_hca(dev, 0);
1033 mlx5_cmd_cleanup(dev);
1034
1035 return 0;
1036 }
1037
1038 static int mlx5_load(struct mlx5_core_dev *dev)
1039 {
1040 int err;
1041
1042 dev->priv.uar = mlx5_get_uars_page(dev);
1043 if (IS_ERR(dev->priv.uar)) {
1044 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1045 err = PTR_ERR(dev->priv.uar);
1046 return err;
1047 }
1048
1049 mlx5_events_start(dev);
1050 mlx5_pagealloc_start(dev);
1051
1052 err = mlx5_eq_table_create(dev);
1053 if (err) {
1054 mlx5_core_err(dev, "Failed to create EQs\n");
1055 goto err_eq_table;
1056 }
1057
1058 err = mlx5_fw_tracer_init(dev->tracer);
1059 if (err) {
1060 mlx5_core_err(dev, "Failed to init FW tracer\n");
1061 goto err_fw_tracer;
1062 }
1063
1064 err = mlx5_fpga_device_start(dev);
1065 if (err) {
1066 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1067 goto err_fpga_start;
1068 }
1069
1070 err = mlx5_accel_ipsec_init(dev);
1071 if (err) {
1072 mlx5_core_err(dev, "IPSec device start failed %d\n", err);
1073 goto err_ipsec_start;
1074 }
1075
1076 err = mlx5_accel_tls_init(dev);
1077 if (err) {
1078 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1079 goto err_tls_start;
1080 }
1081
1082 err = mlx5_init_fs(dev);
1083 if (err) {
1084 mlx5_core_err(dev, "Failed to init flow steering\n");
1085 goto err_fs;
1086 }
1087
1088 err = mlx5_core_set_hca_defaults(dev);
1089 if (err) {
1090 mlx5_core_err(dev, "Failed to set hca defaults\n");
1091 goto err_fs;
1092 }
1093
1094 err = mlx5_sriov_attach(dev);
1095 if (err) {
1096 mlx5_core_err(dev, "sriov init failed %d\n", err);
1097 goto err_sriov;
1098 }
1099
1100 err = mlx5_ec_init(dev);
1101 if (err) {
1102 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1103 goto err_ec;
1104 }
1105
1106 return 0;
1107
1108 err_ec:
1109 mlx5_sriov_detach(dev);
1110 err_sriov:
1111 mlx5_cleanup_fs(dev);
1112 err_fs:
1113 mlx5_accel_tls_cleanup(dev);
1114 err_tls_start:
1115 mlx5_accel_ipsec_cleanup(dev);
1116 err_ipsec_start:
1117 mlx5_fpga_device_stop(dev);
1118 err_fpga_start:
1119 mlx5_fw_tracer_cleanup(dev->tracer);
1120 err_fw_tracer:
1121 mlx5_eq_table_destroy(dev);
1122 err_eq_table:
1123 mlx5_pagealloc_stop(dev);
1124 mlx5_events_stop(dev);
1125 mlx5_put_uars_page(dev, dev->priv.uar);
1126 return err;
1127 }
1128
1129 static void mlx5_unload(struct mlx5_core_dev *dev)
1130 {
1131 mlx5_ec_cleanup(dev);
1132 mlx5_sriov_detach(dev);
1133 mlx5_cleanup_fs(dev);
1134 mlx5_accel_ipsec_cleanup(dev);
1135 mlx5_accel_tls_cleanup(dev);
1136 mlx5_fpga_device_stop(dev);
1137 mlx5_fw_tracer_cleanup(dev->tracer);
1138 mlx5_eq_table_destroy(dev);
1139 mlx5_pagealloc_stop(dev);
1140 mlx5_events_stop(dev);
1141 mlx5_put_uars_page(dev, dev->priv.uar);
1142 }
1143
1144 static int mlx5_load_one(struct mlx5_core_dev *dev, bool boot)
1145 {
1146 int err = 0;
1147
1148 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
1149 mutex_lock(&dev->intf_state_mutex);
1150 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1151 mlx5_core_warn(dev, "interface is up, NOP\n");
1152 goto out;
1153 }
1154 /* remove any previous indication of internal error */
1155 dev->state = MLX5_DEVICE_STATE_UP;
1156
1157 err = mlx5_function_setup(dev, boot);
1158 if (err)
1159 goto out;
1160
1161 if (boot) {
1162 err = mlx5_init_once(dev);
1163 if (err) {
1164 mlx5_core_err(dev, "sw objs init failed\n");
1165 goto function_teardown;
1166 }
1167 }
1168
1169 err = mlx5_load(dev);
1170 if (err)
1171 goto err_load;
1172
1173 if (mlx5_device_registered(dev)) {
1174 mlx5_attach_device(dev);
1175 } else {
1176 err = mlx5_register_device(dev);
1177 if (err) {
1178 mlx5_core_err(dev, "register device failed %d\n", err);
1179 goto err_reg_dev;
1180 }
1181 }
1182
1183 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1184 out:
1185 mutex_unlock(&dev->intf_state_mutex);
1186
1187 return err;
1188
1189 err_reg_dev:
1190 mlx5_unload(dev);
1191 err_load:
1192 if (boot)
1193 mlx5_cleanup_once(dev);
1194 function_teardown:
1195 mlx5_function_teardown(dev, boot);
1196 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1197 mutex_unlock(&dev->intf_state_mutex);
1198
1199 return err;
1200 }
1201
1202 static int mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup)
1203 {
1204 int err = 0;
1205
1206 if (cleanup)
1207 mlx5_drain_health_recovery(dev);
1208
1209 mutex_lock(&dev->intf_state_mutex);
1210 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1211 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1212 __func__);
1213 if (cleanup)
1214 mlx5_cleanup_once(dev);
1215 goto out;
1216 }
1217
1218 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1219
1220 if (mlx5_device_registered(dev))
1221 mlx5_detach_device(dev);
1222
1223 mlx5_unload(dev);
1224
1225 if (cleanup)
1226 mlx5_cleanup_once(dev);
1227
1228 mlx5_function_teardown(dev, cleanup);
1229 out:
1230 mutex_unlock(&dev->intf_state_mutex);
1231 return err;
1232 }
1233
1234 static const struct devlink_ops mlx5_devlink_ops = {
1235 #ifdef CONFIG_MLX5_ESWITCH
1236 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1237 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1238 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1239 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
1240 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1241 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
1242 #endif
1243 };
1244
1245 static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx, const char *name)
1246 {
1247 struct mlx5_priv *priv = &dev->priv;
1248 int err;
1249
1250 strncpy(priv->name, name, MLX5_MAX_NAME_LEN);
1251 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
1252
1253 dev->profile = &profile[profile_idx];
1254
1255 INIT_LIST_HEAD(&priv->ctx_list);
1256 spin_lock_init(&priv->ctx_lock);
1257 mutex_init(&dev->pci_status_mutex);
1258 mutex_init(&dev->intf_state_mutex);
1259
1260 mutex_init(&priv->bfregs.reg_head.lock);
1261 mutex_init(&priv->bfregs.wc_head.lock);
1262 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1263 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1264
1265 mutex_init(&priv->alloc_mutex);
1266 mutex_init(&priv->pgdir_mutex);
1267 INIT_LIST_HEAD(&priv->pgdir_list);
1268 spin_lock_init(&priv->mkey_lock);
1269
1270 priv->dbg_root = debugfs_create_dir(name, mlx5_debugfs_root);
1271 if (!priv->dbg_root) {
1272 pr_err("mlx5_core: %s error, Cannot create debugfs dir, aborting\n", name);
1273 return -ENOMEM;
1274 }
1275
1276 err = mlx5_health_init(dev);
1277 if (err)
1278 goto err_health_init;
1279
1280 err = mlx5_pagealloc_init(dev);
1281 if (err)
1282 goto err_pagealloc_init;
1283
1284 return 0;
1285
1286 err_pagealloc_init:
1287 mlx5_health_cleanup(dev);
1288 err_health_init:
1289 debugfs_remove(dev->priv.dbg_root);
1290
1291 return err;
1292 }
1293
1294 static void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1295 {
1296 mlx5_pagealloc_cleanup(dev);
1297 mlx5_health_cleanup(dev);
1298 debugfs_remove_recursive(dev->priv.dbg_root);
1299 }
1300
1301 #define MLX5_IB_MOD "mlx5_ib"
1302 static int init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1303 {
1304 struct mlx5_core_dev *dev;
1305 struct devlink *devlink;
1306 int err;
1307
1308 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1309 if (!devlink) {
1310 dev_err(&pdev->dev, "kzalloc failed\n");
1311 return -ENOMEM;
1312 }
1313
1314 dev = devlink_priv(devlink);
1315
1316 err = mlx5_mdev_init(dev, prof_sel, dev_name(&pdev->dev));
1317 if (err)
1318 goto mdev_init_err;
1319
1320 err = mlx5_pci_init(dev, pdev, id);
1321 if (err) {
1322 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1323 err);
1324 goto pci_init_err;
1325 }
1326
1327 err = mlx5_load_one(dev, true);
1328 if (err) {
1329 mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n",
1330 err);
1331 goto err_load_one;
1332 }
1333
1334 request_module_nowait(MLX5_IB_MOD);
1335
1336 err = devlink_register(devlink, &pdev->dev);
1337 if (err)
1338 goto clean_load;
1339
1340 pci_save_state(pdev);
1341 return 0;
1342
1343 clean_load:
1344 mlx5_unload_one(dev, true);
1345
1346 err_load_one:
1347 mlx5_pci_close(dev);
1348 pci_init_err:
1349 mlx5_mdev_uninit(dev);
1350 mdev_init_err:
1351 devlink_free(devlink);
1352
1353 return err;
1354 }
1355
1356 static void remove_one(struct pci_dev *pdev)
1357 {
1358 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1359 struct devlink *devlink = priv_to_devlink(dev);
1360
1361 devlink_unregister(devlink);
1362 mlx5_unregister_device(dev);
1363
1364 if (mlx5_unload_one(dev, true)) {
1365 mlx5_core_err(dev, "mlx5_unload_one failed\n");
1366 mlx5_health_flush(dev);
1367 return;
1368 }
1369
1370 mlx5_pci_close(dev);
1371 mlx5_mdev_uninit(dev);
1372 devlink_free(devlink);
1373 }
1374
1375 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1376 pci_channel_state_t state)
1377 {
1378 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1379
1380 mlx5_core_info(dev, "%s was called\n", __func__);
1381
1382 mlx5_enter_error_state(dev, false);
1383 mlx5_unload_one(dev, false);
1384 /* In case of kernel call drain the health wq */
1385 if (state) {
1386 mlx5_drain_health_wq(dev);
1387 mlx5_pci_disable_device(dev);
1388 }
1389
1390 return state == pci_channel_io_perm_failure ?
1391 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1392 }
1393
1394 /* wait for the device to show vital signs by waiting
1395 * for the health counter to start counting.
1396 */
1397 static int wait_vital(struct pci_dev *pdev)
1398 {
1399 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1400 struct mlx5_core_health *health = &dev->priv.health;
1401 const int niter = 100;
1402 u32 last_count = 0;
1403 u32 count;
1404 int i;
1405
1406 for (i = 0; i < niter; i++) {
1407 count = ioread32be(health->health_counter);
1408 if (count && count != 0xffffffff) {
1409 if (last_count && last_count != count) {
1410 mlx5_core_info(dev,
1411 "wait vital counter value 0x%x after %d iterations\n",
1412 count, i);
1413 return 0;
1414 }
1415 last_count = count;
1416 }
1417 msleep(50);
1418 }
1419
1420 return -ETIMEDOUT;
1421 }
1422
1423 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1424 {
1425 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1426 int err;
1427
1428 mlx5_core_info(dev, "%s was called\n", __func__);
1429
1430 err = mlx5_pci_enable_device(dev);
1431 if (err) {
1432 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1433 __func__, err);
1434 return PCI_ERS_RESULT_DISCONNECT;
1435 }
1436
1437 pci_set_master(pdev);
1438 pci_restore_state(pdev);
1439 pci_save_state(pdev);
1440
1441 if (wait_vital(pdev)) {
1442 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__);
1443 return PCI_ERS_RESULT_DISCONNECT;
1444 }
1445
1446 return PCI_ERS_RESULT_RECOVERED;
1447 }
1448
1449 static void mlx5_pci_resume(struct pci_dev *pdev)
1450 {
1451 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1452 int err;
1453
1454 mlx5_core_info(dev, "%s was called\n", __func__);
1455
1456 err = mlx5_load_one(dev, false);
1457 if (err)
1458 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n",
1459 __func__, err);
1460 else
1461 mlx5_core_info(dev, "%s: device recovered\n", __func__);
1462 }
1463
1464 static const struct pci_error_handlers mlx5_err_handler = {
1465 .error_detected = mlx5_pci_err_detected,
1466 .slot_reset = mlx5_pci_slot_reset,
1467 .resume = mlx5_pci_resume
1468 };
1469
1470 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1471 {
1472 bool fast_teardown = false, force_teardown = false;
1473 int ret = 1;
1474
1475 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1476 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1477
1478 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1479 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1480
1481 if (!fast_teardown && !force_teardown)
1482 return -EOPNOTSUPP;
1483
1484 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1485 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1486 return -EAGAIN;
1487 }
1488
1489 /* Panic tear down fw command will stop the PCI bus communication
1490 * with the HCA, so the health polll is no longer needed.
1491 */
1492 mlx5_drain_health_wq(dev);
1493 mlx5_stop_health_poll(dev, false);
1494
1495 ret = mlx5_cmd_fast_teardown_hca(dev);
1496 if (!ret)
1497 goto succeed;
1498
1499 ret = mlx5_cmd_force_teardown_hca(dev);
1500 if (!ret)
1501 goto succeed;
1502
1503 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1504 mlx5_start_health_poll(dev);
1505 return ret;
1506
1507 succeed:
1508 mlx5_enter_error_state(dev, true);
1509
1510 /* Some platforms requiring freeing the IRQ's in the shutdown
1511 * flow. If they aren't freed they can't be allocated after
1512 * kexec. There is no need to cleanup the mlx5_core software
1513 * contexts.
1514 */
1515 mlx5_core_eq_free_irqs(dev);
1516
1517 return 0;
1518 }
1519
1520 static void shutdown(struct pci_dev *pdev)
1521 {
1522 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1523 int err;
1524
1525 mlx5_core_info(dev, "Shutdown was called\n");
1526 err = mlx5_try_fast_unload(dev);
1527 if (err)
1528 mlx5_unload_one(dev, false);
1529 mlx5_pci_disable_device(dev);
1530 }
1531
1532 static const struct pci_device_id mlx5_core_pci_table[] = {
1533 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1534 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1535 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1536 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1537 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1538 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1539 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1540 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1541 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1542 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1543 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1544 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1545 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1546 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1547 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1548 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1549 { 0, }
1550 };
1551
1552 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1553
1554 void mlx5_disable_device(struct mlx5_core_dev *dev)
1555 {
1556 mlx5_pci_err_detected(dev->pdev, 0);
1557 }
1558
1559 void mlx5_recover_device(struct mlx5_core_dev *dev)
1560 {
1561 mlx5_pci_disable_device(dev);
1562 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1563 mlx5_pci_resume(dev->pdev);
1564 }
1565
1566 static struct pci_driver mlx5_core_driver = {
1567 .name = DRIVER_NAME,
1568 .id_table = mlx5_core_pci_table,
1569 .probe = init_one,
1570 .remove = remove_one,
1571 .shutdown = shutdown,
1572 .err_handler = &mlx5_err_handler,
1573 .sriov_configure = mlx5_core_sriov_configure,
1574 };
1575
1576 static void mlx5_core_verify_params(void)
1577 {
1578 if (prof_sel >= ARRAY_SIZE(profile)) {
1579 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1580 prof_sel,
1581 ARRAY_SIZE(profile) - 1,
1582 MLX5_DEFAULT_PROF);
1583 prof_sel = MLX5_DEFAULT_PROF;
1584 }
1585 }
1586
1587 static int __init init(void)
1588 {
1589 int err;
1590
1591 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1592
1593 mlx5_core_verify_params();
1594 mlx5_fpga_ipsec_build_fs_cmds();
1595 mlx5_register_debugfs();
1596
1597 err = pci_register_driver(&mlx5_core_driver);
1598 if (err)
1599 goto err_debug;
1600
1601 #ifdef CONFIG_MLX5_CORE_EN
1602 mlx5e_init();
1603 #endif
1604
1605 return 0;
1606
1607 err_debug:
1608 mlx5_unregister_debugfs();
1609 return err;
1610 }
1611
1612 static void __exit cleanup(void)
1613 {
1614 #ifdef CONFIG_MLX5_CORE_EN
1615 mlx5e_cleanup();
1616 #endif
1617 pci_unregister_driver(&mlx5_core_driver);
1618 mlx5_unregister_debugfs();
1619 }
1620
1621 module_init(init);
1622 module_exit(cleanup);
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