drivers/net/ethernet/mellanox/mlx5/core/port.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <linux/mlx5/driver.h>
  35 #include <linux/mlx5/port.h>
  36 #include <linux/mlx5/cmd.h>
  37 #include "mlx5_core.h"
  38
  39 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
  40                          int size_in, void *data_out, int size_out,
  41                          u16 reg_num, int arg, int write)
  42 {
  43         struct mlx5_access_reg_mbox_in *in = NULL;
  44         struct mlx5_access_reg_mbox_out *out = NULL;
  45         int err = -ENOMEM;
  46
  47         in = mlx5_vzalloc(sizeof(*in) + size_in);
  48         if (!in)
  49                 return -ENOMEM;
  50
  51         out = mlx5_vzalloc(sizeof(*out) + size_out);
  52         if (!out)
  53                 goto ex1;
  54
  55         memcpy(in->data, data_in, size_in);
  56         in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
  57         in->hdr.opmod = cpu_to_be16(!write);
  58         in->arg = cpu_to_be32(arg);
  59         in->register_id = cpu_to_be16(reg_num);
  60         err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
  61                             sizeof(*out) + size_out);
  62         if (err)
  63                 goto ex2;
  64
  65         if (out->hdr.status)
  66                 err = mlx5_cmd_status_to_err(&out->hdr);
  67
  68         if (!err)
  69                 memcpy(data_out, out->data, size_out);
  70
  71 ex2:
  72         kvfree(out);
  73 ex1:
  74         kvfree(in);
  75         return err;
  76 }
  77 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
  78
  79
  80 struct mlx5_reg_pcap {
  81         u8                      rsvd0;
  82         u8                      port_num;
  83         u8                      rsvd1[2];
  84         __be32                  caps_127_96;
  85         __be32                  caps_95_64;
  86         __be32                  caps_63_32;
  87         __be32                  caps_31_0;
  88 };
  89
  90 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
  91 {
  92         struct mlx5_reg_pcap in;
  93         struct mlx5_reg_pcap out;
  94
  95         memset(&in, 0, sizeof(in));
  96         in.caps_127_96 = cpu_to_be32(caps);
  97         in.port_num = port_num;
  98
  99         return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
 100                                     sizeof(out), MLX5_REG_PCAP, 0, 1);
 101 }
 102 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
 103
 104 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
 105                          int ptys_size, int proto_mask, u8 local_port)
 106 {
 107         u32 in[MLX5_ST_SZ_DW(ptys_reg)];
 108
 109         memset(in, 0, sizeof(in));
 110         MLX5_SET(ptys_reg, in, local_port, local_port);
 111         MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
 112
 113         return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
 114                                     ptys_size, MLX5_REG_PTYS, 0, 0);
 115 }
 116 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
 117
 118 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
 119 {
 120         u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
 121         u32 in[MLX5_ST_SZ_DW(mlcr_reg)];
 122
 123         memset(in, 0, sizeof(in));
 124         MLX5_SET(mlcr_reg, in, local_port, 1);
 125         MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
 126
 127         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 128                                     sizeof(out), MLX5_REG_MLCR, 0, 1);
 129 }
 130
 131 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
 132                               u32 *proto_cap, int proto_mask)
 133 {
 134         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 135         int err;
 136
 137         err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
 138         if (err)
 139                 return err;
 140
 141         if (proto_mask == MLX5_PTYS_EN)
 142                 *proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
 143         else
 144                 *proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
 145
 146         return 0;
 147 }
 148 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
 149
 150 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
 151                                 u32 *proto_admin, int proto_mask)
 152 {
 153         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 154         int err;
 155
 156         err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
 157         if (err)
 158                 return err;
 159
 160         if (proto_mask == MLX5_PTYS_EN)
 161                 *proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
 162         else
 163                 *proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
 164
 165         return 0;
 166 }
 167 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
 168
 169 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
 170                                     u8 *link_width_oper, u8 local_port)
 171 {
 172         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 173         int err;
 174
 175         err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
 176         if (err)
 177                 return err;
 178
 179         *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
 180
 181         return 0;
 182 }
 183 EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);
 184
 185 int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
 186                                u8 *proto_oper, int proto_mask,
 187                                u8 local_port)
 188 {
 189         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 190         int err;
 191
 192         err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, local_port);
 193         if (err)
 194                 return err;
 195
 196         if (proto_mask == MLX5_PTYS_EN)
 197                 *proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 198         else
 199                 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
 200
 201         return 0;
 202 }
 203 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper);
 204
 205 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
 206                         int proto_mask)
 207 {
 208         u32 in[MLX5_ST_SZ_DW(ptys_reg)];
 209         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 210
 211         memset(in, 0, sizeof(in));
 212
 213         MLX5_SET(ptys_reg, in, local_port, 1);
 214         MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
 215         if (proto_mask == MLX5_PTYS_EN)
 216                 MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
 217         else
 218                 MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
 219
 220         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 221                                     sizeof(out), MLX5_REG_PTYS, 0, 1);
 222 }
 223 EXPORT_SYMBOL_GPL(mlx5_set_port_proto);
 224
 225 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
 226                                enum mlx5_port_status status)
 227 {
 228         u32 in[MLX5_ST_SZ_DW(paos_reg)];
 229         u32 out[MLX5_ST_SZ_DW(paos_reg)];
 230
 231         memset(in, 0, sizeof(in));
 232
 233         MLX5_SET(paos_reg, in, local_port, 1);
 234         MLX5_SET(paos_reg, in, admin_status, status);
 235         MLX5_SET(paos_reg, in, ase, 1);
 236
 237         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 238                                     sizeof(out), MLX5_REG_PAOS, 0, 1);
 239 }
 240 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
 241
 242 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
 243                                  enum mlx5_port_status *status)
 244 {
 245         u32 in[MLX5_ST_SZ_DW(paos_reg)];
 246         u32 out[MLX5_ST_SZ_DW(paos_reg)];
 247         int err;
 248
 249         memset(in, 0, sizeof(in));
 250
 251         MLX5_SET(paos_reg, in, local_port, 1);
 252
 253         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 254                                    sizeof(out), MLX5_REG_PAOS, 0, 0);
 255         if (err)
 256                 return err;
 257
 258         *status = MLX5_GET(paos_reg, out, admin_status);
 259         return 0;
 260 }
 261 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
 262
 263 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu,
 264                                 u16 *max_mtu, u16 *oper_mtu, u8 port)
 265 {
 266         u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
 267         u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
 268
 269         memset(in, 0, sizeof(in));
 270
 271         MLX5_SET(pmtu_reg, in, local_port, port);
 272
 273         mlx5_core_access_reg(dev, in, sizeof(in), out,
 274                              sizeof(out), MLX5_REG_PMTU, 0, 0);
 275
 276         if (max_mtu)
 277                 *max_mtu  = MLX5_GET(pmtu_reg, out, max_mtu);
 278         if (oper_mtu)
 279                 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
 280         if (admin_mtu)
 281                 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
 282 }
 283
 284 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
 285 {
 286         u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
 287         u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
 288
 289         memset(in, 0, sizeof(in));
 290
 291         MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
 292         MLX5_SET(pmtu_reg, in, local_port, port);
 293
 294         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 295                                    sizeof(out), MLX5_REG_PMTU, 0, 1);
 296 }
 297 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
 298
 299 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu,
 300                              u8 port)
 301 {
 302         mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
 303 }
 304 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
 305
 306 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
 307                               u8 port)
 308 {
 309         mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
 310 }
 311 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
 312
 313 static int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num)
 314 {
 315         u32 out[MLX5_ST_SZ_DW(pmlp_reg)];
 316         u32 in[MLX5_ST_SZ_DW(pmlp_reg)];
 317         int module_mapping;
 318         int err;
 319
 320         memset(in, 0, sizeof(in));
 321
 322         MLX5_SET(pmlp_reg, in, local_port, 1);
 323
 324         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 325                                    MLX5_REG_PMLP, 0, 0);
 326         if (err)
 327                 return err;
 328
 329         module_mapping = MLX5_GET(pmlp_reg, out, lane0_module_mapping);
 330         *module_num = module_mapping & MLX5_EEPROM_IDENTIFIER_BYTE_MASK;
 331
 332         return 0;
 333 }
 334
 335 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
 336                              u16 offset, u16 size, u8 *data)
 337 {
 338         u32 out[MLX5_ST_SZ_DW(mcia_reg)];
 339         u32 in[MLX5_ST_SZ_DW(mcia_reg)];
 340         int module_num;
 341         u16 i2c_addr;
 342         int status;
 343         int err;
 344         void *ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
 345
 346         err = mlx5_query_module_num(dev, &module_num);
 347         if (err)
 348                 return err;
 349
 350         memset(in, 0, sizeof(in));
 351         size = min_t(int, size, MLX5_EEPROM_MAX_BYTES);
 352
 353         if (offset < MLX5_EEPROM_PAGE_LENGTH &&
 354             offset + size > MLX5_EEPROM_PAGE_LENGTH)
 355                 /* Cross pages read, read until offset 256 in low page */
 356                 size -= offset + size - MLX5_EEPROM_PAGE_LENGTH;
 357
 358         i2c_addr = MLX5_I2C_ADDR_LOW;
 359         if (offset >= MLX5_EEPROM_PAGE_LENGTH) {
 360                 i2c_addr = MLX5_I2C_ADDR_HIGH;
 361                 offset -= MLX5_EEPROM_PAGE_LENGTH;
 362         }
 363
 364         MLX5_SET(mcia_reg, in, l, 0);
 365         MLX5_SET(mcia_reg, in, module, module_num);
 366         MLX5_SET(mcia_reg, in, i2c_device_address, i2c_addr);
 367         MLX5_SET(mcia_reg, in, page_number, 0);
 368         MLX5_SET(mcia_reg, in, device_address, offset);
 369         MLX5_SET(mcia_reg, in, size, size);
 370
 371         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 372                                    sizeof(out), MLX5_REG_MCIA, 0, 0);
 373         if (err)
 374                 return err;
 375
 376         status = MLX5_GET(mcia_reg, out, status);
 377         if (status) {
 378                 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
 379                               status);
 380                 return -EIO;
 381         }
 382
 383         memcpy(data, ptr, size);
 384
 385         return size;
 386 }
 387 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom);
 388
 389 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
 390                                 int pvlc_size,  u8 local_port)
 391 {
 392         u32 in[MLX5_ST_SZ_DW(pvlc_reg)];
 393
 394         memset(in, 0, sizeof(in));
 395         MLX5_SET(pvlc_reg, in, local_port, local_port);
 396
 397         return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
 398                                     pvlc_size, MLX5_REG_PVLC, 0, 0);
 399 }
 400
 401 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
 402                               u8 *vl_hw_cap, u8 local_port)
 403 {
 404         u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
 405         int err;
 406
 407         err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
 408         if (err)
 409                 return err;
 410
 411         *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
 412
 413         return 0;
 414 }
 415 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
 416
 417 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
 418                              u8 port_num, void *out, size_t sz)
 419 {
 420         u32 *in;
 421         int err;
 422
 423         in  = mlx5_vzalloc(sz);
 424         if (!in) {
 425                 err = -ENOMEM;
 426                 return err;
 427         }
 428
 429         MLX5_SET(ppcnt_reg, in, local_port, port_num);
 430
 431         MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
 432         err = mlx5_core_access_reg(dev, in, sz, out,
 433                                    sz, MLX5_REG_PPCNT, 0, 0);
 434
 435         kvfree(in);
 436         return err;
 437 }
 438 EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);
 439
 440 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
 441 {
 442         u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
 443         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 444
 445         memset(in, 0, sizeof(in));
 446         MLX5_SET(pfcc_reg, in, local_port, 1);
 447         MLX5_SET(pfcc_reg, in, pptx, tx_pause);
 448         MLX5_SET(pfcc_reg, in, pprx, rx_pause);
 449
 450         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 451                                     sizeof(out), MLX5_REG_PFCC, 0, 1);
 452 }
 453 EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
 454
 455 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
 456                           u32 *rx_pause, u32 *tx_pause)
 457 {
 458         u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
 459         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 460         int err;
 461
 462         memset(in, 0, sizeof(in));
 463         MLX5_SET(pfcc_reg, in, local_port, 1);
 464
 465         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 466                                    sizeof(out), MLX5_REG_PFCC, 0, 0);
 467         if (err)
 468                 return err;
 469
 470         if (rx_pause)
 471                 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
 472
 473         if (tx_pause)
 474                 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
 475
 476         return 0;
 477 }
 478 EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
 479
 480 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
 481 {
 482         u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
 483         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 484
 485         memset(in, 0, sizeof(in));
 486         MLX5_SET(pfcc_reg, in, local_port, 1);
 487         MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
 488         MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
 489         MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
 490         MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
 491
 492         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 493                                     sizeof(out), MLX5_REG_PFCC, 0, 1);
 494 }
 495 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
 496
 497 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
 498 {
 499         u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
 500         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 501         int err;
 502
 503         memset(in, 0, sizeof(in));
 504         MLX5_SET(pfcc_reg, in, local_port, 1);
 505
 506         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 507                                    sizeof(out), MLX5_REG_PFCC, 0, 0);
 508         if (err)
 509                 return err;
 510
 511         if (pfc_en_tx)
 512                 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
 513
 514         if (pfc_en_rx)
 515                 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
 516
 517         return 0;
 518 }
 519 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
 520
 521 int mlx5_max_tc(struct mlx5_core_dev *mdev)
 522 {
 523         u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
 524
 525         return num_tc - 1;
 526 }
 527
 528 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
 529 {
 530         u32 in[MLX5_ST_SZ_DW(qtct_reg)];
 531         u32 out[MLX5_ST_SZ_DW(qtct_reg)];
 532         int err;
 533         int i;
 534
 535         memset(in, 0, sizeof(in));
 536         for (i = 0; i < 8; i++) {
 537                 if (prio_tc[i] > mlx5_max_tc(mdev))
 538                         return -EINVAL;
 539
 540                 MLX5_SET(qtct_reg, in, prio, i);
 541                 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
 542
 543                 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
 544                                            sizeof(out), MLX5_REG_QTCT, 0, 1);
 545                 if (err)
 546                         return err;
 547         }
 548
 549         return 0;
 550 }
 551 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
 552
 553 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
 554                                    int inlen)
 555 {
 556         u32 out[MLX5_ST_SZ_DW(qtct_reg)];
 557
 558         if (!MLX5_CAP_GEN(mdev, ets))
 559                 return -ENOTSUPP;
 560
 561         return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
 562                                     MLX5_REG_QETCR, 0, 1);
 563 }
 564
 565 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
 566                                      int outlen)
 567 {
 568         u32 in[MLX5_ST_SZ_DW(qtct_reg)];
 569
 570         if (!MLX5_CAP_GEN(mdev, ets))
 571                 return -ENOTSUPP;
 572
 573         memset(in, 0, sizeof(in));
 574         return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
 575                                     MLX5_REG_QETCR, 0, 0);
 576 }
 577
 578 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
 579 {
 580         u32 in[MLX5_ST_SZ_DW(qetc_reg)];
 581         int i;
 582
 583         memset(in, 0, sizeof(in));
 584
 585         for (i = 0; i <= mlx5_max_tc(mdev); i++) {
 586                 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
 587                 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
 588         }
 589
 590         return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
 591 }
 592 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
 593
 594 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
 595 {
 596         u32 in[MLX5_ST_SZ_DW(qetc_reg)];
 597         int i;
 598
 599         memset(in, 0, sizeof(in));
 600
 601         for (i = 0; i <= mlx5_max_tc(mdev); i++) {
 602                 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
 603                 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
 604         }
 605
 606         return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
 607 }
 608 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
 609
 610 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
 611                                     u8 *max_bw_value,
 612                                     u8 *max_bw_units)
 613 {
 614         u32 in[MLX5_ST_SZ_DW(qetc_reg)];
 615         void *ets_tcn_conf;
 616         int i;
 617
 618         memset(in, 0, sizeof(in));
 619
 620         MLX5_SET(qetc_reg, in, port_number, 1);
 621
 622         for (i = 0; i <= mlx5_max_tc(mdev); i++) {
 623                 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
 624
 625                 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
 626                 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
 627                          max_bw_units[i]);
 628                 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
 629                          max_bw_value[i]);
 630         }
 631
 632         return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
 633 }
 634 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
 635
 636 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
 637                                    u8 *max_bw_value,
 638                                    u8 *max_bw_units)
 639 {
 640         u32 out[MLX5_ST_SZ_DW(qetc_reg)];
 641         void *ets_tcn_conf;
 642         int err;
 643         int i;
 644
 645         err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
 646         if (err)
 647                 return err;
 648
 649         for (i = 0; i <= mlx5_max_tc(mdev); i++) {
 650                 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
 651
 652                 max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
 653                                            max_bw_value);
 654                 max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
 655                                            max_bw_units);
 656         }
 657
 658         return 0;
 659 }
 660 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
 661
 662 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
 663 {
 664         u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)];
 665         u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)];
 666
 667         memset(in, 0, sizeof(in));
 668         memset(out, 0, sizeof(out));
 669
 670         MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
 671         MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
 672         MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
 673
 674         return mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
 675                                           out, sizeof(out));
 676 }
 677 EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
 678
 679 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
 680 {
 681         u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)];
 682         u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)];
 683         int err;
 684
 685         memset(in, 0, sizeof(in));
 686         memset(out, 0, sizeof(out));
 687
 688         MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
 689
 690         err = mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
 691                                          out, sizeof(out));
 692
 693         if (!err)
 694                 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
 695
 696         return err;
 697 }
 698 EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
 699
 700 static int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out,
 701                                   int outlen)
 702 {
 703         u32 in[MLX5_ST_SZ_DW(pcmr_reg)];
 704
 705         memset(in, 0, sizeof(in));
 706         MLX5_SET(pcmr_reg, in, local_port, 1);
 707
 708         return mlx5_core_access_reg(mdev, in, sizeof(in), out,
 709                                     outlen, MLX5_REG_PCMR, 0, 0);
 710 }
 711
 712 static int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
 713 {
 714         u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
 715
 716         return mlx5_core_access_reg(mdev, in, inlen, out,
 717                                     sizeof(out), MLX5_REG_PCMR, 0, 1);
 718 }
 719
 720 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
 721 {
 722         u32 in[MLX5_ST_SZ_DW(pcmr_reg)];
 723
 724         memset(in, 0, sizeof(in));
 725         MLX5_SET(pcmr_reg, in, local_port, 1);
 726         MLX5_SET(pcmr_reg, in, fcs_chk, enable);
 727
 728         return mlx5_set_ports_check(mdev, in, sizeof(in));
 729 }
 730
 731 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
 732                          bool *enabled)
 733 {
 734         u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
 735         /* Default values for FW which do not support MLX5_REG_PCMR */
 736         *supported = false;
 737         *enabled = true;
 738
 739         if (!MLX5_CAP_GEN(mdev, ports_check))
 740                 return;
 741
 742         if (mlx5_query_ports_check(mdev, out, sizeof(out)))
 743                 return;
 744
 745         *supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
 746         *enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));
 747 }