drivers/net/ethernet/mellanox/mlx5/core/port.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/port.h>
  34 #include "mlx5_core.h"
  35
  36 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
  37                          int size_in, void *data_out, int size_out,
  38                          u16 reg_id, int arg, int write)
  39 {
  40         int outlen = MLX5_ST_SZ_BYTES(access_register_out) + size_out;
  41         int inlen = MLX5_ST_SZ_BYTES(access_register_in) + size_in;
  42         int err = -ENOMEM;
  43         u32 *out = NULL;
  44         u32 *in = NULL;
  45         void *data;
  46
  47         in = kvzalloc(inlen, GFP_KERNEL);
  48         out = kvzalloc(outlen, GFP_KERNEL);
  49         if (!in || !out)
  50                 goto out;
  51
  52         data = MLX5_ADDR_OF(access_register_in, in, register_data);
  53         memcpy(data, data_in, size_in);
  54
  55         MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REG);
  56         MLX5_SET(access_register_in, in, op_mod, !write);
  57         MLX5_SET(access_register_in, in, argument, arg);
  58         MLX5_SET(access_register_in, in, register_id, reg_id);
  59
  60         err = mlx5_cmd_exec(dev, in, inlen, out, outlen);
  61         if (err)
  62                 goto out;
  63
  64         data = MLX5_ADDR_OF(access_register_out, out, register_data);
  65         memcpy(data_out, data, size_out);
  66
  67 out:
  68         kvfree(out);
  69         kvfree(in);
  70         return err;
  71 }
  72 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
  73
  74 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
  75                         u8 access_reg_group)
  76 {
  77         u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0};
  78         int sz = MLX5_ST_SZ_BYTES(pcam_reg);
  79
  80         MLX5_SET(pcam_reg, in, feature_group, feature_group);
  81         MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group);
  82
  83         return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0);
  84 }
  85
  86 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group,
  87                         u8 access_reg_group)
  88 {
  89         u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0};
  90         int sz = MLX5_ST_SZ_BYTES(mcam_reg);
  91
  92         MLX5_SET(mcam_reg, in, feature_group, feature_group);
  93         MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group);
  94
  95         return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);
  96 }
  97
  98 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
  99                         u8 feature_group, u8 access_reg_group)
 100 {
 101         u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};
 102         int sz = MLX5_ST_SZ_BYTES(qcam_reg);
 103
 104         MLX5_SET(qcam_reg, in, feature_group, feature_group);
 105         MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group);
 106
 107         return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0);
 108 }
 109
 110 struct mlx5_reg_pcap {
 111         u8                      rsvd0;
 112         u8                      port_num;
 113         u8                      rsvd1[2];
 114         __be32                  caps_127_96;
 115         __be32                  caps_95_64;
 116         __be32                  caps_63_32;
 117         __be32                  caps_31_0;
 118 };
 119
 120 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
 121 {
 122         struct mlx5_reg_pcap in;
 123         struct mlx5_reg_pcap out;
 124
 125         memset(&in, 0, sizeof(in));
 126         in.caps_127_96 = cpu_to_be32(caps);
 127         in.port_num = port_num;
 128
 129         return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
 130                                     sizeof(out), MLX5_REG_PCAP, 0, 1);
 131 }
 132 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
 133
 134 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
 135                          int ptys_size, int proto_mask, u8 local_port)
 136 {
 137         u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
 138
 139         MLX5_SET(ptys_reg, in, local_port, local_port);
 140         MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
 141         return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
 142                                     ptys_size, MLX5_REG_PTYS, 0, 0);
 143 }
 144 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
 145
 146 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
 147 {
 148         u32 in[MLX5_ST_SZ_DW(mlcr_reg)]  = {0};
 149         u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
 150
 151         MLX5_SET(mlcr_reg, in, local_port, 1);
 152         MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
 153         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 154                                     sizeof(out), MLX5_REG_MLCR, 0, 1);
 155 }
 156
 157 int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper,
 158                             u16 *proto_oper, u8 local_port)
 159 {
 160         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 161         int err;
 162
 163         err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB,
 164                                    local_port);
 165         if (err)
 166                 return err;
 167
 168         *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
 169         *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
 170
 171         return 0;
 172 }
 173 EXPORT_SYMBOL(mlx5_query_ib_port_oper);
 174
 175 /* This function should be used after setting a port register only */
 176 void mlx5_toggle_port_link(struct mlx5_core_dev *dev)
 177 {
 178         enum mlx5_port_status ps;
 179
 180         mlx5_query_port_admin_status(dev, &ps);
 181         mlx5_set_port_admin_status(dev, MLX5_PORT_DOWN);
 182         if (ps == MLX5_PORT_UP)
 183                 mlx5_set_port_admin_status(dev, MLX5_PORT_UP);
 184 }
 185 EXPORT_SYMBOL_GPL(mlx5_toggle_port_link);
 186
 187 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
 188                                enum mlx5_port_status status)
 189 {
 190         u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
 191         u32 out[MLX5_ST_SZ_DW(paos_reg)];
 192
 193         MLX5_SET(paos_reg, in, local_port, 1);
 194         MLX5_SET(paos_reg, in, admin_status, status);
 195         MLX5_SET(paos_reg, in, ase, 1);
 196         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 197                                     sizeof(out), MLX5_REG_PAOS, 0, 1);
 198 }
 199 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
 200
 201 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
 202                                  enum mlx5_port_status *status)
 203 {
 204         u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
 205         u32 out[MLX5_ST_SZ_DW(paos_reg)];
 206         int err;
 207
 208         MLX5_SET(paos_reg, in, local_port, 1);
 209         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 210                                    sizeof(out), MLX5_REG_PAOS, 0, 0);
 211         if (err)
 212                 return err;
 213         *status = MLX5_GET(paos_reg, out, admin_status);
 214         return 0;
 215 }
 216 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
 217
 218 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu,
 219                                 u16 *max_mtu, u16 *oper_mtu, u8 port)
 220 {
 221         u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
 222         u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
 223
 224         MLX5_SET(pmtu_reg, in, local_port, port);
 225         mlx5_core_access_reg(dev, in, sizeof(in), out,
 226                              sizeof(out), MLX5_REG_PMTU, 0, 0);
 227
 228         if (max_mtu)
 229                 *max_mtu  = MLX5_GET(pmtu_reg, out, max_mtu);
 230         if (oper_mtu)
 231                 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
 232         if (admin_mtu)
 233                 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
 234 }
 235
 236 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
 237 {
 238         u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
 239         u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
 240
 241         MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
 242         MLX5_SET(pmtu_reg, in, local_port, port);
 243         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 244                                    sizeof(out), MLX5_REG_PMTU, 0, 1);
 245 }
 246 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
 247
 248 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu,
 249                              u8 port)
 250 {
 251         mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
 252 }
 253 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
 254
 255 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
 256                               u8 port)
 257 {
 258         mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
 259 }
 260 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
 261
 262 static int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num)
 263 {
 264         u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0};
 265         u32 out[MLX5_ST_SZ_DW(pmlp_reg)];
 266         int module_mapping;
 267         int err;
 268
 269         MLX5_SET(pmlp_reg, in, local_port, 1);
 270         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 271                                    MLX5_REG_PMLP, 0, 0);
 272         if (err)
 273                 return err;
 274
 275         module_mapping = MLX5_GET(pmlp_reg, out, lane0_module_mapping);
 276         *module_num = module_mapping & MLX5_EEPROM_IDENTIFIER_BYTE_MASK;
 277
 278         return 0;
 279 }
 280
 281 static int mlx5_query_module_id(struct mlx5_core_dev *dev, int module_num,
 282                                 u8 *module_id)
 283 {
 284         u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {};
 285         u32 out[MLX5_ST_SZ_DW(mcia_reg)];
 286         int err, status;
 287         u8 *ptr;
 288
 289         MLX5_SET(mcia_reg, in, i2c_device_address, MLX5_I2C_ADDR_LOW);
 290         MLX5_SET(mcia_reg, in, module, module_num);
 291         MLX5_SET(mcia_reg, in, device_address, 0);
 292         MLX5_SET(mcia_reg, in, page_number, 0);
 293         MLX5_SET(mcia_reg, in, size, 1);
 294         MLX5_SET(mcia_reg, in, l, 0);
 295
 296         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 297                                    sizeof(out), MLX5_REG_MCIA, 0, 0);
 298         if (err)
 299                 return err;
 300
 301         status = MLX5_GET(mcia_reg, out, status);
 302         if (status) {
 303                 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
 304                               status);
 305                 return -EIO;
 306         }
 307         ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
 308
 309         *module_id = ptr[0];
 310
 311         return 0;
 312 }
 313
 314 static int mlx5_qsfp_eeprom_page(u16 offset)
 315 {
 316         if (offset < MLX5_EEPROM_PAGE_LENGTH)
 317                 /* Addresses between 0-255 - page 00 */
 318                 return 0;
 319
 320         /* Addresses between 256 - 639 belongs to pages 01, 02 and 03
 321          * For example, offset = 400 belongs to page 02:
 322          * 1 + ((400 - 256)/128) = 2
 323          */
 324         return 1 + ((offset - MLX5_EEPROM_PAGE_LENGTH) /
 325                     MLX5_EEPROM_HIGH_PAGE_LENGTH);
 326 }
 327
 328 static int mlx5_qsfp_eeprom_high_page_offset(int page_num)
 329 {
 330         if (!page_num) /* Page 0 always start from low page */
 331                 return 0;
 332
 333         /* High page */
 334         return page_num * MLX5_EEPROM_HIGH_PAGE_LENGTH;
 335 }
 336
 337 static void mlx5_qsfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset)
 338 {
 339         *i2c_addr = MLX5_I2C_ADDR_LOW;
 340         *page_num = mlx5_qsfp_eeprom_page(*offset);
 341         *offset -=  mlx5_qsfp_eeprom_high_page_offset(*page_num);
 342 }
 343
 344 static void mlx5_sfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset)
 345 {
 346         *i2c_addr = MLX5_I2C_ADDR_LOW;
 347         *page_num = 0;
 348
 349         if (*offset < MLX5_EEPROM_PAGE_LENGTH)
 350                 return;
 351
 352         *i2c_addr = MLX5_I2C_ADDR_HIGH;
 353         *offset -= MLX5_EEPROM_PAGE_LENGTH;
 354 }
 355
 356 static int mlx5_query_mcia(struct mlx5_core_dev *dev,
 357                            struct mlx5_module_eeprom_query_params *params, u8 *data)
 358 {
 359         u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {};
 360         u32 out[MLX5_ST_SZ_DW(mcia_reg)];
 361         int status, err;
 362         void *ptr;
 363         u16 size;
 364
 365         size = min_t(int, params->size, MLX5_EEPROM_MAX_BYTES);
 366
 367         MLX5_SET(mcia_reg, in, l, 0);
 368         MLX5_SET(mcia_reg, in, size, size);
 369         MLX5_SET(mcia_reg, in, module, params->module_number);
 370         MLX5_SET(mcia_reg, in, device_address, params->offset);
 371         MLX5_SET(mcia_reg, in, page_number, params->page);
 372         MLX5_SET(mcia_reg, in, i2c_device_address, params->i2c_address);
 373
 374         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 375                                    sizeof(out), MLX5_REG_MCIA, 0, 0);
 376         if (err)
 377                 return err;
 378
 379         status = MLX5_GET(mcia_reg, out, status);
 380         if (status) {
 381                 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
 382                               status);
 383                 return -EIO;
 384         }
 385
 386         ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
 387         memcpy(data, ptr, size);
 388
 389         return size;
 390 }
 391
 392 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
 393                              u16 offset, u16 size, u8 *data)
 394 {
 395         struct mlx5_module_eeprom_query_params query = {0};
 396         u8 module_id;
 397         int err;
 398
 399         err = mlx5_query_module_num(dev, &query.module_number);
 400         if (err)
 401                 return err;
 402
 403         err = mlx5_query_module_id(dev, query.module_number, &module_id);
 404         if (err)
 405                 return err;
 406
 407         switch (module_id) {
 408         case MLX5_MODULE_ID_SFP:
 409                 mlx5_sfp_eeprom_params_set(&query.i2c_address, &query.page, &query.offset);
 410                 break;
 411         case MLX5_MODULE_ID_QSFP:
 412         case MLX5_MODULE_ID_QSFP_PLUS:
 413         case MLX5_MODULE_ID_QSFP28:
 414                 mlx5_qsfp_eeprom_params_set(&query.i2c_address, &query.page, &query.offset);
 415                 break;
 416         default:
 417                 mlx5_core_err(dev, "Module ID not recognized: 0x%x\n", module_id);
 418                 return -EINVAL;
 419         }
 420
 421         if (query.offset + size > MLX5_EEPROM_PAGE_LENGTH)
 422                 /* Cross pages read, read until offset 256 in low page */
 423                 size -= offset + size - MLX5_EEPROM_PAGE_LENGTH;
 424
 425         query.size = size;
 426
 427         return mlx5_query_mcia(dev, &query, data);
 428 }
 429 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom);
 430
 431 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
 432                                 int pvlc_size,  u8 local_port)
 433 {
 434         u32 in[MLX5_ST_SZ_DW(pvlc_reg)] = {0};
 435
 436         MLX5_SET(pvlc_reg, in, local_port, local_port);
 437         return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
 438                                     pvlc_size, MLX5_REG_PVLC, 0, 0);
 439 }
 440
 441 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
 442                               u8 *vl_hw_cap, u8 local_port)
 443 {
 444         u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
 445         int err;
 446
 447         err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
 448         if (err)
 449                 return err;
 450
 451         *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
 452
 453         return 0;
 454 }
 455 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
 456
 457 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
 458                              u8 port_num, void *out, size_t sz)
 459 {
 460         u32 *in;
 461         int err;
 462
 463         in  = kvzalloc(sz, GFP_KERNEL);
 464         if (!in) {
 465                 err = -ENOMEM;
 466                 return err;
 467         }
 468
 469         MLX5_SET(ppcnt_reg, in, local_port, port_num);
 470
 471         MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
 472         err = mlx5_core_access_reg(dev, in, sz, out,
 473                                    sz, MLX5_REG_PPCNT, 0, 0);
 474
 475         kvfree(in);
 476         return err;
 477 }
 478 EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);
 479
 480 static int mlx5_query_pfcc_reg(struct mlx5_core_dev *dev, u32 *out,
 481                                u32 out_size)
 482 {
 483         u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
 484
 485         MLX5_SET(pfcc_reg, in, local_port, 1);
 486
 487         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 488                                     out_size, MLX5_REG_PFCC, 0, 0);
 489 }
 490
 491 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
 492 {
 493         u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
 494         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 495
 496         MLX5_SET(pfcc_reg, in, local_port, 1);
 497         MLX5_SET(pfcc_reg, in, pptx, tx_pause);
 498         MLX5_SET(pfcc_reg, in, pprx, rx_pause);
 499
 500         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 501                                     sizeof(out), MLX5_REG_PFCC, 0, 1);
 502 }
 503 EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
 504
 505 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
 506                           u32 *rx_pause, u32 *tx_pause)
 507 {
 508         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 509         int err;
 510
 511         err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
 512         if (err)
 513                 return err;
 514
 515         if (rx_pause)
 516                 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
 517
 518         if (tx_pause)
 519                 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
 520
 521         return 0;
 522 }
 523 EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
 524
 525 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
 526                                   u16 stall_critical_watermark,
 527                                   u16 stall_minor_watermark)
 528 {
 529         u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
 530         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 531
 532         MLX5_SET(pfcc_reg, in, local_port, 1);
 533         MLX5_SET(pfcc_reg, in, pptx_mask_n, 1);
 534         MLX5_SET(pfcc_reg, in, pprx_mask_n, 1);
 535         MLX5_SET(pfcc_reg, in, ppan_mask_n, 1);
 536         MLX5_SET(pfcc_reg, in, critical_stall_mask, 1);
 537         MLX5_SET(pfcc_reg, in, minor_stall_mask, 1);
 538         MLX5_SET(pfcc_reg, in, device_stall_critical_watermark,
 539                  stall_critical_watermark);
 540         MLX5_SET(pfcc_reg, in, device_stall_minor_watermark, stall_minor_watermark);
 541
 542         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 543                                     sizeof(out), MLX5_REG_PFCC, 0, 1);
 544 }
 545
 546 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
 547                                     u16 *stall_critical_watermark,
 548                                     u16 *stall_minor_watermark)
 549 {
 550         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 551         int err;
 552
 553         err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
 554         if (err)
 555                 return err;
 556
 557         if (stall_critical_watermark)
 558                 *stall_critical_watermark = MLX5_GET(pfcc_reg, out,
 559                                                      device_stall_critical_watermark);
 560
 561         if (stall_minor_watermark)
 562                 *stall_minor_watermark = MLX5_GET(pfcc_reg, out,
 563                                                   device_stall_minor_watermark);
 564
 565         return 0;
 566 }
 567
 568 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
 569 {
 570         u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
 571         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 572
 573         MLX5_SET(pfcc_reg, in, local_port, 1);
 574         MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
 575         MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
 576         MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
 577         MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
 578
 579         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 580                                     sizeof(out), MLX5_REG_PFCC, 0, 1);
 581 }
 582 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
 583
 584 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
 585 {
 586         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 587         int err;
 588
 589         err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
 590         if (err)
 591                 return err;
 592
 593         if (pfc_en_tx)
 594                 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
 595
 596         if (pfc_en_rx)
 597                 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
 598
 599         return 0;
 600 }
 601 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
 602
 603 int mlx5_max_tc(struct mlx5_core_dev *mdev)
 604 {
 605         u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
 606
 607         return num_tc - 1;
 608 }
 609
 610 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out)
 611 {
 612         u32 in[MLX5_ST_SZ_DW(dcbx_param)] = {0};
 613
 614         MLX5_SET(dcbx_param, in, port_number, 1);
 615
 616         return  mlx5_core_access_reg(mdev, in, sizeof(in), out,
 617                                     sizeof(in), MLX5_REG_DCBX_PARAM, 0, 0);
 618 }
 619
 620 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in)
 621 {
 622         u32 out[MLX5_ST_SZ_DW(dcbx_param)];
 623
 624         MLX5_SET(dcbx_param, in, port_number, 1);
 625
 626         return mlx5_core_access_reg(mdev, in, sizeof(out), out,
 627                                     sizeof(out), MLX5_REG_DCBX_PARAM, 0, 1);
 628 }
 629
 630 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
 631 {
 632         u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0};
 633         u32 out[MLX5_ST_SZ_DW(qtct_reg)];
 634         int err;
 635         int i;
 636
 637         for (i = 0; i < 8; i++) {
 638                 if (prio_tc[i] > mlx5_max_tc(mdev))
 639                         return -EINVAL;
 640
 641                 MLX5_SET(qtct_reg, in, prio, i);
 642                 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
 643
 644                 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
 645                                            sizeof(out), MLX5_REG_QTCT, 0, 1);
 646                 if (err)
 647                         return err;
 648         }
 649
 650         return 0;
 651 }
 652 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
 653
 654 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
 655                             u8 prio, u8 *tc)
 656 {
 657         u32 in[MLX5_ST_SZ_DW(qtct_reg)];
 658         u32 out[MLX5_ST_SZ_DW(qtct_reg)];
 659         int err;
 660
 661         memset(in, 0, sizeof(in));
 662         memset(out, 0, sizeof(out));
 663
 664         MLX5_SET(qtct_reg, in, port_number, 1);
 665         MLX5_SET(qtct_reg, in, prio, prio);
 666
 667         err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
 668                                    sizeof(out), MLX5_REG_QTCT, 0, 0);
 669         if (!err)
 670                 *tc = MLX5_GET(qtct_reg, out, tclass);
 671
 672         return err;
 673 }
 674 EXPORT_SYMBOL_GPL(mlx5_query_port_prio_tc);
 675
 676 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
 677                                    int inlen)
 678 {
 679         u32 out[MLX5_ST_SZ_DW(qetc_reg)];
 680
 681         if (!MLX5_CAP_GEN(mdev, ets))
 682                 return -EOPNOTSUPP;
 683
 684         return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
 685                                     MLX5_REG_QETCR, 0, 1);
 686 }
 687
 688 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
 689                                      int outlen)
 690 {
 691         u32 in[MLX5_ST_SZ_DW(qetc_reg)];
 692
 693         if (!MLX5_CAP_GEN(mdev, ets))
 694                 return -EOPNOTSUPP;
 695
 696         memset(in, 0, sizeof(in));
 697         return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
 698                                     MLX5_REG_QETCR, 0, 0);
 699 }
 700
 701 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
 702 {
 703         u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
 704         int i;
 705
 706         for (i = 0; i <= mlx5_max_tc(mdev); i++) {
 707                 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
 708                 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
 709         }
 710
 711         return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
 712 }
 713 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
 714
 715 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
 716                              u8 tc, u8 *tc_group)
 717 {
 718         u32 out[MLX5_ST_SZ_DW(qetc_reg)];
 719         void *ets_tcn_conf;
 720         int err;
 721
 722         err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
 723         if (err)
 724                 return err;
 725
 726         ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
 727                                     tc_configuration[tc]);
 728
 729         *tc_group = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
 730                              group);
 731
 732         return 0;
 733 }
 734 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_group);
 735
 736 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
 737 {
 738         u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
 739         int i;
 740
 741         for (i = 0; i <= mlx5_max_tc(mdev); i++) {
 742                 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
 743                 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
 744         }
 745
 746         return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
 747 }
 748 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
 749
 750 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
 751                                 u8 tc, u8 *bw_pct)
 752 {
 753         u32 out[MLX5_ST_SZ_DW(qetc_reg)];
 754         void *ets_tcn_conf;
 755         int err;
 756
 757         err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
 758         if (err)
 759                 return err;
 760
 761         ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
 762                                     tc_configuration[tc]);
 763
 764         *bw_pct = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
 765                            bw_allocation);
 766
 767         return 0;
 768 }
 769 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_bw_alloc);
 770
 771 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
 772                                     u8 *max_bw_value,
 773                                     u8 *max_bw_units)
 774 {
 775         u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
 776         void *ets_tcn_conf;
 777         int i;
 778
 779         MLX5_SET(qetc_reg, in, port_number, 1);
 780
 781         for (i = 0; i <= mlx5_max_tc(mdev); i++) {
 782                 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
 783
 784                 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
 785                 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
 786                          max_bw_units[i]);
 787                 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
 788                          max_bw_value[i]);
 789         }
 790
 791         return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
 792 }
 793 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
 794
 795 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
 796                                    u8 *max_bw_value,
 797                                    u8 *max_bw_units)
 798 {
 799         u32 out[MLX5_ST_SZ_DW(qetc_reg)];
 800         void *ets_tcn_conf;
 801         int err;
 802         int i;
 803
 804         err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
 805         if (err)
 806                 return err;
 807
 808         for (i = 0; i <= mlx5_max_tc(mdev); i++) {
 809                 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
 810
 811                 max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
 812                                            max_bw_value);
 813                 max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
 814                                            max_bw_units);
 815         }
 816
 817         return 0;
 818 }
 819 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
 820
 821 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
 822 {
 823         u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {};
 824
 825         MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
 826         MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
 827         MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
 828         return mlx5_cmd_exec_in(mdev, set_wol_rol, in);
 829 }
 830 EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
 831
 832 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
 833 {
 834         u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)] = {};
 835         u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {};
 836         int err;
 837
 838         MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
 839         err = mlx5_cmd_exec_inout(mdev, query_wol_rol, in, out);
 840         if (!err)
 841                 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
 842
 843         return err;
 844 }
 845 EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
 846
 847 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen)
 848 {
 849         u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
 850
 851         MLX5_SET(pcmr_reg, in, local_port, 1);
 852         return mlx5_core_access_reg(mdev, in, sizeof(in), out,
 853                                     outlen, MLX5_REG_PCMR, 0, 0);
 854 }
 855
 856 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
 857 {
 858         u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
 859
 860         return mlx5_core_access_reg(mdev, in, inlen, out,
 861                                     sizeof(out), MLX5_REG_PCMR, 0, 1);
 862 }
 863
 864 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
 865 {
 866         u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
 867         int err;
 868
 869         err = mlx5_query_ports_check(mdev, in, sizeof(in));
 870         if (err)
 871                 return err;
 872         MLX5_SET(pcmr_reg, in, local_port, 1);
 873         MLX5_SET(pcmr_reg, in, fcs_chk, enable);
 874         return mlx5_set_ports_check(mdev, in, sizeof(in));
 875 }
 876
 877 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
 878                          bool *enabled)
 879 {
 880         u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
 881         /* Default values for FW which do not support MLX5_REG_PCMR */
 882         *supported = false;
 883         *enabled = true;
 884
 885         if (!MLX5_CAP_GEN(mdev, ports_check))
 886                 return;
 887
 888         if (mlx5_query_ports_check(mdev, out, sizeof(out)))
 889                 return;
 890
 891         *supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
 892         *enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));
 893 }
 894
 895 int mlx5_query_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
 896 {
 897         u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
 898
 899         return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,
 900                                     mtpps_size, MLX5_REG_MTPPS, 0, 0);
 901 }
 902
 903 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
 904 {
 905         u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
 906
 907         return mlx5_core_access_reg(mdev, mtpps, mtpps_size, out,
 908                                     sizeof(out), MLX5_REG_MTPPS, 0, 1);
 909 }
 910
 911 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode)
 912 {
 913         u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
 914         u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
 915         int err = 0;
 916
 917         MLX5_SET(mtppse_reg, in, pin, pin);
 918
 919         err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
 920                                    sizeof(out), MLX5_REG_MTPPSE, 0, 0);
 921         if (err)
 922                 return err;
 923
 924         *arm = MLX5_GET(mtppse_reg, in, event_arm);
 925         *mode = MLX5_GET(mtppse_reg, in, event_generation_mode);
 926
 927         return err;
 928 }
 929
 930 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode)
 931 {
 932         u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
 933         u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
 934
 935         MLX5_SET(mtppse_reg, in, pin, pin);
 936         MLX5_SET(mtppse_reg, in, event_arm, arm);
 937         MLX5_SET(mtppse_reg, in, event_generation_mode, mode);
 938
 939         return mlx5_core_access_reg(mdev, in, sizeof(in), out,
 940                                     sizeof(out), MLX5_REG_MTPPSE, 0, 1);
 941 }
 942
 943 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state)
 944 {
 945         u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
 946         u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
 947         int err;
 948
 949         MLX5_SET(qpts_reg, in, local_port, 1);
 950         MLX5_SET(qpts_reg, in, trust_state, trust_state);
 951
 952         err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
 953                                    sizeof(out), MLX5_REG_QPTS, 0, 1);
 954         return err;
 955 }
 956
 957 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state)
 958 {
 959         u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
 960         u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
 961         int err;
 962
 963         MLX5_SET(qpts_reg, in, local_port, 1);
 964
 965         err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
 966                                    sizeof(out), MLX5_REG_QPTS, 0, 0);
 967         if (!err)
 968                 *trust_state = MLX5_GET(qpts_reg, out, trust_state);
 969
 970         return err;
 971 }
 972
 973 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio)
 974 {
 975         int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
 976         void *qpdpm_dscp;
 977         void *out;
 978         void *in;
 979         int err;
 980
 981         in = kzalloc(sz, GFP_KERNEL);
 982         out = kzalloc(sz, GFP_KERNEL);
 983         if (!in || !out) {
 984                 err = -ENOMEM;
 985                 goto out;
 986         }
 987
 988         MLX5_SET(qpdpm_reg, in, local_port, 1);
 989         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
 990         if (err)
 991                 goto out;
 992
 993         memcpy(in, out, sz);
 994         MLX5_SET(qpdpm_reg, in, local_port, 1);
 995
 996         /* Update the corresponding dscp entry */
 997         qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, in, dscp[dscp]);
 998         MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, prio, prio);
 999         MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, e, 1);
1000         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 1);
1001
1002 out:
1003         kfree(in);
1004         kfree(out);
1005         return err;
1006 }
1007
1008 /* dscp2prio[i]: priority that dscp i mapped to */
1009 #define MLX5E_SUPPORTED_DSCP 64
1010 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio)
1011 {
1012         int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
1013         void *qpdpm_dscp;
1014         void *out;
1015         void *in;
1016         int err;
1017         int i;
1018
1019         in = kzalloc(sz, GFP_KERNEL);
1020         out = kzalloc(sz, GFP_KERNEL);
1021         if (!in || !out) {
1022                 err = -ENOMEM;
1023                 goto out;
1024         }
1025
1026         MLX5_SET(qpdpm_reg, in, local_port, 1);
1027         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
1028         if (err)
1029                 goto out;
1030
1031         for (i = 0; i < (MLX5E_SUPPORTED_DSCP); i++) {
1032                 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, out, dscp[i]);
1033                 dscp2prio[i] = MLX5_GET16(qpdpm_dscp_reg, qpdpm_dscp, prio);
1034         }
1035
1036 out:
1037         kfree(in);
1038         kfree(out);
1039         return err;
1040 }