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[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / mellanox / mlx5 / core / port.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/port.h>
36 #include <linux/mlx5/cmd.h>
37 #include "mlx5_core.h"
38
39 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
40 int size_in, void *data_out, int size_out,
41 u16 reg_id, int arg, int write)
42 {
43 int outlen = MLX5_ST_SZ_BYTES(access_register_out) + size_out;
44 int inlen = MLX5_ST_SZ_BYTES(access_register_in) + size_in;
45 int err = -ENOMEM;
46 u32 *out = NULL;
47 u32 *in = NULL;
48 void *data;
49
50 in = kvzalloc(inlen, GFP_KERNEL);
51 out = kvzalloc(outlen, GFP_KERNEL);
52 if (!in || !out)
53 goto out;
54
55 data = MLX5_ADDR_OF(access_register_in, in, register_data);
56 memcpy(data, data_in, size_in);
57
58 MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REG);
59 MLX5_SET(access_register_in, in, op_mod, !write);
60 MLX5_SET(access_register_in, in, argument, arg);
61 MLX5_SET(access_register_in, in, register_id, reg_id);
62
63 err = mlx5_cmd_exec(dev, in, inlen, out, outlen);
64 if (err)
65 goto out;
66
67 data = MLX5_ADDR_OF(access_register_out, out, register_data);
68 memcpy(data_out, data, size_out);
69
70 out:
71 kvfree(out);
72 kvfree(in);
73 return err;
74 }
75 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
76
77 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
78 u8 access_reg_group)
79 {
80 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0};
81 int sz = MLX5_ST_SZ_BYTES(pcam_reg);
82
83 MLX5_SET(pcam_reg, in, feature_group, feature_group);
84 MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group);
85
86 return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0);
87 }
88
89 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group,
90 u8 access_reg_group)
91 {
92 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0};
93 int sz = MLX5_ST_SZ_BYTES(mcam_reg);
94
95 MLX5_SET(mcam_reg, in, feature_group, feature_group);
96 MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group);
97
98 return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);
99 }
100
101 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
102 u8 feature_group, u8 access_reg_group)
103 {
104 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};
105 int sz = MLX5_ST_SZ_BYTES(qcam_reg);
106
107 MLX5_SET(qcam_reg, in, feature_group, feature_group);
108 MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group);
109
110 return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0);
111 }
112
113 struct mlx5_reg_pcap {
114 u8 rsvd0;
115 u8 port_num;
116 u8 rsvd1[2];
117 __be32 caps_127_96;
118 __be32 caps_95_64;
119 __be32 caps_63_32;
120 __be32 caps_31_0;
121 };
122
123 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
124 {
125 struct mlx5_reg_pcap in;
126 struct mlx5_reg_pcap out;
127
128 memset(&in, 0, sizeof(in));
129 in.caps_127_96 = cpu_to_be32(caps);
130 in.port_num = port_num;
131
132 return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
133 sizeof(out), MLX5_REG_PCAP, 0, 1);
134 }
135 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
136
137 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
138 int ptys_size, int proto_mask, u8 local_port)
139 {
140 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
141
142 MLX5_SET(ptys_reg, in, local_port, local_port);
143 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
144 return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
145 ptys_size, MLX5_REG_PTYS, 0, 0);
146 }
147 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
148
149 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
150 {
151 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0};
152 u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
153
154 MLX5_SET(mlcr_reg, in, local_port, 1);
155 MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
156 return mlx5_core_access_reg(dev, in, sizeof(in), out,
157 sizeof(out), MLX5_REG_MLCR, 0, 1);
158 }
159
160 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
161 u32 *proto_cap, int proto_mask)
162 {
163 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
164 int err;
165
166 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
167 if (err)
168 return err;
169
170 if (proto_mask == MLX5_PTYS_EN)
171 *proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
172 else
173 *proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
174
175 return 0;
176 }
177 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
178
179 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
180 u32 *proto_admin, int proto_mask)
181 {
182 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
183 int err;
184
185 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
186 if (err)
187 return err;
188
189 if (proto_mask == MLX5_PTYS_EN)
190 *proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
191 else
192 *proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
193
194 return 0;
195 }
196 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
197
198 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
199 u8 *link_width_oper, u8 local_port)
200 {
201 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
202 int err;
203
204 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
205 if (err)
206 return err;
207
208 *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
209
210 return 0;
211 }
212 EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);
213
214 int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev,
215 u32 *proto_oper, u8 local_port)
216 {
217 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
218 int err;
219
220 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_EN,
221 local_port);
222 if (err)
223 return err;
224
225 *proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
226
227 return 0;
228 }
229 EXPORT_SYMBOL(mlx5_query_port_eth_proto_oper);
230
231 int mlx5_query_port_ib_proto_oper(struct mlx5_core_dev *dev,
232 u8 *proto_oper, u8 local_port)
233 {
234 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
235 int err;
236
237 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB,
238 local_port);
239 if (err)
240 return err;
241
242 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
243
244 return 0;
245 }
246 EXPORT_SYMBOL(mlx5_query_port_ib_proto_oper);
247
248 int mlx5_set_port_ptys(struct mlx5_core_dev *dev, bool an_disable,
249 u32 proto_admin, int proto_mask)
250 {
251 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
252 u32 in[MLX5_ST_SZ_DW(ptys_reg)];
253 u8 an_disable_admin;
254 u8 an_disable_cap;
255 u8 an_status;
256
257 mlx5_query_port_autoneg(dev, proto_mask, &an_status,
258 &an_disable_cap, &an_disable_admin);
259 if (!an_disable_cap && an_disable)
260 return -EPERM;
261
262 memset(in, 0, sizeof(in));
263
264 MLX5_SET(ptys_reg, in, local_port, 1);
265 MLX5_SET(ptys_reg, in, an_disable_admin, an_disable);
266 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
267 if (proto_mask == MLX5_PTYS_EN)
268 MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
269 else
270 MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
271
272 return mlx5_core_access_reg(dev, in, sizeof(in), out,
273 sizeof(out), MLX5_REG_PTYS, 0, 1);
274 }
275 EXPORT_SYMBOL_GPL(mlx5_set_port_ptys);
276
277 /* This function should be used after setting a port register only */
278 void mlx5_toggle_port_link(struct mlx5_core_dev *dev)
279 {
280 enum mlx5_port_status ps;
281
282 mlx5_query_port_admin_status(dev, &ps);
283 mlx5_set_port_admin_status(dev, MLX5_PORT_DOWN);
284 if (ps == MLX5_PORT_UP)
285 mlx5_set_port_admin_status(dev, MLX5_PORT_UP);
286 }
287 EXPORT_SYMBOL_GPL(mlx5_toggle_port_link);
288
289 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
290 enum mlx5_port_status status)
291 {
292 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
293 u32 out[MLX5_ST_SZ_DW(paos_reg)];
294
295 MLX5_SET(paos_reg, in, local_port, 1);
296 MLX5_SET(paos_reg, in, admin_status, status);
297 MLX5_SET(paos_reg, in, ase, 1);
298 return mlx5_core_access_reg(dev, in, sizeof(in), out,
299 sizeof(out), MLX5_REG_PAOS, 0, 1);
300 }
301 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
302
303 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
304 enum mlx5_port_status *status)
305 {
306 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
307 u32 out[MLX5_ST_SZ_DW(paos_reg)];
308 int err;
309
310 MLX5_SET(paos_reg, in, local_port, 1);
311 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
312 sizeof(out), MLX5_REG_PAOS, 0, 0);
313 if (err)
314 return err;
315 *status = MLX5_GET(paos_reg, out, admin_status);
316 return 0;
317 }
318 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
319
320 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu,
321 u16 *max_mtu, u16 *oper_mtu, u8 port)
322 {
323 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
324 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
325
326 MLX5_SET(pmtu_reg, in, local_port, port);
327 mlx5_core_access_reg(dev, in, sizeof(in), out,
328 sizeof(out), MLX5_REG_PMTU, 0, 0);
329
330 if (max_mtu)
331 *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
332 if (oper_mtu)
333 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
334 if (admin_mtu)
335 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
336 }
337
338 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
339 {
340 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
341 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
342
343 MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
344 MLX5_SET(pmtu_reg, in, local_port, port);
345 return mlx5_core_access_reg(dev, in, sizeof(in), out,
346 sizeof(out), MLX5_REG_PMTU, 0, 1);
347 }
348 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
349
350 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu,
351 u8 port)
352 {
353 mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
354 }
355 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
356
357 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
358 u8 port)
359 {
360 mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
361 }
362 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
363
364 static int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num)
365 {
366 u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0};
367 u32 out[MLX5_ST_SZ_DW(pmlp_reg)];
368 int module_mapping;
369 int err;
370
371 MLX5_SET(pmlp_reg, in, local_port, 1);
372 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
373 MLX5_REG_PMLP, 0, 0);
374 if (err)
375 return err;
376
377 module_mapping = MLX5_GET(pmlp_reg, out, lane0_module_mapping);
378 *module_num = module_mapping & MLX5_EEPROM_IDENTIFIER_BYTE_MASK;
379
380 return 0;
381 }
382
383 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
384 u16 offset, u16 size, u8 *data)
385 {
386 u32 out[MLX5_ST_SZ_DW(mcia_reg)];
387 u32 in[MLX5_ST_SZ_DW(mcia_reg)];
388 int module_num;
389 u16 i2c_addr;
390 int status;
391 int err;
392 void *ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
393
394 err = mlx5_query_module_num(dev, &module_num);
395 if (err)
396 return err;
397
398 memset(in, 0, sizeof(in));
399 size = min_t(int, size, MLX5_EEPROM_MAX_BYTES);
400
401 if (offset < MLX5_EEPROM_PAGE_LENGTH &&
402 offset + size > MLX5_EEPROM_PAGE_LENGTH)
403 /* Cross pages read, read until offset 256 in low page */
404 size -= offset + size - MLX5_EEPROM_PAGE_LENGTH;
405
406 i2c_addr = MLX5_I2C_ADDR_LOW;
407 if (offset >= MLX5_EEPROM_PAGE_LENGTH) {
408 i2c_addr = MLX5_I2C_ADDR_HIGH;
409 offset -= MLX5_EEPROM_PAGE_LENGTH;
410 }
411
412 MLX5_SET(mcia_reg, in, l, 0);
413 MLX5_SET(mcia_reg, in, module, module_num);
414 MLX5_SET(mcia_reg, in, i2c_device_address, i2c_addr);
415 MLX5_SET(mcia_reg, in, page_number, 0);
416 MLX5_SET(mcia_reg, in, device_address, offset);
417 MLX5_SET(mcia_reg, in, size, size);
418
419 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
420 sizeof(out), MLX5_REG_MCIA, 0, 0);
421 if (err)
422 return err;
423
424 status = MLX5_GET(mcia_reg, out, status);
425 if (status) {
426 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
427 status);
428 return -EIO;
429 }
430
431 memcpy(data, ptr, size);
432
433 return size;
434 }
435 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom);
436
437 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
438 int pvlc_size, u8 local_port)
439 {
440 u32 in[MLX5_ST_SZ_DW(pvlc_reg)] = {0};
441
442 MLX5_SET(pvlc_reg, in, local_port, local_port);
443 return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
444 pvlc_size, MLX5_REG_PVLC, 0, 0);
445 }
446
447 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
448 u8 *vl_hw_cap, u8 local_port)
449 {
450 u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
451 int err;
452
453 err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
454 if (err)
455 return err;
456
457 *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
458
459 return 0;
460 }
461 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
462
463 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
464 u8 port_num, void *out, size_t sz)
465 {
466 u32 *in;
467 int err;
468
469 in = kvzalloc(sz, GFP_KERNEL);
470 if (!in) {
471 err = -ENOMEM;
472 return err;
473 }
474
475 MLX5_SET(ppcnt_reg, in, local_port, port_num);
476
477 MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
478 err = mlx5_core_access_reg(dev, in, sz, out,
479 sz, MLX5_REG_PPCNT, 0, 0);
480
481 kvfree(in);
482 return err;
483 }
484 EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);
485
486 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
487 {
488 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
489 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
490
491 MLX5_SET(pfcc_reg, in, local_port, 1);
492 MLX5_SET(pfcc_reg, in, pptx, tx_pause);
493 MLX5_SET(pfcc_reg, in, pprx, rx_pause);
494
495 return mlx5_core_access_reg(dev, in, sizeof(in), out,
496 sizeof(out), MLX5_REG_PFCC, 0, 1);
497 }
498 EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
499
500 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
501 u32 *rx_pause, u32 *tx_pause)
502 {
503 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
504 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
505 int err;
506
507 MLX5_SET(pfcc_reg, in, local_port, 1);
508 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
509 sizeof(out), MLX5_REG_PFCC, 0, 0);
510 if (err)
511 return err;
512
513 if (rx_pause)
514 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
515
516 if (tx_pause)
517 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
518
519 return 0;
520 }
521 EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
522
523 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
524 {
525 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
526 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
527
528 MLX5_SET(pfcc_reg, in, local_port, 1);
529 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
530 MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
531 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
532 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
533
534 return mlx5_core_access_reg(dev, in, sizeof(in), out,
535 sizeof(out), MLX5_REG_PFCC, 0, 1);
536 }
537 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
538
539 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
540 {
541 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
542 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
543 int err;
544
545 MLX5_SET(pfcc_reg, in, local_port, 1);
546 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
547 sizeof(out), MLX5_REG_PFCC, 0, 0);
548 if (err)
549 return err;
550
551 if (pfc_en_tx)
552 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
553
554 if (pfc_en_rx)
555 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
556
557 return 0;
558 }
559 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
560
561 void mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask,
562 u8 *an_status,
563 u8 *an_disable_cap, u8 *an_disable_admin)
564 {
565 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
566
567 *an_status = 0;
568 *an_disable_cap = 0;
569 *an_disable_admin = 0;
570
571 if (mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1))
572 return;
573
574 *an_status = MLX5_GET(ptys_reg, out, an_status);
575 *an_disable_cap = MLX5_GET(ptys_reg, out, an_disable_cap);
576 *an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
577 }
578 EXPORT_SYMBOL_GPL(mlx5_query_port_autoneg);
579
580 int mlx5_max_tc(struct mlx5_core_dev *mdev)
581 {
582 u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
583
584 return num_tc - 1;
585 }
586
587 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out)
588 {
589 u32 in[MLX5_ST_SZ_DW(dcbx_param)] = {0};
590
591 MLX5_SET(dcbx_param, in, port_number, 1);
592
593 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
594 sizeof(in), MLX5_REG_DCBX_PARAM, 0, 0);
595 }
596
597 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in)
598 {
599 u32 out[MLX5_ST_SZ_DW(dcbx_param)];
600
601 MLX5_SET(dcbx_param, in, port_number, 1);
602
603 return mlx5_core_access_reg(mdev, in, sizeof(out), out,
604 sizeof(out), MLX5_REG_DCBX_PARAM, 0, 1);
605 }
606
607 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
608 {
609 u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0};
610 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
611 int err;
612 int i;
613
614 for (i = 0; i < 8; i++) {
615 if (prio_tc[i] > mlx5_max_tc(mdev))
616 return -EINVAL;
617
618 MLX5_SET(qtct_reg, in, prio, i);
619 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
620
621 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
622 sizeof(out), MLX5_REG_QTCT, 0, 1);
623 if (err)
624 return err;
625 }
626
627 return 0;
628 }
629 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
630
631 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
632 u8 prio, u8 *tc)
633 {
634 u32 in[MLX5_ST_SZ_DW(qtct_reg)];
635 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
636 int err;
637
638 memset(in, 0, sizeof(in));
639 memset(out, 0, sizeof(out));
640
641 MLX5_SET(qtct_reg, in, port_number, 1);
642 MLX5_SET(qtct_reg, in, prio, prio);
643
644 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
645 sizeof(out), MLX5_REG_QTCT, 0, 0);
646 if (!err)
647 *tc = MLX5_GET(qtct_reg, out, tclass);
648
649 return err;
650 }
651 EXPORT_SYMBOL_GPL(mlx5_query_port_prio_tc);
652
653 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
654 int inlen)
655 {
656 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
657
658 if (!MLX5_CAP_GEN(mdev, ets))
659 return -EOPNOTSUPP;
660
661 return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
662 MLX5_REG_QETCR, 0, 1);
663 }
664
665 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
666 int outlen)
667 {
668 u32 in[MLX5_ST_SZ_DW(qtct_reg)];
669
670 if (!MLX5_CAP_GEN(mdev, ets))
671 return -EOPNOTSUPP;
672
673 memset(in, 0, sizeof(in));
674 return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
675 MLX5_REG_QETCR, 0, 0);
676 }
677
678 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
679 {
680 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
681 int i;
682
683 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
684 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
685 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
686 }
687
688 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
689 }
690 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
691
692 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
693 u8 tc, u8 *tc_group)
694 {
695 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
696 void *ets_tcn_conf;
697 int err;
698
699 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
700 if (err)
701 return err;
702
703 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
704 tc_configuration[tc]);
705
706 *tc_group = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
707 group);
708
709 return 0;
710 }
711 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_group);
712
713 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
714 {
715 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
716 int i;
717
718 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
719 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
720 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
721 }
722
723 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
724 }
725 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
726
727 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
728 u8 tc, u8 *bw_pct)
729 {
730 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
731 void *ets_tcn_conf;
732 int err;
733
734 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
735 if (err)
736 return err;
737
738 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
739 tc_configuration[tc]);
740
741 *bw_pct = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
742 bw_allocation);
743
744 return 0;
745 }
746 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_bw_alloc);
747
748 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
749 u8 *max_bw_value,
750 u8 *max_bw_units)
751 {
752 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
753 void *ets_tcn_conf;
754 int i;
755
756 MLX5_SET(qetc_reg, in, port_number, 1);
757
758 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
759 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
760
761 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
762 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
763 max_bw_units[i]);
764 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
765 max_bw_value[i]);
766 }
767
768 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
769 }
770 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
771
772 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
773 u8 *max_bw_value,
774 u8 *max_bw_units)
775 {
776 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
777 void *ets_tcn_conf;
778 int err;
779 int i;
780
781 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
782 if (err)
783 return err;
784
785 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
786 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
787
788 max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
789 max_bw_value);
790 max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
791 max_bw_units);
792 }
793
794 return 0;
795 }
796 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
797
798 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
799 {
800 u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {0};
801 u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)] = {0};
802
803 MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
804 MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
805 MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
806 return mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
807 }
808 EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
809
810 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
811 {
812 u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {0};
813 u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)] = {0};
814 int err;
815
816 MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
817 err = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
818 if (!err)
819 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
820
821 return err;
822 }
823 EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
824
825 static int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out,
826 int outlen)
827 {
828 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
829
830 MLX5_SET(pcmr_reg, in, local_port, 1);
831 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
832 outlen, MLX5_REG_PCMR, 0, 0);
833 }
834
835 static int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
836 {
837 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
838
839 return mlx5_core_access_reg(mdev, in, inlen, out,
840 sizeof(out), MLX5_REG_PCMR, 0, 1);
841 }
842
843 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
844 {
845 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
846
847 MLX5_SET(pcmr_reg, in, local_port, 1);
848 MLX5_SET(pcmr_reg, in, fcs_chk, enable);
849 return mlx5_set_ports_check(mdev, in, sizeof(in));
850 }
851
852 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
853 bool *enabled)
854 {
855 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
856 /* Default values for FW which do not support MLX5_REG_PCMR */
857 *supported = false;
858 *enabled = true;
859
860 if (!MLX5_CAP_GEN(mdev, ports_check))
861 return;
862
863 if (mlx5_query_ports_check(mdev, out, sizeof(out)))
864 return;
865
866 *supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
867 *enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));
868 }
869
870 static const char *mlx5_pme_status[MLX5_MODULE_STATUS_NUM] = {
871 "Cable plugged", /* MLX5_MODULE_STATUS_PLUGGED = 0x1 */
872 "Cable unplugged", /* MLX5_MODULE_STATUS_UNPLUGGED = 0x2 */
873 "Cable error", /* MLX5_MODULE_STATUS_ERROR = 0x3 */
874 };
875
876 static const char *mlx5_pme_error[MLX5_MODULE_EVENT_ERROR_NUM] = {
877 "Power budget exceeded",
878 "Long Range for non MLNX cable",
879 "Bus stuck(I2C or data shorted)",
880 "No EEPROM/retry timeout",
881 "Enforce part number list",
882 "Unknown identifier",
883 "High Temperature",
884 "Bad or shorted cable/module",
885 "Unknown status",
886 };
887
888 void mlx5_port_module_event(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe)
889 {
890 enum port_module_event_status_type module_status;
891 enum port_module_event_error_type error_type;
892 struct mlx5_eqe_port_module *module_event_eqe;
893 struct mlx5_priv *priv = &dev->priv;
894 u8 module_num;
895
896 module_event_eqe = &eqe->data.port_module;
897 module_num = module_event_eqe->module;
898 module_status = module_event_eqe->module_status &
899 PORT_MODULE_EVENT_MODULE_STATUS_MASK;
900 error_type = module_event_eqe->error_type &
901 PORT_MODULE_EVENT_ERROR_TYPE_MASK;
902
903 if (module_status < MLX5_MODULE_STATUS_ERROR) {
904 priv->pme_stats.status_counters[module_status - 1]++;
905 } else if (module_status == MLX5_MODULE_STATUS_ERROR) {
906 if (error_type >= MLX5_MODULE_EVENT_ERROR_UNKNOWN)
907 /* Unknown error type */
908 error_type = MLX5_MODULE_EVENT_ERROR_UNKNOWN;
909 priv->pme_stats.error_counters[error_type]++;
910 }
911
912 if (!printk_ratelimit())
913 return;
914
915 if (module_status < MLX5_MODULE_STATUS_ERROR)
916 mlx5_core_info(dev,
917 "Port module event: module %u, %s\n",
918 module_num, mlx5_pme_status[module_status - 1]);
919
920 else if (module_status == MLX5_MODULE_STATUS_ERROR)
921 mlx5_core_info(dev,
922 "Port module event[error]: module %u, %s, %s\n",
923 module_num, mlx5_pme_status[module_status - 1],
924 mlx5_pme_error[error_type]);
925 }
926
927 int mlx5_query_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
928 {
929 u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
930
931 return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,
932 mtpps_size, MLX5_REG_MTPPS, 0, 0);
933 }
934
935 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
936 {
937 u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
938
939 return mlx5_core_access_reg(mdev, mtpps, mtpps_size, out,
940 sizeof(out), MLX5_REG_MTPPS, 0, 1);
941 }
942
943 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode)
944 {
945 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
946 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
947 int err = 0;
948
949 MLX5_SET(mtppse_reg, in, pin, pin);
950
951 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
952 sizeof(out), MLX5_REG_MTPPSE, 0, 0);
953 if (err)
954 return err;
955
956 *arm = MLX5_GET(mtppse_reg, in, event_arm);
957 *mode = MLX5_GET(mtppse_reg, in, event_generation_mode);
958
959 return err;
960 }
961
962 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode)
963 {
964 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
965 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
966
967 MLX5_SET(mtppse_reg, in, pin, pin);
968 MLX5_SET(mtppse_reg, in, event_arm, arm);
969 MLX5_SET(mtppse_reg, in, event_generation_mode, mode);
970
971 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
972 sizeof(out), MLX5_REG_MTPPSE, 0, 1);
973 }
974
975 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state)
976 {
977 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
978 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
979 int err;
980
981 MLX5_SET(qpts_reg, in, local_port, 1);
982 MLX5_SET(qpts_reg, in, trust_state, trust_state);
983
984 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
985 sizeof(out), MLX5_REG_QPTS, 0, 1);
986 return err;
987 }
988
989 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state)
990 {
991 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
992 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
993 int err;
994
995 MLX5_SET(qpts_reg, in, local_port, 1);
996
997 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
998 sizeof(out), MLX5_REG_QPTS, 0, 0);
999 if (!err)
1000 *trust_state = MLX5_GET(qpts_reg, out, trust_state);
1001
1002 return err;
1003 }
1004
1005 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio)
1006 {
1007 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
1008 void *qpdpm_dscp;
1009 void *out;
1010 void *in;
1011 int err;
1012
1013 in = kzalloc(sz, GFP_KERNEL);
1014 out = kzalloc(sz, GFP_KERNEL);
1015 if (!in || !out) {
1016 err = -ENOMEM;
1017 goto out;
1018 }
1019
1020 MLX5_SET(qpdpm_reg, in, local_port, 1);
1021 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
1022 if (err)
1023 goto out;
1024
1025 memcpy(in, out, sz);
1026 MLX5_SET(qpdpm_reg, in, local_port, 1);
1027
1028 /* Update the corresponding dscp entry */
1029 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, in, dscp[dscp]);
1030 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, prio, prio);
1031 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, e, 1);
1032 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 1);
1033
1034 out:
1035 kfree(in);
1036 kfree(out);
1037 return err;
1038 }
1039
1040 /* dscp2prio[i]: priority that dscp i mapped to */
1041 #define MLX5E_SUPPORTED_DSCP 64
1042 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio)
1043 {
1044 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
1045 void *qpdpm_dscp;
1046 void *out;
1047 void *in;
1048 int err;
1049 int i;
1050
1051 in = kzalloc(sz, GFP_KERNEL);
1052 out = kzalloc(sz, GFP_KERNEL);
1053 if (!in || !out) {
1054 err = -ENOMEM;
1055 goto out;
1056 }
1057
1058 MLX5_SET(qpdpm_reg, in, local_port, 1);
1059 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
1060 if (err)
1061 goto out;
1062
1063 for (i = 0; i < (MLX5E_SUPPORTED_DSCP); i++) {
1064 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, out, dscp[i]);
1065 dscp2prio[i] = MLX5_GET16(qpdpm_dscp_reg, qpdpm_dscp, prio);
1066 }
1067
1068 out:
1069 kfree(in);
1070 kfree(out);
1071 return err;
1072 }
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