1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2019, Mellanox Technologies */
8 MLX5DR_ACTION_MDFY_HW_FLD_L2_0
= 0,
9 MLX5DR_ACTION_MDFY_HW_FLD_L2_1
= 1,
10 MLX5DR_ACTION_MDFY_HW_FLD_L2_2
= 2,
11 MLX5DR_ACTION_MDFY_HW_FLD_L3_0
= 3,
12 MLX5DR_ACTION_MDFY_HW_FLD_L3_1
= 4,
13 MLX5DR_ACTION_MDFY_HW_FLD_L3_2
= 5,
14 MLX5DR_ACTION_MDFY_HW_FLD_L3_3
= 6,
15 MLX5DR_ACTION_MDFY_HW_FLD_L3_4
= 7,
16 MLX5DR_ACTION_MDFY_HW_FLD_L4_0
= 8,
17 MLX5DR_ACTION_MDFY_HW_FLD_L4_1
= 9,
18 MLX5DR_ACTION_MDFY_HW_FLD_MPLS
= 10,
19 MLX5DR_ACTION_MDFY_HW_FLD_L2_TNL_0
= 11,
20 MLX5DR_ACTION_MDFY_HW_FLD_REG_0
= 12,
21 MLX5DR_ACTION_MDFY_HW_FLD_REG_1
= 13,
22 MLX5DR_ACTION_MDFY_HW_FLD_REG_2
= 14,
23 MLX5DR_ACTION_MDFY_HW_FLD_REG_3
= 15,
24 MLX5DR_ACTION_MDFY_HW_FLD_L4_2
= 16,
25 MLX5DR_ACTION_MDFY_HW_FLD_FLEX_0
= 17,
26 MLX5DR_ACTION_MDFY_HW_FLD_FLEX_1
= 18,
27 MLX5DR_ACTION_MDFY_HW_FLD_FLEX_2
= 19,
28 MLX5DR_ACTION_MDFY_HW_FLD_FLEX_3
= 20,
29 MLX5DR_ACTION_MDFY_HW_FLD_L2_TNL_1
= 21,
30 MLX5DR_ACTION_MDFY_HW_FLD_METADATA
= 22,
31 MLX5DR_ACTION_MDFY_HW_FLD_RESERVED
= 23,
35 MLX5DR_ACTION_MDFY_HW_OP_SET
= 0x2,
36 MLX5DR_ACTION_MDFY_HW_OP_ADD
= 0x3,
40 MLX5DR_ACTION_MDFY_HW_HDR_L3_NONE
= 0x0,
41 MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4
= 0x1,
42 MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6
= 0x2,
46 MLX5DR_ACTION_MDFY_HW_HDR_L4_NONE
= 0x0,
47 MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP
= 0x1,
48 MLX5DR_ACTION_MDFY_HW_HDR_L4_UDP
= 0x2,
52 MLX5DR_STE_LU_TYPE_NOP
= 0x00,
53 MLX5DR_STE_LU_TYPE_SRC_GVMI_AND_QP
= 0x05,
54 MLX5DR_STE_LU_TYPE_ETHL2_TUNNELING_I
= 0x0a,
55 MLX5DR_STE_LU_TYPE_ETHL2_DST_O
= 0x06,
56 MLX5DR_STE_LU_TYPE_ETHL2_DST_I
= 0x07,
57 MLX5DR_STE_LU_TYPE_ETHL2_DST_D
= 0x1b,
58 MLX5DR_STE_LU_TYPE_ETHL2_SRC_O
= 0x08,
59 MLX5DR_STE_LU_TYPE_ETHL2_SRC_I
= 0x09,
60 MLX5DR_STE_LU_TYPE_ETHL2_SRC_D
= 0x1c,
61 MLX5DR_STE_LU_TYPE_ETHL2_SRC_DST_O
= 0x36,
62 MLX5DR_STE_LU_TYPE_ETHL2_SRC_DST_I
= 0x37,
63 MLX5DR_STE_LU_TYPE_ETHL2_SRC_DST_D
= 0x38,
64 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_DST_O
= 0x0d,
65 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_DST_I
= 0x0e,
66 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_DST_D
= 0x1e,
67 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_SRC_O
= 0x0f,
68 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_SRC_I
= 0x10,
69 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_SRC_D
= 0x1f,
70 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_5_TUPLE_O
= 0x11,
71 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_5_TUPLE_I
= 0x12,
72 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_5_TUPLE_D
= 0x20,
73 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_MISC_O
= 0x29,
74 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_MISC_I
= 0x2a,
75 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_MISC_D
= 0x2b,
76 MLX5DR_STE_LU_TYPE_ETHL4_O
= 0x13,
77 MLX5DR_STE_LU_TYPE_ETHL4_I
= 0x14,
78 MLX5DR_STE_LU_TYPE_ETHL4_D
= 0x21,
79 MLX5DR_STE_LU_TYPE_ETHL4_MISC_O
= 0x2c,
80 MLX5DR_STE_LU_TYPE_ETHL4_MISC_I
= 0x2d,
81 MLX5DR_STE_LU_TYPE_ETHL4_MISC_D
= 0x2e,
82 MLX5DR_STE_LU_TYPE_MPLS_FIRST_O
= 0x15,
83 MLX5DR_STE_LU_TYPE_MPLS_FIRST_I
= 0x24,
84 MLX5DR_STE_LU_TYPE_MPLS_FIRST_D
= 0x25,
85 MLX5DR_STE_LU_TYPE_GRE
= 0x16,
86 MLX5DR_STE_LU_TYPE_FLEX_PARSER_0
= 0x22,
87 MLX5DR_STE_LU_TYPE_FLEX_PARSER_1
= 0x23,
88 MLX5DR_STE_LU_TYPE_FLEX_PARSER_TNL_HEADER
= 0x19,
89 MLX5DR_STE_LU_TYPE_GENERAL_PURPOSE
= 0x18,
90 MLX5DR_STE_LU_TYPE_STEERING_REGISTERS_0
= 0x2f,
91 MLX5DR_STE_LU_TYPE_STEERING_REGISTERS_1
= 0x30,
92 MLX5DR_STE_LU_TYPE_DONT_CARE
= 0x0f,
95 enum mlx5dr_ste_entry_type
{
96 MLX5DR_STE_TYPE_TX
= 1,
97 MLX5DR_STE_TYPE_RX
= 2,
98 MLX5DR_STE_TYPE_MODIFY_PKT
= 6,
101 struct mlx5_ifc_ste_general_bits
{
103 u8 reserved_at_4
[0x4];
104 u8 entry_sub_type
[0x8];
107 u8 next_table_base_63_48
[0x10];
108 u8 next_lu_type
[0x8];
109 u8 next_table_base_39_32_size
[0x8];
111 u8 next_table_base_31_5_size
[0x1b];
112 u8 linear_hash_enable
[0x1];
113 u8 reserved_at_5c
[0x2];
114 u8 next_table_rank
[0x2];
116 u8 reserved_at_60
[0xa0];
121 struct mlx5_ifc_ste_sx_transmit_bits
{
123 u8 reserved_at_4
[0x4];
124 u8 entry_sub_type
[0x8];
127 u8 next_table_base_63_48
[0x10];
128 u8 next_lu_type
[0x8];
129 u8 next_table_base_39_32_size
[0x8];
131 u8 next_table_base_31_5_size
[0x1b];
132 u8 linear_hash_enable
[0x1];
133 u8 reserved_at_5c
[0x2];
134 u8 next_table_rank
[0x2];
139 u8 sx_wire_enable
[0x1];
140 u8 sx_func_lb_enable
[0x1];
141 u8 sx_sniffer_enable
[0x1];
143 u8 reserved_at_69
[0x1];
144 u8 action_description
[0x6];
147 u8 encap_pointer_vlan_data
[0x20];
149 u8 loopback_syndome_en
[0x8];
150 u8 loopback_syndome
[0x8];
151 u8 counter_trigger
[0x10];
153 u8 miss_address_63_48
[0x10];
154 u8 counter_trigger_23_16
[0x8];
155 u8 miss_address_39_32
[0x8];
157 u8 miss_address_31_6
[0x1a];
158 u8 learning_point
[0x1];
160 u8 match_polarity
[0x1];
165 struct mlx5_ifc_ste_rx_steering_mult_bits
{
167 u8 reserved_at_4
[0x4];
168 u8 entry_sub_type
[0x8];
171 u8 next_table_base_63_48
[0x10];
172 u8 next_lu_type
[0x8];
173 u8 next_table_base_39_32_size
[0x8];
175 u8 next_table_base_31_5_size
[0x1b];
176 u8 linear_hash_enable
[0x1];
177 u8 reserved_at_
[0x2];
178 u8 next_table_rank
[0x2];
180 u8 member_count
[0x10];
183 u8 qp_list_pointer
[0x20];
185 u8 reserved_at_a0
[0x1];
186 u8 tunneling_action
[0x3];
187 u8 action_description
[0x4];
188 u8 reserved_at_a8
[0x8];
189 u8 counter_trigger_15_0
[0x10];
191 u8 miss_address_63_48
[0x10];
192 u8 counter_trigger_23_16
[0x08];
193 u8 miss_address_39_32
[0x8];
195 u8 miss_address_31_6
[0x1a];
196 u8 learning_point
[0x1];
197 u8 fail_on_error
[0x1];
198 u8 match_polarity
[0x1];
203 struct mlx5_ifc_ste_modify_packet_bits
{
205 u8 reserved_at_4
[0x4];
206 u8 entry_sub_type
[0x8];
209 u8 next_table_base_63_48
[0x10];
210 u8 next_lu_type
[0x8];
211 u8 next_table_base_39_32_size
[0x8];
213 u8 next_table_base_31_5_size
[0x1b];
214 u8 linear_hash_enable
[0x1];
215 u8 reserved_at_
[0x2];
216 u8 next_table_rank
[0x2];
218 u8 number_of_re_write_actions
[0x10];
221 u8 header_re_write_actions_pointer
[0x20];
223 u8 reserved_at_a0
[0x1];
224 u8 tunneling_action
[0x3];
225 u8 action_description
[0x4];
226 u8 reserved_at_a8
[0x8];
227 u8 counter_trigger_15_0
[0x10];
229 u8 miss_address_63_48
[0x10];
230 u8 counter_trigger_23_16
[0x08];
231 u8 miss_address_39_32
[0x8];
233 u8 miss_address_31_6
[0x1a];
234 u8 learning_point
[0x1];
235 u8 fail_on_error
[0x1];
236 u8 match_polarity
[0x1];
241 struct mlx5_ifc_ste_eth_l2_src_bits
{
245 u8 l3_ethertype
[0x10];
248 u8 ethertype_filter
[0x1];
249 u8 reserved_at_43
[0x1];
252 u8 functional_lb
[0x1];
254 u8 reserved_at_48
[0x4];
255 u8 first_priority
[0x3];
257 u8 first_vlan_qualifier
[0x2];
258 u8 reserved_at_52
[0x2];
259 u8 first_vlan_id
[0xc];
261 u8 ip_fragmented
[0x1];
266 u8 reserved_at_68
[0x4];
267 u8 second_priority
[0x3];
269 u8 second_vlan_qualifier
[0x2];
270 u8 reserved_at_72
[0x2];
271 u8 second_vlan_id
[0xc];
274 struct mlx5_ifc_ste_eth_l2_dst_bits
{
278 u8 l3_ethertype
[0x10];
281 u8 ethertype_filter
[0x1];
282 u8 reserved_at_43
[0x1];
285 u8 functional_lb
[0x1];
287 u8 reserved_at_48
[0x4];
288 u8 first_priority
[0x3];
290 u8 first_vlan_qualifier
[0x2];
291 u8 reserved_at_52
[0x2];
292 u8 first_vlan_id
[0xc];
294 u8 ip_fragmented
[0x1];
299 u8 reserved_at_68
[0x4];
300 u8 second_priority
[0x3];
302 u8 second_vlan_qualifier
[0x2];
303 u8 reserved_at_72
[0x2];
304 u8 second_vlan_id
[0xc];
307 struct mlx5_ifc_ste_eth_l2_src_dst_bits
{
317 u8 functional_lb
[0x1];
320 u8 reserved_at_66
[0x6];
321 u8 first_priority
[0x3];
323 u8 first_vlan_qualifier
[0x2];
324 u8 reserved_at_72
[0x2];
325 u8 first_vlan_id
[0xc];
328 struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_bits
{
329 u8 destination_address
[0x20];
331 u8 source_address
[0x20];
333 u8 source_port
[0x10];
334 u8 destination_port
[0x10];
337 u8 first_fragment
[0x1];
338 u8 reserved_at_62
[0x2];
339 u8 reserved_at_64
[0x1];
351 u8 reserved_at_76
[0x2];
355 struct mlx5_ifc_ste_eth_l3_ipv6_dst_bits
{
356 u8 dst_ip_127_96
[0x20];
358 u8 dst_ip_95_64
[0x20];
360 u8 dst_ip_63_32
[0x20];
362 u8 dst_ip_31_0
[0x20];
365 struct mlx5_ifc_ste_eth_l2_tnl_bits
{
369 u8 l3_ethertype
[0x10];
371 u8 l2_tunneling_network_id
[0x20];
373 u8 ip_fragmented
[0x1];
378 u8 first_priority
[0x3];
380 u8 reserved_at_6c
[0x3];
381 u8 gre_key_flag
[0x1];
382 u8 first_vlan_qualifier
[0x2];
383 u8 reserved_at_72
[0x2];
384 u8 first_vlan_id
[0xc];
387 struct mlx5_ifc_ste_eth_l3_ipv6_src_bits
{
388 u8 src_ip_127_96
[0x20];
390 u8 src_ip_95_64
[0x20];
392 u8 src_ip_63_32
[0x20];
394 u8 src_ip_31_0
[0x20];
397 struct mlx5_ifc_ste_eth_l3_ipv4_misc_bits
{
400 u8 reserved_at_8
[0x8];
401 u8 total_length
[0x10];
403 u8 identification
[0x10];
405 u8 fragment_offset
[0xd];
407 u8 time_to_live
[0x8];
408 u8 reserved_at_48
[0x8];
411 u8 reserved_at_60
[0x20];
414 struct mlx5_ifc_ste_eth_l4_bits
{
416 u8 first_fragment
[0x1];
417 u8 reserved_at_2
[0x6];
421 u8 ipv6_version
[0x4];
422 u8 reserved_at_24
[0x1];
435 u8 ipv6_payload_length
[0x10];
436 u8 ipv6_hop_limit
[0x8];
438 u8 reserved_at_5e
[0x2];
440 u8 tcp_data_offset
[0x4];
441 u8 reserved_at_64
[0x8];
445 struct mlx5_ifc_ste_eth_l4_misc_bits
{
453 u8 urgent_pointer
[0x10];
454 u8 window_size
[0x10];
457 struct mlx5_ifc_ste_mpls_bits
{
458 u8 mpls0_label
[0x14];
463 u8 mpls1_label
[0x20];
465 u8 mpls2_label
[0x20];
467 u8 reserved_at_60
[0x16];
469 u8 mpls4_qualifier
[0x1];
471 u8 mpls3_qualifier
[0x1];
473 u8 mpls2_qualifier
[0x1];
475 u8 mpls1_qualifier
[0x1];
477 u8 mpls0_qualifier
[0x1];
480 struct mlx5_ifc_ste_register_0_bits
{
481 u8 register_0_h
[0x20];
483 u8 register_0_l
[0x20];
485 u8 register_1_h
[0x20];
487 u8 register_1_l
[0x20];
490 struct mlx5_ifc_ste_register_1_bits
{
491 u8 register_2_h
[0x20];
493 u8 register_2_l
[0x20];
495 u8 register_3_h
[0x20];
497 u8 register_3_l
[0x20];
500 struct mlx5_ifc_ste_gre_bits
{
501 u8 gre_c_present
[0x1];
502 u8 reserved_at_30
[0x1];
503 u8 gre_k_present
[0x1];
504 u8 gre_s_present
[0x1];
505 u8 strict_src_route
[0x1];
509 u8 gre_protocol
[0x10];
520 struct mlx5_ifc_ste_flex_parser_0_bits
{
521 u8 parser_3_label
[0x14];
522 u8 parser_3_exp
[0x3];
523 u8 parser_3_s_bos
[0x1];
524 u8 parser_3_ttl
[0x8];
526 u8 flex_parser_2
[0x20];
528 u8 flex_parser_1
[0x20];
530 u8 flex_parser_0
[0x20];
533 struct mlx5_ifc_ste_flex_parser_1_bits
{
534 u8 flex_parser_7
[0x20];
536 u8 flex_parser_6
[0x20];
538 u8 flex_parser_5
[0x20];
540 u8 flex_parser_4
[0x20];
543 struct mlx5_ifc_ste_flex_parser_tnl_bits
{
544 u8 flex_parser_tunneling_header_63_32
[0x20];
546 u8 flex_parser_tunneling_header_31_0
[0x20];
548 u8 reserved_at_40
[0x40];
551 struct mlx5_ifc_ste_flex_parser_tnl_vxlan_gpe_bits
{
552 u8 outer_vxlan_gpe_flags
[0x8];
553 u8 reserved_at_8
[0x10];
554 u8 outer_vxlan_gpe_next_protocol
[0x8];
556 u8 outer_vxlan_gpe_vni
[0x18];
557 u8 reserved_at_38
[0x8];
559 u8 reserved_at_40
[0x40];
562 struct mlx5_ifc_ste_flex_parser_tnl_geneve_bits
{
563 u8 reserved_at_0
[0x2];
564 u8 geneve_opt_len
[0x6];
566 u8 reserved_at_9
[0x7];
567 u8 geneve_protocol_type
[0x10];
570 u8 reserved_at_38
[0x8];
572 u8 reserved_at_40
[0x40];
575 struct mlx5_ifc_ste_general_purpose_bits
{
576 u8 general_purpose_lookup_field
[0x20];
578 u8 reserved_at_20
[0x20];
580 u8 reserved_at_40
[0x20];
582 u8 reserved_at_60
[0x20];
585 struct mlx5_ifc_ste_src_gvmi_qp_bits
{
586 u8 loopback_syndrome
[0x8];
587 u8 reserved_at_8
[0x8];
588 u8 source_gvmi
[0x10];
590 u8 reserved_at_20
[0x5];
592 u8 functional_lb
[0x1];
593 u8 source_is_requestor
[0x1];
596 u8 reserved_at_40
[0x20];
598 u8 reserved_at_60
[0x20];
601 struct mlx5_ifc_l2_hdr_bits
{
613 u8 reserved_at_90
[0x10];
616 /* Both HW set and HW add share the same HW format with different opcodes */
617 struct mlx5_ifc_dr_action_hw_set_bits
{
619 u8 destination_field_code
[0x8];
620 u8 reserved_at_10
[0x2];
621 u8 destination_left_shifter
[0x6];
622 u8 reserved_at_18
[0x3];
623 u8 destination_length
[0x5];
625 u8 inline_data
[0x20];
628 #endif /* MLX5_IFC_DR_H */