2 * drivers/net/ethernet/mellanox/mlxsw/pci.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the names of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
18 * Alternatively, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") version 2 as published by the Free
20 * Software Foundation.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/export.h>
38 #include <linux/err.h>
39 #include <linux/device.h>
40 #include <linux/pci.h>
41 #include <linux/interrupt.h>
42 #include <linux/wait.h>
43 #include <linux/types.h>
44 #include <linux/skbuff.h>
45 #include <linux/if_vlan.h>
46 #include <linux/log2.h>
47 #include <linux/string.h>
54 #include "resources.h"
56 static const char mlxsw_pci_driver_name
[] = "mlxsw_pci";
58 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
59 iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
60 #define mlxsw_pci_read32(mlxsw_pci, reg) \
61 ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
63 enum mlxsw_pci_queue_type
{
64 MLXSW_PCI_QUEUE_TYPE_SDQ
,
65 MLXSW_PCI_QUEUE_TYPE_RDQ
,
66 MLXSW_PCI_QUEUE_TYPE_CQ
,
67 MLXSW_PCI_QUEUE_TYPE_EQ
,
70 #define MLXSW_PCI_QUEUE_TYPE_COUNT 4
72 static const u16 mlxsw_pci_doorbell_type_offset
[] = {
73 MLXSW_PCI_DOORBELL_SDQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
74 MLXSW_PCI_DOORBELL_RDQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
75 MLXSW_PCI_DOORBELL_CQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
76 MLXSW_PCI_DOORBELL_EQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
79 static const u16 mlxsw_pci_doorbell_arm_type_offset
[] = {
82 MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
83 MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
86 struct mlxsw_pci_mem_item
{
92 struct mlxsw_pci_queue_elem_info
{
93 char *elem
; /* pointer to actual dma mapped element mem chunk */
104 struct mlxsw_pci_queue
{
105 spinlock_t lock
; /* for queue accesses */
106 struct mlxsw_pci_mem_item mem_item
;
107 struct mlxsw_pci_queue_elem_info
*elem_info
;
108 u16 producer_counter
;
109 u16 consumer_counter
;
110 u16 count
; /* number of elements in queue */
111 u8 num
; /* queue number */
112 u8 elem_size
; /* size of one element */
113 enum mlxsw_pci_queue_type type
;
114 struct tasklet_struct tasklet
; /* queue processing tasklet */
115 struct mlxsw_pci
*pci
;
129 struct mlxsw_pci_queue_type_group
{
130 struct mlxsw_pci_queue
*q
;
131 u8 count
; /* number of queues in group */
135 struct pci_dev
*pdev
;
137 struct mlxsw_pci_queue_type_group queues
[MLXSW_PCI_QUEUE_TYPE_COUNT
];
139 struct mlxsw_core
*core
;
141 struct mlxsw_pci_mem_item
*items
;
145 struct mlxsw_pci_mem_item out_mbox
;
146 struct mlxsw_pci_mem_item in_mbox
;
147 struct mutex lock
; /* Lock access to command registers */
149 wait_queue_head_t wait
;
156 struct mlxsw_bus_info bus_info
;
159 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue
*q
)
161 tasklet_schedule(&q
->tasklet
);
164 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue
*q
,
165 size_t elem_size
, int elem_index
)
167 return q
->mem_item
.buf
+ (elem_size
* elem_index
);
170 static struct mlxsw_pci_queue_elem_info
*
171 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue
*q
, int elem_index
)
173 return &q
->elem_info
[elem_index
];
176 static struct mlxsw_pci_queue_elem_info
*
177 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue
*q
)
179 int index
= q
->producer_counter
& (q
->count
- 1);
181 if ((u16
) (q
->producer_counter
- q
->consumer_counter
) == q
->count
)
183 return mlxsw_pci_queue_elem_info_get(q
, index
);
186 static struct mlxsw_pci_queue_elem_info
*
187 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue
*q
)
189 int index
= q
->consumer_counter
& (q
->count
- 1);
191 return mlxsw_pci_queue_elem_info_get(q
, index
);
194 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue
*q
, int elem_index
)
196 return mlxsw_pci_queue_elem_info_get(q
, elem_index
)->elem
;
199 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue
*q
, bool owner_bit
)
201 return owner_bit
!= !!(q
->consumer_counter
& q
->count
);
205 mlxsw_pci_queue_sw_elem_get(struct mlxsw_pci_queue
*q
,
206 u32 (*get_elem_owner_func
)(const char *))
208 struct mlxsw_pci_queue_elem_info
*elem_info
;
212 elem_info
= mlxsw_pci_queue_elem_info_consumer_get(q
);
213 elem
= elem_info
->elem
;
214 owner_bit
= get_elem_owner_func(elem
);
215 if (mlxsw_pci_elem_hw_owned(q
, owner_bit
))
217 q
->consumer_counter
++;
218 rmb(); /* make sure we read owned bit before the rest of elem */
222 static struct mlxsw_pci_queue_type_group
*
223 mlxsw_pci_queue_type_group_get(struct mlxsw_pci
*mlxsw_pci
,
224 enum mlxsw_pci_queue_type q_type
)
226 return &mlxsw_pci
->queues
[q_type
];
229 static u8
__mlxsw_pci_queue_count(struct mlxsw_pci
*mlxsw_pci
,
230 enum mlxsw_pci_queue_type q_type
)
232 struct mlxsw_pci_queue_type_group
*queue_group
;
234 queue_group
= mlxsw_pci_queue_type_group_get(mlxsw_pci
, q_type
);
235 return queue_group
->count
;
238 static u8
mlxsw_pci_sdq_count(struct mlxsw_pci
*mlxsw_pci
)
240 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_SDQ
);
243 static u8
mlxsw_pci_cq_count(struct mlxsw_pci
*mlxsw_pci
)
245 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_CQ
);
248 static struct mlxsw_pci_queue
*
249 __mlxsw_pci_queue_get(struct mlxsw_pci
*mlxsw_pci
,
250 enum mlxsw_pci_queue_type q_type
, u8 q_num
)
252 return &mlxsw_pci
->queues
[q_type
].q
[q_num
];
255 static struct mlxsw_pci_queue
*mlxsw_pci_sdq_get(struct mlxsw_pci
*mlxsw_pci
,
258 return __mlxsw_pci_queue_get(mlxsw_pci
,
259 MLXSW_PCI_QUEUE_TYPE_SDQ
, q_num
);
262 static struct mlxsw_pci_queue
*mlxsw_pci_rdq_get(struct mlxsw_pci
*mlxsw_pci
,
265 return __mlxsw_pci_queue_get(mlxsw_pci
,
266 MLXSW_PCI_QUEUE_TYPE_RDQ
, q_num
);
269 static struct mlxsw_pci_queue
*mlxsw_pci_cq_get(struct mlxsw_pci
*mlxsw_pci
,
272 return __mlxsw_pci_queue_get(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_CQ
, q_num
);
275 static struct mlxsw_pci_queue
*mlxsw_pci_eq_get(struct mlxsw_pci
*mlxsw_pci
,
278 return __mlxsw_pci_queue_get(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_EQ
, q_num
);
281 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci
*mlxsw_pci
,
282 struct mlxsw_pci_queue
*q
,
285 mlxsw_pci_write32(mlxsw_pci
,
286 DOORBELL(mlxsw_pci
->doorbell_offset
,
287 mlxsw_pci_doorbell_type_offset
[q
->type
],
291 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci
*mlxsw_pci
,
292 struct mlxsw_pci_queue
*q
,
295 mlxsw_pci_write32(mlxsw_pci
,
296 DOORBELL(mlxsw_pci
->doorbell_offset
,
297 mlxsw_pci_doorbell_arm_type_offset
[q
->type
],
301 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci
*mlxsw_pci
,
302 struct mlxsw_pci_queue
*q
)
304 wmb(); /* ensure all writes are done before we ring a bell */
305 __mlxsw_pci_queue_doorbell_set(mlxsw_pci
, q
, q
->producer_counter
);
308 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci
*mlxsw_pci
,
309 struct mlxsw_pci_queue
*q
)
311 wmb(); /* ensure all writes are done before we ring a bell */
312 __mlxsw_pci_queue_doorbell_set(mlxsw_pci
, q
,
313 q
->consumer_counter
+ q
->count
);
317 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci
*mlxsw_pci
,
318 struct mlxsw_pci_queue
*q
)
320 wmb(); /* ensure all writes are done before we ring a bell */
321 __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci
, q
, q
->consumer_counter
);
324 static dma_addr_t
__mlxsw_pci_queue_page_get(struct mlxsw_pci_queue
*q
,
327 return q
->mem_item
.mapaddr
+ MLXSW_PCI_PAGE_SIZE
* page_index
;
330 static int mlxsw_pci_sdq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
331 struct mlxsw_pci_queue
*q
)
336 q
->producer_counter
= 0;
337 q
->consumer_counter
= 0;
339 /* Set CQ of same number of this SDQ. */
340 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox
, q
->num
);
341 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox
, 3);
342 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox
, 3); /* 8 pages */
343 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
344 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
346 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox
, i
, mapaddr
);
349 err
= mlxsw_cmd_sw2hw_sdq(mlxsw_pci
->core
, mbox
, q
->num
);
352 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
356 static void mlxsw_pci_sdq_fini(struct mlxsw_pci
*mlxsw_pci
,
357 struct mlxsw_pci_queue
*q
)
359 mlxsw_cmd_hw2sw_sdq(mlxsw_pci
->core
, q
->num
);
362 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci
*mlxsw_pci
, char *wqe
,
363 int index
, char *frag_data
, size_t frag_len
,
366 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
369 mapaddr
= pci_map_single(pdev
, frag_data
, frag_len
, direction
);
370 if (unlikely(pci_dma_mapping_error(pdev
, mapaddr
))) {
371 dev_err_ratelimited(&pdev
->dev
, "failed to dma map tx frag\n");
374 mlxsw_pci_wqe_address_set(wqe
, index
, mapaddr
);
375 mlxsw_pci_wqe_byte_count_set(wqe
, index
, frag_len
);
379 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci
*mlxsw_pci
, char *wqe
,
380 int index
, int direction
)
382 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
383 size_t frag_len
= mlxsw_pci_wqe_byte_count_get(wqe
, index
);
384 dma_addr_t mapaddr
= mlxsw_pci_wqe_address_get(wqe
, index
);
388 pci_unmap_single(pdev
, mapaddr
, frag_len
, direction
);
391 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci
*mlxsw_pci
,
392 struct mlxsw_pci_queue_elem_info
*elem_info
)
394 size_t buf_len
= MLXSW_PORT_MAX_MTU
;
395 char *wqe
= elem_info
->elem
;
399 elem_info
->u
.rdq
.skb
= NULL
;
400 skb
= netdev_alloc_skb_ip_align(NULL
, buf_len
);
404 /* Assume that wqe was previously zeroed. */
406 err
= mlxsw_pci_wqe_frag_map(mlxsw_pci
, wqe
, 0, skb
->data
,
407 buf_len
, DMA_FROM_DEVICE
);
411 elem_info
->u
.rdq
.skb
= skb
;
415 dev_kfree_skb_any(skb
);
419 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci
*mlxsw_pci
,
420 struct mlxsw_pci_queue_elem_info
*elem_info
)
425 skb
= elem_info
->u
.rdq
.skb
;
426 wqe
= elem_info
->elem
;
428 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, 0, DMA_FROM_DEVICE
);
429 dev_kfree_skb_any(skb
);
432 static int mlxsw_pci_rdq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
433 struct mlxsw_pci_queue
*q
)
435 struct mlxsw_pci_queue_elem_info
*elem_info
;
436 u8 sdq_count
= mlxsw_pci_sdq_count(mlxsw_pci
);
440 q
->producer_counter
= 0;
441 q
->consumer_counter
= 0;
443 /* Set CQ of same number of this RDQ with base
444 * above SDQ count as the lower ones are assigned to SDQs.
446 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox
, sdq_count
+ q
->num
);
447 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox
, 3); /* 8 pages */
448 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
449 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
451 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox
, i
, mapaddr
);
454 err
= mlxsw_cmd_sw2hw_rdq(mlxsw_pci
->core
, mbox
, q
->num
);
458 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
460 for (i
= 0; i
< q
->count
; i
++) {
461 elem_info
= mlxsw_pci_queue_elem_info_producer_get(q
);
463 err
= mlxsw_pci_rdq_skb_alloc(mlxsw_pci
, elem_info
);
466 /* Everything is set up, ring doorbell to pass elem to HW */
467 q
->producer_counter
++;
468 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
474 for (i
--; i
>= 0; i
--) {
475 elem_info
= mlxsw_pci_queue_elem_info_get(q
, i
);
476 mlxsw_pci_rdq_skb_free(mlxsw_pci
, elem_info
);
478 mlxsw_cmd_hw2sw_rdq(mlxsw_pci
->core
, q
->num
);
483 static void mlxsw_pci_rdq_fini(struct mlxsw_pci
*mlxsw_pci
,
484 struct mlxsw_pci_queue
*q
)
486 struct mlxsw_pci_queue_elem_info
*elem_info
;
489 mlxsw_cmd_hw2sw_rdq(mlxsw_pci
->core
, q
->num
);
490 for (i
= 0; i
< q
->count
; i
++) {
491 elem_info
= mlxsw_pci_queue_elem_info_get(q
, i
);
492 mlxsw_pci_rdq_skb_free(mlxsw_pci
, elem_info
);
496 static int mlxsw_pci_cq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
497 struct mlxsw_pci_queue
*q
)
502 q
->consumer_counter
= 0;
504 for (i
= 0; i
< q
->count
; i
++) {
505 char *elem
= mlxsw_pci_queue_elem_get(q
, i
);
507 mlxsw_pci_cqe_owner_set(elem
, 1);
510 mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox
, 0); /* CQE ver 0 */
511 mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox
, MLXSW_PCI_EQ_COMP_NUM
);
512 mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox
, 0);
513 mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox
, ilog2(q
->count
));
514 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
515 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
517 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox
, i
, mapaddr
);
519 err
= mlxsw_cmd_sw2hw_cq(mlxsw_pci
->core
, mbox
, q
->num
);
522 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
523 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
527 static void mlxsw_pci_cq_fini(struct mlxsw_pci
*mlxsw_pci
,
528 struct mlxsw_pci_queue
*q
)
530 mlxsw_cmd_hw2sw_cq(mlxsw_pci
->core
, q
->num
);
533 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci
*mlxsw_pci
,
534 struct mlxsw_pci_queue
*q
,
535 u16 consumer_counter_limit
,
538 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
539 struct mlxsw_pci_queue_elem_info
*elem_info
;
545 elem_info
= mlxsw_pci_queue_elem_info_consumer_get(q
);
546 skb
= elem_info
->u
.sdq
.skb
;
547 wqe
= elem_info
->elem
;
548 for (i
= 0; i
< MLXSW_PCI_WQE_SG_ENTRIES
; i
++)
549 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, i
, DMA_TO_DEVICE
);
550 dev_kfree_skb_any(skb
);
551 elem_info
->u
.sdq
.skb
= NULL
;
553 if (q
->consumer_counter
++ != consumer_counter_limit
)
554 dev_dbg_ratelimited(&pdev
->dev
, "Consumer counter does not match limit in SDQ\n");
555 spin_unlock(&q
->lock
);
558 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci
*mlxsw_pci
,
559 struct mlxsw_pci_queue
*q
,
560 u16 consumer_counter_limit
,
563 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
564 struct mlxsw_pci_queue_elem_info
*elem_info
;
567 struct mlxsw_rx_info rx_info
;
571 elem_info
= mlxsw_pci_queue_elem_info_consumer_get(q
);
572 skb
= elem_info
->u
.sdq
.skb
;
575 wqe
= elem_info
->elem
;
576 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, 0, DMA_FROM_DEVICE
);
578 if (q
->consumer_counter
++ != consumer_counter_limit
)
579 dev_dbg_ratelimited(&pdev
->dev
, "Consumer counter does not match limit in RDQ\n");
581 if (mlxsw_pci_cqe_lag_get(cqe
)) {
582 rx_info
.is_lag
= true;
583 rx_info
.u
.lag_id
= mlxsw_pci_cqe_lag_id_get(cqe
);
584 rx_info
.lag_port_index
= mlxsw_pci_cqe_lag_port_index_get(cqe
);
586 rx_info
.is_lag
= false;
587 rx_info
.u
.sys_port
= mlxsw_pci_cqe_system_port_get(cqe
);
590 rx_info
.trap_id
= mlxsw_pci_cqe_trap_id_get(cqe
);
592 byte_count
= mlxsw_pci_cqe_byte_count_get(cqe
);
593 if (mlxsw_pci_cqe_crc_get(cqe
))
594 byte_count
-= ETH_FCS_LEN
;
595 skb_put(skb
, byte_count
);
596 mlxsw_core_skb_receive(mlxsw_pci
->core
, skb
, &rx_info
);
598 memset(wqe
, 0, q
->elem_size
);
599 err
= mlxsw_pci_rdq_skb_alloc(mlxsw_pci
, elem_info
);
601 dev_dbg_ratelimited(&pdev
->dev
, "Failed to alloc skb for RDQ\n");
602 /* Everything is set up, ring doorbell to pass elem to HW */
603 q
->producer_counter
++;
604 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
608 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue
*q
)
610 return mlxsw_pci_queue_sw_elem_get(q
, mlxsw_pci_cqe_owner_get
);
613 static void mlxsw_pci_cq_tasklet(unsigned long data
)
615 struct mlxsw_pci_queue
*q
= (struct mlxsw_pci_queue
*) data
;
616 struct mlxsw_pci
*mlxsw_pci
= q
->pci
;
619 int credits
= q
->count
>> 1;
621 while ((cqe
= mlxsw_pci_cq_sw_cqe_get(q
))) {
622 u16 wqe_counter
= mlxsw_pci_cqe_wqe_counter_get(cqe
);
623 u8 sendq
= mlxsw_pci_cqe_sr_get(cqe
);
624 u8 dqn
= mlxsw_pci_cqe_dqn_get(cqe
);
627 struct mlxsw_pci_queue
*sdq
;
629 sdq
= mlxsw_pci_sdq_get(mlxsw_pci
, dqn
);
630 mlxsw_pci_cqe_sdq_handle(mlxsw_pci
, sdq
,
632 q
->u
.cq
.comp_sdq_count
++;
634 struct mlxsw_pci_queue
*rdq
;
636 rdq
= mlxsw_pci_rdq_get(mlxsw_pci
, dqn
);
637 mlxsw_pci_cqe_rdq_handle(mlxsw_pci
, rdq
,
639 q
->u
.cq
.comp_rdq_count
++;
641 if (++items
== credits
)
645 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
646 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
650 static int mlxsw_pci_eq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
651 struct mlxsw_pci_queue
*q
)
656 q
->consumer_counter
= 0;
658 for (i
= 0; i
< q
->count
; i
++) {
659 char *elem
= mlxsw_pci_queue_elem_get(q
, i
);
661 mlxsw_pci_eqe_owner_set(elem
, 1);
664 mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox
, 1); /* MSI-X used */
665 mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox
, 1); /* armed */
666 mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox
, ilog2(q
->count
));
667 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
668 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
670 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox
, i
, mapaddr
);
672 err
= mlxsw_cmd_sw2hw_eq(mlxsw_pci
->core
, mbox
, q
->num
);
675 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
676 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
680 static void mlxsw_pci_eq_fini(struct mlxsw_pci
*mlxsw_pci
,
681 struct mlxsw_pci_queue
*q
)
683 mlxsw_cmd_hw2sw_eq(mlxsw_pci
->core
, q
->num
);
686 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci
*mlxsw_pci
, char *eqe
)
688 mlxsw_pci
->cmd
.comp
.status
= mlxsw_pci_eqe_cmd_status_get(eqe
);
689 mlxsw_pci
->cmd
.comp
.out_param
=
690 ((u64
) mlxsw_pci_eqe_cmd_out_param_h_get(eqe
)) << 32 |
691 mlxsw_pci_eqe_cmd_out_param_l_get(eqe
);
692 mlxsw_pci
->cmd
.wait_done
= true;
693 wake_up(&mlxsw_pci
->cmd
.wait
);
696 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue
*q
)
698 return mlxsw_pci_queue_sw_elem_get(q
, mlxsw_pci_eqe_owner_get
);
701 static void mlxsw_pci_eq_tasklet(unsigned long data
)
703 struct mlxsw_pci_queue
*q
= (struct mlxsw_pci_queue
*) data
;
704 struct mlxsw_pci
*mlxsw_pci
= q
->pci
;
705 u8 cq_count
= mlxsw_pci_cq_count(mlxsw_pci
);
706 unsigned long active_cqns
[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX
)];
709 bool cq_handle
= false;
711 int credits
= q
->count
>> 1;
713 memset(&active_cqns
, 0, sizeof(active_cqns
));
715 while ((eqe
= mlxsw_pci_eq_sw_eqe_get(q
))) {
716 u8 event_type
= mlxsw_pci_eqe_event_type_get(eqe
);
718 switch (event_type
) {
719 case MLXSW_PCI_EQE_EVENT_TYPE_CMD
:
720 mlxsw_pci_eq_cmd_event(mlxsw_pci
, eqe
);
721 q
->u
.eq
.ev_cmd_count
++;
723 case MLXSW_PCI_EQE_EVENT_TYPE_COMP
:
724 cqn
= mlxsw_pci_eqe_cqn_get(eqe
);
725 set_bit(cqn
, active_cqns
);
727 q
->u
.eq
.ev_comp_count
++;
730 q
->u
.eq
.ev_other_count
++;
732 if (++items
== credits
)
736 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
737 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
742 for_each_set_bit(cqn
, active_cqns
, cq_count
) {
743 q
= mlxsw_pci_cq_get(mlxsw_pci
, cqn
);
744 mlxsw_pci_queue_tasklet_schedule(q
);
748 struct mlxsw_pci_queue_ops
{
750 enum mlxsw_pci_queue_type type
;
751 int (*init
)(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
752 struct mlxsw_pci_queue
*q
);
753 void (*fini
)(struct mlxsw_pci
*mlxsw_pci
,
754 struct mlxsw_pci_queue
*q
);
755 void (*tasklet
)(unsigned long data
);
760 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops
= {
761 .type
= MLXSW_PCI_QUEUE_TYPE_SDQ
,
762 .init
= mlxsw_pci_sdq_init
,
763 .fini
= mlxsw_pci_sdq_fini
,
764 .elem_count
= MLXSW_PCI_WQE_COUNT
,
765 .elem_size
= MLXSW_PCI_WQE_SIZE
,
768 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops
= {
769 .type
= MLXSW_PCI_QUEUE_TYPE_RDQ
,
770 .init
= mlxsw_pci_rdq_init
,
771 .fini
= mlxsw_pci_rdq_fini
,
772 .elem_count
= MLXSW_PCI_WQE_COUNT
,
773 .elem_size
= MLXSW_PCI_WQE_SIZE
776 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops
= {
777 .type
= MLXSW_PCI_QUEUE_TYPE_CQ
,
778 .init
= mlxsw_pci_cq_init
,
779 .fini
= mlxsw_pci_cq_fini
,
780 .tasklet
= mlxsw_pci_cq_tasklet
,
781 .elem_count
= MLXSW_PCI_CQE_COUNT
,
782 .elem_size
= MLXSW_PCI_CQE_SIZE
785 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops
= {
786 .type
= MLXSW_PCI_QUEUE_TYPE_EQ
,
787 .init
= mlxsw_pci_eq_init
,
788 .fini
= mlxsw_pci_eq_fini
,
789 .tasklet
= mlxsw_pci_eq_tasklet
,
790 .elem_count
= MLXSW_PCI_EQE_COUNT
,
791 .elem_size
= MLXSW_PCI_EQE_SIZE
794 static int mlxsw_pci_queue_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
795 const struct mlxsw_pci_queue_ops
*q_ops
,
796 struct mlxsw_pci_queue
*q
, u8 q_num
)
798 struct mlxsw_pci_mem_item
*mem_item
= &q
->mem_item
;
802 spin_lock_init(&q
->lock
);
804 q
->count
= q_ops
->elem_count
;
805 q
->elem_size
= q_ops
->elem_size
;
806 q
->type
= q_ops
->type
;
810 tasklet_init(&q
->tasklet
, q_ops
->tasklet
, (unsigned long) q
);
812 mem_item
->size
= MLXSW_PCI_AQ_SIZE
;
813 mem_item
->buf
= pci_alloc_consistent(mlxsw_pci
->pdev
,
818 memset(mem_item
->buf
, 0, mem_item
->size
);
820 q
->elem_info
= kcalloc(q
->count
, sizeof(*q
->elem_info
), GFP_KERNEL
);
823 goto err_elem_info_alloc
;
826 /* Initialize dma mapped elements info elem_info for
827 * future easy access.
829 for (i
= 0; i
< q
->count
; i
++) {
830 struct mlxsw_pci_queue_elem_info
*elem_info
;
832 elem_info
= mlxsw_pci_queue_elem_info_get(q
, i
);
834 __mlxsw_pci_queue_elem_get(q
, q_ops
->elem_size
, i
);
837 mlxsw_cmd_mbox_zero(mbox
);
838 err
= q_ops
->init(mlxsw_pci
, mbox
, q
);
846 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
847 mem_item
->buf
, mem_item
->mapaddr
);
851 static void mlxsw_pci_queue_fini(struct mlxsw_pci
*mlxsw_pci
,
852 const struct mlxsw_pci_queue_ops
*q_ops
,
853 struct mlxsw_pci_queue
*q
)
855 struct mlxsw_pci_mem_item
*mem_item
= &q
->mem_item
;
857 q_ops
->fini(mlxsw_pci
, q
);
859 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
860 mem_item
->buf
, mem_item
->mapaddr
);
863 static int mlxsw_pci_queue_group_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
864 const struct mlxsw_pci_queue_ops
*q_ops
,
867 struct mlxsw_pci_queue_type_group
*queue_group
;
871 queue_group
= mlxsw_pci_queue_type_group_get(mlxsw_pci
, q_ops
->type
);
872 queue_group
->q
= kcalloc(num_qs
, sizeof(*queue_group
->q
), GFP_KERNEL
);
876 for (i
= 0; i
< num_qs
; i
++) {
877 err
= mlxsw_pci_queue_init(mlxsw_pci
, mbox
, q_ops
,
878 &queue_group
->q
[i
], i
);
882 queue_group
->count
= num_qs
;
887 for (i
--; i
>= 0; i
--)
888 mlxsw_pci_queue_fini(mlxsw_pci
, q_ops
, &queue_group
->q
[i
]);
889 kfree(queue_group
->q
);
893 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci
*mlxsw_pci
,
894 const struct mlxsw_pci_queue_ops
*q_ops
)
896 struct mlxsw_pci_queue_type_group
*queue_group
;
899 queue_group
= mlxsw_pci_queue_type_group_get(mlxsw_pci
, q_ops
->type
);
900 for (i
= 0; i
< queue_group
->count
; i
++)
901 mlxsw_pci_queue_fini(mlxsw_pci
, q_ops
, &queue_group
->q
[i
]);
902 kfree(queue_group
->q
);
905 static int mlxsw_pci_aqs_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
)
907 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
918 mlxsw_cmd_mbox_zero(mbox
);
919 err
= mlxsw_cmd_query_aq_cap(mlxsw_pci
->core
, mbox
);
923 num_sdqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox
);
924 sdq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox
);
925 num_rdqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox
);
926 rdq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox
);
927 num_cqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox
);
928 cq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox
);
929 num_eqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox
);
930 eq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox
);
932 if (num_sdqs
+ num_rdqs
> num_cqs
||
933 num_cqs
> MLXSW_PCI_CQS_MAX
|| num_eqs
!= MLXSW_PCI_EQS_COUNT
) {
934 dev_err(&pdev
->dev
, "Unsupported number of queues\n");
938 if ((1 << sdq_log2sz
!= MLXSW_PCI_WQE_COUNT
) ||
939 (1 << rdq_log2sz
!= MLXSW_PCI_WQE_COUNT
) ||
940 (1 << cq_log2sz
!= MLXSW_PCI_CQE_COUNT
) ||
941 (1 << eq_log2sz
!= MLXSW_PCI_EQE_COUNT
)) {
942 dev_err(&pdev
->dev
, "Unsupported number of async queue descriptors\n");
946 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_eq_ops
,
949 dev_err(&pdev
->dev
, "Failed to initialize event queues\n");
953 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_cq_ops
,
956 dev_err(&pdev
->dev
, "Failed to initialize completion queues\n");
960 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_sdq_ops
,
963 dev_err(&pdev
->dev
, "Failed to initialize send descriptor queues\n");
967 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_rdq_ops
,
970 dev_err(&pdev
->dev
, "Failed to initialize receive descriptor queues\n");
974 /* We have to poll in command interface until queues are initialized */
975 mlxsw_pci
->cmd
.nopoll
= true;
979 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_sdq_ops
);
981 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_cq_ops
);
983 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_eq_ops
);
987 static void mlxsw_pci_aqs_fini(struct mlxsw_pci
*mlxsw_pci
)
989 mlxsw_pci
->cmd
.nopoll
= false;
990 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_rdq_ops
);
991 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_sdq_ops
);
992 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_cq_ops
);
993 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_eq_ops
);
997 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci
*mlxsw_pci
,
998 char *mbox
, int index
,
999 const struct mlxsw_swid_config
*swid
)
1003 if (swid
->used_type
) {
1004 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1005 mbox
, index
, swid
->type
);
1008 if (swid
->used_properties
) {
1009 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1010 mbox
, index
, swid
->properties
);
1013 mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox
, index
, mask
);
1016 static int mlxsw_pci_resources_query(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
1017 struct mlxsw_res
*res
,
1025 /* Not all the versions support resources query */
1029 mlxsw_cmd_mbox_zero(mbox
);
1031 for (index
= 0; index
< MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES
;
1033 err
= mlxsw_cmd_query_resources(mlxsw_pci
->core
, mbox
, index
);
1037 for (i
= 0; i
< MLXSW_CMD_QUERY_RESOURCES_PER_QUERY
; i
++) {
1038 id
= mlxsw_cmd_mbox_query_resource_id_get(mbox
, i
);
1039 data
= mlxsw_cmd_mbox_query_resource_data_get(mbox
, i
);
1041 if (id
== MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID
)
1044 mlxsw_res_parse(res
, id
, data
);
1048 /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get
1049 * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW.
1055 mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_config_profile
*profile
,
1056 struct mlxsw_res
*res
)
1058 u32 single_size
, double_size
, linear_size
;
1060 if (!MLXSW_RES_VALID(res
, KVD_SINGLE_MIN_SIZE
) ||
1061 !MLXSW_RES_VALID(res
, KVD_DOUBLE_MIN_SIZE
) ||
1062 !profile
->used_kvd_split_data
)
1065 linear_size
= profile
->kvd_linear_size
;
1067 /* The hash part is what left of the kvd without the
1068 * linear part. It is split to the single size and
1069 * double size by the parts ratio from the profile.
1070 * Both sizes must be a multiplications of the
1071 * granularity from the profile.
1073 double_size
= MLXSW_RES_GET(res
, KVD_SIZE
) - linear_size
;
1074 double_size
*= profile
->kvd_hash_double_parts
;
1075 double_size
/= profile
->kvd_hash_double_parts
+
1076 profile
->kvd_hash_single_parts
;
1077 double_size
/= profile
->kvd_hash_granularity
;
1078 double_size
*= profile
->kvd_hash_granularity
;
1079 single_size
= MLXSW_RES_GET(res
, KVD_SIZE
) - double_size
-
1082 /* Check results are legal. */
1083 if (single_size
< MLXSW_RES_GET(res
, KVD_SINGLE_MIN_SIZE
) ||
1084 double_size
< MLXSW_RES_GET(res
, KVD_DOUBLE_MIN_SIZE
) ||
1085 MLXSW_RES_GET(res
, KVD_SIZE
) < linear_size
)
1088 MLXSW_RES_SET(res
, KVD_SINGLE_SIZE
, single_size
);
1089 MLXSW_RES_SET(res
, KVD_DOUBLE_SIZE
, double_size
);
1090 MLXSW_RES_SET(res
, KVD_LINEAR_SIZE
, linear_size
);
1095 static int mlxsw_pci_config_profile(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
1096 const struct mlxsw_config_profile
*profile
,
1097 struct mlxsw_res
*res
)
1102 mlxsw_cmd_mbox_zero(mbox
);
1104 if (profile
->used_max_vepa_channels
) {
1105 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1107 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1108 mbox
, profile
->max_vepa_channels
);
1110 if (profile
->used_max_mid
) {
1111 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1113 mlxsw_cmd_mbox_config_profile_max_mid_set(
1114 mbox
, profile
->max_mid
);
1116 if (profile
->used_max_pgt
) {
1117 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1119 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1120 mbox
, profile
->max_pgt
);
1122 if (profile
->used_max_system_port
) {
1123 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1125 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1126 mbox
, profile
->max_system_port
);
1128 if (profile
->used_max_vlan_groups
) {
1129 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1131 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1132 mbox
, profile
->max_vlan_groups
);
1134 if (profile
->used_max_regions
) {
1135 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1137 mlxsw_cmd_mbox_config_profile_max_regions_set(
1138 mbox
, profile
->max_regions
);
1140 if (profile
->used_flood_tables
) {
1141 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1143 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1144 mbox
, profile
->max_flood_tables
);
1145 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1146 mbox
, profile
->max_vid_flood_tables
);
1147 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set(
1148 mbox
, profile
->max_fid_offset_flood_tables
);
1149 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set(
1150 mbox
, profile
->fid_offset_flood_table_size
);
1151 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set(
1152 mbox
, profile
->max_fid_flood_tables
);
1153 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(
1154 mbox
, profile
->fid_flood_table_size
);
1156 if (profile
->used_flood_mode
) {
1157 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1159 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1160 mbox
, profile
->flood_mode
);
1162 if (profile
->used_max_ib_mc
) {
1163 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1165 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1166 mbox
, profile
->max_ib_mc
);
1168 if (profile
->used_max_pkey
) {
1169 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1171 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1172 mbox
, profile
->max_pkey
);
1174 if (profile
->used_ar_sec
) {
1175 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1177 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1178 mbox
, profile
->ar_sec
);
1180 if (profile
->used_adaptive_routing_group_cap
) {
1181 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1183 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1184 mbox
, profile
->adaptive_routing_group_cap
);
1186 if (MLXSW_RES_VALID(res
, KVD_SIZE
)) {
1187 err
= mlxsw_pci_profile_get_kvd_sizes(profile
, res
);
1191 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox
, 1);
1192 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox
,
1193 MLXSW_RES_GET(res
, KVD_LINEAR_SIZE
));
1194 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox
,
1196 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox
,
1197 MLXSW_RES_GET(res
, KVD_SINGLE_SIZE
));
1198 mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set(
1200 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox
,
1201 MLXSW_RES_GET(res
, KVD_DOUBLE_SIZE
));
1204 for (i
= 0; i
< MLXSW_CONFIG_PROFILE_SWID_COUNT
; i
++)
1205 mlxsw_pci_config_profile_swid_config(mlxsw_pci
, mbox
, i
,
1206 &profile
->swid_config
[i
]);
1208 return mlxsw_cmd_config_profile_set(mlxsw_pci
->core
, mbox
);
1211 static int mlxsw_pci_boardinfo(struct mlxsw_pci
*mlxsw_pci
, char *mbox
)
1213 struct mlxsw_bus_info
*bus_info
= &mlxsw_pci
->bus_info
;
1216 mlxsw_cmd_mbox_zero(mbox
);
1217 err
= mlxsw_cmd_boardinfo(mlxsw_pci
->core
, mbox
);
1220 mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox
, bus_info
->vsd
);
1221 mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox
, bus_info
->psid
);
1225 static int mlxsw_pci_fw_area_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
1228 struct mlxsw_pci_mem_item
*mem_item
;
1233 mlxsw_pci
->fw_area
.items
= kcalloc(num_pages
, sizeof(*mem_item
),
1235 if (!mlxsw_pci
->fw_area
.items
)
1237 mlxsw_pci
->fw_area
.count
= num_pages
;
1239 mlxsw_cmd_mbox_zero(mbox
);
1240 for (i
= 0; i
< num_pages
; i
++) {
1241 mem_item
= &mlxsw_pci
->fw_area
.items
[i
];
1243 mem_item
->size
= MLXSW_PCI_PAGE_SIZE
;
1244 mem_item
->buf
= pci_alloc_consistent(mlxsw_pci
->pdev
,
1246 &mem_item
->mapaddr
);
1247 if (!mem_item
->buf
) {
1251 mlxsw_cmd_mbox_map_fa_pa_set(mbox
, nent
, mem_item
->mapaddr
);
1252 mlxsw_cmd_mbox_map_fa_log2size_set(mbox
, nent
, 0); /* 1 page */
1253 if (++nent
== MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX
) {
1254 err
= mlxsw_cmd_map_fa(mlxsw_pci
->core
, mbox
, nent
);
1256 goto err_cmd_map_fa
;
1258 mlxsw_cmd_mbox_zero(mbox
);
1263 err
= mlxsw_cmd_map_fa(mlxsw_pci
->core
, mbox
, nent
);
1265 goto err_cmd_map_fa
;
1272 for (i
--; i
>= 0; i
--) {
1273 mem_item
= &mlxsw_pci
->fw_area
.items
[i
];
1275 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
1276 mem_item
->buf
, mem_item
->mapaddr
);
1278 kfree(mlxsw_pci
->fw_area
.items
);
1282 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci
*mlxsw_pci
)
1284 struct mlxsw_pci_mem_item
*mem_item
;
1287 mlxsw_cmd_unmap_fa(mlxsw_pci
->core
);
1289 for (i
= 0; i
< mlxsw_pci
->fw_area
.count
; i
++) {
1290 mem_item
= &mlxsw_pci
->fw_area
.items
[i
];
1292 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
1293 mem_item
->buf
, mem_item
->mapaddr
);
1295 kfree(mlxsw_pci
->fw_area
.items
);
1298 static irqreturn_t
mlxsw_pci_eq_irq_handler(int irq
, void *dev_id
)
1300 struct mlxsw_pci
*mlxsw_pci
= dev_id
;
1301 struct mlxsw_pci_queue
*q
;
1304 for (i
= 0; i
< MLXSW_PCI_EQS_COUNT
; i
++) {
1305 q
= mlxsw_pci_eq_get(mlxsw_pci
, i
);
1306 mlxsw_pci_queue_tasklet_schedule(q
);
1311 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci
*mlxsw_pci
,
1312 struct mlxsw_pci_mem_item
*mbox
)
1314 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1317 mbox
->size
= MLXSW_CMD_MBOX_SIZE
;
1318 mbox
->buf
= pci_alloc_consistent(pdev
, MLXSW_CMD_MBOX_SIZE
,
1321 dev_err(&pdev
->dev
, "Failed allocating memory for mailbox\n");
1328 static void mlxsw_pci_mbox_free(struct mlxsw_pci
*mlxsw_pci
,
1329 struct mlxsw_pci_mem_item
*mbox
)
1331 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1333 pci_free_consistent(pdev
, MLXSW_CMD_MBOX_SIZE
, mbox
->buf
,
1337 static int mlxsw_pci_init(void *bus_priv
, struct mlxsw_core
*mlxsw_core
,
1338 const struct mlxsw_config_profile
*profile
,
1339 struct mlxsw_res
*res
)
1341 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1342 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1347 mutex_init(&mlxsw_pci
->cmd
.lock
);
1348 init_waitqueue_head(&mlxsw_pci
->cmd
.wait
);
1350 mlxsw_pci
->core
= mlxsw_core
;
1352 mbox
= mlxsw_cmd_mbox_alloc();
1356 err
= mlxsw_pci_mbox_alloc(mlxsw_pci
, &mlxsw_pci
->cmd
.in_mbox
);
1360 err
= mlxsw_pci_mbox_alloc(mlxsw_pci
, &mlxsw_pci
->cmd
.out_mbox
);
1362 goto err_out_mbox_alloc
;
1364 err
= mlxsw_cmd_query_fw(mlxsw_core
, mbox
);
1368 mlxsw_pci
->bus_info
.fw_rev
.major
=
1369 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox
);
1370 mlxsw_pci
->bus_info
.fw_rev
.minor
=
1371 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox
);
1372 mlxsw_pci
->bus_info
.fw_rev
.subminor
=
1373 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox
);
1375 if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox
) != 1) {
1376 dev_err(&pdev
->dev
, "Unsupported cmd interface revision ID queried from hw\n");
1380 if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox
) != 0) {
1381 dev_err(&pdev
->dev
, "Unsupported doorbell page bar queried from hw\n");
1383 goto err_doorbell_page_bar
;
1386 mlxsw_pci
->doorbell_offset
=
1387 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox
);
1389 num_pages
= mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox
);
1390 err
= mlxsw_pci_fw_area_init(mlxsw_pci
, mbox
, num_pages
);
1392 goto err_fw_area_init
;
1394 err
= mlxsw_pci_boardinfo(mlxsw_pci
, mbox
);
1398 err
= mlxsw_pci_resources_query(mlxsw_pci
, mbox
, res
,
1399 profile
->resource_query_enable
);
1401 goto err_query_resources
;
1403 err
= mlxsw_pci_config_profile(mlxsw_pci
, mbox
, profile
, res
);
1405 goto err_config_profile
;
1407 err
= mlxsw_pci_aqs_init(mlxsw_pci
, mbox
);
1411 err
= request_irq(pci_irq_vector(pdev
, 0),
1412 mlxsw_pci_eq_irq_handler
, 0,
1413 mlxsw_pci
->bus_info
.device_kind
, mlxsw_pci
);
1415 dev_err(&pdev
->dev
, "IRQ request failed\n");
1416 goto err_request_eq_irq
;
1422 mlxsw_pci_aqs_fini(mlxsw_pci
);
1425 err_query_resources
:
1427 mlxsw_pci_fw_area_fini(mlxsw_pci
);
1429 err_doorbell_page_bar
:
1432 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.out_mbox
);
1434 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.in_mbox
);
1436 mlxsw_cmd_mbox_free(mbox
);
1440 static void mlxsw_pci_fini(void *bus_priv
)
1442 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1444 free_irq(pci_irq_vector(mlxsw_pci
->pdev
, 0), mlxsw_pci
);
1445 mlxsw_pci_aqs_fini(mlxsw_pci
);
1446 mlxsw_pci_fw_area_fini(mlxsw_pci
);
1447 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.out_mbox
);
1448 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.in_mbox
);
1451 static struct mlxsw_pci_queue
*
1452 mlxsw_pci_sdq_pick(struct mlxsw_pci
*mlxsw_pci
,
1453 const struct mlxsw_tx_info
*tx_info
)
1455 u8 sdqn
= tx_info
->local_port
% mlxsw_pci_sdq_count(mlxsw_pci
);
1457 return mlxsw_pci_sdq_get(mlxsw_pci
, sdqn
);
1460 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv
,
1461 const struct mlxsw_tx_info
*tx_info
)
1463 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1464 struct mlxsw_pci_queue
*q
= mlxsw_pci_sdq_pick(mlxsw_pci
, tx_info
);
1466 return !mlxsw_pci_queue_elem_info_producer_get(q
);
1469 static int mlxsw_pci_skb_transmit(void *bus_priv
, struct sk_buff
*skb
,
1470 const struct mlxsw_tx_info
*tx_info
)
1472 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1473 struct mlxsw_pci_queue
*q
;
1474 struct mlxsw_pci_queue_elem_info
*elem_info
;
1479 if (skb_shinfo(skb
)->nr_frags
> MLXSW_PCI_WQE_SG_ENTRIES
- 1) {
1480 err
= skb_linearize(skb
);
1485 q
= mlxsw_pci_sdq_pick(mlxsw_pci
, tx_info
);
1486 spin_lock_bh(&q
->lock
);
1487 elem_info
= mlxsw_pci_queue_elem_info_producer_get(q
);
1493 elem_info
->u
.sdq
.skb
= skb
;
1495 wqe
= elem_info
->elem
;
1496 mlxsw_pci_wqe_c_set(wqe
, 1); /* always report completion */
1497 mlxsw_pci_wqe_lp_set(wqe
, !!tx_info
->is_emad
);
1498 mlxsw_pci_wqe_type_set(wqe
, MLXSW_PCI_WQE_TYPE_ETHERNET
);
1500 err
= mlxsw_pci_wqe_frag_map(mlxsw_pci
, wqe
, 0, skb
->data
,
1501 skb_headlen(skb
), DMA_TO_DEVICE
);
1505 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1506 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1508 err
= mlxsw_pci_wqe_frag_map(mlxsw_pci
, wqe
, i
+ 1,
1509 skb_frag_address(frag
),
1510 skb_frag_size(frag
),
1516 /* Set unused sq entries byte count to zero. */
1517 for (i
++; i
< MLXSW_PCI_WQE_SG_ENTRIES
; i
++)
1518 mlxsw_pci_wqe_byte_count_set(wqe
, i
, 0);
1520 /* Everything is set up, ring producer doorbell to get HW going */
1521 q
->producer_counter
++;
1522 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
1528 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, i
, DMA_TO_DEVICE
);
1530 spin_unlock_bh(&q
->lock
);
1534 static int mlxsw_pci_cmd_exec(void *bus_priv
, u16 opcode
, u8 opcode_mod
,
1535 u32 in_mod
, bool out_mbox_direct
,
1536 char *in_mbox
, size_t in_mbox_size
,
1537 char *out_mbox
, size_t out_mbox_size
,
1540 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1541 dma_addr_t in_mapaddr
= mlxsw_pci
->cmd
.in_mbox
.mapaddr
;
1542 dma_addr_t out_mapaddr
= mlxsw_pci
->cmd
.out_mbox
.mapaddr
;
1543 bool evreq
= mlxsw_pci
->cmd
.nopoll
;
1544 unsigned long timeout
= msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS
);
1545 bool *p_wait_done
= &mlxsw_pci
->cmd
.wait_done
;
1548 *p_status
= MLXSW_CMD_STATUS_OK
;
1550 err
= mutex_lock_interruptible(&mlxsw_pci
->cmd
.lock
);
1555 memcpy(mlxsw_pci
->cmd
.in_mbox
.buf
, in_mbox
, in_mbox_size
);
1556 mlxsw_pci_write32(mlxsw_pci
, CIR_IN_PARAM_HI
, upper_32_bits(in_mapaddr
));
1557 mlxsw_pci_write32(mlxsw_pci
, CIR_IN_PARAM_LO
, lower_32_bits(in_mapaddr
));
1559 mlxsw_pci_write32(mlxsw_pci
, CIR_OUT_PARAM_HI
, upper_32_bits(out_mapaddr
));
1560 mlxsw_pci_write32(mlxsw_pci
, CIR_OUT_PARAM_LO
, lower_32_bits(out_mapaddr
));
1562 mlxsw_pci_write32(mlxsw_pci
, CIR_IN_MODIFIER
, in_mod
);
1563 mlxsw_pci_write32(mlxsw_pci
, CIR_TOKEN
, 0);
1565 *p_wait_done
= false;
1567 wmb(); /* all needs to be written before we write control register */
1568 mlxsw_pci_write32(mlxsw_pci
, CIR_CTRL
,
1569 MLXSW_PCI_CIR_CTRL_GO_BIT
|
1570 (evreq
? MLXSW_PCI_CIR_CTRL_EVREQ_BIT
: 0) |
1571 (opcode_mod
<< MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT
) |
1577 end
= jiffies
+ timeout
;
1579 u32 ctrl
= mlxsw_pci_read32(mlxsw_pci
, CIR_CTRL
);
1581 if (!(ctrl
& MLXSW_PCI_CIR_CTRL_GO_BIT
)) {
1582 *p_wait_done
= true;
1583 *p_status
= ctrl
>> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT
;
1587 } while (time_before(jiffies
, end
));
1589 wait_event_timeout(mlxsw_pci
->cmd
.wait
, *p_wait_done
, timeout
);
1590 *p_status
= mlxsw_pci
->cmd
.comp
.status
;
1601 if (!err
&& out_mbox
&& out_mbox_direct
) {
1602 /* Some commands don't use output param as address to mailbox
1603 * but they store output directly into registers. In that case,
1604 * copy registers into mbox buffer.
1609 tmp
= cpu_to_be32(mlxsw_pci_read32(mlxsw_pci
,
1611 memcpy(out_mbox
, &tmp
, sizeof(tmp
));
1612 tmp
= cpu_to_be32(mlxsw_pci_read32(mlxsw_pci
,
1614 memcpy(out_mbox
+ sizeof(tmp
), &tmp
, sizeof(tmp
));
1616 } else if (!err
&& out_mbox
) {
1617 memcpy(out_mbox
, mlxsw_pci
->cmd
.out_mbox
.buf
, out_mbox_size
);
1620 mutex_unlock(&mlxsw_pci
->cmd
.lock
);
1625 static const struct mlxsw_bus mlxsw_pci_bus
= {
1627 .init
= mlxsw_pci_init
,
1628 .fini
= mlxsw_pci_fini
,
1629 .skb_transmit_busy
= mlxsw_pci_skb_transmit_busy
,
1630 .skb_transmit
= mlxsw_pci_skb_transmit
,
1631 .cmd_exec
= mlxsw_pci_cmd_exec
,
1632 .features
= MLXSW_BUS_F_TXRX
,
1635 static int mlxsw_pci_sw_reset(struct mlxsw_pci
*mlxsw_pci
,
1636 const struct pci_device_id
*id
)
1640 mlxsw_pci_write32(mlxsw_pci
, SW_RESET
, MLXSW_PCI_SW_RESET_RST_BIT
);
1641 if (id
->device
== PCI_DEVICE_ID_MELLANOX_SWITCHX2
) {
1642 msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS
);
1646 /* Reset needs to be written before we read control register, and
1647 * we must wait for the HW to become responsive once again
1650 msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS
);
1652 end
= jiffies
+ msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS
);
1654 u32 val
= mlxsw_pci_read32(mlxsw_pci
, FW_READY
);
1656 if ((val
& MLXSW_PCI_FW_READY_MASK
) == MLXSW_PCI_FW_READY_MAGIC
)
1659 } while (time_before(jiffies
, end
));
1663 static int mlxsw_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1665 const char *driver_name
= pdev
->driver
->name
;
1666 struct mlxsw_pci
*mlxsw_pci
;
1669 mlxsw_pci
= kzalloc(sizeof(*mlxsw_pci
), GFP_KERNEL
);
1673 err
= pci_enable_device(pdev
);
1675 dev_err(&pdev
->dev
, "pci_enable_device failed\n");
1676 goto err_pci_enable_device
;
1679 err
= pci_request_regions(pdev
, driver_name
);
1681 dev_err(&pdev
->dev
, "pci_request_regions failed\n");
1682 goto err_pci_request_regions
;
1685 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
1687 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
1689 dev_err(&pdev
->dev
, "pci_set_consistent_dma_mask failed\n");
1690 goto err_pci_set_dma_mask
;
1693 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
1695 dev_err(&pdev
->dev
, "pci_set_dma_mask failed\n");
1696 goto err_pci_set_dma_mask
;
1700 if (pci_resource_len(pdev
, 0) < MLXSW_PCI_BAR0_SIZE
) {
1701 dev_err(&pdev
->dev
, "invalid PCI region size\n");
1703 goto err_pci_resource_len_check
;
1706 mlxsw_pci
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
1707 pci_resource_len(pdev
, 0));
1708 if (!mlxsw_pci
->hw_addr
) {
1709 dev_err(&pdev
->dev
, "ioremap failed\n");
1713 pci_set_master(pdev
);
1715 mlxsw_pci
->pdev
= pdev
;
1716 pci_set_drvdata(pdev
, mlxsw_pci
);
1718 err
= mlxsw_pci_sw_reset(mlxsw_pci
, id
);
1720 dev_err(&pdev
->dev
, "Software reset failed\n");
1724 err
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_MSIX
);
1726 dev_err(&pdev
->dev
, "MSI-X init failed\n");
1730 mlxsw_pci
->bus_info
.device_kind
= driver_name
;
1731 mlxsw_pci
->bus_info
.device_name
= pci_name(mlxsw_pci
->pdev
);
1732 mlxsw_pci
->bus_info
.dev
= &pdev
->dev
;
1734 err
= mlxsw_core_bus_device_register(&mlxsw_pci
->bus_info
,
1735 &mlxsw_pci_bus
, mlxsw_pci
);
1737 dev_err(&pdev
->dev
, "cannot register bus device\n");
1738 goto err_bus_device_register
;
1743 err_bus_device_register
:
1744 pci_free_irq_vectors(mlxsw_pci
->pdev
);
1747 iounmap(mlxsw_pci
->hw_addr
);
1749 err_pci_resource_len_check
:
1750 err_pci_set_dma_mask
:
1751 pci_release_regions(pdev
);
1752 err_pci_request_regions
:
1753 pci_disable_device(pdev
);
1754 err_pci_enable_device
:
1759 static void mlxsw_pci_remove(struct pci_dev
*pdev
)
1761 struct mlxsw_pci
*mlxsw_pci
= pci_get_drvdata(pdev
);
1763 mlxsw_core_bus_device_unregister(mlxsw_pci
->core
);
1764 pci_free_irq_vectors(mlxsw_pci
->pdev
);
1765 iounmap(mlxsw_pci
->hw_addr
);
1766 pci_release_regions(mlxsw_pci
->pdev
);
1767 pci_disable_device(mlxsw_pci
->pdev
);
1771 int mlxsw_pci_driver_register(struct pci_driver
*pci_driver
)
1773 pci_driver
->probe
= mlxsw_pci_probe
;
1774 pci_driver
->remove
= mlxsw_pci_remove
;
1775 return pci_register_driver(pci_driver
);
1777 EXPORT_SYMBOL(mlxsw_pci_driver_register
);
1779 void mlxsw_pci_driver_unregister(struct pci_driver
*pci_driver
)
1781 pci_unregister_driver(pci_driver
);
1783 EXPORT_SYMBOL(mlxsw_pci_driver_unregister
);
1785 static int __init
mlxsw_pci_module_init(void)
1790 static void __exit
mlxsw_pci_module_exit(void)
1794 module_init(mlxsw_pci_module_init
);
1795 module_exit(mlxsw_pci_module_exit
);
1797 MODULE_LICENSE("Dual BSD/GPL");
1798 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1799 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");