2 * drivers/net/ethernet/mellanox/mlxsw/pci.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the names of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
18 * Alternatively, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") version 2 as published by the Free
20 * Software Foundation.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/export.h>
38 #include <linux/err.h>
39 #include <linux/device.h>
40 #include <linux/pci.h>
41 #include <linux/interrupt.h>
42 #include <linux/wait.h>
43 #include <linux/types.h>
44 #include <linux/skbuff.h>
45 #include <linux/if_vlan.h>
46 #include <linux/log2.h>
47 #include <linux/debugfs.h>
48 #include <linux/seq_file.h>
49 #include <linux/string.h>
56 static const char mlxsw_pci_driver_name
[] = "mlxsw_pci";
58 static const struct pci_device_id mlxsw_pci_id_table
[] = {
59 {PCI_VDEVICE(MELLANOX
, PCI_DEVICE_ID_MELLANOX_SWITCHX2
), 0},
60 {PCI_VDEVICE(MELLANOX
, PCI_DEVICE_ID_MELLANOX_SPECTRUM
), 0},
64 static struct dentry
*mlxsw_pci_dbg_root
;
66 static const char *mlxsw_pci_device_kind_get(const struct pci_device_id
*id
)
69 case PCI_DEVICE_ID_MELLANOX_SWITCHX2
:
70 return MLXSW_DEVICE_KIND_SWITCHX2
;
71 case PCI_DEVICE_ID_MELLANOX_SPECTRUM
:
72 return MLXSW_DEVICE_KIND_SPECTRUM
;
78 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
79 iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
80 #define mlxsw_pci_read32(mlxsw_pci, reg) \
81 ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
83 enum mlxsw_pci_queue_type
{
84 MLXSW_PCI_QUEUE_TYPE_SDQ
,
85 MLXSW_PCI_QUEUE_TYPE_RDQ
,
86 MLXSW_PCI_QUEUE_TYPE_CQ
,
87 MLXSW_PCI_QUEUE_TYPE_EQ
,
90 static const char *mlxsw_pci_queue_type_str(enum mlxsw_pci_queue_type q_type
)
93 case MLXSW_PCI_QUEUE_TYPE_SDQ
:
95 case MLXSW_PCI_QUEUE_TYPE_RDQ
:
97 case MLXSW_PCI_QUEUE_TYPE_CQ
:
99 case MLXSW_PCI_QUEUE_TYPE_EQ
:
105 #define MLXSW_PCI_QUEUE_TYPE_COUNT 4
107 static const u16 mlxsw_pci_doorbell_type_offset
[] = {
108 MLXSW_PCI_DOORBELL_SDQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
109 MLXSW_PCI_DOORBELL_RDQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
110 MLXSW_PCI_DOORBELL_CQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
111 MLXSW_PCI_DOORBELL_EQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
114 static const u16 mlxsw_pci_doorbell_arm_type_offset
[] = {
117 MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
118 MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
121 struct mlxsw_pci_mem_item
{
127 struct mlxsw_pci_queue_elem_info
{
128 char *elem
; /* pointer to actual dma mapped element mem chunk */
139 struct mlxsw_pci_queue
{
140 spinlock_t lock
; /* for queue accesses */
141 struct mlxsw_pci_mem_item mem_item
;
142 struct mlxsw_pci_queue_elem_info
*elem_info
;
143 u16 producer_counter
;
144 u16 consumer_counter
;
145 u16 count
; /* number of elements in queue */
146 u8 num
; /* queue number */
147 u8 elem_size
; /* size of one element */
148 enum mlxsw_pci_queue_type type
;
149 struct tasklet_struct tasklet
; /* queue processing tasklet */
150 struct mlxsw_pci
*pci
;
164 struct mlxsw_pci_queue_type_group
{
165 struct mlxsw_pci_queue
*q
;
166 u8 count
; /* number of queues in group */
170 struct pci_dev
*pdev
;
172 struct mlxsw_pci_queue_type_group queues
[MLXSW_PCI_QUEUE_TYPE_COUNT
];
174 struct msix_entry msix_entry
;
175 struct mlxsw_core
*core
;
177 struct mlxsw_pci_mem_item
*items
;
181 struct mlxsw_pci_mem_item out_mbox
;
182 struct mlxsw_pci_mem_item in_mbox
;
183 struct mutex lock
; /* Lock access to command registers */
185 wait_queue_head_t wait
;
192 struct mlxsw_bus_info bus_info
;
193 struct dentry
*dbg_dir
;
196 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue
*q
)
198 tasklet_schedule(&q
->tasklet
);
201 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue
*q
,
202 size_t elem_size
, int elem_index
)
204 return q
->mem_item
.buf
+ (elem_size
* elem_index
);
207 static struct mlxsw_pci_queue_elem_info
*
208 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue
*q
, int elem_index
)
210 return &q
->elem_info
[elem_index
];
213 static struct mlxsw_pci_queue_elem_info
*
214 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue
*q
)
216 int index
= q
->producer_counter
& (q
->count
- 1);
218 if ((q
->producer_counter
- q
->consumer_counter
) == q
->count
)
220 return mlxsw_pci_queue_elem_info_get(q
, index
);
223 static struct mlxsw_pci_queue_elem_info
*
224 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue
*q
)
226 int index
= q
->consumer_counter
& (q
->count
- 1);
228 return mlxsw_pci_queue_elem_info_get(q
, index
);
231 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue
*q
, int elem_index
)
233 return mlxsw_pci_queue_elem_info_get(q
, elem_index
)->elem
;
236 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue
*q
, bool owner_bit
)
238 return owner_bit
!= !!(q
->consumer_counter
& q
->count
);
241 static char *mlxsw_pci_queue_sw_elem_get(struct mlxsw_pci_queue
*q
,
242 u32 (*get_elem_owner_func
)(char *))
244 struct mlxsw_pci_queue_elem_info
*elem_info
;
248 elem_info
= mlxsw_pci_queue_elem_info_consumer_get(q
);
249 elem
= elem_info
->elem
;
250 owner_bit
= get_elem_owner_func(elem
);
251 if (mlxsw_pci_elem_hw_owned(q
, owner_bit
))
253 q
->consumer_counter
++;
254 rmb(); /* make sure we read owned bit before the rest of elem */
258 static struct mlxsw_pci_queue_type_group
*
259 mlxsw_pci_queue_type_group_get(struct mlxsw_pci
*mlxsw_pci
,
260 enum mlxsw_pci_queue_type q_type
)
262 return &mlxsw_pci
->queues
[q_type
];
265 static u8
__mlxsw_pci_queue_count(struct mlxsw_pci
*mlxsw_pci
,
266 enum mlxsw_pci_queue_type q_type
)
268 struct mlxsw_pci_queue_type_group
*queue_group
;
270 queue_group
= mlxsw_pci_queue_type_group_get(mlxsw_pci
, q_type
);
271 return queue_group
->count
;
274 static u8
mlxsw_pci_sdq_count(struct mlxsw_pci
*mlxsw_pci
)
276 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_SDQ
);
279 static u8
mlxsw_pci_rdq_count(struct mlxsw_pci
*mlxsw_pci
)
281 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_RDQ
);
284 static u8
mlxsw_pci_cq_count(struct mlxsw_pci
*mlxsw_pci
)
286 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_CQ
);
289 static u8
mlxsw_pci_eq_count(struct mlxsw_pci
*mlxsw_pci
)
291 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_EQ
);
294 static struct mlxsw_pci_queue
*
295 __mlxsw_pci_queue_get(struct mlxsw_pci
*mlxsw_pci
,
296 enum mlxsw_pci_queue_type q_type
, u8 q_num
)
298 return &mlxsw_pci
->queues
[q_type
].q
[q_num
];
301 static struct mlxsw_pci_queue
*mlxsw_pci_sdq_get(struct mlxsw_pci
*mlxsw_pci
,
304 return __mlxsw_pci_queue_get(mlxsw_pci
,
305 MLXSW_PCI_QUEUE_TYPE_SDQ
, q_num
);
308 static struct mlxsw_pci_queue
*mlxsw_pci_rdq_get(struct mlxsw_pci
*mlxsw_pci
,
311 return __mlxsw_pci_queue_get(mlxsw_pci
,
312 MLXSW_PCI_QUEUE_TYPE_RDQ
, q_num
);
315 static struct mlxsw_pci_queue
*mlxsw_pci_cq_get(struct mlxsw_pci
*mlxsw_pci
,
318 return __mlxsw_pci_queue_get(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_CQ
, q_num
);
321 static struct mlxsw_pci_queue
*mlxsw_pci_eq_get(struct mlxsw_pci
*mlxsw_pci
,
324 return __mlxsw_pci_queue_get(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_EQ
, q_num
);
327 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci
*mlxsw_pci
,
328 struct mlxsw_pci_queue
*q
,
331 mlxsw_pci_write32(mlxsw_pci
,
332 DOORBELL(mlxsw_pci
->doorbell_offset
,
333 mlxsw_pci_doorbell_type_offset
[q
->type
],
337 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci
*mlxsw_pci
,
338 struct mlxsw_pci_queue
*q
,
341 mlxsw_pci_write32(mlxsw_pci
,
342 DOORBELL(mlxsw_pci
->doorbell_offset
,
343 mlxsw_pci_doorbell_arm_type_offset
[q
->type
],
347 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci
*mlxsw_pci
,
348 struct mlxsw_pci_queue
*q
)
350 wmb(); /* ensure all writes are done before we ring a bell */
351 __mlxsw_pci_queue_doorbell_set(mlxsw_pci
, q
, q
->producer_counter
);
354 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci
*mlxsw_pci
,
355 struct mlxsw_pci_queue
*q
)
357 wmb(); /* ensure all writes are done before we ring a bell */
358 __mlxsw_pci_queue_doorbell_set(mlxsw_pci
, q
,
359 q
->consumer_counter
+ q
->count
);
363 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci
*mlxsw_pci
,
364 struct mlxsw_pci_queue
*q
)
366 wmb(); /* ensure all writes are done before we ring a bell */
367 __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci
, q
, q
->consumer_counter
);
370 static dma_addr_t
__mlxsw_pci_queue_page_get(struct mlxsw_pci_queue
*q
,
373 return q
->mem_item
.mapaddr
+ MLXSW_PCI_PAGE_SIZE
* page_index
;
376 static int mlxsw_pci_sdq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
377 struct mlxsw_pci_queue
*q
)
382 q
->producer_counter
= 0;
383 q
->consumer_counter
= 0;
385 /* Set CQ of same number of this SDQ. */
386 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox
, q
->num
);
387 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox
, 3);
388 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox
, 3); /* 8 pages */
389 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
390 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
392 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox
, i
, mapaddr
);
395 err
= mlxsw_cmd_sw2hw_sdq(mlxsw_pci
->core
, mbox
, q
->num
);
398 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
402 static void mlxsw_pci_sdq_fini(struct mlxsw_pci
*mlxsw_pci
,
403 struct mlxsw_pci_queue
*q
)
405 mlxsw_cmd_hw2sw_sdq(mlxsw_pci
->core
, q
->num
);
408 static int mlxsw_pci_sdq_dbg_read(struct seq_file
*file
, void *data
)
410 struct mlxsw_pci
*mlxsw_pci
= dev_get_drvdata(file
->private);
411 struct mlxsw_pci_queue
*q
;
413 static const char hdr
[] =
414 "NUM PROD_COUNT CONS_COUNT COUNT\n";
416 seq_printf(file
, hdr
);
417 for (i
= 0; i
< mlxsw_pci_sdq_count(mlxsw_pci
); i
++) {
418 q
= mlxsw_pci_sdq_get(mlxsw_pci
, i
);
419 spin_lock_bh(&q
->lock
);
420 seq_printf(file
, "%3d %10d %10d %5d\n",
421 i
, q
->producer_counter
, q
->consumer_counter
,
423 spin_unlock_bh(&q
->lock
);
428 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci
*mlxsw_pci
, char *wqe
,
429 int index
, char *frag_data
, size_t frag_len
,
432 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
435 mapaddr
= pci_map_single(pdev
, frag_data
, frag_len
, direction
);
436 if (unlikely(pci_dma_mapping_error(pdev
, mapaddr
))) {
437 dev_err_ratelimited(&pdev
->dev
, "failed to dma map tx frag\n");
440 mlxsw_pci_wqe_address_set(wqe
, index
, mapaddr
);
441 mlxsw_pci_wqe_byte_count_set(wqe
, index
, frag_len
);
445 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci
*mlxsw_pci
, char *wqe
,
446 int index
, int direction
)
448 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
449 size_t frag_len
= mlxsw_pci_wqe_byte_count_get(wqe
, index
);
450 dma_addr_t mapaddr
= mlxsw_pci_wqe_address_get(wqe
, index
);
454 pci_unmap_single(pdev
, mapaddr
, frag_len
, direction
);
457 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci
*mlxsw_pci
,
458 struct mlxsw_pci_queue_elem_info
*elem_info
)
460 size_t buf_len
= MLXSW_PORT_MAX_MTU
;
461 char *wqe
= elem_info
->elem
;
465 elem_info
->u
.rdq
.skb
= NULL
;
466 skb
= netdev_alloc_skb_ip_align(NULL
, buf_len
);
470 /* Assume that wqe was previously zeroed. */
472 err
= mlxsw_pci_wqe_frag_map(mlxsw_pci
, wqe
, 0, skb
->data
,
473 buf_len
, DMA_FROM_DEVICE
);
477 elem_info
->u
.rdq
.skb
= skb
;
481 dev_kfree_skb_any(skb
);
485 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci
*mlxsw_pci
,
486 struct mlxsw_pci_queue_elem_info
*elem_info
)
491 skb
= elem_info
->u
.rdq
.skb
;
492 wqe
= elem_info
->elem
;
494 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, 0, DMA_FROM_DEVICE
);
495 dev_kfree_skb_any(skb
);
498 static int mlxsw_pci_rdq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
499 struct mlxsw_pci_queue
*q
)
501 struct mlxsw_pci_queue_elem_info
*elem_info
;
502 u8 sdq_count
= mlxsw_pci_sdq_count(mlxsw_pci
);
506 q
->producer_counter
= 0;
507 q
->consumer_counter
= 0;
509 /* Set CQ of same number of this RDQ with base
510 * above SDQ count as the lower ones are assigned to SDQs.
512 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox
, sdq_count
+ q
->num
);
513 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox
, 3); /* 8 pages */
514 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
515 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
517 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox
, i
, mapaddr
);
520 err
= mlxsw_cmd_sw2hw_rdq(mlxsw_pci
->core
, mbox
, q
->num
);
524 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
526 for (i
= 0; i
< q
->count
; i
++) {
527 elem_info
= mlxsw_pci_queue_elem_info_producer_get(q
);
529 err
= mlxsw_pci_rdq_skb_alloc(mlxsw_pci
, elem_info
);
532 /* Everything is set up, ring doorbell to pass elem to HW */
533 q
->producer_counter
++;
534 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
540 for (i
--; i
>= 0; i
--) {
541 elem_info
= mlxsw_pci_queue_elem_info_get(q
, i
);
542 mlxsw_pci_rdq_skb_free(mlxsw_pci
, elem_info
);
544 mlxsw_cmd_hw2sw_rdq(mlxsw_pci
->core
, q
->num
);
549 static void mlxsw_pci_rdq_fini(struct mlxsw_pci
*mlxsw_pci
,
550 struct mlxsw_pci_queue
*q
)
552 struct mlxsw_pci_queue_elem_info
*elem_info
;
555 mlxsw_cmd_hw2sw_rdq(mlxsw_pci
->core
, q
->num
);
556 for (i
= 0; i
< q
->count
; i
++) {
557 elem_info
= mlxsw_pci_queue_elem_info_get(q
, i
);
558 mlxsw_pci_rdq_skb_free(mlxsw_pci
, elem_info
);
562 static int mlxsw_pci_rdq_dbg_read(struct seq_file
*file
, void *data
)
564 struct mlxsw_pci
*mlxsw_pci
= dev_get_drvdata(file
->private);
565 struct mlxsw_pci_queue
*q
;
567 static const char hdr
[] =
568 "NUM PROD_COUNT CONS_COUNT COUNT\n";
570 seq_printf(file
, hdr
);
571 for (i
= 0; i
< mlxsw_pci_rdq_count(mlxsw_pci
); i
++) {
572 q
= mlxsw_pci_rdq_get(mlxsw_pci
, i
);
573 spin_lock_bh(&q
->lock
);
574 seq_printf(file
, "%3d %10d %10d %5d\n",
575 i
, q
->producer_counter
, q
->consumer_counter
,
577 spin_unlock_bh(&q
->lock
);
582 static int mlxsw_pci_cq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
583 struct mlxsw_pci_queue
*q
)
588 q
->consumer_counter
= 0;
590 for (i
= 0; i
< q
->count
; i
++) {
591 char *elem
= mlxsw_pci_queue_elem_get(q
, i
);
593 mlxsw_pci_cqe_owner_set(elem
, 1);
596 mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox
, 0); /* CQE ver 0 */
597 mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox
, MLXSW_PCI_EQ_COMP_NUM
);
598 mlxsw_cmd_mbox_sw2hw_cq_oi_set(mbox
, 0);
599 mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox
, 0);
600 mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox
, ilog2(q
->count
));
601 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
602 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
604 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox
, i
, mapaddr
);
606 err
= mlxsw_cmd_sw2hw_cq(mlxsw_pci
->core
, mbox
, q
->num
);
609 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
610 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
614 static void mlxsw_pci_cq_fini(struct mlxsw_pci
*mlxsw_pci
,
615 struct mlxsw_pci_queue
*q
)
617 mlxsw_cmd_hw2sw_cq(mlxsw_pci
->core
, q
->num
);
620 static int mlxsw_pci_cq_dbg_read(struct seq_file
*file
, void *data
)
622 struct mlxsw_pci
*mlxsw_pci
= dev_get_drvdata(file
->private);
624 struct mlxsw_pci_queue
*q
;
626 static const char hdr
[] =
627 "NUM CONS_INDEX SDQ_COUNT RDQ_COUNT COUNT\n";
629 seq_printf(file
, hdr
);
630 for (i
= 0; i
< mlxsw_pci_cq_count(mlxsw_pci
); i
++) {
631 q
= mlxsw_pci_cq_get(mlxsw_pci
, i
);
632 spin_lock_bh(&q
->lock
);
633 seq_printf(file
, "%3d %10d %10d %10d %5d\n",
634 i
, q
->consumer_counter
, q
->u
.cq
.comp_sdq_count
,
635 q
->u
.cq
.comp_rdq_count
, q
->count
);
636 spin_unlock_bh(&q
->lock
);
641 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci
*mlxsw_pci
,
642 struct mlxsw_pci_queue
*q
,
643 u16 consumer_counter_limit
,
646 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
647 struct mlxsw_pci_queue_elem_info
*elem_info
;
653 elem_info
= mlxsw_pci_queue_elem_info_consumer_get(q
);
654 skb
= elem_info
->u
.sdq
.skb
;
655 wqe
= elem_info
->elem
;
656 for (i
= 0; i
< MLXSW_PCI_WQE_SG_ENTRIES
; i
++)
657 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, i
, DMA_TO_DEVICE
);
658 dev_kfree_skb_any(skb
);
659 elem_info
->u
.sdq
.skb
= NULL
;
661 if (q
->consumer_counter
++ != consumer_counter_limit
)
662 dev_dbg_ratelimited(&pdev
->dev
, "Consumer counter does not match limit in SDQ\n");
663 spin_unlock(&q
->lock
);
666 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci
*mlxsw_pci
,
667 struct mlxsw_pci_queue
*q
,
668 u16 consumer_counter_limit
,
671 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
672 struct mlxsw_pci_queue_elem_info
*elem_info
;
675 struct mlxsw_rx_info rx_info
;
679 elem_info
= mlxsw_pci_queue_elem_info_consumer_get(q
);
680 skb
= elem_info
->u
.sdq
.skb
;
683 wqe
= elem_info
->elem
;
684 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, 0, DMA_FROM_DEVICE
);
686 if (q
->consumer_counter
++ != consumer_counter_limit
)
687 dev_dbg_ratelimited(&pdev
->dev
, "Consumer counter does not match limit in RDQ\n");
689 if (mlxsw_pci_cqe_lag_get(cqe
)) {
690 rx_info
.is_lag
= true;
691 rx_info
.u
.lag_id
= mlxsw_pci_cqe_lag_id_get(cqe
);
692 rx_info
.lag_port_index
= mlxsw_pci_cqe_lag_port_index_get(cqe
);
694 rx_info
.is_lag
= false;
695 rx_info
.u
.sys_port
= mlxsw_pci_cqe_system_port_get(cqe
);
698 rx_info
.trap_id
= mlxsw_pci_cqe_trap_id_get(cqe
);
700 byte_count
= mlxsw_pci_cqe_byte_count_get(cqe
);
701 if (mlxsw_pci_cqe_crc_get(cqe
))
702 byte_count
-= ETH_FCS_LEN
;
703 skb_put(skb
, byte_count
);
704 mlxsw_core_skb_receive(mlxsw_pci
->core
, skb
, &rx_info
);
706 memset(wqe
, 0, q
->elem_size
);
707 err
= mlxsw_pci_rdq_skb_alloc(mlxsw_pci
, elem_info
);
709 dev_dbg_ratelimited(&pdev
->dev
, "Failed to alloc skb for RDQ\n");
710 /* Everything is set up, ring doorbell to pass elem to HW */
711 q
->producer_counter
++;
712 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
716 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue
*q
)
718 return mlxsw_pci_queue_sw_elem_get(q
, mlxsw_pci_cqe_owner_get
);
721 static void mlxsw_pci_cq_tasklet(unsigned long data
)
723 struct mlxsw_pci_queue
*q
= (struct mlxsw_pci_queue
*) data
;
724 struct mlxsw_pci
*mlxsw_pci
= q
->pci
;
727 int credits
= q
->count
>> 1;
729 while ((cqe
= mlxsw_pci_cq_sw_cqe_get(q
))) {
730 u16 wqe_counter
= mlxsw_pci_cqe_wqe_counter_get(cqe
);
731 u8 sendq
= mlxsw_pci_cqe_sr_get(cqe
);
732 u8 dqn
= mlxsw_pci_cqe_dqn_get(cqe
);
735 struct mlxsw_pci_queue
*sdq
;
737 sdq
= mlxsw_pci_sdq_get(mlxsw_pci
, dqn
);
738 mlxsw_pci_cqe_sdq_handle(mlxsw_pci
, sdq
,
740 q
->u
.cq
.comp_sdq_count
++;
742 struct mlxsw_pci_queue
*rdq
;
744 rdq
= mlxsw_pci_rdq_get(mlxsw_pci
, dqn
);
745 mlxsw_pci_cqe_rdq_handle(mlxsw_pci
, rdq
,
747 q
->u
.cq
.comp_rdq_count
++;
749 if (++items
== credits
)
753 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
754 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
758 static int mlxsw_pci_eq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
759 struct mlxsw_pci_queue
*q
)
764 q
->consumer_counter
= 0;
766 for (i
= 0; i
< q
->count
; i
++) {
767 char *elem
= mlxsw_pci_queue_elem_get(q
, i
);
769 mlxsw_pci_eqe_owner_set(elem
, 1);
772 mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox
, 1); /* MSI-X used */
773 mlxsw_cmd_mbox_sw2hw_eq_oi_set(mbox
, 0);
774 mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox
, 1); /* armed */
775 mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox
, ilog2(q
->count
));
776 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
777 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
779 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox
, i
, mapaddr
);
781 err
= mlxsw_cmd_sw2hw_eq(mlxsw_pci
->core
, mbox
, q
->num
);
784 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
785 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
789 static void mlxsw_pci_eq_fini(struct mlxsw_pci
*mlxsw_pci
,
790 struct mlxsw_pci_queue
*q
)
792 mlxsw_cmd_hw2sw_eq(mlxsw_pci
->core
, q
->num
);
795 static int mlxsw_pci_eq_dbg_read(struct seq_file
*file
, void *data
)
797 struct mlxsw_pci
*mlxsw_pci
= dev_get_drvdata(file
->private);
798 struct mlxsw_pci_queue
*q
;
800 static const char hdr
[] =
801 "NUM CONS_COUNT EV_CMD EV_COMP EV_OTHER COUNT\n";
803 seq_printf(file
, hdr
);
804 for (i
= 0; i
< mlxsw_pci_eq_count(mlxsw_pci
); i
++) {
805 q
= mlxsw_pci_eq_get(mlxsw_pci
, i
);
806 spin_lock_bh(&q
->lock
);
807 seq_printf(file
, "%3d %10d %10d %10d %10d %5d\n",
808 i
, q
->consumer_counter
, q
->u
.eq
.ev_cmd_count
,
809 q
->u
.eq
.ev_comp_count
, q
->u
.eq
.ev_other_count
,
811 spin_unlock_bh(&q
->lock
);
816 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci
*mlxsw_pci
, char *eqe
)
818 mlxsw_pci
->cmd
.comp
.status
= mlxsw_pci_eqe_cmd_status_get(eqe
);
819 mlxsw_pci
->cmd
.comp
.out_param
=
820 ((u64
) mlxsw_pci_eqe_cmd_out_param_h_get(eqe
)) << 32 |
821 mlxsw_pci_eqe_cmd_out_param_l_get(eqe
);
822 mlxsw_pci
->cmd
.wait_done
= true;
823 wake_up(&mlxsw_pci
->cmd
.wait
);
826 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue
*q
)
828 return mlxsw_pci_queue_sw_elem_get(q
, mlxsw_pci_eqe_owner_get
);
831 static void mlxsw_pci_eq_tasklet(unsigned long data
)
833 struct mlxsw_pci_queue
*q
= (struct mlxsw_pci_queue
*) data
;
834 struct mlxsw_pci
*mlxsw_pci
= q
->pci
;
835 u8 cq_count
= mlxsw_pci_cq_count(mlxsw_pci
);
836 unsigned long active_cqns
[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX
)];
839 bool cq_handle
= false;
841 int credits
= q
->count
>> 1;
843 memset(&active_cqns
, 0, sizeof(active_cqns
));
845 while ((eqe
= mlxsw_pci_eq_sw_eqe_get(q
))) {
846 u8 event_type
= mlxsw_pci_eqe_event_type_get(eqe
);
848 switch (event_type
) {
849 case MLXSW_PCI_EQE_EVENT_TYPE_CMD
:
850 mlxsw_pci_eq_cmd_event(mlxsw_pci
, eqe
);
851 q
->u
.eq
.ev_cmd_count
++;
853 case MLXSW_PCI_EQE_EVENT_TYPE_COMP
:
854 cqn
= mlxsw_pci_eqe_cqn_get(eqe
);
855 set_bit(cqn
, active_cqns
);
857 q
->u
.eq
.ev_comp_count
++;
860 q
->u
.eq
.ev_other_count
++;
862 if (++items
== credits
)
866 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
867 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
872 for_each_set_bit(cqn
, active_cqns
, cq_count
) {
873 q
= mlxsw_pci_cq_get(mlxsw_pci
, cqn
);
874 mlxsw_pci_queue_tasklet_schedule(q
);
878 struct mlxsw_pci_queue_ops
{
880 enum mlxsw_pci_queue_type type
;
881 int (*init
)(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
882 struct mlxsw_pci_queue
*q
);
883 void (*fini
)(struct mlxsw_pci
*mlxsw_pci
,
884 struct mlxsw_pci_queue
*q
);
885 void (*tasklet
)(unsigned long data
);
886 int (*dbg_read
)(struct seq_file
*s
, void *data
);
891 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops
= {
892 .type
= MLXSW_PCI_QUEUE_TYPE_SDQ
,
893 .init
= mlxsw_pci_sdq_init
,
894 .fini
= mlxsw_pci_sdq_fini
,
895 .dbg_read
= mlxsw_pci_sdq_dbg_read
,
896 .elem_count
= MLXSW_PCI_WQE_COUNT
,
897 .elem_size
= MLXSW_PCI_WQE_SIZE
,
900 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops
= {
901 .type
= MLXSW_PCI_QUEUE_TYPE_RDQ
,
902 .init
= mlxsw_pci_rdq_init
,
903 .fini
= mlxsw_pci_rdq_fini
,
904 .dbg_read
= mlxsw_pci_rdq_dbg_read
,
905 .elem_count
= MLXSW_PCI_WQE_COUNT
,
906 .elem_size
= MLXSW_PCI_WQE_SIZE
909 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops
= {
910 .type
= MLXSW_PCI_QUEUE_TYPE_CQ
,
911 .init
= mlxsw_pci_cq_init
,
912 .fini
= mlxsw_pci_cq_fini
,
913 .tasklet
= mlxsw_pci_cq_tasklet
,
914 .dbg_read
= mlxsw_pci_cq_dbg_read
,
915 .elem_count
= MLXSW_PCI_CQE_COUNT
,
916 .elem_size
= MLXSW_PCI_CQE_SIZE
919 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops
= {
920 .type
= MLXSW_PCI_QUEUE_TYPE_EQ
,
921 .init
= mlxsw_pci_eq_init
,
922 .fini
= mlxsw_pci_eq_fini
,
923 .tasklet
= mlxsw_pci_eq_tasklet
,
924 .dbg_read
= mlxsw_pci_eq_dbg_read
,
925 .elem_count
= MLXSW_PCI_EQE_COUNT
,
926 .elem_size
= MLXSW_PCI_EQE_SIZE
929 static int mlxsw_pci_queue_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
930 const struct mlxsw_pci_queue_ops
*q_ops
,
931 struct mlxsw_pci_queue
*q
, u8 q_num
)
933 struct mlxsw_pci_mem_item
*mem_item
= &q
->mem_item
;
937 spin_lock_init(&q
->lock
);
939 q
->count
= q_ops
->elem_count
;
940 q
->elem_size
= q_ops
->elem_size
;
941 q
->type
= q_ops
->type
;
945 tasklet_init(&q
->tasklet
, q_ops
->tasklet
, (unsigned long) q
);
947 mem_item
->size
= MLXSW_PCI_AQ_SIZE
;
948 mem_item
->buf
= pci_alloc_consistent(mlxsw_pci
->pdev
,
953 memset(mem_item
->buf
, 0, mem_item
->size
);
955 q
->elem_info
= kcalloc(q
->count
, sizeof(*q
->elem_info
), GFP_KERNEL
);
958 goto err_elem_info_alloc
;
961 /* Initialize dma mapped elements info elem_info for
962 * future easy access.
964 for (i
= 0; i
< q
->count
; i
++) {
965 struct mlxsw_pci_queue_elem_info
*elem_info
;
967 elem_info
= mlxsw_pci_queue_elem_info_get(q
, i
);
969 __mlxsw_pci_queue_elem_get(q
, q_ops
->elem_size
, i
);
972 mlxsw_cmd_mbox_zero(mbox
);
973 err
= q_ops
->init(mlxsw_pci
, mbox
, q
);
981 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
982 mem_item
->buf
, mem_item
->mapaddr
);
986 static void mlxsw_pci_queue_fini(struct mlxsw_pci
*mlxsw_pci
,
987 const struct mlxsw_pci_queue_ops
*q_ops
,
988 struct mlxsw_pci_queue
*q
)
990 struct mlxsw_pci_mem_item
*mem_item
= &q
->mem_item
;
992 q_ops
->fini(mlxsw_pci
, q
);
994 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
995 mem_item
->buf
, mem_item
->mapaddr
);
998 static int mlxsw_pci_queue_group_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
999 const struct mlxsw_pci_queue_ops
*q_ops
,
1002 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1003 struct mlxsw_pci_queue_type_group
*queue_group
;
1008 queue_group
= mlxsw_pci_queue_type_group_get(mlxsw_pci
, q_ops
->type
);
1009 queue_group
->q
= kcalloc(num_qs
, sizeof(*queue_group
->q
), GFP_KERNEL
);
1010 if (!queue_group
->q
)
1013 for (i
= 0; i
< num_qs
; i
++) {
1014 err
= mlxsw_pci_queue_init(mlxsw_pci
, mbox
, q_ops
,
1015 &queue_group
->q
[i
], i
);
1017 goto err_queue_init
;
1019 queue_group
->count
= num_qs
;
1021 sprintf(tmp
, "%s_stats", mlxsw_pci_queue_type_str(q_ops
->type
));
1022 debugfs_create_devm_seqfile(&pdev
->dev
, tmp
, mlxsw_pci
->dbg_dir
,
1028 for (i
--; i
>= 0; i
--)
1029 mlxsw_pci_queue_fini(mlxsw_pci
, q_ops
, &queue_group
->q
[i
]);
1030 kfree(queue_group
->q
);
1034 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci
*mlxsw_pci
,
1035 const struct mlxsw_pci_queue_ops
*q_ops
)
1037 struct mlxsw_pci_queue_type_group
*queue_group
;
1040 queue_group
= mlxsw_pci_queue_type_group_get(mlxsw_pci
, q_ops
->type
);
1041 for (i
= 0; i
< queue_group
->count
; i
++)
1042 mlxsw_pci_queue_fini(mlxsw_pci
, q_ops
, &queue_group
->q
[i
]);
1043 kfree(queue_group
->q
);
1046 static int mlxsw_pci_aqs_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
)
1048 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1059 mlxsw_cmd_mbox_zero(mbox
);
1060 err
= mlxsw_cmd_query_aq_cap(mlxsw_pci
->core
, mbox
);
1064 num_sdqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox
);
1065 sdq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox
);
1066 num_rdqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox
);
1067 rdq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox
);
1068 num_cqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox
);
1069 cq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox
);
1070 num_eqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox
);
1071 eq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox
);
1073 if (num_sdqs
+ num_rdqs
> num_cqs
||
1074 num_cqs
> MLXSW_PCI_CQS_MAX
|| num_eqs
!= MLXSW_PCI_EQS_COUNT
) {
1075 dev_err(&pdev
->dev
, "Unsupported number of queues\n");
1079 if ((1 << sdq_log2sz
!= MLXSW_PCI_WQE_COUNT
) ||
1080 (1 << rdq_log2sz
!= MLXSW_PCI_WQE_COUNT
) ||
1081 (1 << cq_log2sz
!= MLXSW_PCI_CQE_COUNT
) ||
1082 (1 << eq_log2sz
!= MLXSW_PCI_EQE_COUNT
)) {
1083 dev_err(&pdev
->dev
, "Unsupported number of async queue descriptors\n");
1087 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_eq_ops
,
1090 dev_err(&pdev
->dev
, "Failed to initialize event queues\n");
1094 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_cq_ops
,
1097 dev_err(&pdev
->dev
, "Failed to initialize completion queues\n");
1101 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_sdq_ops
,
1104 dev_err(&pdev
->dev
, "Failed to initialize send descriptor queues\n");
1108 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_rdq_ops
,
1111 dev_err(&pdev
->dev
, "Failed to initialize receive descriptor queues\n");
1115 /* We have to poll in command interface until queues are initialized */
1116 mlxsw_pci
->cmd
.nopoll
= true;
1120 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_sdq_ops
);
1122 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_cq_ops
);
1124 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_eq_ops
);
1128 static void mlxsw_pci_aqs_fini(struct mlxsw_pci
*mlxsw_pci
)
1130 mlxsw_pci
->cmd
.nopoll
= false;
1131 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_rdq_ops
);
1132 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_sdq_ops
);
1133 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_cq_ops
);
1134 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_eq_ops
);
1138 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci
*mlxsw_pci
,
1139 char *mbox
, int index
,
1140 const struct mlxsw_swid_config
*swid
)
1144 if (swid
->used_type
) {
1145 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1146 mbox
, index
, swid
->type
);
1149 if (swid
->used_properties
) {
1150 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1151 mbox
, index
, swid
->properties
);
1154 mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox
, index
, mask
);
1157 static int mlxsw_pci_config_profile(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
1158 const struct mlxsw_config_profile
*profile
)
1162 mlxsw_cmd_mbox_zero(mbox
);
1164 if (profile
->used_max_vepa_channels
) {
1165 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1167 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1168 mbox
, profile
->max_vepa_channels
);
1170 if (profile
->used_max_lag
) {
1171 mlxsw_cmd_mbox_config_profile_set_max_lag_set(
1173 mlxsw_cmd_mbox_config_profile_max_lag_set(
1174 mbox
, profile
->max_lag
);
1176 if (profile
->used_max_port_per_lag
) {
1177 mlxsw_cmd_mbox_config_profile_set_max_port_per_lag_set(
1179 mlxsw_cmd_mbox_config_profile_max_port_per_lag_set(
1180 mbox
, profile
->max_port_per_lag
);
1182 if (profile
->used_max_mid
) {
1183 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1185 mlxsw_cmd_mbox_config_profile_max_mid_set(
1186 mbox
, profile
->max_mid
);
1188 if (profile
->used_max_pgt
) {
1189 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1191 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1192 mbox
, profile
->max_pgt
);
1194 if (profile
->used_max_system_port
) {
1195 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1197 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1198 mbox
, profile
->max_system_port
);
1200 if (profile
->used_max_vlan_groups
) {
1201 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1203 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1204 mbox
, profile
->max_vlan_groups
);
1206 if (profile
->used_max_regions
) {
1207 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1209 mlxsw_cmd_mbox_config_profile_max_regions_set(
1210 mbox
, profile
->max_regions
);
1212 if (profile
->used_flood_tables
) {
1213 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1215 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1216 mbox
, profile
->max_flood_tables
);
1217 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1218 mbox
, profile
->max_vid_flood_tables
);
1219 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set(
1220 mbox
, profile
->max_fid_offset_flood_tables
);
1221 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set(
1222 mbox
, profile
->fid_offset_flood_table_size
);
1223 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set(
1224 mbox
, profile
->max_fid_flood_tables
);
1225 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(
1226 mbox
, profile
->fid_flood_table_size
);
1228 if (profile
->used_flood_mode
) {
1229 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1231 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1232 mbox
, profile
->flood_mode
);
1234 if (profile
->used_max_ib_mc
) {
1235 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1237 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1238 mbox
, profile
->max_ib_mc
);
1240 if (profile
->used_max_pkey
) {
1241 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1243 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1244 mbox
, profile
->max_pkey
);
1246 if (profile
->used_ar_sec
) {
1247 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1249 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1250 mbox
, profile
->ar_sec
);
1252 if (profile
->used_adaptive_routing_group_cap
) {
1253 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1255 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1256 mbox
, profile
->adaptive_routing_group_cap
);
1259 for (i
= 0; i
< MLXSW_CONFIG_PROFILE_SWID_COUNT
; i
++)
1260 mlxsw_pci_config_profile_swid_config(mlxsw_pci
, mbox
, i
,
1261 &profile
->swid_config
[i
]);
1263 return mlxsw_cmd_config_profile_set(mlxsw_pci
->core
, mbox
);
1266 static int mlxsw_pci_boardinfo(struct mlxsw_pci
*mlxsw_pci
, char *mbox
)
1268 struct mlxsw_bus_info
*bus_info
= &mlxsw_pci
->bus_info
;
1271 mlxsw_cmd_mbox_zero(mbox
);
1272 err
= mlxsw_cmd_boardinfo(mlxsw_pci
->core
, mbox
);
1275 mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox
, bus_info
->vsd
);
1276 mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox
, bus_info
->psid
);
1280 static int mlxsw_pci_fw_area_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
1283 struct mlxsw_pci_mem_item
*mem_item
;
1288 mlxsw_pci
->fw_area
.items
= kcalloc(num_pages
, sizeof(*mem_item
),
1290 if (!mlxsw_pci
->fw_area
.items
)
1292 mlxsw_pci
->fw_area
.count
= num_pages
;
1294 mlxsw_cmd_mbox_zero(mbox
);
1295 for (i
= 0; i
< num_pages
; i
++) {
1296 mem_item
= &mlxsw_pci
->fw_area
.items
[i
];
1298 mem_item
->size
= MLXSW_PCI_PAGE_SIZE
;
1299 mem_item
->buf
= pci_alloc_consistent(mlxsw_pci
->pdev
,
1301 &mem_item
->mapaddr
);
1302 if (!mem_item
->buf
) {
1306 mlxsw_cmd_mbox_map_fa_pa_set(mbox
, nent
, mem_item
->mapaddr
);
1307 mlxsw_cmd_mbox_map_fa_log2size_set(mbox
, nent
, 0); /* 1 page */
1308 if (++nent
== MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX
) {
1309 err
= mlxsw_cmd_map_fa(mlxsw_pci
->core
, mbox
, nent
);
1311 goto err_cmd_map_fa
;
1313 mlxsw_cmd_mbox_zero(mbox
);
1318 err
= mlxsw_cmd_map_fa(mlxsw_pci
->core
, mbox
, nent
);
1320 goto err_cmd_map_fa
;
1327 for (i
--; i
>= 0; i
--) {
1328 mem_item
= &mlxsw_pci
->fw_area
.items
[i
];
1330 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
1331 mem_item
->buf
, mem_item
->mapaddr
);
1333 kfree(mlxsw_pci
->fw_area
.items
);
1337 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci
*mlxsw_pci
)
1339 struct mlxsw_pci_mem_item
*mem_item
;
1342 mlxsw_cmd_unmap_fa(mlxsw_pci
->core
);
1344 for (i
= 0; i
< mlxsw_pci
->fw_area
.count
; i
++) {
1345 mem_item
= &mlxsw_pci
->fw_area
.items
[i
];
1347 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
1348 mem_item
->buf
, mem_item
->mapaddr
);
1350 kfree(mlxsw_pci
->fw_area
.items
);
1353 static irqreturn_t
mlxsw_pci_eq_irq_handler(int irq
, void *dev_id
)
1355 struct mlxsw_pci
*mlxsw_pci
= dev_id
;
1356 struct mlxsw_pci_queue
*q
;
1359 for (i
= 0; i
< MLXSW_PCI_EQS_COUNT
; i
++) {
1360 q
= mlxsw_pci_eq_get(mlxsw_pci
, i
);
1361 mlxsw_pci_queue_tasklet_schedule(q
);
1366 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci
*mlxsw_pci
,
1367 struct mlxsw_pci_mem_item
*mbox
)
1369 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1372 mbox
->size
= MLXSW_CMD_MBOX_SIZE
;
1373 mbox
->buf
= pci_alloc_consistent(pdev
, MLXSW_CMD_MBOX_SIZE
,
1376 dev_err(&pdev
->dev
, "Failed allocating memory for mailbox\n");
1383 static void mlxsw_pci_mbox_free(struct mlxsw_pci
*mlxsw_pci
,
1384 struct mlxsw_pci_mem_item
*mbox
)
1386 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1388 pci_free_consistent(pdev
, MLXSW_CMD_MBOX_SIZE
, mbox
->buf
,
1392 static int mlxsw_pci_init(void *bus_priv
, struct mlxsw_core
*mlxsw_core
,
1393 const struct mlxsw_config_profile
*profile
)
1395 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1396 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1401 mutex_init(&mlxsw_pci
->cmd
.lock
);
1402 init_waitqueue_head(&mlxsw_pci
->cmd
.wait
);
1404 mlxsw_pci
->core
= mlxsw_core
;
1406 mbox
= mlxsw_cmd_mbox_alloc();
1410 err
= mlxsw_pci_mbox_alloc(mlxsw_pci
, &mlxsw_pci
->cmd
.in_mbox
);
1414 err
= mlxsw_pci_mbox_alloc(mlxsw_pci
, &mlxsw_pci
->cmd
.out_mbox
);
1416 goto err_out_mbox_alloc
;
1418 err
= mlxsw_cmd_query_fw(mlxsw_core
, mbox
);
1422 mlxsw_pci
->bus_info
.fw_rev
.major
=
1423 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox
);
1424 mlxsw_pci
->bus_info
.fw_rev
.minor
=
1425 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox
);
1426 mlxsw_pci
->bus_info
.fw_rev
.subminor
=
1427 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox
);
1429 if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox
) != 1) {
1430 dev_err(&pdev
->dev
, "Unsupported cmd interface revision ID queried from hw\n");
1434 if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox
) != 0) {
1435 dev_err(&pdev
->dev
, "Unsupported doorbell page bar queried from hw\n");
1437 goto err_doorbell_page_bar
;
1440 mlxsw_pci
->doorbell_offset
=
1441 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox
);
1443 num_pages
= mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox
);
1444 err
= mlxsw_pci_fw_area_init(mlxsw_pci
, mbox
, num_pages
);
1446 goto err_fw_area_init
;
1448 err
= mlxsw_pci_boardinfo(mlxsw_pci
, mbox
);
1452 err
= mlxsw_pci_config_profile(mlxsw_pci
, mbox
, profile
);
1454 goto err_config_profile
;
1456 err
= mlxsw_pci_aqs_init(mlxsw_pci
, mbox
);
1460 err
= request_irq(mlxsw_pci
->msix_entry
.vector
,
1461 mlxsw_pci_eq_irq_handler
, 0,
1462 mlxsw_pci_driver_name
, mlxsw_pci
);
1464 dev_err(&pdev
->dev
, "IRQ request failed\n");
1465 goto err_request_eq_irq
;
1471 mlxsw_pci_aqs_fini(mlxsw_pci
);
1475 mlxsw_pci_fw_area_fini(mlxsw_pci
);
1477 err_doorbell_page_bar
:
1480 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.out_mbox
);
1482 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.in_mbox
);
1484 mlxsw_cmd_mbox_free(mbox
);
1488 static void mlxsw_pci_fini(void *bus_priv
)
1490 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1492 free_irq(mlxsw_pci
->msix_entry
.vector
, mlxsw_pci
);
1493 mlxsw_pci_aqs_fini(mlxsw_pci
);
1494 mlxsw_pci_fw_area_fini(mlxsw_pci
);
1495 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.out_mbox
);
1496 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.in_mbox
);
1499 static struct mlxsw_pci_queue
*
1500 mlxsw_pci_sdq_pick(struct mlxsw_pci
*mlxsw_pci
,
1501 const struct mlxsw_tx_info
*tx_info
)
1503 u8 sdqn
= tx_info
->local_port
% mlxsw_pci_sdq_count(mlxsw_pci
);
1505 return mlxsw_pci_sdq_get(mlxsw_pci
, sdqn
);
1508 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv
,
1509 const struct mlxsw_tx_info
*tx_info
)
1511 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1512 struct mlxsw_pci_queue
*q
= mlxsw_pci_sdq_pick(mlxsw_pci
, tx_info
);
1514 return !mlxsw_pci_queue_elem_info_producer_get(q
);
1517 static int mlxsw_pci_skb_transmit(void *bus_priv
, struct sk_buff
*skb
,
1518 const struct mlxsw_tx_info
*tx_info
)
1520 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1521 struct mlxsw_pci_queue
*q
;
1522 struct mlxsw_pci_queue_elem_info
*elem_info
;
1527 if (skb_shinfo(skb
)->nr_frags
> MLXSW_PCI_WQE_SG_ENTRIES
- 1) {
1528 err
= skb_linearize(skb
);
1533 q
= mlxsw_pci_sdq_pick(mlxsw_pci
, tx_info
);
1534 spin_lock_bh(&q
->lock
);
1535 elem_info
= mlxsw_pci_queue_elem_info_producer_get(q
);
1541 elem_info
->u
.sdq
.skb
= skb
;
1543 wqe
= elem_info
->elem
;
1544 mlxsw_pci_wqe_c_set(wqe
, 1); /* always report completion */
1545 mlxsw_pci_wqe_lp_set(wqe
, !!tx_info
->is_emad
);
1546 mlxsw_pci_wqe_type_set(wqe
, MLXSW_PCI_WQE_TYPE_ETHERNET
);
1548 err
= mlxsw_pci_wqe_frag_map(mlxsw_pci
, wqe
, 0, skb
->data
,
1549 skb_headlen(skb
), DMA_TO_DEVICE
);
1553 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1554 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1556 err
= mlxsw_pci_wqe_frag_map(mlxsw_pci
, wqe
, i
+ 1,
1557 skb_frag_address(frag
),
1558 skb_frag_size(frag
),
1564 /* Set unused sq entries byte count to zero. */
1565 for (i
++; i
< MLXSW_PCI_WQE_SG_ENTRIES
; i
++)
1566 mlxsw_pci_wqe_byte_count_set(wqe
, i
, 0);
1568 /* Everything is set up, ring producer doorbell to get HW going */
1569 q
->producer_counter
++;
1570 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
1576 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, i
, DMA_TO_DEVICE
);
1578 spin_unlock_bh(&q
->lock
);
1582 static int mlxsw_pci_cmd_exec(void *bus_priv
, u16 opcode
, u8 opcode_mod
,
1583 u32 in_mod
, bool out_mbox_direct
,
1584 char *in_mbox
, size_t in_mbox_size
,
1585 char *out_mbox
, size_t out_mbox_size
,
1588 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1589 dma_addr_t in_mapaddr
= mlxsw_pci
->cmd
.in_mbox
.mapaddr
;
1590 dma_addr_t out_mapaddr
= mlxsw_pci
->cmd
.out_mbox
.mapaddr
;
1591 bool evreq
= mlxsw_pci
->cmd
.nopoll
;
1592 unsigned long timeout
= msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS
);
1593 bool *p_wait_done
= &mlxsw_pci
->cmd
.wait_done
;
1596 *p_status
= MLXSW_CMD_STATUS_OK
;
1598 err
= mutex_lock_interruptible(&mlxsw_pci
->cmd
.lock
);
1603 memcpy(mlxsw_pci
->cmd
.in_mbox
.buf
, in_mbox
, in_mbox_size
);
1604 mlxsw_pci_write32(mlxsw_pci
, CIR_IN_PARAM_HI
, upper_32_bits(in_mapaddr
));
1605 mlxsw_pci_write32(mlxsw_pci
, CIR_IN_PARAM_LO
, lower_32_bits(in_mapaddr
));
1607 mlxsw_pci_write32(mlxsw_pci
, CIR_OUT_PARAM_HI
, upper_32_bits(out_mapaddr
));
1608 mlxsw_pci_write32(mlxsw_pci
, CIR_OUT_PARAM_LO
, lower_32_bits(out_mapaddr
));
1610 mlxsw_pci_write32(mlxsw_pci
, CIR_IN_MODIFIER
, in_mod
);
1611 mlxsw_pci_write32(mlxsw_pci
, CIR_TOKEN
, 0);
1613 *p_wait_done
= false;
1615 wmb(); /* all needs to be written before we write control register */
1616 mlxsw_pci_write32(mlxsw_pci
, CIR_CTRL
,
1617 MLXSW_PCI_CIR_CTRL_GO_BIT
|
1618 (evreq
? MLXSW_PCI_CIR_CTRL_EVREQ_BIT
: 0) |
1619 (opcode_mod
<< MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT
) |
1625 end
= jiffies
+ timeout
;
1627 u32 ctrl
= mlxsw_pci_read32(mlxsw_pci
, CIR_CTRL
);
1629 if (!(ctrl
& MLXSW_PCI_CIR_CTRL_GO_BIT
)) {
1630 *p_wait_done
= true;
1631 *p_status
= ctrl
>> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT
;
1635 } while (time_before(jiffies
, end
));
1637 wait_event_timeout(mlxsw_pci
->cmd
.wait
, *p_wait_done
, timeout
);
1638 *p_status
= mlxsw_pci
->cmd
.comp
.status
;
1649 if (!err
&& out_mbox
&& out_mbox_direct
) {
1650 /* Some commands don't use output param as address to mailbox
1651 * but they store output directly into registers. In that case,
1652 * copy registers into mbox buffer.
1657 tmp
= cpu_to_be32(mlxsw_pci_read32(mlxsw_pci
,
1659 memcpy(out_mbox
, &tmp
, sizeof(tmp
));
1660 tmp
= cpu_to_be32(mlxsw_pci_read32(mlxsw_pci
,
1662 memcpy(out_mbox
+ sizeof(tmp
), &tmp
, sizeof(tmp
));
1664 } else if (!err
&& out_mbox
) {
1665 memcpy(out_mbox
, mlxsw_pci
->cmd
.out_mbox
.buf
, out_mbox_size
);
1668 mutex_unlock(&mlxsw_pci
->cmd
.lock
);
1673 static const struct mlxsw_bus mlxsw_pci_bus
= {
1675 .init
= mlxsw_pci_init
,
1676 .fini
= mlxsw_pci_fini
,
1677 .skb_transmit_busy
= mlxsw_pci_skb_transmit_busy
,
1678 .skb_transmit
= mlxsw_pci_skb_transmit
,
1679 .cmd_exec
= mlxsw_pci_cmd_exec
,
1682 static int mlxsw_pci_sw_reset(struct mlxsw_pci
*mlxsw_pci
)
1684 mlxsw_pci_write32(mlxsw_pci
, SW_RESET
, MLXSW_PCI_SW_RESET_RST_BIT
);
1685 /* Current firware does not let us know when the reset is done.
1686 * So we just wait here for constant time and hope for the best.
1688 msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS
);
1692 static int mlxsw_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1694 struct mlxsw_pci
*mlxsw_pci
;
1697 mlxsw_pci
= kzalloc(sizeof(*mlxsw_pci
), GFP_KERNEL
);
1701 err
= pci_enable_device(pdev
);
1703 dev_err(&pdev
->dev
, "pci_enable_device failed\n");
1704 goto err_pci_enable_device
;
1707 err
= pci_request_regions(pdev
, mlxsw_pci_driver_name
);
1709 dev_err(&pdev
->dev
, "pci_request_regions failed\n");
1710 goto err_pci_request_regions
;
1713 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
1715 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
1717 dev_err(&pdev
->dev
, "pci_set_consistent_dma_mask failed\n");
1718 goto err_pci_set_dma_mask
;
1721 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
1723 dev_err(&pdev
->dev
, "pci_set_dma_mask failed\n");
1724 goto err_pci_set_dma_mask
;
1728 if (pci_resource_len(pdev
, 0) < MLXSW_PCI_BAR0_SIZE
) {
1729 dev_err(&pdev
->dev
, "invalid PCI region size\n");
1731 goto err_pci_resource_len_check
;
1734 mlxsw_pci
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
1735 pci_resource_len(pdev
, 0));
1736 if (!mlxsw_pci
->hw_addr
) {
1737 dev_err(&pdev
->dev
, "ioremap failed\n");
1741 pci_set_master(pdev
);
1743 mlxsw_pci
->pdev
= pdev
;
1744 pci_set_drvdata(pdev
, mlxsw_pci
);
1746 err
= mlxsw_pci_sw_reset(mlxsw_pci
);
1748 dev_err(&pdev
->dev
, "Software reset failed\n");
1752 err
= pci_enable_msix_exact(pdev
, &mlxsw_pci
->msix_entry
, 1);
1754 dev_err(&pdev
->dev
, "MSI-X init failed\n");
1758 mlxsw_pci
->bus_info
.device_kind
= mlxsw_pci_device_kind_get(id
);
1759 mlxsw_pci
->bus_info
.device_name
= pci_name(mlxsw_pci
->pdev
);
1760 mlxsw_pci
->bus_info
.dev
= &pdev
->dev
;
1762 mlxsw_pci
->dbg_dir
= debugfs_create_dir(mlxsw_pci
->bus_info
.device_name
,
1763 mlxsw_pci_dbg_root
);
1764 if (!mlxsw_pci
->dbg_dir
) {
1765 dev_err(&pdev
->dev
, "Failed to create debugfs dir\n");
1767 goto err_dbg_create_dir
;
1770 err
= mlxsw_core_bus_device_register(&mlxsw_pci
->bus_info
,
1771 &mlxsw_pci_bus
, mlxsw_pci
);
1773 dev_err(&pdev
->dev
, "cannot register bus device\n");
1774 goto err_bus_device_register
;
1779 err_bus_device_register
:
1780 debugfs_remove_recursive(mlxsw_pci
->dbg_dir
);
1782 pci_disable_msix(mlxsw_pci
->pdev
);
1785 iounmap(mlxsw_pci
->hw_addr
);
1787 err_pci_resource_len_check
:
1788 err_pci_set_dma_mask
:
1789 pci_release_regions(pdev
);
1790 err_pci_request_regions
:
1791 pci_disable_device(pdev
);
1792 err_pci_enable_device
:
1797 static void mlxsw_pci_remove(struct pci_dev
*pdev
)
1799 struct mlxsw_pci
*mlxsw_pci
= pci_get_drvdata(pdev
);
1801 mlxsw_core_bus_device_unregister(mlxsw_pci
->core
);
1802 debugfs_remove_recursive(mlxsw_pci
->dbg_dir
);
1803 pci_disable_msix(mlxsw_pci
->pdev
);
1804 iounmap(mlxsw_pci
->hw_addr
);
1805 pci_release_regions(mlxsw_pci
->pdev
);
1806 pci_disable_device(mlxsw_pci
->pdev
);
1810 static struct pci_driver mlxsw_pci_driver
= {
1811 .name
= mlxsw_pci_driver_name
,
1812 .id_table
= mlxsw_pci_id_table
,
1813 .probe
= mlxsw_pci_probe
,
1814 .remove
= mlxsw_pci_remove
,
1817 static int __init
mlxsw_pci_module_init(void)
1821 mlxsw_pci_dbg_root
= debugfs_create_dir(mlxsw_pci_driver_name
, NULL
);
1822 if (!mlxsw_pci_dbg_root
)
1824 err
= pci_register_driver(&mlxsw_pci_driver
);
1826 goto err_register_driver
;
1829 err_register_driver
:
1830 debugfs_remove_recursive(mlxsw_pci_dbg_root
);
1834 static void __exit
mlxsw_pci_module_exit(void)
1836 pci_unregister_driver(&mlxsw_pci_driver
);
1837 debugfs_remove_recursive(mlxsw_pci_dbg_root
);
1840 module_init(mlxsw_pci_module_init
);
1841 module_exit(mlxsw_pci_module_exit
);
1843 MODULE_LICENSE("Dual BSD/GPL");
1844 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1845 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");
1846 MODULE_DEVICE_TABLE(pci
, mlxsw_pci_id_table
);