2 * drivers/net/ethernet/mellanox/mlxsw/pci.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the names of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
18 * Alternatively, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") version 2 as published by the Free
20 * Software Foundation.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/export.h>
38 #include <linux/err.h>
39 #include <linux/device.h>
40 #include <linux/pci.h>
41 #include <linux/interrupt.h>
42 #include <linux/wait.h>
43 #include <linux/types.h>
44 #include <linux/skbuff.h>
45 #include <linux/if_vlan.h>
46 #include <linux/log2.h>
47 #include <linux/debugfs.h>
48 #include <linux/seq_file.h>
49 #include <linux/string.h>
56 #include "resources.h"
58 static const char mlxsw_pci_driver_name
[] = "mlxsw_pci";
60 static struct dentry
*mlxsw_pci_dbg_root
;
62 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
63 iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
64 #define mlxsw_pci_read32(mlxsw_pci, reg) \
65 ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
67 enum mlxsw_pci_queue_type
{
68 MLXSW_PCI_QUEUE_TYPE_SDQ
,
69 MLXSW_PCI_QUEUE_TYPE_RDQ
,
70 MLXSW_PCI_QUEUE_TYPE_CQ
,
71 MLXSW_PCI_QUEUE_TYPE_EQ
,
74 static const char *mlxsw_pci_queue_type_str(enum mlxsw_pci_queue_type q_type
)
77 case MLXSW_PCI_QUEUE_TYPE_SDQ
:
79 case MLXSW_PCI_QUEUE_TYPE_RDQ
:
81 case MLXSW_PCI_QUEUE_TYPE_CQ
:
83 case MLXSW_PCI_QUEUE_TYPE_EQ
:
89 #define MLXSW_PCI_QUEUE_TYPE_COUNT 4
91 static const u16 mlxsw_pci_doorbell_type_offset
[] = {
92 MLXSW_PCI_DOORBELL_SDQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
93 MLXSW_PCI_DOORBELL_RDQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
94 MLXSW_PCI_DOORBELL_CQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
95 MLXSW_PCI_DOORBELL_EQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
98 static const u16 mlxsw_pci_doorbell_arm_type_offset
[] = {
101 MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
102 MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET
, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
105 struct mlxsw_pci_mem_item
{
111 struct mlxsw_pci_queue_elem_info
{
112 char *elem
; /* pointer to actual dma mapped element mem chunk */
123 struct mlxsw_pci_queue
{
124 spinlock_t lock
; /* for queue accesses */
125 struct mlxsw_pci_mem_item mem_item
;
126 struct mlxsw_pci_queue_elem_info
*elem_info
;
127 u16 producer_counter
;
128 u16 consumer_counter
;
129 u16 count
; /* number of elements in queue */
130 u8 num
; /* queue number */
131 u8 elem_size
; /* size of one element */
132 enum mlxsw_pci_queue_type type
;
133 struct tasklet_struct tasklet
; /* queue processing tasklet */
134 struct mlxsw_pci
*pci
;
148 struct mlxsw_pci_queue_type_group
{
149 struct mlxsw_pci_queue
*q
;
150 u8 count
; /* number of queues in group */
154 struct pci_dev
*pdev
;
156 struct mlxsw_pci_queue_type_group queues
[MLXSW_PCI_QUEUE_TYPE_COUNT
];
158 struct msix_entry msix_entry
;
159 struct mlxsw_core
*core
;
161 struct mlxsw_pci_mem_item
*items
;
165 struct mlxsw_pci_mem_item out_mbox
;
166 struct mlxsw_pci_mem_item in_mbox
;
167 struct mutex lock
; /* Lock access to command registers */
169 wait_queue_head_t wait
;
176 struct mlxsw_bus_info bus_info
;
177 struct dentry
*dbg_dir
;
180 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue
*q
)
182 tasklet_schedule(&q
->tasklet
);
185 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue
*q
,
186 size_t elem_size
, int elem_index
)
188 return q
->mem_item
.buf
+ (elem_size
* elem_index
);
191 static struct mlxsw_pci_queue_elem_info
*
192 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue
*q
, int elem_index
)
194 return &q
->elem_info
[elem_index
];
197 static struct mlxsw_pci_queue_elem_info
*
198 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue
*q
)
200 int index
= q
->producer_counter
& (q
->count
- 1);
202 if ((u16
) (q
->producer_counter
- q
->consumer_counter
) == q
->count
)
204 return mlxsw_pci_queue_elem_info_get(q
, index
);
207 static struct mlxsw_pci_queue_elem_info
*
208 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue
*q
)
210 int index
= q
->consumer_counter
& (q
->count
- 1);
212 return mlxsw_pci_queue_elem_info_get(q
, index
);
215 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue
*q
, int elem_index
)
217 return mlxsw_pci_queue_elem_info_get(q
, elem_index
)->elem
;
220 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue
*q
, bool owner_bit
)
222 return owner_bit
!= !!(q
->consumer_counter
& q
->count
);
226 mlxsw_pci_queue_sw_elem_get(struct mlxsw_pci_queue
*q
,
227 u32 (*get_elem_owner_func
)(const char *))
229 struct mlxsw_pci_queue_elem_info
*elem_info
;
233 elem_info
= mlxsw_pci_queue_elem_info_consumer_get(q
);
234 elem
= elem_info
->elem
;
235 owner_bit
= get_elem_owner_func(elem
);
236 if (mlxsw_pci_elem_hw_owned(q
, owner_bit
))
238 q
->consumer_counter
++;
239 rmb(); /* make sure we read owned bit before the rest of elem */
243 static struct mlxsw_pci_queue_type_group
*
244 mlxsw_pci_queue_type_group_get(struct mlxsw_pci
*mlxsw_pci
,
245 enum mlxsw_pci_queue_type q_type
)
247 return &mlxsw_pci
->queues
[q_type
];
250 static u8
__mlxsw_pci_queue_count(struct mlxsw_pci
*mlxsw_pci
,
251 enum mlxsw_pci_queue_type q_type
)
253 struct mlxsw_pci_queue_type_group
*queue_group
;
255 queue_group
= mlxsw_pci_queue_type_group_get(mlxsw_pci
, q_type
);
256 return queue_group
->count
;
259 static u8
mlxsw_pci_sdq_count(struct mlxsw_pci
*mlxsw_pci
)
261 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_SDQ
);
264 static u8
mlxsw_pci_rdq_count(struct mlxsw_pci
*mlxsw_pci
)
266 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_RDQ
);
269 static u8
mlxsw_pci_cq_count(struct mlxsw_pci
*mlxsw_pci
)
271 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_CQ
);
274 static u8
mlxsw_pci_eq_count(struct mlxsw_pci
*mlxsw_pci
)
276 return __mlxsw_pci_queue_count(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_EQ
);
279 static struct mlxsw_pci_queue
*
280 __mlxsw_pci_queue_get(struct mlxsw_pci
*mlxsw_pci
,
281 enum mlxsw_pci_queue_type q_type
, u8 q_num
)
283 return &mlxsw_pci
->queues
[q_type
].q
[q_num
];
286 static struct mlxsw_pci_queue
*mlxsw_pci_sdq_get(struct mlxsw_pci
*mlxsw_pci
,
289 return __mlxsw_pci_queue_get(mlxsw_pci
,
290 MLXSW_PCI_QUEUE_TYPE_SDQ
, q_num
);
293 static struct mlxsw_pci_queue
*mlxsw_pci_rdq_get(struct mlxsw_pci
*mlxsw_pci
,
296 return __mlxsw_pci_queue_get(mlxsw_pci
,
297 MLXSW_PCI_QUEUE_TYPE_RDQ
, q_num
);
300 static struct mlxsw_pci_queue
*mlxsw_pci_cq_get(struct mlxsw_pci
*mlxsw_pci
,
303 return __mlxsw_pci_queue_get(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_CQ
, q_num
);
306 static struct mlxsw_pci_queue
*mlxsw_pci_eq_get(struct mlxsw_pci
*mlxsw_pci
,
309 return __mlxsw_pci_queue_get(mlxsw_pci
, MLXSW_PCI_QUEUE_TYPE_EQ
, q_num
);
312 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci
*mlxsw_pci
,
313 struct mlxsw_pci_queue
*q
,
316 mlxsw_pci_write32(mlxsw_pci
,
317 DOORBELL(mlxsw_pci
->doorbell_offset
,
318 mlxsw_pci_doorbell_type_offset
[q
->type
],
322 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci
*mlxsw_pci
,
323 struct mlxsw_pci_queue
*q
,
326 mlxsw_pci_write32(mlxsw_pci
,
327 DOORBELL(mlxsw_pci
->doorbell_offset
,
328 mlxsw_pci_doorbell_arm_type_offset
[q
->type
],
332 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci
*mlxsw_pci
,
333 struct mlxsw_pci_queue
*q
)
335 wmb(); /* ensure all writes are done before we ring a bell */
336 __mlxsw_pci_queue_doorbell_set(mlxsw_pci
, q
, q
->producer_counter
);
339 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci
*mlxsw_pci
,
340 struct mlxsw_pci_queue
*q
)
342 wmb(); /* ensure all writes are done before we ring a bell */
343 __mlxsw_pci_queue_doorbell_set(mlxsw_pci
, q
,
344 q
->consumer_counter
+ q
->count
);
348 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci
*mlxsw_pci
,
349 struct mlxsw_pci_queue
*q
)
351 wmb(); /* ensure all writes are done before we ring a bell */
352 __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci
, q
, q
->consumer_counter
);
355 static dma_addr_t
__mlxsw_pci_queue_page_get(struct mlxsw_pci_queue
*q
,
358 return q
->mem_item
.mapaddr
+ MLXSW_PCI_PAGE_SIZE
* page_index
;
361 static int mlxsw_pci_sdq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
362 struct mlxsw_pci_queue
*q
)
367 q
->producer_counter
= 0;
368 q
->consumer_counter
= 0;
370 /* Set CQ of same number of this SDQ. */
371 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox
, q
->num
);
372 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox
, 3);
373 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox
, 3); /* 8 pages */
374 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
375 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
377 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox
, i
, mapaddr
);
380 err
= mlxsw_cmd_sw2hw_sdq(mlxsw_pci
->core
, mbox
, q
->num
);
383 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
387 static void mlxsw_pci_sdq_fini(struct mlxsw_pci
*mlxsw_pci
,
388 struct mlxsw_pci_queue
*q
)
390 mlxsw_cmd_hw2sw_sdq(mlxsw_pci
->core
, q
->num
);
393 static int mlxsw_pci_sdq_dbg_read(struct seq_file
*file
, void *data
)
395 struct mlxsw_pci
*mlxsw_pci
= dev_get_drvdata(file
->private);
396 struct mlxsw_pci_queue
*q
;
398 static const char hdr
[] =
399 "NUM PROD_COUNT CONS_COUNT COUNT\n";
401 seq_printf(file
, hdr
);
402 for (i
= 0; i
< mlxsw_pci_sdq_count(mlxsw_pci
); i
++) {
403 q
= mlxsw_pci_sdq_get(mlxsw_pci
, i
);
404 spin_lock_bh(&q
->lock
);
405 seq_printf(file
, "%3d %10d %10d %5d\n",
406 i
, q
->producer_counter
, q
->consumer_counter
,
408 spin_unlock_bh(&q
->lock
);
413 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci
*mlxsw_pci
, char *wqe
,
414 int index
, char *frag_data
, size_t frag_len
,
417 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
420 mapaddr
= pci_map_single(pdev
, frag_data
, frag_len
, direction
);
421 if (unlikely(pci_dma_mapping_error(pdev
, mapaddr
))) {
422 dev_err_ratelimited(&pdev
->dev
, "failed to dma map tx frag\n");
425 mlxsw_pci_wqe_address_set(wqe
, index
, mapaddr
);
426 mlxsw_pci_wqe_byte_count_set(wqe
, index
, frag_len
);
430 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci
*mlxsw_pci
, char *wqe
,
431 int index
, int direction
)
433 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
434 size_t frag_len
= mlxsw_pci_wqe_byte_count_get(wqe
, index
);
435 dma_addr_t mapaddr
= mlxsw_pci_wqe_address_get(wqe
, index
);
439 pci_unmap_single(pdev
, mapaddr
, frag_len
, direction
);
442 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci
*mlxsw_pci
,
443 struct mlxsw_pci_queue_elem_info
*elem_info
)
445 size_t buf_len
= MLXSW_PORT_MAX_MTU
;
446 char *wqe
= elem_info
->elem
;
450 elem_info
->u
.rdq
.skb
= NULL
;
451 skb
= netdev_alloc_skb_ip_align(NULL
, buf_len
);
455 /* Assume that wqe was previously zeroed. */
457 err
= mlxsw_pci_wqe_frag_map(mlxsw_pci
, wqe
, 0, skb
->data
,
458 buf_len
, DMA_FROM_DEVICE
);
462 elem_info
->u
.rdq
.skb
= skb
;
466 dev_kfree_skb_any(skb
);
470 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci
*mlxsw_pci
,
471 struct mlxsw_pci_queue_elem_info
*elem_info
)
476 skb
= elem_info
->u
.rdq
.skb
;
477 wqe
= elem_info
->elem
;
479 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, 0, DMA_FROM_DEVICE
);
480 dev_kfree_skb_any(skb
);
483 static int mlxsw_pci_rdq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
484 struct mlxsw_pci_queue
*q
)
486 struct mlxsw_pci_queue_elem_info
*elem_info
;
487 u8 sdq_count
= mlxsw_pci_sdq_count(mlxsw_pci
);
491 q
->producer_counter
= 0;
492 q
->consumer_counter
= 0;
494 /* Set CQ of same number of this RDQ with base
495 * above SDQ count as the lower ones are assigned to SDQs.
497 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox
, sdq_count
+ q
->num
);
498 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox
, 3); /* 8 pages */
499 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
500 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
502 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox
, i
, mapaddr
);
505 err
= mlxsw_cmd_sw2hw_rdq(mlxsw_pci
->core
, mbox
, q
->num
);
509 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
511 for (i
= 0; i
< q
->count
; i
++) {
512 elem_info
= mlxsw_pci_queue_elem_info_producer_get(q
);
514 err
= mlxsw_pci_rdq_skb_alloc(mlxsw_pci
, elem_info
);
517 /* Everything is set up, ring doorbell to pass elem to HW */
518 q
->producer_counter
++;
519 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
525 for (i
--; i
>= 0; i
--) {
526 elem_info
= mlxsw_pci_queue_elem_info_get(q
, i
);
527 mlxsw_pci_rdq_skb_free(mlxsw_pci
, elem_info
);
529 mlxsw_cmd_hw2sw_rdq(mlxsw_pci
->core
, q
->num
);
534 static void mlxsw_pci_rdq_fini(struct mlxsw_pci
*mlxsw_pci
,
535 struct mlxsw_pci_queue
*q
)
537 struct mlxsw_pci_queue_elem_info
*elem_info
;
540 mlxsw_cmd_hw2sw_rdq(mlxsw_pci
->core
, q
->num
);
541 for (i
= 0; i
< q
->count
; i
++) {
542 elem_info
= mlxsw_pci_queue_elem_info_get(q
, i
);
543 mlxsw_pci_rdq_skb_free(mlxsw_pci
, elem_info
);
547 static int mlxsw_pci_rdq_dbg_read(struct seq_file
*file
, void *data
)
549 struct mlxsw_pci
*mlxsw_pci
= dev_get_drvdata(file
->private);
550 struct mlxsw_pci_queue
*q
;
552 static const char hdr
[] =
553 "NUM PROD_COUNT CONS_COUNT COUNT\n";
555 seq_printf(file
, hdr
);
556 for (i
= 0; i
< mlxsw_pci_rdq_count(mlxsw_pci
); i
++) {
557 q
= mlxsw_pci_rdq_get(mlxsw_pci
, i
);
558 spin_lock_bh(&q
->lock
);
559 seq_printf(file
, "%3d %10d %10d %5d\n",
560 i
, q
->producer_counter
, q
->consumer_counter
,
562 spin_unlock_bh(&q
->lock
);
567 static int mlxsw_pci_cq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
568 struct mlxsw_pci_queue
*q
)
573 q
->consumer_counter
= 0;
575 for (i
= 0; i
< q
->count
; i
++) {
576 char *elem
= mlxsw_pci_queue_elem_get(q
, i
);
578 mlxsw_pci_cqe_owner_set(elem
, 1);
581 mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox
, 0); /* CQE ver 0 */
582 mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox
, MLXSW_PCI_EQ_COMP_NUM
);
583 mlxsw_cmd_mbox_sw2hw_cq_oi_set(mbox
, 0);
584 mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox
, 0);
585 mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox
, ilog2(q
->count
));
586 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
587 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
589 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox
, i
, mapaddr
);
591 err
= mlxsw_cmd_sw2hw_cq(mlxsw_pci
->core
, mbox
, q
->num
);
594 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
595 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
599 static void mlxsw_pci_cq_fini(struct mlxsw_pci
*mlxsw_pci
,
600 struct mlxsw_pci_queue
*q
)
602 mlxsw_cmd_hw2sw_cq(mlxsw_pci
->core
, q
->num
);
605 static int mlxsw_pci_cq_dbg_read(struct seq_file
*file
, void *data
)
607 struct mlxsw_pci
*mlxsw_pci
= dev_get_drvdata(file
->private);
609 struct mlxsw_pci_queue
*q
;
611 static const char hdr
[] =
612 "NUM CONS_INDEX SDQ_COUNT RDQ_COUNT COUNT\n";
614 seq_printf(file
, hdr
);
615 for (i
= 0; i
< mlxsw_pci_cq_count(mlxsw_pci
); i
++) {
616 q
= mlxsw_pci_cq_get(mlxsw_pci
, i
);
617 spin_lock_bh(&q
->lock
);
618 seq_printf(file
, "%3d %10d %10d %10d %5d\n",
619 i
, q
->consumer_counter
, q
->u
.cq
.comp_sdq_count
,
620 q
->u
.cq
.comp_rdq_count
, q
->count
);
621 spin_unlock_bh(&q
->lock
);
626 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci
*mlxsw_pci
,
627 struct mlxsw_pci_queue
*q
,
628 u16 consumer_counter_limit
,
631 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
632 struct mlxsw_pci_queue_elem_info
*elem_info
;
638 elem_info
= mlxsw_pci_queue_elem_info_consumer_get(q
);
639 skb
= elem_info
->u
.sdq
.skb
;
640 wqe
= elem_info
->elem
;
641 for (i
= 0; i
< MLXSW_PCI_WQE_SG_ENTRIES
; i
++)
642 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, i
, DMA_TO_DEVICE
);
643 dev_kfree_skb_any(skb
);
644 elem_info
->u
.sdq
.skb
= NULL
;
646 if (q
->consumer_counter
++ != consumer_counter_limit
)
647 dev_dbg_ratelimited(&pdev
->dev
, "Consumer counter does not match limit in SDQ\n");
648 spin_unlock(&q
->lock
);
651 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci
*mlxsw_pci
,
652 struct mlxsw_pci_queue
*q
,
653 u16 consumer_counter_limit
,
656 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
657 struct mlxsw_pci_queue_elem_info
*elem_info
;
660 struct mlxsw_rx_info rx_info
;
664 elem_info
= mlxsw_pci_queue_elem_info_consumer_get(q
);
665 skb
= elem_info
->u
.sdq
.skb
;
668 wqe
= elem_info
->elem
;
669 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, 0, DMA_FROM_DEVICE
);
671 if (q
->consumer_counter
++ != consumer_counter_limit
)
672 dev_dbg_ratelimited(&pdev
->dev
, "Consumer counter does not match limit in RDQ\n");
674 if (mlxsw_pci_cqe_lag_get(cqe
)) {
675 rx_info
.is_lag
= true;
676 rx_info
.u
.lag_id
= mlxsw_pci_cqe_lag_id_get(cqe
);
677 rx_info
.lag_port_index
= mlxsw_pci_cqe_lag_port_index_get(cqe
);
679 rx_info
.is_lag
= false;
680 rx_info
.u
.sys_port
= mlxsw_pci_cqe_system_port_get(cqe
);
683 rx_info
.trap_id
= mlxsw_pci_cqe_trap_id_get(cqe
);
685 byte_count
= mlxsw_pci_cqe_byte_count_get(cqe
);
686 if (mlxsw_pci_cqe_crc_get(cqe
))
687 byte_count
-= ETH_FCS_LEN
;
688 skb_put(skb
, byte_count
);
689 mlxsw_core_skb_receive(mlxsw_pci
->core
, skb
, &rx_info
);
691 memset(wqe
, 0, q
->elem_size
);
692 err
= mlxsw_pci_rdq_skb_alloc(mlxsw_pci
, elem_info
);
694 dev_dbg_ratelimited(&pdev
->dev
, "Failed to alloc skb for RDQ\n");
695 /* Everything is set up, ring doorbell to pass elem to HW */
696 q
->producer_counter
++;
697 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
701 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue
*q
)
703 return mlxsw_pci_queue_sw_elem_get(q
, mlxsw_pci_cqe_owner_get
);
706 static void mlxsw_pci_cq_tasklet(unsigned long data
)
708 struct mlxsw_pci_queue
*q
= (struct mlxsw_pci_queue
*) data
;
709 struct mlxsw_pci
*mlxsw_pci
= q
->pci
;
712 int credits
= q
->count
>> 1;
714 while ((cqe
= mlxsw_pci_cq_sw_cqe_get(q
))) {
715 u16 wqe_counter
= mlxsw_pci_cqe_wqe_counter_get(cqe
);
716 u8 sendq
= mlxsw_pci_cqe_sr_get(cqe
);
717 u8 dqn
= mlxsw_pci_cqe_dqn_get(cqe
);
720 struct mlxsw_pci_queue
*sdq
;
722 sdq
= mlxsw_pci_sdq_get(mlxsw_pci
, dqn
);
723 mlxsw_pci_cqe_sdq_handle(mlxsw_pci
, sdq
,
725 q
->u
.cq
.comp_sdq_count
++;
727 struct mlxsw_pci_queue
*rdq
;
729 rdq
= mlxsw_pci_rdq_get(mlxsw_pci
, dqn
);
730 mlxsw_pci_cqe_rdq_handle(mlxsw_pci
, rdq
,
732 q
->u
.cq
.comp_rdq_count
++;
734 if (++items
== credits
)
738 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
739 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
743 static int mlxsw_pci_eq_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
744 struct mlxsw_pci_queue
*q
)
749 q
->consumer_counter
= 0;
751 for (i
= 0; i
< q
->count
; i
++) {
752 char *elem
= mlxsw_pci_queue_elem_get(q
, i
);
754 mlxsw_pci_eqe_owner_set(elem
, 1);
757 mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox
, 1); /* MSI-X used */
758 mlxsw_cmd_mbox_sw2hw_eq_oi_set(mbox
, 0);
759 mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox
, 1); /* armed */
760 mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox
, ilog2(q
->count
));
761 for (i
= 0; i
< MLXSW_PCI_AQ_PAGES
; i
++) {
762 dma_addr_t mapaddr
= __mlxsw_pci_queue_page_get(q
, i
);
764 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox
, i
, mapaddr
);
766 err
= mlxsw_cmd_sw2hw_eq(mlxsw_pci
->core
, mbox
, q
->num
);
769 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
770 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
774 static void mlxsw_pci_eq_fini(struct mlxsw_pci
*mlxsw_pci
,
775 struct mlxsw_pci_queue
*q
)
777 mlxsw_cmd_hw2sw_eq(mlxsw_pci
->core
, q
->num
);
780 static int mlxsw_pci_eq_dbg_read(struct seq_file
*file
, void *data
)
782 struct mlxsw_pci
*mlxsw_pci
= dev_get_drvdata(file
->private);
783 struct mlxsw_pci_queue
*q
;
785 static const char hdr
[] =
786 "NUM CONS_COUNT EV_CMD EV_COMP EV_OTHER COUNT\n";
788 seq_printf(file
, hdr
);
789 for (i
= 0; i
< mlxsw_pci_eq_count(mlxsw_pci
); i
++) {
790 q
= mlxsw_pci_eq_get(mlxsw_pci
, i
);
791 spin_lock_bh(&q
->lock
);
792 seq_printf(file
, "%3d %10d %10d %10d %10d %5d\n",
793 i
, q
->consumer_counter
, q
->u
.eq
.ev_cmd_count
,
794 q
->u
.eq
.ev_comp_count
, q
->u
.eq
.ev_other_count
,
796 spin_unlock_bh(&q
->lock
);
801 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci
*mlxsw_pci
, char *eqe
)
803 mlxsw_pci
->cmd
.comp
.status
= mlxsw_pci_eqe_cmd_status_get(eqe
);
804 mlxsw_pci
->cmd
.comp
.out_param
=
805 ((u64
) mlxsw_pci_eqe_cmd_out_param_h_get(eqe
)) << 32 |
806 mlxsw_pci_eqe_cmd_out_param_l_get(eqe
);
807 mlxsw_pci
->cmd
.wait_done
= true;
808 wake_up(&mlxsw_pci
->cmd
.wait
);
811 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue
*q
)
813 return mlxsw_pci_queue_sw_elem_get(q
, mlxsw_pci_eqe_owner_get
);
816 static void mlxsw_pci_eq_tasklet(unsigned long data
)
818 struct mlxsw_pci_queue
*q
= (struct mlxsw_pci_queue
*) data
;
819 struct mlxsw_pci
*mlxsw_pci
= q
->pci
;
820 u8 cq_count
= mlxsw_pci_cq_count(mlxsw_pci
);
821 unsigned long active_cqns
[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX
)];
824 bool cq_handle
= false;
826 int credits
= q
->count
>> 1;
828 memset(&active_cqns
, 0, sizeof(active_cqns
));
830 while ((eqe
= mlxsw_pci_eq_sw_eqe_get(q
))) {
831 u8 event_type
= mlxsw_pci_eqe_event_type_get(eqe
);
833 switch (event_type
) {
834 case MLXSW_PCI_EQE_EVENT_TYPE_CMD
:
835 mlxsw_pci_eq_cmd_event(mlxsw_pci
, eqe
);
836 q
->u
.eq
.ev_cmd_count
++;
838 case MLXSW_PCI_EQE_EVENT_TYPE_COMP
:
839 cqn
= mlxsw_pci_eqe_cqn_get(eqe
);
840 set_bit(cqn
, active_cqns
);
842 q
->u
.eq
.ev_comp_count
++;
845 q
->u
.eq
.ev_other_count
++;
847 if (++items
== credits
)
851 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci
, q
);
852 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci
, q
);
857 for_each_set_bit(cqn
, active_cqns
, cq_count
) {
858 q
= mlxsw_pci_cq_get(mlxsw_pci
, cqn
);
859 mlxsw_pci_queue_tasklet_schedule(q
);
863 struct mlxsw_pci_queue_ops
{
865 enum mlxsw_pci_queue_type type
;
866 int (*init
)(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
867 struct mlxsw_pci_queue
*q
);
868 void (*fini
)(struct mlxsw_pci
*mlxsw_pci
,
869 struct mlxsw_pci_queue
*q
);
870 void (*tasklet
)(unsigned long data
);
871 int (*dbg_read
)(struct seq_file
*s
, void *data
);
876 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops
= {
877 .type
= MLXSW_PCI_QUEUE_TYPE_SDQ
,
878 .init
= mlxsw_pci_sdq_init
,
879 .fini
= mlxsw_pci_sdq_fini
,
880 .dbg_read
= mlxsw_pci_sdq_dbg_read
,
881 .elem_count
= MLXSW_PCI_WQE_COUNT
,
882 .elem_size
= MLXSW_PCI_WQE_SIZE
,
885 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops
= {
886 .type
= MLXSW_PCI_QUEUE_TYPE_RDQ
,
887 .init
= mlxsw_pci_rdq_init
,
888 .fini
= mlxsw_pci_rdq_fini
,
889 .dbg_read
= mlxsw_pci_rdq_dbg_read
,
890 .elem_count
= MLXSW_PCI_WQE_COUNT
,
891 .elem_size
= MLXSW_PCI_WQE_SIZE
894 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops
= {
895 .type
= MLXSW_PCI_QUEUE_TYPE_CQ
,
896 .init
= mlxsw_pci_cq_init
,
897 .fini
= mlxsw_pci_cq_fini
,
898 .tasklet
= mlxsw_pci_cq_tasklet
,
899 .dbg_read
= mlxsw_pci_cq_dbg_read
,
900 .elem_count
= MLXSW_PCI_CQE_COUNT
,
901 .elem_size
= MLXSW_PCI_CQE_SIZE
904 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops
= {
905 .type
= MLXSW_PCI_QUEUE_TYPE_EQ
,
906 .init
= mlxsw_pci_eq_init
,
907 .fini
= mlxsw_pci_eq_fini
,
908 .tasklet
= mlxsw_pci_eq_tasklet
,
909 .dbg_read
= mlxsw_pci_eq_dbg_read
,
910 .elem_count
= MLXSW_PCI_EQE_COUNT
,
911 .elem_size
= MLXSW_PCI_EQE_SIZE
914 static int mlxsw_pci_queue_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
915 const struct mlxsw_pci_queue_ops
*q_ops
,
916 struct mlxsw_pci_queue
*q
, u8 q_num
)
918 struct mlxsw_pci_mem_item
*mem_item
= &q
->mem_item
;
922 spin_lock_init(&q
->lock
);
924 q
->count
= q_ops
->elem_count
;
925 q
->elem_size
= q_ops
->elem_size
;
926 q
->type
= q_ops
->type
;
930 tasklet_init(&q
->tasklet
, q_ops
->tasklet
, (unsigned long) q
);
932 mem_item
->size
= MLXSW_PCI_AQ_SIZE
;
933 mem_item
->buf
= pci_alloc_consistent(mlxsw_pci
->pdev
,
938 memset(mem_item
->buf
, 0, mem_item
->size
);
940 q
->elem_info
= kcalloc(q
->count
, sizeof(*q
->elem_info
), GFP_KERNEL
);
943 goto err_elem_info_alloc
;
946 /* Initialize dma mapped elements info elem_info for
947 * future easy access.
949 for (i
= 0; i
< q
->count
; i
++) {
950 struct mlxsw_pci_queue_elem_info
*elem_info
;
952 elem_info
= mlxsw_pci_queue_elem_info_get(q
, i
);
954 __mlxsw_pci_queue_elem_get(q
, q_ops
->elem_size
, i
);
957 mlxsw_cmd_mbox_zero(mbox
);
958 err
= q_ops
->init(mlxsw_pci
, mbox
, q
);
966 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
967 mem_item
->buf
, mem_item
->mapaddr
);
971 static void mlxsw_pci_queue_fini(struct mlxsw_pci
*mlxsw_pci
,
972 const struct mlxsw_pci_queue_ops
*q_ops
,
973 struct mlxsw_pci_queue
*q
)
975 struct mlxsw_pci_mem_item
*mem_item
= &q
->mem_item
;
977 q_ops
->fini(mlxsw_pci
, q
);
979 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
980 mem_item
->buf
, mem_item
->mapaddr
);
983 static int mlxsw_pci_queue_group_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
984 const struct mlxsw_pci_queue_ops
*q_ops
,
987 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
988 struct mlxsw_pci_queue_type_group
*queue_group
;
993 queue_group
= mlxsw_pci_queue_type_group_get(mlxsw_pci
, q_ops
->type
);
994 queue_group
->q
= kcalloc(num_qs
, sizeof(*queue_group
->q
), GFP_KERNEL
);
998 for (i
= 0; i
< num_qs
; i
++) {
999 err
= mlxsw_pci_queue_init(mlxsw_pci
, mbox
, q_ops
,
1000 &queue_group
->q
[i
], i
);
1002 goto err_queue_init
;
1004 queue_group
->count
= num_qs
;
1006 sprintf(tmp
, "%s_stats", mlxsw_pci_queue_type_str(q_ops
->type
));
1007 debugfs_create_devm_seqfile(&pdev
->dev
, tmp
, mlxsw_pci
->dbg_dir
,
1013 for (i
--; i
>= 0; i
--)
1014 mlxsw_pci_queue_fini(mlxsw_pci
, q_ops
, &queue_group
->q
[i
]);
1015 kfree(queue_group
->q
);
1019 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci
*mlxsw_pci
,
1020 const struct mlxsw_pci_queue_ops
*q_ops
)
1022 struct mlxsw_pci_queue_type_group
*queue_group
;
1025 queue_group
= mlxsw_pci_queue_type_group_get(mlxsw_pci
, q_ops
->type
);
1026 for (i
= 0; i
< queue_group
->count
; i
++)
1027 mlxsw_pci_queue_fini(mlxsw_pci
, q_ops
, &queue_group
->q
[i
]);
1028 kfree(queue_group
->q
);
1031 static int mlxsw_pci_aqs_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
)
1033 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1044 mlxsw_cmd_mbox_zero(mbox
);
1045 err
= mlxsw_cmd_query_aq_cap(mlxsw_pci
->core
, mbox
);
1049 num_sdqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox
);
1050 sdq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox
);
1051 num_rdqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox
);
1052 rdq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox
);
1053 num_cqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox
);
1054 cq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox
);
1055 num_eqs
= mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox
);
1056 eq_log2sz
= mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox
);
1058 if (num_sdqs
+ num_rdqs
> num_cqs
||
1059 num_cqs
> MLXSW_PCI_CQS_MAX
|| num_eqs
!= MLXSW_PCI_EQS_COUNT
) {
1060 dev_err(&pdev
->dev
, "Unsupported number of queues\n");
1064 if ((1 << sdq_log2sz
!= MLXSW_PCI_WQE_COUNT
) ||
1065 (1 << rdq_log2sz
!= MLXSW_PCI_WQE_COUNT
) ||
1066 (1 << cq_log2sz
!= MLXSW_PCI_CQE_COUNT
) ||
1067 (1 << eq_log2sz
!= MLXSW_PCI_EQE_COUNT
)) {
1068 dev_err(&pdev
->dev
, "Unsupported number of async queue descriptors\n");
1072 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_eq_ops
,
1075 dev_err(&pdev
->dev
, "Failed to initialize event queues\n");
1079 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_cq_ops
,
1082 dev_err(&pdev
->dev
, "Failed to initialize completion queues\n");
1086 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_sdq_ops
,
1089 dev_err(&pdev
->dev
, "Failed to initialize send descriptor queues\n");
1093 err
= mlxsw_pci_queue_group_init(mlxsw_pci
, mbox
, &mlxsw_pci_rdq_ops
,
1096 dev_err(&pdev
->dev
, "Failed to initialize receive descriptor queues\n");
1100 /* We have to poll in command interface until queues are initialized */
1101 mlxsw_pci
->cmd
.nopoll
= true;
1105 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_sdq_ops
);
1107 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_cq_ops
);
1109 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_eq_ops
);
1113 static void mlxsw_pci_aqs_fini(struct mlxsw_pci
*mlxsw_pci
)
1115 mlxsw_pci
->cmd
.nopoll
= false;
1116 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_rdq_ops
);
1117 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_sdq_ops
);
1118 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_cq_ops
);
1119 mlxsw_pci_queue_group_fini(mlxsw_pci
, &mlxsw_pci_eq_ops
);
1123 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci
*mlxsw_pci
,
1124 char *mbox
, int index
,
1125 const struct mlxsw_swid_config
*swid
)
1129 if (swid
->used_type
) {
1130 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1131 mbox
, index
, swid
->type
);
1134 if (swid
->used_properties
) {
1135 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1136 mbox
, index
, swid
->properties
);
1139 mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox
, index
, mask
);
1142 static int mlxsw_pci_resources_query(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
1143 struct mlxsw_res
*res
,
1151 /* Not all the versions support resources query */
1155 mlxsw_cmd_mbox_zero(mbox
);
1157 for (index
= 0; index
< MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES
;
1159 err
= mlxsw_cmd_query_resources(mlxsw_pci
->core
, mbox
, index
);
1163 for (i
= 0; i
< MLXSW_CMD_QUERY_RESOURCES_PER_QUERY
; i
++) {
1164 id
= mlxsw_cmd_mbox_query_resource_id_get(mbox
, i
);
1165 data
= mlxsw_cmd_mbox_query_resource_data_get(mbox
, i
);
1167 if (id
== MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID
)
1170 mlxsw_res_parse(res
, id
, data
);
1174 /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get
1175 * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW.
1181 mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_config_profile
*profile
,
1182 struct mlxsw_res
*res
)
1184 u32 single_size
, double_size
, linear_size
;
1186 if (!MLXSW_RES_VALID(res
, KVD_SINGLE_MIN_SIZE
) ||
1187 !MLXSW_RES_VALID(res
, KVD_DOUBLE_MIN_SIZE
) ||
1188 !profile
->used_kvd_split_data
)
1191 linear_size
= profile
->kvd_linear_size
;
1193 /* The hash part is what left of the kvd without the
1194 * linear part. It is split to the single size and
1195 * double size by the parts ratio from the profile.
1196 * Both sizes must be a multiplications of the
1197 * granularity from the profile.
1199 double_size
= MLXSW_RES_GET(res
, KVD_SIZE
) - linear_size
;
1200 double_size
*= profile
->kvd_hash_double_parts
;
1201 double_size
/= profile
->kvd_hash_double_parts
+
1202 profile
->kvd_hash_single_parts
;
1203 double_size
/= profile
->kvd_hash_granularity
;
1204 double_size
*= profile
->kvd_hash_granularity
;
1205 single_size
= MLXSW_RES_GET(res
, KVD_SIZE
) - double_size
-
1208 /* Check results are legal. */
1209 if (single_size
< MLXSW_RES_GET(res
, KVD_SINGLE_MIN_SIZE
) ||
1210 double_size
< MLXSW_RES_GET(res
, KVD_DOUBLE_MIN_SIZE
) ||
1211 MLXSW_RES_GET(res
, KVD_SIZE
) < linear_size
)
1214 MLXSW_RES_SET(res
, KVD_SINGLE_SIZE
, single_size
);
1215 MLXSW_RES_SET(res
, KVD_DOUBLE_SIZE
, double_size
);
1216 MLXSW_RES_SET(res
, KVD_LINEAR_SIZE
, linear_size
);
1221 static int mlxsw_pci_config_profile(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
1222 const struct mlxsw_config_profile
*profile
,
1223 struct mlxsw_res
*res
)
1228 mlxsw_cmd_mbox_zero(mbox
);
1230 if (profile
->used_max_vepa_channels
) {
1231 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1233 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1234 mbox
, profile
->max_vepa_channels
);
1236 if (profile
->used_max_mid
) {
1237 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1239 mlxsw_cmd_mbox_config_profile_max_mid_set(
1240 mbox
, profile
->max_mid
);
1242 if (profile
->used_max_pgt
) {
1243 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1245 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1246 mbox
, profile
->max_pgt
);
1248 if (profile
->used_max_system_port
) {
1249 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1251 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1252 mbox
, profile
->max_system_port
);
1254 if (profile
->used_max_vlan_groups
) {
1255 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1257 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1258 mbox
, profile
->max_vlan_groups
);
1260 if (profile
->used_max_regions
) {
1261 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1263 mlxsw_cmd_mbox_config_profile_max_regions_set(
1264 mbox
, profile
->max_regions
);
1266 if (profile
->used_flood_tables
) {
1267 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1269 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1270 mbox
, profile
->max_flood_tables
);
1271 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1272 mbox
, profile
->max_vid_flood_tables
);
1273 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set(
1274 mbox
, profile
->max_fid_offset_flood_tables
);
1275 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set(
1276 mbox
, profile
->fid_offset_flood_table_size
);
1277 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set(
1278 mbox
, profile
->max_fid_flood_tables
);
1279 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(
1280 mbox
, profile
->fid_flood_table_size
);
1282 if (profile
->used_flood_mode
) {
1283 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1285 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1286 mbox
, profile
->flood_mode
);
1288 if (profile
->used_max_ib_mc
) {
1289 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1291 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1292 mbox
, profile
->max_ib_mc
);
1294 if (profile
->used_max_pkey
) {
1295 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1297 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1298 mbox
, profile
->max_pkey
);
1300 if (profile
->used_ar_sec
) {
1301 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1303 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1304 mbox
, profile
->ar_sec
);
1306 if (profile
->used_adaptive_routing_group_cap
) {
1307 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1309 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1310 mbox
, profile
->adaptive_routing_group_cap
);
1312 if (MLXSW_RES_VALID(res
, KVD_SIZE
)) {
1313 err
= mlxsw_pci_profile_get_kvd_sizes(profile
, res
);
1317 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox
, 1);
1318 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox
,
1319 MLXSW_RES_GET(res
, KVD_LINEAR_SIZE
));
1320 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox
,
1322 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox
,
1323 MLXSW_RES_GET(res
, KVD_SINGLE_SIZE
));
1324 mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set(
1326 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox
,
1327 MLXSW_RES_GET(res
, KVD_DOUBLE_SIZE
));
1330 for (i
= 0; i
< MLXSW_CONFIG_PROFILE_SWID_COUNT
; i
++)
1331 mlxsw_pci_config_profile_swid_config(mlxsw_pci
, mbox
, i
,
1332 &profile
->swid_config
[i
]);
1334 return mlxsw_cmd_config_profile_set(mlxsw_pci
->core
, mbox
);
1337 static int mlxsw_pci_boardinfo(struct mlxsw_pci
*mlxsw_pci
, char *mbox
)
1339 struct mlxsw_bus_info
*bus_info
= &mlxsw_pci
->bus_info
;
1342 mlxsw_cmd_mbox_zero(mbox
);
1343 err
= mlxsw_cmd_boardinfo(mlxsw_pci
->core
, mbox
);
1346 mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox
, bus_info
->vsd
);
1347 mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox
, bus_info
->psid
);
1351 static int mlxsw_pci_fw_area_init(struct mlxsw_pci
*mlxsw_pci
, char *mbox
,
1354 struct mlxsw_pci_mem_item
*mem_item
;
1359 mlxsw_pci
->fw_area
.items
= kcalloc(num_pages
, sizeof(*mem_item
),
1361 if (!mlxsw_pci
->fw_area
.items
)
1363 mlxsw_pci
->fw_area
.count
= num_pages
;
1365 mlxsw_cmd_mbox_zero(mbox
);
1366 for (i
= 0; i
< num_pages
; i
++) {
1367 mem_item
= &mlxsw_pci
->fw_area
.items
[i
];
1369 mem_item
->size
= MLXSW_PCI_PAGE_SIZE
;
1370 mem_item
->buf
= pci_alloc_consistent(mlxsw_pci
->pdev
,
1372 &mem_item
->mapaddr
);
1373 if (!mem_item
->buf
) {
1377 mlxsw_cmd_mbox_map_fa_pa_set(mbox
, nent
, mem_item
->mapaddr
);
1378 mlxsw_cmd_mbox_map_fa_log2size_set(mbox
, nent
, 0); /* 1 page */
1379 if (++nent
== MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX
) {
1380 err
= mlxsw_cmd_map_fa(mlxsw_pci
->core
, mbox
, nent
);
1382 goto err_cmd_map_fa
;
1384 mlxsw_cmd_mbox_zero(mbox
);
1389 err
= mlxsw_cmd_map_fa(mlxsw_pci
->core
, mbox
, nent
);
1391 goto err_cmd_map_fa
;
1398 for (i
--; i
>= 0; i
--) {
1399 mem_item
= &mlxsw_pci
->fw_area
.items
[i
];
1401 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
1402 mem_item
->buf
, mem_item
->mapaddr
);
1404 kfree(mlxsw_pci
->fw_area
.items
);
1408 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci
*mlxsw_pci
)
1410 struct mlxsw_pci_mem_item
*mem_item
;
1413 mlxsw_cmd_unmap_fa(mlxsw_pci
->core
);
1415 for (i
= 0; i
< mlxsw_pci
->fw_area
.count
; i
++) {
1416 mem_item
= &mlxsw_pci
->fw_area
.items
[i
];
1418 pci_free_consistent(mlxsw_pci
->pdev
, mem_item
->size
,
1419 mem_item
->buf
, mem_item
->mapaddr
);
1421 kfree(mlxsw_pci
->fw_area
.items
);
1424 static irqreturn_t
mlxsw_pci_eq_irq_handler(int irq
, void *dev_id
)
1426 struct mlxsw_pci
*mlxsw_pci
= dev_id
;
1427 struct mlxsw_pci_queue
*q
;
1430 for (i
= 0; i
< MLXSW_PCI_EQS_COUNT
; i
++) {
1431 q
= mlxsw_pci_eq_get(mlxsw_pci
, i
);
1432 mlxsw_pci_queue_tasklet_schedule(q
);
1437 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci
*mlxsw_pci
,
1438 struct mlxsw_pci_mem_item
*mbox
)
1440 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1443 mbox
->size
= MLXSW_CMD_MBOX_SIZE
;
1444 mbox
->buf
= pci_alloc_consistent(pdev
, MLXSW_CMD_MBOX_SIZE
,
1447 dev_err(&pdev
->dev
, "Failed allocating memory for mailbox\n");
1454 static void mlxsw_pci_mbox_free(struct mlxsw_pci
*mlxsw_pci
,
1455 struct mlxsw_pci_mem_item
*mbox
)
1457 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1459 pci_free_consistent(pdev
, MLXSW_CMD_MBOX_SIZE
, mbox
->buf
,
1463 static int mlxsw_pci_init(void *bus_priv
, struct mlxsw_core
*mlxsw_core
,
1464 const struct mlxsw_config_profile
*profile
,
1465 struct mlxsw_res
*res
)
1467 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1468 struct pci_dev
*pdev
= mlxsw_pci
->pdev
;
1473 mutex_init(&mlxsw_pci
->cmd
.lock
);
1474 init_waitqueue_head(&mlxsw_pci
->cmd
.wait
);
1476 mlxsw_pci
->core
= mlxsw_core
;
1478 mbox
= mlxsw_cmd_mbox_alloc();
1482 err
= mlxsw_pci_mbox_alloc(mlxsw_pci
, &mlxsw_pci
->cmd
.in_mbox
);
1486 err
= mlxsw_pci_mbox_alloc(mlxsw_pci
, &mlxsw_pci
->cmd
.out_mbox
);
1488 goto err_out_mbox_alloc
;
1490 err
= mlxsw_cmd_query_fw(mlxsw_core
, mbox
);
1494 mlxsw_pci
->bus_info
.fw_rev
.major
=
1495 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox
);
1496 mlxsw_pci
->bus_info
.fw_rev
.minor
=
1497 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox
);
1498 mlxsw_pci
->bus_info
.fw_rev
.subminor
=
1499 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox
);
1501 if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox
) != 1) {
1502 dev_err(&pdev
->dev
, "Unsupported cmd interface revision ID queried from hw\n");
1506 if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox
) != 0) {
1507 dev_err(&pdev
->dev
, "Unsupported doorbell page bar queried from hw\n");
1509 goto err_doorbell_page_bar
;
1512 mlxsw_pci
->doorbell_offset
=
1513 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox
);
1515 num_pages
= mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox
);
1516 err
= mlxsw_pci_fw_area_init(mlxsw_pci
, mbox
, num_pages
);
1518 goto err_fw_area_init
;
1520 err
= mlxsw_pci_boardinfo(mlxsw_pci
, mbox
);
1524 err
= mlxsw_pci_resources_query(mlxsw_pci
, mbox
, res
,
1525 profile
->resource_query_enable
);
1527 goto err_query_resources
;
1529 err
= mlxsw_pci_config_profile(mlxsw_pci
, mbox
, profile
, res
);
1531 goto err_config_profile
;
1533 err
= mlxsw_pci_aqs_init(mlxsw_pci
, mbox
);
1537 err
= request_irq(mlxsw_pci
->msix_entry
.vector
,
1538 mlxsw_pci_eq_irq_handler
, 0,
1539 mlxsw_pci
->bus_info
.device_kind
, mlxsw_pci
);
1541 dev_err(&pdev
->dev
, "IRQ request failed\n");
1542 goto err_request_eq_irq
;
1548 mlxsw_pci_aqs_fini(mlxsw_pci
);
1551 err_query_resources
:
1553 mlxsw_pci_fw_area_fini(mlxsw_pci
);
1555 err_doorbell_page_bar
:
1558 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.out_mbox
);
1560 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.in_mbox
);
1562 mlxsw_cmd_mbox_free(mbox
);
1566 static void mlxsw_pci_fini(void *bus_priv
)
1568 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1570 free_irq(mlxsw_pci
->msix_entry
.vector
, mlxsw_pci
);
1571 mlxsw_pci_aqs_fini(mlxsw_pci
);
1572 mlxsw_pci_fw_area_fini(mlxsw_pci
);
1573 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.out_mbox
);
1574 mlxsw_pci_mbox_free(mlxsw_pci
, &mlxsw_pci
->cmd
.in_mbox
);
1577 static struct mlxsw_pci_queue
*
1578 mlxsw_pci_sdq_pick(struct mlxsw_pci
*mlxsw_pci
,
1579 const struct mlxsw_tx_info
*tx_info
)
1581 u8 sdqn
= tx_info
->local_port
% mlxsw_pci_sdq_count(mlxsw_pci
);
1583 return mlxsw_pci_sdq_get(mlxsw_pci
, sdqn
);
1586 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv
,
1587 const struct mlxsw_tx_info
*tx_info
)
1589 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1590 struct mlxsw_pci_queue
*q
= mlxsw_pci_sdq_pick(mlxsw_pci
, tx_info
);
1592 return !mlxsw_pci_queue_elem_info_producer_get(q
);
1595 static int mlxsw_pci_skb_transmit(void *bus_priv
, struct sk_buff
*skb
,
1596 const struct mlxsw_tx_info
*tx_info
)
1598 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1599 struct mlxsw_pci_queue
*q
;
1600 struct mlxsw_pci_queue_elem_info
*elem_info
;
1605 if (skb_shinfo(skb
)->nr_frags
> MLXSW_PCI_WQE_SG_ENTRIES
- 1) {
1606 err
= skb_linearize(skb
);
1611 q
= mlxsw_pci_sdq_pick(mlxsw_pci
, tx_info
);
1612 spin_lock_bh(&q
->lock
);
1613 elem_info
= mlxsw_pci_queue_elem_info_producer_get(q
);
1619 elem_info
->u
.sdq
.skb
= skb
;
1621 wqe
= elem_info
->elem
;
1622 mlxsw_pci_wqe_c_set(wqe
, 1); /* always report completion */
1623 mlxsw_pci_wqe_lp_set(wqe
, !!tx_info
->is_emad
);
1624 mlxsw_pci_wqe_type_set(wqe
, MLXSW_PCI_WQE_TYPE_ETHERNET
);
1626 err
= mlxsw_pci_wqe_frag_map(mlxsw_pci
, wqe
, 0, skb
->data
,
1627 skb_headlen(skb
), DMA_TO_DEVICE
);
1631 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1632 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1634 err
= mlxsw_pci_wqe_frag_map(mlxsw_pci
, wqe
, i
+ 1,
1635 skb_frag_address(frag
),
1636 skb_frag_size(frag
),
1642 /* Set unused sq entries byte count to zero. */
1643 for (i
++; i
< MLXSW_PCI_WQE_SG_ENTRIES
; i
++)
1644 mlxsw_pci_wqe_byte_count_set(wqe
, i
, 0);
1646 /* Everything is set up, ring producer doorbell to get HW going */
1647 q
->producer_counter
++;
1648 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci
, q
);
1654 mlxsw_pci_wqe_frag_unmap(mlxsw_pci
, wqe
, i
, DMA_TO_DEVICE
);
1656 spin_unlock_bh(&q
->lock
);
1660 static int mlxsw_pci_cmd_exec(void *bus_priv
, u16 opcode
, u8 opcode_mod
,
1661 u32 in_mod
, bool out_mbox_direct
,
1662 char *in_mbox
, size_t in_mbox_size
,
1663 char *out_mbox
, size_t out_mbox_size
,
1666 struct mlxsw_pci
*mlxsw_pci
= bus_priv
;
1667 dma_addr_t in_mapaddr
= mlxsw_pci
->cmd
.in_mbox
.mapaddr
;
1668 dma_addr_t out_mapaddr
= mlxsw_pci
->cmd
.out_mbox
.mapaddr
;
1669 bool evreq
= mlxsw_pci
->cmd
.nopoll
;
1670 unsigned long timeout
= msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS
);
1671 bool *p_wait_done
= &mlxsw_pci
->cmd
.wait_done
;
1674 *p_status
= MLXSW_CMD_STATUS_OK
;
1676 err
= mutex_lock_interruptible(&mlxsw_pci
->cmd
.lock
);
1681 memcpy(mlxsw_pci
->cmd
.in_mbox
.buf
, in_mbox
, in_mbox_size
);
1682 mlxsw_pci_write32(mlxsw_pci
, CIR_IN_PARAM_HI
, upper_32_bits(in_mapaddr
));
1683 mlxsw_pci_write32(mlxsw_pci
, CIR_IN_PARAM_LO
, lower_32_bits(in_mapaddr
));
1685 mlxsw_pci_write32(mlxsw_pci
, CIR_OUT_PARAM_HI
, upper_32_bits(out_mapaddr
));
1686 mlxsw_pci_write32(mlxsw_pci
, CIR_OUT_PARAM_LO
, lower_32_bits(out_mapaddr
));
1688 mlxsw_pci_write32(mlxsw_pci
, CIR_IN_MODIFIER
, in_mod
);
1689 mlxsw_pci_write32(mlxsw_pci
, CIR_TOKEN
, 0);
1691 *p_wait_done
= false;
1693 wmb(); /* all needs to be written before we write control register */
1694 mlxsw_pci_write32(mlxsw_pci
, CIR_CTRL
,
1695 MLXSW_PCI_CIR_CTRL_GO_BIT
|
1696 (evreq
? MLXSW_PCI_CIR_CTRL_EVREQ_BIT
: 0) |
1697 (opcode_mod
<< MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT
) |
1703 end
= jiffies
+ timeout
;
1705 u32 ctrl
= mlxsw_pci_read32(mlxsw_pci
, CIR_CTRL
);
1707 if (!(ctrl
& MLXSW_PCI_CIR_CTRL_GO_BIT
)) {
1708 *p_wait_done
= true;
1709 *p_status
= ctrl
>> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT
;
1713 } while (time_before(jiffies
, end
));
1715 wait_event_timeout(mlxsw_pci
->cmd
.wait
, *p_wait_done
, timeout
);
1716 *p_status
= mlxsw_pci
->cmd
.comp
.status
;
1727 if (!err
&& out_mbox
&& out_mbox_direct
) {
1728 /* Some commands don't use output param as address to mailbox
1729 * but they store output directly into registers. In that case,
1730 * copy registers into mbox buffer.
1735 tmp
= cpu_to_be32(mlxsw_pci_read32(mlxsw_pci
,
1737 memcpy(out_mbox
, &tmp
, sizeof(tmp
));
1738 tmp
= cpu_to_be32(mlxsw_pci_read32(mlxsw_pci
,
1740 memcpy(out_mbox
+ sizeof(tmp
), &tmp
, sizeof(tmp
));
1742 } else if (!err
&& out_mbox
) {
1743 memcpy(out_mbox
, mlxsw_pci
->cmd
.out_mbox
.buf
, out_mbox_size
);
1746 mutex_unlock(&mlxsw_pci
->cmd
.lock
);
1751 static const struct mlxsw_bus mlxsw_pci_bus
= {
1753 .init
= mlxsw_pci_init
,
1754 .fini
= mlxsw_pci_fini
,
1755 .skb_transmit_busy
= mlxsw_pci_skb_transmit_busy
,
1756 .skb_transmit
= mlxsw_pci_skb_transmit
,
1757 .cmd_exec
= mlxsw_pci_cmd_exec
,
1758 .features
= MLXSW_BUS_F_TXRX
,
1761 static int mlxsw_pci_sw_reset(struct mlxsw_pci
*mlxsw_pci
,
1762 const struct pci_device_id
*id
)
1766 mlxsw_pci_write32(mlxsw_pci
, SW_RESET
, MLXSW_PCI_SW_RESET_RST_BIT
);
1767 if (id
->device
== PCI_DEVICE_ID_MELLANOX_SWITCHX2
) {
1768 msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS
);
1772 wmb(); /* reset needs to be written before we read control register */
1773 end
= jiffies
+ msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS
);
1775 u32 val
= mlxsw_pci_read32(mlxsw_pci
, FW_READY
);
1777 if ((val
& MLXSW_PCI_FW_READY_MASK
) == MLXSW_PCI_FW_READY_MAGIC
)
1780 } while (time_before(jiffies
, end
));
1784 static int mlxsw_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1786 const char *driver_name
= pdev
->driver
->name
;
1787 struct mlxsw_pci
*mlxsw_pci
;
1790 mlxsw_pci
= kzalloc(sizeof(*mlxsw_pci
), GFP_KERNEL
);
1794 err
= pci_enable_device(pdev
);
1796 dev_err(&pdev
->dev
, "pci_enable_device failed\n");
1797 goto err_pci_enable_device
;
1800 err
= pci_request_regions(pdev
, driver_name
);
1802 dev_err(&pdev
->dev
, "pci_request_regions failed\n");
1803 goto err_pci_request_regions
;
1806 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
1808 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
1810 dev_err(&pdev
->dev
, "pci_set_consistent_dma_mask failed\n");
1811 goto err_pci_set_dma_mask
;
1814 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
1816 dev_err(&pdev
->dev
, "pci_set_dma_mask failed\n");
1817 goto err_pci_set_dma_mask
;
1821 if (pci_resource_len(pdev
, 0) < MLXSW_PCI_BAR0_SIZE
) {
1822 dev_err(&pdev
->dev
, "invalid PCI region size\n");
1824 goto err_pci_resource_len_check
;
1827 mlxsw_pci
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
1828 pci_resource_len(pdev
, 0));
1829 if (!mlxsw_pci
->hw_addr
) {
1830 dev_err(&pdev
->dev
, "ioremap failed\n");
1834 pci_set_master(pdev
);
1836 mlxsw_pci
->pdev
= pdev
;
1837 pci_set_drvdata(pdev
, mlxsw_pci
);
1839 err
= mlxsw_pci_sw_reset(mlxsw_pci
, id
);
1841 dev_err(&pdev
->dev
, "Software reset failed\n");
1845 err
= pci_enable_msix_exact(pdev
, &mlxsw_pci
->msix_entry
, 1);
1847 dev_err(&pdev
->dev
, "MSI-X init failed\n");
1851 mlxsw_pci
->bus_info
.device_kind
= driver_name
;
1852 mlxsw_pci
->bus_info
.device_name
= pci_name(mlxsw_pci
->pdev
);
1853 mlxsw_pci
->bus_info
.dev
= &pdev
->dev
;
1855 mlxsw_pci
->dbg_dir
= debugfs_create_dir(mlxsw_pci
->bus_info
.device_name
,
1856 mlxsw_pci_dbg_root
);
1857 if (!mlxsw_pci
->dbg_dir
) {
1858 dev_err(&pdev
->dev
, "Failed to create debugfs dir\n");
1860 goto err_dbg_create_dir
;
1863 err
= mlxsw_core_bus_device_register(&mlxsw_pci
->bus_info
,
1864 &mlxsw_pci_bus
, mlxsw_pci
);
1866 dev_err(&pdev
->dev
, "cannot register bus device\n");
1867 goto err_bus_device_register
;
1872 err_bus_device_register
:
1873 debugfs_remove_recursive(mlxsw_pci
->dbg_dir
);
1875 pci_disable_msix(mlxsw_pci
->pdev
);
1878 iounmap(mlxsw_pci
->hw_addr
);
1880 err_pci_resource_len_check
:
1881 err_pci_set_dma_mask
:
1882 pci_release_regions(pdev
);
1883 err_pci_request_regions
:
1884 pci_disable_device(pdev
);
1885 err_pci_enable_device
:
1890 static void mlxsw_pci_remove(struct pci_dev
*pdev
)
1892 struct mlxsw_pci
*mlxsw_pci
= pci_get_drvdata(pdev
);
1894 mlxsw_core_bus_device_unregister(mlxsw_pci
->core
);
1895 debugfs_remove_recursive(mlxsw_pci
->dbg_dir
);
1896 pci_disable_msix(mlxsw_pci
->pdev
);
1897 iounmap(mlxsw_pci
->hw_addr
);
1898 pci_release_regions(mlxsw_pci
->pdev
);
1899 pci_disable_device(mlxsw_pci
->pdev
);
1903 int mlxsw_pci_driver_register(struct pci_driver
*pci_driver
)
1905 pci_driver
->probe
= mlxsw_pci_probe
;
1906 pci_driver
->remove
= mlxsw_pci_remove
;
1907 return pci_register_driver(pci_driver
);
1909 EXPORT_SYMBOL(mlxsw_pci_driver_register
);
1911 void mlxsw_pci_driver_unregister(struct pci_driver
*pci_driver
)
1913 pci_unregister_driver(pci_driver
);
1915 EXPORT_SYMBOL(mlxsw_pci_driver_unregister
);
1917 static int __init
mlxsw_pci_module_init(void)
1919 mlxsw_pci_dbg_root
= debugfs_create_dir(mlxsw_pci_driver_name
, NULL
);
1920 if (!mlxsw_pci_dbg_root
)
1925 static void __exit
mlxsw_pci_module_exit(void)
1927 debugfs_remove_recursive(mlxsw_pci_dbg_root
);
1930 module_init(mlxsw_pci_module_init
);
1931 module_exit(mlxsw_pci_module_exit
);
1933 MODULE_LICENSE("Dual BSD/GPL");
1934 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1935 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");