drivers/net/ethernet/mellanox/mlxsw/pci.h

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/pci.h
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the names of the copyright holders nor the names of its
  15  *    contributors may be used to endorse or promote products derived from
  16  *    this software without specific prior written permission.
  17  *
  18  * Alternatively, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") version 2 as published by the Free
  20  * Software Foundation.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #ifndef _MLXSW_PCI_H
  36 #define _MLXSW_PCI_H
  37
  38 #include <linux/bitops.h>
  39
  40 #include "item.h"
  41
  42 #define PCI_DEVICE_ID_MELLANOX_SWITCHX2 0xc738
  43 #define PCI_DEVICE_ID_MELLANOX_SPECTRUM 0xcb84
  44 #define MLXSW_PCI_BAR0_SIZE             (1024 * 1024) /* 1MB */
  45 #define MLXSW_PCI_PAGE_SIZE             4096
  46
  47 #define MLXSW_PCI_CIR_BASE                      0x71000
  48 #define MLXSW_PCI_CIR_IN_PARAM_HI               MLXSW_PCI_CIR_BASE
  49 #define MLXSW_PCI_CIR_IN_PARAM_LO               (MLXSW_PCI_CIR_BASE + 0x04)
  50 #define MLXSW_PCI_CIR_IN_MODIFIER               (MLXSW_PCI_CIR_BASE + 0x08)
  51 #define MLXSW_PCI_CIR_OUT_PARAM_HI              (MLXSW_PCI_CIR_BASE + 0x0C)
  52 #define MLXSW_PCI_CIR_OUT_PARAM_LO              (MLXSW_PCI_CIR_BASE + 0x10)
  53 #define MLXSW_PCI_CIR_TOKEN                     (MLXSW_PCI_CIR_BASE + 0x14)
  54 #define MLXSW_PCI_CIR_CTRL                      (MLXSW_PCI_CIR_BASE + 0x18)
  55 #define MLXSW_PCI_CIR_CTRL_GO_BIT               BIT(23)
  56 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT            BIT(22)
  57 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT     12
  58 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT         24
  59 #define MLXSW_PCI_CIR_TIMEOUT_MSECS             1000
  60
  61 #define MLXSW_PCI_SW_RESET                      0xF0010
  62 #define MLXSW_PCI_SW_RESET_RST_BIT              BIT(0)
  63 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS        5000
  64 #define MLXSW_PCI_FW_READY                      0xA1844
  65 #define MLXSW_PCI_FW_READY_MASK                 0xFF
  66 #define MLXSW_PCI_FW_READY_MAGIC                0x5E
  67
  68 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET           0x000
  69 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET           0x200
  70 #define MLXSW_PCI_DOORBELL_CQ_OFFSET            0x400
  71 #define MLXSW_PCI_DOORBELL_EQ_OFFSET            0x600
  72 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET        0x800
  73 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET        0xA00
  74
  75 #define MLXSW_PCI_DOORBELL(offset, type_offset, num)    \
  76         ((offset) + (type_offset) + (num) * 4)
  77
  78 #define MLXSW_PCI_CQS_MAX       96
  79 #define MLXSW_PCI_EQS_COUNT     2
  80 #define MLXSW_PCI_EQ_ASYNC_NUM  0
  81 #define MLXSW_PCI_EQ_COMP_NUM   1
  82
  83 #define MLXSW_PCI_AQ_PAGES      8
  84 #define MLXSW_PCI_AQ_SIZE       (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
  85 #define MLXSW_PCI_WQE_SIZE      32 /* 32 bytes per element */
  86 #define MLXSW_PCI_CQE_SIZE      16 /* 16 bytes per element */
  87 #define MLXSW_PCI_EQE_SIZE      16 /* 16 bytes per element */
  88 #define MLXSW_PCI_WQE_COUNT     (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
  89 #define MLXSW_PCI_CQE_COUNT     (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE_SIZE)
  90 #define MLXSW_PCI_EQE_COUNT     (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
  91 #define MLXSW_PCI_EQE_UPDATE_COUNT      0x80
  92
  93 #define MLXSW_PCI_WQE_SG_ENTRIES        3
  94 #define MLXSW_PCI_WQE_TYPE_ETHERNET     0xA
  95
  96 /* pci_wqe_c
  97  * If set it indicates that a completion should be reported upon
  98  * execution of this descriptor.
  99  */
 100 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
 101
 102 /* pci_wqe_lp
 103  * Local Processing, set if packet should be processed by the local
 104  * switch hardware:
 105  * For Ethernet EMAD (Direct Route and non Direct Route) -
 106  * must be set if packet destination is local device
 107  * For InfiniBand CTL - must be set if packet destination is local device
 108  * Otherwise it must be clear
 109  * Local Process packets must not exceed the size of 2K (including payload
 110  * and headers).
 111  */
 112 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
 113
 114 /* pci_wqe_type
 115  * Packet type.
 116  */
 117 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
 118
 119 /* pci_wqe_byte_count
 120  * Size of i-th scatter/gather entry, 0 if entry is unused.
 121  */
 122 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
 123
 124 /* pci_wqe_address
 125  * Physical address of i-th scatter/gather entry.
 126  * Gather Entries must be 2Byte aligned.
 127  */
 128 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
 129
 130 /* pci_cqe_lag
 131  * Packet arrives from a port which is a LAG
 132  */
 133 MLXSW_ITEM32(pci, cqe, lag, 0x00, 23, 1);
 134
 135 /* pci_cqe_system_port/lag_id
 136  * When lag=0: System port on which the packet was received
 137  * When lag=1:
 138  * bits [15:4] LAG ID on which the packet was received
 139  * bits [3:0] sub_port on which the packet was received
 140  */
 141 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
 142 MLXSW_ITEM32(pci, cqe, lag_id, 0x00, 4, 12);
 143 MLXSW_ITEM32(pci, cqe, lag_port_index, 0x00, 0, 4);
 144
 145 /* pci_cqe_wqe_counter
 146  * WQE count of the WQEs completed on the associated dqn
 147  */
 148 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
 149
 150 /* pci_cqe_byte_count
 151  * Byte count of received packets including additional two
 152  * Reserved Bytes that are append to the end of the frame.
 153  * Reserved for Send CQE.
 154  */
 155 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
 156
 157 /* pci_cqe_trap_id
 158  * Trap ID that captured the packet.
 159  */
 160 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 8);
 161
 162 /* pci_cqe_crc
 163  * Length include CRC. Indicates the length field includes
 164  * the packet's CRC.
 165  */
 166 MLXSW_ITEM32(pci, cqe, crc, 0x0C, 8, 1);
 167
 168 /* pci_cqe_e
 169  * CQE with Error.
 170  */
 171 MLXSW_ITEM32(pci, cqe, e, 0x0C, 7, 1);
 172
 173 /* pci_cqe_sr
 174  * 1 - Send Queue
 175  * 0 - Receive Queue
 176  */
 177 MLXSW_ITEM32(pci, cqe, sr, 0x0C, 6, 1);
 178
 179 /* pci_cqe_dqn
 180  * Descriptor Queue (DQ) Number.
 181  */
 182 MLXSW_ITEM32(pci, cqe, dqn, 0x0C, 1, 5);
 183
 184 /* pci_cqe_owner
 185  * Ownership bit.
 186  */
 187 MLXSW_ITEM32(pci, cqe, owner, 0x0C, 0, 1);
 188
 189 /* pci_eqe_event_type
 190  * Event type.
 191  */
 192 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
 193 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP   0x00
 194 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD    0x0A
 195
 196 /* pci_eqe_event_sub_type
 197  * Event type.
 198  */
 199 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
 200
 201 /* pci_eqe_cqn
 202  * Completion Queue that triggeret this EQE.
 203  */
 204 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
 205
 206 /* pci_eqe_owner
 207  * Ownership bit.
 208  */
 209 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
 210
 211 /* pci_eqe_cmd_token
 212  * Command completion event - token
 213  */
 214 MLXSW_ITEM32(pci, eqe, cmd_token, 0x08, 16, 16);
 215
 216 /* pci_eqe_cmd_status
 217  * Command completion event - status
 218  */
 219 MLXSW_ITEM32(pci, eqe, cmd_status, 0x08, 0, 8);
 220
 221 /* pci_eqe_cmd_out_param_h
 222  * Command completion event - output parameter - higher part
 223  */
 224 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x0C, 0, 32);
 225
 226 /* pci_eqe_cmd_out_param_l
 227  * Command completion event - output parameter - lower part
 228  */
 229 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x10, 0, 32);
 230
 231 #endif