drivers/net/ethernet/mellanox/mlxsw/pci_hw.h

   1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3
   4 #ifndef _MLXSW_PCI_HW_H
   5 #define _MLXSW_PCI_HW_H
   6
   7 #include <linux/bitops.h>
   8
   9 #include "item.h"
  10
  11 #define MLXSW_PCI_BAR0_SIZE             (1024 * 1024) /* 1MB */
  12 #define MLXSW_PCI_PAGE_SIZE             4096
  13
  14 #define MLXSW_PCI_CIR_BASE                      0x71000
  15 #define MLXSW_PCI_CIR_IN_PARAM_HI               MLXSW_PCI_CIR_BASE
  16 #define MLXSW_PCI_CIR_IN_PARAM_LO               (MLXSW_PCI_CIR_BASE + 0x04)
  17 #define MLXSW_PCI_CIR_IN_MODIFIER               (MLXSW_PCI_CIR_BASE + 0x08)
  18 #define MLXSW_PCI_CIR_OUT_PARAM_HI              (MLXSW_PCI_CIR_BASE + 0x0C)
  19 #define MLXSW_PCI_CIR_OUT_PARAM_LO              (MLXSW_PCI_CIR_BASE + 0x10)
  20 #define MLXSW_PCI_CIR_TOKEN                     (MLXSW_PCI_CIR_BASE + 0x14)
  21 #define MLXSW_PCI_CIR_CTRL                      (MLXSW_PCI_CIR_BASE + 0x18)
  22 #define MLXSW_PCI_CIR_CTRL_GO_BIT               BIT(23)
  23 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT            BIT(22)
  24 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT     12
  25 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT         24
  26 #define MLXSW_PCI_CIR_TIMEOUT_MSECS             1000
  27
  28 #define MLXSW_PCI_SW_RESET                      0xF0010
  29 #define MLXSW_PCI_SW_RESET_RST_BIT              BIT(0)
  30 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS        5000
  31 #define MLXSW_PCI_SW_RESET_WAIT_MSECS           100
  32 #define MLXSW_PCI_FW_READY                      0xA1844
  33 #define MLXSW_PCI_FW_READY_MASK                 0xFFFF
  34 #define MLXSW_PCI_FW_READY_MAGIC                0x5E
  35
  36 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET           0x000
  37 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET           0x200
  38 #define MLXSW_PCI_DOORBELL_CQ_OFFSET            0x400
  39 #define MLXSW_PCI_DOORBELL_EQ_OFFSET            0x600
  40 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET        0x800
  41 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET        0xA00
  42
  43 #define MLXSW_PCI_DOORBELL(offset, type_offset, num)    \
  44         ((offset) + (type_offset) + (num) * 4)
  45
  46 #define MLXSW_PCI_CQS_MAX       96
  47 #define MLXSW_PCI_EQS_COUNT     2
  48 #define MLXSW_PCI_EQ_ASYNC_NUM  0
  49 #define MLXSW_PCI_EQ_COMP_NUM   1
  50
  51 #define MLXSW_PCI_AQ_PAGES      8
  52 #define MLXSW_PCI_AQ_SIZE       (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
  53 #define MLXSW_PCI_WQE_SIZE      32 /* 32 bytes per element */
  54 #define MLXSW_PCI_CQE01_SIZE    16 /* 16 bytes per element */
  55 #define MLXSW_PCI_CQE2_SIZE     32 /* 32 bytes per element */
  56 #define MLXSW_PCI_EQE_SIZE      16 /* 16 bytes per element */
  57 #define MLXSW_PCI_WQE_COUNT     (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
  58 #define MLXSW_PCI_CQE01_COUNT   (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE)
  59 #define MLXSW_PCI_CQE2_COUNT    (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE)
  60 #define MLXSW_PCI_EQE_COUNT     (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
  61 #define MLXSW_PCI_EQE_UPDATE_COUNT      0x80
  62
  63 #define MLXSW_PCI_WQE_SG_ENTRIES        3
  64 #define MLXSW_PCI_WQE_TYPE_ETHERNET     0xA
  65
  66 /* pci_wqe_c
  67  * If set it indicates that a completion should be reported upon
  68  * execution of this descriptor.
  69  */
  70 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
  71
  72 /* pci_wqe_lp
  73  * Local Processing, set if packet should be processed by the local
  74  * switch hardware:
  75  * For Ethernet EMAD (Direct Route and non Direct Route) -
  76  * must be set if packet destination is local device
  77  * For InfiniBand CTL - must be set if packet destination is local device
  78  * Otherwise it must be clear
  79  * Local Process packets must not exceed the size of 2K (including payload
  80  * and headers).
  81  */
  82 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
  83
  84 /* pci_wqe_type
  85  * Packet type.
  86  */
  87 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
  88
  89 /* pci_wqe_byte_count
  90  * Size of i-th scatter/gather entry, 0 if entry is unused.
  91  */
  92 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
  93
  94 /* pci_wqe_address
  95  * Physical address of i-th scatter/gather entry.
  96  * Gather Entries must be 2Byte aligned.
  97  */
  98 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
  99
 100 enum mlxsw_pci_cqe_v {
 101         MLXSW_PCI_CQE_V0,
 102         MLXSW_PCI_CQE_V1,
 103         MLXSW_PCI_CQE_V2,
 104 };
 105
 106 #define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2)                            \
 107 static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe) \
 108 {                                                                               \
 109         switch (v) {                                                            \
 110         default:                                                                \
 111         case MLXSW_PCI_CQE_V0:                                                  \
 112                 return mlxsw_pci_cqe##v0##_##name##_get(cqe);                   \
 113         case MLXSW_PCI_CQE_V1:                                                  \
 114                 return mlxsw_pci_cqe##v1##_##name##_get(cqe);                   \
 115         case MLXSW_PCI_CQE_V2:                                                  \
 116                 return mlxsw_pci_cqe##v2##_##name##_get(cqe);                   \
 117         }                                                                       \
 118 }                                                                               \
 119 static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v,           \
 120                                               char *cqe, u32 val)               \
 121 {                                                                               \
 122         switch (v) {                                                            \
 123         default:                                                                \
 124         case MLXSW_PCI_CQE_V0:                                                  \
 125                 mlxsw_pci_cqe##v0##_##name##_set(cqe, val);                     \
 126                 break;                                                          \
 127         case MLXSW_PCI_CQE_V1:                                                  \
 128                 mlxsw_pci_cqe##v1##_##name##_set(cqe, val);                     \
 129                 break;                                                          \
 130         case MLXSW_PCI_CQE_V2:                                                  \
 131                 mlxsw_pci_cqe##v2##_##name##_set(cqe, val);                     \
 132                 break;                                                          \
 133         }                                                                       \
 134 }
 135
 136 /* pci_cqe_lag
 137  * Packet arrives from a port which is a LAG
 138  */
 139 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
 140 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
 141 mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);
 142
 143 /* pci_cqe_system_port/lag_id
 144  * When lag=0: System port on which the packet was received
 145  * When lag=1:
 146  * bits [15:4] LAG ID on which the packet was received
 147  * bits [3:0] sub_port on which the packet was received
 148  */
 149 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
 150 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
 151 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
 152 mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);
 153 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
 154 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
 155 mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);
 156
 157 /* pci_cqe_wqe_counter
 158  * WQE count of the WQEs completed on the associated dqn
 159  */
 160 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
 161
 162 /* pci_cqe_byte_count
 163  * Byte count of received packets including additional two
 164  * Reserved Bytes that are append to the end of the frame.
 165  * Reserved for Send CQE.
 166  */
 167 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
 168
 169 /* pci_cqe_trap_id
 170  * Trap ID that captured the packet.
 171  */
 172 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9);
 173
 174 /* pci_cqe_crc
 175  * Length include CRC. Indicates the length field includes
 176  * the packet's CRC.
 177  */
 178 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
 179 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
 180 mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);
 181
 182 /* pci_cqe_e
 183  * CQE with Error.
 184  */
 185 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
 186 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
 187 mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);
 188
 189 /* pci_cqe_sr
 190  * 1 - Send Queue
 191  * 0 - Receive Queue
 192  */
 193 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
 194 MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
 195 mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);
 196
 197 /* pci_cqe_dqn
 198  * Descriptor Queue (DQ) Number.
 199  */
 200 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
 201 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
 202 mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
 203
 204 /* pci_cqe_owner
 205  * Ownership bit.
 206  */
 207 MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
 208 MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
 209 mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2);
 210
 211 /* pci_eqe_event_type
 212  * Event type.
 213  */
 214 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
 215 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP   0x00
 216 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD    0x0A
 217
 218 /* pci_eqe_event_sub_type
 219  * Event type.
 220  */
 221 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
 222
 223 /* pci_eqe_cqn
 224  * Completion Queue that triggered this EQE.
 225  */
 226 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
 227
 228 /* pci_eqe_owner
 229  * Ownership bit.
 230  */
 231 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
 232
 233 /* pci_eqe_cmd_token
 234  * Command completion event - token
 235  */
 236 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
 237
 238 /* pci_eqe_cmd_status
 239  * Command completion event - status
 240  */
 241 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
 242
 243 /* pci_eqe_cmd_out_param_h
 244  * Command completion event - output parameter - higher part
 245  */
 246 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
 247
 248 /* pci_eqe_cmd_out_param_l
 249  * Command completion event - output parameter - lower part
 250  */
 251 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);
 252
 253 #endif