2 * drivers/net/ethernet/mellanox/mlxsw/reg.h
3 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com>
5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
6 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
7 * Copyright (c) 2016 Yotam Gigi <yotamg@mellanox.com>
8 * Copyright (c) 2017 Petr Machata <petrm@mellanox.com>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the names of the copyright holders nor the names of its
19 * contributors may be used to endorse or promote products derived from
20 * this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
42 #include <linux/string.h>
43 #include <linux/bitops.h>
44 #include <linux/if_vlan.h>
49 struct mlxsw_reg_info
{
55 #define MLXSW_REG_DEFINE(_name, _id, _len) \
56 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
62 #define MLXSW_REG(type) (&mlxsw_reg_##type)
63 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
64 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
66 /* SGCR - Switch General Configuration Register
67 * --------------------------------------------
68 * This register is used for configuration of the switch capabilities.
70 #define MLXSW_REG_SGCR_ID 0x2000
71 #define MLXSW_REG_SGCR_LEN 0x10
73 MLXSW_REG_DEFINE(sgcr
, MLXSW_REG_SGCR_ID
, MLXSW_REG_SGCR_LEN
);
76 * Link Local Broadcast (Default=0)
77 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
78 * packets and ignore the IGMP snooping entries.
81 MLXSW_ITEM32(reg
, sgcr
, llb
, 0x04, 0, 1);
83 static inline void mlxsw_reg_sgcr_pack(char *payload
, bool llb
)
85 MLXSW_REG_ZERO(sgcr
, payload
);
86 mlxsw_reg_sgcr_llb_set(payload
, !!llb
);
89 /* SPAD - Switch Physical Address Register
90 * ---------------------------------------
91 * The SPAD register configures the switch physical MAC address.
93 #define MLXSW_REG_SPAD_ID 0x2002
94 #define MLXSW_REG_SPAD_LEN 0x10
96 MLXSW_REG_DEFINE(spad
, MLXSW_REG_SPAD_ID
, MLXSW_REG_SPAD_LEN
);
99 * Base MAC address for the switch partitions.
100 * Per switch partition MAC address is equal to:
104 MLXSW_ITEM_BUF(reg
, spad
, base_mac
, 0x02, 6);
106 /* SMID - Switch Multicast ID
107 * --------------------------
108 * The MID record maps from a MID (Multicast ID), which is a unique identifier
109 * of the multicast group within the stacking domain, into a list of local
110 * ports into which the packet is replicated.
112 #define MLXSW_REG_SMID_ID 0x2007
113 #define MLXSW_REG_SMID_LEN 0x240
115 MLXSW_REG_DEFINE(smid
, MLXSW_REG_SMID_ID
, MLXSW_REG_SMID_LEN
);
118 * Switch partition ID.
121 MLXSW_ITEM32(reg
, smid
, swid
, 0x00, 24, 8);
124 * Multicast identifier - global identifier that represents the multicast group
125 * across all devices.
128 MLXSW_ITEM32(reg
, smid
, mid
, 0x00, 0, 16);
131 * Local port memebership (1 bit per port).
134 MLXSW_ITEM_BIT_ARRAY(reg
, smid
, port
, 0x20, 0x20, 1);
136 /* reg_smid_port_mask
137 * Local port mask (1 bit per port).
140 MLXSW_ITEM_BIT_ARRAY(reg
, smid
, port_mask
, 0x220, 0x20, 1);
142 static inline void mlxsw_reg_smid_pack(char *payload
, u16 mid
,
145 MLXSW_REG_ZERO(smid
, payload
);
146 mlxsw_reg_smid_swid_set(payload
, 0);
147 mlxsw_reg_smid_mid_set(payload
, mid
);
148 mlxsw_reg_smid_port_set(payload
, port
, set
);
149 mlxsw_reg_smid_port_mask_set(payload
, port
, 1);
152 /* SSPR - Switch System Port Record Register
153 * -----------------------------------------
154 * Configures the system port to local port mapping.
156 #define MLXSW_REG_SSPR_ID 0x2008
157 #define MLXSW_REG_SSPR_LEN 0x8
159 MLXSW_REG_DEFINE(sspr
, MLXSW_REG_SSPR_ID
, MLXSW_REG_SSPR_LEN
);
162 * Master - if set, then the record describes the master system port.
163 * This is needed in case a local port is mapped into several system ports
164 * (for multipathing). That number will be reported as the source system
165 * port when packets are forwarded to the CPU. Only one master port is allowed
168 * Note: Must be set for Spectrum.
171 MLXSW_ITEM32(reg
, sspr
, m
, 0x00, 31, 1);
173 /* reg_sspr_local_port
178 MLXSW_ITEM32(reg
, sspr
, local_port
, 0x00, 16, 8);
181 * Virtual port within the physical port.
182 * Should be set to 0 when virtual ports are not enabled on the port.
186 MLXSW_ITEM32(reg
, sspr
, sub_port
, 0x00, 8, 8);
188 /* reg_sspr_system_port
189 * Unique identifier within the stacking domain that represents all the ports
190 * that are available in the system (external ports).
192 * Currently, only single-ASIC configurations are supported, so we default to
193 * 1:1 mapping between system ports and local ports.
196 MLXSW_ITEM32(reg
, sspr
, system_port
, 0x04, 0, 16);
198 static inline void mlxsw_reg_sspr_pack(char *payload
, u8 local_port
)
200 MLXSW_REG_ZERO(sspr
, payload
);
201 mlxsw_reg_sspr_m_set(payload
, 1);
202 mlxsw_reg_sspr_local_port_set(payload
, local_port
);
203 mlxsw_reg_sspr_sub_port_set(payload
, 0);
204 mlxsw_reg_sspr_system_port_set(payload
, local_port
);
207 /* SFDAT - Switch Filtering Database Aging Time
208 * --------------------------------------------
209 * Controls the Switch aging time. Aging time is able to be set per Switch
212 #define MLXSW_REG_SFDAT_ID 0x2009
213 #define MLXSW_REG_SFDAT_LEN 0x8
215 MLXSW_REG_DEFINE(sfdat
, MLXSW_REG_SFDAT_ID
, MLXSW_REG_SFDAT_LEN
);
218 * Switch partition ID.
221 MLXSW_ITEM32(reg
, sfdat
, swid
, 0x00, 24, 8);
223 /* reg_sfdat_age_time
224 * Aging time in seconds
226 * Max - 1,000,000 seconds
227 * Default is 300 seconds.
230 MLXSW_ITEM32(reg
, sfdat
, age_time
, 0x04, 0, 20);
232 static inline void mlxsw_reg_sfdat_pack(char *payload
, u32 age_time
)
234 MLXSW_REG_ZERO(sfdat
, payload
);
235 mlxsw_reg_sfdat_swid_set(payload
, 0);
236 mlxsw_reg_sfdat_age_time_set(payload
, age_time
);
239 /* SFD - Switch Filtering Database
240 * -------------------------------
241 * The following register defines the access to the filtering database.
242 * The register supports querying, adding, removing and modifying the database.
243 * The access is optimized for bulk updates in which case more than one
244 * FDB record is present in the same command.
246 #define MLXSW_REG_SFD_ID 0x200A
247 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
248 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
249 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
250 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
251 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
253 MLXSW_REG_DEFINE(sfd
, MLXSW_REG_SFD_ID
, MLXSW_REG_SFD_LEN
);
256 * Switch partition ID for queries. Reserved on Write.
259 MLXSW_ITEM32(reg
, sfd
, swid
, 0x00, 24, 8);
261 enum mlxsw_reg_sfd_op
{
262 /* Dump entire FDB a (process according to record_locator) */
263 MLXSW_REG_SFD_OP_QUERY_DUMP
= 0,
264 /* Query records by {MAC, VID/FID} value */
265 MLXSW_REG_SFD_OP_QUERY_QUERY
= 1,
266 /* Query and clear activity. Query records by {MAC, VID/FID} value */
267 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY
= 2,
268 /* Test. Response indicates if each of the records could be
271 MLXSW_REG_SFD_OP_WRITE_TEST
= 0,
272 /* Add/modify. Aged-out records cannot be added. This command removes
273 * the learning notification of the {MAC, VID/FID}. Response includes
274 * the entries that were added to the FDB.
276 MLXSW_REG_SFD_OP_WRITE_EDIT
= 1,
277 /* Remove record by {MAC, VID/FID}. This command also removes
278 * the learning notification and aged-out notifications
279 * of the {MAC, VID/FID}. The response provides current (pre-removal)
280 * entries as non-aged-out.
282 MLXSW_REG_SFD_OP_WRITE_REMOVE
= 2,
283 /* Remove learned notification by {MAC, VID/FID}. The response provides
284 * the removed learning notification.
286 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION
= 2,
293 MLXSW_ITEM32(reg
, sfd
, op
, 0x04, 30, 2);
295 /* reg_sfd_record_locator
296 * Used for querying the FDB. Use record_locator=0 to initiate the
297 * query. When a record is returned, a new record_locator is
298 * returned to be used in the subsequent query.
299 * Reserved for database update.
302 MLXSW_ITEM32(reg
, sfd
, record_locator
, 0x04, 0, 30);
305 * Request: Number of records to read/add/modify/remove
306 * Response: Number of records read/added/replaced/removed
307 * See above description for more details.
311 MLXSW_ITEM32(reg
, sfd
, num_rec
, 0x08, 0, 8);
313 static inline void mlxsw_reg_sfd_pack(char *payload
, enum mlxsw_reg_sfd_op op
,
316 MLXSW_REG_ZERO(sfd
, payload
);
317 mlxsw_reg_sfd_op_set(payload
, op
);
318 mlxsw_reg_sfd_record_locator_set(payload
, record_locator
);
322 * Switch partition ID.
325 MLXSW_ITEM32_INDEXED(reg
, sfd
, rec_swid
, MLXSW_REG_SFD_BASE_LEN
, 24, 8,
326 MLXSW_REG_SFD_REC_LEN
, 0x00, false);
328 enum mlxsw_reg_sfd_rec_type
{
329 MLXSW_REG_SFD_REC_TYPE_UNICAST
= 0x0,
330 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG
= 0x1,
331 MLXSW_REG_SFD_REC_TYPE_MULTICAST
= 0x2,
338 MLXSW_ITEM32_INDEXED(reg
, sfd
, rec_type
, MLXSW_REG_SFD_BASE_LEN
, 20, 4,
339 MLXSW_REG_SFD_REC_LEN
, 0x00, false);
341 enum mlxsw_reg_sfd_rec_policy
{
342 /* Replacement disabled, aging disabled. */
343 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY
= 0,
344 /* (mlag remote): Replacement enabled, aging disabled,
345 * learning notification enabled on this port.
347 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG
= 1,
348 /* (ingress device): Replacement enabled, aging enabled. */
349 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS
= 3,
352 /* reg_sfd_rec_policy
356 MLXSW_ITEM32_INDEXED(reg
, sfd
, rec_policy
, MLXSW_REG_SFD_BASE_LEN
, 18, 2,
357 MLXSW_REG_SFD_REC_LEN
, 0x00, false);
360 * Activity. Set for new static entries. Set for static entries if a frame SMAC
361 * lookup hits on the entry.
362 * To clear the a bit, use "query and clear activity" op.
365 MLXSW_ITEM32_INDEXED(reg
, sfd
, rec_a
, MLXSW_REG_SFD_BASE_LEN
, 16, 1,
366 MLXSW_REG_SFD_REC_LEN
, 0x00, false);
372 MLXSW_ITEM_BUF_INDEXED(reg
, sfd
, rec_mac
, MLXSW_REG_SFD_BASE_LEN
, 6,
373 MLXSW_REG_SFD_REC_LEN
, 0x02);
375 enum mlxsw_reg_sfd_rec_action
{
377 MLXSW_REG_SFD_REC_ACTION_NOP
= 0,
378 /* forward and trap, trap_id is FDB_TRAP */
379 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU
= 1,
380 /* trap and do not forward, trap_id is FDB_TRAP */
381 MLXSW_REG_SFD_REC_ACTION_TRAP
= 2,
382 /* forward to IP router */
383 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER
= 3,
384 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR
= 15,
387 /* reg_sfd_rec_action
388 * Action to apply on the packet.
389 * Note: Dynamic entries can only be configured with NOP action.
392 MLXSW_ITEM32_INDEXED(reg
, sfd
, rec_action
, MLXSW_REG_SFD_BASE_LEN
, 28, 4,
393 MLXSW_REG_SFD_REC_LEN
, 0x0C, false);
395 /* reg_sfd_uc_sub_port
396 * VEPA channel on local port.
397 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
398 * VEPA is not enabled.
401 MLXSW_ITEM32_INDEXED(reg
, sfd
, uc_sub_port
, MLXSW_REG_SFD_BASE_LEN
, 16, 8,
402 MLXSW_REG_SFD_REC_LEN
, 0x08, false);
404 /* reg_sfd_uc_fid_vid
405 * Filtering ID or VLAN ID
406 * For SwitchX and SwitchX-2:
407 * - Dynamic entries (policy 2,3) use FID
408 * - Static entries (policy 0) use VID
409 * - When independent learning is configured, VID=FID
410 * For Spectrum: use FID for both Dynamic and Static entries.
411 * VID should not be used.
414 MLXSW_ITEM32_INDEXED(reg
, sfd
, uc_fid_vid
, MLXSW_REG_SFD_BASE_LEN
, 0, 16,
415 MLXSW_REG_SFD_REC_LEN
, 0x08, false);
417 /* reg_sfd_uc_system_port
418 * Unique port identifier for the final destination of the packet.
421 MLXSW_ITEM32_INDEXED(reg
, sfd
, uc_system_port
, MLXSW_REG_SFD_BASE_LEN
, 0, 16,
422 MLXSW_REG_SFD_REC_LEN
, 0x0C, false);
424 static inline void mlxsw_reg_sfd_rec_pack(char *payload
, int rec_index
,
425 enum mlxsw_reg_sfd_rec_type rec_type
,
427 enum mlxsw_reg_sfd_rec_action action
)
429 u8 num_rec
= mlxsw_reg_sfd_num_rec_get(payload
);
431 if (rec_index
>= num_rec
)
432 mlxsw_reg_sfd_num_rec_set(payload
, rec_index
+ 1);
433 mlxsw_reg_sfd_rec_swid_set(payload
, rec_index
, 0);
434 mlxsw_reg_sfd_rec_type_set(payload
, rec_index
, rec_type
);
435 mlxsw_reg_sfd_rec_mac_memcpy_to(payload
, rec_index
, mac
);
436 mlxsw_reg_sfd_rec_action_set(payload
, rec_index
, action
);
439 static inline void mlxsw_reg_sfd_uc_pack(char *payload
, int rec_index
,
440 enum mlxsw_reg_sfd_rec_policy policy
,
441 const char *mac
, u16 fid_vid
,
442 enum mlxsw_reg_sfd_rec_action action
,
445 mlxsw_reg_sfd_rec_pack(payload
, rec_index
,
446 MLXSW_REG_SFD_REC_TYPE_UNICAST
, mac
, action
);
447 mlxsw_reg_sfd_rec_policy_set(payload
, rec_index
, policy
);
448 mlxsw_reg_sfd_uc_sub_port_set(payload
, rec_index
, 0);
449 mlxsw_reg_sfd_uc_fid_vid_set(payload
, rec_index
, fid_vid
);
450 mlxsw_reg_sfd_uc_system_port_set(payload
, rec_index
, local_port
);
453 static inline void mlxsw_reg_sfd_uc_unpack(char *payload
, int rec_index
,
454 char *mac
, u16
*p_fid_vid
,
457 mlxsw_reg_sfd_rec_mac_memcpy_from(payload
, rec_index
, mac
);
458 *p_fid_vid
= mlxsw_reg_sfd_uc_fid_vid_get(payload
, rec_index
);
459 *p_local_port
= mlxsw_reg_sfd_uc_system_port_get(payload
, rec_index
);
462 /* reg_sfd_uc_lag_sub_port
464 * Must be 0 if multichannel VEPA is not enabled.
467 MLXSW_ITEM32_INDEXED(reg
, sfd
, uc_lag_sub_port
, MLXSW_REG_SFD_BASE_LEN
, 16, 8,
468 MLXSW_REG_SFD_REC_LEN
, 0x08, false);
470 /* reg_sfd_uc_lag_fid_vid
471 * Filtering ID or VLAN ID
472 * For SwitchX and SwitchX-2:
473 * - Dynamic entries (policy 2,3) use FID
474 * - Static entries (policy 0) use VID
475 * - When independent learning is configured, VID=FID
476 * For Spectrum: use FID for both Dynamic and Static entries.
477 * VID should not be used.
480 MLXSW_ITEM32_INDEXED(reg
, sfd
, uc_lag_fid_vid
, MLXSW_REG_SFD_BASE_LEN
, 0, 16,
481 MLXSW_REG_SFD_REC_LEN
, 0x08, false);
483 /* reg_sfd_uc_lag_lag_vid
484 * Indicates VID in case of vFIDs. Reserved for FIDs.
487 MLXSW_ITEM32_INDEXED(reg
, sfd
, uc_lag_lag_vid
, MLXSW_REG_SFD_BASE_LEN
, 16, 12,
488 MLXSW_REG_SFD_REC_LEN
, 0x0C, false);
490 /* reg_sfd_uc_lag_lag_id
491 * LAG Identifier - pointer into the LAG descriptor table.
494 MLXSW_ITEM32_INDEXED(reg
, sfd
, uc_lag_lag_id
, MLXSW_REG_SFD_BASE_LEN
, 0, 10,
495 MLXSW_REG_SFD_REC_LEN
, 0x0C, false);
498 mlxsw_reg_sfd_uc_lag_pack(char *payload
, int rec_index
,
499 enum mlxsw_reg_sfd_rec_policy policy
,
500 const char *mac
, u16 fid_vid
,
501 enum mlxsw_reg_sfd_rec_action action
, u16 lag_vid
,
504 mlxsw_reg_sfd_rec_pack(payload
, rec_index
,
505 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG
,
507 mlxsw_reg_sfd_rec_policy_set(payload
, rec_index
, policy
);
508 mlxsw_reg_sfd_uc_lag_sub_port_set(payload
, rec_index
, 0);
509 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload
, rec_index
, fid_vid
);
510 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload
, rec_index
, lag_vid
);
511 mlxsw_reg_sfd_uc_lag_lag_id_set(payload
, rec_index
, lag_id
);
514 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload
, int rec_index
,
515 char *mac
, u16
*p_vid
,
518 mlxsw_reg_sfd_rec_mac_memcpy_from(payload
, rec_index
, mac
);
519 *p_vid
= mlxsw_reg_sfd_uc_lag_fid_vid_get(payload
, rec_index
);
520 *p_lag_id
= mlxsw_reg_sfd_uc_lag_lag_id_get(payload
, rec_index
);
525 * Multicast port group index - index into the port group table.
526 * Value 0x1FFF indicates the pgi should point to the MID entry.
527 * For Spectrum this value must be set to 0x1FFF
530 MLXSW_ITEM32_INDEXED(reg
, sfd
, mc_pgi
, MLXSW_REG_SFD_BASE_LEN
, 16, 13,
531 MLXSW_REG_SFD_REC_LEN
, 0x08, false);
533 /* reg_sfd_mc_fid_vid
535 * Filtering ID or VLAN ID
538 MLXSW_ITEM32_INDEXED(reg
, sfd
, mc_fid_vid
, MLXSW_REG_SFD_BASE_LEN
, 0, 16,
539 MLXSW_REG_SFD_REC_LEN
, 0x08, false);
543 * Multicast identifier - global identifier that represents the multicast
544 * group across all devices.
547 MLXSW_ITEM32_INDEXED(reg
, sfd
, mc_mid
, MLXSW_REG_SFD_BASE_LEN
, 0, 16,
548 MLXSW_REG_SFD_REC_LEN
, 0x0C, false);
551 mlxsw_reg_sfd_mc_pack(char *payload
, int rec_index
,
552 const char *mac
, u16 fid_vid
,
553 enum mlxsw_reg_sfd_rec_action action
, u16 mid
)
555 mlxsw_reg_sfd_rec_pack(payload
, rec_index
,
556 MLXSW_REG_SFD_REC_TYPE_MULTICAST
, mac
, action
);
557 mlxsw_reg_sfd_mc_pgi_set(payload
, rec_index
, 0x1FFF);
558 mlxsw_reg_sfd_mc_fid_vid_set(payload
, rec_index
, fid_vid
);
559 mlxsw_reg_sfd_mc_mid_set(payload
, rec_index
, mid
);
562 /* SFN - Switch FDB Notification Register
563 * -------------------------------------------
564 * The switch provides notifications on newly learned FDB entries and
565 * aged out entries. The notifications can be polled by software.
567 #define MLXSW_REG_SFN_ID 0x200B
568 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
569 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
570 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
571 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
572 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
574 MLXSW_REG_DEFINE(sfn
, MLXSW_REG_SFN_ID
, MLXSW_REG_SFN_LEN
);
577 * Switch partition ID.
580 MLXSW_ITEM32(reg
, sfn
, swid
, 0x00, 24, 8);
583 * Forces the current session to end.
586 MLXSW_ITEM32(reg
, sfn
, end
, 0x04, 20, 1);
589 * Request: Number of learned notifications and aged-out notification
591 * Response: Number of notification records returned (must be smaller
592 * than or equal to the value requested)
596 MLXSW_ITEM32(reg
, sfn
, num_rec
, 0x04, 0, 8);
598 static inline void mlxsw_reg_sfn_pack(char *payload
)
600 MLXSW_REG_ZERO(sfn
, payload
);
601 mlxsw_reg_sfn_swid_set(payload
, 0);
602 mlxsw_reg_sfn_end_set(payload
, 1);
603 mlxsw_reg_sfn_num_rec_set(payload
, MLXSW_REG_SFN_REC_MAX_COUNT
);
607 * Switch partition ID.
610 MLXSW_ITEM32_INDEXED(reg
, sfn
, rec_swid
, MLXSW_REG_SFN_BASE_LEN
, 24, 8,
611 MLXSW_REG_SFN_REC_LEN
, 0x00, false);
613 enum mlxsw_reg_sfn_rec_type
{
614 /* MAC addresses learned on a regular port. */
615 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC
= 0x5,
616 /* MAC addresses learned on a LAG port. */
617 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG
= 0x6,
618 /* Aged-out MAC address on a regular port. */
619 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC
= 0x7,
620 /* Aged-out MAC address on a LAG port. */
621 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG
= 0x8,
625 * Notification record type.
628 MLXSW_ITEM32_INDEXED(reg
, sfn
, rec_type
, MLXSW_REG_SFN_BASE_LEN
, 20, 4,
629 MLXSW_REG_SFN_REC_LEN
, 0x00, false);
635 MLXSW_ITEM_BUF_INDEXED(reg
, sfn
, rec_mac
, MLXSW_REG_SFN_BASE_LEN
, 6,
636 MLXSW_REG_SFN_REC_LEN
, 0x02);
638 /* reg_sfn_mac_sub_port
639 * VEPA channel on the local port.
640 * 0 if multichannel VEPA is not enabled.
643 MLXSW_ITEM32_INDEXED(reg
, sfn
, mac_sub_port
, MLXSW_REG_SFN_BASE_LEN
, 16, 8,
644 MLXSW_REG_SFN_REC_LEN
, 0x08, false);
647 * Filtering identifier.
650 MLXSW_ITEM32_INDEXED(reg
, sfn
, mac_fid
, MLXSW_REG_SFN_BASE_LEN
, 0, 16,
651 MLXSW_REG_SFN_REC_LEN
, 0x08, false);
653 /* reg_sfn_mac_system_port
654 * Unique port identifier for the final destination of the packet.
657 MLXSW_ITEM32_INDEXED(reg
, sfn
, mac_system_port
, MLXSW_REG_SFN_BASE_LEN
, 0, 16,
658 MLXSW_REG_SFN_REC_LEN
, 0x0C, false);
660 static inline void mlxsw_reg_sfn_mac_unpack(char *payload
, int rec_index
,
661 char *mac
, u16
*p_vid
,
664 mlxsw_reg_sfn_rec_mac_memcpy_from(payload
, rec_index
, mac
);
665 *p_vid
= mlxsw_reg_sfn_mac_fid_get(payload
, rec_index
);
666 *p_local_port
= mlxsw_reg_sfn_mac_system_port_get(payload
, rec_index
);
669 /* reg_sfn_mac_lag_lag_id
670 * LAG ID (pointer into the LAG descriptor table).
673 MLXSW_ITEM32_INDEXED(reg
, sfn
, mac_lag_lag_id
, MLXSW_REG_SFN_BASE_LEN
, 0, 10,
674 MLXSW_REG_SFN_REC_LEN
, 0x0C, false);
676 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload
, int rec_index
,
677 char *mac
, u16
*p_vid
,
680 mlxsw_reg_sfn_rec_mac_memcpy_from(payload
, rec_index
, mac
);
681 *p_vid
= mlxsw_reg_sfn_mac_fid_get(payload
, rec_index
);
682 *p_lag_id
= mlxsw_reg_sfn_mac_lag_lag_id_get(payload
, rec_index
);
685 /* SPMS - Switch Port MSTP/RSTP State Register
686 * -------------------------------------------
687 * Configures the spanning tree state of a physical port.
689 #define MLXSW_REG_SPMS_ID 0x200D
690 #define MLXSW_REG_SPMS_LEN 0x404
692 MLXSW_REG_DEFINE(spms
, MLXSW_REG_SPMS_ID
, MLXSW_REG_SPMS_LEN
);
694 /* reg_spms_local_port
698 MLXSW_ITEM32(reg
, spms
, local_port
, 0x00, 16, 8);
700 enum mlxsw_reg_spms_state
{
701 MLXSW_REG_SPMS_STATE_NO_CHANGE
,
702 MLXSW_REG_SPMS_STATE_DISCARDING
,
703 MLXSW_REG_SPMS_STATE_LEARNING
,
704 MLXSW_REG_SPMS_STATE_FORWARDING
,
708 * Spanning tree state of each VLAN ID (VID) of the local port.
709 * 0 - Do not change spanning tree state (used only when writing).
710 * 1 - Discarding. No learning or forwarding to/from this port (default).
711 * 2 - Learning. Port is learning, but not forwarding.
712 * 3 - Forwarding. Port is learning and forwarding.
715 MLXSW_ITEM_BIT_ARRAY(reg
, spms
, state
, 0x04, 0x400, 2);
717 static inline void mlxsw_reg_spms_pack(char *payload
, u8 local_port
)
719 MLXSW_REG_ZERO(spms
, payload
);
720 mlxsw_reg_spms_local_port_set(payload
, local_port
);
723 static inline void mlxsw_reg_spms_vid_pack(char *payload
, u16 vid
,
724 enum mlxsw_reg_spms_state state
)
726 mlxsw_reg_spms_state_set(payload
, vid
, state
);
729 /* SPVID - Switch Port VID
730 * -----------------------
731 * The switch port VID configures the default VID for a port.
733 #define MLXSW_REG_SPVID_ID 0x200E
734 #define MLXSW_REG_SPVID_LEN 0x08
736 MLXSW_REG_DEFINE(spvid
, MLXSW_REG_SPVID_ID
, MLXSW_REG_SPVID_LEN
);
738 /* reg_spvid_local_port
742 MLXSW_ITEM32(reg
, spvid
, local_port
, 0x00, 16, 8);
744 /* reg_spvid_sub_port
745 * Virtual port within the physical port.
746 * Should be set to 0 when virtual ports are not enabled on the port.
749 MLXSW_ITEM32(reg
, spvid
, sub_port
, 0x00, 8, 8);
755 MLXSW_ITEM32(reg
, spvid
, pvid
, 0x04, 0, 12);
757 static inline void mlxsw_reg_spvid_pack(char *payload
, u8 local_port
, u16 pvid
)
759 MLXSW_REG_ZERO(spvid
, payload
);
760 mlxsw_reg_spvid_local_port_set(payload
, local_port
);
761 mlxsw_reg_spvid_pvid_set(payload
, pvid
);
764 /* SPVM - Switch Port VLAN Membership
765 * ----------------------------------
766 * The Switch Port VLAN Membership register configures the VLAN membership
767 * of a port in a VLAN denoted by VID. VLAN membership is managed per
768 * virtual port. The register can be used to add and remove VID(s) from a port.
770 #define MLXSW_REG_SPVM_ID 0x200F
771 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
772 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
773 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255
774 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
775 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
777 MLXSW_REG_DEFINE(spvm
, MLXSW_REG_SPVM_ID
, MLXSW_REG_SPVM_LEN
);
780 * Priority tagged. If this bit is set, packets forwarded to the port with
781 * untagged VLAN membership (u bit is set) will be tagged with priority tag
785 MLXSW_ITEM32(reg
, spvm
, pt
, 0x00, 31, 1);
788 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
789 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
792 MLXSW_ITEM32(reg
, spvm
, pte
, 0x00, 30, 1);
794 /* reg_spvm_local_port
798 MLXSW_ITEM32(reg
, spvm
, local_port
, 0x00, 16, 8);
801 * Virtual port within the physical port.
802 * Should be set to 0 when virtual ports are not enabled on the port.
805 MLXSW_ITEM32(reg
, spvm
, sub_port
, 0x00, 8, 8);
808 * Number of records to update. Each record contains: i, e, u, vid.
811 MLXSW_ITEM32(reg
, spvm
, num_rec
, 0x00, 0, 8);
814 * Ingress membership in VLAN ID.
817 MLXSW_ITEM32_INDEXED(reg
, spvm
, rec_i
,
818 MLXSW_REG_SPVM_BASE_LEN
, 14, 1,
819 MLXSW_REG_SPVM_REC_LEN
, 0, false);
822 * Egress membership in VLAN ID.
825 MLXSW_ITEM32_INDEXED(reg
, spvm
, rec_e
,
826 MLXSW_REG_SPVM_BASE_LEN
, 13, 1,
827 MLXSW_REG_SPVM_REC_LEN
, 0, false);
830 * Untagged - port is an untagged member - egress transmission uses untagged
834 MLXSW_ITEM32_INDEXED(reg
, spvm
, rec_u
,
835 MLXSW_REG_SPVM_BASE_LEN
, 12, 1,
836 MLXSW_REG_SPVM_REC_LEN
, 0, false);
839 * Egress membership in VLAN ID.
842 MLXSW_ITEM32_INDEXED(reg
, spvm
, rec_vid
,
843 MLXSW_REG_SPVM_BASE_LEN
, 0, 12,
844 MLXSW_REG_SPVM_REC_LEN
, 0, false);
846 static inline void mlxsw_reg_spvm_pack(char *payload
, u8 local_port
,
847 u16 vid_begin
, u16 vid_end
,
848 bool is_member
, bool untagged
)
850 int size
= vid_end
- vid_begin
+ 1;
853 MLXSW_REG_ZERO(spvm
, payload
);
854 mlxsw_reg_spvm_local_port_set(payload
, local_port
);
855 mlxsw_reg_spvm_num_rec_set(payload
, size
);
857 for (i
= 0; i
< size
; i
++) {
858 mlxsw_reg_spvm_rec_i_set(payload
, i
, is_member
);
859 mlxsw_reg_spvm_rec_e_set(payload
, i
, is_member
);
860 mlxsw_reg_spvm_rec_u_set(payload
, i
, untagged
);
861 mlxsw_reg_spvm_rec_vid_set(payload
, i
, vid_begin
+ i
);
865 /* SPAFT - Switch Port Acceptable Frame Types
866 * ------------------------------------------
867 * The Switch Port Acceptable Frame Types register configures the frame
868 * admittance of the port.
870 #define MLXSW_REG_SPAFT_ID 0x2010
871 #define MLXSW_REG_SPAFT_LEN 0x08
873 MLXSW_REG_DEFINE(spaft
, MLXSW_REG_SPAFT_ID
, MLXSW_REG_SPAFT_LEN
);
875 /* reg_spaft_local_port
879 * Note: CPU port is not supported (all tag types are allowed).
881 MLXSW_ITEM32(reg
, spaft
, local_port
, 0x00, 16, 8);
883 /* reg_spaft_sub_port
884 * Virtual port within the physical port.
885 * Should be set to 0 when virtual ports are not enabled on the port.
888 MLXSW_ITEM32(reg
, spaft
, sub_port
, 0x00, 8, 8);
890 /* reg_spaft_allow_untagged
891 * When set, untagged frames on the ingress are allowed (default).
894 MLXSW_ITEM32(reg
, spaft
, allow_untagged
, 0x04, 31, 1);
896 /* reg_spaft_allow_prio_tagged
897 * When set, priority tagged frames on the ingress are allowed (default).
900 MLXSW_ITEM32(reg
, spaft
, allow_prio_tagged
, 0x04, 30, 1);
902 /* reg_spaft_allow_tagged
903 * When set, tagged frames on the ingress are allowed (default).
906 MLXSW_ITEM32(reg
, spaft
, allow_tagged
, 0x04, 29, 1);
908 static inline void mlxsw_reg_spaft_pack(char *payload
, u8 local_port
,
911 MLXSW_REG_ZERO(spaft
, payload
);
912 mlxsw_reg_spaft_local_port_set(payload
, local_port
);
913 mlxsw_reg_spaft_allow_untagged_set(payload
, allow_untagged
);
914 mlxsw_reg_spaft_allow_prio_tagged_set(payload
, true);
915 mlxsw_reg_spaft_allow_tagged_set(payload
, true);
918 /* SFGC - Switch Flooding Group Configuration
919 * ------------------------------------------
920 * The following register controls the association of flooding tables and MIDs
921 * to packet types used for flooding.
923 #define MLXSW_REG_SFGC_ID 0x2011
924 #define MLXSW_REG_SFGC_LEN 0x10
926 MLXSW_REG_DEFINE(sfgc
, MLXSW_REG_SFGC_ID
, MLXSW_REG_SFGC_LEN
);
928 enum mlxsw_reg_sfgc_type
{
929 MLXSW_REG_SFGC_TYPE_BROADCAST
,
930 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST
,
931 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4
,
932 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6
,
933 MLXSW_REG_SFGC_TYPE_RESERVED
,
934 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP
,
935 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL
,
936 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST
,
937 MLXSW_REG_SFGC_TYPE_MAX
,
941 * The traffic type to reach the flooding table.
944 MLXSW_ITEM32(reg
, sfgc
, type
, 0x00, 0, 4);
946 enum mlxsw_reg_sfgc_bridge_type
{
947 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID
= 0,
948 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID
= 1,
951 /* reg_sfgc_bridge_type
954 * Note: SwitchX-2 only supports 802.1Q mode.
956 MLXSW_ITEM32(reg
, sfgc
, bridge_type
, 0x04, 24, 3);
958 enum mlxsw_flood_table_type
{
959 MLXSW_REG_SFGC_TABLE_TYPE_VID
= 1,
960 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE
= 2,
961 MLXSW_REG_SFGC_TABLE_TYPE_ANY
= 0,
962 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET
= 3,
963 MLXSW_REG_SFGC_TABLE_TYPE_FID
= 4,
966 /* reg_sfgc_table_type
967 * See mlxsw_flood_table_type
970 * Note: FID offset and FID types are not supported in SwitchX-2.
972 MLXSW_ITEM32(reg
, sfgc
, table_type
, 0x04, 16, 3);
974 /* reg_sfgc_flood_table
975 * Flooding table index to associate with the specific type on the specific
979 MLXSW_ITEM32(reg
, sfgc
, flood_table
, 0x04, 0, 6);
982 * The multicast ID for the swid. Not supported for Spectrum
985 MLXSW_ITEM32(reg
, sfgc
, mid
, 0x08, 0, 16);
987 /* reg_sfgc_counter_set_type
988 * Counter Set Type for flow counters.
991 MLXSW_ITEM32(reg
, sfgc
, counter_set_type
, 0x0C, 24, 8);
993 /* reg_sfgc_counter_index
994 * Counter Index for flow counters.
997 MLXSW_ITEM32(reg
, sfgc
, counter_index
, 0x0C, 0, 24);
1000 mlxsw_reg_sfgc_pack(char *payload
, enum mlxsw_reg_sfgc_type type
,
1001 enum mlxsw_reg_sfgc_bridge_type bridge_type
,
1002 enum mlxsw_flood_table_type table_type
,
1003 unsigned int flood_table
)
1005 MLXSW_REG_ZERO(sfgc
, payload
);
1006 mlxsw_reg_sfgc_type_set(payload
, type
);
1007 mlxsw_reg_sfgc_bridge_type_set(payload
, bridge_type
);
1008 mlxsw_reg_sfgc_table_type_set(payload
, table_type
);
1009 mlxsw_reg_sfgc_flood_table_set(payload
, flood_table
);
1010 mlxsw_reg_sfgc_mid_set(payload
, MLXSW_PORT_MID
);
1013 /* SFTR - Switch Flooding Table Register
1014 * -------------------------------------
1015 * The switch flooding table is used for flooding packet replication. The table
1016 * defines a bit mask of ports for packet replication.
1018 #define MLXSW_REG_SFTR_ID 0x2012
1019 #define MLXSW_REG_SFTR_LEN 0x420
1021 MLXSW_REG_DEFINE(sftr
, MLXSW_REG_SFTR_ID
, MLXSW_REG_SFTR_LEN
);
1024 * Switch partition ID with which to associate the port.
1027 MLXSW_ITEM32(reg
, sftr
, swid
, 0x00, 24, 8);
1029 /* reg_sftr_flood_table
1030 * Flooding table index to associate with the specific type on the specific
1034 MLXSW_ITEM32(reg
, sftr
, flood_table
, 0x00, 16, 6);
1037 * Index. Used as an index into the Flooding Table in case the table is
1038 * configured to use VID / FID or FID Offset.
1041 MLXSW_ITEM32(reg
, sftr
, index
, 0x00, 0, 16);
1043 /* reg_sftr_table_type
1044 * See mlxsw_flood_table_type
1047 MLXSW_ITEM32(reg
, sftr
, table_type
, 0x04, 16, 3);
1050 * Range of entries to update
1053 MLXSW_ITEM32(reg
, sftr
, range
, 0x04, 0, 16);
1056 * Local port membership (1 bit per port).
1059 MLXSW_ITEM_BIT_ARRAY(reg
, sftr
, port
, 0x20, 0x20, 1);
1061 /* reg_sftr_cpu_port_mask
1062 * CPU port mask (1 bit per port).
1065 MLXSW_ITEM_BIT_ARRAY(reg
, sftr
, port_mask
, 0x220, 0x20, 1);
1067 static inline void mlxsw_reg_sftr_pack(char *payload
,
1068 unsigned int flood_table
,
1070 enum mlxsw_flood_table_type table_type
,
1071 unsigned int range
, u8 port
, bool set
)
1073 MLXSW_REG_ZERO(sftr
, payload
);
1074 mlxsw_reg_sftr_swid_set(payload
, 0);
1075 mlxsw_reg_sftr_flood_table_set(payload
, flood_table
);
1076 mlxsw_reg_sftr_index_set(payload
, index
);
1077 mlxsw_reg_sftr_table_type_set(payload
, table_type
);
1078 mlxsw_reg_sftr_range_set(payload
, range
);
1079 mlxsw_reg_sftr_port_set(payload
, port
, set
);
1080 mlxsw_reg_sftr_port_mask_set(payload
, port
, 1);
1083 /* SFDF - Switch Filtering DB Flush
1084 * --------------------------------
1085 * The switch filtering DB flush register is used to flush the FDB.
1086 * Note that FDB notifications are flushed as well.
1088 #define MLXSW_REG_SFDF_ID 0x2013
1089 #define MLXSW_REG_SFDF_LEN 0x14
1091 MLXSW_REG_DEFINE(sfdf
, MLXSW_REG_SFDF_ID
, MLXSW_REG_SFDF_LEN
);
1094 * Switch partition ID.
1097 MLXSW_ITEM32(reg
, sfdf
, swid
, 0x00, 24, 8);
1099 enum mlxsw_reg_sfdf_flush_type
{
1100 MLXSW_REG_SFDF_FLUSH_PER_SWID
,
1101 MLXSW_REG_SFDF_FLUSH_PER_FID
,
1102 MLXSW_REG_SFDF_FLUSH_PER_PORT
,
1103 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID
,
1104 MLXSW_REG_SFDF_FLUSH_PER_LAG
,
1105 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID
,
1108 /* reg_sfdf_flush_type
1110 * 0 - All SWID dynamic entries are flushed.
1111 * 1 - All FID dynamic entries are flushed.
1112 * 2 - All dynamic entries pointing to port are flushed.
1113 * 3 - All FID dynamic entries pointing to port are flushed.
1114 * 4 - All dynamic entries pointing to LAG are flushed.
1115 * 5 - All FID dynamic entries pointing to LAG are flushed.
1118 MLXSW_ITEM32(reg
, sfdf
, flush_type
, 0x04, 28, 4);
1120 /* reg_sfdf_flush_static
1122 * 0 - Flush only dynamic entries.
1123 * 1 - Flush both dynamic and static entries.
1126 MLXSW_ITEM32(reg
, sfdf
, flush_static
, 0x04, 24, 1);
1128 static inline void mlxsw_reg_sfdf_pack(char *payload
,
1129 enum mlxsw_reg_sfdf_flush_type type
)
1131 MLXSW_REG_ZERO(sfdf
, payload
);
1132 mlxsw_reg_sfdf_flush_type_set(payload
, type
);
1133 mlxsw_reg_sfdf_flush_static_set(payload
, true);
1140 MLXSW_ITEM32(reg
, sfdf
, fid
, 0x0C, 0, 16);
1142 /* reg_sfdf_system_port
1146 MLXSW_ITEM32(reg
, sfdf
, system_port
, 0x0C, 0, 16);
1148 /* reg_sfdf_port_fid_system_port
1149 * Port to flush, pointed to by FID.
1152 MLXSW_ITEM32(reg
, sfdf
, port_fid_system_port
, 0x08, 0, 16);
1158 MLXSW_ITEM32(reg
, sfdf
, lag_id
, 0x0C, 0, 10);
1160 /* reg_sfdf_lag_fid_lag_id
1161 * LAG ID to flush, pointed to by FID.
1164 MLXSW_ITEM32(reg
, sfdf
, lag_fid_lag_id
, 0x08, 0, 10);
1166 /* SLDR - Switch LAG Descriptor Register
1167 * -----------------------------------------
1168 * The switch LAG descriptor register is populated by LAG descriptors.
1169 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1172 #define MLXSW_REG_SLDR_ID 0x2014
1173 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1175 MLXSW_REG_DEFINE(sldr
, MLXSW_REG_SLDR_ID
, MLXSW_REG_SLDR_LEN
);
1177 enum mlxsw_reg_sldr_op
{
1178 /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1179 MLXSW_REG_SLDR_OP_LAG_CREATE
,
1180 MLXSW_REG_SLDR_OP_LAG_DESTROY
,
1181 /* Ports that appear in the list have the Distributor enabled */
1182 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST
,
1183 /* Removes ports from the disributor list */
1184 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST
,
1191 MLXSW_ITEM32(reg
, sldr
, op
, 0x00, 29, 3);
1194 * LAG identifier. The lag_id is the index into the LAG descriptor table.
1197 MLXSW_ITEM32(reg
, sldr
, lag_id
, 0x00, 0, 10);
1199 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload
, u8 lag_id
)
1201 MLXSW_REG_ZERO(sldr
, payload
);
1202 mlxsw_reg_sldr_op_set(payload
, MLXSW_REG_SLDR_OP_LAG_CREATE
);
1203 mlxsw_reg_sldr_lag_id_set(payload
, lag_id
);
1206 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload
, u8 lag_id
)
1208 MLXSW_REG_ZERO(sldr
, payload
);
1209 mlxsw_reg_sldr_op_set(payload
, MLXSW_REG_SLDR_OP_LAG_DESTROY
);
1210 mlxsw_reg_sldr_lag_id_set(payload
, lag_id
);
1213 /* reg_sldr_num_ports
1214 * The number of member ports of the LAG.
1215 * Reserved for Create / Destroy operations
1216 * For Add / Remove operations - indicates the number of ports in the list.
1219 MLXSW_ITEM32(reg
, sldr
, num_ports
, 0x04, 24, 8);
1221 /* reg_sldr_system_port
1225 MLXSW_ITEM32_INDEXED(reg
, sldr
, system_port
, 0x08, 0, 16, 4, 0, false);
1227 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload
, u8 lag_id
,
1230 MLXSW_REG_ZERO(sldr
, payload
);
1231 mlxsw_reg_sldr_op_set(payload
, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST
);
1232 mlxsw_reg_sldr_lag_id_set(payload
, lag_id
);
1233 mlxsw_reg_sldr_num_ports_set(payload
, 1);
1234 mlxsw_reg_sldr_system_port_set(payload
, 0, local_port
);
1237 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload
, u8 lag_id
,
1240 MLXSW_REG_ZERO(sldr
, payload
);
1241 mlxsw_reg_sldr_op_set(payload
, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST
);
1242 mlxsw_reg_sldr_lag_id_set(payload
, lag_id
);
1243 mlxsw_reg_sldr_num_ports_set(payload
, 1);
1244 mlxsw_reg_sldr_system_port_set(payload
, 0, local_port
);
1247 /* SLCR - Switch LAG Configuration 2 Register
1248 * -------------------------------------------
1249 * The Switch LAG Configuration register is used for configuring the
1250 * LAG properties of the switch.
1252 #define MLXSW_REG_SLCR_ID 0x2015
1253 #define MLXSW_REG_SLCR_LEN 0x10
1255 MLXSW_REG_DEFINE(slcr
, MLXSW_REG_SLCR_ID
, MLXSW_REG_SLCR_LEN
);
1257 enum mlxsw_reg_slcr_pp
{
1258 /* Global Configuration (for all ports) */
1259 MLXSW_REG_SLCR_PP_GLOBAL
,
1260 /* Per port configuration, based on local_port field */
1261 MLXSW_REG_SLCR_PP_PER_PORT
,
1265 * Per Port Configuration
1266 * Note: Reading at Global mode results in reading port 1 configuration.
1269 MLXSW_ITEM32(reg
, slcr
, pp
, 0x00, 24, 1);
1271 /* reg_slcr_local_port
1273 * Supported from CPU port
1274 * Not supported from router port
1275 * Reserved when pp = Global Configuration
1278 MLXSW_ITEM32(reg
, slcr
, local_port
, 0x00, 16, 8);
1280 enum mlxsw_reg_slcr_type
{
1281 MLXSW_REG_SLCR_TYPE_CRC
, /* default */
1282 MLXSW_REG_SLCR_TYPE_XOR
,
1283 MLXSW_REG_SLCR_TYPE_RANDOM
,
1290 MLXSW_ITEM32(reg
, slcr
, type
, 0x00, 0, 4);
1293 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1294 /* SMAC - for IPv4 and IPv6 packets */
1295 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1296 /* SMAC - for non-IP packets */
1297 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1298 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1299 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1300 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1301 /* DMAC - for IPv4 and IPv6 packets */
1302 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1303 /* DMAC - for non-IP packets */
1304 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1305 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1306 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1307 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1308 /* Ethertype - for IPv4 and IPv6 packets */
1309 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1310 /* Ethertype - for non-IP packets */
1311 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1312 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1313 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1314 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1315 /* VLAN ID - for IPv4 and IPv6 packets */
1316 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1317 /* VLAN ID - for non-IP packets */
1318 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1319 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1320 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1321 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1322 /* Source IP address (can be IPv4 or IPv6) */
1323 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1324 /* Destination IP address (can be IPv4 or IPv6) */
1325 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1326 /* TCP/UDP source port */
1327 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1328 /* TCP/UDP destination port*/
1329 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1330 /* IPv4 Protocol/IPv6 Next Header */
1331 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1332 /* IPv6 Flow label */
1333 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1334 /* SID - FCoE source ID */
1335 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1336 /* DID - FCoE destination ID */
1337 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1338 /* OXID - FCoE originator exchange ID */
1339 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1340 /* Destination QP number - for RoCE packets */
1341 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1343 /* reg_slcr_lag_hash
1344 * LAG hashing configuration. This is a bitmask, in which each set
1345 * bit includes the corresponding item in the LAG hash calculation.
1346 * The default lag_hash contains SMAC, DMAC, VLANID and
1347 * Ethertype (for all packet types).
1350 MLXSW_ITEM32(reg
, slcr
, lag_hash
, 0x04, 0, 20);
1352 static inline void mlxsw_reg_slcr_pack(char *payload
, u16 lag_hash
)
1354 MLXSW_REG_ZERO(slcr
, payload
);
1355 mlxsw_reg_slcr_pp_set(payload
, MLXSW_REG_SLCR_PP_GLOBAL
);
1356 mlxsw_reg_slcr_type_set(payload
, MLXSW_REG_SLCR_TYPE_CRC
);
1357 mlxsw_reg_slcr_lag_hash_set(payload
, lag_hash
);
1360 /* SLCOR - Switch LAG Collector Register
1361 * -------------------------------------
1362 * The Switch LAG Collector register controls the Local Port membership
1363 * in a LAG and enablement of the collector.
1365 #define MLXSW_REG_SLCOR_ID 0x2016
1366 #define MLXSW_REG_SLCOR_LEN 0x10
1368 MLXSW_REG_DEFINE(slcor
, MLXSW_REG_SLCOR_ID
, MLXSW_REG_SLCOR_LEN
);
1370 enum mlxsw_reg_slcor_col
{
1371 /* Port is added with collector disabled */
1372 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT
,
1373 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED
,
1374 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED
,
1375 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT
,
1379 * Collector configuration
1382 MLXSW_ITEM32(reg
, slcor
, col
, 0x00, 30, 2);
1384 /* reg_slcor_local_port
1386 * Not supported for CPU port
1389 MLXSW_ITEM32(reg
, slcor
, local_port
, 0x00, 16, 8);
1392 * LAG Identifier. Index into the LAG descriptor table.
1395 MLXSW_ITEM32(reg
, slcor
, lag_id
, 0x00, 0, 10);
1397 /* reg_slcor_port_index
1398 * Port index in the LAG list. Only valid on Add Port to LAG col.
1399 * Valid range is from 0 to cap_max_lag_members-1
1402 MLXSW_ITEM32(reg
, slcor
, port_index
, 0x04, 0, 10);
1404 static inline void mlxsw_reg_slcor_pack(char *payload
,
1405 u8 local_port
, u16 lag_id
,
1406 enum mlxsw_reg_slcor_col col
)
1408 MLXSW_REG_ZERO(slcor
, payload
);
1409 mlxsw_reg_slcor_col_set(payload
, col
);
1410 mlxsw_reg_slcor_local_port_set(payload
, local_port
);
1411 mlxsw_reg_slcor_lag_id_set(payload
, lag_id
);
1414 static inline void mlxsw_reg_slcor_port_add_pack(char *payload
,
1415 u8 local_port
, u16 lag_id
,
1418 mlxsw_reg_slcor_pack(payload
, local_port
, lag_id
,
1419 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT
);
1420 mlxsw_reg_slcor_port_index_set(payload
, port_index
);
1423 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload
,
1424 u8 local_port
, u16 lag_id
)
1426 mlxsw_reg_slcor_pack(payload
, local_port
, lag_id
,
1427 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT
);
1430 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload
,
1431 u8 local_port
, u16 lag_id
)
1433 mlxsw_reg_slcor_pack(payload
, local_port
, lag_id
,
1434 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED
);
1437 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload
,
1438 u8 local_port
, u16 lag_id
)
1440 mlxsw_reg_slcor_pack(payload
, local_port
, lag_id
,
1441 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED
);
1444 /* SPMLR - Switch Port MAC Learning Register
1445 * -----------------------------------------
1446 * Controls the Switch MAC learning policy per port.
1448 #define MLXSW_REG_SPMLR_ID 0x2018
1449 #define MLXSW_REG_SPMLR_LEN 0x8
1451 MLXSW_REG_DEFINE(spmlr
, MLXSW_REG_SPMLR_ID
, MLXSW_REG_SPMLR_LEN
);
1453 /* reg_spmlr_local_port
1454 * Local port number.
1457 MLXSW_ITEM32(reg
, spmlr
, local_port
, 0x00, 16, 8);
1459 /* reg_spmlr_sub_port
1460 * Virtual port within the physical port.
1461 * Should be set to 0 when virtual ports are not enabled on the port.
1464 MLXSW_ITEM32(reg
, spmlr
, sub_port
, 0x00, 8, 8);
1466 enum mlxsw_reg_spmlr_learn_mode
{
1467 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE
= 0,
1468 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE
= 2,
1469 MLXSW_REG_SPMLR_LEARN_MODE_SEC
= 3,
1472 /* reg_spmlr_learn_mode
1473 * Learning mode on the port.
1474 * 0 - Learning disabled.
1475 * 2 - Learning enabled.
1476 * 3 - Security mode.
1478 * In security mode the switch does not learn MACs on the port, but uses the
1479 * SMAC to see if it exists on another ingress port. If so, the packet is
1480 * classified as a bad packet and is discarded unless the software registers
1481 * to receive port security error packets usign HPKT.
1483 MLXSW_ITEM32(reg
, spmlr
, learn_mode
, 0x04, 30, 2);
1485 static inline void mlxsw_reg_spmlr_pack(char *payload
, u8 local_port
,
1486 enum mlxsw_reg_spmlr_learn_mode mode
)
1488 MLXSW_REG_ZERO(spmlr
, payload
);
1489 mlxsw_reg_spmlr_local_port_set(payload
, local_port
);
1490 mlxsw_reg_spmlr_sub_port_set(payload
, 0);
1491 mlxsw_reg_spmlr_learn_mode_set(payload
, mode
);
1494 /* SVFA - Switch VID to FID Allocation Register
1495 * --------------------------------------------
1496 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1497 * virtualized ports.
1499 #define MLXSW_REG_SVFA_ID 0x201C
1500 #define MLXSW_REG_SVFA_LEN 0x10
1502 MLXSW_REG_DEFINE(svfa
, MLXSW_REG_SVFA_ID
, MLXSW_REG_SVFA_LEN
);
1505 * Switch partition ID.
1508 MLXSW_ITEM32(reg
, svfa
, swid
, 0x00, 24, 8);
1510 /* reg_svfa_local_port
1511 * Local port number.
1514 * Note: Reserved for 802.1Q FIDs.
1516 MLXSW_ITEM32(reg
, svfa
, local_port
, 0x00, 16, 8);
1518 enum mlxsw_reg_svfa_mt
{
1519 MLXSW_REG_SVFA_MT_VID_TO_FID
,
1520 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID
,
1523 /* reg_svfa_mapping_table
1526 * 1 - {Port, VID} to FID
1529 * Note: Reserved for SwitchX-2.
1531 MLXSW_ITEM32(reg
, svfa
, mapping_table
, 0x00, 8, 3);
1538 * Note: Reserved for SwitchX-2.
1540 MLXSW_ITEM32(reg
, svfa
, v
, 0x00, 0, 1);
1546 MLXSW_ITEM32(reg
, svfa
, fid
, 0x04, 16, 16);
1552 MLXSW_ITEM32(reg
, svfa
, vid
, 0x04, 0, 12);
1554 /* reg_svfa_counter_set_type
1555 * Counter set type for flow counters.
1558 * Note: Reserved for SwitchX-2.
1560 MLXSW_ITEM32(reg
, svfa
, counter_set_type
, 0x08, 24, 8);
1562 /* reg_svfa_counter_index
1563 * Counter index for flow counters.
1566 * Note: Reserved for SwitchX-2.
1568 MLXSW_ITEM32(reg
, svfa
, counter_index
, 0x08, 0, 24);
1570 static inline void mlxsw_reg_svfa_pack(char *payload
, u8 local_port
,
1571 enum mlxsw_reg_svfa_mt mt
, bool valid
,
1574 MLXSW_REG_ZERO(svfa
, payload
);
1575 local_port
= mt
== MLXSW_REG_SVFA_MT_VID_TO_FID
? 0 : local_port
;
1576 mlxsw_reg_svfa_swid_set(payload
, 0);
1577 mlxsw_reg_svfa_local_port_set(payload
, local_port
);
1578 mlxsw_reg_svfa_mapping_table_set(payload
, mt
);
1579 mlxsw_reg_svfa_v_set(payload
, valid
);
1580 mlxsw_reg_svfa_fid_set(payload
, fid
);
1581 mlxsw_reg_svfa_vid_set(payload
, vid
);
1584 /* SVPE - Switch Virtual-Port Enabling Register
1585 * --------------------------------------------
1586 * Enables port virtualization.
1588 #define MLXSW_REG_SVPE_ID 0x201E
1589 #define MLXSW_REG_SVPE_LEN 0x4
1591 MLXSW_REG_DEFINE(svpe
, MLXSW_REG_SVPE_ID
, MLXSW_REG_SVPE_LEN
);
1593 /* reg_svpe_local_port
1597 * Note: CPU port is not supported (uses VLAN mode only).
1599 MLXSW_ITEM32(reg
, svpe
, local_port
, 0x00, 16, 8);
1602 * Virtual port enable.
1603 * 0 - Disable, VLAN mode (VID to FID).
1604 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1607 MLXSW_ITEM32(reg
, svpe
, vp_en
, 0x00, 8, 1);
1609 static inline void mlxsw_reg_svpe_pack(char *payload
, u8 local_port
,
1612 MLXSW_REG_ZERO(svpe
, payload
);
1613 mlxsw_reg_svpe_local_port_set(payload
, local_port
);
1614 mlxsw_reg_svpe_vp_en_set(payload
, enable
);
1617 /* SFMR - Switch FID Management Register
1618 * -------------------------------------
1619 * Creates and configures FIDs.
1621 #define MLXSW_REG_SFMR_ID 0x201F
1622 #define MLXSW_REG_SFMR_LEN 0x18
1624 MLXSW_REG_DEFINE(sfmr
, MLXSW_REG_SFMR_ID
, MLXSW_REG_SFMR_LEN
);
1626 enum mlxsw_reg_sfmr_op
{
1627 MLXSW_REG_SFMR_OP_CREATE_FID
,
1628 MLXSW_REG_SFMR_OP_DESTROY_FID
,
1633 * 0 - Create or edit FID.
1637 MLXSW_ITEM32(reg
, sfmr
, op
, 0x00, 24, 4);
1643 MLXSW_ITEM32(reg
, sfmr
, fid
, 0x00, 0, 16);
1645 /* reg_sfmr_fid_offset
1647 * Used to point into the flooding table selected by SFGC register if
1648 * the table is of type FID-Offset. Otherwise, this field is reserved.
1651 MLXSW_ITEM32(reg
, sfmr
, fid_offset
, 0x08, 0, 16);
1654 * Valid Tunnel Flood Pointer.
1655 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1658 * Note: Reserved for 802.1Q FIDs.
1660 MLXSW_ITEM32(reg
, sfmr
, vtfp
, 0x0C, 31, 1);
1662 /* reg_sfmr_nve_tunnel_flood_ptr
1663 * Underlay Flooding and BC Pointer.
1664 * Used as a pointer to the first entry of the group based link lists of
1665 * flooding or BC entries (for NVE tunnels).
1668 MLXSW_ITEM32(reg
, sfmr
, nve_tunnel_flood_ptr
, 0x0C, 0, 24);
1672 * If not set, then vni is reserved.
1675 * Note: Reserved for 802.1Q FIDs.
1677 MLXSW_ITEM32(reg
, sfmr
, vv
, 0x10, 31, 1);
1680 * Virtual Network Identifier.
1683 * Note: A given VNI can only be assigned to one FID.
1685 MLXSW_ITEM32(reg
, sfmr
, vni
, 0x10, 0, 24);
1687 static inline void mlxsw_reg_sfmr_pack(char *payload
,
1688 enum mlxsw_reg_sfmr_op op
, u16 fid
,
1691 MLXSW_REG_ZERO(sfmr
, payload
);
1692 mlxsw_reg_sfmr_op_set(payload
, op
);
1693 mlxsw_reg_sfmr_fid_set(payload
, fid
);
1694 mlxsw_reg_sfmr_fid_offset_set(payload
, fid_offset
);
1695 mlxsw_reg_sfmr_vtfp_set(payload
, false);
1696 mlxsw_reg_sfmr_vv_set(payload
, false);
1699 /* SPVMLR - Switch Port VLAN MAC Learning Register
1700 * -----------------------------------------------
1701 * Controls the switch MAC learning policy per {Port, VID}.
1703 #define MLXSW_REG_SPVMLR_ID 0x2020
1704 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1705 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1706 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1707 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1708 MLXSW_REG_SPVMLR_REC_LEN * \
1709 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1711 MLXSW_REG_DEFINE(spvmlr
, MLXSW_REG_SPVMLR_ID
, MLXSW_REG_SPVMLR_LEN
);
1713 /* reg_spvmlr_local_port
1714 * Local ingress port.
1717 * Note: CPU port is not supported.
1719 MLXSW_ITEM32(reg
, spvmlr
, local_port
, 0x00, 16, 8);
1721 /* reg_spvmlr_num_rec
1722 * Number of records to update.
1725 MLXSW_ITEM32(reg
, spvmlr
, num_rec
, 0x00, 0, 8);
1727 /* reg_spvmlr_rec_learn_enable
1728 * 0 - Disable learning for {Port, VID}.
1729 * 1 - Enable learning for {Port, VID}.
1732 MLXSW_ITEM32_INDEXED(reg
, spvmlr
, rec_learn_enable
, MLXSW_REG_SPVMLR_BASE_LEN
,
1733 31, 1, MLXSW_REG_SPVMLR_REC_LEN
, 0x00, false);
1735 /* reg_spvmlr_rec_vid
1736 * VLAN ID to be added/removed from port or for querying.
1739 MLXSW_ITEM32_INDEXED(reg
, spvmlr
, rec_vid
, MLXSW_REG_SPVMLR_BASE_LEN
, 0, 12,
1740 MLXSW_REG_SPVMLR_REC_LEN
, 0x00, false);
1742 static inline void mlxsw_reg_spvmlr_pack(char *payload
, u8 local_port
,
1743 u16 vid_begin
, u16 vid_end
,
1746 int num_rec
= vid_end
- vid_begin
+ 1;
1749 WARN_ON(num_rec
< 1 || num_rec
> MLXSW_REG_SPVMLR_REC_MAX_COUNT
);
1751 MLXSW_REG_ZERO(spvmlr
, payload
);
1752 mlxsw_reg_spvmlr_local_port_set(payload
, local_port
);
1753 mlxsw_reg_spvmlr_num_rec_set(payload
, num_rec
);
1755 for (i
= 0; i
< num_rec
; i
++) {
1756 mlxsw_reg_spvmlr_rec_learn_enable_set(payload
, i
, learn_enable
);
1757 mlxsw_reg_spvmlr_rec_vid_set(payload
, i
, vid_begin
+ i
);
1761 /* PPBT - Policy-Engine Port Binding Table
1762 * ---------------------------------------
1763 * This register is used for configuration of the Port Binding Table.
1765 #define MLXSW_REG_PPBT_ID 0x3002
1766 #define MLXSW_REG_PPBT_LEN 0x14
1768 MLXSW_REG_DEFINE(ppbt
, MLXSW_REG_PPBT_ID
, MLXSW_REG_PPBT_LEN
);
1770 enum mlxsw_reg_pxbt_e
{
1771 MLXSW_REG_PXBT_E_IACL
,
1772 MLXSW_REG_PXBT_E_EACL
,
1778 MLXSW_ITEM32(reg
, ppbt
, e
, 0x00, 31, 1);
1780 enum mlxsw_reg_pxbt_op
{
1781 MLXSW_REG_PXBT_OP_BIND
,
1782 MLXSW_REG_PXBT_OP_UNBIND
,
1788 MLXSW_ITEM32(reg
, ppbt
, op
, 0x00, 28, 3);
1790 /* reg_ppbt_local_port
1791 * Local port. Not including CPU port.
1794 MLXSW_ITEM32(reg
, ppbt
, local_port
, 0x00, 16, 8);
1797 * group - When set, the binding is of an ACL group. When cleared,
1798 * the binding is of an ACL.
1799 * Must be set to 1 for Spectrum.
1802 MLXSW_ITEM32(reg
, ppbt
, g
, 0x10, 31, 1);
1804 /* reg_ppbt_acl_info
1805 * ACL/ACL group identifier. If the g bit is set, this field should hold
1806 * the acl_group_id, else it should hold the acl_id.
1809 MLXSW_ITEM32(reg
, ppbt
, acl_info
, 0x10, 0, 16);
1811 static inline void mlxsw_reg_ppbt_pack(char *payload
, enum mlxsw_reg_pxbt_e e
,
1812 enum mlxsw_reg_pxbt_op op
,
1813 u8 local_port
, u16 acl_info
)
1815 MLXSW_REG_ZERO(ppbt
, payload
);
1816 mlxsw_reg_ppbt_e_set(payload
, e
);
1817 mlxsw_reg_ppbt_op_set(payload
, op
);
1818 mlxsw_reg_ppbt_local_port_set(payload
, local_port
);
1819 mlxsw_reg_ppbt_g_set(payload
, true);
1820 mlxsw_reg_ppbt_acl_info_set(payload
, acl_info
);
1823 /* PACL - Policy-Engine ACL Register
1824 * ---------------------------------
1825 * This register is used for configuration of the ACL.
1827 #define MLXSW_REG_PACL_ID 0x3004
1828 #define MLXSW_REG_PACL_LEN 0x70
1830 MLXSW_REG_DEFINE(pacl
, MLXSW_REG_PACL_ID
, MLXSW_REG_PACL_LEN
);
1833 * Valid. Setting the v bit makes the ACL valid. It should not be cleared
1834 * while the ACL is bounded to either a port, VLAN or ACL rule.
1837 MLXSW_ITEM32(reg
, pacl
, v
, 0x00, 24, 1);
1840 * An identifier representing the ACL (managed by software)
1841 * Range 0 .. cap_max_acl_regions - 1
1844 MLXSW_ITEM32(reg
, pacl
, acl_id
, 0x08, 0, 16);
1846 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
1848 /* reg_pacl_tcam_region_info
1849 * Opaque object that represents a TCAM region.
1850 * Obtained through PTAR register.
1853 MLXSW_ITEM_BUF(reg
, pacl
, tcam_region_info
, 0x30,
1854 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN
);
1856 static inline void mlxsw_reg_pacl_pack(char *payload
, u16 acl_id
,
1857 bool valid
, const char *tcam_region_info
)
1859 MLXSW_REG_ZERO(pacl
, payload
);
1860 mlxsw_reg_pacl_acl_id_set(payload
, acl_id
);
1861 mlxsw_reg_pacl_v_set(payload
, valid
);
1862 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload
, tcam_region_info
);
1865 /* PAGT - Policy-Engine ACL Group Table
1866 * ------------------------------------
1867 * This register is used for configuration of the ACL Group Table.
1869 #define MLXSW_REG_PAGT_ID 0x3005
1870 #define MLXSW_REG_PAGT_BASE_LEN 0x30
1871 #define MLXSW_REG_PAGT_ACL_LEN 4
1872 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16
1873 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
1874 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
1876 MLXSW_REG_DEFINE(pagt
, MLXSW_REG_PAGT_ID
, MLXSW_REG_PAGT_LEN
);
1879 * Number of ACLs in the group.
1880 * Size 0 invalidates a group.
1881 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
1882 * Total number of ACLs in all groups must be lower or equal
1883 * to cap_max_acl_tot_groups
1884 * Note: a group which is binded must not be invalidated
1887 MLXSW_ITEM32(reg
, pagt
, size
, 0x00, 0, 8);
1889 /* reg_pagt_acl_group_id
1890 * An identifier (numbered from 0..cap_max_acl_groups-1) representing
1891 * the ACL Group identifier (managed by software).
1894 MLXSW_ITEM32(reg
, pagt
, acl_group_id
, 0x08, 0, 16);
1900 MLXSW_ITEM32_INDEXED(reg
, pagt
, acl_id
, 0x30, 0, 16, 0x04, 0x00, false);
1902 static inline void mlxsw_reg_pagt_pack(char *payload
, u16 acl_group_id
)
1904 MLXSW_REG_ZERO(pagt
, payload
);
1905 mlxsw_reg_pagt_acl_group_id_set(payload
, acl_group_id
);
1908 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload
, int index
,
1911 u8 size
= mlxsw_reg_pagt_size_get(payload
);
1914 mlxsw_reg_pagt_size_set(payload
, index
+ 1);
1915 mlxsw_reg_pagt_acl_id_set(payload
, index
, acl_id
);
1918 /* PTAR - Policy-Engine TCAM Allocation Register
1919 * ---------------------------------------------
1920 * This register is used for allocation of regions in the TCAM.
1921 * Note: Query method is not supported on this register.
1923 #define MLXSW_REG_PTAR_ID 0x3006
1924 #define MLXSW_REG_PTAR_BASE_LEN 0x20
1925 #define MLXSW_REG_PTAR_KEY_ID_LEN 1
1926 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
1927 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
1928 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
1930 MLXSW_REG_DEFINE(ptar
, MLXSW_REG_PTAR_ID
, MLXSW_REG_PTAR_LEN
);
1932 enum mlxsw_reg_ptar_op
{
1933 /* allocate a TCAM region */
1934 MLXSW_REG_PTAR_OP_ALLOC
,
1935 /* resize a TCAM region */
1936 MLXSW_REG_PTAR_OP_RESIZE
,
1937 /* deallocate TCAM region */
1938 MLXSW_REG_PTAR_OP_FREE
,
1939 /* test allocation */
1940 MLXSW_REG_PTAR_OP_TEST
,
1946 MLXSW_ITEM32(reg
, ptar
, op
, 0x00, 28, 4);
1948 /* reg_ptar_action_set_type
1949 * Type of action set to be used on this region.
1950 * For Spectrum, this is always type 2 - "flexible"
1953 MLXSW_ITEM32(reg
, ptar
, action_set_type
, 0x00, 16, 8);
1955 /* reg_ptar_key_type
1956 * TCAM key type for the region.
1957 * For Spectrum, this is always type 0x50 - "FLEX_KEY"
1960 MLXSW_ITEM32(reg
, ptar
, key_type
, 0x00, 0, 8);
1962 /* reg_ptar_region_size
1963 * TCAM region size. When allocating/resizing this is the requested size,
1964 * the response is the actual size. Note that actual size may be
1965 * larger than requested.
1966 * Allowed range 1 .. cap_max_rules-1
1967 * Reserved during op deallocate.
1970 MLXSW_ITEM32(reg
, ptar
, region_size
, 0x04, 0, 16);
1972 /* reg_ptar_region_id
1974 * Range 0 .. cap_max_regions-1
1977 MLXSW_ITEM32(reg
, ptar
, region_id
, 0x08, 0, 16);
1979 /* reg_ptar_tcam_region_info
1980 * Opaque object that represents the TCAM region.
1981 * Returned when allocating a region.
1982 * Provided by software for ACL generation and region deallocation and resize.
1985 MLXSW_ITEM_BUF(reg
, ptar
, tcam_region_info
, 0x10,
1986 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN
);
1988 /* reg_ptar_flexible_key_id
1989 * Identifier of the Flexible Key.
1990 * Only valid if key_type == "FLEX_KEY"
1991 * The key size will be rounded up to one of the following values:
1992 * 9B, 18B, 36B, 54B.
1993 * This field is reserved for in resize operation.
1996 MLXSW_ITEM8_INDEXED(reg
, ptar
, flexible_key_id
, 0x20, 0, 8,
1997 MLXSW_REG_PTAR_KEY_ID_LEN
, 0x00, false);
1999 static inline void mlxsw_reg_ptar_pack(char *payload
, enum mlxsw_reg_ptar_op op
,
2000 u16 region_size
, u16 region_id
,
2001 const char *tcam_region_info
)
2003 MLXSW_REG_ZERO(ptar
, payload
);
2004 mlxsw_reg_ptar_op_set(payload
, op
);
2005 mlxsw_reg_ptar_action_set_type_set(payload
, 2); /* "flexible" */
2006 mlxsw_reg_ptar_key_type_set(payload
, 0x50); /* "FLEX_KEY" */
2007 mlxsw_reg_ptar_region_size_set(payload
, region_size
);
2008 mlxsw_reg_ptar_region_id_set(payload
, region_id
);
2009 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload
, tcam_region_info
);
2012 static inline void mlxsw_reg_ptar_key_id_pack(char *payload
, int index
,
2015 mlxsw_reg_ptar_flexible_key_id_set(payload
, index
, key_id
);
2018 static inline void mlxsw_reg_ptar_unpack(char *payload
, char *tcam_region_info
)
2020 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload
, tcam_region_info
);
2023 /* PPBS - Policy-Engine Policy Based Switching Register
2024 * ----------------------------------------------------
2025 * This register retrieves and sets Policy Based Switching Table entries.
2027 #define MLXSW_REG_PPBS_ID 0x300C
2028 #define MLXSW_REG_PPBS_LEN 0x14
2030 MLXSW_REG_DEFINE(ppbs
, MLXSW_REG_PPBS_ID
, MLXSW_REG_PPBS_LEN
);
2033 * Index into the PBS table.
2034 * For Spectrum, the index points to the KVD Linear.
2037 MLXSW_ITEM32(reg
, ppbs
, pbs_ptr
, 0x08, 0, 24);
2039 /* reg_ppbs_system_port
2040 * Unique port identifier for the final destination of the packet.
2043 MLXSW_ITEM32(reg
, ppbs
, system_port
, 0x10, 0, 16);
2045 static inline void mlxsw_reg_ppbs_pack(char *payload
, u32 pbs_ptr
,
2048 MLXSW_REG_ZERO(ppbs
, payload
);
2049 mlxsw_reg_ppbs_pbs_ptr_set(payload
, pbs_ptr
);
2050 mlxsw_reg_ppbs_system_port_set(payload
, system_port
);
2053 /* PRCR - Policy-Engine Rules Copy Register
2054 * ----------------------------------------
2055 * This register is used for accessing rules within a TCAM region.
2057 #define MLXSW_REG_PRCR_ID 0x300D
2058 #define MLXSW_REG_PRCR_LEN 0x40
2060 MLXSW_REG_DEFINE(prcr
, MLXSW_REG_PRCR_ID
, MLXSW_REG_PRCR_LEN
);
2062 enum mlxsw_reg_prcr_op
{
2063 /* Move rules. Moves the rules from "tcam_region_info" starting
2064 * at offset "offset" to "dest_tcam_region_info"
2065 * at offset "dest_offset."
2067 MLXSW_REG_PRCR_OP_MOVE
,
2068 /* Copy rules. Copies the rules from "tcam_region_info" starting
2069 * at offset "offset" to "dest_tcam_region_info"
2070 * at offset "dest_offset."
2072 MLXSW_REG_PRCR_OP_COPY
,
2078 MLXSW_ITEM32(reg
, prcr
, op
, 0x00, 28, 4);
2081 * Offset within the source region to copy/move from.
2084 MLXSW_ITEM32(reg
, prcr
, offset
, 0x00, 0, 16);
2087 * The number of rules to copy/move.
2090 MLXSW_ITEM32(reg
, prcr
, size
, 0x04, 0, 16);
2092 /* reg_prcr_tcam_region_info
2093 * Opaque object that represents the source TCAM region.
2096 MLXSW_ITEM_BUF(reg
, prcr
, tcam_region_info
, 0x10,
2097 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN
);
2099 /* reg_prcr_dest_offset
2100 * Offset within the source region to copy/move to.
2103 MLXSW_ITEM32(reg
, prcr
, dest_offset
, 0x20, 0, 16);
2105 /* reg_prcr_dest_tcam_region_info
2106 * Opaque object that represents the destination TCAM region.
2109 MLXSW_ITEM_BUF(reg
, prcr
, dest_tcam_region_info
, 0x30,
2110 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN
);
2112 static inline void mlxsw_reg_prcr_pack(char *payload
, enum mlxsw_reg_prcr_op op
,
2113 const char *src_tcam_region_info
,
2115 const char *dest_tcam_region_info
,
2116 u16 dest_offset
, u16 size
)
2118 MLXSW_REG_ZERO(prcr
, payload
);
2119 mlxsw_reg_prcr_op_set(payload
, op
);
2120 mlxsw_reg_prcr_offset_set(payload
, src_offset
);
2121 mlxsw_reg_prcr_size_set(payload
, size
);
2122 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload
,
2123 src_tcam_region_info
);
2124 mlxsw_reg_prcr_dest_offset_set(payload
, dest_offset
);
2125 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload
,
2126 dest_tcam_region_info
);
2129 /* PEFA - Policy-Engine Extended Flexible Action Register
2130 * ------------------------------------------------------
2131 * This register is used for accessing an extended flexible action entry
2132 * in the central KVD Linear Database.
2134 #define MLXSW_REG_PEFA_ID 0x300F
2135 #define MLXSW_REG_PEFA_LEN 0xB0
2137 MLXSW_REG_DEFINE(pefa
, MLXSW_REG_PEFA_ID
, MLXSW_REG_PEFA_LEN
);
2140 * Index in the KVD Linear Centralized Database.
2143 MLXSW_ITEM32(reg
, pefa
, index
, 0x00, 0, 24);
2145 #define MLXSW_REG_PXXX_FLEX_ACTION_SET_LEN 0xA8
2147 /* reg_pefa_flex_action_set
2148 * Action-set to perform when rule is matched.
2149 * Must be zero padded if action set is shorter.
2152 MLXSW_ITEM_BUF(reg
, pefa
, flex_action_set
, 0x08,
2153 MLXSW_REG_PXXX_FLEX_ACTION_SET_LEN
);
2155 static inline void mlxsw_reg_pefa_pack(char *payload
, u32 index
,
2156 const char *flex_action_set
)
2158 MLXSW_REG_ZERO(pefa
, payload
);
2159 mlxsw_reg_pefa_index_set(payload
, index
);
2160 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload
, flex_action_set
);
2163 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
2164 * -----------------------------------------------------
2165 * This register is used for accessing rules within a TCAM region.
2166 * It is a new version of PTCE in order to support wider key,
2167 * mask and action within a TCAM region. This register is not supported
2168 * by SwitchX and SwitchX-2.
2170 #define MLXSW_REG_PTCE2_ID 0x3017
2171 #define MLXSW_REG_PTCE2_LEN 0x1D8
2173 MLXSW_REG_DEFINE(ptce2
, MLXSW_REG_PTCE2_ID
, MLXSW_REG_PTCE2_LEN
);
2179 MLXSW_ITEM32(reg
, ptce2
, v
, 0x00, 31, 1);
2182 * Activity. Set if a packet lookup has hit on the specific entry.
2183 * To clear the "a" bit, use "clear activity" op or "clear on read" op.
2186 MLXSW_ITEM32(reg
, ptce2
, a
, 0x00, 30, 1);
2188 enum mlxsw_reg_ptce2_op
{
2189 /* Read operation. */
2190 MLXSW_REG_PTCE2_OP_QUERY_READ
= 0,
2191 /* clear on read operation. Used to read entry
2192 * and clear Activity bit.
2194 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ
= 1,
2195 /* Write operation. Used to write a new entry to the table.
2196 * All R/W fields are relevant for new entry. Activity bit is set
2197 * for new entries - Note write with v = 0 will delete the entry.
2199 MLXSW_REG_PTCE2_OP_WRITE_WRITE
= 0,
2200 /* Update action. Only action set will be updated. */
2201 MLXSW_REG_PTCE2_OP_WRITE_UPDATE
= 1,
2202 /* Clear activity. A bit is cleared for the entry. */
2203 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY
= 2,
2209 MLXSW_ITEM32(reg
, ptce2
, op
, 0x00, 20, 3);
2214 MLXSW_ITEM32(reg
, ptce2
, offset
, 0x00, 0, 16);
2216 /* reg_ptce2_tcam_region_info
2217 * Opaque object that represents the TCAM region.
2220 MLXSW_ITEM_BUF(reg
, ptce2
, tcam_region_info
, 0x10,
2221 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN
);
2223 #define MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN 96
2225 /* reg_ptce2_flex_key_blocks
2229 MLXSW_ITEM_BUF(reg
, ptce2
, flex_key_blocks
, 0x20,
2230 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN
);
2233 * mask- in the same size as key. A bit that is set directs the TCAM
2234 * to compare the corresponding bit in key. A bit that is clear directs
2235 * the TCAM to ignore the corresponding bit in key.
2238 MLXSW_ITEM_BUF(reg
, ptce2
, mask
, 0x80,
2239 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN
);
2241 /* reg_ptce2_flex_action_set
2245 MLXSW_ITEM_BUF(reg
, ptce2
, flex_action_set
, 0xE0,
2246 MLXSW_REG_PXXX_FLEX_ACTION_SET_LEN
);
2248 static inline void mlxsw_reg_ptce2_pack(char *payload
, bool valid
,
2249 enum mlxsw_reg_ptce2_op op
,
2250 const char *tcam_region_info
,
2253 MLXSW_REG_ZERO(ptce2
, payload
);
2254 mlxsw_reg_ptce2_v_set(payload
, valid
);
2255 mlxsw_reg_ptce2_op_set(payload
, op
);
2256 mlxsw_reg_ptce2_offset_set(payload
, offset
);
2257 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload
, tcam_region_info
);
2260 /* QPCR - QoS Policer Configuration Register
2261 * -----------------------------------------
2262 * The QPCR register is used to create policers - that limit
2263 * the rate of bytes or packets via some trap group.
2265 #define MLXSW_REG_QPCR_ID 0x4004
2266 #define MLXSW_REG_QPCR_LEN 0x28
2268 MLXSW_REG_DEFINE(qpcr
, MLXSW_REG_QPCR_ID
, MLXSW_REG_QPCR_LEN
);
2270 enum mlxsw_reg_qpcr_g
{
2271 MLXSW_REG_QPCR_G_GLOBAL
= 2,
2272 MLXSW_REG_QPCR_G_STORM_CONTROL
= 3,
2279 MLXSW_ITEM32(reg
, qpcr
, g
, 0x00, 14, 2);
2285 MLXSW_ITEM32(reg
, qpcr
, pid
, 0x00, 0, 14);
2287 /* reg_qpcr_color_aware
2288 * Is the policer aware of colors.
2289 * Must be 0 (unaware) for cpu port.
2290 * Access: RW for unbounded policer. RO for bounded policer.
2292 MLXSW_ITEM32(reg
, qpcr
, color_aware
, 0x04, 15, 1);
2295 * Is policer limit is for bytes per sec or packets per sec.
2298 * Access: RW for unbounded policer. RO for bounded policer.
2300 MLXSW_ITEM32(reg
, qpcr
, bytes
, 0x04, 14, 1);
2302 enum mlxsw_reg_qpcr_ir_units
{
2303 MLXSW_REG_QPCR_IR_UNITS_M
,
2304 MLXSW_REG_QPCR_IR_UNITS_K
,
2307 /* reg_qpcr_ir_units
2308 * Policer's units for cir and eir fields (for bytes limits only)
2313 MLXSW_ITEM32(reg
, qpcr
, ir_units
, 0x04, 12, 1);
2315 enum mlxsw_reg_qpcr_rate_type
{
2316 MLXSW_REG_QPCR_RATE_TYPE_SINGLE
= 1,
2317 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE
= 2,
2320 /* reg_qpcr_rate_type
2321 * Policer can have one limit (single rate) or 2 limits with specific operation
2322 * for packets that exceed the lower rate but not the upper one.
2323 * (For cpu port must be single rate)
2324 * Access: RW for unbounded policer. RO for bounded policer.
2326 MLXSW_ITEM32(reg
, qpcr
, rate_type
, 0x04, 8, 2);
2329 * Policer's committed burst size.
2330 * The policer is working with time slices of 50 nano sec. By default every
2331 * slice is granted the proportionate share of the committed rate. If we want to
2332 * allow a slice to exceed that share (while still keeping the rate per sec) we
2333 * can allow burst. The burst size is between the default proportionate share
2334 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
2335 * committed rate will result in exceeding the rate). The burst size must be a
2336 * log of 2 and will be determined by 2^cbs.
2339 MLXSW_ITEM32(reg
, qpcr
, cbs
, 0x08, 24, 6);
2342 * Policer's committed rate.
2343 * The rate used for sungle rate, the lower rate for double rate.
2344 * For bytes limits, the rate will be this value * the unit from ir_units.
2345 * (Resolution error is up to 1%).
2348 MLXSW_ITEM32(reg
, qpcr
, cir
, 0x0C, 0, 32);
2351 * Policer's exceed rate.
2352 * The higher rate for double rate, reserved for single rate.
2353 * Lower rate for double rate policer.
2354 * For bytes limits, the rate will be this value * the unit from ir_units.
2355 * (Resolution error is up to 1%).
2358 MLXSW_ITEM32(reg
, qpcr
, eir
, 0x10, 0, 32);
2360 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
2362 /* reg_qpcr_exceed_action.
2363 * What to do with packets between the 2 limits for double rate.
2364 * Access: RW for unbounded policer. RO for bounded policer.
2366 MLXSW_ITEM32(reg
, qpcr
, exceed_action
, 0x14, 0, 4);
2368 enum mlxsw_reg_qpcr_action
{
2370 MLXSW_REG_QPCR_ACTION_DISCARD
= 1,
2371 /* Forward and set color to red.
2372 * If the packet is intended to cpu port, it will be dropped.
2374 MLXSW_REG_QPCR_ACTION_FORWARD
= 2,
2377 /* reg_qpcr_violate_action
2378 * What to do with packets that cross the cir limit (for single rate) or the eir
2379 * limit (for double rate).
2380 * Access: RW for unbounded policer. RO for bounded policer.
2382 MLXSW_ITEM32(reg
, qpcr
, violate_action
, 0x18, 0, 4);
2384 static inline void mlxsw_reg_qpcr_pack(char *payload
, u16 pid
,
2385 enum mlxsw_reg_qpcr_ir_units ir_units
,
2386 bool bytes
, u32 cir
, u16 cbs
)
2388 MLXSW_REG_ZERO(qpcr
, payload
);
2389 mlxsw_reg_qpcr_pid_set(payload
, pid
);
2390 mlxsw_reg_qpcr_g_set(payload
, MLXSW_REG_QPCR_G_GLOBAL
);
2391 mlxsw_reg_qpcr_rate_type_set(payload
, MLXSW_REG_QPCR_RATE_TYPE_SINGLE
);
2392 mlxsw_reg_qpcr_violate_action_set(payload
,
2393 MLXSW_REG_QPCR_ACTION_DISCARD
);
2394 mlxsw_reg_qpcr_cir_set(payload
, cir
);
2395 mlxsw_reg_qpcr_ir_units_set(payload
, ir_units
);
2396 mlxsw_reg_qpcr_bytes_set(payload
, bytes
);
2397 mlxsw_reg_qpcr_cbs_set(payload
, cbs
);
2400 /* QTCT - QoS Switch Traffic Class Table
2401 * -------------------------------------
2402 * Configures the mapping between the packet switch priority and the
2403 * traffic class on the transmit port.
2405 #define MLXSW_REG_QTCT_ID 0x400A
2406 #define MLXSW_REG_QTCT_LEN 0x08
2408 MLXSW_REG_DEFINE(qtct
, MLXSW_REG_QTCT_ID
, MLXSW_REG_QTCT_LEN
);
2410 /* reg_qtct_local_port
2411 * Local port number.
2414 * Note: CPU port is not supported.
2416 MLXSW_ITEM32(reg
, qtct
, local_port
, 0x00, 16, 8);
2418 /* reg_qtct_sub_port
2419 * Virtual port within the physical port.
2420 * Should be set to 0 when virtual ports are not enabled on the port.
2423 MLXSW_ITEM32(reg
, qtct
, sub_port
, 0x00, 8, 8);
2425 /* reg_qtct_switch_prio
2429 MLXSW_ITEM32(reg
, qtct
, switch_prio
, 0x00, 0, 4);
2434 * switch_prio 0 : tclass 1
2435 * switch_prio 1 : tclass 0
2436 * switch_prio i : tclass i, for i > 1
2439 MLXSW_ITEM32(reg
, qtct
, tclass
, 0x04, 0, 4);
2441 static inline void mlxsw_reg_qtct_pack(char *payload
, u8 local_port
,
2442 u8 switch_prio
, u8 tclass
)
2444 MLXSW_REG_ZERO(qtct
, payload
);
2445 mlxsw_reg_qtct_local_port_set(payload
, local_port
);
2446 mlxsw_reg_qtct_switch_prio_set(payload
, switch_prio
);
2447 mlxsw_reg_qtct_tclass_set(payload
, tclass
);
2450 /* QEEC - QoS ETS Element Configuration Register
2451 * ---------------------------------------------
2452 * Configures the ETS elements.
2454 #define MLXSW_REG_QEEC_ID 0x400D
2455 #define MLXSW_REG_QEEC_LEN 0x1C
2457 MLXSW_REG_DEFINE(qeec
, MLXSW_REG_QEEC_ID
, MLXSW_REG_QEEC_LEN
);
2459 /* reg_qeec_local_port
2460 * Local port number.
2463 * Note: CPU port is supported.
2465 MLXSW_ITEM32(reg
, qeec
, local_port
, 0x00, 16, 8);
2467 enum mlxsw_reg_qeec_hr
{
2468 MLXSW_REG_QEEC_HIERARCY_PORT
,
2469 MLXSW_REG_QEEC_HIERARCY_GROUP
,
2470 MLXSW_REG_QEEC_HIERARCY_SUBGROUP
,
2471 MLXSW_REG_QEEC_HIERARCY_TC
,
2474 /* reg_qeec_element_hierarchy
2481 MLXSW_ITEM32(reg
, qeec
, element_hierarchy
, 0x04, 16, 4);
2483 /* reg_qeec_element_index
2484 * The index of the element in the hierarchy.
2487 MLXSW_ITEM32(reg
, qeec
, element_index
, 0x04, 0, 8);
2489 /* reg_qeec_next_element_index
2490 * The index of the next (lower) element in the hierarchy.
2493 * Note: Reserved for element_hierarchy 0.
2495 MLXSW_ITEM32(reg
, qeec
, next_element_index
, 0x08, 0, 8);
2498 MLXSW_REG_QEEC_BYTES_MODE
,
2499 MLXSW_REG_QEEC_PACKETS_MODE
,
2503 * Packets or bytes mode.
2508 * Note: Used for max shaper configuration. For Spectrum, packets mode
2509 * is supported only for traffic classes of CPU port.
2511 MLXSW_ITEM32(reg
, qeec
, pb
, 0x0C, 28, 1);
2514 * Max shaper configuration enable. Enables configuration of the max
2515 * shaper on this ETS element.
2520 MLXSW_ITEM32(reg
, qeec
, mase
, 0x10, 31, 1);
2522 /* A large max rate will disable the max shaper. */
2523 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */
2525 /* reg_qeec_max_shaper_rate
2526 * Max shaper information rate.
2527 * For CPU port, can only be configured for port hierarchy.
2528 * When in bytes mode, value is specified in units of 1000bps.
2531 MLXSW_ITEM32(reg
, qeec
, max_shaper_rate
, 0x10, 0, 28);
2534 * DWRR configuration enable. Enables configuration of the dwrr and
2540 MLXSW_ITEM32(reg
, qeec
, de
, 0x18, 31, 1);
2543 * Transmission selection algorithm to use on the link going down from
2545 * 0 - Strict priority
2549 MLXSW_ITEM32(reg
, qeec
, dwrr
, 0x18, 15, 1);
2551 /* reg_qeec_dwrr_weight
2552 * DWRR weight on the link going down from the ETS element. The
2553 * percentage of bandwidth guaranteed to an ETS element within
2554 * its hierarchy. The sum of all weights across all ETS elements
2555 * within one hierarchy should be equal to 100. Reserved when
2556 * transmission selection algorithm is strict priority.
2559 MLXSW_ITEM32(reg
, qeec
, dwrr_weight
, 0x18, 0, 8);
2561 static inline void mlxsw_reg_qeec_pack(char *payload
, u8 local_port
,
2562 enum mlxsw_reg_qeec_hr hr
, u8 index
,
2565 MLXSW_REG_ZERO(qeec
, payload
);
2566 mlxsw_reg_qeec_local_port_set(payload
, local_port
);
2567 mlxsw_reg_qeec_element_hierarchy_set(payload
, hr
);
2568 mlxsw_reg_qeec_element_index_set(payload
, index
);
2569 mlxsw_reg_qeec_next_element_index_set(payload
, next_index
);
2572 /* PMLP - Ports Module to Local Port Register
2573 * ------------------------------------------
2574 * Configures the assignment of modules to local ports.
2576 #define MLXSW_REG_PMLP_ID 0x5002
2577 #define MLXSW_REG_PMLP_LEN 0x40
2579 MLXSW_REG_DEFINE(pmlp
, MLXSW_REG_PMLP_ID
, MLXSW_REG_PMLP_LEN
);
2582 * 0 - Tx value is used for both Tx and Rx.
2583 * 1 - Rx value is taken from a separte field.
2586 MLXSW_ITEM32(reg
, pmlp
, rxtx
, 0x00, 31, 1);
2588 /* reg_pmlp_local_port
2589 * Local port number.
2592 MLXSW_ITEM32(reg
, pmlp
, local_port
, 0x00, 16, 8);
2595 * 0 - Unmap local port.
2596 * 1 - Lane 0 is used.
2597 * 2 - Lanes 0 and 1 are used.
2598 * 4 - Lanes 0, 1, 2 and 3 are used.
2601 MLXSW_ITEM32(reg
, pmlp
, width
, 0x00, 0, 8);
2607 MLXSW_ITEM32_INDEXED(reg
, pmlp
, module
, 0x04, 0, 8, 0x04, 0x00, false);
2610 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
2613 MLXSW_ITEM32_INDEXED(reg
, pmlp
, tx_lane
, 0x04, 16, 2, 0x04, 0x00, false);
2616 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
2620 MLXSW_ITEM32_INDEXED(reg
, pmlp
, rx_lane
, 0x04, 24, 2, 0x04, 0x00, false);
2622 static inline void mlxsw_reg_pmlp_pack(char *payload
, u8 local_port
)
2624 MLXSW_REG_ZERO(pmlp
, payload
);
2625 mlxsw_reg_pmlp_local_port_set(payload
, local_port
);
2628 /* PMTU - Port MTU Register
2629 * ------------------------
2630 * Configures and reports the port MTU.
2632 #define MLXSW_REG_PMTU_ID 0x5003
2633 #define MLXSW_REG_PMTU_LEN 0x10
2635 MLXSW_REG_DEFINE(pmtu
, MLXSW_REG_PMTU_ID
, MLXSW_REG_PMTU_LEN
);
2637 /* reg_pmtu_local_port
2638 * Local port number.
2641 MLXSW_ITEM32(reg
, pmtu
, local_port
, 0x00, 16, 8);
2645 * When port type (e.g. Ethernet) is configured, the relevant MTU is
2646 * reported, otherwise the minimum between the max_mtu of the different
2647 * types is reported.
2650 MLXSW_ITEM32(reg
, pmtu
, max_mtu
, 0x04, 16, 16);
2652 /* reg_pmtu_admin_mtu
2653 * MTU value to set port to. Must be smaller or equal to max_mtu.
2654 * Note: If port type is Infiniband, then port must be disabled, when its
2658 MLXSW_ITEM32(reg
, pmtu
, admin_mtu
, 0x08, 16, 16);
2660 /* reg_pmtu_oper_mtu
2661 * The actual MTU configured on the port. Packets exceeding this size
2663 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
2664 * oper_mtu might be smaller than admin_mtu.
2667 MLXSW_ITEM32(reg
, pmtu
, oper_mtu
, 0x0C, 16, 16);
2669 static inline void mlxsw_reg_pmtu_pack(char *payload
, u8 local_port
,
2672 MLXSW_REG_ZERO(pmtu
, payload
);
2673 mlxsw_reg_pmtu_local_port_set(payload
, local_port
);
2674 mlxsw_reg_pmtu_max_mtu_set(payload
, 0);
2675 mlxsw_reg_pmtu_admin_mtu_set(payload
, new_mtu
);
2676 mlxsw_reg_pmtu_oper_mtu_set(payload
, 0);
2679 /* PTYS - Port Type and Speed Register
2680 * -----------------------------------
2681 * Configures and reports the port speed type.
2683 * Note: When set while the link is up, the changes will not take effect
2684 * until the port transitions from down to up state.
2686 #define MLXSW_REG_PTYS_ID 0x5004
2687 #define MLXSW_REG_PTYS_LEN 0x40
2689 MLXSW_REG_DEFINE(ptys
, MLXSW_REG_PTYS_ID
, MLXSW_REG_PTYS_LEN
);
2691 /* reg_ptys_local_port
2692 * Local port number.
2695 MLXSW_ITEM32(reg
, ptys
, local_port
, 0x00, 16, 8);
2697 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0)
2698 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
2700 /* reg_ptys_proto_mask
2701 * Protocol mask. Indicates which protocol is used.
2703 * 1 - Fibre Channel.
2707 MLXSW_ITEM32(reg
, ptys
, proto_mask
, 0x00, 0, 3);
2710 MLXSW_REG_PTYS_AN_STATUS_NA
,
2711 MLXSW_REG_PTYS_AN_STATUS_OK
,
2712 MLXSW_REG_PTYS_AN_STATUS_FAIL
,
2715 /* reg_ptys_an_status
2716 * Autonegotiation status.
2719 MLXSW_ITEM32(reg
, ptys
, an_status
, 0x04, 28, 4);
2721 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
2722 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
2723 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
2724 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
2725 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
2726 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
2727 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
2728 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
2729 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
2730 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
2731 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
2732 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
2733 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
2734 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
2735 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
2736 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
2737 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
2738 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
2739 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
2740 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
2741 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
2742 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
2743 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
2744 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
2745 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
2746 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
2747 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
2748 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
2750 /* reg_ptys_eth_proto_cap
2751 * Ethernet port supported speeds and protocols.
2754 MLXSW_ITEM32(reg
, ptys
, eth_proto_cap
, 0x0C, 0, 32);
2756 /* reg_ptys_ib_link_width_cap
2757 * IB port supported widths.
2760 MLXSW_ITEM32(reg
, ptys
, ib_link_width_cap
, 0x10, 16, 16);
2762 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0)
2763 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1)
2764 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2)
2765 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3)
2766 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4)
2767 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5)
2769 /* reg_ptys_ib_proto_cap
2770 * IB port supported speeds and protocols.
2773 MLXSW_ITEM32(reg
, ptys
, ib_proto_cap
, 0x10, 0, 16);
2775 /* reg_ptys_eth_proto_admin
2776 * Speed and protocol to set port to.
2779 MLXSW_ITEM32(reg
, ptys
, eth_proto_admin
, 0x18, 0, 32);
2781 /* reg_ptys_ib_link_width_admin
2782 * IB width to set port to.
2785 MLXSW_ITEM32(reg
, ptys
, ib_link_width_admin
, 0x1C, 16, 16);
2787 /* reg_ptys_ib_proto_admin
2788 * IB speeds and protocols to set port to.
2791 MLXSW_ITEM32(reg
, ptys
, ib_proto_admin
, 0x1C, 0, 16);
2793 /* reg_ptys_eth_proto_oper
2794 * The current speed and protocol configured for the port.
2797 MLXSW_ITEM32(reg
, ptys
, eth_proto_oper
, 0x24, 0, 32);
2799 /* reg_ptys_ib_link_width_oper
2800 * The current IB width to set port to.
2803 MLXSW_ITEM32(reg
, ptys
, ib_link_width_oper
, 0x28, 16, 16);
2805 /* reg_ptys_ib_proto_oper
2806 * The current IB speed and protocol.
2809 MLXSW_ITEM32(reg
, ptys
, ib_proto_oper
, 0x28, 0, 16);
2811 /* reg_ptys_eth_proto_lp_advertise
2812 * The protocols that were advertised by the link partner during
2816 MLXSW_ITEM32(reg
, ptys
, eth_proto_lp_advertise
, 0x30, 0, 32);
2818 static inline void mlxsw_reg_ptys_eth_pack(char *payload
, u8 local_port
,
2821 MLXSW_REG_ZERO(ptys
, payload
);
2822 mlxsw_reg_ptys_local_port_set(payload
, local_port
);
2823 mlxsw_reg_ptys_proto_mask_set(payload
, MLXSW_REG_PTYS_PROTO_MASK_ETH
);
2824 mlxsw_reg_ptys_eth_proto_admin_set(payload
, proto_admin
);
2827 static inline void mlxsw_reg_ptys_eth_unpack(char *payload
,
2828 u32
*p_eth_proto_cap
,
2829 u32
*p_eth_proto_adm
,
2830 u32
*p_eth_proto_oper
)
2832 if (p_eth_proto_cap
)
2833 *p_eth_proto_cap
= mlxsw_reg_ptys_eth_proto_cap_get(payload
);
2834 if (p_eth_proto_adm
)
2835 *p_eth_proto_adm
= mlxsw_reg_ptys_eth_proto_admin_get(payload
);
2836 if (p_eth_proto_oper
)
2837 *p_eth_proto_oper
= mlxsw_reg_ptys_eth_proto_oper_get(payload
);
2840 static inline void mlxsw_reg_ptys_ib_pack(char *payload
, u8 local_port
,
2841 u16 proto_admin
, u16 link_width
)
2843 MLXSW_REG_ZERO(ptys
, payload
);
2844 mlxsw_reg_ptys_local_port_set(payload
, local_port
);
2845 mlxsw_reg_ptys_proto_mask_set(payload
, MLXSW_REG_PTYS_PROTO_MASK_IB
);
2846 mlxsw_reg_ptys_ib_proto_admin_set(payload
, proto_admin
);
2847 mlxsw_reg_ptys_ib_link_width_admin_set(payload
, link_width
);
2850 static inline void mlxsw_reg_ptys_ib_unpack(char *payload
, u16
*p_ib_proto_cap
,
2851 u16
*p_ib_link_width_cap
,
2852 u16
*p_ib_proto_oper
,
2853 u16
*p_ib_link_width_oper
)
2856 *p_ib_proto_cap
= mlxsw_reg_ptys_ib_proto_cap_get(payload
);
2857 if (p_ib_link_width_cap
)
2858 *p_ib_link_width_cap
=
2859 mlxsw_reg_ptys_ib_link_width_cap_get(payload
);
2860 if (p_ib_proto_oper
)
2861 *p_ib_proto_oper
= mlxsw_reg_ptys_ib_proto_oper_get(payload
);
2862 if (p_ib_link_width_oper
)
2863 *p_ib_link_width_oper
=
2864 mlxsw_reg_ptys_ib_link_width_oper_get(payload
);
2867 /* PPAD - Port Physical Address Register
2868 * -------------------------------------
2869 * The PPAD register configures the per port physical MAC address.
2871 #define MLXSW_REG_PPAD_ID 0x5005
2872 #define MLXSW_REG_PPAD_LEN 0x10
2874 MLXSW_REG_DEFINE(ppad
, MLXSW_REG_PPAD_ID
, MLXSW_REG_PPAD_LEN
);
2876 /* reg_ppad_single_base_mac
2877 * 0: base_mac, local port should be 0 and mac[7:0] is
2878 * reserved. HW will set incremental
2879 * 1: single_mac - mac of the local_port
2882 MLXSW_ITEM32(reg
, ppad
, single_base_mac
, 0x00, 28, 1);
2884 /* reg_ppad_local_port
2885 * port number, if single_base_mac = 0 then local_port is reserved
2888 MLXSW_ITEM32(reg
, ppad
, local_port
, 0x00, 16, 8);
2891 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
2892 * If single_base_mac = 1 - the per port MAC address
2895 MLXSW_ITEM_BUF(reg
, ppad
, mac
, 0x02, 6);
2897 static inline void mlxsw_reg_ppad_pack(char *payload
, bool single_base_mac
,
2900 MLXSW_REG_ZERO(ppad
, payload
);
2901 mlxsw_reg_ppad_single_base_mac_set(payload
, !!single_base_mac
);
2902 mlxsw_reg_ppad_local_port_set(payload
, local_port
);
2905 /* PAOS - Ports Administrative and Operational Status Register
2906 * -----------------------------------------------------------
2907 * Configures and retrieves per port administrative and operational status.
2909 #define MLXSW_REG_PAOS_ID 0x5006
2910 #define MLXSW_REG_PAOS_LEN 0x10
2912 MLXSW_REG_DEFINE(paos
, MLXSW_REG_PAOS_ID
, MLXSW_REG_PAOS_LEN
);
2915 * Switch partition ID with which to associate the port.
2916 * Note: while external ports uses unique local port numbers (and thus swid is
2917 * redundant), router ports use the same local port number where swid is the
2918 * only indication for the relevant port.
2921 MLXSW_ITEM32(reg
, paos
, swid
, 0x00, 24, 8);
2923 /* reg_paos_local_port
2924 * Local port number.
2927 MLXSW_ITEM32(reg
, paos
, local_port
, 0x00, 16, 8);
2929 /* reg_paos_admin_status
2930 * Port administrative state (the desired state of the port):
2933 * 3 - Up once. This means that in case of link failure, the port won't go
2934 * into polling mode, but will wait to be re-enabled by software.
2935 * 4 - Disabled by system. Can only be set by hardware.
2938 MLXSW_ITEM32(reg
, paos
, admin_status
, 0x00, 8, 4);
2940 /* reg_paos_oper_status
2941 * Port operational state (the current state):
2944 * 3 - Down by port failure. This means that the device will not let the
2945 * port up again until explicitly specified by software.
2948 MLXSW_ITEM32(reg
, paos
, oper_status
, 0x00, 0, 4);
2951 * Admin state update enabled.
2954 MLXSW_ITEM32(reg
, paos
, ase
, 0x04, 31, 1);
2957 * Event update enable. If this bit is set, event generation will be
2958 * updated based on the e field.
2961 MLXSW_ITEM32(reg
, paos
, ee
, 0x04, 30, 1);
2964 * Event generation on operational state change:
2965 * 0 - Do not generate event.
2966 * 1 - Generate Event.
2967 * 2 - Generate Single Event.
2970 MLXSW_ITEM32(reg
, paos
, e
, 0x04, 0, 2);
2972 static inline void mlxsw_reg_paos_pack(char *payload
, u8 local_port
,
2973 enum mlxsw_port_admin_status status
)
2975 MLXSW_REG_ZERO(paos
, payload
);
2976 mlxsw_reg_paos_swid_set(payload
, 0);
2977 mlxsw_reg_paos_local_port_set(payload
, local_port
);
2978 mlxsw_reg_paos_admin_status_set(payload
, status
);
2979 mlxsw_reg_paos_oper_status_set(payload
, 0);
2980 mlxsw_reg_paos_ase_set(payload
, 1);
2981 mlxsw_reg_paos_ee_set(payload
, 1);
2982 mlxsw_reg_paos_e_set(payload
, 1);
2985 /* PFCC - Ports Flow Control Configuration Register
2986 * ------------------------------------------------
2987 * Configures and retrieves the per port flow control configuration.
2989 #define MLXSW_REG_PFCC_ID 0x5007
2990 #define MLXSW_REG_PFCC_LEN 0x20
2992 MLXSW_REG_DEFINE(pfcc
, MLXSW_REG_PFCC_ID
, MLXSW_REG_PFCC_LEN
);
2994 /* reg_pfcc_local_port
2995 * Local port number.
2998 MLXSW_ITEM32(reg
, pfcc
, local_port
, 0x00, 16, 8);
3001 * Port number access type. Determines the way local_port is interpreted:
3002 * 0 - Local port number.
3003 * 1 - IB / label port number.
3006 MLXSW_ITEM32(reg
, pfcc
, pnat
, 0x00, 14, 2);
3009 * Send to higher layers capabilities:
3010 * 0 - No capability of sending Pause and PFC frames to higher layers.
3011 * 1 - Device has capability of sending Pause and PFC frames to higher
3015 MLXSW_ITEM32(reg
, pfcc
, shl_cap
, 0x00, 1, 1);
3018 * Send to higher layers operation:
3019 * 0 - Pause and PFC frames are handled by the port (default).
3020 * 1 - Pause and PFC frames are handled by the port and also sent to
3021 * higher layers. Only valid if shl_cap = 1.
3024 MLXSW_ITEM32(reg
, pfcc
, shl_opr
, 0x00, 0, 1);
3027 * Pause policy auto negotiation.
3028 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
3029 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
3030 * based on the auto-negotiation resolution.
3033 * Note: The auto-negotiation advertisement is set according to pptx and
3034 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
3036 MLXSW_ITEM32(reg
, pfcc
, ppan
, 0x04, 28, 4);
3038 /* reg_pfcc_prio_mask_tx
3039 * Bit per priority indicating if Tx flow control policy should be
3040 * updated based on bit pfctx.
3043 MLXSW_ITEM32(reg
, pfcc
, prio_mask_tx
, 0x04, 16, 8);
3045 /* reg_pfcc_prio_mask_rx
3046 * Bit per priority indicating if Rx flow control policy should be
3047 * updated based on bit pfcrx.
3050 MLXSW_ITEM32(reg
, pfcc
, prio_mask_rx
, 0x04, 0, 8);
3053 * Admin Pause policy on Tx.
3054 * 0 - Never generate Pause frames (default).
3055 * 1 - Generate Pause frames according to Rx buffer threshold.
3058 MLXSW_ITEM32(reg
, pfcc
, pptx
, 0x08, 31, 1);
3061 * Active (operational) Pause policy on Tx.
3062 * 0 - Never generate Pause frames.
3063 * 1 - Generate Pause frames according to Rx buffer threshold.
3066 MLXSW_ITEM32(reg
, pfcc
, aptx
, 0x08, 30, 1);
3069 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
3070 * 0 - Never generate priority Pause frames on the specified priority
3072 * 1 - Generate priority Pause frames according to Rx buffer threshold on
3073 * the specified priority.
3076 * Note: pfctx and pptx must be mutually exclusive.
3078 MLXSW_ITEM32(reg
, pfcc
, pfctx
, 0x08, 16, 8);
3081 * Admin Pause policy on Rx.
3082 * 0 - Ignore received Pause frames (default).
3083 * 1 - Respect received Pause frames.
3086 MLXSW_ITEM32(reg
, pfcc
, pprx
, 0x0C, 31, 1);
3089 * Active (operational) Pause policy on Rx.
3090 * 0 - Ignore received Pause frames.
3091 * 1 - Respect received Pause frames.
3094 MLXSW_ITEM32(reg
, pfcc
, aprx
, 0x0C, 30, 1);
3097 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
3098 * 0 - Ignore incoming priority Pause frames on the specified priority
3100 * 1 - Respect incoming priority Pause frames on the specified priority.
3103 MLXSW_ITEM32(reg
, pfcc
, pfcrx
, 0x0C, 16, 8);
3105 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
3107 static inline void mlxsw_reg_pfcc_prio_pack(char *payload
, u8 pfc_en
)
3109 mlxsw_reg_pfcc_prio_mask_tx_set(payload
, MLXSW_REG_PFCC_ALL_PRIO
);
3110 mlxsw_reg_pfcc_prio_mask_rx_set(payload
, MLXSW_REG_PFCC_ALL_PRIO
);
3111 mlxsw_reg_pfcc_pfctx_set(payload
, pfc_en
);
3112 mlxsw_reg_pfcc_pfcrx_set(payload
, pfc_en
);
3115 static inline void mlxsw_reg_pfcc_pack(char *payload
, u8 local_port
)
3117 MLXSW_REG_ZERO(pfcc
, payload
);
3118 mlxsw_reg_pfcc_local_port_set(payload
, local_port
);
3121 /* PPCNT - Ports Performance Counters Register
3122 * -------------------------------------------
3123 * The PPCNT register retrieves per port performance counters.
3125 #define MLXSW_REG_PPCNT_ID 0x5008
3126 #define MLXSW_REG_PPCNT_LEN 0x100
3128 MLXSW_REG_DEFINE(ppcnt
, MLXSW_REG_PPCNT_ID
, MLXSW_REG_PPCNT_LEN
);
3131 * For HCA: must be always 0.
3132 * Switch partition ID to associate port with.
3133 * Switch partitions are numbered from 0 to 7 inclusively.
3134 * Switch partition 254 indicates stacking ports.
3135 * Switch partition 255 indicates all switch partitions.
3136 * Only valid on Set() operation with local_port=255.
3139 MLXSW_ITEM32(reg
, ppcnt
, swid
, 0x00, 24, 8);
3141 /* reg_ppcnt_local_port
3142 * Local port number.
3143 * 255 indicates all ports on the device, and is only allowed
3144 * for Set() operation.
3147 MLXSW_ITEM32(reg
, ppcnt
, local_port
, 0x00, 16, 8);
3150 * Port number access type:
3151 * 0 - Local port number
3152 * 1 - IB port number
3155 MLXSW_ITEM32(reg
, ppcnt
, pnat
, 0x00, 14, 2);
3157 enum mlxsw_reg_ppcnt_grp
{
3158 MLXSW_REG_PPCNT_IEEE_8023_CNT
= 0x0,
3159 MLXSW_REG_PPCNT_PRIO_CNT
= 0x10,
3160 MLXSW_REG_PPCNT_TC_CNT
= 0x11,
3164 * Performance counter group.
3165 * Group 63 indicates all groups. Only valid on Set() operation with
3167 * 0x0: IEEE 802.3 Counters
3168 * 0x1: RFC 2863 Counters
3169 * 0x2: RFC 2819 Counters
3170 * 0x3: RFC 3635 Counters
3171 * 0x5: Ethernet Extended Counters
3172 * 0x8: Link Level Retransmission Counters
3173 * 0x10: Per Priority Counters
3174 * 0x11: Per Traffic Class Counters
3175 * 0x12: Physical Layer Counters
3178 MLXSW_ITEM32(reg
, ppcnt
, grp
, 0x00, 0, 6);
3181 * Clear counters. Setting the clr bit will reset the counter value
3182 * for all counters in the counter group. This bit can be set
3183 * for both Set() and Get() operation.
3186 MLXSW_ITEM32(reg
, ppcnt
, clr
, 0x04, 31, 1);
3188 /* reg_ppcnt_prio_tc
3189 * Priority for counter set that support per priority, valid values: 0-7.
3190 * Traffic class for counter set that support per traffic class,
3191 * valid values: 0- cap_max_tclass-1 .
3192 * For HCA: cap_max_tclass is always 8.
3193 * Otherwise must be 0.
3196 MLXSW_ITEM32(reg
, ppcnt
, prio_tc
, 0x04, 0, 5);
3198 /* Ethernet IEEE 802.3 Counter Group */
3200 /* reg_ppcnt_a_frames_transmitted_ok
3203 MLXSW_ITEM64(reg
, ppcnt
, a_frames_transmitted_ok
,
3204 0x08 + 0x00, 0, 64);
3206 /* reg_ppcnt_a_frames_received_ok
3209 MLXSW_ITEM64(reg
, ppcnt
, a_frames_received_ok
,
3210 0x08 + 0x08, 0, 64);
3212 /* reg_ppcnt_a_frame_check_sequence_errors
3215 MLXSW_ITEM64(reg
, ppcnt
, a_frame_check_sequence_errors
,
3216 0x08 + 0x10, 0, 64);
3218 /* reg_ppcnt_a_alignment_errors
3221 MLXSW_ITEM64(reg
, ppcnt
, a_alignment_errors
,
3222 0x08 + 0x18, 0, 64);
3224 /* reg_ppcnt_a_octets_transmitted_ok
3227 MLXSW_ITEM64(reg
, ppcnt
, a_octets_transmitted_ok
,
3228 0x08 + 0x20, 0, 64);
3230 /* reg_ppcnt_a_octets_received_ok
3233 MLXSW_ITEM64(reg
, ppcnt
, a_octets_received_ok
,
3234 0x08 + 0x28, 0, 64);
3236 /* reg_ppcnt_a_multicast_frames_xmitted_ok
3239 MLXSW_ITEM64(reg
, ppcnt
, a_multicast_frames_xmitted_ok
,
3240 0x08 + 0x30, 0, 64);
3242 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
3245 MLXSW_ITEM64(reg
, ppcnt
, a_broadcast_frames_xmitted_ok
,
3246 0x08 + 0x38, 0, 64);
3248 /* reg_ppcnt_a_multicast_frames_received_ok
3251 MLXSW_ITEM64(reg
, ppcnt
, a_multicast_frames_received_ok
,
3252 0x08 + 0x40, 0, 64);
3254 /* reg_ppcnt_a_broadcast_frames_received_ok
3257 MLXSW_ITEM64(reg
, ppcnt
, a_broadcast_frames_received_ok
,
3258 0x08 + 0x48, 0, 64);
3260 /* reg_ppcnt_a_in_range_length_errors
3263 MLXSW_ITEM64(reg
, ppcnt
, a_in_range_length_errors
,
3264 0x08 + 0x50, 0, 64);
3266 /* reg_ppcnt_a_out_of_range_length_field
3269 MLXSW_ITEM64(reg
, ppcnt
, a_out_of_range_length_field
,
3270 0x08 + 0x58, 0, 64);
3272 /* reg_ppcnt_a_frame_too_long_errors
3275 MLXSW_ITEM64(reg
, ppcnt
, a_frame_too_long_errors
,
3276 0x08 + 0x60, 0, 64);
3278 /* reg_ppcnt_a_symbol_error_during_carrier
3281 MLXSW_ITEM64(reg
, ppcnt
, a_symbol_error_during_carrier
,
3282 0x08 + 0x68, 0, 64);
3284 /* reg_ppcnt_a_mac_control_frames_transmitted
3287 MLXSW_ITEM64(reg
, ppcnt
, a_mac_control_frames_transmitted
,
3288 0x08 + 0x70, 0, 64);
3290 /* reg_ppcnt_a_mac_control_frames_received
3293 MLXSW_ITEM64(reg
, ppcnt
, a_mac_control_frames_received
,
3294 0x08 + 0x78, 0, 64);
3296 /* reg_ppcnt_a_unsupported_opcodes_received
3299 MLXSW_ITEM64(reg
, ppcnt
, a_unsupported_opcodes_received
,
3300 0x08 + 0x80, 0, 64);
3302 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
3305 MLXSW_ITEM64(reg
, ppcnt
, a_pause_mac_ctrl_frames_received
,
3306 0x08 + 0x88, 0, 64);
3308 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
3311 MLXSW_ITEM64(reg
, ppcnt
, a_pause_mac_ctrl_frames_transmitted
,
3312 0x08 + 0x90, 0, 64);
3314 /* Ethernet Per Priority Group Counters */
3316 /* reg_ppcnt_rx_octets
3319 MLXSW_ITEM64(reg
, ppcnt
, rx_octets
, 0x08 + 0x00, 0, 64);
3321 /* reg_ppcnt_rx_frames
3324 MLXSW_ITEM64(reg
, ppcnt
, rx_frames
, 0x08 + 0x20, 0, 64);
3326 /* reg_ppcnt_tx_octets
3329 MLXSW_ITEM64(reg
, ppcnt
, tx_octets
, 0x08 + 0x28, 0, 64);
3331 /* reg_ppcnt_tx_frames
3334 MLXSW_ITEM64(reg
, ppcnt
, tx_frames
, 0x08 + 0x48, 0, 64);
3336 /* reg_ppcnt_rx_pause
3339 MLXSW_ITEM64(reg
, ppcnt
, rx_pause
, 0x08 + 0x50, 0, 64);
3341 /* reg_ppcnt_rx_pause_duration
3344 MLXSW_ITEM64(reg
, ppcnt
, rx_pause_duration
, 0x08 + 0x58, 0, 64);
3346 /* reg_ppcnt_tx_pause
3349 MLXSW_ITEM64(reg
, ppcnt
, tx_pause
, 0x08 + 0x60, 0, 64);
3351 /* reg_ppcnt_tx_pause_duration
3354 MLXSW_ITEM64(reg
, ppcnt
, tx_pause_duration
, 0x08 + 0x68, 0, 64);
3356 /* reg_ppcnt_rx_pause_transition
3359 MLXSW_ITEM64(reg
, ppcnt
, tx_pause_transition
, 0x08 + 0x70, 0, 64);
3361 /* Ethernet Per Traffic Group Counters */
3363 /* reg_ppcnt_tc_transmit_queue
3364 * Contains the transmit queue depth in cells of traffic class
3365 * selected by prio_tc and the port selected by local_port.
3366 * The field cannot be cleared.
3369 MLXSW_ITEM64(reg
, ppcnt
, tc_transmit_queue
, 0x08 + 0x00, 0, 64);
3371 /* reg_ppcnt_tc_no_buffer_discard_uc
3372 * The number of unicast packets dropped due to lack of shared
3376 MLXSW_ITEM64(reg
, ppcnt
, tc_no_buffer_discard_uc
, 0x08 + 0x08, 0, 64);
3378 static inline void mlxsw_reg_ppcnt_pack(char *payload
, u8 local_port
,
3379 enum mlxsw_reg_ppcnt_grp grp
,
3382 MLXSW_REG_ZERO(ppcnt
, payload
);
3383 mlxsw_reg_ppcnt_swid_set(payload
, 0);
3384 mlxsw_reg_ppcnt_local_port_set(payload
, local_port
);
3385 mlxsw_reg_ppcnt_pnat_set(payload
, 0);
3386 mlxsw_reg_ppcnt_grp_set(payload
, grp
);
3387 mlxsw_reg_ppcnt_clr_set(payload
, 0);
3388 mlxsw_reg_ppcnt_prio_tc_set(payload
, prio_tc
);
3391 /* PLIB - Port Local to InfiniBand Port
3392 * ------------------------------------
3393 * The PLIB register performs mapping from Local Port into InfiniBand Port.
3395 #define MLXSW_REG_PLIB_ID 0x500A
3396 #define MLXSW_REG_PLIB_LEN 0x10
3398 MLXSW_REG_DEFINE(plib
, MLXSW_REG_PLIB_ID
, MLXSW_REG_PLIB_LEN
);
3400 /* reg_plib_local_port
3401 * Local port number.
3404 MLXSW_ITEM32(reg
, plib
, local_port
, 0x00, 16, 8);
3407 * InfiniBand port remapping for local_port.
3410 MLXSW_ITEM32(reg
, plib
, ib_port
, 0x00, 0, 8);
3412 /* PPTB - Port Prio To Buffer Register
3413 * -----------------------------------
3414 * Configures the switch priority to buffer table.
3416 #define MLXSW_REG_PPTB_ID 0x500B
3417 #define MLXSW_REG_PPTB_LEN 0x10
3419 MLXSW_REG_DEFINE(pptb
, MLXSW_REG_PPTB_ID
, MLXSW_REG_PPTB_LEN
);
3422 MLXSW_REG_PPTB_MM_UM
,
3423 MLXSW_REG_PPTB_MM_UNICAST
,
3424 MLXSW_REG_PPTB_MM_MULTICAST
,
3429 * 0 - Map both unicast and multicast packets to the same buffer.
3430 * 1 - Map only unicast packets.
3431 * 2 - Map only multicast packets.
3434 * Note: SwitchX-2 only supports the first option.
3436 MLXSW_ITEM32(reg
, pptb
, mm
, 0x00, 28, 2);
3438 /* reg_pptb_local_port
3439 * Local port number.
3442 MLXSW_ITEM32(reg
, pptb
, local_port
, 0x00, 16, 8);
3445 * Enables the update of the untagged_buf field.
3448 MLXSW_ITEM32(reg
, pptb
, um
, 0x00, 8, 1);
3451 * Enables the update of the prio_to_buff field.
3452 * Bit <i> is a flag for updating the mapping for switch priority <i>.
3455 MLXSW_ITEM32(reg
, pptb
, pm
, 0x00, 0, 8);
3457 /* reg_pptb_prio_to_buff
3458 * Mapping of switch priority <i> to one of the allocated receive port
3462 MLXSW_ITEM_BIT_ARRAY(reg
, pptb
, prio_to_buff
, 0x04, 0x04, 4);
3465 * Enables the update of the prio_to_buff field.
3466 * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
3469 MLXSW_ITEM32(reg
, pptb
, pm_msb
, 0x08, 24, 8);
3471 /* reg_pptb_untagged_buff
3472 * Mapping of untagged frames to one of the allocated receive port buffers.
3475 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
3476 * Spectrum, as it maps untagged packets based on the default switch priority.
3478 MLXSW_ITEM32(reg
, pptb
, untagged_buff
, 0x08, 0, 4);
3480 /* reg_pptb_prio_to_buff_msb
3481 * Mapping of switch priority <i+8> to one of the allocated receive port
3485 MLXSW_ITEM_BIT_ARRAY(reg
, pptb
, prio_to_buff_msb
, 0x0C, 0x04, 4);
3487 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
3489 static inline void mlxsw_reg_pptb_pack(char *payload
, u8 local_port
)
3491 MLXSW_REG_ZERO(pptb
, payload
);
3492 mlxsw_reg_pptb_mm_set(payload
, MLXSW_REG_PPTB_MM_UM
);
3493 mlxsw_reg_pptb_local_port_set(payload
, local_port
);
3494 mlxsw_reg_pptb_pm_set(payload
, MLXSW_REG_PPTB_ALL_PRIO
);
3495 mlxsw_reg_pptb_pm_msb_set(payload
, MLXSW_REG_PPTB_ALL_PRIO
);
3498 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload
, u8 prio
,
3501 mlxsw_reg_pptb_prio_to_buff_set(payload
, prio
, buff
);
3502 mlxsw_reg_pptb_prio_to_buff_msb_set(payload
, prio
, buff
);
3505 /* PBMC - Port Buffer Management Control Register
3506 * ----------------------------------------------
3507 * The PBMC register configures and retrieves the port packet buffer
3508 * allocation for different Prios, and the Pause threshold management.
3510 #define MLXSW_REG_PBMC_ID 0x500C
3511 #define MLXSW_REG_PBMC_LEN 0x6C
3513 MLXSW_REG_DEFINE(pbmc
, MLXSW_REG_PBMC_ID
, MLXSW_REG_PBMC_LEN
);
3515 /* reg_pbmc_local_port
3516 * Local port number.
3519 MLXSW_ITEM32(reg
, pbmc
, local_port
, 0x00, 16, 8);
3521 /* reg_pbmc_xoff_timer_value
3522 * When device generates a pause frame, it uses this value as the pause
3523 * timer (time for the peer port to pause in quota-512 bit time).
3526 MLXSW_ITEM32(reg
, pbmc
, xoff_timer_value
, 0x04, 16, 16);
3528 /* reg_pbmc_xoff_refresh
3529 * The time before a new pause frame should be sent to refresh the pause RW
3530 * state. Using the same units as xoff_timer_value above (in quota-512 bit
3534 MLXSW_ITEM32(reg
, pbmc
, xoff_refresh
, 0x04, 0, 16);
3536 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
3538 /* reg_pbmc_buf_lossy
3539 * The field indicates if the buffer is lossy.
3544 MLXSW_ITEM32_INDEXED(reg
, pbmc
, buf_lossy
, 0x0C, 25, 1, 0x08, 0x00, false);
3546 /* reg_pbmc_buf_epsb
3547 * Eligible for Port Shared buffer.
3548 * If epsb is set, packets assigned to buffer are allowed to insert the port
3550 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
3553 MLXSW_ITEM32_INDEXED(reg
, pbmc
, buf_epsb
, 0x0C, 24, 1, 0x08, 0x00, false);
3555 /* reg_pbmc_buf_size
3556 * The part of the packet buffer array is allocated for the specific buffer.
3557 * Units are represented in cells.
3560 MLXSW_ITEM32_INDEXED(reg
, pbmc
, buf_size
, 0x0C, 0, 16, 0x08, 0x00, false);
3562 /* reg_pbmc_buf_xoff_threshold
3563 * Once the amount of data in the buffer goes above this value, device
3564 * starts sending PFC frames for all priorities associated with the
3565 * buffer. Units are represented in cells. Reserved in case of lossy
3569 * Note: In Spectrum, reserved for buffer[9].
3571 MLXSW_ITEM32_INDEXED(reg
, pbmc
, buf_xoff_threshold
, 0x0C, 16, 16,
3574 /* reg_pbmc_buf_xon_threshold
3575 * When the amount of data in the buffer goes below this value, device
3576 * stops sending PFC frames for the priorities associated with the
3577 * buffer. Units are represented in cells. Reserved in case of lossy
3581 * Note: In Spectrum, reserved for buffer[9].
3583 MLXSW_ITEM32_INDEXED(reg
, pbmc
, buf_xon_threshold
, 0x0C, 0, 16,
3586 static inline void mlxsw_reg_pbmc_pack(char *payload
, u8 local_port
,
3587 u16 xoff_timer_value
, u16 xoff_refresh
)
3589 MLXSW_REG_ZERO(pbmc
, payload
);
3590 mlxsw_reg_pbmc_local_port_set(payload
, local_port
);
3591 mlxsw_reg_pbmc_xoff_timer_value_set(payload
, xoff_timer_value
);
3592 mlxsw_reg_pbmc_xoff_refresh_set(payload
, xoff_refresh
);
3595 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload
,
3599 mlxsw_reg_pbmc_buf_lossy_set(payload
, buf_index
, 1);
3600 mlxsw_reg_pbmc_buf_epsb_set(payload
, buf_index
, 0);
3601 mlxsw_reg_pbmc_buf_size_set(payload
, buf_index
, size
);
3604 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload
,
3605 int buf_index
, u16 size
,
3608 mlxsw_reg_pbmc_buf_lossy_set(payload
, buf_index
, 0);
3609 mlxsw_reg_pbmc_buf_epsb_set(payload
, buf_index
, 0);
3610 mlxsw_reg_pbmc_buf_size_set(payload
, buf_index
, size
);
3611 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload
, buf_index
, threshold
);
3612 mlxsw_reg_pbmc_buf_xon_threshold_set(payload
, buf_index
, threshold
);
3615 /* PSPA - Port Switch Partition Allocation
3616 * ---------------------------------------
3617 * Controls the association of a port with a switch partition and enables
3618 * configuring ports as stacking ports.
3620 #define MLXSW_REG_PSPA_ID 0x500D
3621 #define MLXSW_REG_PSPA_LEN 0x8
3623 MLXSW_REG_DEFINE(pspa
, MLXSW_REG_PSPA_ID
, MLXSW_REG_PSPA_LEN
);
3626 * Switch partition ID.
3629 MLXSW_ITEM32(reg
, pspa
, swid
, 0x00, 24, 8);
3631 /* reg_pspa_local_port
3632 * Local port number.
3635 MLXSW_ITEM32(reg
, pspa
, local_port
, 0x00, 16, 8);
3637 /* reg_pspa_sub_port
3638 * Virtual port within the local port. Set to 0 when virtual ports are
3639 * disabled on the local port.
3642 MLXSW_ITEM32(reg
, pspa
, sub_port
, 0x00, 8, 8);
3644 static inline void mlxsw_reg_pspa_pack(char *payload
, u8 swid
, u8 local_port
)
3646 MLXSW_REG_ZERO(pspa
, payload
);
3647 mlxsw_reg_pspa_swid_set(payload
, swid
);
3648 mlxsw_reg_pspa_local_port_set(payload
, local_port
);
3649 mlxsw_reg_pspa_sub_port_set(payload
, 0);
3652 /* HTGT - Host Trap Group Table
3653 * ----------------------------
3654 * Configures the properties for forwarding to CPU.
3656 #define MLXSW_REG_HTGT_ID 0x7002
3657 #define MLXSW_REG_HTGT_LEN 0x20
3659 MLXSW_REG_DEFINE(htgt
, MLXSW_REG_HTGT_ID
, MLXSW_REG_HTGT_LEN
);
3662 * Switch partition ID.
3665 MLXSW_ITEM32(reg
, htgt
, swid
, 0x00, 24, 8);
3667 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
3673 MLXSW_ITEM32(reg
, htgt
, type
, 0x00, 8, 4);
3675 enum mlxsw_reg_htgt_trap_group
{
3676 MLXSW_REG_HTGT_TRAP_GROUP_EMAD
,
3677 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX
,
3678 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL
,
3679 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP
,
3680 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP
,
3681 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP
,
3682 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP
,
3683 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP
,
3684 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF
,
3685 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP
,
3686 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS
,
3687 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP
,
3688 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE
,
3689 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME
,
3690 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP
,
3691 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT
,
3692 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD
,
3693 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND
,
3696 /* reg_htgt_trap_group
3697 * Trap group number. User defined number specifying which trap groups
3698 * should be forwarded to the CPU. The mapping between trap IDs and trap
3699 * groups is configured using HPKT register.
3702 MLXSW_ITEM32(reg
, htgt
, trap_group
, 0x00, 0, 8);
3705 MLXSW_REG_HTGT_POLICER_DISABLE
,
3706 MLXSW_REG_HTGT_POLICER_ENABLE
,
3710 * Enable policer ID specified using 'pid' field.
3713 MLXSW_ITEM32(reg
, htgt
, pide
, 0x04, 15, 1);
3715 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff
3718 * Policer ID for the trap group.
3721 MLXSW_ITEM32(reg
, htgt
, pid
, 0x04, 0, 8);
3723 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
3725 /* reg_htgt_mirror_action
3726 * Mirror action to use.
3728 * 1 - Trap to CPU and mirror to a mirroring agent.
3729 * 2 - Mirror to a mirroring agent and do not trap to CPU.
3732 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
3734 MLXSW_ITEM32(reg
, htgt
, mirror_action
, 0x08, 8, 2);
3736 /* reg_htgt_mirroring_agent
3740 MLXSW_ITEM32(reg
, htgt
, mirroring_agent
, 0x08, 0, 3);
3742 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
3744 /* reg_htgt_priority
3745 * Trap group priority.
3746 * In case a packet matches multiple classification rules, the packet will
3747 * only be trapped once, based on the trap ID associated with the group (via
3748 * register HPKT) with the highest priority.
3749 * Supported values are 0-7, with 7 represnting the highest priority.
3752 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
3753 * by the 'trap_group' field.
3755 MLXSW_ITEM32(reg
, htgt
, priority
, 0x0C, 0, 4);
3757 #define MLXSW_REG_HTGT_DEFAULT_TC 7
3759 /* reg_htgt_local_path_cpu_tclass
3760 * CPU ingress traffic class for the trap group.
3763 MLXSW_ITEM32(reg
, htgt
, local_path_cpu_tclass
, 0x10, 16, 6);
3765 enum mlxsw_reg_htgt_local_path_rdq
{
3766 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL
= 0x13,
3767 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX
= 0x14,
3768 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD
= 0x15,
3769 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD
= 0x15,
3771 /* reg_htgt_local_path_rdq
3772 * Receive descriptor queue (RDQ) to use for the trap group.
3775 MLXSW_ITEM32(reg
, htgt
, local_path_rdq
, 0x10, 0, 6);
3777 static inline void mlxsw_reg_htgt_pack(char *payload
, u8 group
, u8 policer_id
,
3780 MLXSW_REG_ZERO(htgt
, payload
);
3782 if (policer_id
== MLXSW_REG_HTGT_INVALID_POLICER
) {
3783 mlxsw_reg_htgt_pide_set(payload
,
3784 MLXSW_REG_HTGT_POLICER_DISABLE
);
3786 mlxsw_reg_htgt_pide_set(payload
,
3787 MLXSW_REG_HTGT_POLICER_ENABLE
);
3788 mlxsw_reg_htgt_pid_set(payload
, policer_id
);
3791 mlxsw_reg_htgt_type_set(payload
, MLXSW_REG_HTGT_PATH_TYPE_LOCAL
);
3792 mlxsw_reg_htgt_trap_group_set(payload
, group
);
3793 mlxsw_reg_htgt_mirror_action_set(payload
, MLXSW_REG_HTGT_TRAP_TO_CPU
);
3794 mlxsw_reg_htgt_mirroring_agent_set(payload
, 0);
3795 mlxsw_reg_htgt_priority_set(payload
, priority
);
3796 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload
, tc
);
3797 mlxsw_reg_htgt_local_path_rdq_set(payload
, group
);
3800 /* HPKT - Host Packet Trap
3801 * -----------------------
3802 * Configures trap IDs inside trap groups.
3804 #define MLXSW_REG_HPKT_ID 0x7003
3805 #define MLXSW_REG_HPKT_LEN 0x10
3807 MLXSW_REG_DEFINE(hpkt
, MLXSW_REG_HPKT_ID
, MLXSW_REG_HPKT_LEN
);
3810 MLXSW_REG_HPKT_ACK_NOT_REQUIRED
,
3811 MLXSW_REG_HPKT_ACK_REQUIRED
,
3815 * Require acknowledgements from the host for events.
3816 * If set, then the device will wait for the event it sent to be acknowledged
3817 * by the host. This option is only relevant for event trap IDs.
3820 * Note: Currently not supported by firmware.
3822 MLXSW_ITEM32(reg
, hpkt
, ack
, 0x00, 24, 1);
3824 enum mlxsw_reg_hpkt_action
{
3825 MLXSW_REG_HPKT_ACTION_FORWARD
,
3826 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU
,
3827 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU
,
3828 MLXSW_REG_HPKT_ACTION_DISCARD
,
3829 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD
,
3830 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD
,
3834 * Action to perform on packet when trapped.
3835 * 0 - No action. Forward to CPU based on switching rules.
3836 * 1 - Trap to CPU (CPU receives sole copy).
3837 * 2 - Mirror to CPU (CPU receives a replica of the packet).
3839 * 4 - Soft discard (allow other traps to act on the packet).
3840 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
3843 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
3844 * addressed to the CPU.
3846 MLXSW_ITEM32(reg
, hpkt
, action
, 0x00, 20, 3);
3848 /* reg_hpkt_trap_group
3849 * Trap group to associate the trap with.
3852 MLXSW_ITEM32(reg
, hpkt
, trap_group
, 0x00, 12, 6);
3858 * Note: A trap ID can only be associated with a single trap group. The device
3859 * will associate the trap ID with the last trap group configured.
3861 MLXSW_ITEM32(reg
, hpkt
, trap_id
, 0x00, 0, 9);
3864 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT
,
3865 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER
,
3866 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER
,
3870 * Configure dedicated buffer resources for control packets.
3871 * Ignored by SwitchX-2.
3872 * 0 - Keep factory defaults.
3873 * 1 - Do not use control buffer for this trap ID.
3874 * 2 - Use control buffer for this trap ID.
3877 MLXSW_ITEM32(reg
, hpkt
, ctrl
, 0x04, 16, 2);
3879 static inline void mlxsw_reg_hpkt_pack(char *payload
, u8 action
, u16 trap_id
,
3880 enum mlxsw_reg_htgt_trap_group trap_group
,
3883 MLXSW_REG_ZERO(hpkt
, payload
);
3884 mlxsw_reg_hpkt_ack_set(payload
, MLXSW_REG_HPKT_ACK_NOT_REQUIRED
);
3885 mlxsw_reg_hpkt_action_set(payload
, action
);
3886 mlxsw_reg_hpkt_trap_group_set(payload
, trap_group
);
3887 mlxsw_reg_hpkt_trap_id_set(payload
, trap_id
);
3888 mlxsw_reg_hpkt_ctrl_set(payload
, is_ctrl
?
3889 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER
:
3890 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER
);
3893 /* RGCR - Router General Configuration Register
3894 * --------------------------------------------
3895 * The register is used for setting up the router configuration.
3897 #define MLXSW_REG_RGCR_ID 0x8001
3898 #define MLXSW_REG_RGCR_LEN 0x28
3900 MLXSW_REG_DEFINE(rgcr
, MLXSW_REG_RGCR_ID
, MLXSW_REG_RGCR_LEN
);
3903 * IPv4 router enable.
3906 MLXSW_ITEM32(reg
, rgcr
, ipv4_en
, 0x00, 31, 1);
3909 * IPv6 router enable.
3912 MLXSW_ITEM32(reg
, rgcr
, ipv6_en
, 0x00, 30, 1);
3914 /* reg_rgcr_max_router_interfaces
3915 * Defines the maximum number of active router interfaces for all virtual
3919 MLXSW_ITEM32(reg
, rgcr
, max_router_interfaces
, 0x10, 0, 16);
3922 * Update switch priority and packet color.
3923 * 0 - Preserve the value of Switch Priority and packet color.
3924 * 1 - Recalculate the value of Switch Priority and packet color.
3927 * Note: Not supported by SwitchX and SwitchX-2.
3929 MLXSW_ITEM32(reg
, rgcr
, usp
, 0x18, 20, 1);
3932 * Indicates how to handle the pcp_rewrite_en value:
3933 * 0 - Preserve the value of pcp_rewrite_en.
3934 * 2 - Disable PCP rewrite.
3935 * 3 - Enable PCP rewrite.
3938 * Note: Not supported by SwitchX and SwitchX-2.
3940 MLXSW_ITEM32(reg
, rgcr
, pcp_rw
, 0x18, 16, 2);
3942 /* reg_rgcr_activity_dis
3944 * 0 - Activity will be set when an entry is hit (default).
3945 * 1 - Activity will not be set when an entry is hit.
3947 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
3949 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
3951 * Bits 2:7 are reserved.
3954 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
3956 MLXSW_ITEM32(reg
, rgcr
, activity_dis
, 0x20, 0, 8);
3958 static inline void mlxsw_reg_rgcr_pack(char *payload
, bool ipv4_en
,
3961 MLXSW_REG_ZERO(rgcr
, payload
);
3962 mlxsw_reg_rgcr_ipv4_en_set(payload
, ipv4_en
);
3963 mlxsw_reg_rgcr_ipv6_en_set(payload
, ipv6_en
);
3966 /* RITR - Router Interface Table Register
3967 * --------------------------------------
3968 * The register is used to configure the router interface table.
3970 #define MLXSW_REG_RITR_ID 0x8002
3971 #define MLXSW_REG_RITR_LEN 0x40
3973 MLXSW_REG_DEFINE(ritr
, MLXSW_REG_RITR_ID
, MLXSW_REG_RITR_LEN
);
3976 * Enables routing on the router interface.
3979 MLXSW_ITEM32(reg
, ritr
, enable
, 0x00, 31, 1);
3982 * IPv4 routing enable. Enables routing of IPv4 traffic on the router
3986 MLXSW_ITEM32(reg
, ritr
, ipv4
, 0x00, 29, 1);
3989 * IPv6 routing enable. Enables routing of IPv6 traffic on the router
3993 MLXSW_ITEM32(reg
, ritr
, ipv6
, 0x00, 28, 1);
3995 enum mlxsw_reg_ritr_if_type
{
3996 /* VLAN interface. */
3997 MLXSW_REG_RITR_VLAN_IF
,
3998 /* FID interface. */
3999 MLXSW_REG_RITR_FID_IF
,
4000 /* Sub-port interface. */
4001 MLXSW_REG_RITR_SP_IF
,
4002 /* Loopback Interface. */
4003 MLXSW_REG_RITR_LOOPBACK_IF
,
4007 * Router interface type as per enum mlxsw_reg_ritr_if_type.
4010 MLXSW_ITEM32(reg
, ritr
, type
, 0x00, 23, 3);
4013 MLXSW_REG_RITR_RIF_CREATE
,
4014 MLXSW_REG_RITR_RIF_DEL
,
4019 * 0 - Create or edit RIF.
4021 * Reserved for SwitchX-2. For Spectrum, editing of interface properties
4022 * is not supported. An interface must be deleted and re-created in order
4023 * to update properties.
4026 MLXSW_ITEM32(reg
, ritr
, op
, 0x00, 20, 2);
4029 * Router interface index. A pointer to the Router Interface Table.
4032 MLXSW_ITEM32(reg
, ritr
, rif
, 0x00, 0, 16);
4035 * IPv4 Forwarding Enable.
4036 * Enables routing of IPv4 traffic on the router interface. When disabled,
4037 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
4038 * Not supported in SwitchX-2.
4041 MLXSW_ITEM32(reg
, ritr
, ipv4_fe
, 0x04, 29, 1);
4044 * IPv6 Forwarding Enable.
4045 * Enables routing of IPv6 traffic on the router interface. When disabled,
4046 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
4047 * Not supported in SwitchX-2.
4050 MLXSW_ITEM32(reg
, ritr
, ipv6_fe
, 0x04, 28, 1);
4053 * Loop-back filter enable for unicast packets.
4054 * If the flag is set then loop-back filter for unicast packets is
4055 * implemented on the RIF. Multicast packets are always subject to
4056 * loop-back filtering.
4059 MLXSW_ITEM32(reg
, ritr
, lb_en
, 0x04, 24, 1);
4061 /* reg_ritr_virtual_router
4062 * Virtual router ID associated with the router interface.
4065 MLXSW_ITEM32(reg
, ritr
, virtual_router
, 0x04, 0, 16);
4068 * Router interface MTU.
4071 MLXSW_ITEM32(reg
, ritr
, mtu
, 0x34, 0, 16);
4074 * Switch partition ID.
4077 MLXSW_ITEM32(reg
, ritr
, if_swid
, 0x08, 24, 8);
4080 * Router interface MAC address.
4081 * In Spectrum, all MAC addresses must have the same 38 MSBits.
4084 MLXSW_ITEM_BUF(reg
, ritr
, if_mac
, 0x12, 6);
4086 /* VLAN Interface */
4088 /* reg_ritr_vlan_if_vid
4092 MLXSW_ITEM32(reg
, ritr
, vlan_if_vid
, 0x08, 0, 12);
4096 /* reg_ritr_fid_if_fid
4097 * Filtering ID. Used to connect a bridge to the router. Only FIDs from
4098 * the vFID range are supported.
4101 MLXSW_ITEM32(reg
, ritr
, fid_if_fid
, 0x08, 0, 16);
4103 static inline void mlxsw_reg_ritr_fid_set(char *payload
,
4104 enum mlxsw_reg_ritr_if_type rif_type
,
4107 if (rif_type
== MLXSW_REG_RITR_FID_IF
)
4108 mlxsw_reg_ritr_fid_if_fid_set(payload
, fid
);
4110 mlxsw_reg_ritr_vlan_if_vid_set(payload
, fid
);
4113 /* Sub-port Interface */
4115 /* reg_ritr_sp_if_lag
4116 * LAG indication. When this bit is set the system_port field holds the
4120 MLXSW_ITEM32(reg
, ritr
, sp_if_lag
, 0x08, 24, 1);
4122 /* reg_ritr_sp_system_port
4123 * Port unique indentifier. When lag bit is set, this field holds the
4124 * lag_id in bits 0:9.
4127 MLXSW_ITEM32(reg
, ritr
, sp_if_system_port
, 0x08, 0, 16);
4129 /* reg_ritr_sp_if_vid
4133 MLXSW_ITEM32(reg
, ritr
, sp_if_vid
, 0x18, 0, 12);
4135 /* Loopback Interface */
4137 enum mlxsw_reg_ritr_loopback_protocol
{
4138 /* IPinIP IPv4 underlay Unicast */
4139 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4
,
4140 /* IPinIP IPv6 underlay Unicast */
4141 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6
,
4144 /* reg_ritr_loopback_protocol
4147 MLXSW_ITEM32(reg
, ritr
, loopback_protocol
, 0x08, 28, 4);
4149 enum mlxsw_reg_ritr_loopback_ipip_type
{
4150 /* Tunnel is IPinIP. */
4151 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP
,
4152 /* Tunnel is GRE, no key. */
4153 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP
,
4154 /* Tunnel is GRE, with a key. */
4155 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP
,
4158 /* reg_ritr_loopback_ipip_type
4159 * Encapsulation type.
4162 MLXSW_ITEM32(reg
, ritr
, loopback_ipip_type
, 0x10, 24, 4);
4164 enum mlxsw_reg_ritr_loopback_ipip_options
{
4165 /* The key is defined by gre_key. */
4166 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET
,
4169 /* reg_ritr_loopback_ipip_options
4172 MLXSW_ITEM32(reg
, ritr
, loopback_ipip_options
, 0x10, 20, 4);
4174 /* reg_ritr_loopback_ipip_uvr
4175 * Underlay Virtual Router ID.
4176 * Range is 0..cap_max_virtual_routers-1.
4177 * Reserved for Spectrum-2.
4180 MLXSW_ITEM32(reg
, ritr
, loopback_ipip_uvr
, 0x10, 0, 16);
4182 /* reg_ritr_loopback_ipip_usip*
4183 * Encapsulation Underlay source IP.
4186 MLXSW_ITEM_BUF(reg
, ritr
, loopback_ipip_usip6
, 0x18, 16);
4187 MLXSW_ITEM32(reg
, ritr
, loopback_ipip_usip4
, 0x24, 0, 32);
4189 /* reg_ritr_loopback_ipip_gre_key
4191 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP.
4194 MLXSW_ITEM32(reg
, ritr
, loopback_ipip_gre_key
, 0x28, 0, 32);
4196 /* Shared between ingress/egress */
4197 enum mlxsw_reg_ritr_counter_set_type
{
4199 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT
= 0x0,
4200 /* Basic. Used for router interfaces, counting the following:
4201 * - Error and Discard counters.
4202 * - Unicast, Multicast and Broadcast counters. Sharing the
4203 * same set of counters for the different type of traffic
4204 * (IPv4, IPv6 and mpls).
4206 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC
= 0x9,
4209 /* reg_ritr_ingress_counter_index
4210 * Counter Index for flow counter.
4213 MLXSW_ITEM32(reg
, ritr
, ingress_counter_index
, 0x38, 0, 24);
4215 /* reg_ritr_ingress_counter_set_type
4216 * Igress Counter Set Type for router interface counter.
4219 MLXSW_ITEM32(reg
, ritr
, ingress_counter_set_type
, 0x38, 24, 8);
4221 /* reg_ritr_egress_counter_index
4222 * Counter Index for flow counter.
4225 MLXSW_ITEM32(reg
, ritr
, egress_counter_index
, 0x3C, 0, 24);
4227 /* reg_ritr_egress_counter_set_type
4228 * Egress Counter Set Type for router interface counter.
4231 MLXSW_ITEM32(reg
, ritr
, egress_counter_set_type
, 0x3C, 24, 8);
4233 static inline void mlxsw_reg_ritr_counter_pack(char *payload
, u32 index
,
4234 bool enable
, bool egress
)
4236 enum mlxsw_reg_ritr_counter_set_type set_type
;
4239 set_type
= MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC
;
4241 set_type
= MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT
;
4242 mlxsw_reg_ritr_egress_counter_set_type_set(payload
, set_type
);
4245 mlxsw_reg_ritr_egress_counter_index_set(payload
, index
);
4247 mlxsw_reg_ritr_ingress_counter_index_set(payload
, index
);
4250 static inline void mlxsw_reg_ritr_rif_pack(char *payload
, u16 rif
)
4252 MLXSW_REG_ZERO(ritr
, payload
);
4253 mlxsw_reg_ritr_rif_set(payload
, rif
);
4256 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload
, bool lag
,
4257 u16 system_port
, u16 vid
)
4259 mlxsw_reg_ritr_sp_if_lag_set(payload
, lag
);
4260 mlxsw_reg_ritr_sp_if_system_port_set(payload
, system_port
);
4261 mlxsw_reg_ritr_sp_if_vid_set(payload
, vid
);
4264 static inline void mlxsw_reg_ritr_pack(char *payload
, bool enable
,
4265 enum mlxsw_reg_ritr_if_type type
,
4266 u16 rif
, u16 vr_id
, u16 mtu
)
4268 bool op
= enable
? MLXSW_REG_RITR_RIF_CREATE
: MLXSW_REG_RITR_RIF_DEL
;
4270 MLXSW_REG_ZERO(ritr
, payload
);
4271 mlxsw_reg_ritr_enable_set(payload
, enable
);
4272 mlxsw_reg_ritr_ipv4_set(payload
, 1);
4273 mlxsw_reg_ritr_ipv6_set(payload
, 1);
4274 mlxsw_reg_ritr_type_set(payload
, type
);
4275 mlxsw_reg_ritr_op_set(payload
, op
);
4276 mlxsw_reg_ritr_rif_set(payload
, rif
);
4277 mlxsw_reg_ritr_ipv4_fe_set(payload
, 1);
4278 mlxsw_reg_ritr_ipv6_fe_set(payload
, 1);
4279 mlxsw_reg_ritr_lb_en_set(payload
, 1);
4280 mlxsw_reg_ritr_virtual_router_set(payload
, vr_id
);
4281 mlxsw_reg_ritr_mtu_set(payload
, mtu
);
4284 static inline void mlxsw_reg_ritr_mac_pack(char *payload
, const char *mac
)
4286 mlxsw_reg_ritr_if_mac_memcpy_to(payload
, mac
);
4290 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload
,
4291 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type
,
4292 enum mlxsw_reg_ritr_loopback_ipip_options options
,
4293 u16 uvr_id
, u32 gre_key
)
4295 mlxsw_reg_ritr_loopback_ipip_type_set(payload
, ipip_type
);
4296 mlxsw_reg_ritr_loopback_ipip_options_set(payload
, options
);
4297 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload
, uvr_id
);
4298 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload
, gre_key
);
4302 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload
,
4303 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type
,
4304 enum mlxsw_reg_ritr_loopback_ipip_options options
,
4305 u16 uvr_id
, u32 usip
, u32 gre_key
)
4307 mlxsw_reg_ritr_loopback_protocol_set(payload
,
4308 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4
);
4309 mlxsw_reg_ritr_loopback_ipip_common_pack(payload
, ipip_type
, options
,
4311 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload
, usip
);
4314 /* RATR - Router Adjacency Table Register
4315 * --------------------------------------
4316 * The RATR register is used to configure the Router Adjacency (next-hop)
4319 #define MLXSW_REG_RATR_ID 0x8008
4320 #define MLXSW_REG_RATR_LEN 0x2C
4322 MLXSW_REG_DEFINE(ratr
, MLXSW_REG_RATR_ID
, MLXSW_REG_RATR_LEN
);
4324 enum mlxsw_reg_ratr_op
{
4326 MLXSW_REG_RATR_OP_QUERY_READ
= 0,
4327 /* Read and clear activity */
4328 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR
= 2,
4329 /* Write Adjacency entry */
4330 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY
= 1,
4331 /* Write Adjacency entry only if the activity is cleared.
4332 * The write may not succeed if the activity is set. There is not
4333 * direct feedback if the write has succeeded or not, however
4334 * the get will reveal the actual entry (SW can compare the get
4335 * response to the set command).
4337 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY
= 3,
4341 * Note that Write operation may also be used for updating
4342 * counter_set_type and counter_index. In this case all other
4343 * fields must not be updated.
4346 MLXSW_ITEM32(reg
, ratr
, op
, 0x00, 28, 4);
4349 * Valid bit. Indicates if the adjacency entry is valid.
4350 * Note: the device may need some time before reusing an invalidated
4351 * entry. During this time the entry can not be reused. It is
4352 * recommended to use another entry before reusing an invalidated
4353 * entry (e.g. software can put it at the end of the list for
4354 * reusing). Trying to access an invalidated entry not yet cleared
4355 * by the device results with failure indicating "Try Again" status.
4356 * When valid is '0' then egress_router_interface,trap_action,
4357 * adjacency_parameters and counters are reserved
4360 MLXSW_ITEM32(reg
, ratr
, v
, 0x00, 24, 1);
4363 * Activity. Set for new entries. Set if a packet lookup has hit on
4364 * the specific entry. To clear the a bit, use "clear activity".
4367 MLXSW_ITEM32(reg
, ratr
, a
, 0x00, 16, 1);
4369 enum mlxsw_reg_ratr_type
{
4371 MLXSW_REG_RATR_TYPE_ETHERNET
,
4372 /* IPoIB Unicast without GRH.
4373 * Reserved for Spectrum.
4375 MLXSW_REG_RATR_TYPE_IPOIB_UC
,
4376 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast
4378 * Reserved for Spectrum.
4380 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH
,
4382 * Reserved for Spectrum.
4384 MLXSW_REG_RATR_TYPE_IPOIB_MC
,
4386 * Reserved for SwitchX/-2.
4388 MLXSW_REG_RATR_TYPE_MPLS
,
4390 * Reserved for SwitchX/-2.
4392 MLXSW_REG_RATR_TYPE_IPIP
,
4396 * Adjacency entry type.
4399 MLXSW_ITEM32(reg
, ratr
, type
, 0x04, 28, 4);
4401 /* reg_ratr_adjacency_index_low
4402 * Bits 15:0 of index into the adjacency table.
4403 * For SwitchX and SwitchX-2, the adjacency table is linear and
4404 * used for adjacency entries only.
4405 * For Spectrum, the index is to the KVD linear.
4408 MLXSW_ITEM32(reg
, ratr
, adjacency_index_low
, 0x04, 0, 16);
4410 /* reg_ratr_egress_router_interface
4411 * Range is 0 .. cap_max_router_interfaces - 1
4414 MLXSW_ITEM32(reg
, ratr
, egress_router_interface
, 0x08, 0, 16);
4416 enum mlxsw_reg_ratr_trap_action
{
4417 MLXSW_REG_RATR_TRAP_ACTION_NOP
,
4418 MLXSW_REG_RATR_TRAP_ACTION_TRAP
,
4419 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU
,
4420 MLXSW_REG_RATR_TRAP_ACTION_MIRROR
,
4421 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS
,
4424 /* reg_ratr_trap_action
4425 * see mlxsw_reg_ratr_trap_action
4428 MLXSW_ITEM32(reg
, ratr
, trap_action
, 0x0C, 28, 4);
4430 /* reg_ratr_adjacency_index_high
4431 * Bits 23:16 of the adjacency_index.
4434 MLXSW_ITEM32(reg
, ratr
, adjacency_index_high
, 0x0C, 16, 8);
4436 enum mlxsw_reg_ratr_trap_id
{
4437 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0
,
4438 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1
,
4442 * Trap ID to be reported to CPU.
4443 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
4444 * For trap_action of NOP, MIRROR and DISCARD_ERROR
4447 MLXSW_ITEM32(reg
, ratr
, trap_id
, 0x0C, 0, 8);
4449 /* reg_ratr_eth_destination_mac
4450 * MAC address of the destination next-hop.
4453 MLXSW_ITEM_BUF(reg
, ratr
, eth_destination_mac
, 0x12, 6);
4455 enum mlxsw_reg_ratr_ipip_type
{
4456 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */
4457 MLXSW_REG_RATR_IPIP_TYPE_IPV4
,
4458 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */
4459 MLXSW_REG_RATR_IPIP_TYPE_IPV6
,
4462 /* reg_ratr_ipip_type
4463 * Underlay destination ip type.
4464 * Note: the type field must match the protocol of the router interface.
4467 MLXSW_ITEM32(reg
, ratr
, ipip_type
, 0x10, 16, 4);
4469 /* reg_ratr_ipip_ipv4_udip
4470 * Underlay ipv4 dip.
4471 * Reserved when ipip_type is IPv6.
4474 MLXSW_ITEM32(reg
, ratr
, ipip_ipv4_udip
, 0x18, 0, 32);
4476 /* reg_ratr_ipip_ipv6_ptr
4477 * Pointer to IPv6 underlay destination ip address.
4478 * For Spectrum: Pointer to KVD linear space.
4481 MLXSW_ITEM32(reg
, ratr
, ipip_ipv6_ptr
, 0x1C, 0, 24);
4484 mlxsw_reg_ratr_pack(char *payload
,
4485 enum mlxsw_reg_ratr_op op
, bool valid
,
4486 enum mlxsw_reg_ratr_type type
,
4487 u32 adjacency_index
, u16 egress_rif
)
4489 MLXSW_REG_ZERO(ratr
, payload
);
4490 mlxsw_reg_ratr_op_set(payload
, op
);
4491 mlxsw_reg_ratr_v_set(payload
, valid
);
4492 mlxsw_reg_ratr_type_set(payload
, type
);
4493 mlxsw_reg_ratr_adjacency_index_low_set(payload
, adjacency_index
);
4494 mlxsw_reg_ratr_adjacency_index_high_set(payload
, adjacency_index
>> 16);
4495 mlxsw_reg_ratr_egress_router_interface_set(payload
, egress_rif
);
4498 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload
,
4499 const char *dest_mac
)
4501 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload
, dest_mac
);
4504 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload
, u32 ipv4_udip
)
4506 mlxsw_reg_ratr_ipip_type_set(payload
, MLXSW_REG_RATR_IPIP_TYPE_IPV4
);
4507 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload
, ipv4_udip
);
4510 /* RICNT - Router Interface Counter Register
4511 * -----------------------------------------
4512 * The RICNT register retrieves per port performance counters
4514 #define MLXSW_REG_RICNT_ID 0x800B
4515 #define MLXSW_REG_RICNT_LEN 0x100
4517 MLXSW_REG_DEFINE(ricnt
, MLXSW_REG_RICNT_ID
, MLXSW_REG_RICNT_LEN
);
4519 /* reg_ricnt_counter_index
4523 MLXSW_ITEM32(reg
, ricnt
, counter_index
, 0x04, 0, 24);
4525 enum mlxsw_reg_ricnt_counter_set_type
{
4527 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT
= 0x00,
4528 /* Basic. Used for router interfaces, counting the following:
4529 * - Error and Discard counters.
4530 * - Unicast, Multicast and Broadcast counters. Sharing the
4531 * same set of counters for the different type of traffic
4532 * (IPv4, IPv6 and mpls).
4534 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC
= 0x09,
4537 /* reg_ricnt_counter_set_type
4538 * Counter Set Type for router interface counter
4541 MLXSW_ITEM32(reg
, ricnt
, counter_set_type
, 0x04, 24, 8);
4543 enum mlxsw_reg_ricnt_opcode
{
4544 /* Nop. Supported only for read access*/
4545 MLXSW_REG_RICNT_OPCODE_NOP
= 0x00,
4546 /* Clear. Setting the clr bit will reset the counter value for
4547 * all counters of the specified Router Interface.
4549 MLXSW_REG_RICNT_OPCODE_CLEAR
= 0x08,
4556 MLXSW_ITEM32(reg
, ricnt
, op
, 0x00, 28, 4);
4558 /* reg_ricnt_good_unicast_packets
4559 * good unicast packets.
4562 MLXSW_ITEM64(reg
, ricnt
, good_unicast_packets
, 0x08, 0, 64);
4564 /* reg_ricnt_good_multicast_packets
4565 * good multicast packets.
4568 MLXSW_ITEM64(reg
, ricnt
, good_multicast_packets
, 0x10, 0, 64);
4570 /* reg_ricnt_good_broadcast_packets
4571 * good broadcast packets
4574 MLXSW_ITEM64(reg
, ricnt
, good_broadcast_packets
, 0x18, 0, 64);
4576 /* reg_ricnt_good_unicast_bytes
4577 * A count of L3 data and padding octets not including L2 headers
4578 * for good unicast frames.
4581 MLXSW_ITEM64(reg
, ricnt
, good_unicast_bytes
, 0x20, 0, 64);
4583 /* reg_ricnt_good_multicast_bytes
4584 * A count of L3 data and padding octets not including L2 headers
4585 * for good multicast frames.
4588 MLXSW_ITEM64(reg
, ricnt
, good_multicast_bytes
, 0x28, 0, 64);
4590 /* reg_ritr_good_broadcast_bytes
4591 * A count of L3 data and padding octets not including L2 headers
4592 * for good broadcast frames.
4595 MLXSW_ITEM64(reg
, ricnt
, good_broadcast_bytes
, 0x30, 0, 64);
4597 /* reg_ricnt_error_packets
4598 * A count of errored frames that do not pass the router checks.
4601 MLXSW_ITEM64(reg
, ricnt
, error_packets
, 0x38, 0, 64);
4603 /* reg_ricnt_discrad_packets
4604 * A count of non-errored frames that do not pass the router checks.
4607 MLXSW_ITEM64(reg
, ricnt
, discard_packets
, 0x40, 0, 64);
4609 /* reg_ricnt_error_bytes
4610 * A count of L3 data and padding octets not including L2 headers
4611 * for errored frames.
4614 MLXSW_ITEM64(reg
, ricnt
, error_bytes
, 0x48, 0, 64);
4616 /* reg_ricnt_discard_bytes
4617 * A count of L3 data and padding octets not including L2 headers
4618 * for non-errored frames that do not pass the router checks.
4621 MLXSW_ITEM64(reg
, ricnt
, discard_bytes
, 0x50, 0, 64);
4623 static inline void mlxsw_reg_ricnt_pack(char *payload
, u32 index
,
4624 enum mlxsw_reg_ricnt_opcode op
)
4626 MLXSW_REG_ZERO(ricnt
, payload
);
4627 mlxsw_reg_ricnt_op_set(payload
, op
);
4628 mlxsw_reg_ricnt_counter_index_set(payload
, index
);
4629 mlxsw_reg_ricnt_counter_set_type_set(payload
,
4630 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC
);
4633 /* RALTA - Router Algorithmic LPM Tree Allocation Register
4634 * -------------------------------------------------------
4635 * RALTA is used to allocate the LPM trees of the SHSPM method.
4637 #define MLXSW_REG_RALTA_ID 0x8010
4638 #define MLXSW_REG_RALTA_LEN 0x04
4640 MLXSW_REG_DEFINE(ralta
, MLXSW_REG_RALTA_ID
, MLXSW_REG_RALTA_LEN
);
4643 * opcode (valid for Write, must be 0 on Read)
4644 * 0 - allocate a tree
4645 * 1 - deallocate a tree
4648 MLXSW_ITEM32(reg
, ralta
, op
, 0x00, 28, 2);
4650 enum mlxsw_reg_ralxx_protocol
{
4651 MLXSW_REG_RALXX_PROTOCOL_IPV4
,
4652 MLXSW_REG_RALXX_PROTOCOL_IPV6
,
4655 /* reg_ralta_protocol
4657 * Deallocation opcode: Reserved.
4660 MLXSW_ITEM32(reg
, ralta
, protocol
, 0x00, 24, 4);
4662 /* reg_ralta_tree_id
4663 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
4664 * the tree identifier (managed by software).
4665 * Note that tree_id 0 is allocated for a default-route tree.
4668 MLXSW_ITEM32(reg
, ralta
, tree_id
, 0x00, 0, 8);
4670 static inline void mlxsw_reg_ralta_pack(char *payload
, bool alloc
,
4671 enum mlxsw_reg_ralxx_protocol protocol
,
4674 MLXSW_REG_ZERO(ralta
, payload
);
4675 mlxsw_reg_ralta_op_set(payload
, !alloc
);
4676 mlxsw_reg_ralta_protocol_set(payload
, protocol
);
4677 mlxsw_reg_ralta_tree_id_set(payload
, tree_id
);
4680 /* RALST - Router Algorithmic LPM Structure Tree Register
4681 * ------------------------------------------------------
4682 * RALST is used to set and query the structure of an LPM tree.
4683 * The structure of the tree must be sorted as a sorted binary tree, while
4684 * each node is a bin that is tagged as the length of the prefixes the lookup
4685 * will refer to. Therefore, bin X refers to a set of entries with prefixes
4686 * of X bits to match with the destination address. The bin 0 indicates
4687 * the default action, when there is no match of any prefix.
4689 #define MLXSW_REG_RALST_ID 0x8011
4690 #define MLXSW_REG_RALST_LEN 0x104
4692 MLXSW_REG_DEFINE(ralst
, MLXSW_REG_RALST_ID
, MLXSW_REG_RALST_LEN
);
4694 /* reg_ralst_root_bin
4695 * The bin number of the root bin.
4696 * 0<root_bin=<(length of IP address)
4697 * For a default-route tree configure 0xff
4700 MLXSW_ITEM32(reg
, ralst
, root_bin
, 0x00, 16, 8);
4702 /* reg_ralst_tree_id
4703 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
4706 MLXSW_ITEM32(reg
, ralst
, tree_id
, 0x00, 0, 8);
4708 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
4709 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
4710 #define MLXSW_REG_RALST_BIN_COUNT 128
4712 /* reg_ralst_left_child_bin
4713 * Holding the children of the bin according to the stored tree's structure.
4714 * For trees composed of less than 4 blocks, the bins in excess are reserved.
4715 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
4718 MLXSW_ITEM16_INDEXED(reg
, ralst
, left_child_bin
, 0x04, 8, 8, 0x02, 0x00, false);
4720 /* reg_ralst_right_child_bin
4721 * Holding the children of the bin according to the stored tree's structure.
4722 * For trees composed of less than 4 blocks, the bins in excess are reserved.
4723 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
4726 MLXSW_ITEM16_INDEXED(reg
, ralst
, right_child_bin
, 0x04, 0, 8, 0x02, 0x00,
4729 static inline void mlxsw_reg_ralst_pack(char *payload
, u8 root_bin
, u8 tree_id
)
4731 MLXSW_REG_ZERO(ralst
, payload
);
4733 /* Initialize all bins to have no left or right child */
4734 memset(payload
+ MLXSW_REG_RALST_BIN_OFFSET
,
4735 MLXSW_REG_RALST_BIN_NO_CHILD
, MLXSW_REG_RALST_BIN_COUNT
* 2);
4737 mlxsw_reg_ralst_root_bin_set(payload
, root_bin
);
4738 mlxsw_reg_ralst_tree_id_set(payload
, tree_id
);
4741 static inline void mlxsw_reg_ralst_bin_pack(char *payload
, u8 bin_number
,
4745 int bin_index
= bin_number
- 1;
4747 mlxsw_reg_ralst_left_child_bin_set(payload
, bin_index
, left_child_bin
);
4748 mlxsw_reg_ralst_right_child_bin_set(payload
, bin_index
,
4752 /* RALTB - Router Algorithmic LPM Tree Binding Register
4753 * ----------------------------------------------------
4754 * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
4756 #define MLXSW_REG_RALTB_ID 0x8012
4757 #define MLXSW_REG_RALTB_LEN 0x04
4759 MLXSW_REG_DEFINE(raltb
, MLXSW_REG_RALTB_ID
, MLXSW_REG_RALTB_LEN
);
4761 /* reg_raltb_virtual_router
4763 * Range is 0..cap_max_virtual_routers-1
4766 MLXSW_ITEM32(reg
, raltb
, virtual_router
, 0x00, 16, 16);
4768 /* reg_raltb_protocol
4772 MLXSW_ITEM32(reg
, raltb
, protocol
, 0x00, 12, 4);
4774 /* reg_raltb_tree_id
4775 * Tree to be used for the {virtual_router, protocol}
4776 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
4777 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
4780 MLXSW_ITEM32(reg
, raltb
, tree_id
, 0x00, 0, 8);
4782 static inline void mlxsw_reg_raltb_pack(char *payload
, u16 virtual_router
,
4783 enum mlxsw_reg_ralxx_protocol protocol
,
4786 MLXSW_REG_ZERO(raltb
, payload
);
4787 mlxsw_reg_raltb_virtual_router_set(payload
, virtual_router
);
4788 mlxsw_reg_raltb_protocol_set(payload
, protocol
);
4789 mlxsw_reg_raltb_tree_id_set(payload
, tree_id
);
4792 /* RALUE - Router Algorithmic LPM Unicast Entry Register
4793 * -----------------------------------------------------
4794 * RALUE is used to configure and query LPM entries that serve
4795 * the Unicast protocols.
4797 #define MLXSW_REG_RALUE_ID 0x8013
4798 #define MLXSW_REG_RALUE_LEN 0x38
4800 MLXSW_REG_DEFINE(ralue
, MLXSW_REG_RALUE_ID
, MLXSW_REG_RALUE_LEN
);
4802 /* reg_ralue_protocol
4806 MLXSW_ITEM32(reg
, ralue
, protocol
, 0x00, 24, 4);
4808 enum mlxsw_reg_ralue_op
{
4809 /* Read operation. If entry doesn't exist, the operation fails. */
4810 MLXSW_REG_RALUE_OP_QUERY_READ
= 0,
4811 /* Clear on read operation. Used to read entry and
4812 * clear Activity bit.
4814 MLXSW_REG_RALUE_OP_QUERY_CLEAR
= 1,
4815 /* Write operation. Used to write a new entry to the table. All RW
4816 * fields are written for new entry. Activity bit is set
4819 MLXSW_REG_RALUE_OP_WRITE_WRITE
= 0,
4820 /* Update operation. Used to update an existing route entry and
4821 * only update the RW fields that are detailed in the field
4822 * op_u_mask. If entry doesn't exist, the operation fails.
4824 MLXSW_REG_RALUE_OP_WRITE_UPDATE
= 1,
4825 /* Clear activity. The Activity bit (the field a) is cleared
4828 MLXSW_REG_RALUE_OP_WRITE_CLEAR
= 2,
4829 /* Delete operation. Used to delete an existing entry. If entry
4830 * doesn't exist, the operation fails.
4832 MLXSW_REG_RALUE_OP_WRITE_DELETE
= 3,
4839 MLXSW_ITEM32(reg
, ralue
, op
, 0x00, 20, 3);
4842 * Activity. Set for new entries. Set if a packet lookup has hit on the
4843 * specific entry, only if the entry is a route. To clear the a bit, use
4844 * "clear activity" op.
4845 * Enabled by activity_dis in RGCR
4848 MLXSW_ITEM32(reg
, ralue
, a
, 0x00, 16, 1);
4850 /* reg_ralue_virtual_router
4852 * Range is 0..cap_max_virtual_routers-1
4855 MLXSW_ITEM32(reg
, ralue
, virtual_router
, 0x04, 16, 16);
4857 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
4858 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
4859 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
4861 /* reg_ralue_op_u_mask
4862 * opcode update mask.
4863 * On read operation, this field is reserved.
4864 * This field is valid for update opcode, otherwise - reserved.
4865 * This field is a bitmask of the fields that should be updated.
4868 MLXSW_ITEM32(reg
, ralue
, op_u_mask
, 0x04, 8, 3);
4870 /* reg_ralue_prefix_len
4871 * Number of bits in the prefix of the LPM route.
4872 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
4873 * two entries in the physical HW table.
4876 MLXSW_ITEM32(reg
, ralue
, prefix_len
, 0x08, 0, 8);
4879 * The prefix of the route or of the marker that the object of the LPM
4880 * is compared with. The most significant bits of the dip are the prefix.
4881 * The least significant bits must be '0' if the prefix_len is smaller
4882 * than 128 for IPv6 or smaller than 32 for IPv4.
4883 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
4886 MLXSW_ITEM32(reg
, ralue
, dip4
, 0x18, 0, 32);
4887 MLXSW_ITEM_BUF(reg
, ralue
, dip6
, 0x0C, 16);
4889 enum mlxsw_reg_ralue_entry_type
{
4890 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY
= 1,
4891 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY
= 2,
4892 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY
= 3,
4895 /* reg_ralue_entry_type
4897 * Note - for Marker entries, the action_type and action fields are reserved.
4900 MLXSW_ITEM32(reg
, ralue
, entry_type
, 0x1C, 30, 2);
4902 /* reg_ralue_bmp_len
4903 * The best match prefix length in the case that there is no match for
4905 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
4906 * Note for any update operation with entry_type modification this
4907 * field must be set.
4910 MLXSW_ITEM32(reg
, ralue
, bmp_len
, 0x1C, 16, 8);
4912 enum mlxsw_reg_ralue_action_type
{
4913 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE
,
4914 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL
,
4915 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME
,
4918 /* reg_ralue_action_type
4920 * Indicates how the IP address is connected.
4921 * It can be connected to a local subnet through local_erif or can be
4922 * on a remote subnet connected through a next-hop router,
4923 * or transmitted to the CPU.
4924 * Reserved when entry_type = MARKER_ENTRY
4927 MLXSW_ITEM32(reg
, ralue
, action_type
, 0x1C, 0, 2);
4929 enum mlxsw_reg_ralue_trap_action
{
4930 MLXSW_REG_RALUE_TRAP_ACTION_NOP
,
4931 MLXSW_REG_RALUE_TRAP_ACTION_TRAP
,
4932 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU
,
4933 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR
,
4934 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR
,
4937 /* reg_ralue_trap_action
4939 * For IP2ME action, only NOP and MIRROR are possible.
4942 MLXSW_ITEM32(reg
, ralue
, trap_action
, 0x20, 28, 4);
4944 /* reg_ralue_trap_id
4945 * Trap ID to be reported to CPU.
4946 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
4947 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
4950 MLXSW_ITEM32(reg
, ralue
, trap_id
, 0x20, 0, 9);
4952 /* reg_ralue_adjacency_index
4953 * Points to the first entry of the group-based ECMP.
4954 * Only relevant in case of REMOTE action.
4957 MLXSW_ITEM32(reg
, ralue
, adjacency_index
, 0x24, 0, 24);
4959 /* reg_ralue_ecmp_size
4960 * Amount of sequential entries starting
4961 * from the adjacency_index (the number of ECMPs).
4962 * The valid range is 1-64, 512, 1024, 2048 and 4096.
4963 * Reserved when trap_action is TRAP or DISCARD_ERROR.
4964 * Only relevant in case of REMOTE action.
4967 MLXSW_ITEM32(reg
, ralue
, ecmp_size
, 0x28, 0, 13);
4969 /* reg_ralue_local_erif
4970 * Egress Router Interface.
4971 * Only relevant in case of LOCAL action.
4974 MLXSW_ITEM32(reg
, ralue
, local_erif
, 0x24, 0, 16);
4976 /* reg_ralue_ip2me_v
4977 * Valid bit for the tunnel_ptr field.
4978 * If valid = 0 then trap to CPU as IP2ME trap ID.
4979 * If valid = 1 and the packet format allows NVE or IPinIP tunnel
4980 * decapsulation then tunnel decapsulation is done.
4981 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
4982 * decapsulation then trap as IP2ME trap ID.
4983 * Only relevant in case of IP2ME action.
4986 MLXSW_ITEM32(reg
, ralue
, ip2me_v
, 0x24, 31, 1);
4988 /* reg_ralue_ip2me_tunnel_ptr
4989 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
4990 * For Spectrum, pointer to KVD Linear.
4991 * Only relevant in case of IP2ME action.
4994 MLXSW_ITEM32(reg
, ralue
, ip2me_tunnel_ptr
, 0x24, 0, 24);
4996 static inline void mlxsw_reg_ralue_pack(char *payload
,
4997 enum mlxsw_reg_ralxx_protocol protocol
,
4998 enum mlxsw_reg_ralue_op op
,
4999 u16 virtual_router
, u8 prefix_len
)
5001 MLXSW_REG_ZERO(ralue
, payload
);
5002 mlxsw_reg_ralue_protocol_set(payload
, protocol
);
5003 mlxsw_reg_ralue_op_set(payload
, op
);
5004 mlxsw_reg_ralue_virtual_router_set(payload
, virtual_router
);
5005 mlxsw_reg_ralue_prefix_len_set(payload
, prefix_len
);
5006 mlxsw_reg_ralue_entry_type_set(payload
,
5007 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY
);
5008 mlxsw_reg_ralue_bmp_len_set(payload
, prefix_len
);
5011 static inline void mlxsw_reg_ralue_pack4(char *payload
,
5012 enum mlxsw_reg_ralxx_protocol protocol
,
5013 enum mlxsw_reg_ralue_op op
,
5014 u16 virtual_router
, u8 prefix_len
,
5017 mlxsw_reg_ralue_pack(payload
, protocol
, op
, virtual_router
, prefix_len
);
5018 mlxsw_reg_ralue_dip4_set(payload
, dip
);
5021 static inline void mlxsw_reg_ralue_pack6(char *payload
,
5022 enum mlxsw_reg_ralxx_protocol protocol
,
5023 enum mlxsw_reg_ralue_op op
,
5024 u16 virtual_router
, u8 prefix_len
,
5027 mlxsw_reg_ralue_pack(payload
, protocol
, op
, virtual_router
, prefix_len
);
5028 mlxsw_reg_ralue_dip6_memcpy_to(payload
, dip
);
5032 mlxsw_reg_ralue_act_remote_pack(char *payload
,
5033 enum mlxsw_reg_ralue_trap_action trap_action
,
5034 u16 trap_id
, u32 adjacency_index
, u16 ecmp_size
)
5036 mlxsw_reg_ralue_action_type_set(payload
,
5037 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE
);
5038 mlxsw_reg_ralue_trap_action_set(payload
, trap_action
);
5039 mlxsw_reg_ralue_trap_id_set(payload
, trap_id
);
5040 mlxsw_reg_ralue_adjacency_index_set(payload
, adjacency_index
);
5041 mlxsw_reg_ralue_ecmp_size_set(payload
, ecmp_size
);
5045 mlxsw_reg_ralue_act_local_pack(char *payload
,
5046 enum mlxsw_reg_ralue_trap_action trap_action
,
5047 u16 trap_id
, u16 local_erif
)
5049 mlxsw_reg_ralue_action_type_set(payload
,
5050 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL
);
5051 mlxsw_reg_ralue_trap_action_set(payload
, trap_action
);
5052 mlxsw_reg_ralue_trap_id_set(payload
, trap_id
);
5053 mlxsw_reg_ralue_local_erif_set(payload
, local_erif
);
5057 mlxsw_reg_ralue_act_ip2me_pack(char *payload
)
5059 mlxsw_reg_ralue_action_type_set(payload
,
5060 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME
);
5064 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload
, u32 tunnel_ptr
)
5066 mlxsw_reg_ralue_action_type_set(payload
,
5067 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME
);
5068 mlxsw_reg_ralue_ip2me_v_set(payload
, 1);
5069 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload
, tunnel_ptr
);
5072 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
5073 * ----------------------------------------------------------
5074 * The RAUHT register is used to configure and query the Unicast Host table in
5075 * devices that implement the Algorithmic LPM.
5077 #define MLXSW_REG_RAUHT_ID 0x8014
5078 #define MLXSW_REG_RAUHT_LEN 0x74
5080 MLXSW_REG_DEFINE(rauht
, MLXSW_REG_RAUHT_ID
, MLXSW_REG_RAUHT_LEN
);
5082 enum mlxsw_reg_rauht_type
{
5083 MLXSW_REG_RAUHT_TYPE_IPV4
,
5084 MLXSW_REG_RAUHT_TYPE_IPV6
,
5090 MLXSW_ITEM32(reg
, rauht
, type
, 0x00, 24, 2);
5092 enum mlxsw_reg_rauht_op
{
5093 MLXSW_REG_RAUHT_OP_QUERY_READ
= 0,
5094 /* Read operation */
5095 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ
= 1,
5096 /* Clear on read operation. Used to read entry and clear
5099 MLXSW_REG_RAUHT_OP_WRITE_ADD
= 0,
5100 /* Add. Used to write a new entry to the table. All R/W fields are
5101 * relevant for new entry. Activity bit is set for new entries.
5103 MLXSW_REG_RAUHT_OP_WRITE_UPDATE
= 1,
5104 /* Update action. Used to update an existing route entry and
5105 * only update the following fields:
5106 * trap_action, trap_id, mac, counter_set_type, counter_index
5108 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY
= 2,
5109 /* Clear activity. A bit is cleared for the entry. */
5110 MLXSW_REG_RAUHT_OP_WRITE_DELETE
= 3,
5112 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL
= 4,
5113 /* Delete all host entries on a RIF. In this command, dip
5114 * field is reserved.
5121 MLXSW_ITEM32(reg
, rauht
, op
, 0x00, 20, 3);
5124 * Activity. Set for new entries. Set if a packet lookup has hit on
5125 * the specific entry.
5126 * To clear the a bit, use "clear activity" op.
5127 * Enabled by activity_dis in RGCR
5130 MLXSW_ITEM32(reg
, rauht
, a
, 0x00, 16, 1);
5136 MLXSW_ITEM32(reg
, rauht
, rif
, 0x00, 0, 16);
5139 * Destination address.
5142 MLXSW_ITEM32(reg
, rauht
, dip4
, 0x1C, 0x0, 32);
5143 MLXSW_ITEM_BUF(reg
, rauht
, dip6
, 0x10, 16);
5145 enum mlxsw_reg_rauht_trap_action
{
5146 MLXSW_REG_RAUHT_TRAP_ACTION_NOP
,
5147 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP
,
5148 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU
,
5149 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR
,
5150 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS
,
5153 /* reg_rauht_trap_action
5156 MLXSW_ITEM32(reg
, rauht
, trap_action
, 0x60, 28, 4);
5158 enum mlxsw_reg_rauht_trap_id
{
5159 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0
,
5160 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1
,
5163 /* reg_rauht_trap_id
5164 * Trap ID to be reported to CPU.
5165 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
5166 * For trap_action of NOP, MIRROR and DISCARD_ERROR,
5167 * trap_id is reserved.
5170 MLXSW_ITEM32(reg
, rauht
, trap_id
, 0x60, 0, 9);
5172 enum mlxsw_reg_flow_counter_set_type
{
5174 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT
= 0x00,
5175 /* Count packets and bytes */
5176 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES
= 0x03,
5177 /* Count only packets */
5178 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS
= 0x05,
5181 /* reg_rauht_counter_set_type
5182 * Counter set type for flow counters
5185 MLXSW_ITEM32(reg
, rauht
, counter_set_type
, 0x68, 24, 8);
5187 /* reg_rauht_counter_index
5188 * Counter index for flow counters
5191 MLXSW_ITEM32(reg
, rauht
, counter_index
, 0x68, 0, 24);
5197 MLXSW_ITEM_BUF(reg
, rauht
, mac
, 0x6E, 6);
5199 static inline void mlxsw_reg_rauht_pack(char *payload
,
5200 enum mlxsw_reg_rauht_op op
, u16 rif
,
5203 MLXSW_REG_ZERO(rauht
, payload
);
5204 mlxsw_reg_rauht_op_set(payload
, op
);
5205 mlxsw_reg_rauht_rif_set(payload
, rif
);
5206 mlxsw_reg_rauht_mac_memcpy_to(payload
, mac
);
5209 static inline void mlxsw_reg_rauht_pack4(char *payload
,
5210 enum mlxsw_reg_rauht_op op
, u16 rif
,
5211 const char *mac
, u32 dip
)
5213 mlxsw_reg_rauht_pack(payload
, op
, rif
, mac
);
5214 mlxsw_reg_rauht_dip4_set(payload
, dip
);
5217 static inline void mlxsw_reg_rauht_pack6(char *payload
,
5218 enum mlxsw_reg_rauht_op op
, u16 rif
,
5219 const char *mac
, const char *dip
)
5221 mlxsw_reg_rauht_pack(payload
, op
, rif
, mac
);
5222 mlxsw_reg_rauht_type_set(payload
, MLXSW_REG_RAUHT_TYPE_IPV6
);
5223 mlxsw_reg_rauht_dip6_memcpy_to(payload
, dip
);
5226 static inline void mlxsw_reg_rauht_pack_counter(char *payload
,
5229 mlxsw_reg_rauht_counter_index_set(payload
, counter_index
);
5230 mlxsw_reg_rauht_counter_set_type_set(payload
,
5231 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES
);
5234 /* RALEU - Router Algorithmic LPM ECMP Update Register
5235 * ---------------------------------------------------
5236 * The register enables updating the ECMP section in the action for multiple
5237 * LPM Unicast entries in a single operation. The update is executed to
5238 * all entries of a {virtual router, protocol} tuple using the same ECMP group.
5240 #define MLXSW_REG_RALEU_ID 0x8015
5241 #define MLXSW_REG_RALEU_LEN 0x28
5243 MLXSW_REG_DEFINE(raleu
, MLXSW_REG_RALEU_ID
, MLXSW_REG_RALEU_LEN
);
5245 /* reg_raleu_protocol
5249 MLXSW_ITEM32(reg
, raleu
, protocol
, 0x00, 24, 4);
5251 /* reg_raleu_virtual_router
5253 * Range is 0..cap_max_virtual_routers-1
5256 MLXSW_ITEM32(reg
, raleu
, virtual_router
, 0x00, 0, 16);
5258 /* reg_raleu_adjacency_index
5259 * Adjacency Index used for matching on the existing entries.
5262 MLXSW_ITEM32(reg
, raleu
, adjacency_index
, 0x10, 0, 24);
5264 /* reg_raleu_ecmp_size
5265 * ECMP Size used for matching on the existing entries.
5268 MLXSW_ITEM32(reg
, raleu
, ecmp_size
, 0x14, 0, 13);
5270 /* reg_raleu_new_adjacency_index
5271 * New Adjacency Index.
5274 MLXSW_ITEM32(reg
, raleu
, new_adjacency_index
, 0x20, 0, 24);
5276 /* reg_raleu_new_ecmp_size
5280 MLXSW_ITEM32(reg
, raleu
, new_ecmp_size
, 0x24, 0, 13);
5282 static inline void mlxsw_reg_raleu_pack(char *payload
,
5283 enum mlxsw_reg_ralxx_protocol protocol
,
5285 u32 adjacency_index
, u16 ecmp_size
,
5286 u32 new_adjacency_index
,
5289 MLXSW_REG_ZERO(raleu
, payload
);
5290 mlxsw_reg_raleu_protocol_set(payload
, protocol
);
5291 mlxsw_reg_raleu_virtual_router_set(payload
, virtual_router
);
5292 mlxsw_reg_raleu_adjacency_index_set(payload
, adjacency_index
);
5293 mlxsw_reg_raleu_ecmp_size_set(payload
, ecmp_size
);
5294 mlxsw_reg_raleu_new_adjacency_index_set(payload
, new_adjacency_index
);
5295 mlxsw_reg_raleu_new_ecmp_size_set(payload
, new_ecmp_size
);
5298 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
5299 * ----------------------------------------------------------------
5300 * The RAUHTD register allows dumping entries from the Router Unicast Host
5301 * Table. For a given session an entry is dumped no more than one time. The
5302 * first RAUHTD access after reset is a new session. A session ends when the
5303 * num_rec response is smaller than num_rec request or for IPv4 when the
5304 * num_entries is smaller than 4. The clear activity affect the current session
5305 * or the last session if a new session has not started.
5307 #define MLXSW_REG_RAUHTD_ID 0x8018
5308 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
5309 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
5310 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
5311 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
5312 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
5313 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
5315 MLXSW_REG_DEFINE(rauhtd
, MLXSW_REG_RAUHTD_ID
, MLXSW_REG_RAUHTD_LEN
);
5317 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
5318 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
5320 /* reg_rauhtd_filter_fields
5321 * if a bit is '0' then the relevant field is ignored and dump is done
5322 * regardless of the field value
5323 * Bit0 - filter by activity: entry_a
5324 * Bit3 - filter by entry rip: entry_rif
5327 MLXSW_ITEM32(reg
, rauhtd
, filter_fields
, 0x00, 0, 8);
5329 enum mlxsw_reg_rauhtd_op
{
5330 MLXSW_REG_RAUHTD_OP_DUMP
,
5331 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR
,
5337 MLXSW_ITEM32(reg
, rauhtd
, op
, 0x04, 24, 2);
5339 /* reg_rauhtd_num_rec
5340 * At request: number of records requested
5341 * At response: number of records dumped
5342 * For IPv4, each record has 4 entries at request and up to 4 entries
5344 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
5347 MLXSW_ITEM32(reg
, rauhtd
, num_rec
, 0x04, 0, 8);
5349 /* reg_rauhtd_entry_a
5350 * Dump only if activity has value of entry_a
5351 * Reserved if filter_fields bit0 is '0'
5354 MLXSW_ITEM32(reg
, rauhtd
, entry_a
, 0x08, 16, 1);
5356 enum mlxsw_reg_rauhtd_type
{
5357 MLXSW_REG_RAUHTD_TYPE_IPV4
,
5358 MLXSW_REG_RAUHTD_TYPE_IPV6
,
5362 * Dump only if record type is:
5367 MLXSW_ITEM32(reg
, rauhtd
, type
, 0x08, 0, 4);
5369 /* reg_rauhtd_entry_rif
5370 * Dump only if RIF has value of entry_rif
5371 * Reserved if filter_fields bit3 is '0'
5374 MLXSW_ITEM32(reg
, rauhtd
, entry_rif
, 0x0C, 0, 16);
5376 static inline void mlxsw_reg_rauhtd_pack(char *payload
,
5377 enum mlxsw_reg_rauhtd_type type
)
5379 MLXSW_REG_ZERO(rauhtd
, payload
);
5380 mlxsw_reg_rauhtd_filter_fields_set(payload
, MLXSW_REG_RAUHTD_FILTER_A
);
5381 mlxsw_reg_rauhtd_op_set(payload
, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR
);
5382 mlxsw_reg_rauhtd_num_rec_set(payload
, MLXSW_REG_RAUHTD_REC_MAX_NUM
);
5383 mlxsw_reg_rauhtd_entry_a_set(payload
, 1);
5384 mlxsw_reg_rauhtd_type_set(payload
, type
);
5387 /* reg_rauhtd_ipv4_rec_num_entries
5388 * Number of valid entries in this record:
5390 * 1 - 2 valid entries
5391 * 2 - 3 valid entries
5392 * 3 - 4 valid entries
5395 MLXSW_ITEM32_INDEXED(reg
, rauhtd
, ipv4_rec_num_entries
,
5396 MLXSW_REG_RAUHTD_BASE_LEN
, 28, 2,
5397 MLXSW_REG_RAUHTD_REC_LEN
, 0x00, false);
5399 /* reg_rauhtd_rec_type
5405 MLXSW_ITEM32_INDEXED(reg
, rauhtd
, rec_type
, MLXSW_REG_RAUHTD_BASE_LEN
, 24, 2,
5406 MLXSW_REG_RAUHTD_REC_LEN
, 0x00, false);
5408 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
5410 /* reg_rauhtd_ipv4_ent_a
5411 * Activity. Set for new entries. Set if a packet lookup has hit on the
5415 MLXSW_ITEM32_INDEXED(reg
, rauhtd
, ipv4_ent_a
, MLXSW_REG_RAUHTD_BASE_LEN
, 16, 1,
5416 MLXSW_REG_RAUHTD_IPV4_ENT_LEN
, 0x00, false);
5418 /* reg_rauhtd_ipv4_ent_rif
5422 MLXSW_ITEM32_INDEXED(reg
, rauhtd
, ipv4_ent_rif
, MLXSW_REG_RAUHTD_BASE_LEN
, 0,
5423 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN
, 0x00, false);
5425 /* reg_rauhtd_ipv4_ent_dip
5426 * Destination IPv4 address.
5429 MLXSW_ITEM32_INDEXED(reg
, rauhtd
, ipv4_ent_dip
, MLXSW_REG_RAUHTD_BASE_LEN
, 0,
5430 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN
, 0x04, false);
5432 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
5434 /* reg_rauhtd_ipv6_ent_a
5435 * Activity. Set for new entries. Set if a packet lookup has hit on the
5439 MLXSW_ITEM32_INDEXED(reg
, rauhtd
, ipv6_ent_a
, MLXSW_REG_RAUHTD_BASE_LEN
, 16, 1,
5440 MLXSW_REG_RAUHTD_IPV6_ENT_LEN
, 0x00, false);
5442 /* reg_rauhtd_ipv6_ent_rif
5446 MLXSW_ITEM32_INDEXED(reg
, rauhtd
, ipv6_ent_rif
, MLXSW_REG_RAUHTD_BASE_LEN
, 0,
5447 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN
, 0x00, false);
5449 /* reg_rauhtd_ipv6_ent_dip
5450 * Destination IPv6 address.
5453 MLXSW_ITEM_BUF_INDEXED(reg
, rauhtd
, ipv6_ent_dip
, MLXSW_REG_RAUHTD_BASE_LEN
,
5454 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN
, 0x10);
5456 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload
,
5457 int ent_index
, u16
*p_rif
,
5460 *p_rif
= mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload
, ent_index
);
5461 *p_dip
= mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload
, ent_index
);
5464 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload
,
5465 int rec_index
, u16
*p_rif
,
5468 *p_rif
= mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload
, rec_index
);
5469 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload
, rec_index
, p_dip
);
5472 /* RTDP - Routing Tunnel Decap Properties Register
5473 * -----------------------------------------------
5474 * The RTDP register is used for configuring the tunnel decap properties of NVE
5477 #define MLXSW_REG_RTDP_ID 0x8020
5478 #define MLXSW_REG_RTDP_LEN 0x44
5480 MLXSW_REG_DEFINE(rtdp
, MLXSW_REG_RTDP_ID
, MLXSW_REG_RTDP_LEN
);
5482 enum mlxsw_reg_rtdp_type
{
5483 MLXSW_REG_RTDP_TYPE_NVE
,
5484 MLXSW_REG_RTDP_TYPE_IPIP
,
5488 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type.
5491 MLXSW_ITEM32(reg
, rtdp
, type
, 0x00, 28, 4);
5493 /* reg_rtdp_tunnel_index
5494 * Index to the Decap entry.
5495 * For Spectrum, Index to KVD Linear.
5498 MLXSW_ITEM32(reg
, rtdp
, tunnel_index
, 0x00, 0, 24);
5502 /* reg_rtdp_ipip_irif
5503 * Ingress Router Interface for the overlay router
5506 MLXSW_ITEM32(reg
, rtdp
, ipip_irif
, 0x04, 16, 16);
5508 enum mlxsw_reg_rtdp_ipip_sip_check
{
5509 /* No sip checks. */
5510 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO
,
5511 /* Filter packet if underlay is not IPv4 or if underlay SIP does not
5514 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4
,
5515 /* Filter packet if underlay is not IPv6 or if underlay SIP does not
5518 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6
= 3,
5521 /* reg_rtdp_ipip_sip_check
5522 * SIP check to perform. If decapsulation failed due to these configurations
5523 * then trap_id is IPIP_DECAP_ERROR.
5526 MLXSW_ITEM32(reg
, rtdp
, ipip_sip_check
, 0x04, 0, 3);
5528 /* If set, allow decapsulation of IPinIP (without GRE). */
5529 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0)
5530 /* If set, allow decapsulation of IPinGREinIP without a key. */
5531 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1)
5532 /* If set, allow decapsulation of IPinGREinIP with a key. */
5533 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2)
5535 /* reg_rtdp_ipip_type_check
5536 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to
5537 * these configurations then trap_id is IPIP_DECAP_ERROR.
5540 MLXSW_ITEM32(reg
, rtdp
, ipip_type_check
, 0x08, 24, 3);
5542 /* reg_rtdp_ipip_gre_key_check
5543 * Whether GRE key should be checked. When check is enabled:
5544 * - A packet received as IPinIP (without GRE) will always pass.
5545 * - A packet received as IPinGREinIP without a key will not pass the check.
5546 * - A packet received as IPinGREinIP with a key will pass the check only if the
5547 * key in the packet is equal to expected_gre_key.
5548 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR.
5551 MLXSW_ITEM32(reg
, rtdp
, ipip_gre_key_check
, 0x08, 23, 1);
5553 /* reg_rtdp_ipip_ipv4_usip
5554 * Underlay IPv4 address for ipv4 source address check.
5555 * Reserved when sip_check is not '1'.
5558 MLXSW_ITEM32(reg
, rtdp
, ipip_ipv4_usip
, 0x0C, 0, 32);
5560 /* reg_rtdp_ipip_ipv6_usip_ptr
5561 * This field is valid when sip_check is "sipv6 check explicitly". This is a
5562 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index
5563 * is to the KVD linear.
5564 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6.
5567 MLXSW_ITEM32(reg
, rtdp
, ipip_ipv6_usip_ptr
, 0x10, 0, 24);
5569 /* reg_rtdp_ipip_expected_gre_key
5570 * GRE key for checking.
5571 * Reserved when gre_key_check is '0'.
5574 MLXSW_ITEM32(reg
, rtdp
, ipip_expected_gre_key
, 0x14, 0, 32);
5576 static inline void mlxsw_reg_rtdp_pack(char *payload
,
5577 enum mlxsw_reg_rtdp_type type
,
5580 MLXSW_REG_ZERO(rtdp
, payload
);
5581 mlxsw_reg_rtdp_type_set(payload
, type
);
5582 mlxsw_reg_rtdp_tunnel_index_set(payload
, tunnel_index
);
5586 mlxsw_reg_rtdp_ipip4_pack(char *payload
, u16 irif
,
5587 enum mlxsw_reg_rtdp_ipip_sip_check sip_check
,
5588 unsigned int type_check
, bool gre_key_check
,
5589 u32 ipv4_usip
, u32 expected_gre_key
)
5591 mlxsw_reg_rtdp_ipip_irif_set(payload
, irif
);
5592 mlxsw_reg_rtdp_ipip_sip_check_set(payload
, sip_check
);
5593 mlxsw_reg_rtdp_ipip_type_check_set(payload
, type_check
);
5594 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload
, gre_key_check
);
5595 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload
, ipv4_usip
);
5596 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload
, expected_gre_key
);
5599 /* MFCR - Management Fan Control Register
5600 * --------------------------------------
5601 * This register controls the settings of the Fan Speed PWM mechanism.
5603 #define MLXSW_REG_MFCR_ID 0x9001
5604 #define MLXSW_REG_MFCR_LEN 0x08
5606 MLXSW_REG_DEFINE(mfcr
, MLXSW_REG_MFCR_ID
, MLXSW_REG_MFCR_LEN
);
5608 enum mlxsw_reg_mfcr_pwm_frequency
{
5609 MLXSW_REG_MFCR_PWM_FEQ_11HZ
= 0x00,
5610 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ
= 0x01,
5611 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ
= 0x02,
5612 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ
= 0x40,
5613 MLXSW_REG_MFCR_PWM_FEQ_5KHZ
= 0x41,
5614 MLXSW_REG_MFCR_PWM_FEQ_20KHZ
= 0x42,
5615 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ
= 0x43,
5616 MLXSW_REG_MFCR_PWM_FEQ_25KHZ
= 0x44,
5619 /* reg_mfcr_pwm_frequency
5620 * Controls the frequency of the PWM signal.
5623 MLXSW_ITEM32(reg
, mfcr
, pwm_frequency
, 0x00, 0, 7);
5625 #define MLXSW_MFCR_TACHOS_MAX 10
5627 /* reg_mfcr_tacho_active
5628 * Indicates which of the tachometer is active (bit per tachometer).
5631 MLXSW_ITEM32(reg
, mfcr
, tacho_active
, 0x04, 16, MLXSW_MFCR_TACHOS_MAX
);
5633 #define MLXSW_MFCR_PWMS_MAX 5
5635 /* reg_mfcr_pwm_active
5636 * Indicates which of the PWM control is active (bit per PWM).
5639 MLXSW_ITEM32(reg
, mfcr
, pwm_active
, 0x04, 0, MLXSW_MFCR_PWMS_MAX
);
5642 mlxsw_reg_mfcr_pack(char *payload
,
5643 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency
)
5645 MLXSW_REG_ZERO(mfcr
, payload
);
5646 mlxsw_reg_mfcr_pwm_frequency_set(payload
, pwm_frequency
);
5650 mlxsw_reg_mfcr_unpack(char *payload
,
5651 enum mlxsw_reg_mfcr_pwm_frequency
*p_pwm_frequency
,
5652 u16
*p_tacho_active
, u8
*p_pwm_active
)
5654 *p_pwm_frequency
= mlxsw_reg_mfcr_pwm_frequency_get(payload
);
5655 *p_tacho_active
= mlxsw_reg_mfcr_tacho_active_get(payload
);
5656 *p_pwm_active
= mlxsw_reg_mfcr_pwm_active_get(payload
);
5659 /* MFSC - Management Fan Speed Control Register
5660 * --------------------------------------------
5661 * This register controls the settings of the Fan Speed PWM mechanism.
5663 #define MLXSW_REG_MFSC_ID 0x9002
5664 #define MLXSW_REG_MFSC_LEN 0x08
5666 MLXSW_REG_DEFINE(mfsc
, MLXSW_REG_MFSC_ID
, MLXSW_REG_MFSC_LEN
);
5669 * Fan pwm to control / monitor.
5672 MLXSW_ITEM32(reg
, mfsc
, pwm
, 0x00, 24, 3);
5674 /* reg_mfsc_pwm_duty_cycle
5675 * Controls the duty cycle of the PWM. Value range from 0..255 to
5676 * represent duty cycle of 0%...100%.
5679 MLXSW_ITEM32(reg
, mfsc
, pwm_duty_cycle
, 0x04, 0, 8);
5681 static inline void mlxsw_reg_mfsc_pack(char *payload
, u8 pwm
,
5684 MLXSW_REG_ZERO(mfsc
, payload
);
5685 mlxsw_reg_mfsc_pwm_set(payload
, pwm
);
5686 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload
, pwm_duty_cycle
);
5689 /* MFSM - Management Fan Speed Measurement
5690 * ---------------------------------------
5691 * This register controls the settings of the Tacho measurements and
5692 * enables reading the Tachometer measurements.
5694 #define MLXSW_REG_MFSM_ID 0x9003
5695 #define MLXSW_REG_MFSM_LEN 0x08
5697 MLXSW_REG_DEFINE(mfsm
, MLXSW_REG_MFSM_ID
, MLXSW_REG_MFSM_LEN
);
5700 * Fan tachometer index.
5703 MLXSW_ITEM32(reg
, mfsm
, tacho
, 0x00, 24, 4);
5706 * Fan speed (round per minute).
5709 MLXSW_ITEM32(reg
, mfsm
, rpm
, 0x04, 0, 16);
5711 static inline void mlxsw_reg_mfsm_pack(char *payload
, u8 tacho
)
5713 MLXSW_REG_ZERO(mfsm
, payload
);
5714 mlxsw_reg_mfsm_tacho_set(payload
, tacho
);
5717 /* MFSL - Management Fan Speed Limit Register
5718 * ------------------------------------------
5719 * The Fan Speed Limit register is used to configure the fan speed
5720 * event / interrupt notification mechanism. Fan speed threshold are
5721 * defined for both under-speed and over-speed.
5723 #define MLXSW_REG_MFSL_ID 0x9004
5724 #define MLXSW_REG_MFSL_LEN 0x0C
5726 MLXSW_REG_DEFINE(mfsl
, MLXSW_REG_MFSL_ID
, MLXSW_REG_MFSL_LEN
);
5729 * Fan tachometer index.
5732 MLXSW_ITEM32(reg
, mfsl
, tacho
, 0x00, 24, 4);
5734 /* reg_mfsl_tach_min
5735 * Tachometer minimum value (minimum RPM).
5738 MLXSW_ITEM32(reg
, mfsl
, tach_min
, 0x04, 0, 16);
5740 /* reg_mfsl_tach_max
5741 * Tachometer maximum value (maximum RPM).
5744 MLXSW_ITEM32(reg
, mfsl
, tach_max
, 0x08, 0, 16);
5746 static inline void mlxsw_reg_mfsl_pack(char *payload
, u8 tacho
,
5747 u16 tach_min
, u16 tach_max
)
5749 MLXSW_REG_ZERO(mfsl
, payload
);
5750 mlxsw_reg_mfsl_tacho_set(payload
, tacho
);
5751 mlxsw_reg_mfsl_tach_min_set(payload
, tach_min
);
5752 mlxsw_reg_mfsl_tach_max_set(payload
, tach_max
);
5755 static inline void mlxsw_reg_mfsl_unpack(char *payload
, u8 tacho
,
5756 u16
*p_tach_min
, u16
*p_tach_max
)
5759 *p_tach_min
= mlxsw_reg_mfsl_tach_min_get(payload
);
5762 *p_tach_max
= mlxsw_reg_mfsl_tach_max_get(payload
);
5765 /* MTCAP - Management Temperature Capabilities
5766 * -------------------------------------------
5767 * This register exposes the capabilities of the device and
5768 * system temperature sensing.
5770 #define MLXSW_REG_MTCAP_ID 0x9009
5771 #define MLXSW_REG_MTCAP_LEN 0x08
5773 MLXSW_REG_DEFINE(mtcap
, MLXSW_REG_MTCAP_ID
, MLXSW_REG_MTCAP_LEN
);
5775 /* reg_mtcap_sensor_count
5776 * Number of sensors supported by the device.
5777 * This includes the QSFP module sensors (if exists in the QSFP module).
5780 MLXSW_ITEM32(reg
, mtcap
, sensor_count
, 0x00, 0, 7);
5782 /* MTMP - Management Temperature
5783 * -----------------------------
5784 * This register controls the settings of the temperature measurements
5785 * and enables reading the temperature measurements. Note that temperature
5786 * is in 0.125 degrees Celsius.
5788 #define MLXSW_REG_MTMP_ID 0x900A
5789 #define MLXSW_REG_MTMP_LEN 0x20
5791 MLXSW_REG_DEFINE(mtmp
, MLXSW_REG_MTMP_ID
, MLXSW_REG_MTMP_LEN
);
5793 /* reg_mtmp_sensor_index
5794 * Sensors index to access.
5795 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
5796 * (module 0 is mapped to sensor_index 64).
5799 MLXSW_ITEM32(reg
, mtmp
, sensor_index
, 0x00, 0, 7);
5801 /* Convert to milli degrees Celsius */
5802 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
5804 /* reg_mtmp_temperature
5805 * Temperature reading from the sensor. Reading is in 0.125 Celsius
5809 MLXSW_ITEM32(reg
, mtmp
, temperature
, 0x04, 0, 16);
5812 * Max Temperature Enable - enables measuring the max temperature on a sensor.
5815 MLXSW_ITEM32(reg
, mtmp
, mte
, 0x08, 31, 1);
5818 * Max Temperature Reset - clears the value of the max temperature register.
5821 MLXSW_ITEM32(reg
, mtmp
, mtr
, 0x08, 30, 1);
5823 /* reg_mtmp_max_temperature
5824 * The highest measured temperature from the sensor.
5825 * When the bit mte is cleared, the field max_temperature is reserved.
5828 MLXSW_ITEM32(reg
, mtmp
, max_temperature
, 0x08, 0, 16);
5830 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
5832 /* reg_mtmp_sensor_name
5836 MLXSW_ITEM_BUF(reg
, mtmp
, sensor_name
, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE
);
5838 static inline void mlxsw_reg_mtmp_pack(char *payload
, u8 sensor_index
,
5839 bool max_temp_enable
,
5840 bool max_temp_reset
)
5842 MLXSW_REG_ZERO(mtmp
, payload
);
5843 mlxsw_reg_mtmp_sensor_index_set(payload
, sensor_index
);
5844 mlxsw_reg_mtmp_mte_set(payload
, max_temp_enable
);
5845 mlxsw_reg_mtmp_mtr_set(payload
, max_temp_reset
);
5848 static inline void mlxsw_reg_mtmp_unpack(char *payload
, unsigned int *p_temp
,
5849 unsigned int *p_max_temp
,
5855 temp
= mlxsw_reg_mtmp_temperature_get(payload
);
5856 *p_temp
= MLXSW_REG_MTMP_TEMP_TO_MC(temp
);
5859 temp
= mlxsw_reg_mtmp_max_temperature_get(payload
);
5860 *p_max_temp
= MLXSW_REG_MTMP_TEMP_TO_MC(temp
);
5863 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload
, sensor_name
);
5866 /* MCIA - Management Cable Info Access
5867 * -----------------------------------
5868 * MCIA register is used to access the SFP+ and QSFP connector's EPROM.
5871 #define MLXSW_REG_MCIA_ID 0x9014
5872 #define MLXSW_REG_MCIA_LEN 0x40
5874 MLXSW_REG_DEFINE(mcia
, MLXSW_REG_MCIA_ID
, MLXSW_REG_MCIA_LEN
);
5877 * Lock bit. Setting this bit will lock the access to the specific
5878 * cable. Used for updating a full page in a cable EPROM. Any access
5879 * other then subsequence writes will fail while the port is locked.
5882 MLXSW_ITEM32(reg
, mcia
, l
, 0x00, 31, 1);
5888 MLXSW_ITEM32(reg
, mcia
, module
, 0x00, 16, 8);
5894 MLXSW_ITEM32(reg
, mcia
, status
, 0x00, 0, 8);
5896 /* reg_mcia_i2c_device_address
5897 * I2C device address.
5900 MLXSW_ITEM32(reg
, mcia
, i2c_device_address
, 0x04, 24, 8);
5902 /* reg_mcia_page_number
5906 MLXSW_ITEM32(reg
, mcia
, page_number
, 0x04, 16, 8);
5908 /* reg_mcia_device_address
5912 MLXSW_ITEM32(reg
, mcia
, device_address
, 0x04, 0, 16);
5915 * Number of bytes to read/write (up to 48 bytes).
5918 MLXSW_ITEM32(reg
, mcia
, size
, 0x08, 0, 16);
5920 #define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48
5923 * Bytes to read/write.
5926 MLXSW_ITEM_BUF(reg
, mcia
, eeprom
, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE
);
5928 static inline void mlxsw_reg_mcia_pack(char *payload
, u8 module
, u8 lock
,
5929 u8 page_number
, u16 device_addr
,
5930 u8 size
, u8 i2c_device_addr
)
5932 MLXSW_REG_ZERO(mcia
, payload
);
5933 mlxsw_reg_mcia_module_set(payload
, module
);
5934 mlxsw_reg_mcia_l_set(payload
, lock
);
5935 mlxsw_reg_mcia_page_number_set(payload
, page_number
);
5936 mlxsw_reg_mcia_device_address_set(payload
, device_addr
);
5937 mlxsw_reg_mcia_size_set(payload
, size
);
5938 mlxsw_reg_mcia_i2c_device_address_set(payload
, i2c_device_addr
);
5941 /* MPAT - Monitoring Port Analyzer Table
5942 * -------------------------------------
5943 * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
5944 * For an enabled analyzer, all fields except e (enable) cannot be modified.
5946 #define MLXSW_REG_MPAT_ID 0x901A
5947 #define MLXSW_REG_MPAT_LEN 0x78
5949 MLXSW_REG_DEFINE(mpat
, MLXSW_REG_MPAT_ID
, MLXSW_REG_MPAT_LEN
);
5955 MLXSW_ITEM32(reg
, mpat
, pa_id
, 0x00, 28, 4);
5957 /* reg_mpat_system_port
5958 * A unique port identifier for the final destination of the packet.
5961 MLXSW_ITEM32(reg
, mpat
, system_port
, 0x00, 0, 16);
5964 * Enable. Indicating the Port Analyzer is enabled.
5967 MLXSW_ITEM32(reg
, mpat
, e
, 0x04, 31, 1);
5970 * Quality Of Service Mode.
5971 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
5972 * PCP, DEI, DSCP or VL) are configured.
5973 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
5974 * same as in the original packet that has triggered the mirroring. For
5975 * SPAN also the pcp,dei are maintained.
5978 MLXSW_ITEM32(reg
, mpat
, qos
, 0x04, 26, 1);
5981 * Best effort mode. Indicates mirroring traffic should not cause packet
5982 * drop or back pressure, but will discard the mirrored packets. Mirrored
5983 * packets will be forwarded on a best effort manner.
5984 * 0: Do not discard mirrored packets
5985 * 1: Discard mirrored packets if causing congestion
5988 MLXSW_ITEM32(reg
, mpat
, be
, 0x04, 25, 1);
5990 static inline void mlxsw_reg_mpat_pack(char *payload
, u8 pa_id
,
5991 u16 system_port
, bool e
)
5993 MLXSW_REG_ZERO(mpat
, payload
);
5994 mlxsw_reg_mpat_pa_id_set(payload
, pa_id
);
5995 mlxsw_reg_mpat_system_port_set(payload
, system_port
);
5996 mlxsw_reg_mpat_e_set(payload
, e
);
5997 mlxsw_reg_mpat_qos_set(payload
, 1);
5998 mlxsw_reg_mpat_be_set(payload
, 1);
6001 /* MPAR - Monitoring Port Analyzer Register
6002 * ----------------------------------------
6003 * MPAR register is used to query and configure the port analyzer port mirroring
6006 #define MLXSW_REG_MPAR_ID 0x901B
6007 #define MLXSW_REG_MPAR_LEN 0x08
6009 MLXSW_REG_DEFINE(mpar
, MLXSW_REG_MPAR_ID
, MLXSW_REG_MPAR_LEN
);
6011 /* reg_mpar_local_port
6012 * The local port to mirror the packets from.
6015 MLXSW_ITEM32(reg
, mpar
, local_port
, 0x00, 16, 8);
6017 enum mlxsw_reg_mpar_i_e
{
6018 MLXSW_REG_MPAR_TYPE_EGRESS
,
6019 MLXSW_REG_MPAR_TYPE_INGRESS
,
6026 MLXSW_ITEM32(reg
, mpar
, i_e
, 0x00, 0, 4);
6030 * By default, port mirroring is disabled for all ports.
6033 MLXSW_ITEM32(reg
, mpar
, enable
, 0x04, 31, 1);
6039 MLXSW_ITEM32(reg
, mpar
, pa_id
, 0x04, 0, 4);
6041 static inline void mlxsw_reg_mpar_pack(char *payload
, u8 local_port
,
6042 enum mlxsw_reg_mpar_i_e i_e
,
6043 bool enable
, u8 pa_id
)
6045 MLXSW_REG_ZERO(mpar
, payload
);
6046 mlxsw_reg_mpar_local_port_set(payload
, local_port
);
6047 mlxsw_reg_mpar_enable_set(payload
, enable
);
6048 mlxsw_reg_mpar_i_e_set(payload
, i_e
);
6049 mlxsw_reg_mpar_pa_id_set(payload
, pa_id
);
6052 /* MLCR - Management LED Control Register
6053 * --------------------------------------
6054 * Controls the system LEDs.
6056 #define MLXSW_REG_MLCR_ID 0x902B
6057 #define MLXSW_REG_MLCR_LEN 0x0C
6059 MLXSW_REG_DEFINE(mlcr
, MLXSW_REG_MLCR_ID
, MLXSW_REG_MLCR_LEN
);
6061 /* reg_mlcr_local_port
6062 * Local port number.
6065 MLXSW_ITEM32(reg
, mlcr
, local_port
, 0x00, 16, 8);
6067 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
6069 /* reg_mlcr_beacon_duration
6070 * Duration of the beacon to be active, in seconds.
6071 * 0x0 - Will turn off the beacon.
6072 * 0xFFFF - Will turn on the beacon until explicitly turned off.
6075 MLXSW_ITEM32(reg
, mlcr
, beacon_duration
, 0x04, 0, 16);
6077 /* reg_mlcr_beacon_remain
6078 * Remaining duration of the beacon, in seconds.
6079 * 0xFFFF indicates an infinite amount of time.
6082 MLXSW_ITEM32(reg
, mlcr
, beacon_remain
, 0x08, 0, 16);
6084 static inline void mlxsw_reg_mlcr_pack(char *payload
, u8 local_port
,
6087 MLXSW_REG_ZERO(mlcr
, payload
);
6088 mlxsw_reg_mlcr_local_port_set(payload
, local_port
);
6089 mlxsw_reg_mlcr_beacon_duration_set(payload
, active
?
6090 MLXSW_REG_MLCR_DURATION_MAX
: 0);
6093 /* MCQI - Management Component Query Information
6094 * ---------------------------------------------
6095 * This register allows querying information about firmware components.
6097 #define MLXSW_REG_MCQI_ID 0x9061
6098 #define MLXSW_REG_MCQI_BASE_LEN 0x18
6099 #define MLXSW_REG_MCQI_CAP_LEN 0x14
6100 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
6102 MLXSW_REG_DEFINE(mcqi
, MLXSW_REG_MCQI_ID
, MLXSW_REG_MCQI_LEN
);
6104 /* reg_mcqi_component_index
6105 * Index of the accessed component.
6108 MLXSW_ITEM32(reg
, mcqi
, component_index
, 0x00, 0, 16);
6110 enum mlxfw_reg_mcqi_info_type
{
6111 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES
,
6114 /* reg_mcqi_info_type
6115 * Component properties set.
6118 MLXSW_ITEM32(reg
, mcqi
, info_type
, 0x08, 0, 5);
6121 * The requested/returned data offset from the section start, given in bytes.
6122 * Must be DWORD aligned.
6125 MLXSW_ITEM32(reg
, mcqi
, offset
, 0x10, 0, 32);
6127 /* reg_mcqi_data_size
6128 * The requested/returned data size, given in bytes. If data_size is not DWORD
6129 * aligned, the last bytes are zero padded.
6132 MLXSW_ITEM32(reg
, mcqi
, data_size
, 0x14, 0, 16);
6134 /* reg_mcqi_cap_max_component_size
6135 * Maximum size for this component, given in bytes.
6138 MLXSW_ITEM32(reg
, mcqi
, cap_max_component_size
, 0x20, 0, 32);
6140 /* reg_mcqi_cap_log_mcda_word_size
6141 * Log 2 of the access word size in bytes. Read and write access must be aligned
6142 * to the word size. Write access must be done for an integer number of words.
6145 MLXSW_ITEM32(reg
, mcqi
, cap_log_mcda_word_size
, 0x24, 28, 4);
6147 /* reg_mcqi_cap_mcda_max_write_size
6148 * Maximal write size for MCDA register
6151 MLXSW_ITEM32(reg
, mcqi
, cap_mcda_max_write_size
, 0x24, 0, 16);
6153 static inline void mlxsw_reg_mcqi_pack(char *payload
, u16 component_index
)
6155 MLXSW_REG_ZERO(mcqi
, payload
);
6156 mlxsw_reg_mcqi_component_index_set(payload
, component_index
);
6157 mlxsw_reg_mcqi_info_type_set(payload
,
6158 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES
);
6159 mlxsw_reg_mcqi_offset_set(payload
, 0);
6160 mlxsw_reg_mcqi_data_size_set(payload
, MLXSW_REG_MCQI_CAP_LEN
);
6163 static inline void mlxsw_reg_mcqi_unpack(char *payload
,
6164 u32
*p_cap_max_component_size
,
6165 u8
*p_cap_log_mcda_word_size
,
6166 u16
*p_cap_mcda_max_write_size
)
6168 *p_cap_max_component_size
=
6169 mlxsw_reg_mcqi_cap_max_component_size_get(payload
);
6170 *p_cap_log_mcda_word_size
=
6171 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload
);
6172 *p_cap_mcda_max_write_size
=
6173 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload
);
6176 /* MCC - Management Component Control
6177 * ----------------------------------
6178 * Controls the firmware component and updates the FSM.
6180 #define MLXSW_REG_MCC_ID 0x9062
6181 #define MLXSW_REG_MCC_LEN 0x1C
6183 MLXSW_REG_DEFINE(mcc
, MLXSW_REG_MCC_ID
, MLXSW_REG_MCC_LEN
);
6185 enum mlxsw_reg_mcc_instruction
{
6186 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE
= 0x01,
6187 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE
= 0x02,
6188 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT
= 0x03,
6189 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT
= 0x04,
6190 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE
= 0x06,
6191 MLXSW_REG_MCC_INSTRUCTION_CANCEL
= 0x08,
6194 /* reg_mcc_instruction
6195 * Command to be executed by the FSM.
6196 * Applicable for write operation only.
6199 MLXSW_ITEM32(reg
, mcc
, instruction
, 0x00, 0, 8);
6201 /* reg_mcc_component_index
6202 * Index of the accessed component. Applicable only for commands that
6203 * refer to components. Otherwise, this field is reserved.
6206 MLXSW_ITEM32(reg
, mcc
, component_index
, 0x04, 0, 16);
6208 /* reg_mcc_update_handle
6209 * Token representing the current flow executed by the FSM.
6212 MLXSW_ITEM32(reg
, mcc
, update_handle
, 0x08, 0, 24);
6214 /* reg_mcc_error_code
6215 * Indicates the successful completion of the instruction, or the reason it
6219 MLXSW_ITEM32(reg
, mcc
, error_code
, 0x0C, 8, 8);
6221 /* reg_mcc_control_state
6225 MLXSW_ITEM32(reg
, mcc
, control_state
, 0x0C, 0, 4);
6227 /* reg_mcc_component_size
6228 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying
6229 * the size may shorten the update time. Value 0x0 means that size is
6233 MLXSW_ITEM32(reg
, mcc
, component_size
, 0x10, 0, 32);
6235 static inline void mlxsw_reg_mcc_pack(char *payload
,
6236 enum mlxsw_reg_mcc_instruction instr
,
6237 u16 component_index
, u32 update_handle
,
6240 MLXSW_REG_ZERO(mcc
, payload
);
6241 mlxsw_reg_mcc_instruction_set(payload
, instr
);
6242 mlxsw_reg_mcc_component_index_set(payload
, component_index
);
6243 mlxsw_reg_mcc_update_handle_set(payload
, update_handle
);
6244 mlxsw_reg_mcc_component_size_set(payload
, component_size
);
6247 static inline void mlxsw_reg_mcc_unpack(char *payload
, u32
*p_update_handle
,
6248 u8
*p_error_code
, u8
*p_control_state
)
6250 if (p_update_handle
)
6251 *p_update_handle
= mlxsw_reg_mcc_update_handle_get(payload
);
6253 *p_error_code
= mlxsw_reg_mcc_error_code_get(payload
);
6254 if (p_control_state
)
6255 *p_control_state
= mlxsw_reg_mcc_control_state_get(payload
);
6258 /* MCDA - Management Component Data Access
6259 * ---------------------------------------
6260 * This register allows reading and writing a firmware component.
6262 #define MLXSW_REG_MCDA_ID 0x9063
6263 #define MLXSW_REG_MCDA_BASE_LEN 0x10
6264 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
6265 #define MLXSW_REG_MCDA_LEN \
6266 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
6268 MLXSW_REG_DEFINE(mcda
, MLXSW_REG_MCDA_ID
, MLXSW_REG_MCDA_LEN
);
6270 /* reg_mcda_update_handle
6271 * Token representing the current flow executed by the FSM.
6274 MLXSW_ITEM32(reg
, mcda
, update_handle
, 0x00, 0, 24);
6277 * Offset of accessed address relative to component start. Accesses must be in
6278 * accordance to log_mcda_word_size in MCQI reg.
6281 MLXSW_ITEM32(reg
, mcda
, offset
, 0x04, 0, 32);
6284 * Size of the data accessed, given in bytes.
6287 MLXSW_ITEM32(reg
, mcda
, size
, 0x08, 0, 16);
6290 * Data block accessed.
6293 MLXSW_ITEM32_INDEXED(reg
, mcda
, data
, 0x10, 0, 32, 4, 0, false);
6295 static inline void mlxsw_reg_mcda_pack(char *payload
, u32 update_handle
,
6296 u32 offset
, u16 size
, u8
*data
)
6300 MLXSW_REG_ZERO(mcda
, payload
);
6301 mlxsw_reg_mcda_update_handle_set(payload
, update_handle
);
6302 mlxsw_reg_mcda_offset_set(payload
, offset
);
6303 mlxsw_reg_mcda_size_set(payload
, size
);
6305 for (i
= 0; i
< size
/ 4; i
++)
6306 mlxsw_reg_mcda_data_set(payload
, i
, *(u32
*) &data
[i
* 4]);
6309 /* MPSC - Monitoring Packet Sampling Configuration Register
6310 * --------------------------------------------------------
6311 * MPSC Register is used to configure the Packet Sampling mechanism.
6313 #define MLXSW_REG_MPSC_ID 0x9080
6314 #define MLXSW_REG_MPSC_LEN 0x1C
6316 MLXSW_REG_DEFINE(mpsc
, MLXSW_REG_MPSC_ID
, MLXSW_REG_MPSC_LEN
);
6318 /* reg_mpsc_local_port
6320 * Not supported for CPU port
6323 MLXSW_ITEM32(reg
, mpsc
, local_port
, 0x00, 16, 8);
6326 * Enable sampling on port local_port
6329 MLXSW_ITEM32(reg
, mpsc
, e
, 0x04, 30, 1);
6331 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
6334 * Sampling rate = 1 out of rate packets (with randomization around
6335 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
6338 MLXSW_ITEM32(reg
, mpsc
, rate
, 0x08, 0, 32);
6340 static inline void mlxsw_reg_mpsc_pack(char *payload
, u8 local_port
, bool e
,
6343 MLXSW_REG_ZERO(mpsc
, payload
);
6344 mlxsw_reg_mpsc_local_port_set(payload
, local_port
);
6345 mlxsw_reg_mpsc_e_set(payload
, e
);
6346 mlxsw_reg_mpsc_rate_set(payload
, rate
);
6349 /* MGPC - Monitoring General Purpose Counter Set Register
6350 * The MGPC register retrieves and sets the General Purpose Counter Set.
6352 #define MLXSW_REG_MGPC_ID 0x9081
6353 #define MLXSW_REG_MGPC_LEN 0x18
6355 MLXSW_REG_DEFINE(mgpc
, MLXSW_REG_MGPC_ID
, MLXSW_REG_MGPC_LEN
);
6357 /* reg_mgpc_counter_set_type
6361 MLXSW_ITEM32(reg
, mgpc
, counter_set_type
, 0x00, 24, 8);
6363 /* reg_mgpc_counter_index
6367 MLXSW_ITEM32(reg
, mgpc
, counter_index
, 0x00, 0, 24);
6369 enum mlxsw_reg_mgpc_opcode
{
6371 MLXSW_REG_MGPC_OPCODE_NOP
= 0x00,
6372 /* Clear counters */
6373 MLXSW_REG_MGPC_OPCODE_CLEAR
= 0x08,
6380 MLXSW_ITEM32(reg
, mgpc
, opcode
, 0x04, 28, 4);
6382 /* reg_mgpc_byte_counter
6383 * Byte counter value.
6386 MLXSW_ITEM64(reg
, mgpc
, byte_counter
, 0x08, 0, 64);
6388 /* reg_mgpc_packet_counter
6389 * Packet counter value.
6392 MLXSW_ITEM64(reg
, mgpc
, packet_counter
, 0x10, 0, 64);
6394 static inline void mlxsw_reg_mgpc_pack(char *payload
, u32 counter_index
,
6395 enum mlxsw_reg_mgpc_opcode opcode
,
6396 enum mlxsw_reg_flow_counter_set_type set_type
)
6398 MLXSW_REG_ZERO(mgpc
, payload
);
6399 mlxsw_reg_mgpc_counter_index_set(payload
, counter_index
);
6400 mlxsw_reg_mgpc_counter_set_type_set(payload
, set_type
);
6401 mlxsw_reg_mgpc_opcode_set(payload
, opcode
);
6404 /* SBPR - Shared Buffer Pools Register
6405 * -----------------------------------
6406 * The SBPR configures and retrieves the shared buffer pools and configuration.
6408 #define MLXSW_REG_SBPR_ID 0xB001
6409 #define MLXSW_REG_SBPR_LEN 0x14
6411 MLXSW_REG_DEFINE(sbpr
, MLXSW_REG_SBPR_ID
, MLXSW_REG_SBPR_LEN
);
6413 /* shared direstion enum for SBPR, SBCM, SBPM */
6414 enum mlxsw_reg_sbxx_dir
{
6415 MLXSW_REG_SBXX_DIR_INGRESS
,
6416 MLXSW_REG_SBXX_DIR_EGRESS
,
6423 MLXSW_ITEM32(reg
, sbpr
, dir
, 0x00, 24, 2);
6429 MLXSW_ITEM32(reg
, sbpr
, pool
, 0x00, 0, 4);
6432 * Pool size in buffer cells.
6435 MLXSW_ITEM32(reg
, sbpr
, size
, 0x04, 0, 24);
6437 enum mlxsw_reg_sbpr_mode
{
6438 MLXSW_REG_SBPR_MODE_STATIC
,
6439 MLXSW_REG_SBPR_MODE_DYNAMIC
,
6443 * Pool quota calculation mode.
6446 MLXSW_ITEM32(reg
, sbpr
, mode
, 0x08, 0, 4);
6448 static inline void mlxsw_reg_sbpr_pack(char *payload
, u8 pool
,
6449 enum mlxsw_reg_sbxx_dir dir
,
6450 enum mlxsw_reg_sbpr_mode mode
, u32 size
)
6452 MLXSW_REG_ZERO(sbpr
, payload
);
6453 mlxsw_reg_sbpr_pool_set(payload
, pool
);
6454 mlxsw_reg_sbpr_dir_set(payload
, dir
);
6455 mlxsw_reg_sbpr_mode_set(payload
, mode
);
6456 mlxsw_reg_sbpr_size_set(payload
, size
);
6459 /* SBCM - Shared Buffer Class Management Register
6460 * ----------------------------------------------
6461 * The SBCM register configures and retrieves the shared buffer allocation
6462 * and configuration according to Port-PG, including the binding to pool
6463 * and definition of the associated quota.
6465 #define MLXSW_REG_SBCM_ID 0xB002
6466 #define MLXSW_REG_SBCM_LEN 0x28
6468 MLXSW_REG_DEFINE(sbcm
, MLXSW_REG_SBCM_ID
, MLXSW_REG_SBCM_LEN
);
6470 /* reg_sbcm_local_port
6471 * Local port number.
6472 * For Ingress: excludes CPU port and Router port
6473 * For Egress: excludes IP Router
6476 MLXSW_ITEM32(reg
, sbcm
, local_port
, 0x00, 16, 8);
6479 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
6480 * For PG buffer: range is 0..cap_max_pg_buffers - 1
6481 * For traffic class: range is 0..cap_max_tclass - 1
6482 * Note that when traffic class is in MC aware mode then the traffic
6483 * classes which are MC aware cannot be configured.
6486 MLXSW_ITEM32(reg
, sbcm
, pg_buff
, 0x00, 8, 6);
6492 MLXSW_ITEM32(reg
, sbcm
, dir
, 0x00, 0, 2);
6494 /* reg_sbcm_min_buff
6495 * Minimum buffer size for the limiter, in cells.
6498 MLXSW_ITEM32(reg
, sbcm
, min_buff
, 0x18, 0, 24);
6500 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
6501 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
6502 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
6504 /* reg_sbcm_max_buff
6505 * When the pool associated to the port-pg/tclass is configured to
6506 * static, Maximum buffer size for the limiter configured in cells.
6507 * When the pool associated to the port-pg/tclass is configured to
6508 * dynamic, the max_buff holds the "alpha" parameter, supporting
6509 * the following values:
6511 * i: (1/128)*2^(i-1), for i=1..14
6515 MLXSW_ITEM32(reg
, sbcm
, max_buff
, 0x1C, 0, 24);
6518 * Association of the port-priority to a pool.
6521 MLXSW_ITEM32(reg
, sbcm
, pool
, 0x24, 0, 4);
6523 static inline void mlxsw_reg_sbcm_pack(char *payload
, u8 local_port
, u8 pg_buff
,
6524 enum mlxsw_reg_sbxx_dir dir
,
6525 u32 min_buff
, u32 max_buff
, u8 pool
)
6527 MLXSW_REG_ZERO(sbcm
, payload
);
6528 mlxsw_reg_sbcm_local_port_set(payload
, local_port
);
6529 mlxsw_reg_sbcm_pg_buff_set(payload
, pg_buff
);
6530 mlxsw_reg_sbcm_dir_set(payload
, dir
);
6531 mlxsw_reg_sbcm_min_buff_set(payload
, min_buff
);
6532 mlxsw_reg_sbcm_max_buff_set(payload
, max_buff
);
6533 mlxsw_reg_sbcm_pool_set(payload
, pool
);
6536 /* SBPM - Shared Buffer Port Management Register
6537 * ---------------------------------------------
6538 * The SBPM register configures and retrieves the shared buffer allocation
6539 * and configuration according to Port-Pool, including the definition
6540 * of the associated quota.
6542 #define MLXSW_REG_SBPM_ID 0xB003
6543 #define MLXSW_REG_SBPM_LEN 0x28
6545 MLXSW_REG_DEFINE(sbpm
, MLXSW_REG_SBPM_ID
, MLXSW_REG_SBPM_LEN
);
6547 /* reg_sbpm_local_port
6548 * Local port number.
6549 * For Ingress: excludes CPU port and Router port
6550 * For Egress: excludes IP Router
6553 MLXSW_ITEM32(reg
, sbpm
, local_port
, 0x00, 16, 8);
6556 * The pool associated to quota counting on the local_port.
6559 MLXSW_ITEM32(reg
, sbpm
, pool
, 0x00, 8, 4);
6565 MLXSW_ITEM32(reg
, sbpm
, dir
, 0x00, 0, 2);
6567 /* reg_sbpm_buff_occupancy
6568 * Current buffer occupancy in cells.
6571 MLXSW_ITEM32(reg
, sbpm
, buff_occupancy
, 0x10, 0, 24);
6574 * Clear Max Buffer Occupancy
6575 * When this bit is set, max_buff_occupancy field is cleared (and a
6576 * new max value is tracked from the time the clear was performed).
6579 MLXSW_ITEM32(reg
, sbpm
, clr
, 0x14, 31, 1);
6581 /* reg_sbpm_max_buff_occupancy
6582 * Maximum value of buffer occupancy in cells monitored. Cleared by
6583 * writing to the clr field.
6586 MLXSW_ITEM32(reg
, sbpm
, max_buff_occupancy
, 0x14, 0, 24);
6588 /* reg_sbpm_min_buff
6589 * Minimum buffer size for the limiter, in cells.
6592 MLXSW_ITEM32(reg
, sbpm
, min_buff
, 0x18, 0, 24);
6594 /* reg_sbpm_max_buff
6595 * When the pool associated to the port-pg/tclass is configured to
6596 * static, Maximum buffer size for the limiter configured in cells.
6597 * When the pool associated to the port-pg/tclass is configured to
6598 * dynamic, the max_buff holds the "alpha" parameter, supporting
6599 * the following values:
6601 * i: (1/128)*2^(i-1), for i=1..14
6605 MLXSW_ITEM32(reg
, sbpm
, max_buff
, 0x1C, 0, 24);
6607 static inline void mlxsw_reg_sbpm_pack(char *payload
, u8 local_port
, u8 pool
,
6608 enum mlxsw_reg_sbxx_dir dir
, bool clr
,
6609 u32 min_buff
, u32 max_buff
)
6611 MLXSW_REG_ZERO(sbpm
, payload
);
6612 mlxsw_reg_sbpm_local_port_set(payload
, local_port
);
6613 mlxsw_reg_sbpm_pool_set(payload
, pool
);
6614 mlxsw_reg_sbpm_dir_set(payload
, dir
);
6615 mlxsw_reg_sbpm_clr_set(payload
, clr
);
6616 mlxsw_reg_sbpm_min_buff_set(payload
, min_buff
);
6617 mlxsw_reg_sbpm_max_buff_set(payload
, max_buff
);
6620 static inline void mlxsw_reg_sbpm_unpack(char *payload
, u32
*p_buff_occupancy
,
6621 u32
*p_max_buff_occupancy
)
6623 *p_buff_occupancy
= mlxsw_reg_sbpm_buff_occupancy_get(payload
);
6624 *p_max_buff_occupancy
= mlxsw_reg_sbpm_max_buff_occupancy_get(payload
);
6627 /* SBMM - Shared Buffer Multicast Management Register
6628 * --------------------------------------------------
6629 * The SBMM register configures and retrieves the shared buffer allocation
6630 * and configuration for MC packets according to Switch-Priority, including
6631 * the binding to pool and definition of the associated quota.
6633 #define MLXSW_REG_SBMM_ID 0xB004
6634 #define MLXSW_REG_SBMM_LEN 0x28
6636 MLXSW_REG_DEFINE(sbmm
, MLXSW_REG_SBMM_ID
, MLXSW_REG_SBMM_LEN
);
6642 MLXSW_ITEM32(reg
, sbmm
, prio
, 0x00, 8, 4);
6644 /* reg_sbmm_min_buff
6645 * Minimum buffer size for the limiter, in cells.
6648 MLXSW_ITEM32(reg
, sbmm
, min_buff
, 0x18, 0, 24);
6650 /* reg_sbmm_max_buff
6651 * When the pool associated to the port-pg/tclass is configured to
6652 * static, Maximum buffer size for the limiter configured in cells.
6653 * When the pool associated to the port-pg/tclass is configured to
6654 * dynamic, the max_buff holds the "alpha" parameter, supporting
6655 * the following values:
6657 * i: (1/128)*2^(i-1), for i=1..14
6661 MLXSW_ITEM32(reg
, sbmm
, max_buff
, 0x1C, 0, 24);
6664 * Association of the port-priority to a pool.
6667 MLXSW_ITEM32(reg
, sbmm
, pool
, 0x24, 0, 4);
6669 static inline void mlxsw_reg_sbmm_pack(char *payload
, u8 prio
, u32 min_buff
,
6670 u32 max_buff
, u8 pool
)
6672 MLXSW_REG_ZERO(sbmm
, payload
);
6673 mlxsw_reg_sbmm_prio_set(payload
, prio
);
6674 mlxsw_reg_sbmm_min_buff_set(payload
, min_buff
);
6675 mlxsw_reg_sbmm_max_buff_set(payload
, max_buff
);
6676 mlxsw_reg_sbmm_pool_set(payload
, pool
);
6679 /* SBSR - Shared Buffer Status Register
6680 * ------------------------------------
6681 * The SBSR register retrieves the shared buffer occupancy according to
6682 * Port-Pool. Note that this register enables reading a large amount of data.
6683 * It is the user's responsibility to limit the amount of data to ensure the
6684 * response can match the maximum transfer unit. In case the response exceeds
6685 * the maximum transport unit, it will be truncated with no special notice.
6687 #define MLXSW_REG_SBSR_ID 0xB005
6688 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
6689 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
6690 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
6691 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
6692 MLXSW_REG_SBSR_REC_LEN * \
6693 MLXSW_REG_SBSR_REC_MAX_COUNT)
6695 MLXSW_REG_DEFINE(sbsr
, MLXSW_REG_SBSR_ID
, MLXSW_REG_SBSR_LEN
);
6698 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
6699 * field is cleared (and a new max value is tracked from the time the clear
6703 MLXSW_ITEM32(reg
, sbsr
, clr
, 0x00, 31, 1);
6705 /* reg_sbsr_ingress_port_mask
6706 * Bit vector for all ingress network ports.
6707 * Indicates which of the ports (for which the relevant bit is set)
6708 * are affected by the set operation. Configuration of any other port
6712 MLXSW_ITEM_BIT_ARRAY(reg
, sbsr
, ingress_port_mask
, 0x10, 0x20, 1);
6714 /* reg_sbsr_pg_buff_mask
6715 * Bit vector for all switch priority groups.
6716 * Indicates which of the priorities (for which the relevant bit is set)
6717 * are affected by the set operation. Configuration of any other priority
6719 * Range is 0..cap_max_pg_buffers - 1
6722 MLXSW_ITEM_BIT_ARRAY(reg
, sbsr
, pg_buff_mask
, 0x30, 0x4, 1);
6724 /* reg_sbsr_egress_port_mask
6725 * Bit vector for all egress network ports.
6726 * Indicates which of the ports (for which the relevant bit is set)
6727 * are affected by the set operation. Configuration of any other port
6731 MLXSW_ITEM_BIT_ARRAY(reg
, sbsr
, egress_port_mask
, 0x34, 0x20, 1);
6733 /* reg_sbsr_tclass_mask
6734 * Bit vector for all traffic classes.
6735 * Indicates which of the traffic classes (for which the relevant bit is
6736 * set) are affected by the set operation. Configuration of any other
6737 * traffic class does not change.
6738 * Range is 0..cap_max_tclass - 1
6741 MLXSW_ITEM_BIT_ARRAY(reg
, sbsr
, tclass_mask
, 0x54, 0x8, 1);
6743 static inline void mlxsw_reg_sbsr_pack(char *payload
, bool clr
)
6745 MLXSW_REG_ZERO(sbsr
, payload
);
6746 mlxsw_reg_sbsr_clr_set(payload
, clr
);
6749 /* reg_sbsr_rec_buff_occupancy
6750 * Current buffer occupancy in cells.
6753 MLXSW_ITEM32_INDEXED(reg
, sbsr
, rec_buff_occupancy
, MLXSW_REG_SBSR_BASE_LEN
,
6754 0, 24, MLXSW_REG_SBSR_REC_LEN
, 0x00, false);
6756 /* reg_sbsr_rec_max_buff_occupancy
6757 * Maximum value of buffer occupancy in cells monitored. Cleared by
6758 * writing to the clr field.
6761 MLXSW_ITEM32_INDEXED(reg
, sbsr
, rec_max_buff_occupancy
, MLXSW_REG_SBSR_BASE_LEN
,
6762 0, 24, MLXSW_REG_SBSR_REC_LEN
, 0x04, false);
6764 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload
, int rec_index
,
6765 u32
*p_buff_occupancy
,
6766 u32
*p_max_buff_occupancy
)
6769 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload
, rec_index
);
6770 *p_max_buff_occupancy
=
6771 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload
, rec_index
);
6774 /* SBIB - Shared Buffer Internal Buffer Register
6775 * ---------------------------------------------
6776 * The SBIB register configures per port buffers for internal use. The internal
6777 * buffers consume memory on the port buffers (note that the port buffers are
6778 * used also by PBMC).
6780 * For Spectrum this is used for egress mirroring.
6782 #define MLXSW_REG_SBIB_ID 0xB006
6783 #define MLXSW_REG_SBIB_LEN 0x10
6785 MLXSW_REG_DEFINE(sbib
, MLXSW_REG_SBIB_ID
, MLXSW_REG_SBIB_LEN
);
6787 /* reg_sbib_local_port
6789 * Not supported for CPU port and router port
6792 MLXSW_ITEM32(reg
, sbib
, local_port
, 0x00, 16, 8);
6794 /* reg_sbib_buff_size
6795 * Units represented in cells
6796 * Allowed range is 0 to (cap_max_headroom_size - 1)
6800 MLXSW_ITEM32(reg
, sbib
, buff_size
, 0x08, 0, 24);
6802 static inline void mlxsw_reg_sbib_pack(char *payload
, u8 local_port
,
6805 MLXSW_REG_ZERO(sbib
, payload
);
6806 mlxsw_reg_sbib_local_port_set(payload
, local_port
);
6807 mlxsw_reg_sbib_buff_size_set(payload
, buff_size
);
6810 static const struct mlxsw_reg_info
*mlxsw_reg_infos
[] = {
6892 static inline const char *mlxsw_reg_id_str(u16 reg_id
)
6894 const struct mlxsw_reg_info
*reg_info
;
6897 for (i
= 0; i
< ARRAY_SIZE(mlxsw_reg_infos
); i
++) {
6898 reg_info
= mlxsw_reg_infos
[i
];
6899 if (reg_info
->id
== reg_id
)
6900 return reg_info
->name
;
6905 /* PUDE - Port Up / Down Event
6906 * ---------------------------
6907 * Reports the operational state change of a port.
6909 #define MLXSW_REG_PUDE_LEN 0x10
6912 * Switch partition ID with which to associate the port.
6915 MLXSW_ITEM32(reg
, pude
, swid
, 0x00, 24, 8);
6917 /* reg_pude_local_port
6918 * Local port number.
6921 MLXSW_ITEM32(reg
, pude
, local_port
, 0x00, 16, 8);
6923 /* reg_pude_admin_status
6924 * Port administrative state (the desired state).
6927 * 3 - Up once. This means that in case of link failure, the port won't go
6928 * into polling mode, but will wait to be re-enabled by software.
6929 * 4 - Disabled by system. Can only be set by hardware.
6932 MLXSW_ITEM32(reg
, pude
, admin_status
, 0x00, 8, 4);
6934 /* reg_pude_oper_status
6935 * Port operatioanl state.
6938 * 3 - Down by port failure. This means that the device will not let the
6939 * port up again until explicitly specified by software.
6942 MLXSW_ITEM32(reg
, pude
, oper_status
, 0x00, 0, 4);