drivers/net/ethernet/mellanox/mlxsw/reg.h

   1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3
   4 #ifndef _MLXSW_REG_H
   5 #define _MLXSW_REG_H
   6
   7 #include <linux/kernel.h>
   8 #include <linux/string.h>
   9 #include <linux/bitops.h>
  10 #include <linux/if_vlan.h>
  11
  12 #include "item.h"
  13 #include "port.h"
  14
  15 struct mlxsw_reg_info {
  16         u16 id;
  17         u16 len; /* In u8 */
  18         const char *name;
  19 };
  20
  21 #define MLXSW_REG_DEFINE(_name, _id, _len)                              \
  22 static const struct mlxsw_reg_info mlxsw_reg_##_name = {                \
  23         .id = _id,                                                      \
  24         .len = _len,                                                    \
  25         .name = #_name,                                                 \
  26 }
  27
  28 #define MLXSW_REG(type) (&mlxsw_reg_##type)
  29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
  30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
  31
  32 /* SGCR - Switch General Configuration Register
  33  * --------------------------------------------
  34  * This register is used for configuration of the switch capabilities.
  35  */
  36 #define MLXSW_REG_SGCR_ID 0x2000
  37 #define MLXSW_REG_SGCR_LEN 0x10
  38
  39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
  40
  41 /* reg_sgcr_llb
  42  * Link Local Broadcast (Default=0)
  43  * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
  44  * packets and ignore the IGMP snooping entries.
  45  * Access: RW
  46  */
  47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
  48
  49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
  50 {
  51         MLXSW_REG_ZERO(sgcr, payload);
  52         mlxsw_reg_sgcr_llb_set(payload, !!llb);
  53 }
  54
  55 /* SPAD - Switch Physical Address Register
  56  * ---------------------------------------
  57  * The SPAD register configures the switch physical MAC address.
  58  */
  59 #define MLXSW_REG_SPAD_ID 0x2002
  60 #define MLXSW_REG_SPAD_LEN 0x10
  61
  62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
  63
  64 /* reg_spad_base_mac
  65  * Base MAC address for the switch partitions.
  66  * Per switch partition MAC address is equal to:
  67  * base_mac + swid
  68  * Access: RW
  69  */
  70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
  71
  72 /* SMID - Switch Multicast ID
  73  * --------------------------
  74  * The MID record maps from a MID (Multicast ID), which is a unique identifier
  75  * of the multicast group within the stacking domain, into a list of local
  76  * ports into which the packet is replicated.
  77  */
  78 #define MLXSW_REG_SMID_ID 0x2007
  79 #define MLXSW_REG_SMID_LEN 0x240
  80
  81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);
  82
  83 /* reg_smid_swid
  84  * Switch partition ID.
  85  * Access: Index
  86  */
  87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
  88
  89 /* reg_smid_mid
  90  * Multicast identifier - global identifier that represents the multicast group
  91  * across all devices.
  92  * Access: Index
  93  */
  94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
  95
  96 /* reg_smid_port
  97  * Local port memebership (1 bit per port).
  98  * Access: RW
  99  */
 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
 101
 102 /* reg_smid_port_mask
 103  * Local port mask (1 bit per port).
 104  * Access: W
 105  */
 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
 107
 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
 109                                        u8 port, bool set)
 110 {
 111         MLXSW_REG_ZERO(smid, payload);
 112         mlxsw_reg_smid_swid_set(payload, 0);
 113         mlxsw_reg_smid_mid_set(payload, mid);
 114         mlxsw_reg_smid_port_set(payload, port, set);
 115         mlxsw_reg_smid_port_mask_set(payload, port, 1);
 116 }
 117
 118 /* SSPR - Switch System Port Record Register
 119  * -----------------------------------------
 120  * Configures the system port to local port mapping.
 121  */
 122 #define MLXSW_REG_SSPR_ID 0x2008
 123 #define MLXSW_REG_SSPR_LEN 0x8
 124
 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
 126
 127 /* reg_sspr_m
 128  * Master - if set, then the record describes the master system port.
 129  * This is needed in case a local port is mapped into several system ports
 130  * (for multipathing). That number will be reported as the source system
 131  * port when packets are forwarded to the CPU. Only one master port is allowed
 132  * per local port.
 133  *
 134  * Note: Must be set for Spectrum.
 135  * Access: RW
 136  */
 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
 138
 139 /* reg_sspr_local_port
 140  * Local port number.
 141  *
 142  * Access: RW
 143  */
 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
 145
 146 /* reg_sspr_sub_port
 147  * Virtual port within the physical port.
 148  * Should be set to 0 when virtual ports are not enabled on the port.
 149  *
 150  * Access: RW
 151  */
 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
 153
 154 /* reg_sspr_system_port
 155  * Unique identifier within the stacking domain that represents all the ports
 156  * that are available in the system (external ports).
 157  *
 158  * Currently, only single-ASIC configurations are supported, so we default to
 159  * 1:1 mapping between system ports and local ports.
 160  * Access: Index
 161  */
 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
 163
 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
 165 {
 166         MLXSW_REG_ZERO(sspr, payload);
 167         mlxsw_reg_sspr_m_set(payload, 1);
 168         mlxsw_reg_sspr_local_port_set(payload, local_port);
 169         mlxsw_reg_sspr_sub_port_set(payload, 0);
 170         mlxsw_reg_sspr_system_port_set(payload, local_port);
 171 }
 172
 173 /* SFDAT - Switch Filtering Database Aging Time
 174  * --------------------------------------------
 175  * Controls the Switch aging time. Aging time is able to be set per Switch
 176  * Partition.
 177  */
 178 #define MLXSW_REG_SFDAT_ID 0x2009
 179 #define MLXSW_REG_SFDAT_LEN 0x8
 180
 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
 182
 183 /* reg_sfdat_swid
 184  * Switch partition ID.
 185  * Access: Index
 186  */
 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
 188
 189 /* reg_sfdat_age_time
 190  * Aging time in seconds
 191  * Min - 10 seconds
 192  * Max - 1,000,000 seconds
 193  * Default is 300 seconds.
 194  * Access: RW
 195  */
 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
 197
 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
 199 {
 200         MLXSW_REG_ZERO(sfdat, payload);
 201         mlxsw_reg_sfdat_swid_set(payload, 0);
 202         mlxsw_reg_sfdat_age_time_set(payload, age_time);
 203 }
 204
 205 /* SFD - Switch Filtering Database
 206  * -------------------------------
 207  * The following register defines the access to the filtering database.
 208  * The register supports querying, adding, removing and modifying the database.
 209  * The access is optimized for bulk updates in which case more than one
 210  * FDB record is present in the same command.
 211  */
 212 #define MLXSW_REG_SFD_ID 0x200A
 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN +     \
 217                            MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
 218
 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
 220
 221 /* reg_sfd_swid
 222  * Switch partition ID for queries. Reserved on Write.
 223  * Access: Index
 224  */
 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
 226
 227 enum mlxsw_reg_sfd_op {
 228         /* Dump entire FDB a (process according to record_locator) */
 229         MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
 230         /* Query records by {MAC, VID/FID} value */
 231         MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
 232         /* Query and clear activity. Query records by {MAC, VID/FID} value */
 233         MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
 234         /* Test. Response indicates if each of the records could be
 235          * added to the FDB.
 236          */
 237         MLXSW_REG_SFD_OP_WRITE_TEST = 0,
 238         /* Add/modify. Aged-out records cannot be added. This command removes
 239          * the learning notification of the {MAC, VID/FID}. Response includes
 240          * the entries that were added to the FDB.
 241          */
 242         MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
 243         /* Remove record by {MAC, VID/FID}. This command also removes
 244          * the learning notification and aged-out notifications
 245          * of the {MAC, VID/FID}. The response provides current (pre-removal)
 246          * entries as non-aged-out.
 247          */
 248         MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
 249         /* Remove learned notification by {MAC, VID/FID}. The response provides
 250          * the removed learning notification.
 251          */
 252         MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
 253 };
 254
 255 /* reg_sfd_op
 256  * Operation.
 257  * Access: OP
 258  */
 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
 260
 261 /* reg_sfd_record_locator
 262  * Used for querying the FDB. Use record_locator=0 to initiate the
 263  * query. When a record is returned, a new record_locator is
 264  * returned to be used in the subsequent query.
 265  * Reserved for database update.
 266  * Access: Index
 267  */
 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
 269
 270 /* reg_sfd_num_rec
 271  * Request: Number of records to read/add/modify/remove
 272  * Response: Number of records read/added/replaced/removed
 273  * See above description for more details.
 274  * Ranges 0..64
 275  * Access: RW
 276  */
 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
 278
 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
 280                                       u32 record_locator)
 281 {
 282         MLXSW_REG_ZERO(sfd, payload);
 283         mlxsw_reg_sfd_op_set(payload, op);
 284         mlxsw_reg_sfd_record_locator_set(payload, record_locator);
 285 }
 286
 287 /* reg_sfd_rec_swid
 288  * Switch partition ID.
 289  * Access: Index
 290  */
 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
 292                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 293
 294 enum mlxsw_reg_sfd_rec_type {
 295         MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
 296         MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
 297         MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
 298         MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
 299 };
 300
 301 /* reg_sfd_rec_type
 302  * FDB record type.
 303  * Access: RW
 304  */
 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
 306                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 307
 308 enum mlxsw_reg_sfd_rec_policy {
 309         /* Replacement disabled, aging disabled. */
 310         MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
 311         /* (mlag remote): Replacement enabled, aging disabled,
 312          * learning notification enabled on this port.
 313          */
 314         MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
 315         /* (ingress device): Replacement enabled, aging enabled. */
 316         MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
 317 };
 318
 319 /* reg_sfd_rec_policy
 320  * Policy.
 321  * Access: RW
 322  */
 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
 324                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 325
 326 /* reg_sfd_rec_a
 327  * Activity. Set for new static entries. Set for static entries if a frame SMAC
 328  * lookup hits on the entry.
 329  * To clear the a bit, use "query and clear activity" op.
 330  * Access: RO
 331  */
 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
 333                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 334
 335 /* reg_sfd_rec_mac
 336  * MAC address.
 337  * Access: Index
 338  */
 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
 340                        MLXSW_REG_SFD_REC_LEN, 0x02);
 341
 342 enum mlxsw_reg_sfd_rec_action {
 343         /* forward */
 344         MLXSW_REG_SFD_REC_ACTION_NOP = 0,
 345         /* forward and trap, trap_id is FDB_TRAP */
 346         MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
 347         /* trap and do not forward, trap_id is FDB_TRAP */
 348         MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
 349         /* forward to IP router */
 350         MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
 351         MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
 352 };
 353
 354 /* reg_sfd_rec_action
 355  * Action to apply on the packet.
 356  * Note: Dynamic entries can only be configured with NOP action.
 357  * Access: RW
 358  */
 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
 360                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 361
 362 /* reg_sfd_uc_sub_port
 363  * VEPA channel on local port.
 364  * Valid only if local port is a non-stacking port. Must be 0 if multichannel
 365  * VEPA is not enabled.
 366  * Access: RW
 367  */
 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
 369                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 370
 371 /* reg_sfd_uc_fid_vid
 372  * Filtering ID or VLAN ID
 373  * For SwitchX and SwitchX-2:
 374  * - Dynamic entries (policy 2,3) use FID
 375  * - Static entries (policy 0) use VID
 376  * - When independent learning is configured, VID=FID
 377  * For Spectrum: use FID for both Dynamic and Static entries.
 378  * VID should not be used.
 379  * Access: Index
 380  */
 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 382                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 383
 384 /* reg_sfd_uc_system_port
 385  * Unique port identifier for the final destination of the packet.
 386  * Access: RW
 387  */
 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 389                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 390
 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
 392                                           enum mlxsw_reg_sfd_rec_type rec_type,
 393                                           const char *mac,
 394                                           enum mlxsw_reg_sfd_rec_action action)
 395 {
 396         u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
 397
 398         if (rec_index >= num_rec)
 399                 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
 400         mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
 401         mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
 402         mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
 403         mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
 404 }
 405
 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
 407                                          enum mlxsw_reg_sfd_rec_policy policy,
 408                                          const char *mac, u16 fid_vid,
 409                                          enum mlxsw_reg_sfd_rec_action action,
 410                                          u8 local_port)
 411 {
 412         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 413                                MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
 414         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 415         mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
 416         mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
 417         mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
 418 }
 419
 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
 421                                            char *mac, u16 *p_fid_vid,
 422                                            u8 *p_local_port)
 423 {
 424         mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
 425         *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
 426         *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
 427 }
 428
 429 /* reg_sfd_uc_lag_sub_port
 430  * LAG sub port.
 431  * Must be 0 if multichannel VEPA is not enabled.
 432  * Access: RW
 433  */
 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
 435                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 436
 437 /* reg_sfd_uc_lag_fid_vid
 438  * Filtering ID or VLAN ID
 439  * For SwitchX and SwitchX-2:
 440  * - Dynamic entries (policy 2,3) use FID
 441  * - Static entries (policy 0) use VID
 442  * - When independent learning is configured, VID=FID
 443  * For Spectrum: use FID for both Dynamic and Static entries.
 444  * VID should not be used.
 445  * Access: Index
 446  */
 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 448                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 449
 450 /* reg_sfd_uc_lag_lag_vid
 451  * Indicates VID in case of vFIDs. Reserved for FIDs.
 452  * Access: RW
 453  */
 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
 455                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 456
 457 /* reg_sfd_uc_lag_lag_id
 458  * LAG Identifier - pointer into the LAG descriptor table.
 459  * Access: RW
 460  */
 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
 462                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 463
 464 static inline void
 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
 466                           enum mlxsw_reg_sfd_rec_policy policy,
 467                           const char *mac, u16 fid_vid,
 468                           enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
 469                           u16 lag_id)
 470 {
 471         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 472                                MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
 473                                mac, action);
 474         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 475         mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
 476         mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
 477         mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
 478         mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
 479 }
 480
 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
 482                                                char *mac, u16 *p_vid,
 483                                                u16 *p_lag_id)
 484 {
 485         mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
 486         *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
 487         *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
 488 }
 489
 490 /* reg_sfd_mc_pgi
 491  *
 492  * Multicast port group index - index into the port group table.
 493  * Value 0x1FFF indicates the pgi should point to the MID entry.
 494  * For Spectrum this value must be set to 0x1FFF
 495  * Access: RW
 496  */
 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
 498                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 499
 500 /* reg_sfd_mc_fid_vid
 501  *
 502  * Filtering ID or VLAN ID
 503  * Access: Index
 504  */
 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 506                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 507
 508 /* reg_sfd_mc_mid
 509  *
 510  * Multicast identifier - global identifier that represents the multicast
 511  * group across all devices.
 512  * Access: RW
 513  */
 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 515                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 516
 517 static inline void
 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
 519                       const char *mac, u16 fid_vid,
 520                       enum mlxsw_reg_sfd_rec_action action, u16 mid)
 521 {
 522         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 523                                MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
 524         mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
 525         mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
 526         mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
 527 }
 528
 529 /* reg_sfd_uc_tunnel_uip_msb
 530  * When protocol is IPv4, the most significant byte of the underlay IPv4
 531  * destination IP.
 532  * When protocol is IPv6, reserved.
 533  * Access: RW
 534  */
 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
 536                      8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
 537
 538 /* reg_sfd_uc_tunnel_fid
 539  * Filtering ID.
 540  * Access: Index
 541  */
 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 543                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 544
 545 enum mlxsw_reg_sfd_uc_tunnel_protocol {
 546         MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
 547         MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
 548 };
 549
 550 /* reg_sfd_uc_tunnel_protocol
 551  * IP protocol.
 552  * Access: RW
 553  */
 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
 555                      1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 556
 557 /* reg_sfd_uc_tunnel_uip_lsb
 558  * When protocol is IPv4, the least significant bytes of the underlay
 559  * IPv4 destination IP.
 560  * When protocol is IPv6, pointer to the underlay IPv6 destination IP
 561  * which is configured by RIPS.
 562  * Access: RW
 563  */
 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
 565                      24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 566
 567 static inline void
 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
 569                              enum mlxsw_reg_sfd_rec_policy policy,
 570                              const char *mac, u16 fid,
 571                              enum mlxsw_reg_sfd_rec_action action, u32 uip,
 572                              enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
 573 {
 574         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 575                                MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
 576                                action);
 577         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 578         mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
 579         mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
 580         mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
 581         mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
 582 }
 583
 584 /* SFN - Switch FDB Notification Register
 585  * -------------------------------------------
 586  * The switch provides notifications on newly learned FDB entries and
 587  * aged out entries. The notifications can be polled by software.
 588  */
 589 #define MLXSW_REG_SFN_ID 0x200B
 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN +     \
 594                            MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
 595
 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
 597
 598 /* reg_sfn_swid
 599  * Switch partition ID.
 600  * Access: Index
 601  */
 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
 603
 604 /* reg_sfn_end
 605  * Forces the current session to end.
 606  * Access: OP
 607  */
 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
 609
 610 /* reg_sfn_num_rec
 611  * Request: Number of learned notifications and aged-out notification
 612  * records requested.
 613  * Response: Number of notification records returned (must be smaller
 614  * than or equal to the value requested)
 615  * Ranges 0..64
 616  * Access: OP
 617  */
 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
 619
 620 static inline void mlxsw_reg_sfn_pack(char *payload)
 621 {
 622         MLXSW_REG_ZERO(sfn, payload);
 623         mlxsw_reg_sfn_swid_set(payload, 0);
 624         mlxsw_reg_sfn_end_set(payload, 1);
 625         mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
 626 }
 627
 628 /* reg_sfn_rec_swid
 629  * Switch partition ID.
 630  * Access: RO
 631  */
 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
 633                      MLXSW_REG_SFN_REC_LEN, 0x00, false);
 634
 635 enum mlxsw_reg_sfn_rec_type {
 636         /* MAC addresses learned on a regular port. */
 637         MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
 638         /* MAC addresses learned on a LAG port. */
 639         MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
 640         /* Aged-out MAC address on a regular port. */
 641         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
 642         /* Aged-out MAC address on a LAG port. */
 643         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
 644         /* Learned unicast tunnel record. */
 645         MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
 646         /* Aged-out unicast tunnel record. */
 647         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
 648 };
 649
 650 /* reg_sfn_rec_type
 651  * Notification record type.
 652  * Access: RO
 653  */
 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
 655                      MLXSW_REG_SFN_REC_LEN, 0x00, false);
 656
 657 /* reg_sfn_rec_mac
 658  * MAC address.
 659  * Access: RO
 660  */
 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
 662                        MLXSW_REG_SFN_REC_LEN, 0x02);
 663
 664 /* reg_sfn_mac_sub_port
 665  * VEPA channel on the local port.
 666  * 0 if multichannel VEPA is not enabled.
 667  * Access: RO
 668  */
 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
 670                      MLXSW_REG_SFN_REC_LEN, 0x08, false);
 671
 672 /* reg_sfn_mac_fid
 673  * Filtering identifier.
 674  * Access: RO
 675  */
 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
 677                      MLXSW_REG_SFN_REC_LEN, 0x08, false);
 678
 679 /* reg_sfn_mac_system_port
 680  * Unique port identifier for the final destination of the packet.
 681  * Access: RO
 682  */
 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
 684                      MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 685
 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
 687                                             char *mac, u16 *p_vid,
 688                                             u8 *p_local_port)
 689 {
 690         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 691         *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 692         *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
 693 }
 694
 695 /* reg_sfn_mac_lag_lag_id
 696  * LAG ID (pointer into the LAG descriptor table).
 697  * Access: RO
 698  */
 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
 700                      MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 701
 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
 703                                                 char *mac, u16 *p_vid,
 704                                                 u16 *p_lag_id)
 705 {
 706         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 707         *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 708         *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
 709 }
 710
 711 /* reg_sfn_uc_tunnel_uip_msb
 712  * When protocol is IPv4, the most significant byte of the underlay IPv4
 713  * address of the remote VTEP.
 714  * When protocol is IPv6, reserved.
 715  * Access: RO
 716  */
 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
 718                      8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
 719
 720 enum mlxsw_reg_sfn_uc_tunnel_protocol {
 721         MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
 722         MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
 723 };
 724
 725 /* reg_sfn_uc_tunnel_protocol
 726  * IP protocol.
 727  * Access: RO
 728  */
 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
 730                      1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 731
 732 /* reg_sfn_uc_tunnel_uip_lsb
 733  * When protocol is IPv4, the least significant bytes of the underlay
 734  * IPv4 address of the remote VTEP.
 735  * When protocol is IPv6, ipv6_id to be queried from TNIPSD.
 736  * Access: RO
 737  */
 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
 739                      24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 740
 741 enum mlxsw_reg_sfn_tunnel_port {
 742         MLXSW_REG_SFN_TUNNEL_PORT_NVE,
 743         MLXSW_REG_SFN_TUNNEL_PORT_VPLS,
 744         MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0,
 745         MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1,
 746 };
 747
 748 /* reg_sfn_uc_tunnel_port
 749  * Tunnel port.
 750  * Reserved on Spectrum.
 751  * Access: RO
 752  */
 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
 754                      MLXSW_REG_SFN_REC_LEN, 0x10, false);
 755
 756 static inline void
 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
 758                                u16 *p_fid, u32 *p_uip,
 759                                enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
 760 {
 761         u32 uip_msb, uip_lsb;
 762
 763         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 764         *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 765         uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
 766         uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
 767         *p_uip = uip_msb << 24 | uip_lsb;
 768         *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
 769 }
 770
 771 /* SPMS - Switch Port MSTP/RSTP State Register
 772  * -------------------------------------------
 773  * Configures the spanning tree state of a physical port.
 774  */
 775 #define MLXSW_REG_SPMS_ID 0x200D
 776 #define MLXSW_REG_SPMS_LEN 0x404
 777
 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
 779
 780 /* reg_spms_local_port
 781  * Local port number.
 782  * Access: Index
 783  */
 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
 785
 786 enum mlxsw_reg_spms_state {
 787         MLXSW_REG_SPMS_STATE_NO_CHANGE,
 788         MLXSW_REG_SPMS_STATE_DISCARDING,
 789         MLXSW_REG_SPMS_STATE_LEARNING,
 790         MLXSW_REG_SPMS_STATE_FORWARDING,
 791 };
 792
 793 /* reg_spms_state
 794  * Spanning tree state of each VLAN ID (VID) of the local port.
 795  * 0 - Do not change spanning tree state (used only when writing).
 796  * 1 - Discarding. No learning or forwarding to/from this port (default).
 797  * 2 - Learning. Port is learning, but not forwarding.
 798  * 3 - Forwarding. Port is learning and forwarding.
 799  * Access: RW
 800  */
 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
 802
 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
 804 {
 805         MLXSW_REG_ZERO(spms, payload);
 806         mlxsw_reg_spms_local_port_set(payload, local_port);
 807 }
 808
 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
 810                                            enum mlxsw_reg_spms_state state)
 811 {
 812         mlxsw_reg_spms_state_set(payload, vid, state);
 813 }
 814
 815 /* SPVID - Switch Port VID
 816  * -----------------------
 817  * The switch port VID configures the default VID for a port.
 818  */
 819 #define MLXSW_REG_SPVID_ID 0x200E
 820 #define MLXSW_REG_SPVID_LEN 0x08
 821
 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
 823
 824 /* reg_spvid_local_port
 825  * Local port number.
 826  * Access: Index
 827  */
 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
 829
 830 /* reg_spvid_sub_port
 831  * Virtual port within the physical port.
 832  * Should be set to 0 when virtual ports are not enabled on the port.
 833  * Access: Index
 834  */
 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
 836
 837 /* reg_spvid_pvid
 838  * Port default VID
 839  * Access: RW
 840  */
 841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
 842
 843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
 844 {
 845         MLXSW_REG_ZERO(spvid, payload);
 846         mlxsw_reg_spvid_local_port_set(payload, local_port);
 847         mlxsw_reg_spvid_pvid_set(payload, pvid);
 848 }
 849
 850 /* SPVM - Switch Port VLAN Membership
 851  * ----------------------------------
 852  * The Switch Port VLAN Membership register configures the VLAN membership
 853  * of a port in a VLAN denoted by VID. VLAN membership is managed per
 854  * virtual port. The register can be used to add and remove VID(s) from a port.
 855  */
 856 #define MLXSW_REG_SPVM_ID 0x200F
 857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
 858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
 859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255
 860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN +   \
 861                     MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
 862
 863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
 864
 865 /* reg_spvm_pt
 866  * Priority tagged. If this bit is set, packets forwarded to the port with
 867  * untagged VLAN membership (u bit is set) will be tagged with priority tag
 868  * (VID=0)
 869  * Access: RW
 870  */
 871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
 872
 873 /* reg_spvm_pte
 874  * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
 875  * the pt bit will NOT be updated. To update the pt bit, pte must be set.
 876  * Access: WO
 877  */
 878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
 879
 880 /* reg_spvm_local_port
 881  * Local port number.
 882  * Access: Index
 883  */
 884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
 885
 886 /* reg_spvm_sub_port
 887  * Virtual port within the physical port.
 888  * Should be set to 0 when virtual ports are not enabled on the port.
 889  * Access: Index
 890  */
 891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
 892
 893 /* reg_spvm_num_rec
 894  * Number of records to update. Each record contains: i, e, u, vid.
 895  * Access: OP
 896  */
 897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
 898
 899 /* reg_spvm_rec_i
 900  * Ingress membership in VLAN ID.
 901  * Access: Index
 902  */
 903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
 904                      MLXSW_REG_SPVM_BASE_LEN, 14, 1,
 905                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 906
 907 /* reg_spvm_rec_e
 908  * Egress membership in VLAN ID.
 909  * Access: Index
 910  */
 911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
 912                      MLXSW_REG_SPVM_BASE_LEN, 13, 1,
 913                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 914
 915 /* reg_spvm_rec_u
 916  * Untagged - port is an untagged member - egress transmission uses untagged
 917  * frames on VID<n>
 918  * Access: Index
 919  */
 920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
 921                      MLXSW_REG_SPVM_BASE_LEN, 12, 1,
 922                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 923
 924 /* reg_spvm_rec_vid
 925  * Egress membership in VLAN ID.
 926  * Access: Index
 927  */
 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
 929                      MLXSW_REG_SPVM_BASE_LEN, 0, 12,
 930                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 931
 932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
 933                                        u16 vid_begin, u16 vid_end,
 934                                        bool is_member, bool untagged)
 935 {
 936         int size = vid_end - vid_begin + 1;
 937         int i;
 938
 939         MLXSW_REG_ZERO(spvm, payload);
 940         mlxsw_reg_spvm_local_port_set(payload, local_port);
 941         mlxsw_reg_spvm_num_rec_set(payload, size);
 942
 943         for (i = 0; i < size; i++) {
 944                 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
 945                 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
 946                 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
 947                 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
 948         }
 949 }
 950
 951 /* SPAFT - Switch Port Acceptable Frame Types
 952  * ------------------------------------------
 953  * The Switch Port Acceptable Frame Types register configures the frame
 954  * admittance of the port.
 955  */
 956 #define MLXSW_REG_SPAFT_ID 0x2010
 957 #define MLXSW_REG_SPAFT_LEN 0x08
 958
 959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
 960
 961 /* reg_spaft_local_port
 962  * Local port number.
 963  * Access: Index
 964  *
 965  * Note: CPU port is not supported (all tag types are allowed).
 966  */
 967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
 968
 969 /* reg_spaft_sub_port
 970  * Virtual port within the physical port.
 971  * Should be set to 0 when virtual ports are not enabled on the port.
 972  * Access: RW
 973  */
 974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
 975
 976 /* reg_spaft_allow_untagged
 977  * When set, untagged frames on the ingress are allowed (default).
 978  * Access: RW
 979  */
 980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
 981
 982 /* reg_spaft_allow_prio_tagged
 983  * When set, priority tagged frames on the ingress are allowed (default).
 984  * Access: RW
 985  */
 986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
 987
 988 /* reg_spaft_allow_tagged
 989  * When set, tagged frames on the ingress are allowed (default).
 990  * Access: RW
 991  */
 992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
 993
 994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
 995                                         bool allow_untagged)
 996 {
 997         MLXSW_REG_ZERO(spaft, payload);
 998         mlxsw_reg_spaft_local_port_set(payload, local_port);
 999         mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
1000         mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
1001         mlxsw_reg_spaft_allow_tagged_set(payload, true);
1002 }
1003
1004 /* SFGC - Switch Flooding Group Configuration
1005  * ------------------------------------------
1006  * The following register controls the association of flooding tables and MIDs
1007  * to packet types used for flooding.
1008  */
1009 #define MLXSW_REG_SFGC_ID 0x2011
1010 #define MLXSW_REG_SFGC_LEN 0x10
1011
1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1013
1014 enum mlxsw_reg_sfgc_type {
1015         MLXSW_REG_SFGC_TYPE_BROADCAST,
1016         MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1017         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1018         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1019         MLXSW_REG_SFGC_TYPE_RESERVED,
1020         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1021         MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1022         MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1023         MLXSW_REG_SFGC_TYPE_MAX,
1024 };
1025
1026 /* reg_sfgc_type
1027  * The traffic type to reach the flooding table.
1028  * Access: Index
1029  */
1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1031
1032 enum mlxsw_reg_sfgc_bridge_type {
1033         MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
1034         MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
1035 };
1036
1037 /* reg_sfgc_bridge_type
1038  * Access: Index
1039  *
1040  * Note: SwitchX-2 only supports 802.1Q mode.
1041  */
1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1043
1044 enum mlxsw_flood_table_type {
1045         MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1046         MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1047         MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1048         MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1049         MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1050 };
1051
1052 /* reg_sfgc_table_type
1053  * See mlxsw_flood_table_type
1054  * Access: RW
1055  *
1056  * Note: FID offset and FID types are not supported in SwitchX-2.
1057  */
1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1059
1060 /* reg_sfgc_flood_table
1061  * Flooding table index to associate with the specific type on the specific
1062  * switch partition.
1063  * Access: RW
1064  */
1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1066
1067 /* reg_sfgc_mid
1068  * The multicast ID for the swid. Not supported for Spectrum
1069  * Access: RW
1070  */
1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1072
1073 /* reg_sfgc_counter_set_type
1074  * Counter Set Type for flow counters.
1075  * Access: RW
1076  */
1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1078
1079 /* reg_sfgc_counter_index
1080  * Counter Index for flow counters.
1081  * Access: RW
1082  */
1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1084
1085 static inline void
1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1087                     enum mlxsw_reg_sfgc_bridge_type bridge_type,
1088                     enum mlxsw_flood_table_type table_type,
1089                     unsigned int flood_table)
1090 {
1091         MLXSW_REG_ZERO(sfgc, payload);
1092         mlxsw_reg_sfgc_type_set(payload, type);
1093         mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1094         mlxsw_reg_sfgc_table_type_set(payload, table_type);
1095         mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1096         mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1097 }
1098
1099 /* SFTR - Switch Flooding Table Register
1100  * -------------------------------------
1101  * The switch flooding table is used for flooding packet replication. The table
1102  * defines a bit mask of ports for packet replication.
1103  */
1104 #define MLXSW_REG_SFTR_ID 0x2012
1105 #define MLXSW_REG_SFTR_LEN 0x420
1106
1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN);
1108
1109 /* reg_sftr_swid
1110  * Switch partition ID with which to associate the port.
1111  * Access: Index
1112  */
1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1114
1115 /* reg_sftr_flood_table
1116  * Flooding table index to associate with the specific type on the specific
1117  * switch partition.
1118  * Access: Index
1119  */
1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1121
1122 /* reg_sftr_index
1123  * Index. Used as an index into the Flooding Table in case the table is
1124  * configured to use VID / FID or FID Offset.
1125  * Access: Index
1126  */
1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1128
1129 /* reg_sftr_table_type
1130  * See mlxsw_flood_table_type
1131  * Access: RW
1132  */
1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1134
1135 /* reg_sftr_range
1136  * Range of entries to update
1137  * Access: Index
1138  */
1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1140
1141 /* reg_sftr_port
1142  * Local port membership (1 bit per port).
1143  * Access: RW
1144  */
1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1146
1147 /* reg_sftr_cpu_port_mask
1148  * CPU port mask (1 bit per port).
1149  * Access: W
1150  */
1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1152
1153 static inline void mlxsw_reg_sftr_pack(char *payload,
1154                                        unsigned int flood_table,
1155                                        unsigned int index,
1156                                        enum mlxsw_flood_table_type table_type,
1157                                        unsigned int range, u8 port, bool set)
1158 {
1159         MLXSW_REG_ZERO(sftr, payload);
1160         mlxsw_reg_sftr_swid_set(payload, 0);
1161         mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1162         mlxsw_reg_sftr_index_set(payload, index);
1163         mlxsw_reg_sftr_table_type_set(payload, table_type);
1164         mlxsw_reg_sftr_range_set(payload, range);
1165         mlxsw_reg_sftr_port_set(payload, port, set);
1166         mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1167 }
1168
1169 /* SFDF - Switch Filtering DB Flush
1170  * --------------------------------
1171  * The switch filtering DB flush register is used to flush the FDB.
1172  * Note that FDB notifications are flushed as well.
1173  */
1174 #define MLXSW_REG_SFDF_ID 0x2013
1175 #define MLXSW_REG_SFDF_LEN 0x14
1176
1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1178
1179 /* reg_sfdf_swid
1180  * Switch partition ID.
1181  * Access: Index
1182  */
1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1184
1185 enum mlxsw_reg_sfdf_flush_type {
1186         MLXSW_REG_SFDF_FLUSH_PER_SWID,
1187         MLXSW_REG_SFDF_FLUSH_PER_FID,
1188         MLXSW_REG_SFDF_FLUSH_PER_PORT,
1189         MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1190         MLXSW_REG_SFDF_FLUSH_PER_LAG,
1191         MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1192         MLXSW_REG_SFDF_FLUSH_PER_NVE,
1193         MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1194 };
1195
1196 /* reg_sfdf_flush_type
1197  * Flush type.
1198  * 0 - All SWID dynamic entries are flushed.
1199  * 1 - All FID dynamic entries are flushed.
1200  * 2 - All dynamic entries pointing to port are flushed.
1201  * 3 - All FID dynamic entries pointing to port are flushed.
1202  * 4 - All dynamic entries pointing to LAG are flushed.
1203  * 5 - All FID dynamic entries pointing to LAG are flushed.
1204  * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1205  *     flushed.
1206  * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1207  *     flushed, per FID.
1208  * Access: RW
1209  */
1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1211
1212 /* reg_sfdf_flush_static
1213  * Static.
1214  * 0 - Flush only dynamic entries.
1215  * 1 - Flush both dynamic and static entries.
1216  * Access: RW
1217  */
1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1219
1220 static inline void mlxsw_reg_sfdf_pack(char *payload,
1221                                        enum mlxsw_reg_sfdf_flush_type type)
1222 {
1223         MLXSW_REG_ZERO(sfdf, payload);
1224         mlxsw_reg_sfdf_flush_type_set(payload, type);
1225         mlxsw_reg_sfdf_flush_static_set(payload, true);
1226 }
1227
1228 /* reg_sfdf_fid
1229  * FID to flush.
1230  * Access: RW
1231  */
1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1233
1234 /* reg_sfdf_system_port
1235  * Port to flush.
1236  * Access: RW
1237  */
1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1239
1240 /* reg_sfdf_port_fid_system_port
1241  * Port to flush, pointed to by FID.
1242  * Access: RW
1243  */
1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1245
1246 /* reg_sfdf_lag_id
1247  * LAG ID to flush.
1248  * Access: RW
1249  */
1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1251
1252 /* reg_sfdf_lag_fid_lag_id
1253  * LAG ID to flush, pointed to by FID.
1254  * Access: RW
1255  */
1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1257
1258 /* SLDR - Switch LAG Descriptor Register
1259  * -----------------------------------------
1260  * The switch LAG descriptor register is populated by LAG descriptors.
1261  * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1262  * max_lag-1.
1263  */
1264 #define MLXSW_REG_SLDR_ID 0x2014
1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1266
1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1268
1269 enum mlxsw_reg_sldr_op {
1270         /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1271         MLXSW_REG_SLDR_OP_LAG_CREATE,
1272         MLXSW_REG_SLDR_OP_LAG_DESTROY,
1273         /* Ports that appear in the list have the Distributor enabled */
1274         MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1275         /* Removes ports from the disributor list */
1276         MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1277 };
1278
1279 /* reg_sldr_op
1280  * Operation.
1281  * Access: RW
1282  */
1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1284
1285 /* reg_sldr_lag_id
1286  * LAG identifier. The lag_id is the index into the LAG descriptor table.
1287  * Access: Index
1288  */
1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1290
1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1292 {
1293         MLXSW_REG_ZERO(sldr, payload);
1294         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1295         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1296 }
1297
1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1299 {
1300         MLXSW_REG_ZERO(sldr, payload);
1301         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1302         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1303 }
1304
1305 /* reg_sldr_num_ports
1306  * The number of member ports of the LAG.
1307  * Reserved for Create / Destroy operations
1308  * For Add / Remove operations - indicates the number of ports in the list.
1309  * Access: RW
1310  */
1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1312
1313 /* reg_sldr_system_port
1314  * System port.
1315  * Access: RW
1316  */
1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1318
1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1320                                                     u8 local_port)
1321 {
1322         MLXSW_REG_ZERO(sldr, payload);
1323         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1324         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1325         mlxsw_reg_sldr_num_ports_set(payload, 1);
1326         mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1327 }
1328
1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1330                                                        u8 local_port)
1331 {
1332         MLXSW_REG_ZERO(sldr, payload);
1333         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1334         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1335         mlxsw_reg_sldr_num_ports_set(payload, 1);
1336         mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1337 }
1338
1339 /* SLCR - Switch LAG Configuration 2 Register
1340  * -------------------------------------------
1341  * The Switch LAG Configuration register is used for configuring the
1342  * LAG properties of the switch.
1343  */
1344 #define MLXSW_REG_SLCR_ID 0x2015
1345 #define MLXSW_REG_SLCR_LEN 0x10
1346
1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1348
1349 enum mlxsw_reg_slcr_pp {
1350         /* Global Configuration (for all ports) */
1351         MLXSW_REG_SLCR_PP_GLOBAL,
1352         /* Per port configuration, based on local_port field */
1353         MLXSW_REG_SLCR_PP_PER_PORT,
1354 };
1355
1356 /* reg_slcr_pp
1357  * Per Port Configuration
1358  * Note: Reading at Global mode results in reading port 1 configuration.
1359  * Access: Index
1360  */
1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1362
1363 /* reg_slcr_local_port
1364  * Local port number
1365  * Supported from CPU port
1366  * Not supported from router port
1367  * Reserved when pp = Global Configuration
1368  * Access: Index
1369  */
1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1371
1372 enum mlxsw_reg_slcr_type {
1373         MLXSW_REG_SLCR_TYPE_CRC, /* default */
1374         MLXSW_REG_SLCR_TYPE_XOR,
1375         MLXSW_REG_SLCR_TYPE_RANDOM,
1376 };
1377
1378 /* reg_slcr_type
1379  * Hash type
1380  * Access: RW
1381  */
1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1383
1384 /* Ingress port */
1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT         BIT(0)
1386 /* SMAC - for IPv4 and IPv6 packets */
1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP         BIT(1)
1388 /* SMAC - for non-IP packets */
1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP      BIT(2)
1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1391         (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1392          MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1393 /* DMAC - for IPv4 and IPv6 packets */
1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP         BIT(3)
1395 /* DMAC - for non-IP packets */
1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP      BIT(4)
1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1398         (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1399          MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1400 /* Ethertype - for IPv4 and IPv6 packets */
1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP    BIT(5)
1402 /* Ethertype - for non-IP packets */
1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1405         (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1406          MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1407 /* VLAN ID - for IPv4 and IPv6 packets */
1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP       BIT(7)
1409 /* VLAN ID - for non-IP packets */
1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP    BIT(8)
1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1412         (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1413          MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1414 /* Source IP address (can be IPv4 or IPv6) */
1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP             BIT(9)
1416 /* Destination IP address (can be IPv4 or IPv6) */
1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP             BIT(10)
1418 /* TCP/UDP source port */
1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT           BIT(11)
1420 /* TCP/UDP destination port*/
1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT           BIT(12)
1422 /* IPv4 Protocol/IPv6 Next Header */
1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO         BIT(13)
1424 /* IPv6 Flow label */
1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL       BIT(14)
1426 /* SID - FCoE source ID */
1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID        BIT(15)
1428 /* DID - FCoE destination ID */
1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID        BIT(16)
1430 /* OXID - FCoE originator exchange ID */
1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID       BIT(17)
1432 /* Destination QP number - for RoCE packets */
1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP        BIT(19)
1434
1435 /* reg_slcr_lag_hash
1436  * LAG hashing configuration. This is a bitmask, in which each set
1437  * bit includes the corresponding item in the LAG hash calculation.
1438  * The default lag_hash contains SMAC, DMAC, VLANID and
1439  * Ethertype (for all packet types).
1440  * Access: RW
1441  */
1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1443
1444 /* reg_slcr_seed
1445  * LAG seed value. The seed is the same for all ports.
1446  * Access: RW
1447  */
1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1449
1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1451 {
1452         MLXSW_REG_ZERO(slcr, payload);
1453         mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1454         mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1455         mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1456         mlxsw_reg_slcr_seed_set(payload, seed);
1457 }
1458
1459 /* SLCOR - Switch LAG Collector Register
1460  * -------------------------------------
1461  * The Switch LAG Collector register controls the Local Port membership
1462  * in a LAG and enablement of the collector.
1463  */
1464 #define MLXSW_REG_SLCOR_ID 0x2016
1465 #define MLXSW_REG_SLCOR_LEN 0x10
1466
1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1468
1469 enum mlxsw_reg_slcor_col {
1470         /* Port is added with collector disabled */
1471         MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1472         MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1473         MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1474         MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1475 };
1476
1477 /* reg_slcor_col
1478  * Collector configuration
1479  * Access: RW
1480  */
1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1482
1483 /* reg_slcor_local_port
1484  * Local port number
1485  * Not supported for CPU port
1486  * Access: Index
1487  */
1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1489
1490 /* reg_slcor_lag_id
1491  * LAG Identifier. Index into the LAG descriptor table.
1492  * Access: Index
1493  */
1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1495
1496 /* reg_slcor_port_index
1497  * Port index in the LAG list. Only valid on Add Port to LAG col.
1498  * Valid range is from 0 to cap_max_lag_members-1
1499  * Access: RW
1500  */
1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1502
1503 static inline void mlxsw_reg_slcor_pack(char *payload,
1504                                         u8 local_port, u16 lag_id,
1505                                         enum mlxsw_reg_slcor_col col)
1506 {
1507         MLXSW_REG_ZERO(slcor, payload);
1508         mlxsw_reg_slcor_col_set(payload, col);
1509         mlxsw_reg_slcor_local_port_set(payload, local_port);
1510         mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1511 }
1512
1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1514                                                  u8 local_port, u16 lag_id,
1515                                                  u8 port_index)
1516 {
1517         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1518                              MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1519         mlxsw_reg_slcor_port_index_set(payload, port_index);
1520 }
1521
1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1523                                                     u8 local_port, u16 lag_id)
1524 {
1525         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1526                              MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1527 }
1528
1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1530                                                    u8 local_port, u16 lag_id)
1531 {
1532         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1533                              MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1534 }
1535
1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1537                                                     u8 local_port, u16 lag_id)
1538 {
1539         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1540                              MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1541 }
1542
1543 /* SPMLR - Switch Port MAC Learning Register
1544  * -----------------------------------------
1545  * Controls the Switch MAC learning policy per port.
1546  */
1547 #define MLXSW_REG_SPMLR_ID 0x2018
1548 #define MLXSW_REG_SPMLR_LEN 0x8
1549
1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1551
1552 /* reg_spmlr_local_port
1553  * Local port number.
1554  * Access: Index
1555  */
1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1557
1558 /* reg_spmlr_sub_port
1559  * Virtual port within the physical port.
1560  * Should be set to 0 when virtual ports are not enabled on the port.
1561  * Access: Index
1562  */
1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1564
1565 enum mlxsw_reg_spmlr_learn_mode {
1566         MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1567         MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1568         MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1569 };
1570
1571 /* reg_spmlr_learn_mode
1572  * Learning mode on the port.
1573  * 0 - Learning disabled.
1574  * 2 - Learning enabled.
1575  * 3 - Security mode.
1576  *
1577  * In security mode the switch does not learn MACs on the port, but uses the
1578  * SMAC to see if it exists on another ingress port. If so, the packet is
1579  * classified as a bad packet and is discarded unless the software registers
1580  * to receive port security error packets usign HPKT.
1581  */
1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1583
1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1585                                         enum mlxsw_reg_spmlr_learn_mode mode)
1586 {
1587         MLXSW_REG_ZERO(spmlr, payload);
1588         mlxsw_reg_spmlr_local_port_set(payload, local_port);
1589         mlxsw_reg_spmlr_sub_port_set(payload, 0);
1590         mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1591 }
1592
1593 /* SVFA - Switch VID to FID Allocation Register
1594  * --------------------------------------------
1595  * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1596  * virtualized ports.
1597  */
1598 #define MLXSW_REG_SVFA_ID 0x201C
1599 #define MLXSW_REG_SVFA_LEN 0x10
1600
1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1602
1603 /* reg_svfa_swid
1604  * Switch partition ID.
1605  * Access: Index
1606  */
1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1608
1609 /* reg_svfa_local_port
1610  * Local port number.
1611  * Access: Index
1612  *
1613  * Note: Reserved for 802.1Q FIDs.
1614  */
1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1616
1617 enum mlxsw_reg_svfa_mt {
1618         MLXSW_REG_SVFA_MT_VID_TO_FID,
1619         MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1620 };
1621
1622 /* reg_svfa_mapping_table
1623  * Mapping table:
1624  * 0 - VID to FID
1625  * 1 - {Port, VID} to FID
1626  * Access: Index
1627  *
1628  * Note: Reserved for SwitchX-2.
1629  */
1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1631
1632 /* reg_svfa_v
1633  * Valid.
1634  * Valid if set.
1635  * Access: RW
1636  *
1637  * Note: Reserved for SwitchX-2.
1638  */
1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1640
1641 /* reg_svfa_fid
1642  * Filtering ID.
1643  * Access: RW
1644  */
1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1646
1647 /* reg_svfa_vid
1648  * VLAN ID.
1649  * Access: Index
1650  */
1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1652
1653 /* reg_svfa_counter_set_type
1654  * Counter set type for flow counters.
1655  * Access: RW
1656  *
1657  * Note: Reserved for SwitchX-2.
1658  */
1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1660
1661 /* reg_svfa_counter_index
1662  * Counter index for flow counters.
1663  * Access: RW
1664  *
1665  * Note: Reserved for SwitchX-2.
1666  */
1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1668
1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1670                                        enum mlxsw_reg_svfa_mt mt, bool valid,
1671                                        u16 fid, u16 vid)
1672 {
1673         MLXSW_REG_ZERO(svfa, payload);
1674         local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1675         mlxsw_reg_svfa_swid_set(payload, 0);
1676         mlxsw_reg_svfa_local_port_set(payload, local_port);
1677         mlxsw_reg_svfa_mapping_table_set(payload, mt);
1678         mlxsw_reg_svfa_v_set(payload, valid);
1679         mlxsw_reg_svfa_fid_set(payload, fid);
1680         mlxsw_reg_svfa_vid_set(payload, vid);
1681 }
1682
1683 /* SVPE - Switch Virtual-Port Enabling Register
1684  * --------------------------------------------
1685  * Enables port virtualization.
1686  */
1687 #define MLXSW_REG_SVPE_ID 0x201E
1688 #define MLXSW_REG_SVPE_LEN 0x4
1689
1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1691
1692 /* reg_svpe_local_port
1693  * Local port number
1694  * Access: Index
1695  *
1696  * Note: CPU port is not supported (uses VLAN mode only).
1697  */
1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1699
1700 /* reg_svpe_vp_en
1701  * Virtual port enable.
1702  * 0 - Disable, VLAN mode (VID to FID).
1703  * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1704  * Access: RW
1705  */
1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1707
1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1709                                        bool enable)
1710 {
1711         MLXSW_REG_ZERO(svpe, payload);
1712         mlxsw_reg_svpe_local_port_set(payload, local_port);
1713         mlxsw_reg_svpe_vp_en_set(payload, enable);
1714 }
1715
1716 /* SFMR - Switch FID Management Register
1717  * -------------------------------------
1718  * Creates and configures FIDs.
1719  */
1720 #define MLXSW_REG_SFMR_ID 0x201F
1721 #define MLXSW_REG_SFMR_LEN 0x18
1722
1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1724
1725 enum mlxsw_reg_sfmr_op {
1726         MLXSW_REG_SFMR_OP_CREATE_FID,
1727         MLXSW_REG_SFMR_OP_DESTROY_FID,
1728 };
1729
1730 /* reg_sfmr_op
1731  * Operation.
1732  * 0 - Create or edit FID.
1733  * 1 - Destroy FID.
1734  * Access: WO
1735  */
1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1737
1738 /* reg_sfmr_fid
1739  * Filtering ID.
1740  * Access: Index
1741  */
1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1743
1744 /* reg_sfmr_fid_offset
1745  * FID offset.
1746  * Used to point into the flooding table selected by SFGC register if
1747  * the table is of type FID-Offset. Otherwise, this field is reserved.
1748  * Access: RW
1749  */
1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1751
1752 /* reg_sfmr_vtfp
1753  * Valid Tunnel Flood Pointer.
1754  * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1755  * Access: RW
1756  *
1757  * Note: Reserved for 802.1Q FIDs.
1758  */
1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1760
1761 /* reg_sfmr_nve_tunnel_flood_ptr
1762  * Underlay Flooding and BC Pointer.
1763  * Used as a pointer to the first entry of the group based link lists of
1764  * flooding or BC entries (for NVE tunnels).
1765  * Access: RW
1766  */
1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1768
1769 /* reg_sfmr_vv
1770  * VNI Valid.
1771  * If not set, then vni is reserved.
1772  * Access: RW
1773  *
1774  * Note: Reserved for 802.1Q FIDs.
1775  */
1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1777
1778 /* reg_sfmr_vni
1779  * Virtual Network Identifier.
1780  * Access: RW
1781  *
1782  * Note: A given VNI can only be assigned to one FID.
1783  */
1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1785
1786 static inline void mlxsw_reg_sfmr_pack(char *payload,
1787                                        enum mlxsw_reg_sfmr_op op, u16 fid,
1788                                        u16 fid_offset)
1789 {
1790         MLXSW_REG_ZERO(sfmr, payload);
1791         mlxsw_reg_sfmr_op_set(payload, op);
1792         mlxsw_reg_sfmr_fid_set(payload, fid);
1793         mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1794         mlxsw_reg_sfmr_vtfp_set(payload, false);
1795         mlxsw_reg_sfmr_vv_set(payload, false);
1796 }
1797
1798 /* SPVMLR - Switch Port VLAN MAC Learning Register
1799  * -----------------------------------------------
1800  * Controls the switch MAC learning policy per {Port, VID}.
1801  */
1802 #define MLXSW_REG_SPVMLR_ID 0x2020
1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1807                               MLXSW_REG_SPVMLR_REC_LEN * \
1808                               MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1809
1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1811
1812 /* reg_spvmlr_local_port
1813  * Local ingress port.
1814  * Access: Index
1815  *
1816  * Note: CPU port is not supported.
1817  */
1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1819
1820 /* reg_spvmlr_num_rec
1821  * Number of records to update.
1822  * Access: OP
1823  */
1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1825
1826 /* reg_spvmlr_rec_learn_enable
1827  * 0 - Disable learning for {Port, VID}.
1828  * 1 - Enable learning for {Port, VID}.
1829  * Access: RW
1830  */
1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1832                      31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1833
1834 /* reg_spvmlr_rec_vid
1835  * VLAN ID to be added/removed from port or for querying.
1836  * Access: Index
1837  */
1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1839                      MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1840
1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1842                                          u16 vid_begin, u16 vid_end,
1843                                          bool learn_enable)
1844 {
1845         int num_rec = vid_end - vid_begin + 1;
1846         int i;
1847
1848         WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1849
1850         MLXSW_REG_ZERO(spvmlr, payload);
1851         mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1852         mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1853
1854         for (i = 0; i < num_rec; i++) {
1855                 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1856                 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1857         }
1858 }
1859
1860 /* CWTP - Congetion WRED ECN TClass Profile
1861  * ----------------------------------------
1862  * Configures the profiles for queues of egress port and traffic class
1863  */
1864 #define MLXSW_REG_CWTP_ID 0x2802
1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28
1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
1867 #define MLXSW_REG_CWTP_LEN 0x40
1868
1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
1870
1871 /* reg_cwtp_local_port
1872  * Local port number
1873  * Not supported for CPU port
1874  * Access: Index
1875  */
1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
1877
1878 /* reg_cwtp_traffic_class
1879  * Traffic Class to configure
1880  * Access: Index
1881  */
1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
1883
1884 /* reg_cwtp_profile_min
1885  * Minimum Average Queue Size of the profile in cells.
1886  * Access: RW
1887  */
1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
1889                      0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
1890
1891 /* reg_cwtp_profile_percent
1892  * Percentage of WRED and ECN marking for maximum Average Queue size
1893  * Range is 0 to 100, units of integer percentage
1894  * Access: RW
1895  */
1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
1897                      24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1898
1899 /* reg_cwtp_profile_max
1900  * Maximum Average Queue size of the profile in cells
1901  * Access: RW
1902  */
1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
1904                      0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1905
1906 #define MLXSW_REG_CWTP_MIN_VALUE 64
1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2
1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
1909
1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
1911                                        u8 traffic_class)
1912 {
1913         int i;
1914
1915         MLXSW_REG_ZERO(cwtp, payload);
1916         mlxsw_reg_cwtp_local_port_set(payload, local_port);
1917         mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
1918
1919         for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
1920                 mlxsw_reg_cwtp_profile_min_set(payload, i,
1921                                                MLXSW_REG_CWTP_MIN_VALUE);
1922                 mlxsw_reg_cwtp_profile_max_set(payload, i,
1923                                                MLXSW_REG_CWTP_MIN_VALUE);
1924         }
1925 }
1926
1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
1928
1929 static inline void
1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
1931                             u32 probability)
1932 {
1933         u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
1934
1935         mlxsw_reg_cwtp_profile_min_set(payload, index, min);
1936         mlxsw_reg_cwtp_profile_max_set(payload, index, max);
1937         mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
1938 }
1939
1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping
1941  * ---------------------------------------------------
1942  * The CWTPM register maps each egress port and traffic class to profile num.
1943  */
1944 #define MLXSW_REG_CWTPM_ID 0x2803
1945 #define MLXSW_REG_CWTPM_LEN 0x44
1946
1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
1948
1949 /* reg_cwtpm_local_port
1950  * Local port number
1951  * Not supported for CPU port
1952  * Access: Index
1953  */
1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
1955
1956 /* reg_cwtpm_traffic_class
1957  * Traffic Class to configure
1958  * Access: Index
1959  */
1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
1961
1962 /* reg_cwtpm_ew
1963  * Control enablement of WRED for traffic class:
1964  * 0 - Disable
1965  * 1 - Enable
1966  * Access: RW
1967  */
1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
1969
1970 /* reg_cwtpm_ee
1971  * Control enablement of ECN for traffic class:
1972  * 0 - Disable
1973  * 1 - Enable
1974  * Access: RW
1975  */
1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
1977
1978 /* reg_cwtpm_tcp_g
1979  * TCP Green Profile.
1980  * Index of the profile within {port, traffic class} to use.
1981  * 0 for disabling both WRED and ECN for this type of traffic.
1982  * Access: RW
1983  */
1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
1985
1986 /* reg_cwtpm_tcp_y
1987  * TCP Yellow Profile.
1988  * Index of the profile within {port, traffic class} to use.
1989  * 0 for disabling both WRED and ECN for this type of traffic.
1990  * Access: RW
1991  */
1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
1993
1994 /* reg_cwtpm_tcp_r
1995  * TCP Red Profile.
1996  * Index of the profile within {port, traffic class} to use.
1997  * 0 for disabling both WRED and ECN for this type of traffic.
1998  * Access: RW
1999  */
2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2001
2002 /* reg_cwtpm_ntcp_g
2003  * Non-TCP Green Profile.
2004  * Index of the profile within {port, traffic class} to use.
2005  * 0 for disabling both WRED and ECN for this type of traffic.
2006  * Access: RW
2007  */
2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2009
2010 /* reg_cwtpm_ntcp_y
2011  * Non-TCP Yellow Profile.
2012  * Index of the profile within {port, traffic class} to use.
2013  * 0 for disabling both WRED and ECN for this type of traffic.
2014  * Access: RW
2015  */
2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2017
2018 /* reg_cwtpm_ntcp_r
2019  * Non-TCP Red Profile.
2020  * Index of the profile within {port, traffic class} to use.
2021  * 0 for disabling both WRED and ECN for this type of traffic.
2022  * Access: RW
2023  */
2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2025
2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0
2027
2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
2029                                         u8 traffic_class, u8 profile,
2030                                         bool wred, bool ecn)
2031 {
2032         MLXSW_REG_ZERO(cwtpm, payload);
2033         mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2034         mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2035         mlxsw_reg_cwtpm_ew_set(payload, wred);
2036         mlxsw_reg_cwtpm_ee_set(payload, ecn);
2037         mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
2038         mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
2039         mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
2040         mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
2041         mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
2042         mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
2043 }
2044
2045 /* PGCR - Policy-Engine General Configuration Register
2046  * ---------------------------------------------------
2047  * This register configures general Policy-Engine settings.
2048  */
2049 #define MLXSW_REG_PGCR_ID 0x3001
2050 #define MLXSW_REG_PGCR_LEN 0x20
2051
2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2053
2054 /* reg_pgcr_default_action_pointer_base
2055  * Default action pointer base. Each region has a default action pointer
2056  * which is equal to default_action_pointer_base + region_id.
2057  * Access: RW
2058  */
2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2060
2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2062 {
2063         MLXSW_REG_ZERO(pgcr, payload);
2064         mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2065 }
2066
2067 /* PPBT - Policy-Engine Port Binding Table
2068  * ---------------------------------------
2069  * This register is used for configuration of the Port Binding Table.
2070  */
2071 #define MLXSW_REG_PPBT_ID 0x3002
2072 #define MLXSW_REG_PPBT_LEN 0x14
2073
2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2075
2076 enum mlxsw_reg_pxbt_e {
2077         MLXSW_REG_PXBT_E_IACL,
2078         MLXSW_REG_PXBT_E_EACL,
2079 };
2080
2081 /* reg_ppbt_e
2082  * Access: Index
2083  */
2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2085
2086 enum mlxsw_reg_pxbt_op {
2087         MLXSW_REG_PXBT_OP_BIND,
2088         MLXSW_REG_PXBT_OP_UNBIND,
2089 };
2090
2091 /* reg_ppbt_op
2092  * Access: RW
2093  */
2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2095
2096 /* reg_ppbt_local_port
2097  * Local port. Not including CPU port.
2098  * Access: Index
2099  */
2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8);
2101
2102 /* reg_ppbt_g
2103  * group - When set, the binding is of an ACL group. When cleared,
2104  * the binding is of an ACL.
2105  * Must be set to 1 for Spectrum.
2106  * Access: RW
2107  */
2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2109
2110 /* reg_ppbt_acl_info
2111  * ACL/ACL group identifier. If the g bit is set, this field should hold
2112  * the acl_group_id, else it should hold the acl_id.
2113  * Access: RW
2114  */
2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2116
2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2118                                        enum mlxsw_reg_pxbt_op op,
2119                                        u8 local_port, u16 acl_info)
2120 {
2121         MLXSW_REG_ZERO(ppbt, payload);
2122         mlxsw_reg_ppbt_e_set(payload, e);
2123         mlxsw_reg_ppbt_op_set(payload, op);
2124         mlxsw_reg_ppbt_local_port_set(payload, local_port);
2125         mlxsw_reg_ppbt_g_set(payload, true);
2126         mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2127 }
2128
2129 /* PACL - Policy-Engine ACL Register
2130  * ---------------------------------
2131  * This register is used for configuration of the ACL.
2132  */
2133 #define MLXSW_REG_PACL_ID 0x3004
2134 #define MLXSW_REG_PACL_LEN 0x70
2135
2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2137
2138 /* reg_pacl_v
2139  * Valid. Setting the v bit makes the ACL valid. It should not be cleared
2140  * while the ACL is bounded to either a port, VLAN or ACL rule.
2141  * Access: RW
2142  */
2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2144
2145 /* reg_pacl_acl_id
2146  * An identifier representing the ACL (managed by software)
2147  * Range 0 .. cap_max_acl_regions - 1
2148  * Access: Index
2149  */
2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2151
2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2153
2154 /* reg_pacl_tcam_region_info
2155  * Opaque object that represents a TCAM region.
2156  * Obtained through PTAR register.
2157  * Access: RW
2158  */
2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2160                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2161
2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2163                                        bool valid, const char *tcam_region_info)
2164 {
2165         MLXSW_REG_ZERO(pacl, payload);
2166         mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2167         mlxsw_reg_pacl_v_set(payload, valid);
2168         mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2169 }
2170
2171 /* PAGT - Policy-Engine ACL Group Table
2172  * ------------------------------------
2173  * This register is used for configuration of the ACL Group Table.
2174  */
2175 #define MLXSW_REG_PAGT_ID 0x3005
2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30
2177 #define MLXSW_REG_PAGT_ACL_LEN 4
2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2180                 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2181
2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2183
2184 /* reg_pagt_size
2185  * Number of ACLs in the group.
2186  * Size 0 invalidates a group.
2187  * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
2188  * Total number of ACLs in all groups must be lower or equal
2189  * to cap_max_acl_tot_groups
2190  * Note: a group which is binded must not be invalidated
2191  * Access: Index
2192  */
2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2194
2195 /* reg_pagt_acl_group_id
2196  * An identifier (numbered from 0..cap_max_acl_groups-1) representing
2197  * the ACL Group identifier (managed by software).
2198  * Access: Index
2199  */
2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2201
2202 /* reg_pagt_multi
2203  * Multi-ACL
2204  * 0 - This ACL is the last ACL in the multi-ACL
2205  * 1 - This ACL is part of a multi-ACL
2206  * Access: RW
2207  */
2208 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2209
2210 /* reg_pagt_acl_id
2211  * ACL identifier
2212  * Access: RW
2213  */
2214 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2215
2216 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2217 {
2218         MLXSW_REG_ZERO(pagt, payload);
2219         mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2220 }
2221
2222 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2223                                               u16 acl_id, bool multi)
2224 {
2225         u8 size = mlxsw_reg_pagt_size_get(payload);
2226
2227         if (index >= size)
2228                 mlxsw_reg_pagt_size_set(payload, index + 1);
2229         mlxsw_reg_pagt_multi_set(payload, index, multi);
2230         mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2231 }
2232
2233 /* PTAR - Policy-Engine TCAM Allocation Register
2234  * ---------------------------------------------
2235  * This register is used for allocation of regions in the TCAM.
2236  * Note: Query method is not supported on this register.
2237  */
2238 #define MLXSW_REG_PTAR_ID 0x3006
2239 #define MLXSW_REG_PTAR_BASE_LEN 0x20
2240 #define MLXSW_REG_PTAR_KEY_ID_LEN 1
2241 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2242 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2243                 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2244
2245 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2246
2247 enum mlxsw_reg_ptar_op {
2248         /* allocate a TCAM region */
2249         MLXSW_REG_PTAR_OP_ALLOC,
2250         /* resize a TCAM region */
2251         MLXSW_REG_PTAR_OP_RESIZE,
2252         /* deallocate TCAM region */
2253         MLXSW_REG_PTAR_OP_FREE,
2254         /* test allocation */
2255         MLXSW_REG_PTAR_OP_TEST,
2256 };
2257
2258 /* reg_ptar_op
2259  * Access: OP
2260  */
2261 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2262
2263 /* reg_ptar_action_set_type
2264  * Type of action set to be used on this region.
2265  * For Spectrum and Spectrum-2, this is always type 2 - "flexible"
2266  * Access: WO
2267  */
2268 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2269
2270 enum mlxsw_reg_ptar_key_type {
2271         MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */
2272         MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */
2273 };
2274
2275 /* reg_ptar_key_type
2276  * TCAM key type for the region.
2277  * Access: WO
2278  */
2279 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2280
2281 /* reg_ptar_region_size
2282  * TCAM region size. When allocating/resizing this is the requested size,
2283  * the response is the actual size. Note that actual size may be
2284  * larger than requested.
2285  * Allowed range 1 .. cap_max_rules-1
2286  * Reserved during op deallocate.
2287  * Access: WO
2288  */
2289 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2290
2291 /* reg_ptar_region_id
2292  * Region identifier
2293  * Range 0 .. cap_max_regions-1
2294  * Access: Index
2295  */
2296 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2297
2298 /* reg_ptar_tcam_region_info
2299  * Opaque object that represents the TCAM region.
2300  * Returned when allocating a region.
2301  * Provided by software for ACL generation and region deallocation and resize.
2302  * Access: RW
2303  */
2304 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2305                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2306
2307 /* reg_ptar_flexible_key_id
2308  * Identifier of the Flexible Key.
2309  * Only valid if key_type == "FLEX_KEY"
2310  * The key size will be rounded up to one of the following values:
2311  * 9B, 18B, 36B, 54B.
2312  * This field is reserved for in resize operation.
2313  * Access: WO
2314  */
2315 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2316                     MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2317
2318 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2319                                        enum mlxsw_reg_ptar_key_type key_type,
2320                                        u16 region_size, u16 region_id,
2321                                        const char *tcam_region_info)
2322 {
2323         MLXSW_REG_ZERO(ptar, payload);
2324         mlxsw_reg_ptar_op_set(payload, op);
2325         mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */
2326         mlxsw_reg_ptar_key_type_set(payload, key_type);
2327         mlxsw_reg_ptar_region_size_set(payload, region_size);
2328         mlxsw_reg_ptar_region_id_set(payload, region_id);
2329         mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2330 }
2331
2332 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2333                                               u16 key_id)
2334 {
2335         mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2336 }
2337
2338 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2339 {
2340         mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2341 }
2342
2343 /* PPBS - Policy-Engine Policy Based Switching Register
2344  * ----------------------------------------------------
2345  * This register retrieves and sets Policy Based Switching Table entries.
2346  */
2347 #define MLXSW_REG_PPBS_ID 0x300C
2348 #define MLXSW_REG_PPBS_LEN 0x14
2349
2350 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2351
2352 /* reg_ppbs_pbs_ptr
2353  * Index into the PBS table.
2354  * For Spectrum, the index points to the KVD Linear.
2355  * Access: Index
2356  */
2357 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2358
2359 /* reg_ppbs_system_port
2360  * Unique port identifier for the final destination of the packet.
2361  * Access: RW
2362  */
2363 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2364
2365 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2366                                        u16 system_port)
2367 {
2368         MLXSW_REG_ZERO(ppbs, payload);
2369         mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2370         mlxsw_reg_ppbs_system_port_set(payload, system_port);
2371 }
2372
2373 /* PRCR - Policy-Engine Rules Copy Register
2374  * ----------------------------------------
2375  * This register is used for accessing rules within a TCAM region.
2376  */
2377 #define MLXSW_REG_PRCR_ID 0x300D
2378 #define MLXSW_REG_PRCR_LEN 0x40
2379
2380 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2381
2382 enum mlxsw_reg_prcr_op {
2383         /* Move rules. Moves the rules from "tcam_region_info" starting
2384          * at offset "offset" to "dest_tcam_region_info"
2385          * at offset "dest_offset."
2386          */
2387         MLXSW_REG_PRCR_OP_MOVE,
2388         /* Copy rules. Copies the rules from "tcam_region_info" starting
2389          * at offset "offset" to "dest_tcam_region_info"
2390          * at offset "dest_offset."
2391          */
2392         MLXSW_REG_PRCR_OP_COPY,
2393 };
2394
2395 /* reg_prcr_op
2396  * Access: OP
2397  */
2398 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2399
2400 /* reg_prcr_offset
2401  * Offset within the source region to copy/move from.
2402  * Access: Index
2403  */
2404 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2405
2406 /* reg_prcr_size
2407  * The number of rules to copy/move.
2408  * Access: WO
2409  */
2410 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2411
2412 /* reg_prcr_tcam_region_info
2413  * Opaque object that represents the source TCAM region.
2414  * Access: Index
2415  */
2416 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2417                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2418
2419 /* reg_prcr_dest_offset
2420  * Offset within the source region to copy/move to.
2421  * Access: Index
2422  */
2423 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2424
2425 /* reg_prcr_dest_tcam_region_info
2426  * Opaque object that represents the destination TCAM region.
2427  * Access: Index
2428  */
2429 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2430                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2431
2432 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2433                                        const char *src_tcam_region_info,
2434                                        u16 src_offset,
2435                                        const char *dest_tcam_region_info,
2436                                        u16 dest_offset, u16 size)
2437 {
2438         MLXSW_REG_ZERO(prcr, payload);
2439         mlxsw_reg_prcr_op_set(payload, op);
2440         mlxsw_reg_prcr_offset_set(payload, src_offset);
2441         mlxsw_reg_prcr_size_set(payload, size);
2442         mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2443                                                   src_tcam_region_info);
2444         mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2445         mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2446                                                        dest_tcam_region_info);
2447 }
2448
2449 /* PEFA - Policy-Engine Extended Flexible Action Register
2450  * ------------------------------------------------------
2451  * This register is used for accessing an extended flexible action entry
2452  * in the central KVD Linear Database.
2453  */
2454 #define MLXSW_REG_PEFA_ID 0x300F
2455 #define MLXSW_REG_PEFA_LEN 0xB0
2456
2457 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2458
2459 /* reg_pefa_index
2460  * Index in the KVD Linear Centralized Database.
2461  * Access: Index
2462  */
2463 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2464
2465 /* reg_pefa_a
2466  * Index in the KVD Linear Centralized Database.
2467  * Activity
2468  * For a new entry: set if ca=0, clear if ca=1
2469  * Set if a packet lookup has hit on the specific entry
2470  * Access: RO
2471  */
2472 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2473
2474 /* reg_pefa_ca
2475  * Clear activity
2476  * When write: activity is according to this field
2477  * When read: after reading the activity is cleared according to ca
2478  * Access: OP
2479  */
2480 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2481
2482 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2483
2484 /* reg_pefa_flex_action_set
2485  * Action-set to perform when rule is matched.
2486  * Must be zero padded if action set is shorter.
2487  * Access: RW
2488  */
2489 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2490
2491 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2492                                        const char *flex_action_set)
2493 {
2494         MLXSW_REG_ZERO(pefa, payload);
2495         mlxsw_reg_pefa_index_set(payload, index);
2496         mlxsw_reg_pefa_ca_set(payload, ca);
2497         if (flex_action_set)
2498                 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2499                                                          flex_action_set);
2500 }
2501
2502 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2503 {
2504         *p_a = mlxsw_reg_pefa_a_get(payload);
2505 }
2506
2507 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register
2508  * --------------------------------------------------------------
2509  * This register is used for binding Multicast router to an ACL group
2510  * that serves the MC router.
2511  * This register is not supported by SwitchX/-2 and Spectrum.
2512  */
2513 #define MLXSW_REG_PEMRBT_ID 0x3014
2514 #define MLXSW_REG_PEMRBT_LEN 0x14
2515
2516 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
2517
2518 enum mlxsw_reg_pemrbt_protocol {
2519         MLXSW_REG_PEMRBT_PROTO_IPV4,
2520         MLXSW_REG_PEMRBT_PROTO_IPV6,
2521 };
2522
2523 /* reg_pemrbt_protocol
2524  * Access: Index
2525  */
2526 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
2527
2528 /* reg_pemrbt_group_id
2529  * ACL group identifier.
2530  * Range 0..cap_max_acl_groups-1
2531  * Access: RW
2532  */
2533 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
2534
2535 static inline void
2536 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
2537                       u16 group_id)
2538 {
2539         MLXSW_REG_ZERO(pemrbt, payload);
2540         mlxsw_reg_pemrbt_protocol_set(payload, protocol);
2541         mlxsw_reg_pemrbt_group_id_set(payload, group_id);
2542 }
2543
2544 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
2545  * -----------------------------------------------------
2546  * This register is used for accessing rules within a TCAM region.
2547  * It is a new version of PTCE in order to support wider key,
2548  * mask and action within a TCAM region. This register is not supported
2549  * by SwitchX and SwitchX-2.
2550  */
2551 #define MLXSW_REG_PTCE2_ID 0x3017
2552 #define MLXSW_REG_PTCE2_LEN 0x1D8
2553
2554 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2555
2556 /* reg_ptce2_v
2557  * Valid.
2558  * Access: RW
2559  */
2560 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2561
2562 /* reg_ptce2_a
2563  * Activity. Set if a packet lookup has hit on the specific entry.
2564  * To clear the "a" bit, use "clear activity" op or "clear on read" op.
2565  * Access: RO
2566  */
2567 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2568
2569 enum mlxsw_reg_ptce2_op {
2570         /* Read operation. */
2571         MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2572         /* clear on read operation. Used to read entry
2573          * and clear Activity bit.
2574          */
2575         MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2576         /* Write operation. Used to write a new entry to the table.
2577          * All R/W fields are relevant for new entry. Activity bit is set
2578          * for new entries - Note write with v = 0 will delete the entry.
2579          */
2580         MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2581         /* Update action. Only action set will be updated. */
2582         MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2583         /* Clear activity. A bit is cleared for the entry. */
2584         MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2585 };
2586
2587 /* reg_ptce2_op
2588  * Access: OP
2589  */
2590 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2591
2592 /* reg_ptce2_offset
2593  * Access: Index
2594  */
2595 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2596
2597 /* reg_ptce2_priority
2598  * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.
2599  * Note: priority does not have to be unique per rule.
2600  * Within a region, higher priority should have lower offset (no limitation
2601  * between regions in a multi-region).
2602  * Access: RW
2603  */
2604 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2605
2606 /* reg_ptce2_tcam_region_info
2607  * Opaque object that represents the TCAM region.
2608  * Access: Index
2609  */
2610 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2611                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2612
2613 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2614
2615 /* reg_ptce2_flex_key_blocks
2616  * ACL Key.
2617  * Access: RW
2618  */
2619 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2620                MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2621
2622 /* reg_ptce2_mask
2623  * mask- in the same size as key. A bit that is set directs the TCAM
2624  * to compare the corresponding bit in key. A bit that is clear directs
2625  * the TCAM to ignore the corresponding bit in key.
2626  * Access: RW
2627  */
2628 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2629                MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2630
2631 /* reg_ptce2_flex_action_set
2632  * ACL action set.
2633  * Access: RW
2634  */
2635 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2636                MLXSW_REG_FLEX_ACTION_SET_LEN);
2637
2638 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2639                                         enum mlxsw_reg_ptce2_op op,
2640                                         const char *tcam_region_info,
2641                                         u16 offset, u32 priority)
2642 {
2643         MLXSW_REG_ZERO(ptce2, payload);
2644         mlxsw_reg_ptce2_v_set(payload, valid);
2645         mlxsw_reg_ptce2_op_set(payload, op);
2646         mlxsw_reg_ptce2_offset_set(payload, offset);
2647         mlxsw_reg_ptce2_priority_set(payload, priority);
2648         mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2649 }
2650
2651 /* PERPT - Policy-Engine ERP Table Register
2652  * ----------------------------------------
2653  * This register adds and removes eRPs from the eRP table.
2654  */
2655 #define MLXSW_REG_PERPT_ID 0x3021
2656 #define MLXSW_REG_PERPT_LEN 0x80
2657
2658 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2659
2660 /* reg_perpt_erpt_bank
2661  * eRP table bank.
2662  * Range 0 .. cap_max_erp_table_banks - 1
2663  * Access: Index
2664  */
2665 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2666
2667 /* reg_perpt_erpt_index
2668  * Index to eRP table within the eRP bank.
2669  * Range is 0 .. cap_max_erp_table_bank_size - 1
2670  * Access: Index
2671  */
2672 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2673
2674 enum mlxsw_reg_perpt_key_size {
2675         MLXSW_REG_PERPT_KEY_SIZE_2KB,
2676         MLXSW_REG_PERPT_KEY_SIZE_4KB,
2677         MLXSW_REG_PERPT_KEY_SIZE_8KB,
2678         MLXSW_REG_PERPT_KEY_SIZE_12KB,
2679 };
2680
2681 /* reg_perpt_key_size
2682  * Access: OP
2683  */
2684 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2685
2686 /* reg_perpt_bf_bypass
2687  * 0 - The eRP is used only if bloom filter state is set for the given
2688  * rule.
2689  * 1 - The eRP is used regardless of bloom filter state.
2690  * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass
2691  * Access: RW
2692  */
2693 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2694
2695 /* reg_perpt_erp_id
2696  * eRP ID for use by the rules.
2697  * Access: RW
2698  */
2699 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2700
2701 /* reg_perpt_erpt_base_bank
2702  * Base eRP table bank, points to head of erp_vector
2703  * Range is 0 .. cap_max_erp_table_banks - 1
2704  * Access: OP
2705  */
2706 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2707
2708 /* reg_perpt_erpt_base_index
2709  * Base index to eRP table within the eRP bank
2710  * Range is 0 .. cap_max_erp_table_bank_size - 1
2711  * Access: OP
2712  */
2713 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2714
2715 /* reg_perpt_erp_index_in_vector
2716  * eRP index in the vector.
2717  * Access: OP
2718  */
2719 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2720
2721 /* reg_perpt_erp_vector
2722  * eRP vector.
2723  * Access: OP
2724  */
2725 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2726
2727 /* reg_perpt_mask
2728  * Mask
2729  * 0 - A-TCAM will ignore the bit in key
2730  * 1 - A-TCAM will compare the bit in key
2731  * Access: RW
2732  */
2733 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2734
2735 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
2736                                                    unsigned long *erp_vector,
2737                                                    unsigned long size)
2738 {
2739         unsigned long bit;
2740
2741         for_each_set_bit(bit, erp_vector, size)
2742                 mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
2743 }
2744
2745 static inline void
2746 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
2747                      enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
2748                      u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
2749                      char *mask)
2750 {
2751         MLXSW_REG_ZERO(perpt, payload);
2752         mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
2753         mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
2754         mlxsw_reg_perpt_key_size_set(payload, key_size);
2755         mlxsw_reg_perpt_bf_bypass_set(payload, false);
2756         mlxsw_reg_perpt_erp_id_set(payload, erp_id);
2757         mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
2758         mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
2759         mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
2760         mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
2761 }
2762
2763 /* PERAR - Policy-Engine Region Association Register
2764  * -------------------------------------------------
2765  * This register associates a hw region for region_id's. Changing on the fly
2766  * is supported by the device.
2767  */
2768 #define MLXSW_REG_PERAR_ID 0x3026
2769 #define MLXSW_REG_PERAR_LEN 0x08
2770
2771 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
2772
2773 /* reg_perar_region_id
2774  * Region identifier
2775  * Range 0 .. cap_max_regions-1
2776  * Access: Index
2777  */
2778 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
2779
2780 static inline unsigned int
2781 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
2782 {
2783         return DIV_ROUND_UP(block_num, 4);
2784 }
2785
2786 /* reg_perar_hw_region
2787  * HW Region
2788  * Range 0 .. cap_max_regions-1
2789  * Default: hw_region = region_id
2790  * For a 8 key block region, 2 consecutive regions are used
2791  * For a 12 key block region, 3 consecutive regions are used
2792  * Access: RW
2793  */
2794 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
2795
2796 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
2797                                         u16 hw_region)
2798 {
2799         MLXSW_REG_ZERO(perar, payload);
2800         mlxsw_reg_perar_region_id_set(payload, region_id);
2801         mlxsw_reg_perar_hw_region_set(payload, hw_region);
2802 }
2803
2804 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3
2805  * -----------------------------------------------------
2806  * This register is a new version of PTCE-V2 in order to support the
2807  * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
2808  */
2809 #define MLXSW_REG_PTCE3_ID 0x3027
2810 #define MLXSW_REG_PTCE3_LEN 0xF0
2811
2812 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
2813
2814 /* reg_ptce3_v
2815  * Valid.
2816  * Access: RW
2817  */
2818 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
2819
2820 enum mlxsw_reg_ptce3_op {
2821         /* Write operation. Used to write a new entry to the table.
2822          * All R/W fields are relevant for new entry. Activity bit is set
2823          * for new entries. Write with v = 0 will delete the entry. Must
2824          * not be used if an entry exists.
2825          */
2826          MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
2827          /* Update operation */
2828          MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
2829          /* Read operation */
2830          MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
2831 };
2832
2833 /* reg_ptce3_op
2834  * Access: OP
2835  */
2836 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
2837
2838 /* reg_ptce3_priority
2839  * Priority of the rule. Higher values win.
2840  * For Spectrum-2 range is 1..cap_kvd_size - 1
2841  * Note: Priority does not have to be unique per rule.
2842  * Access: RW
2843  */
2844 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
2845
2846 /* reg_ptce3_tcam_region_info
2847  * Opaque object that represents the TCAM region.
2848  * Access: Index
2849  */
2850 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
2851                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2852
2853 /* reg_ptce3_flex2_key_blocks
2854  * ACL key. The key must be masked according to eRP (if exists) or
2855  * according to master mask.
2856  * Access: Index
2857  */
2858 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
2859                MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2860
2861 /* reg_ptce3_erp_id
2862  * eRP ID.
2863  * Access: Index
2864  */
2865 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
2866
2867 /* reg_ptce3_delta_start
2868  * Start point of delta_value and delta_mask, in bits. Must not exceed
2869  * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.
2870  * Access: Index
2871  */
2872 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
2873
2874 /* reg_ptce3_delta_mask
2875  * Delta mask.
2876  * 0 - Ignore relevant bit in delta_value
2877  * 1 - Compare relevant bit in delta_value
2878  * Delta mask must not be set for reserved fields in the key blocks.
2879  * Note: No delta when no eRPs. Thus, for regions with
2880  * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.
2881  * Access: Index
2882  */
2883 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
2884
2885 /* reg_ptce3_delta_value
2886  * Delta value.
2887  * Bits which are masked by delta_mask must be 0.
2888  * Access: Index
2889  */
2890 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
2891
2892 /* reg_ptce3_prune_vector
2893  * Pruning vector relative to the PERPT.erp_id.
2894  * Used for reducing lookups.
2895  * 0 - NEED: Do a lookup using the eRP.
2896  * 1 - PRUNE: Do not perform a lookup using the eRP.
2897  * Maybe be modified by PEAPBL and PEAPBM.
2898  * Note: In Spectrum-2, a region of 8 key blocks must be set to either
2899  * all 1's or all 0's.
2900  * Access: RW
2901  */
2902 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
2903
2904 /* reg_ptce3_prune_ctcam
2905  * Pruning on C-TCAM. Used for reducing lookups.
2906  * 0 - NEED: Do a lookup in the C-TCAM.
2907  * 1 - PRUNE: Do not perform a lookup in the C-TCAM.
2908  * Access: RW
2909  */
2910 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
2911
2912 /* reg_ptce3_large_exists
2913  * Large entry key ID exists.
2914  * Within the region:
2915  * 0 - SINGLE: The large_entry_key_id is not currently in use.
2916  * For rule insert: The MSB of the key (blocks 6..11) will be added.
2917  * For rule delete: The MSB of the key will be removed.
2918  * 1 - NON_SINGLE: The large_entry_key_id is currently in use.
2919  * For rule insert: The MSB of the key (blocks 6..11) will not be added.
2920  * For rule delete: The MSB of the key will not be removed.
2921  * Access: WO
2922  */
2923 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
2924
2925 /* reg_ptce3_large_entry_key_id
2926  * Large entry key ID.
2927  * A key for 12 key blocks rules. Reserved when region has less than 12 key
2928  * blocks. Must be different for different keys which have the same common
2929  * 6 key blocks (MSB, blocks 6..11) key within a region.
2930  * Range is 0..cap_max_pe_large_key_id - 1
2931  * Access: RW
2932  */
2933 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
2934
2935 /* reg_ptce3_action_pointer
2936  * Pointer to action.
2937  * Range is 0..cap_max_kvd_action_sets - 1
2938  * Access: RW
2939  */
2940 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
2941
2942 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
2943                                         enum mlxsw_reg_ptce3_op op,
2944                                         u32 priority,
2945                                         const char *tcam_region_info,
2946                                         const char *key, u8 erp_id,
2947                                         u16 delta_start, u8 delta_mask,
2948                                         u8 delta_value, bool large_exists,
2949                                         u32 lkey_id, u32 action_pointer)
2950 {
2951         MLXSW_REG_ZERO(ptce3, payload);
2952         mlxsw_reg_ptce3_v_set(payload, valid);
2953         mlxsw_reg_ptce3_op_set(payload, op);
2954         mlxsw_reg_ptce3_priority_set(payload, priority);
2955         mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
2956         mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
2957         mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
2958         mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
2959         mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
2960         mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
2961         mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
2962         mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
2963         mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
2964 }
2965
2966 /* PERCR - Policy-Engine Region Configuration Register
2967  * ---------------------------------------------------
2968  * This register configures the region parameters. The region_id must be
2969  * allocated.
2970  */
2971 #define MLXSW_REG_PERCR_ID 0x302A
2972 #define MLXSW_REG_PERCR_LEN 0x80
2973
2974 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
2975
2976 /* reg_percr_region_id
2977  * Region identifier.
2978  * Range 0..cap_max_regions-1
2979  * Access: Index
2980  */
2981 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
2982
2983 /* reg_percr_atcam_ignore_prune
2984  * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.
2985  * Access: RW
2986  */
2987 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
2988
2989 /* reg_percr_ctcam_ignore_prune
2990  * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.
2991  * Access: RW
2992  */
2993 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
2994
2995 /* reg_percr_bf_bypass
2996  * Bloom filter bypass.
2997  * 0 - Bloom filter is used (default)
2998  * 1 - Bloom filter is bypassed. The bypass is an OR condition of
2999  * region_id or eRP. See PERPT.bf_bypass
3000  * Access: RW
3001  */
3002 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3003
3004 /* reg_percr_master_mask
3005  * Master mask. Logical OR mask of all masks of all rules of a region
3006  * (both A-TCAM and C-TCAM). When there are no eRPs
3007  * (erpt_pointer_valid = 0), then this provides the mask.
3008  * Access: RW
3009  */
3010 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3011
3012 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3013 {
3014         MLXSW_REG_ZERO(percr, payload);
3015         mlxsw_reg_percr_region_id_set(payload, region_id);
3016         mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
3017         mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
3018         mlxsw_reg_percr_bf_bypass_set(payload, false);
3019 }
3020
3021 /* PERERP - Policy-Engine Region eRP Register
3022  * ------------------------------------------
3023  * This register configures the region eRP. The region_id must be
3024  * allocated.
3025  */
3026 #define MLXSW_REG_PERERP_ID 0x302B
3027 #define MLXSW_REG_PERERP_LEN 0x1C
3028
3029 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3030
3031 /* reg_pererp_region_id
3032  * Region identifier.
3033  * Range 0..cap_max_regions-1
3034  * Access: Index
3035  */
3036 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3037
3038 /* reg_pererp_ctcam_le
3039  * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
3040  * Access: RW
3041  */
3042 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3043
3044 /* reg_pererp_erpt_pointer_valid
3045  * erpt_pointer is valid.
3046  * Access: RW
3047  */
3048 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3049
3050 /* reg_pererp_erpt_bank_pointer
3051  * Pointer to eRP table bank. May be modified at any time.
3052  * Range 0..cap_max_erp_table_banks-1
3053  * Reserved when erpt_pointer_valid = 0
3054  */
3055 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3056
3057 /* reg_pererp_erpt_pointer
3058  * Pointer to eRP table within the eRP bank. Can be changed for an
3059  * existing region.
3060  * Range 0..cap_max_erp_table_size-1
3061  * Reserved when erpt_pointer_valid = 0
3062  * Access: RW
3063  */
3064 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3065
3066 /* reg_pererp_erpt_vector
3067  * Vector of allowed eRP indexes starting from erpt_pointer within the
3068  * erpt_bank_pointer. Next entries will be in next bank.
3069  * Note that eRP index is used and not eRP ID.
3070  * Reserved when erpt_pointer_valid = 0
3071  * Access: RW
3072  */
3073 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3074
3075 /* reg_pererp_master_rp_id
3076  * Master RP ID. When there are no eRPs, then this provides the eRP ID
3077  * for the lookup. Can be changed for an existing region.
3078  * Reserved when erpt_pointer_valid = 1
3079  * Access: RW
3080  */
3081 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3082
3083 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3084                                                     unsigned long *erp_vector,
3085                                                     unsigned long size)
3086 {
3087         unsigned long bit;
3088
3089         for_each_set_bit(bit, erp_vector, size)
3090                 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
3091 }
3092
3093 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3094                                          bool ctcam_le, bool erpt_pointer_valid,
3095                                          u8 erpt_bank_pointer, u8 erpt_pointer,
3096                                          u8 master_rp_id)
3097 {
3098         MLXSW_REG_ZERO(pererp, payload);
3099         mlxsw_reg_pererp_region_id_set(payload, region_id);
3100         mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
3101         mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
3102         mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
3103         mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
3104         mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
3105 }
3106
3107 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register
3108  * ----------------------------------------------------------------
3109  * This register configures the Bloom filter entries.
3110  */
3111 #define MLXSW_REG_PEABFE_ID 0x3022
3112 #define MLXSW_REG_PEABFE_BASE_LEN 0x10
3113 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3114 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3115 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3116                               MLXSW_REG_PEABFE_BF_REC_LEN * \
3117                               MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3118
3119 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3120
3121 /* reg_peabfe_size
3122  * Number of BF entries to be updated.
3123  * Range 1..256
3124  * Access: Op
3125  */
3126 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3127
3128 /* reg_peabfe_bf_entry_state
3129  * Bloom filter state
3130  * 0 - Clear
3131  * 1 - Set
3132  * Access: RW
3133  */
3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3135                      MLXSW_REG_PEABFE_BASE_LEN, 31, 1,
3136                      MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3137
3138 /* reg_peabfe_bf_entry_bank
3139  * Bloom filter bank ID
3140  * Range 0..cap_max_erp_table_banks-1
3141  * Access: Index
3142  */
3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3144                      MLXSW_REG_PEABFE_BASE_LEN, 24, 4,
3145                      MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3146
3147 /* reg_peabfe_bf_entry_index
3148  * Bloom filter entry index
3149  * Range 0..2^cap_max_bf_log-1
3150  * Access: Index
3151  */
3152 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3153                      MLXSW_REG_PEABFE_BASE_LEN, 0, 24,
3154                      MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3155
3156 static inline void mlxsw_reg_peabfe_pack(char *payload)
3157 {
3158         MLXSW_REG_ZERO(peabfe, payload);
3159 }
3160
3161 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3162                                              u8 state, u8 bank, u32 bf_index)
3163 {
3164         u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
3165
3166         if (rec_index >= num_rec)
3167                 mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
3168         mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
3169         mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
3170         mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
3171 }
3172
3173 /* IEDR - Infrastructure Entry Delete Register
3174  * ----------------------------------------------------
3175  * This register is used for deleting entries from the entry tables.
3176  * It is legitimate to attempt to delete a nonexisting entry (the device will
3177  * respond as a good flow).
3178  */
3179 #define MLXSW_REG_IEDR_ID 0x3804
3180 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */
3181 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */
3182 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3183 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN +   \
3184                             MLXSW_REG_IEDR_REC_LEN *    \
3185                             MLXSW_REG_IEDR_REC_MAX_COUNT)
3186
3187 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3188
3189 /* reg_iedr_num_rec
3190  * Number of records.
3191  * Access: OP
3192  */
3193 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3194
3195 /* reg_iedr_rec_type
3196  * Resource type.
3197  * Access: OP
3198  */
3199 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3200                      MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3201
3202 /* reg_iedr_rec_size
3203  * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
3204  * Access: OP
3205  */
3206 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11,
3207                      MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3208
3209 /* reg_iedr_rec_index_start
3210  * Resource index start.
3211  * Access: OP
3212  */
3213 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3214                      MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3215
3216 static inline void mlxsw_reg_iedr_pack(char *payload)
3217 {
3218         MLXSW_REG_ZERO(iedr, payload);
3219 }
3220
3221 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3222                                            u8 rec_type, u16 rec_size,
3223                                            u32 rec_index_start)
3224 {
3225         u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3226
3227         if (rec_index >= num_rec)
3228                 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3229         mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3230         mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3231         mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3232 }
3233
3234 /* QPTS - QoS Priority Trust State Register
3235  * ----------------------------------------
3236  * This register controls the port policy to calculate the switch priority and
3237  * packet color based on incoming packet fields.
3238  */
3239 #define MLXSW_REG_QPTS_ID 0x4002
3240 #define MLXSW_REG_QPTS_LEN 0x8
3241
3242 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3243
3244 /* reg_qpts_local_port
3245  * Local port number.
3246  * Access: Index
3247  *
3248  * Note: CPU port is supported.
3249  */
3250 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8);
3251
3252 enum mlxsw_reg_qpts_trust_state {
3253         MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3254         MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */
3255 };
3256
3257 /* reg_qpts_trust_state
3258  * Trust state for a given port.
3259  * Access: RW
3260  */
3261 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3262
3263 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port,
3264                                        enum mlxsw_reg_qpts_trust_state ts)
3265 {
3266         MLXSW_REG_ZERO(qpts, payload);
3267
3268         mlxsw_reg_qpts_local_port_set(payload, local_port);
3269         mlxsw_reg_qpts_trust_state_set(payload, ts);
3270 }
3271
3272 /* QPCR - QoS Policer Configuration Register
3273  * -----------------------------------------
3274  * The QPCR register is used to create policers - that limit
3275  * the rate of bytes or packets via some trap group.
3276  */
3277 #define MLXSW_REG_QPCR_ID 0x4004
3278 #define MLXSW_REG_QPCR_LEN 0x28
3279
3280 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3281
3282 enum mlxsw_reg_qpcr_g {
3283         MLXSW_REG_QPCR_G_GLOBAL = 2,
3284         MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3285 };
3286
3287 /* reg_qpcr_g
3288  * The policer type.
3289  * Access: Index
3290  */
3291 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3292
3293 /* reg_qpcr_pid
3294  * Policer ID.
3295  * Access: Index
3296  */
3297 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3298
3299 /* reg_qpcr_color_aware
3300  * Is the policer aware of colors.
3301  * Must be 0 (unaware) for cpu port.
3302  * Access: RW for unbounded policer. RO for bounded policer.
3303  */
3304 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3305
3306 /* reg_qpcr_bytes
3307  * Is policer limit is for bytes per sec or packets per sec.
3308  * 0 - packets
3309  * 1 - bytes
3310  * Access: RW for unbounded policer. RO for bounded policer.
3311  */
3312 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3313
3314 enum mlxsw_reg_qpcr_ir_units {
3315         MLXSW_REG_QPCR_IR_UNITS_M,
3316         MLXSW_REG_QPCR_IR_UNITS_K,
3317 };
3318
3319 /* reg_qpcr_ir_units
3320  * Policer's units for cir and eir fields (for bytes limits only)
3321  * 1 - 10^3
3322  * 0 - 10^6
3323  * Access: OP
3324  */
3325 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3326
3327 enum mlxsw_reg_qpcr_rate_type {
3328         MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3329         MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3330 };
3331
3332 /* reg_qpcr_rate_type
3333  * Policer can have one limit (single rate) or 2 limits with specific operation
3334  * for packets that exceed the lower rate but not the upper one.
3335  * (For cpu port must be single rate)
3336  * Access: RW for unbounded policer. RO for bounded policer.
3337  */
3338 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3339
3340 /* reg_qpc_cbs
3341  * Policer's committed burst size.
3342  * The policer is working with time slices of 50 nano sec. By default every
3343  * slice is granted the proportionate share of the committed rate. If we want to
3344  * allow a slice to exceed that share (while still keeping the rate per sec) we
3345  * can allow burst. The burst size is between the default proportionate share
3346  * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
3347  * committed rate will result in exceeding the rate). The burst size must be a
3348  * log of 2 and will be determined by 2^cbs.
3349  * Access: RW
3350  */
3351 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3352
3353 /* reg_qpcr_cir
3354  * Policer's committed rate.
3355  * The rate used for sungle rate, the lower rate for double rate.
3356  * For bytes limits, the rate will be this value * the unit from ir_units.
3357  * (Resolution error is up to 1%).
3358  * Access: RW
3359  */
3360 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3361
3362 /* reg_qpcr_eir
3363  * Policer's exceed rate.
3364  * The higher rate for double rate, reserved for single rate.
3365  * Lower rate for double rate policer.
3366  * For bytes limits, the rate will be this value * the unit from ir_units.
3367  * (Resolution error is up to 1%).
3368  * Access: RW
3369  */
3370 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3371
3372 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3373
3374 /* reg_qpcr_exceed_action.
3375  * What to do with packets between the 2 limits for double rate.
3376  * Access: RW for unbounded policer. RO for bounded policer.
3377  */
3378 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3379
3380 enum mlxsw_reg_qpcr_action {
3381         /* Discard */
3382         MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3383         /* Forward and set color to red.
3384          * If the packet is intended to cpu port, it will be dropped.
3385          */
3386         MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3387 };
3388
3389 /* reg_qpcr_violate_action
3390  * What to do with packets that cross the cir limit (for single rate) or the eir
3391  * limit (for double rate).
3392  * Access: RW for unbounded policer. RO for bounded policer.
3393  */
3394 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3395
3396 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3397                                        enum mlxsw_reg_qpcr_ir_units ir_units,
3398                                        bool bytes, u32 cir, u16 cbs)
3399 {
3400         MLXSW_REG_ZERO(qpcr, payload);
3401         mlxsw_reg_qpcr_pid_set(payload, pid);
3402         mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3403         mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3404         mlxsw_reg_qpcr_violate_action_set(payload,
3405                                           MLXSW_REG_QPCR_ACTION_DISCARD);
3406         mlxsw_reg_qpcr_cir_set(payload, cir);
3407         mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3408         mlxsw_reg_qpcr_bytes_set(payload, bytes);
3409         mlxsw_reg_qpcr_cbs_set(payload, cbs);
3410 }
3411
3412 /* QTCT - QoS Switch Traffic Class Table
3413  * -------------------------------------
3414  * Configures the mapping between the packet switch priority and the
3415  * traffic class on the transmit port.
3416  */
3417 #define MLXSW_REG_QTCT_ID 0x400A
3418 #define MLXSW_REG_QTCT_LEN 0x08
3419
3420 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3421
3422 /* reg_qtct_local_port
3423  * Local port number.
3424  * Access: Index
3425  *
3426  * Note: CPU port is not supported.
3427  */
3428 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
3429
3430 /* reg_qtct_sub_port
3431  * Virtual port within the physical port.
3432  * Should be set to 0 when virtual ports are not enabled on the port.
3433  * Access: Index
3434  */
3435 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3436
3437 /* reg_qtct_switch_prio
3438  * Switch priority.
3439  * Access: Index
3440  */
3441 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3442
3443 /* reg_qtct_tclass
3444  * Traffic class.
3445  * Default values:
3446  * switch_prio 0 : tclass 1
3447  * switch_prio 1 : tclass 0
3448  * switch_prio i : tclass i, for i > 1
3449  * Access: RW
3450  */
3451 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3452
3453 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
3454                                        u8 switch_prio, u8 tclass)
3455 {
3456         MLXSW_REG_ZERO(qtct, payload);
3457         mlxsw_reg_qtct_local_port_set(payload, local_port);
3458         mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3459         mlxsw_reg_qtct_tclass_set(payload, tclass);
3460 }
3461
3462 /* QEEC - QoS ETS Element Configuration Register
3463  * ---------------------------------------------
3464  * Configures the ETS elements.
3465  */
3466 #define MLXSW_REG_QEEC_ID 0x400D
3467 #define MLXSW_REG_QEEC_LEN 0x20
3468
3469 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3470
3471 /* reg_qeec_local_port
3472  * Local port number.
3473  * Access: Index
3474  *
3475  * Note: CPU port is supported.
3476  */
3477 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
3478
3479 enum mlxsw_reg_qeec_hr {
3480         MLXSW_REG_QEEC_HIERARCY_PORT,
3481         MLXSW_REG_QEEC_HIERARCY_GROUP,
3482         MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3483         MLXSW_REG_QEEC_HIERARCY_TC,
3484 };
3485
3486 /* reg_qeec_element_hierarchy
3487  * 0 - Port
3488  * 1 - Group
3489  * 2 - Subgroup
3490  * 3 - Traffic Class
3491  * Access: Index
3492  */
3493 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3494
3495 /* reg_qeec_element_index
3496  * The index of the element in the hierarchy.
3497  * Access: Index
3498  */
3499 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3500
3501 /* reg_qeec_next_element_index
3502  * The index of the next (lower) element in the hierarchy.
3503  * Access: RW
3504  *
3505  * Note: Reserved for element_hierarchy 0.
3506  */
3507 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3508
3509 /* reg_qeec_mise
3510  * Min shaper configuration enable. Enables configuration of the min
3511  * shaper on this ETS element
3512  * 0 - Disable
3513  * 1 - Enable
3514  * Access: RW
3515  */
3516 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3517
3518 /* reg_qeec_ptps
3519  * PTP shaper
3520  * 0: regular shaper mode
3521  * 1: PTP oriented shaper
3522  * Allowed only for hierarchy 0
3523  * Not supported for CPU port
3524  * Note that ptps mode may affect the shaper rates of all hierarchies
3525  * Supported only on Spectrum-1
3526  * Access: RW
3527  */
3528 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
3529
3530 enum {
3531         MLXSW_REG_QEEC_BYTES_MODE,
3532         MLXSW_REG_QEEC_PACKETS_MODE,
3533 };
3534
3535 /* reg_qeec_pb
3536  * Packets or bytes mode.
3537  * 0 - Bytes mode
3538  * 1 - Packets mode
3539  * Access: RW
3540  *
3541  * Note: Used for max shaper configuration. For Spectrum, packets mode
3542  * is supported only for traffic classes of CPU port.
3543  */
3544 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3545
3546 /* The smallest permitted min shaper rate. */
3547 #define MLXSW_REG_QEEC_MIS_MIN  200000          /* Kbps */
3548
3549 /* reg_qeec_min_shaper_rate
3550  * Min shaper information rate.
3551  * For CPU port, can only be configured for port hierarchy.
3552  * When in bytes mode, value is specified in units of 1000bps.
3553  * Access: RW
3554  */
3555 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3556
3557 /* reg_qeec_mase
3558  * Max shaper configuration enable. Enables configuration of the max
3559  * shaper on this ETS element.
3560  * 0 - Disable
3561  * 1 - Enable
3562  * Access: RW
3563  */
3564 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3565
3566 /* A large max rate will disable the max shaper. */
3567 #define MLXSW_REG_QEEC_MAS_DIS  200000000       /* Kbps */
3568
3569 /* reg_qeec_max_shaper_rate
3570  * Max shaper information rate.
3571  * For CPU port, can only be configured for port hierarchy.
3572  * When in bytes mode, value is specified in units of 1000bps.
3573  * Access: RW
3574  */
3575 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
3576
3577 /* reg_qeec_de
3578  * DWRR configuration enable. Enables configuration of the dwrr and
3579  * dwrr_weight.
3580  * 0 - Disable
3581  * 1 - Enable
3582  * Access: RW
3583  */
3584 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3585
3586 /* reg_qeec_dwrr
3587  * Transmission selection algorithm to use on the link going down from
3588  * the ETS element.
3589  * 0 - Strict priority
3590  * 1 - DWRR
3591  * Access: RW
3592  */
3593 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3594
3595 /* reg_qeec_dwrr_weight
3596  * DWRR weight on the link going down from the ETS element. The
3597  * percentage of bandwidth guaranteed to an ETS element within
3598  * its hierarchy. The sum of all weights across all ETS elements
3599  * within one hierarchy should be equal to 100. Reserved when
3600  * transmission selection algorithm is strict priority.
3601  * Access: RW
3602  */
3603 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3604
3605 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3606                                        enum mlxsw_reg_qeec_hr hr, u8 index,
3607                                        u8 next_index)
3608 {
3609         MLXSW_REG_ZERO(qeec, payload);
3610         mlxsw_reg_qeec_local_port_set(payload, local_port);
3611         mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3612         mlxsw_reg_qeec_element_index_set(payload, index);
3613         mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3614 }
3615
3616 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port,
3617                                             bool ptps)
3618 {
3619         MLXSW_REG_ZERO(qeec, payload);
3620         mlxsw_reg_qeec_local_port_set(payload, local_port);
3621         mlxsw_reg_qeec_element_hierarchy_set(payload,
3622                                              MLXSW_REG_QEEC_HIERARCY_PORT);
3623         mlxsw_reg_qeec_ptps_set(payload, ptps);
3624 }
3625
3626 /* QRWE - QoS ReWrite Enable
3627  * -------------------------
3628  * This register configures the rewrite enable per receive port.
3629  */
3630 #define MLXSW_REG_QRWE_ID 0x400F
3631 #define MLXSW_REG_QRWE_LEN 0x08
3632
3633 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3634
3635 /* reg_qrwe_local_port
3636  * Local port number.
3637  * Access: Index
3638  *
3639  * Note: CPU port is supported. No support for router port.
3640  */
3641 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8);
3642
3643 /* reg_qrwe_dscp
3644  * Whether to enable DSCP rewrite (default is 0, don't rewrite).
3645  * Access: RW
3646  */
3647 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3648
3649 /* reg_qrwe_pcp
3650  * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
3651  * Access: RW
3652  */
3653 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3654
3655 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port,
3656                                        bool rewrite_pcp, bool rewrite_dscp)
3657 {
3658         MLXSW_REG_ZERO(qrwe, payload);
3659         mlxsw_reg_qrwe_local_port_set(payload, local_port);
3660         mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3661         mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3662 }
3663
3664 /* QPDSM - QoS Priority to DSCP Mapping
3665  * ------------------------------------
3666  * QoS Priority to DSCP Mapping Register
3667  */
3668 #define MLXSW_REG_QPDSM_ID 0x4011
3669 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */
3670 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */
3671 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3672 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN +                 \
3673                              MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN *       \
3674                              MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3675
3676 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3677
3678 /* reg_qpdsm_local_port
3679  * Local Port. Supported for data packets from CPU port.
3680  * Access: Index
3681  */
3682 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8);
3683
3684 /* reg_qpdsm_prio_entry_color0_e
3685  * Enable update of the entry for color 0 and a given port.
3686  * Access: WO
3687  */
3688 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
3689                      MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
3690                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3691
3692 /* reg_qpdsm_prio_entry_color0_dscp
3693  * DSCP field in the outer label of the packet for color 0 and a given port.
3694  * Reserved when e=0.
3695  * Access: RW
3696  */
3697 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
3698                      MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
3699                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3700
3701 /* reg_qpdsm_prio_entry_color1_e
3702  * Enable update of the entry for color 1 and a given port.
3703  * Access: WO
3704  */
3705 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
3706                      MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
3707                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3708
3709 /* reg_qpdsm_prio_entry_color1_dscp
3710  * DSCP field in the outer label of the packet for color 1 and a given port.
3711  * Reserved when e=0.
3712  * Access: RW
3713  */
3714 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
3715                      MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
3716                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3717
3718 /* reg_qpdsm_prio_entry_color2_e
3719  * Enable update of the entry for color 2 and a given port.
3720  * Access: WO
3721  */
3722 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
3723                      MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
3724                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3725
3726 /* reg_qpdsm_prio_entry_color2_dscp
3727  * DSCP field in the outer label of the packet for color 2 and a given port.
3728  * Reserved when e=0.
3729  * Access: RW
3730  */
3731 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
3732                      MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
3733                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3734
3735 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port)
3736 {
3737         MLXSW_REG_ZERO(qpdsm, payload);
3738         mlxsw_reg_qpdsm_local_port_set(payload, local_port);
3739 }
3740
3741 static inline void
3742 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
3743 {
3744         mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
3745         mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
3746         mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
3747         mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
3748         mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
3749         mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
3750 }
3751
3752 /* QPDPM - QoS Port DSCP to Priority Mapping Register
3753  * --------------------------------------------------
3754  * This register controls the mapping from DSCP field to
3755  * Switch Priority for IP packets.
3756  */
3757 #define MLXSW_REG_QPDPM_ID 0x4013
3758 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */
3759 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */
3760 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
3761 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN +                 \
3762                              MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN *       \
3763                              MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
3764
3765 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
3766
3767 /* reg_qpdpm_local_port
3768  * Local Port. Supported for data packets from CPU port.
3769  * Access: Index
3770  */
3771 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8);
3772
3773 /* reg_qpdpm_dscp_e
3774  * Enable update of the specific entry. When cleared, the switch_prio and color
3775  * fields are ignored and the previous switch_prio and color values are
3776  * preserved.
3777  * Access: WO
3778  */
3779 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
3780                      MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3781
3782 /* reg_qpdpm_dscp_prio
3783  * The new Switch Priority value for the relevant DSCP value.
3784  * Access: RW
3785  */
3786 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
3787                      MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
3788                      MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3789
3790 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port)
3791 {
3792         MLXSW_REG_ZERO(qpdpm, payload);
3793         mlxsw_reg_qpdpm_local_port_set(payload, local_port);
3794 }
3795
3796 static inline void
3797 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
3798 {
3799         mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
3800         mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
3801 }
3802
3803 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register
3804  * ------------------------------------------------------------------
3805  * This register configures if the Switch Priority to Traffic Class mapping is
3806  * based on Multicast packet indication. If so, then multicast packets will get
3807  * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by
3808  * QTCT.
3809  * By default, Switch Priority to Traffic Class mapping is not based on
3810  * Multicast packet indication.
3811  */
3812 #define MLXSW_REG_QTCTM_ID 0x401A
3813 #define MLXSW_REG_QTCTM_LEN 0x08
3814
3815 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
3816
3817 /* reg_qtctm_local_port
3818  * Local port number.
3819  * No support for CPU port.
3820  * Access: Index
3821  */
3822 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8);
3823
3824 /* reg_qtctm_mc
3825  * Multicast Mode
3826  * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
3827  * indication (default is 0, not based on Multicast packet indication).
3828  */
3829 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
3830
3831 static inline void
3832 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc)
3833 {
3834         MLXSW_REG_ZERO(qtctm, payload);
3835         mlxsw_reg_qtctm_local_port_set(payload, local_port);
3836         mlxsw_reg_qtctm_mc_set(payload, mc);
3837 }
3838
3839 /* PMLP - Ports Module to Local Port Register
3840  * ------------------------------------------
3841  * Configures the assignment of modules to local ports.
3842  */
3843 #define MLXSW_REG_PMLP_ID 0x5002
3844 #define MLXSW_REG_PMLP_LEN 0x40
3845
3846 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
3847
3848 /* reg_pmlp_rxtx
3849  * 0 - Tx value is used for both Tx and Rx.
3850  * 1 - Rx value is taken from a separte field.
3851  * Access: RW
3852  */
3853 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
3854
3855 /* reg_pmlp_local_port
3856  * Local port number.
3857  * Access: Index
3858  */
3859 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
3860
3861 /* reg_pmlp_width
3862  * 0 - Unmap local port.
3863  * 1 - Lane 0 is used.
3864  * 2 - Lanes 0 and 1 are used.
3865  * 4 - Lanes 0, 1, 2 and 3 are used.
3866  * Access: RW
3867  */
3868 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
3869
3870 /* reg_pmlp_module
3871  * Module number.
3872  * Access: RW
3873  */
3874 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
3875
3876 /* reg_pmlp_tx_lane
3877  * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
3878  * Access: RW
3879  */
3880 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
3881
3882 /* reg_pmlp_rx_lane
3883  * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
3884  * equal to Tx lane.
3885  * Access: RW
3886  */
3887 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
3888
3889 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
3890 {
3891         MLXSW_REG_ZERO(pmlp, payload);
3892         mlxsw_reg_pmlp_local_port_set(payload, local_port);
3893 }
3894
3895 /* PMTU - Port MTU Register
3896  * ------------------------
3897  * Configures and reports the port MTU.
3898  */
3899 #define MLXSW_REG_PMTU_ID 0x5003
3900 #define MLXSW_REG_PMTU_LEN 0x10
3901
3902 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
3903
3904 /* reg_pmtu_local_port
3905  * Local port number.
3906  * Access: Index
3907  */
3908 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
3909
3910 /* reg_pmtu_max_mtu
3911  * Maximum MTU.
3912  * When port type (e.g. Ethernet) is configured, the relevant MTU is
3913  * reported, otherwise the minimum between the max_mtu of the different
3914  * types is reported.
3915  * Access: RO
3916  */
3917 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
3918
3919 /* reg_pmtu_admin_mtu
3920  * MTU value to set port to. Must be smaller or equal to max_mtu.
3921  * Note: If port type is Infiniband, then port must be disabled, when its
3922  * MTU is set.
3923  * Access: RW
3924  */
3925 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
3926
3927 /* reg_pmtu_oper_mtu
3928  * The actual MTU configured on the port. Packets exceeding this size
3929  * will be dropped.
3930  * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
3931  * oper_mtu might be smaller than admin_mtu.
3932  * Access: RO
3933  */
3934 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
3935
3936 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
3937                                        u16 new_mtu)
3938 {
3939         MLXSW_REG_ZERO(pmtu, payload);
3940         mlxsw_reg_pmtu_local_port_set(payload, local_port);
3941         mlxsw_reg_pmtu_max_mtu_set(payload, 0);
3942         mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
3943         mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
3944 }
3945
3946 /* PTYS - Port Type and Speed Register
3947  * -----------------------------------
3948  * Configures and reports the port speed type.
3949  *
3950  * Note: When set while the link is up, the changes will not take effect
3951  * until the port transitions from down to up state.
3952  */
3953 #define MLXSW_REG_PTYS_ID 0x5004
3954 #define MLXSW_REG_PTYS_LEN 0x40
3955
3956 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
3957
3958 /* an_disable_admin
3959  * Auto negotiation disable administrative configuration
3960  * 0 - Device doesn't support AN disable.
3961  * 1 - Device supports AN disable.
3962  * Access: RW
3963  */
3964 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
3965
3966 /* reg_ptys_local_port
3967  * Local port number.
3968  * Access: Index
3969  */
3970 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
3971
3972 #define MLXSW_REG_PTYS_PROTO_MASK_IB    BIT(0)
3973 #define MLXSW_REG_PTYS_PROTO_MASK_ETH   BIT(2)
3974
3975 /* reg_ptys_proto_mask
3976  * Protocol mask. Indicates which protocol is used.
3977  * 0 - Infiniband.
3978  * 1 - Fibre Channel.
3979  * 2 - Ethernet.
3980  * Access: Index
3981  */
3982 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
3983
3984 enum {
3985         MLXSW_REG_PTYS_AN_STATUS_NA,
3986         MLXSW_REG_PTYS_AN_STATUS_OK,
3987         MLXSW_REG_PTYS_AN_STATUS_FAIL,
3988 };
3989
3990 /* reg_ptys_an_status
3991  * Autonegotiation status.
3992  * Access: RO
3993  */
3994 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
3995
3996 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M                         BIT(0)
3997 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII                   BIT(1)
3998 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII                 BIT(2)
3999 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R                           BIT(3)
4000 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G                     BIT(4)
4001 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G                BIT(5)
4002 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR             BIT(6)
4003 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2    BIT(7)
4004 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR      BIT(8)
4005 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4            BIT(9)
4006 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2         BIT(10)
4007 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4         BIT(12)
4008
4009 /* reg_ptys_ext_eth_proto_cap
4010  * Extended Ethernet port supported speeds and protocols.
4011  * Access: RO
4012  */
4013 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
4014
4015 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII                  BIT(0)
4016 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX            BIT(1)
4017 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4            BIT(2)
4018 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4            BIT(3)
4019 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR             BIT(4)
4020 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2            BIT(5)
4021 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4            BIT(6)
4022 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4            BIT(7)
4023 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4             BIT(8)
4024 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR             BIT(12)
4025 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR             BIT(13)
4026 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR          BIT(14)
4027 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4            BIT(15)
4028 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4        BIT(16)
4029 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2            BIT(18)
4030 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4            BIT(19)
4031 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4           BIT(20)
4032 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4           BIT(21)
4033 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4           BIT(22)
4034 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4       BIT(23)
4035 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX             BIT(24)
4036 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T              BIT(25)
4037 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T              BIT(26)
4038 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR             BIT(27)
4039 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR             BIT(28)
4040 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR             BIT(29)
4041 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2            BIT(30)
4042 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2            BIT(31)
4043
4044 /* reg_ptys_eth_proto_cap
4045  * Ethernet port supported speeds and protocols.
4046  * Access: RO
4047  */
4048 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4049
4050 /* reg_ptys_ib_link_width_cap
4051  * IB port supported widths.
4052  * Access: RO
4053  */
4054 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
4055
4056 #define MLXSW_REG_PTYS_IB_SPEED_SDR     BIT(0)
4057 #define MLXSW_REG_PTYS_IB_SPEED_DDR     BIT(1)
4058 #define MLXSW_REG_PTYS_IB_SPEED_QDR     BIT(2)
4059 #define MLXSW_REG_PTYS_IB_SPEED_FDR10   BIT(3)
4060 #define MLXSW_REG_PTYS_IB_SPEED_FDR     BIT(4)
4061 #define MLXSW_REG_PTYS_IB_SPEED_EDR     BIT(5)
4062
4063 /* reg_ptys_ib_proto_cap
4064  * IB port supported speeds and protocols.
4065  * Access: RO
4066  */
4067 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
4068
4069 /* reg_ptys_ext_eth_proto_admin
4070  * Extended speed and protocol to set port to.
4071  * Access: RW
4072  */
4073 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4074
4075 /* reg_ptys_eth_proto_admin
4076  * Speed and protocol to set port to.
4077  * Access: RW
4078  */
4079 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4080
4081 /* reg_ptys_ib_link_width_admin
4082  * IB width to set port to.
4083  * Access: RW
4084  */
4085 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
4086
4087 /* reg_ptys_ib_proto_admin
4088  * IB speeds and protocols to set port to.
4089  * Access: RW
4090  */
4091 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
4092
4093 /* reg_ptys_ext_eth_proto_oper
4094  * The extended current speed and protocol configured for the port.
4095  * Access: RO
4096  */
4097 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4098
4099 /* reg_ptys_eth_proto_oper
4100  * The current speed and protocol configured for the port.
4101  * Access: RO
4102  */
4103 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4104
4105 /* reg_ptys_ib_link_width_oper
4106  * The current IB width to set port to.
4107  * Access: RO
4108  */
4109 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
4110
4111 /* reg_ptys_ib_proto_oper
4112  * The current IB speed and protocol.
4113  * Access: RO
4114  */
4115 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
4116
4117 enum mlxsw_reg_ptys_connector_type {
4118         MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4119         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4120         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4121         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4122         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4123         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4124         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4125         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4126         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4127 };
4128
4129 /* reg_ptys_connector_type
4130  * Connector type indication.
4131  * Access: RO
4132  */
4133 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4134
4135 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
4136                                            u32 proto_admin, bool autoneg)
4137 {
4138         MLXSW_REG_ZERO(ptys, payload);
4139         mlxsw_reg_ptys_local_port_set(payload, local_port);
4140         mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4141         mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4142         mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4143 }
4144
4145 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port,
4146                                                u32 proto_admin, bool autoneg)
4147 {
4148         MLXSW_REG_ZERO(ptys, payload);
4149         mlxsw_reg_ptys_local_port_set(payload, local_port);
4150         mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4151         mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4152         mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4153 }
4154
4155 static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
4156                                              u32 *p_eth_proto_cap,
4157                                              u32 *p_eth_proto_admin,
4158                                              u32 *p_eth_proto_oper)
4159 {
4160         if (p_eth_proto_cap)
4161                 *p_eth_proto_cap =
4162                         mlxsw_reg_ptys_eth_proto_cap_get(payload);
4163         if (p_eth_proto_admin)
4164                 *p_eth_proto_admin =
4165                         mlxsw_reg_ptys_eth_proto_admin_get(payload);
4166         if (p_eth_proto_oper)
4167                 *p_eth_proto_oper =
4168                         mlxsw_reg_ptys_eth_proto_oper_get(payload);
4169 }
4170
4171 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4172                                                  u32 *p_eth_proto_cap,
4173                                                  u32 *p_eth_proto_admin,
4174                                                  u32 *p_eth_proto_oper)
4175 {
4176         if (p_eth_proto_cap)
4177                 *p_eth_proto_cap =
4178                         mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4179         if (p_eth_proto_admin)
4180                 *p_eth_proto_admin =
4181                         mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4182         if (p_eth_proto_oper)
4183                 *p_eth_proto_oper =
4184                         mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4185 }
4186
4187 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
4188                                           u16 proto_admin, u16 link_width)
4189 {
4190         MLXSW_REG_ZERO(ptys, payload);
4191         mlxsw_reg_ptys_local_port_set(payload, local_port);
4192         mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
4193         mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
4194         mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
4195 }
4196
4197 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
4198                                             u16 *p_ib_link_width_cap,
4199                                             u16 *p_ib_proto_oper,
4200                                             u16 *p_ib_link_width_oper)
4201 {
4202         if (p_ib_proto_cap)
4203                 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
4204         if (p_ib_link_width_cap)
4205                 *p_ib_link_width_cap =
4206                         mlxsw_reg_ptys_ib_link_width_cap_get(payload);
4207         if (p_ib_proto_oper)
4208                 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
4209         if (p_ib_link_width_oper)
4210                 *p_ib_link_width_oper =
4211                         mlxsw_reg_ptys_ib_link_width_oper_get(payload);
4212 }
4213
4214 /* PPAD - Port Physical Address Register
4215  * -------------------------------------
4216  * The PPAD register configures the per port physical MAC address.
4217  */
4218 #define MLXSW_REG_PPAD_ID 0x5005
4219 #define MLXSW_REG_PPAD_LEN 0x10
4220
4221 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
4222
4223 /* reg_ppad_single_base_mac
4224  * 0: base_mac, local port should be 0 and mac[7:0] is
4225  * reserved. HW will set incremental
4226  * 1: single_mac - mac of the local_port
4227  * Access: RW
4228  */
4229 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4230
4231 /* reg_ppad_local_port
4232  * port number, if single_base_mac = 0 then local_port is reserved
4233  * Access: RW
4234  */
4235 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
4236
4237 /* reg_ppad_mac
4238  * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
4239  * If single_base_mac = 1 - the per port MAC address
4240  * Access: RW
4241  */
4242 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4243
4244 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4245                                        u8 local_port)
4246 {
4247         MLXSW_REG_ZERO(ppad, payload);
4248         mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4249         mlxsw_reg_ppad_local_port_set(payload, local_port);
4250 }
4251
4252 /* PAOS - Ports Administrative and Operational Status Register
4253  * -----------------------------------------------------------
4254  * Configures and retrieves per port administrative and operational status.
4255  */
4256 #define MLXSW_REG_PAOS_ID 0x5006
4257 #define MLXSW_REG_PAOS_LEN 0x10
4258
4259 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
4260
4261 /* reg_paos_swid
4262  * Switch partition ID with which to associate the port.
4263  * Note: while external ports uses unique local port numbers (and thus swid is
4264  * redundant), router ports use the same local port number where swid is the
4265  * only indication for the relevant port.
4266  * Access: Index
4267  */
4268 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4269
4270 /* reg_paos_local_port
4271  * Local port number.
4272  * Access: Index
4273  */
4274 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
4275
4276 /* reg_paos_admin_status
4277  * Port administrative state (the desired state of the port):
4278  * 1 - Up.
4279  * 2 - Down.
4280  * 3 - Up once. This means that in case of link failure, the port won't go
4281  *     into polling mode, but will wait to be re-enabled by software.
4282  * 4 - Disabled by system. Can only be set by hardware.
4283  * Access: RW
4284  */
4285 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4286
4287 /* reg_paos_oper_status
4288  * Port operational state (the current state):
4289  * 1 - Up.
4290  * 2 - Down.
4291  * 3 - Down by port failure. This means that the device will not let the
4292  *     port up again until explicitly specified by software.
4293  * Access: RO
4294  */
4295 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4296
4297 /* reg_paos_ase
4298  * Admin state update enabled.
4299  * Access: WO
4300  */
4301 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4302
4303 /* reg_paos_ee
4304  * Event update enable. If this bit is set, event generation will be
4305  * updated based on the e field.
4306  * Access: WO
4307  */
4308 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4309
4310 /* reg_paos_e
4311  * Event generation on operational state change:
4312  * 0 - Do not generate event.
4313  * 1 - Generate Event.
4314  * 2 - Generate Single Event.
4315  * Access: RW
4316  */
4317 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4318
4319 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
4320                                        enum mlxsw_port_admin_status status)
4321 {
4322         MLXSW_REG_ZERO(paos, payload);
4323         mlxsw_reg_paos_swid_set(payload, 0);
4324         mlxsw_reg_paos_local_port_set(payload, local_port);
4325         mlxsw_reg_paos_admin_status_set(payload, status);
4326         mlxsw_reg_paos_oper_status_set(payload, 0);
4327         mlxsw_reg_paos_ase_set(payload, 1);
4328         mlxsw_reg_paos_ee_set(payload, 1);
4329         mlxsw_reg_paos_e_set(payload, 1);
4330 }
4331
4332 /* PFCC - Ports Flow Control Configuration Register
4333  * ------------------------------------------------
4334  * Configures and retrieves the per port flow control configuration.
4335  */
4336 #define MLXSW_REG_PFCC_ID 0x5007
4337 #define MLXSW_REG_PFCC_LEN 0x20
4338
4339 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4340
4341 /* reg_pfcc_local_port
4342  * Local port number.
4343  * Access: Index
4344  */
4345 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
4346
4347 /* reg_pfcc_pnat
4348  * Port number access type. Determines the way local_port is interpreted:
4349  * 0 - Local port number.
4350  * 1 - IB / label port number.
4351  * Access: Index
4352  */
4353 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4354
4355 /* reg_pfcc_shl_cap
4356  * Send to higher layers capabilities:
4357  * 0 - No capability of sending Pause and PFC frames to higher layers.
4358  * 1 - Device has capability of sending Pause and PFC frames to higher
4359  *     layers.
4360  * Access: RO
4361  */
4362 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4363
4364 /* reg_pfcc_shl_opr
4365  * Send to higher layers operation:
4366  * 0 - Pause and PFC frames are handled by the port (default).
4367  * 1 - Pause and PFC frames are handled by the port and also sent to
4368  *     higher layers. Only valid if shl_cap = 1.
4369  * Access: RW
4370  */
4371 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4372
4373 /* reg_pfcc_ppan
4374  * Pause policy auto negotiation.
4375  * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
4376  * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
4377  *     based on the auto-negotiation resolution.
4378  * Access: RW
4379  *
4380  * Note: The auto-negotiation advertisement is set according to pptx and
4381  * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
4382  */
4383 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4384
4385 /* reg_pfcc_prio_mask_tx
4386  * Bit per priority indicating if Tx flow control policy should be
4387  * updated based on bit pfctx.
4388  * Access: WO
4389  */
4390 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4391
4392 /* reg_pfcc_prio_mask_rx
4393  * Bit per priority indicating if Rx flow control policy should be
4394  * updated based on bit pfcrx.
4395  * Access: WO
4396  */
4397 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4398
4399 /* reg_pfcc_pptx
4400  * Admin Pause policy on Tx.
4401  * 0 - Never generate Pause frames (default).
4402  * 1 - Generate Pause frames according to Rx buffer threshold.
4403  * Access: RW
4404  */
4405 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4406
4407 /* reg_pfcc_aptx
4408  * Active (operational) Pause policy on Tx.
4409  * 0 - Never generate Pause frames.
4410  * 1 - Generate Pause frames according to Rx buffer threshold.
4411  * Access: RO
4412  */
4413 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4414
4415 /* reg_pfcc_pfctx
4416  * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
4417  * 0 - Never generate priority Pause frames on the specified priority
4418  *     (default).
4419  * 1 - Generate priority Pause frames according to Rx buffer threshold on
4420  *     the specified priority.
4421  * Access: RW
4422  *
4423  * Note: pfctx and pptx must be mutually exclusive.
4424  */
4425 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4426
4427 /* reg_pfcc_pprx
4428  * Admin Pause policy on Rx.
4429  * 0 - Ignore received Pause frames (default).
4430  * 1 - Respect received Pause frames.
4431  * Access: RW
4432  */
4433 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4434
4435 /* reg_pfcc_aprx
4436  * Active (operational) Pause policy on Rx.
4437  * 0 - Ignore received Pause frames.
4438  * 1 - Respect received Pause frames.
4439  * Access: RO
4440  */
4441 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4442
4443 /* reg_pfcc_pfcrx
4444  * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
4445  * 0 - Ignore incoming priority Pause frames on the specified priority
4446  *     (default).
4447  * 1 - Respect incoming priority Pause frames on the specified priority.
4448  * Access: RW
4449  */
4450 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4451
4452 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4453
4454 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4455 {
4456         mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4457         mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4458         mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4459         mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4460 }
4461
4462 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
4463 {
4464         MLXSW_REG_ZERO(pfcc, payload);
4465         mlxsw_reg_pfcc_local_port_set(payload, local_port);
4466 }
4467
4468 /* PPCNT - Ports Performance Counters Register
4469  * -------------------------------------------
4470  * The PPCNT register retrieves per port performance counters.
4471  */
4472 #define MLXSW_REG_PPCNT_ID 0x5008
4473 #define MLXSW_REG_PPCNT_LEN 0x100
4474 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4475
4476 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4477
4478 /* reg_ppcnt_swid
4479  * For HCA: must be always 0.
4480  * Switch partition ID to associate port with.
4481  * Switch partitions are numbered from 0 to 7 inclusively.
4482  * Switch partition 254 indicates stacking ports.
4483  * Switch partition 255 indicates all switch partitions.
4484  * Only valid on Set() operation with local_port=255.
4485  * Access: Index
4486  */
4487 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4488
4489 /* reg_ppcnt_local_port
4490  * Local port number.
4491  * 255 indicates all ports on the device, and is only allowed
4492  * for Set() operation.
4493  * Access: Index
4494  */
4495 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
4496
4497 /* reg_ppcnt_pnat
4498  * Port number access type:
4499  * 0 - Local port number
4500  * 1 - IB port number
4501  * Access: Index
4502  */
4503 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4504
4505 enum mlxsw_reg_ppcnt_grp {
4506         MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4507         MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
4508         MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4509         MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
4510         MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4511         MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
4512         MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4513         MLXSW_REG_PPCNT_TC_CNT = 0x11,
4514         MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
4515 };
4516
4517 /* reg_ppcnt_grp
4518  * Performance counter group.
4519  * Group 63 indicates all groups. Only valid on Set() operation with
4520  * clr bit set.
4521  * 0x0: IEEE 802.3 Counters
4522  * 0x1: RFC 2863 Counters
4523  * 0x2: RFC 2819 Counters
4524  * 0x3: RFC 3635 Counters
4525  * 0x5: Ethernet Extended Counters
4526  * 0x6: Ethernet Discard Counters
4527  * 0x8: Link Level Retransmission Counters
4528  * 0x10: Per Priority Counters
4529  * 0x11: Per Traffic Class Counters
4530  * 0x12: Physical Layer Counters
4531  * 0x13: Per Traffic Class Congestion Counters
4532  * Access: Index
4533  */
4534 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4535
4536 /* reg_ppcnt_clr
4537  * Clear counters. Setting the clr bit will reset the counter value
4538  * for all counters in the counter group. This bit can be set
4539  * for both Set() and Get() operation.
4540  * Access: OP
4541  */
4542 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4543
4544 /* reg_ppcnt_prio_tc
4545  * Priority for counter set that support per priority, valid values: 0-7.
4546  * Traffic class for counter set that support per traffic class,
4547  * valid values: 0- cap_max_tclass-1 .
4548  * For HCA: cap_max_tclass is always 8.
4549  * Otherwise must be 0.
4550  * Access: Index
4551  */
4552 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
4553
4554 /* Ethernet IEEE 802.3 Counter Group */
4555
4556 /* reg_ppcnt_a_frames_transmitted_ok
4557  * Access: RO
4558  */
4559 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
4560              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4561
4562 /* reg_ppcnt_a_frames_received_ok
4563  * Access: RO
4564  */
4565 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
4566              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4567
4568 /* reg_ppcnt_a_frame_check_sequence_errors
4569  * Access: RO
4570  */
4571 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
4572              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4573
4574 /* reg_ppcnt_a_alignment_errors
4575  * Access: RO
4576  */
4577 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
4578              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4579
4580 /* reg_ppcnt_a_octets_transmitted_ok
4581  * Access: RO
4582  */
4583 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
4584              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4585
4586 /* reg_ppcnt_a_octets_received_ok
4587  * Access: RO
4588  */
4589 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
4590              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4591
4592 /* reg_ppcnt_a_multicast_frames_xmitted_ok
4593  * Access: RO
4594  */
4595 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
4596              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4597
4598 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
4599  * Access: RO
4600  */
4601 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
4602              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4603
4604 /* reg_ppcnt_a_multicast_frames_received_ok
4605  * Access: RO
4606  */
4607 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
4608              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4609
4610 /* reg_ppcnt_a_broadcast_frames_received_ok
4611  * Access: RO
4612  */
4613 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
4614              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4615
4616 /* reg_ppcnt_a_in_range_length_errors
4617  * Access: RO
4618  */
4619 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
4620              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4621
4622 /* reg_ppcnt_a_out_of_range_length_field
4623  * Access: RO
4624  */
4625 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
4626              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4627
4628 /* reg_ppcnt_a_frame_too_long_errors
4629  * Access: RO
4630  */
4631 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
4632              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4633
4634 /* reg_ppcnt_a_symbol_error_during_carrier
4635  * Access: RO
4636  */
4637 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
4638              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4639
4640 /* reg_ppcnt_a_mac_control_frames_transmitted
4641  * Access: RO
4642  */
4643 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
4644              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4645
4646 /* reg_ppcnt_a_mac_control_frames_received
4647  * Access: RO
4648  */
4649 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
4650              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4651
4652 /* reg_ppcnt_a_unsupported_opcodes_received
4653  * Access: RO
4654  */
4655 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
4656              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4657
4658 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
4659  * Access: RO
4660  */
4661 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
4662              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4663
4664 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
4665  * Access: RO
4666  */
4667 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
4668              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4669
4670 /* Ethernet RFC 2863 Counter Group */
4671
4672 /* reg_ppcnt_if_in_discards
4673  * Access: RO
4674  */
4675 MLXSW_ITEM64(reg, ppcnt, if_in_discards,
4676              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4677
4678 /* reg_ppcnt_if_out_discards
4679  * Access: RO
4680  */
4681 MLXSW_ITEM64(reg, ppcnt, if_out_discards,
4682              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4683
4684 /* reg_ppcnt_if_out_errors
4685  * Access: RO
4686  */
4687 MLXSW_ITEM64(reg, ppcnt, if_out_errors,
4688              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4689
4690 /* Ethernet RFC 2819 Counter Group */
4691
4692 /* reg_ppcnt_ether_stats_undersize_pkts
4693  * Access: RO
4694  */
4695 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
4696              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4697
4698 /* reg_ppcnt_ether_stats_oversize_pkts
4699  * Access: RO
4700  */
4701 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
4702              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4703
4704 /* reg_ppcnt_ether_stats_fragments
4705  * Access: RO
4706  */
4707 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
4708              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4709
4710 /* reg_ppcnt_ether_stats_pkts64octets
4711  * Access: RO
4712  */
4713 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
4714              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4715
4716 /* reg_ppcnt_ether_stats_pkts65to127octets
4717  * Access: RO
4718  */
4719 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
4720              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4721
4722 /* reg_ppcnt_ether_stats_pkts128to255octets
4723  * Access: RO
4724  */
4725 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
4726              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4727
4728 /* reg_ppcnt_ether_stats_pkts256to511octets
4729  * Access: RO
4730  */
4731 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
4732              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4733
4734 /* reg_ppcnt_ether_stats_pkts512to1023octets
4735  * Access: RO
4736  */
4737 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
4738              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4739
4740 /* reg_ppcnt_ether_stats_pkts1024to1518octets
4741  * Access: RO
4742  */
4743 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
4744              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4745
4746 /* reg_ppcnt_ether_stats_pkts1519to2047octets
4747  * Access: RO
4748  */
4749 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
4750              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4751
4752 /* reg_ppcnt_ether_stats_pkts2048to4095octets
4753  * Access: RO
4754  */
4755 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
4756              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4757
4758 /* reg_ppcnt_ether_stats_pkts4096to8191octets
4759  * Access: RO
4760  */
4761 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
4762              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
4763
4764 /* reg_ppcnt_ether_stats_pkts8192to10239octets
4765  * Access: RO
4766  */
4767 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
4768              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
4769
4770 /* Ethernet RFC 3635 Counter Group */
4771
4772 /* reg_ppcnt_dot3stats_fcs_errors
4773  * Access: RO
4774  */
4775 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
4776              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4777
4778 /* reg_ppcnt_dot3stats_symbol_errors
4779  * Access: RO
4780  */
4781 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
4782              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4783
4784 /* reg_ppcnt_dot3control_in_unknown_opcodes
4785  * Access: RO
4786  */
4787 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
4788              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4789
4790 /* reg_ppcnt_dot3in_pause_frames
4791  * Access: RO
4792  */
4793 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
4794              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4795
4796 /* Ethernet Extended Counter Group Counters */
4797
4798 /* reg_ppcnt_ecn_marked
4799  * Access: RO
4800  */
4801 MLXSW_ITEM64(reg, ppcnt, ecn_marked,
4802              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4803
4804 /* Ethernet Discard Counter Group Counters */
4805
4806 /* reg_ppcnt_ingress_general
4807  * Access: RO
4808  */
4809 MLXSW_ITEM64(reg, ppcnt, ingress_general,
4810              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4811
4812 /* reg_ppcnt_ingress_policy_engine
4813  * Access: RO
4814  */
4815 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
4816              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4817
4818 /* reg_ppcnt_ingress_vlan_membership
4819  * Access: RO
4820  */
4821 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
4822              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4823
4824 /* reg_ppcnt_ingress_tag_frame_type
4825  * Access: RO
4826  */
4827 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
4828              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4829
4830 /* reg_ppcnt_egress_vlan_membership
4831  * Access: RO
4832  */
4833 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
4834              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4835
4836 /* reg_ppcnt_loopback_filter
4837  * Access: RO
4838  */
4839 MLXSW_ITEM64(reg, ppcnt, loopback_filter,
4840              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4841
4842 /* reg_ppcnt_egress_general
4843  * Access: RO
4844  */
4845 MLXSW_ITEM64(reg, ppcnt, egress_general,
4846              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4847
4848 /* reg_ppcnt_egress_hoq
4849  * Access: RO
4850  */
4851 MLXSW_ITEM64(reg, ppcnt, egress_hoq,
4852              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4853
4854 /* reg_ppcnt_egress_policy_engine
4855  * Access: RO
4856  */
4857 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
4858              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4859
4860 /* reg_ppcnt_ingress_tx_link_down
4861  * Access: RO
4862  */
4863 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
4864              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4865
4866 /* reg_ppcnt_egress_stp_filter
4867  * Access: RO
4868  */
4869 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
4870              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4871
4872 /* reg_ppcnt_egress_sll
4873  * Access: RO
4874  */
4875 MLXSW_ITEM64(reg, ppcnt, egress_sll,
4876              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4877
4878 /* Ethernet Per Priority Group Counters */
4879
4880 /* reg_ppcnt_rx_octets
4881  * Access: RO
4882  */
4883 MLXSW_ITEM64(reg, ppcnt, rx_octets,
4884              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4885
4886 /* reg_ppcnt_rx_frames
4887  * Access: RO
4888  */
4889 MLXSW_ITEM64(reg, ppcnt, rx_frames,
4890              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4891
4892 /* reg_ppcnt_tx_octets
4893  * Access: RO
4894  */
4895 MLXSW_ITEM64(reg, ppcnt, tx_octets,
4896              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4897
4898 /* reg_ppcnt_tx_frames
4899  * Access: RO
4900  */
4901 MLXSW_ITEM64(reg, ppcnt, tx_frames,
4902              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4903
4904 /* reg_ppcnt_rx_pause
4905  * Access: RO
4906  */
4907 MLXSW_ITEM64(reg, ppcnt, rx_pause,
4908              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4909
4910 /* reg_ppcnt_rx_pause_duration
4911  * Access: RO
4912  */
4913 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
4914              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4915
4916 /* reg_ppcnt_tx_pause
4917  * Access: RO
4918  */
4919 MLXSW_ITEM64(reg, ppcnt, tx_pause,
4920              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4921
4922 /* reg_ppcnt_tx_pause_duration
4923  * Access: RO
4924  */
4925 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
4926              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4927
4928 /* reg_ppcnt_rx_pause_transition
4929  * Access: RO
4930  */
4931 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
4932              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4933
4934 /* Ethernet Per Traffic Group Counters */
4935
4936 /* reg_ppcnt_tc_transmit_queue
4937  * Contains the transmit queue depth in cells of traffic class
4938  * selected by prio_tc and the port selected by local_port.
4939  * The field cannot be cleared.
4940  * Access: RO
4941  */
4942 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
4943              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4944
4945 /* reg_ppcnt_tc_no_buffer_discard_uc
4946  * The number of unicast packets dropped due to lack of shared
4947  * buffer resources.
4948  * Access: RO
4949  */
4950 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
4951              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4952
4953 /* Ethernet Per Traffic Class Congestion Group Counters */
4954
4955 /* reg_ppcnt_wred_discard
4956  * Access: RO
4957  */
4958 MLXSW_ITEM64(reg, ppcnt, wred_discard,
4959              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4960
4961 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
4962                                         enum mlxsw_reg_ppcnt_grp grp,
4963                                         u8 prio_tc)
4964 {
4965         MLXSW_REG_ZERO(ppcnt, payload);
4966         mlxsw_reg_ppcnt_swid_set(payload, 0);
4967         mlxsw_reg_ppcnt_local_port_set(payload, local_port);
4968         mlxsw_reg_ppcnt_pnat_set(payload, 0);
4969         mlxsw_reg_ppcnt_grp_set(payload, grp);
4970         mlxsw_reg_ppcnt_clr_set(payload, 0);
4971         mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
4972 }
4973
4974 /* PLIB - Port Local to InfiniBand Port
4975  * ------------------------------------
4976  * The PLIB register performs mapping from Local Port into InfiniBand Port.
4977  */
4978 #define MLXSW_REG_PLIB_ID 0x500A
4979 #define MLXSW_REG_PLIB_LEN 0x10
4980
4981 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
4982
4983 /* reg_plib_local_port
4984  * Local port number.
4985  * Access: Index
4986  */
4987 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8);
4988
4989 /* reg_plib_ib_port
4990  * InfiniBand port remapping for local_port.
4991  * Access: RW
4992  */
4993 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
4994
4995 /* PPTB - Port Prio To Buffer Register
4996  * -----------------------------------
4997  * Configures the switch priority to buffer table.
4998  */
4999 #define MLXSW_REG_PPTB_ID 0x500B
5000 #define MLXSW_REG_PPTB_LEN 0x10
5001
5002 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
5003
5004 enum {
5005         MLXSW_REG_PPTB_MM_UM,
5006         MLXSW_REG_PPTB_MM_UNICAST,
5007         MLXSW_REG_PPTB_MM_MULTICAST,
5008 };
5009
5010 /* reg_pptb_mm
5011  * Mapping mode.
5012  * 0 - Map both unicast and multicast packets to the same buffer.
5013  * 1 - Map only unicast packets.
5014  * 2 - Map only multicast packets.
5015  * Access: Index
5016  *
5017  * Note: SwitchX-2 only supports the first option.
5018  */
5019 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
5020
5021 /* reg_pptb_local_port
5022  * Local port number.
5023  * Access: Index
5024  */
5025 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
5026
5027 /* reg_pptb_um
5028  * Enables the update of the untagged_buf field.
5029  * Access: RW
5030  */
5031 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
5032
5033 /* reg_pptb_pm
5034  * Enables the update of the prio_to_buff field.
5035  * Bit <i> is a flag for updating the mapping for switch priority <i>.
5036  * Access: RW
5037  */
5038 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
5039
5040 /* reg_pptb_prio_to_buff
5041  * Mapping of switch priority <i> to one of the allocated receive port
5042  * buffers.
5043  * Access: RW
5044  */
5045 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
5046
5047 /* reg_pptb_pm_msb
5048  * Enables the update of the prio_to_buff field.
5049  * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
5050  * Access: RW
5051  */
5052 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
5053
5054 /* reg_pptb_untagged_buff
5055  * Mapping of untagged frames to one of the allocated receive port buffers.
5056  * Access: RW
5057  *
5058  * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
5059  * Spectrum, as it maps untagged packets based on the default switch priority.
5060  */
5061 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
5062
5063 /* reg_pptb_prio_to_buff_msb
5064  * Mapping of switch priority <i+8> to one of the allocated receive port
5065  * buffers.
5066  * Access: RW
5067  */
5068 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5069
5070 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5071
5072 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
5073 {
5074         MLXSW_REG_ZERO(pptb, payload);
5075         mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5076         mlxsw_reg_pptb_local_port_set(payload, local_port);
5077         mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5078         mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5079 }
5080
5081 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
5082                                                     u8 buff)
5083 {
5084         mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
5085         mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
5086 }
5087
5088 /* PBMC - Port Buffer Management Control Register
5089  * ----------------------------------------------
5090  * The PBMC register configures and retrieves the port packet buffer
5091  * allocation for different Prios, and the Pause threshold management.
5092  */
5093 #define MLXSW_REG_PBMC_ID 0x500C
5094 #define MLXSW_REG_PBMC_LEN 0x6C
5095
5096 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
5097
5098 /* reg_pbmc_local_port
5099  * Local port number.
5100  * Access: Index
5101  */
5102 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
5103
5104 /* reg_pbmc_xoff_timer_value
5105  * When device generates a pause frame, it uses this value as the pause
5106  * timer (time for the peer port to pause in quota-512 bit time).
5107  * Access: RW
5108  */
5109 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
5110
5111 /* reg_pbmc_xoff_refresh
5112  * The time before a new pause frame should be sent to refresh the pause RW
5113  * state. Using the same units as xoff_timer_value above (in quota-512 bit
5114  * time).
5115  * Access: RW
5116  */
5117 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
5118
5119 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
5120
5121 /* reg_pbmc_buf_lossy
5122  * The field indicates if the buffer is lossy.
5123  * 0 - Lossless
5124  * 1 - Lossy
5125  * Access: RW
5126  */
5127 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
5128
5129 /* reg_pbmc_buf_epsb
5130  * Eligible for Port Shared buffer.
5131  * If epsb is set, packets assigned to buffer are allowed to insert the port
5132  * shared buffer.
5133  * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
5134  * Access: RW
5135  */
5136 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
5137
5138 /* reg_pbmc_buf_size
5139  * The part of the packet buffer array is allocated for the specific buffer.
5140  * Units are represented in cells.
5141  * Access: RW
5142  */
5143 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
5144
5145 /* reg_pbmc_buf_xoff_threshold
5146  * Once the amount of data in the buffer goes above this value, device
5147  * starts sending PFC frames for all priorities associated with the
5148  * buffer. Units are represented in cells. Reserved in case of lossy
5149  * buffer.
5150  * Access: RW
5151  *
5152  * Note: In Spectrum, reserved for buffer[9].
5153  */
5154 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
5155                      0x08, 0x04, false);
5156
5157 /* reg_pbmc_buf_xon_threshold
5158  * When the amount of data in the buffer goes below this value, device
5159  * stops sending PFC frames for the priorities associated with the
5160  * buffer. Units are represented in cells. Reserved in case of lossy
5161  * buffer.
5162  * Access: RW
5163  *
5164  * Note: In Spectrum, reserved for buffer[9].
5165  */
5166 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5167                      0x08, 0x04, false);
5168
5169 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
5170                                        u16 xoff_timer_value, u16 xoff_refresh)
5171 {
5172         MLXSW_REG_ZERO(pbmc, payload);
5173         mlxsw_reg_pbmc_local_port_set(payload, local_port);
5174         mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5175         mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5176 }
5177
5178 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
5179                                                     int buf_index,
5180                                                     u16 size)
5181 {
5182         mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
5183         mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5184         mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5185 }
5186
5187 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
5188                                                        int buf_index, u16 size,
5189                                                        u16 threshold)
5190 {
5191         mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
5192         mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5193         mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5194         mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
5195         mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
5196 }
5197
5198 /* PSPA - Port Switch Partition Allocation
5199  * ---------------------------------------
5200  * Controls the association of a port with a switch partition and enables
5201  * configuring ports as stacking ports.
5202  */
5203 #define MLXSW_REG_PSPA_ID 0x500D
5204 #define MLXSW_REG_PSPA_LEN 0x8
5205
5206 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
5207
5208 /* reg_pspa_swid
5209  * Switch partition ID.
5210  * Access: RW
5211  */
5212 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
5213
5214 /* reg_pspa_local_port
5215  * Local port number.
5216  * Access: Index
5217  */
5218 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
5219
5220 /* reg_pspa_sub_port
5221  * Virtual port within the local port. Set to 0 when virtual ports are
5222  * disabled on the local port.
5223  * Access: Index
5224  */
5225 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5226
5227 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
5228 {
5229         MLXSW_REG_ZERO(pspa, payload);
5230         mlxsw_reg_pspa_swid_set(payload, swid);
5231         mlxsw_reg_pspa_local_port_set(payload, local_port);
5232         mlxsw_reg_pspa_sub_port_set(payload, 0);
5233 }
5234
5235 /* PPLR - Port Physical Loopback Register
5236  * --------------------------------------
5237  * This register allows configuration of the port's loopback mode.
5238  */
5239 #define MLXSW_REG_PPLR_ID 0x5018
5240 #define MLXSW_REG_PPLR_LEN 0x8
5241
5242 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);
5243
5244 /* reg_pplr_local_port
5245  * Local port number.
5246  * Access: Index
5247  */
5248 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8);
5249
5250 /* Phy local loopback. When set the port's egress traffic is looped back
5251  * to the receiver and the port transmitter is disabled.
5252  */
5253 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
5254
5255 /* reg_pplr_lb_en
5256  * Loopback enable.
5257  * Access: RW
5258  */
5259 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5260
5261 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port,
5262                                        bool phy_local)
5263 {
5264         MLXSW_REG_ZERO(pplr, payload);
5265         mlxsw_reg_pplr_local_port_set(payload, local_port);
5266         mlxsw_reg_pplr_lb_en_set(payload,
5267                                  phy_local ?
5268                                  MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
5269 }
5270
5271 /* HTGT - Host Trap Group Table
5272  * ----------------------------
5273  * Configures the properties for forwarding to CPU.
5274  */
5275 #define MLXSW_REG_HTGT_ID 0x7002
5276 #define MLXSW_REG_HTGT_LEN 0x20
5277
5278 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
5279
5280 /* reg_htgt_swid
5281  * Switch partition ID.
5282  * Access: Index
5283  */
5284 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
5285
5286 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0      /* For locally attached CPU */
5287
5288 /* reg_htgt_type
5289  * CPU path type.
5290  * Access: RW
5291  */
5292 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
5293
5294 enum mlxsw_reg_htgt_trap_group {
5295         MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
5296         MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
5297         MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
5298         MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
5299         MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
5300         MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
5301         MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP,
5302         MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
5303         MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
5304         MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
5305         MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
5306         MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP,
5307         MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS,
5308         MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
5309         MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE,
5310         MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
5311         MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
5312         MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF,
5313         MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
5314         MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,
5315         MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,
5316         MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
5317         MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,
5318         MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,
5319 };
5320
5321 /* reg_htgt_trap_group
5322  * Trap group number. User defined number specifying which trap groups
5323  * should be forwarded to the CPU. The mapping between trap IDs and trap
5324  * groups is configured using HPKT register.
5325  * Access: Index
5326  */
5327 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
5328
5329 enum {
5330         MLXSW_REG_HTGT_POLICER_DISABLE,
5331         MLXSW_REG_HTGT_POLICER_ENABLE,
5332 };
5333
5334 /* reg_htgt_pide
5335  * Enable policer ID specified using 'pid' field.
5336  * Access: RW
5337  */
5338 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
5339
5340 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff
5341
5342 /* reg_htgt_pid
5343  * Policer ID for the trap group.
5344  * Access: RW
5345  */
5346 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
5347
5348 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
5349
5350 /* reg_htgt_mirror_action
5351  * Mirror action to use.
5352  * 0 - Trap to CPU.
5353  * 1 - Trap to CPU and mirror to a mirroring agent.
5354  * 2 - Mirror to a mirroring agent and do not trap to CPU.
5355  * Access: RW
5356  *
5357  * Note: Mirroring to a mirroring agent is only supported in Spectrum.
5358  */
5359 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
5360
5361 /* reg_htgt_mirroring_agent
5362  * Mirroring agent.
5363  * Access: RW
5364  */
5365 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
5366
5367 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
5368
5369 /* reg_htgt_priority
5370  * Trap group priority.
5371  * In case a packet matches multiple classification rules, the packet will
5372  * only be trapped once, based on the trap ID associated with the group (via
5373  * register HPKT) with the highest priority.
5374  * Supported values are 0-7, with 7 represnting the highest priority.
5375  * Access: RW
5376  *
5377  * Note: In SwitchX-2 this field is ignored and the priority value is replaced
5378  * by the 'trap_group' field.
5379  */
5380 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
5381
5382 #define MLXSW_REG_HTGT_DEFAULT_TC 7
5383
5384 /* reg_htgt_local_path_cpu_tclass
5385  * CPU ingress traffic class for the trap group.
5386  * Access: RW
5387  */
5388 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
5389
5390 enum mlxsw_reg_htgt_local_path_rdq {
5391         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
5392         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
5393         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
5394         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
5395 };
5396 /* reg_htgt_local_path_rdq
5397  * Receive descriptor queue (RDQ) to use for the trap group.
5398  * Access: RW
5399  */
5400 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
5401
5402 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
5403                                        u8 priority, u8 tc)
5404 {
5405         MLXSW_REG_ZERO(htgt, payload);
5406
5407         if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
5408                 mlxsw_reg_htgt_pide_set(payload,
5409                                         MLXSW_REG_HTGT_POLICER_DISABLE);
5410         } else {
5411                 mlxsw_reg_htgt_pide_set(payload,
5412                                         MLXSW_REG_HTGT_POLICER_ENABLE);
5413                 mlxsw_reg_htgt_pid_set(payload, policer_id);
5414         }
5415
5416         mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
5417         mlxsw_reg_htgt_trap_group_set(payload, group);
5418         mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
5419         mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
5420         mlxsw_reg_htgt_priority_set(payload, priority);
5421         mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
5422         mlxsw_reg_htgt_local_path_rdq_set(payload, group);
5423 }
5424
5425 /* HPKT - Host Packet Trap
5426  * -----------------------
5427  * Configures trap IDs inside trap groups.
5428  */
5429 #define MLXSW_REG_HPKT_ID 0x7003
5430 #define MLXSW_REG_HPKT_LEN 0x10
5431
5432 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
5433
5434 enum {
5435         MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
5436         MLXSW_REG_HPKT_ACK_REQUIRED,
5437 };
5438
5439 /* reg_hpkt_ack
5440  * Require acknowledgements from the host for events.
5441  * If set, then the device will wait for the event it sent to be acknowledged
5442  * by the host. This option is only relevant for event trap IDs.
5443  * Access: RW
5444  *
5445  * Note: Currently not supported by firmware.
5446  */
5447 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
5448
5449 enum mlxsw_reg_hpkt_action {
5450         MLXSW_REG_HPKT_ACTION_FORWARD,
5451         MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
5452         MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
5453         MLXSW_REG_HPKT_ACTION_DISCARD,
5454         MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
5455         MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
5456 };
5457
5458 /* reg_hpkt_action
5459  * Action to perform on packet when trapped.
5460  * 0 - No action. Forward to CPU based on switching rules.
5461  * 1 - Trap to CPU (CPU receives sole copy).
5462  * 2 - Mirror to CPU (CPU receives a replica of the packet).
5463  * 3 - Discard.
5464  * 4 - Soft discard (allow other traps to act on the packet).
5465  * 5 - Trap and soft discard (allow other traps to overwrite this trap).
5466  * Access: RW
5467  *
5468  * Note: Must be set to 0 (forward) for event trap IDs, as they are already
5469  * addressed to the CPU.
5470  */
5471 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
5472
5473 /* reg_hpkt_trap_group
5474  * Trap group to associate the trap with.
5475  * Access: RW
5476  */
5477 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
5478
5479 /* reg_hpkt_trap_id
5480  * Trap ID.
5481  * Access: Index
5482  *
5483  * Note: A trap ID can only be associated with a single trap group. The device
5484  * will associate the trap ID with the last trap group configured.
5485  */
5486 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
5487
5488 enum {
5489         MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
5490         MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
5491         MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
5492 };
5493
5494 /* reg_hpkt_ctrl
5495  * Configure dedicated buffer resources for control packets.
5496  * Ignored by SwitchX-2.
5497  * 0 - Keep factory defaults.
5498  * 1 - Do not use control buffer for this trap ID.
5499  * 2 - Use control buffer for this trap ID.
5500  * Access: RW
5501  */
5502 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
5503
5504 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
5505                                        enum mlxsw_reg_htgt_trap_group trap_group,
5506                                        bool is_ctrl)
5507 {
5508         MLXSW_REG_ZERO(hpkt, payload);
5509         mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
5510         mlxsw_reg_hpkt_action_set(payload, action);
5511         mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
5512         mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
5513         mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
5514                                 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
5515                                 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
5516 }
5517
5518 /* RGCR - Router General Configuration Register
5519  * --------------------------------------------
5520  * The register is used for setting up the router configuration.
5521  */
5522 #define MLXSW_REG_RGCR_ID 0x8001
5523 #define MLXSW_REG_RGCR_LEN 0x28
5524
5525 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
5526
5527 /* reg_rgcr_ipv4_en
5528  * IPv4 router enable.
5529  * Access: RW
5530  */
5531 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
5532
5533 /* reg_rgcr_ipv6_en
5534  * IPv6 router enable.
5535  * Access: RW
5536  */
5537 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
5538
5539 /* reg_rgcr_max_router_interfaces
5540  * Defines the maximum number of active router interfaces for all virtual
5541  * routers.
5542  * Access: RW
5543  */
5544 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
5545
5546 /* reg_rgcr_usp
5547  * Update switch priority and packet color.
5548  * 0 - Preserve the value of Switch Priority and packet color.
5549  * 1 - Recalculate the value of Switch Priority and packet color.
5550  * Access: RW
5551  *
5552  * Note: Not supported by SwitchX and SwitchX-2.
5553  */
5554 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
5555
5556 /* reg_rgcr_pcp_rw
5557  * Indicates how to handle the pcp_rewrite_en value:
5558  * 0 - Preserve the value of pcp_rewrite_en.
5559  * 2 - Disable PCP rewrite.
5560  * 3 - Enable PCP rewrite.
5561  * Access: RW
5562  *
5563  * Note: Not supported by SwitchX and SwitchX-2.
5564  */
5565 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
5566
5567 /* reg_rgcr_activity_dis
5568  * Activity disable:
5569  * 0 - Activity will be set when an entry is hit (default).
5570  * 1 - Activity will not be set when an entry is hit.
5571  *
5572  * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
5573  * (RALUE).
5574  * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
5575  * Entry (RAUHT).
5576  * Bits 2:7 are reserved.
5577  * Access: RW
5578  *
5579  * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
5580  */
5581 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
5582
5583 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
5584                                        bool ipv6_en)
5585 {
5586         MLXSW_REG_ZERO(rgcr, payload);
5587         mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
5588         mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
5589 }
5590
5591 /* RITR - Router Interface Table Register
5592  * --------------------------------------
5593  * The register is used to configure the router interface table.
5594  */
5595 #define MLXSW_REG_RITR_ID 0x8002
5596 #define MLXSW_REG_RITR_LEN 0x40
5597
5598 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
5599
5600 /* reg_ritr_enable
5601  * Enables routing on the router interface.
5602  * Access: RW
5603  */
5604 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
5605
5606 /* reg_ritr_ipv4
5607  * IPv4 routing enable. Enables routing of IPv4 traffic on the router
5608  * interface.
5609  * Access: RW
5610  */
5611 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
5612
5613 /* reg_ritr_ipv6
5614  * IPv6 routing enable. Enables routing of IPv6 traffic on the router
5615  * interface.
5616  * Access: RW
5617  */
5618 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
5619
5620 /* reg_ritr_ipv4_mc
5621  * IPv4 multicast routing enable.
5622  * Access: RW
5623  */
5624 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
5625
5626 /* reg_ritr_ipv6_mc
5627  * IPv6 multicast routing enable.
5628  * Access: RW
5629  */
5630 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
5631
5632 enum mlxsw_reg_ritr_if_type {
5633         /* VLAN interface. */
5634         MLXSW_REG_RITR_VLAN_IF,
5635         /* FID interface. */
5636         MLXSW_REG_RITR_FID_IF,
5637         /* Sub-port interface. */
5638         MLXSW_REG_RITR_SP_IF,
5639         /* Loopback Interface. */
5640         MLXSW_REG_RITR_LOOPBACK_IF,
5641 };
5642
5643 /* reg_ritr_type
5644  * Router interface type as per enum mlxsw_reg_ritr_if_type.
5645  * Access: RW
5646  */
5647 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
5648
5649 enum {
5650         MLXSW_REG_RITR_RIF_CREATE,
5651         MLXSW_REG_RITR_RIF_DEL,
5652 };
5653
5654 /* reg_ritr_op
5655  * Opcode:
5656  * 0 - Create or edit RIF.
5657  * 1 - Delete RIF.
5658  * Reserved for SwitchX-2. For Spectrum, editing of interface properties
5659  * is not supported. An interface must be deleted and re-created in order
5660  * to update properties.
5661  * Access: WO
5662  */
5663 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
5664
5665 /* reg_ritr_rif
5666  * Router interface index. A pointer to the Router Interface Table.
5667  * Access: Index
5668  */
5669 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
5670
5671 /* reg_ritr_ipv4_fe
5672  * IPv4 Forwarding Enable.
5673  * Enables routing of IPv4 traffic on the router interface. When disabled,
5674  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5675  * Not supported in SwitchX-2.
5676  * Access: RW
5677  */
5678 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
5679
5680 /* reg_ritr_ipv6_fe
5681  * IPv6 Forwarding Enable.
5682  * Enables routing of IPv6 traffic on the router interface. When disabled,
5683  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5684  * Not supported in SwitchX-2.
5685  * Access: RW
5686  */
5687 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
5688
5689 /* reg_ritr_ipv4_mc_fe
5690  * IPv4 Multicast Forwarding Enable.
5691  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5692  * will be enabled.
5693  * Access: RW
5694  */
5695 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
5696
5697 /* reg_ritr_ipv6_mc_fe
5698  * IPv6 Multicast Forwarding Enable.
5699  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5700  * will be enabled.
5701  * Access: RW
5702  */
5703 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
5704
5705 /* reg_ritr_lb_en
5706  * Loop-back filter enable for unicast packets.
5707  * If the flag is set then loop-back filter for unicast packets is
5708  * implemented on the RIF. Multicast packets are always subject to
5709  * loop-back filtering.
5710  * Access: RW
5711  */
5712 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
5713
5714 /* reg_ritr_virtual_router
5715  * Virtual router ID associated with the router interface.
5716  * Access: RW
5717  */
5718 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
5719
5720 /* reg_ritr_mtu
5721  * Router interface MTU.
5722  * Access: RW
5723  */
5724 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
5725
5726 /* reg_ritr_if_swid
5727  * Switch partition ID.
5728  * Access: RW
5729  */
5730 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
5731
5732 /* reg_ritr_if_mac
5733  * Router interface MAC address.
5734  * In Spectrum, all MAC addresses must have the same 38 MSBits.
5735  * Access: RW
5736  */
5737 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
5738
5739 /* reg_ritr_if_vrrp_id_ipv6
5740  * VRRP ID for IPv6
5741  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5742  * Access: RW
5743  */
5744 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
5745
5746 /* reg_ritr_if_vrrp_id_ipv4
5747  * VRRP ID for IPv4
5748  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5749  * Access: RW
5750  */
5751 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
5752
5753 /* VLAN Interface */
5754
5755 /* reg_ritr_vlan_if_vid
5756  * VLAN ID.
5757  * Access: RW
5758  */
5759 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
5760
5761 /* FID Interface */
5762
5763 /* reg_ritr_fid_if_fid
5764  * Filtering ID. Used to connect a bridge to the router. Only FIDs from
5765  * the vFID range are supported.
5766  * Access: RW
5767  */
5768 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
5769
5770 static inline void mlxsw_reg_ritr_fid_set(char *payload,
5771                                           enum mlxsw_reg_ritr_if_type rif_type,
5772                                           u16 fid)
5773 {
5774         if (rif_type == MLXSW_REG_RITR_FID_IF)
5775                 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
5776         else
5777                 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
5778 }
5779
5780 /* Sub-port Interface */
5781
5782 /* reg_ritr_sp_if_lag
5783  * LAG indication. When this bit is set the system_port field holds the
5784  * LAG identifier.
5785  * Access: RW
5786  */
5787 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
5788
5789 /* reg_ritr_sp_system_port
5790  * Port unique indentifier. When lag bit is set, this field holds the
5791  * lag_id in bits 0:9.
5792  * Access: RW
5793  */
5794 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
5795
5796 /* reg_ritr_sp_if_vid
5797  * VLAN ID.
5798  * Access: RW
5799  */
5800 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
5801
5802 /* Loopback Interface */
5803
5804 enum mlxsw_reg_ritr_loopback_protocol {
5805         /* IPinIP IPv4 underlay Unicast */
5806         MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
5807         /* IPinIP IPv6 underlay Unicast */
5808         MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
5809         /* IPinIP generic - used for Spectrum-2 underlay RIF */
5810         MLXSW_REG_RITR_LOOPBACK_GENERIC,
5811 };
5812
5813 /* reg_ritr_loopback_protocol
5814  * Access: RW
5815  */
5816 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
5817
5818 enum mlxsw_reg_ritr_loopback_ipip_type {
5819         /* Tunnel is IPinIP. */
5820         MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
5821         /* Tunnel is GRE, no key. */
5822         MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
5823         /* Tunnel is GRE, with a key. */
5824         MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
5825 };
5826
5827 /* reg_ritr_loopback_ipip_type
5828  * Encapsulation type.
5829  * Access: RW
5830  */
5831 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
5832
5833 enum mlxsw_reg_ritr_loopback_ipip_options {
5834         /* The key is defined by gre_key. */
5835         MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
5836 };
5837
5838 /* reg_ritr_loopback_ipip_options
5839  * Access: RW
5840  */
5841 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
5842
5843 /* reg_ritr_loopback_ipip_uvr
5844  * Underlay Virtual Router ID.
5845  * Range is 0..cap_max_virtual_routers-1.
5846  * Reserved for Spectrum-2.
5847  * Access: RW
5848  */
5849 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
5850
5851 /* reg_ritr_loopback_ipip_underlay_rif
5852  * Underlay ingress router interface.
5853  * Reserved for Spectrum.
5854  * Access: RW
5855  */
5856 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
5857
5858 /* reg_ritr_loopback_ipip_usip*
5859  * Encapsulation Underlay source IP.
5860  * Access: RW
5861  */
5862 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
5863 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
5864
5865 /* reg_ritr_loopback_ipip_gre_key
5866  * GRE Key.
5867  * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP.
5868  * Access: RW
5869  */
5870 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
5871
5872 /* Shared between ingress/egress */
5873 enum mlxsw_reg_ritr_counter_set_type {
5874         /* No Count. */
5875         MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
5876         /* Basic. Used for router interfaces, counting the following:
5877          *      - Error and Discard counters.
5878          *      - Unicast, Multicast and Broadcast counters. Sharing the
5879          *        same set of counters for the different type of traffic
5880          *        (IPv4, IPv6 and mpls).
5881          */
5882         MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
5883 };
5884
5885 /* reg_ritr_ingress_counter_index
5886  * Counter Index for flow counter.
5887  * Access: RW
5888  */
5889 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
5890
5891 /* reg_ritr_ingress_counter_set_type
5892  * Igress Counter Set Type for router interface counter.
5893  * Access: RW
5894  */
5895 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
5896
5897 /* reg_ritr_egress_counter_index
5898  * Counter Index for flow counter.
5899  * Access: RW
5900  */
5901 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
5902
5903 /* reg_ritr_egress_counter_set_type
5904  * Egress Counter Set Type for router interface counter.
5905  * Access: RW
5906  */
5907 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
5908
5909 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
5910                                                bool enable, bool egress)
5911 {
5912         enum mlxsw_reg_ritr_counter_set_type set_type;
5913
5914         if (enable)
5915                 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
5916         else
5917                 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
5918         mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
5919
5920         if (egress)
5921                 mlxsw_reg_ritr_egress_counter_index_set(payload, index);
5922         else
5923                 mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
5924 }
5925
5926 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
5927 {
5928         MLXSW_REG_ZERO(ritr, payload);
5929         mlxsw_reg_ritr_rif_set(payload, rif);
5930 }
5931
5932 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
5933                                              u16 system_port, u16 vid)
5934 {
5935         mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
5936         mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
5937         mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
5938 }
5939
5940 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
5941                                        enum mlxsw_reg_ritr_if_type type,
5942                                        u16 rif, u16 vr_id, u16 mtu)
5943 {
5944         bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
5945
5946         MLXSW_REG_ZERO(ritr, payload);
5947         mlxsw_reg_ritr_enable_set(payload, enable);
5948         mlxsw_reg_ritr_ipv4_set(payload, 1);
5949         mlxsw_reg_ritr_ipv6_set(payload, 1);
5950         mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
5951         mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
5952         mlxsw_reg_ritr_type_set(payload, type);
5953         mlxsw_reg_ritr_op_set(payload, op);
5954         mlxsw_reg_ritr_rif_set(payload, rif);
5955         mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
5956         mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
5957         mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
5958         mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
5959         mlxsw_reg_ritr_lb_en_set(payload, 1);
5960         mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
5961         mlxsw_reg_ritr_mtu_set(payload, mtu);
5962 }
5963
5964 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
5965 {
5966         mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
5967 }
5968
5969 static inline void
5970 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
5971                             enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
5972                             enum mlxsw_reg_ritr_loopback_ipip_options options,
5973                             u16 uvr_id, u16 underlay_rif, u32 gre_key)
5974 {
5975         mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
5976         mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
5977         mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
5978         mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);
5979         mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
5980 }
5981
5982 static inline void
5983 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
5984                             enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
5985                             enum mlxsw_reg_ritr_loopback_ipip_options options,
5986                             u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)
5987 {
5988         mlxsw_reg_ritr_loopback_protocol_set(payload,
5989                                     MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
5990         mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
5991                                                  uvr_id, underlay_rif, gre_key);
5992         mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
5993 }
5994
5995 /* RTAR - Router TCAM Allocation Register
5996  * --------------------------------------
5997  * This register is used for allocation of regions in the TCAM table.
5998  */
5999 #define MLXSW_REG_RTAR_ID 0x8004
6000 #define MLXSW_REG_RTAR_LEN 0x20
6001
6002 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
6003
6004 enum mlxsw_reg_rtar_op {
6005         MLXSW_REG_RTAR_OP_ALLOCATE,
6006         MLXSW_REG_RTAR_OP_RESIZE,
6007         MLXSW_REG_RTAR_OP_DEALLOCATE,
6008 };
6009
6010 /* reg_rtar_op
6011  * Access: WO
6012  */
6013 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
6014
6015 enum mlxsw_reg_rtar_key_type {
6016         MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
6017         MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
6018 };
6019
6020 /* reg_rtar_key_type
6021  * TCAM key type for the region.
6022  * Access: WO
6023  */
6024 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
6025
6026 /* reg_rtar_region_size
6027  * TCAM region size. When allocating/resizing this is the requested
6028  * size, the response is the actual size.
6029  * Note: Actual size may be larger than requested.
6030  * Reserved for op = Deallocate
6031  * Access: WO
6032  */
6033 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
6034
6035 static inline void mlxsw_reg_rtar_pack(char *payload,
6036                                        enum mlxsw_reg_rtar_op op,
6037                                        enum mlxsw_reg_rtar_key_type key_type,
6038                                        u16 region_size)
6039 {
6040         MLXSW_REG_ZERO(rtar, payload);
6041         mlxsw_reg_rtar_op_set(payload, op);
6042         mlxsw_reg_rtar_key_type_set(payload, key_type);
6043         mlxsw_reg_rtar_region_size_set(payload, region_size);
6044 }
6045
6046 /* RATR - Router Adjacency Table Register
6047  * --------------------------------------
6048  * The RATR register is used to configure the Router Adjacency (next-hop)
6049  * Table.
6050  */
6051 #define MLXSW_REG_RATR_ID 0x8008
6052 #define MLXSW_REG_RATR_LEN 0x2C
6053
6054 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
6055
6056 enum mlxsw_reg_ratr_op {
6057         /* Read */
6058         MLXSW_REG_RATR_OP_QUERY_READ = 0,
6059         /* Read and clear activity */
6060         MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
6061         /* Write Adjacency entry */
6062         MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
6063         /* Write Adjacency entry only if the activity is cleared.
6064          * The write may not succeed if the activity is set. There is not
6065          * direct feedback if the write has succeeded or not, however
6066          * the get will reveal the actual entry (SW can compare the get
6067          * response to the set command).
6068          */
6069         MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
6070 };
6071
6072 /* reg_ratr_op
6073  * Note that Write operation may also be used for updating
6074  * counter_set_type and counter_index. In this case all other
6075  * fields must not be updated.
6076  * Access: OP
6077  */
6078 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
6079
6080 /* reg_ratr_v
6081  * Valid bit. Indicates if the adjacency entry is valid.
6082  * Note: the device may need some time before reusing an invalidated
6083  * entry. During this time the entry can not be reused. It is
6084  * recommended to use another entry before reusing an invalidated
6085  * entry (e.g. software can put it at the end of the list for
6086  * reusing). Trying to access an invalidated entry not yet cleared
6087  * by the device results with failure indicating "Try Again" status.
6088  * When valid is '0' then egress_router_interface,trap_action,
6089  * adjacency_parameters and counters are reserved
6090  * Access: RW
6091  */
6092 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
6093
6094 /* reg_ratr_a
6095  * Activity. Set for new entries. Set if a packet lookup has hit on
6096  * the specific entry. To clear the a bit, use "clear activity".
6097  * Access: RO
6098  */
6099 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
6100
6101 enum mlxsw_reg_ratr_type {
6102         /* Ethernet */
6103         MLXSW_REG_RATR_TYPE_ETHERNET,
6104         /* IPoIB Unicast without GRH.
6105          * Reserved for Spectrum.
6106          */
6107         MLXSW_REG_RATR_TYPE_IPOIB_UC,
6108         /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast
6109          * adjacency).
6110          * Reserved for Spectrum.
6111          */
6112         MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
6113         /* IPoIB Multicast.
6114          * Reserved for Spectrum.
6115          */
6116         MLXSW_REG_RATR_TYPE_IPOIB_MC,
6117         /* MPLS.
6118          * Reserved for SwitchX/-2.
6119          */
6120         MLXSW_REG_RATR_TYPE_MPLS,
6121         /* IPinIP Encap.
6122          * Reserved for SwitchX/-2.
6123          */
6124         MLXSW_REG_RATR_TYPE_IPIP,
6125 };
6126
6127 /* reg_ratr_type
6128  * Adjacency entry type.
6129  * Access: RW
6130  */
6131 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
6132
6133 /* reg_ratr_adjacency_index_low
6134  * Bits 15:0 of index into the adjacency table.
6135  * For SwitchX and SwitchX-2, the adjacency table is linear and
6136  * used for adjacency entries only.
6137  * For Spectrum, the index is to the KVD linear.
6138  * Access: Index
6139  */
6140 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
6141
6142 /* reg_ratr_egress_router_interface
6143  * Range is 0 .. cap_max_router_interfaces - 1
6144  * Access: RW
6145  */
6146 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
6147
6148 enum mlxsw_reg_ratr_trap_action {
6149         MLXSW_REG_RATR_TRAP_ACTION_NOP,
6150         MLXSW_REG_RATR_TRAP_ACTION_TRAP,
6151         MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
6152         MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
6153         MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
6154 };
6155
6156 /* reg_ratr_trap_action
6157  * see mlxsw_reg_ratr_trap_action
6158  * Access: RW
6159  */
6160 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
6161
6162 /* reg_ratr_adjacency_index_high
6163  * Bits 23:16 of the adjacency_index.
6164  * Access: Index
6165  */
6166 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
6167
6168 enum mlxsw_reg_ratr_trap_id {
6169         MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
6170         MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
6171 };
6172
6173 /* reg_ratr_trap_id
6174  * Trap ID to be reported to CPU.
6175  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
6176  * For trap_action of NOP, MIRROR and DISCARD_ERROR
6177  * Access: RW
6178  */
6179 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
6180
6181 /* reg_ratr_eth_destination_mac
6182  * MAC address of the destination next-hop.
6183  * Access: RW
6184  */
6185 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
6186
6187 enum mlxsw_reg_ratr_ipip_type {
6188         /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */
6189         MLXSW_REG_RATR_IPIP_TYPE_IPV4,
6190         /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */
6191         MLXSW_REG_RATR_IPIP_TYPE_IPV6,
6192 };
6193
6194 /* reg_ratr_ipip_type
6195  * Underlay destination ip type.
6196  * Note: the type field must match the protocol of the router interface.
6197  * Access: RW
6198  */
6199 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
6200
6201 /* reg_ratr_ipip_ipv4_udip
6202  * Underlay ipv4 dip.
6203  * Reserved when ipip_type is IPv6.
6204  * Access: RW
6205  */
6206 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
6207
6208 /* reg_ratr_ipip_ipv6_ptr
6209  * Pointer to IPv6 underlay destination ip address.
6210  * For Spectrum: Pointer to KVD linear space.
6211  * Access: RW
6212  */
6213 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
6214
6215 enum mlxsw_reg_flow_counter_set_type {
6216         /* No count */
6217         MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6218         /* Count packets and bytes */
6219         MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
6220         /* Count only packets */
6221         MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
6222 };
6223
6224 /* reg_ratr_counter_set_type
6225  * Counter set type for flow counters
6226  * Access: RW
6227  */
6228 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
6229
6230 /* reg_ratr_counter_index
6231  * Counter index for flow counters
6232  * Access: RW
6233  */
6234 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
6235
6236 static inline void
6237 mlxsw_reg_ratr_pack(char *payload,
6238                     enum mlxsw_reg_ratr_op op, bool valid,
6239                     enum mlxsw_reg_ratr_type type,
6240                     u32 adjacency_index, u16 egress_rif)
6241 {
6242         MLXSW_REG_ZERO(ratr, payload);
6243         mlxsw_reg_ratr_op_set(payload, op);
6244         mlxsw_reg_ratr_v_set(payload, valid);
6245         mlxsw_reg_ratr_type_set(payload, type);
6246         mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
6247         mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
6248         mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
6249 }
6250
6251 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
6252                                                  const char *dest_mac)
6253 {
6254         mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
6255 }
6256
6257 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
6258 {
6259         mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
6260         mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
6261 }
6262
6263 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
6264                                                bool counter_enable)
6265 {
6266         enum mlxsw_reg_flow_counter_set_type set_type;
6267
6268         if (counter_enable)
6269                 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
6270         else
6271                 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
6272
6273         mlxsw_reg_ratr_counter_index_set(payload, counter_index);
6274         mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
6275 }
6276
6277 /* RDPM - Router DSCP to Priority Mapping
6278  * --------------------------------------
6279  * Controls the mapping from DSCP field to switch priority on routed packets
6280  */
6281 #define MLXSW_REG_RDPM_ID 0x8009
6282 #define MLXSW_REG_RDPM_BASE_LEN 0x00
6283 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
6284 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
6285 #define MLXSW_REG_RDPM_LEN 0x40
6286 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
6287                                    MLXSW_REG_RDPM_LEN - \
6288                                    MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
6289
6290 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
6291
6292 /* reg_dscp_entry_e
6293  * Enable update of the specific entry
6294  * Access: Index
6295  */
6296 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
6297                     -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6298
6299 /* reg_dscp_entry_prio
6300  * Switch Priority
6301  * Access: RW
6302  */
6303 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
6304                     -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6305
6306 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
6307                                        u8 prio)
6308 {
6309         mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
6310         mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
6311 }
6312
6313 /* RICNT - Router Interface Counter Register
6314  * -----------------------------------------
6315  * The RICNT register retrieves per port performance counters
6316  */
6317 #define MLXSW_REG_RICNT_ID 0x800B
6318 #define MLXSW_REG_RICNT_LEN 0x100
6319
6320 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
6321
6322 /* reg_ricnt_counter_index
6323  * Counter index
6324  * Access: RW
6325  */
6326 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
6327
6328 enum mlxsw_reg_ricnt_counter_set_type {
6329         /* No Count. */
6330         MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6331         /* Basic. Used for router interfaces, counting the following:
6332          *      - Error and Discard counters.
6333          *      - Unicast, Multicast and Broadcast counters. Sharing the
6334          *        same set of counters for the different type of traffic
6335          *        (IPv4, IPv6 and mpls).
6336          */
6337         MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
6338 };
6339
6340 /* reg_ricnt_counter_set_type
6341  * Counter Set Type for router interface counter
6342  * Access: RW
6343  */
6344 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
6345
6346 enum mlxsw_reg_ricnt_opcode {
6347         /* Nop. Supported only for read access*/
6348         MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
6349         /* Clear. Setting the clr bit will reset the counter value for
6350          * all counters of the specified Router Interface.
6351          */
6352         MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
6353 };
6354
6355 /* reg_ricnt_opcode
6356  * Opcode
6357  * Access: RW
6358  */
6359 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
6360
6361 /* reg_ricnt_good_unicast_packets
6362  * good unicast packets.
6363  * Access: RW
6364  */
6365 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
6366
6367 /* reg_ricnt_good_multicast_packets
6368  * good multicast packets.
6369  * Access: RW
6370  */
6371 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
6372
6373 /* reg_ricnt_good_broadcast_packets
6374  * good broadcast packets
6375  * Access: RW
6376  */
6377 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
6378
6379 /* reg_ricnt_good_unicast_bytes
6380  * A count of L3 data and padding octets not including L2 headers
6381  * for good unicast frames.
6382  * Access: RW
6383  */
6384 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
6385
6386 /* reg_ricnt_good_multicast_bytes
6387  * A count of L3 data and padding octets not including L2 headers
6388  * for good multicast frames.
6389  * Access: RW
6390  */
6391 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
6392
6393 /* reg_ritr_good_broadcast_bytes
6394  * A count of L3 data and padding octets not including L2 headers
6395  * for good broadcast frames.
6396  * Access: RW
6397  */
6398 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
6399
6400 /* reg_ricnt_error_packets
6401  * A count of errored frames that do not pass the router checks.
6402  * Access: RW
6403  */
6404 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
6405
6406 /* reg_ricnt_discrad_packets
6407  * A count of non-errored frames that do not pass the router checks.
6408  * Access: RW
6409  */
6410 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
6411
6412 /* reg_ricnt_error_bytes
6413  * A count of L3 data and padding octets not including L2 headers
6414  * for errored frames.
6415  * Access: RW
6416  */
6417 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
6418
6419 /* reg_ricnt_discard_bytes
6420  * A count of L3 data and padding octets not including L2 headers
6421  * for non-errored frames that do not pass the router checks.
6422  * Access: RW
6423  */
6424 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
6425
6426 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
6427                                         enum mlxsw_reg_ricnt_opcode op)
6428 {
6429         MLXSW_REG_ZERO(ricnt, payload);
6430         mlxsw_reg_ricnt_op_set(payload, op);
6431         mlxsw_reg_ricnt_counter_index_set(payload, index);
6432         mlxsw_reg_ricnt_counter_set_type_set(payload,
6433                                              MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
6434 }
6435
6436 /* RRCR - Router Rules Copy Register Layout
6437  * ----------------------------------------
6438  * This register is used for moving and copying route entry rules.
6439  */
6440 #define MLXSW_REG_RRCR_ID 0x800F
6441 #define MLXSW_REG_RRCR_LEN 0x24
6442
6443 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
6444
6445 enum mlxsw_reg_rrcr_op {
6446         /* Move rules */
6447         MLXSW_REG_RRCR_OP_MOVE,
6448         /* Copy rules */
6449         MLXSW_REG_RRCR_OP_COPY,
6450 };
6451
6452 /* reg_rrcr_op
6453  * Access: WO
6454  */
6455 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
6456
6457 /* reg_rrcr_offset
6458  * Offset within the region from which to copy/move.
6459  * Access: Index
6460  */
6461 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
6462
6463 /* reg_rrcr_size
6464  * The number of rules to copy/move.
6465  * Access: WO
6466  */
6467 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
6468
6469 /* reg_rrcr_table_id
6470  * Identifier of the table on which to perform the operation. Encoding is the
6471  * same as in RTAR.key_type
6472  * Access: Index
6473  */
6474 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
6475
6476 /* reg_rrcr_dest_offset
6477  * Offset within the region to which to copy/move
6478  * Access: Index
6479  */
6480 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
6481
6482 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
6483                                        u16 offset, u16 size,
6484                                        enum mlxsw_reg_rtar_key_type table_id,
6485                                        u16 dest_offset)
6486 {
6487         MLXSW_REG_ZERO(rrcr, payload);
6488         mlxsw_reg_rrcr_op_set(payload, op);
6489         mlxsw_reg_rrcr_offset_set(payload, offset);
6490         mlxsw_reg_rrcr_size_set(payload, size);
6491         mlxsw_reg_rrcr_table_id_set(payload, table_id);
6492         mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
6493 }
6494
6495 /* RALTA - Router Algorithmic LPM Tree Allocation Register
6496  * -------------------------------------------------------
6497  * RALTA is used to allocate the LPM trees of the SHSPM method.
6498  */
6499 #define MLXSW_REG_RALTA_ID 0x8010
6500 #define MLXSW_REG_RALTA_LEN 0x04
6501
6502 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
6503
6504 /* reg_ralta_op
6505  * opcode (valid for Write, must be 0 on Read)
6506  * 0 - allocate a tree
6507  * 1 - deallocate a tree
6508  * Access: OP
6509  */
6510 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
6511
6512 enum mlxsw_reg_ralxx_protocol {
6513         MLXSW_REG_RALXX_PROTOCOL_IPV4,
6514         MLXSW_REG_RALXX_PROTOCOL_IPV6,
6515 };
6516
6517 /* reg_ralta_protocol
6518  * Protocol.
6519  * Deallocation opcode: Reserved.
6520  * Access: RW
6521  */
6522 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
6523
6524 /* reg_ralta_tree_id
6525  * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
6526  * the tree identifier (managed by software).
6527  * Note that tree_id 0 is allocated for a default-route tree.
6528  * Access: Index
6529  */
6530 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
6531
6532 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
6533                                         enum mlxsw_reg_ralxx_protocol protocol,
6534                                         u8 tree_id)
6535 {
6536         MLXSW_REG_ZERO(ralta, payload);
6537         mlxsw_reg_ralta_op_set(payload, !alloc);
6538         mlxsw_reg_ralta_protocol_set(payload, protocol);
6539         mlxsw_reg_ralta_tree_id_set(payload, tree_id);
6540 }
6541
6542 /* RALST - Router Algorithmic LPM Structure Tree Register
6543  * ------------------------------------------------------
6544  * RALST is used to set and query the structure of an LPM tree.
6545  * The structure of the tree must be sorted as a sorted binary tree, while
6546  * each node is a bin that is tagged as the length of the prefixes the lookup
6547  * will refer to. Therefore, bin X refers to a set of entries with prefixes
6548  * of X bits to match with the destination address. The bin 0 indicates
6549  * the default action, when there is no match of any prefix.
6550  */
6551 #define MLXSW_REG_RALST_ID 0x8011
6552 #define MLXSW_REG_RALST_LEN 0x104
6553
6554 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
6555
6556 /* reg_ralst_root_bin
6557  * The bin number of the root bin.
6558  * 0<root_bin=<(length of IP address)
6559  * For a default-route tree configure 0xff
6560  * Access: RW
6561  */
6562 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
6563
6564 /* reg_ralst_tree_id
6565  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6566  * Access: Index
6567  */
6568 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
6569
6570 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
6571 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
6572 #define MLXSW_REG_RALST_BIN_COUNT 128
6573
6574 /* reg_ralst_left_child_bin
6575  * Holding the children of the bin according to the stored tree's structure.
6576  * For trees composed of less than 4 blocks, the bins in excess are reserved.
6577  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6578  * Access: RW
6579  */
6580 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
6581
6582 /* reg_ralst_right_child_bin
6583  * Holding the children of the bin according to the stored tree's structure.
6584  * For trees composed of less than 4 blocks, the bins in excess are reserved.
6585  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6586  * Access: RW
6587  */
6588 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
6589                      false);
6590
6591 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
6592 {
6593         MLXSW_REG_ZERO(ralst, payload);
6594
6595         /* Initialize all bins to have no left or right child */
6596         memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
6597                MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
6598
6599         mlxsw_reg_ralst_root_bin_set(payload, root_bin);
6600         mlxsw_reg_ralst_tree_id_set(payload, tree_id);
6601 }
6602
6603 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
6604                                             u8 left_child_bin,
6605                                             u8 right_child_bin)
6606 {
6607         int bin_index = bin_number - 1;
6608
6609         mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
6610         mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
6611                                             right_child_bin);
6612 }
6613
6614 /* RALTB - Router Algorithmic LPM Tree Binding Register
6615  * ----------------------------------------------------
6616  * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
6617  */
6618 #define MLXSW_REG_RALTB_ID 0x8012
6619 #define MLXSW_REG_RALTB_LEN 0x04
6620
6621 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
6622
6623 /* reg_raltb_virtual_router
6624  * Virtual Router ID
6625  * Range is 0..cap_max_virtual_routers-1
6626  * Access: Index
6627  */
6628 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
6629
6630 /* reg_raltb_protocol
6631  * Protocol.
6632  * Access: Index
6633  */
6634 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
6635
6636 /* reg_raltb_tree_id
6637  * Tree to be used for the {virtual_router, protocol}
6638  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6639  * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
6640  * Access: RW
6641  */
6642 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
6643
6644 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
6645                                         enum mlxsw_reg_ralxx_protocol protocol,
6646                                         u8 tree_id)
6647 {
6648         MLXSW_REG_ZERO(raltb, payload);
6649         mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
6650         mlxsw_reg_raltb_protocol_set(payload, protocol);
6651         mlxsw_reg_raltb_tree_id_set(payload, tree_id);
6652 }
6653
6654 /* RALUE - Router Algorithmic LPM Unicast Entry Register
6655  * -----------------------------------------------------
6656  * RALUE is used to configure and query LPM entries that serve
6657  * the Unicast protocols.
6658  */
6659 #define MLXSW_REG_RALUE_ID 0x8013
6660 #define MLXSW_REG_RALUE_LEN 0x38
6661
6662 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
6663
6664 /* reg_ralue_protocol
6665  * Protocol.
6666  * Access: Index
6667  */
6668 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
6669
6670 enum mlxsw_reg_ralue_op {
6671         /* Read operation. If entry doesn't exist, the operation fails. */
6672         MLXSW_REG_RALUE_OP_QUERY_READ = 0,
6673         /* Clear on read operation. Used to read entry and
6674          * clear Activity bit.
6675          */
6676         MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
6677         /* Write operation. Used to write a new entry to the table. All RW
6678          * fields are written for new entry. Activity bit is set
6679          * for new entries.
6680          */
6681         MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
6682         /* Update operation. Used to update an existing route entry and
6683          * only update the RW fields that are detailed in the field
6684          * op_u_mask. If entry doesn't exist, the operation fails.
6685          */
6686         MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
6687         /* Clear activity. The Activity bit (the field a) is cleared
6688          * for the entry.
6689          */
6690         MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
6691         /* Delete operation. Used to delete an existing entry. If entry
6692          * doesn't exist, the operation fails.
6693          */
6694         MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
6695 };
6696
6697 /* reg_ralue_op
6698  * Operation.
6699  * Access: OP
6700  */
6701 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
6702
6703 /* reg_ralue_a
6704  * Activity. Set for new entries. Set if a packet lookup has hit on the
6705  * specific entry, only if the entry is a route. To clear the a bit, use
6706  * "clear activity" op.
6707  * Enabled by activity_dis in RGCR
6708  * Access: RO
6709  */
6710 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
6711
6712 /* reg_ralue_virtual_router
6713  * Virtual Router ID
6714  * Range is 0..cap_max_virtual_routers-1
6715  * Access: Index
6716  */
6717 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
6718
6719 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE    BIT(0)
6720 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN       BIT(1)
6721 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION        BIT(2)
6722
6723 /* reg_ralue_op_u_mask
6724  * opcode update mask.
6725  * On read operation, this field is reserved.
6726  * This field is valid for update opcode, otherwise - reserved.
6727  * This field is a bitmask of the fields that should be updated.
6728  * Access: WO
6729  */
6730 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
6731
6732 /* reg_ralue_prefix_len
6733  * Number of bits in the prefix of the LPM route.
6734  * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
6735  * two entries in the physical HW table.
6736  * Access: Index
6737  */
6738 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
6739
6740 /* reg_ralue_dip*
6741  * The prefix of the route or of the marker that the object of the LPM
6742  * is compared with. The most significant bits of the dip are the prefix.
6743  * The least significant bits must be '0' if the prefix_len is smaller
6744  * than 128 for IPv6 or smaller than 32 for IPv4.
6745  * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
6746  * Access: Index
6747  */
6748 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
6749 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
6750
6751 enum mlxsw_reg_ralue_entry_type {
6752         MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
6753         MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
6754         MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
6755 };
6756
6757 /* reg_ralue_entry_type
6758  * Entry type.
6759  * Note - for Marker entries, the action_type and action fields are reserved.
6760  * Access: RW
6761  */
6762 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
6763
6764 /* reg_ralue_bmp_len
6765  * The best match prefix length in the case that there is no match for
6766  * longer prefixes.
6767  * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
6768  * Note for any update operation with entry_type modification this
6769  * field must be set.
6770  * Access: RW
6771  */
6772 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
6773
6774 enum mlxsw_reg_ralue_action_type {
6775         MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
6776         MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
6777         MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
6778 };
6779
6780 /* reg_ralue_action_type
6781  * Action Type
6782  * Indicates how the IP address is connected.
6783  * It can be connected to a local subnet through local_erif or can be
6784  * on a remote subnet connected through a next-hop router,
6785  * or transmitted to the CPU.
6786  * Reserved when entry_type = MARKER_ENTRY
6787  * Access: RW
6788  */
6789 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
6790
6791 enum mlxsw_reg_ralue_trap_action {
6792         MLXSW_REG_RALUE_TRAP_ACTION_NOP,
6793         MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
6794         MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
6795         MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
6796         MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
6797 };
6798
6799 /* reg_ralue_trap_action
6800  * Trap action.
6801  * For IP2ME action, only NOP and MIRROR are possible.
6802  * Access: RW
6803  */
6804 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
6805
6806 /* reg_ralue_trap_id
6807  * Trap ID to be reported to CPU.
6808  * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
6809  * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
6810  * Access: RW
6811  */
6812 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
6813
6814 /* reg_ralue_adjacency_index
6815  * Points to the first entry of the group-based ECMP.
6816  * Only relevant in case of REMOTE action.
6817  * Access: RW
6818  */
6819 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
6820
6821 /* reg_ralue_ecmp_size
6822  * Amount of sequential entries starting
6823  * from the adjacency_index (the number of ECMPs).
6824  * The valid range is 1-64, 512, 1024, 2048 and 4096.
6825  * Reserved when trap_action is TRAP or DISCARD_ERROR.
6826  * Only relevant in case of REMOTE action.
6827  * Access: RW
6828  */
6829 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
6830
6831 /* reg_ralue_local_erif
6832  * Egress Router Interface.
6833  * Only relevant in case of LOCAL action.
6834  * Access: RW
6835  */
6836 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
6837
6838 /* reg_ralue_ip2me_v
6839  * Valid bit for the tunnel_ptr field.
6840  * If valid = 0 then trap to CPU as IP2ME trap ID.
6841  * If valid = 1 and the packet format allows NVE or IPinIP tunnel
6842  * decapsulation then tunnel decapsulation is done.
6843  * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
6844  * decapsulation then trap as IP2ME trap ID.
6845  * Only relevant in case of IP2ME action.
6846  * Access: RW
6847  */
6848 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
6849
6850 /* reg_ralue_ip2me_tunnel_ptr
6851  * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
6852  * For Spectrum, pointer to KVD Linear.
6853  * Only relevant in case of IP2ME action.
6854  * Access: RW
6855  */
6856 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
6857
6858 static inline void mlxsw_reg_ralue_pack(char *payload,
6859                                         enum mlxsw_reg_ralxx_protocol protocol,
6860                                         enum mlxsw_reg_ralue_op op,
6861                                         u16 virtual_router, u8 prefix_len)
6862 {
6863         MLXSW_REG_ZERO(ralue, payload);
6864         mlxsw_reg_ralue_protocol_set(payload, protocol);
6865         mlxsw_reg_ralue_op_set(payload, op);
6866         mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
6867         mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
6868         mlxsw_reg_ralue_entry_type_set(payload,
6869                                        MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
6870         mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
6871 }
6872
6873 static inline void mlxsw_reg_ralue_pack4(char *payload,
6874                                          enum mlxsw_reg_ralxx_protocol protocol,
6875                                          enum mlxsw_reg_ralue_op op,
6876                                          u16 virtual_router, u8 prefix_len,
6877                                          u32 dip)
6878 {
6879         mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6880         mlxsw_reg_ralue_dip4_set(payload, dip);
6881 }
6882
6883 static inline void mlxsw_reg_ralue_pack6(char *payload,
6884                                          enum mlxsw_reg_ralxx_protocol protocol,
6885                                          enum mlxsw_reg_ralue_op op,
6886                                          u16 virtual_router, u8 prefix_len,
6887                                          const void *dip)
6888 {
6889         mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6890         mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
6891 }
6892
6893 static inline void
6894 mlxsw_reg_ralue_act_remote_pack(char *payload,
6895                                 enum mlxsw_reg_ralue_trap_action trap_action,
6896                                 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
6897 {
6898         mlxsw_reg_ralue_action_type_set(payload,
6899                                         MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
6900         mlxsw_reg_ralue_trap_action_set(payload, trap_action);
6901         mlxsw_reg_ralue_trap_id_set(payload, trap_id);
6902         mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
6903         mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
6904 }
6905
6906 static inline void
6907 mlxsw_reg_ralue_act_local_pack(char *payload,
6908                                enum mlxsw_reg_ralue_trap_action trap_action,
6909                                u16 trap_id, u16 local_erif)
6910 {
6911         mlxsw_reg_ralue_action_type_set(payload,
6912                                         MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
6913         mlxsw_reg_ralue_trap_action_set(payload, trap_action);
6914         mlxsw_reg_ralue_trap_id_set(payload, trap_id);
6915         mlxsw_reg_ralue_local_erif_set(payload, local_erif);
6916 }
6917
6918 static inline void
6919 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
6920 {
6921         mlxsw_reg_ralue_action_type_set(payload,
6922                                         MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
6923 }
6924
6925 static inline void
6926 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
6927 {
6928         mlxsw_reg_ralue_action_type_set(payload,
6929                                         MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
6930         mlxsw_reg_ralue_ip2me_v_set(payload, 1);
6931         mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
6932 }
6933
6934 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
6935  * ----------------------------------------------------------
6936  * The RAUHT register is used to configure and query the Unicast Host table in
6937  * devices that implement the Algorithmic LPM.
6938  */
6939 #define MLXSW_REG_RAUHT_ID 0x8014
6940 #define MLXSW_REG_RAUHT_LEN 0x74
6941
6942 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
6943
6944 enum mlxsw_reg_rauht_type {
6945         MLXSW_REG_RAUHT_TYPE_IPV4,
6946         MLXSW_REG_RAUHT_TYPE_IPV6,
6947 };
6948
6949 /* reg_rauht_type
6950  * Access: Index
6951  */
6952 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
6953
6954 enum mlxsw_reg_rauht_op {
6955         MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
6956         /* Read operation */
6957         MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
6958         /* Clear on read operation. Used to read entry and clear
6959          * activity bit.
6960          */
6961         MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
6962         /* Add. Used to write a new entry to the table. All R/W fields are
6963          * relevant for new entry. Activity bit is set for new entries.
6964          */
6965         MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
6966         /* Update action. Used to update an existing route entry and
6967          * only update the following fields:
6968          * trap_action, trap_id, mac, counter_set_type, counter_index
6969          */
6970         MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
6971         /* Clear activity. A bit is cleared for the entry. */
6972         MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
6973         /* Delete entry */
6974         MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
6975         /* Delete all host entries on a RIF. In this command, dip
6976          * field is reserved.
6977          */
6978 };
6979
6980 /* reg_rauht_op
6981  * Access: OP
6982  */
6983 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
6984
6985 /* reg_rauht_a
6986  * Activity. Set for new entries. Set if a packet lookup has hit on
6987  * the specific entry.
6988  * To clear the a bit, use "clear activity" op.
6989  * Enabled by activity_dis in RGCR
6990  * Access: RO
6991  */
6992 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
6993
6994 /* reg_rauht_rif
6995  * Router Interface
6996  * Access: Index
6997  */
6998 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
6999
7000 /* reg_rauht_dip*
7001  * Destination address.
7002  * Access: Index
7003  */
7004 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
7005 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
7006
7007 enum mlxsw_reg_rauht_trap_action {
7008         MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
7009         MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
7010         MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
7011         MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
7012         MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
7013 };
7014
7015 /* reg_rauht_trap_action
7016  * Access: RW
7017  */
7018 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
7019
7020 enum mlxsw_reg_rauht_trap_id {
7021         MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
7022         MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
7023 };
7024
7025 /* reg_rauht_trap_id
7026  * Trap ID to be reported to CPU.
7027  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
7028  * For trap_action of NOP, MIRROR and DISCARD_ERROR,
7029  * trap_id is reserved.
7030  * Access: RW
7031  */
7032 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
7033
7034 /* reg_rauht_counter_set_type
7035  * Counter set type for flow counters
7036  * Access: RW
7037  */
7038 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
7039
7040 /* reg_rauht_counter_index
7041  * Counter index for flow counters
7042  * Access: RW
7043  */
7044 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
7045
7046 /* reg_rauht_mac
7047  * MAC address.
7048  * Access: RW
7049  */
7050 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
7051
7052 static inline void mlxsw_reg_rauht_pack(char *payload,
7053                                         enum mlxsw_reg_rauht_op op, u16 rif,
7054                                         const char *mac)
7055 {
7056         MLXSW_REG_ZERO(rauht, payload);
7057         mlxsw_reg_rauht_op_set(payload, op);
7058         mlxsw_reg_rauht_rif_set(payload, rif);
7059         mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
7060 }
7061
7062 static inline void mlxsw_reg_rauht_pack4(char *payload,
7063                                          enum mlxsw_reg_rauht_op op, u16 rif,
7064                                          const char *mac, u32 dip)
7065 {
7066         mlxsw_reg_rauht_pack(payload, op, rif, mac);
7067         mlxsw_reg_rauht_dip4_set(payload, dip);
7068 }
7069
7070 static inline void mlxsw_reg_rauht_pack6(char *payload,
7071                                          enum mlxsw_reg_rauht_op op, u16 rif,
7072                                          const char *mac, const char *dip)
7073 {
7074         mlxsw_reg_rauht_pack(payload, op, rif, mac);
7075         mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
7076         mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
7077 }
7078
7079 static inline void mlxsw_reg_rauht_pack_counter(char *payload,
7080                                                 u64 counter_index)
7081 {
7082         mlxsw_reg_rauht_counter_index_set(payload, counter_index);
7083         mlxsw_reg_rauht_counter_set_type_set(payload,
7084                                              MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
7085 }
7086
7087 /* RALEU - Router Algorithmic LPM ECMP Update Register
7088  * ---------------------------------------------------
7089  * The register enables updating the ECMP section in the action for multiple
7090  * LPM Unicast entries in a single operation. The update is executed to
7091  * all entries of a {virtual router, protocol} tuple using the same ECMP group.
7092  */
7093 #define MLXSW_REG_RALEU_ID 0x8015
7094 #define MLXSW_REG_RALEU_LEN 0x28
7095
7096 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
7097
7098 /* reg_raleu_protocol
7099  * Protocol.
7100  * Access: Index
7101  */
7102 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
7103
7104 /* reg_raleu_virtual_router
7105  * Virtual Router ID
7106  * Range is 0..cap_max_virtual_routers-1
7107  * Access: Index
7108  */
7109 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
7110
7111 /* reg_raleu_adjacency_index
7112  * Adjacency Index used for matching on the existing entries.
7113  * Access: Index
7114  */
7115 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
7116
7117 /* reg_raleu_ecmp_size
7118  * ECMP Size used for matching on the existing entries.
7119  * Access: Index
7120  */
7121 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
7122
7123 /* reg_raleu_new_adjacency_index
7124  * New Adjacency Index.
7125  * Access: WO
7126  */
7127 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
7128
7129 /* reg_raleu_new_ecmp_size
7130  * New ECMP Size.
7131  * Access: WO
7132  */
7133 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
7134
7135 static inline void mlxsw_reg_raleu_pack(char *payload,
7136                                         enum mlxsw_reg_ralxx_protocol protocol,
7137                                         u16 virtual_router,
7138                                         u32 adjacency_index, u16 ecmp_size,
7139                                         u32 new_adjacency_index,
7140                                         u16 new_ecmp_size)
7141 {
7142         MLXSW_REG_ZERO(raleu, payload);
7143         mlxsw_reg_raleu_protocol_set(payload, protocol);
7144         mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
7145         mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
7146         mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
7147         mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
7148         mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
7149 }
7150
7151 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
7152  * ----------------------------------------------------------------
7153  * The RAUHTD register allows dumping entries from the Router Unicast Host
7154  * Table. For a given session an entry is dumped no more than one time. The
7155  * first RAUHTD access after reset is a new session. A session ends when the
7156  * num_rec response is smaller than num_rec request or for IPv4 when the
7157  * num_entries is smaller than 4. The clear activity affect the current session
7158  * or the last session if a new session has not started.
7159  */
7160 #define MLXSW_REG_RAUHTD_ID 0x8018
7161 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
7162 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
7163 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
7164 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
7165                 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
7166 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
7167
7168 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
7169
7170 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
7171 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
7172
7173 /* reg_rauhtd_filter_fields
7174  * if a bit is '0' then the relevant field is ignored and dump is done
7175  * regardless of the field value
7176  * Bit0 - filter by activity: entry_a
7177  * Bit3 - filter by entry rip: entry_rif
7178  * Access: Index
7179  */
7180 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
7181
7182 enum mlxsw_reg_rauhtd_op {
7183         MLXSW_REG_RAUHTD_OP_DUMP,
7184         MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
7185 };
7186
7187 /* reg_rauhtd_op
7188  * Access: OP
7189  */
7190 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
7191
7192 /* reg_rauhtd_num_rec
7193  * At request: number of records requested
7194  * At response: number of records dumped
7195  * For IPv4, each record has 4 entries at request and up to 4 entries
7196  * at response
7197  * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
7198  * Access: Index
7199  */
7200 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
7201
7202 /* reg_rauhtd_entry_a
7203  * Dump only if activity has value of entry_a
7204  * Reserved if filter_fields bit0 is '0'
7205  * Access: Index
7206  */
7207 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
7208
7209 enum mlxsw_reg_rauhtd_type {
7210         MLXSW_REG_RAUHTD_TYPE_IPV4,
7211         MLXSW_REG_RAUHTD_TYPE_IPV6,
7212 };
7213
7214 /* reg_rauhtd_type
7215  * Dump only if record type is:
7216  * 0 - IPv4
7217  * 1 - IPv6
7218  * Access: Index
7219  */
7220 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
7221
7222 /* reg_rauhtd_entry_rif
7223  * Dump only if RIF has value of entry_rif
7224  * Reserved if filter_fields bit3 is '0'
7225  * Access: Index
7226  */
7227 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
7228
7229 static inline void mlxsw_reg_rauhtd_pack(char *payload,
7230                                          enum mlxsw_reg_rauhtd_type type)
7231 {
7232         MLXSW_REG_ZERO(rauhtd, payload);
7233         mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
7234         mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
7235         mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
7236         mlxsw_reg_rauhtd_entry_a_set(payload, 1);
7237         mlxsw_reg_rauhtd_type_set(payload, type);
7238 }
7239
7240 /* reg_rauhtd_ipv4_rec_num_entries
7241  * Number of valid entries in this record:
7242  * 0 - 1 valid entry
7243  * 1 - 2 valid entries
7244  * 2 - 3 valid entries
7245  * 3 - 4 valid entries
7246  * Access: RO
7247  */
7248 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
7249                      MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
7250                      MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7251
7252 /* reg_rauhtd_rec_type
7253  * Record type.
7254  * 0 - IPv4
7255  * 1 - IPv6
7256  * Access: RO
7257  */
7258 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
7259                      MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7260
7261 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
7262
7263 /* reg_rauhtd_ipv4_ent_a
7264  * Activity. Set for new entries. Set if a packet lookup has hit on the
7265  * specific entry.
7266  * Access: RO
7267  */
7268 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7269                      MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7270
7271 /* reg_rauhtd_ipv4_ent_rif
7272  * Router interface.
7273  * Access: RO
7274  */
7275 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7276                      16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7277
7278 /* reg_rauhtd_ipv4_ent_dip
7279  * Destination IPv4 address.
7280  * Access: RO
7281  */
7282 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7283                      32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
7284
7285 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
7286
7287 /* reg_rauhtd_ipv6_ent_a
7288  * Activity. Set for new entries. Set if a packet lookup has hit on the
7289  * specific entry.
7290  * Access: RO
7291  */
7292 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7293                      MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7294
7295 /* reg_rauhtd_ipv6_ent_rif
7296  * Router interface.
7297  * Access: RO
7298  */
7299 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7300                      16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7301
7302 /* reg_rauhtd_ipv6_ent_dip
7303  * Destination IPv6 address.
7304  * Access: RO
7305  */
7306 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
7307                        16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
7308
7309 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
7310                                                     int ent_index, u16 *p_rif,
7311                                                     u32 *p_dip)
7312 {
7313         *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
7314         *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
7315 }
7316
7317 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
7318                                                     int rec_index, u16 *p_rif,
7319                                                     char *p_dip)
7320 {
7321         *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
7322         mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
7323 }
7324
7325 /* RTDP - Routing Tunnel Decap Properties Register
7326  * -----------------------------------------------
7327  * The RTDP register is used for configuring the tunnel decap properties of NVE
7328  * and IPinIP.
7329  */
7330 #define MLXSW_REG_RTDP_ID 0x8020
7331 #define MLXSW_REG_RTDP_LEN 0x44
7332
7333 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
7334
7335 enum mlxsw_reg_rtdp_type {
7336         MLXSW_REG_RTDP_TYPE_NVE,
7337         MLXSW_REG_RTDP_TYPE_IPIP,
7338 };
7339
7340 /* reg_rtdp_type
7341  * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type.
7342  * Access: RW
7343  */
7344 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
7345
7346 /* reg_rtdp_tunnel_index
7347  * Index to the Decap entry.
7348  * For Spectrum, Index to KVD Linear.
7349  * Access: Index
7350  */
7351 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
7352
7353 /* reg_rtdp_egress_router_interface
7354  * Underlay egress router interface.
7355  * Valid range is from 0 to cap_max_router_interfaces - 1
7356  * Access: RW
7357  */
7358 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
7359
7360 /* IPinIP */
7361
7362 /* reg_rtdp_ipip_irif
7363  * Ingress Router Interface for the overlay router
7364  * Access: RW
7365  */
7366 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
7367
7368 enum mlxsw_reg_rtdp_ipip_sip_check {
7369         /* No sip checks. */
7370         MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
7371         /* Filter packet if underlay is not IPv4 or if underlay SIP does not
7372          * equal ipv4_usip.
7373          */
7374         MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
7375         /* Filter packet if underlay is not IPv6 or if underlay SIP does not
7376          * equal ipv6_usip.
7377          */
7378         MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
7379 };
7380
7381 /* reg_rtdp_ipip_sip_check
7382  * SIP check to perform. If decapsulation failed due to these configurations
7383  * then trap_id is IPIP_DECAP_ERROR.
7384  * Access: RW
7385  */
7386 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
7387
7388 /* If set, allow decapsulation of IPinIP (without GRE). */
7389 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP       BIT(0)
7390 /* If set, allow decapsulation of IPinGREinIP without a key. */
7391 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE        BIT(1)
7392 /* If set, allow decapsulation of IPinGREinIP with a key. */
7393 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY    BIT(2)
7394
7395 /* reg_rtdp_ipip_type_check
7396  * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to
7397  * these configurations then trap_id is IPIP_DECAP_ERROR.
7398  * Access: RW
7399  */
7400 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
7401
7402 /* reg_rtdp_ipip_gre_key_check
7403  * Whether GRE key should be checked. When check is enabled:
7404  * - A packet received as IPinIP (without GRE) will always pass.
7405  * - A packet received as IPinGREinIP without a key will not pass the check.
7406  * - A packet received as IPinGREinIP with a key will pass the check only if the
7407  *   key in the packet is equal to expected_gre_key.
7408  * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR.
7409  * Access: RW
7410  */
7411 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
7412
7413 /* reg_rtdp_ipip_ipv4_usip
7414  * Underlay IPv4 address for ipv4 source address check.
7415  * Reserved when sip_check is not '1'.
7416  * Access: RW
7417  */
7418 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
7419
7420 /* reg_rtdp_ipip_ipv6_usip_ptr
7421  * This field is valid when sip_check is "sipv6 check explicitly". This is a
7422  * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index
7423  * is to the KVD linear.
7424  * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6.
7425  * Access: RW
7426  */
7427 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
7428
7429 /* reg_rtdp_ipip_expected_gre_key
7430  * GRE key for checking.
7431  * Reserved when gre_key_check is '0'.
7432  * Access: RW
7433  */
7434 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
7435
7436 static inline void mlxsw_reg_rtdp_pack(char *payload,
7437                                        enum mlxsw_reg_rtdp_type type,
7438                                        u32 tunnel_index)
7439 {
7440         MLXSW_REG_ZERO(rtdp, payload);
7441         mlxsw_reg_rtdp_type_set(payload, type);
7442         mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
7443 }
7444
7445 static inline void
7446 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
7447                           enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
7448                           unsigned int type_check, bool gre_key_check,
7449                           u32 ipv4_usip, u32 expected_gre_key)
7450 {
7451         mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
7452         mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
7453         mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
7454         mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
7455         mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
7456         mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
7457 }
7458
7459 /* RIGR-V2 - Router Interface Group Register Version 2
7460  * ---------------------------------------------------
7461  * The RIGR_V2 register is used to add, remove and query egress interface list
7462  * of a multicast forwarding entry.
7463  */
7464 #define MLXSW_REG_RIGR2_ID 0x8023
7465 #define MLXSW_REG_RIGR2_LEN 0xB0
7466
7467 #define MLXSW_REG_RIGR2_MAX_ERIFS 32
7468
7469 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
7470
7471 /* reg_rigr2_rigr_index
7472  * KVD Linear index.
7473  * Access: Index
7474  */
7475 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
7476
7477 /* reg_rigr2_vnext
7478  * Next RIGR Index is valid.
7479  * Access: RW
7480  */
7481 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
7482
7483 /* reg_rigr2_next_rigr_index
7484  * Next RIGR Index. The index is to the KVD linear.
7485  * Reserved when vnxet = '0'.
7486  * Access: RW
7487  */
7488 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
7489
7490 /* reg_rigr2_vrmid
7491  * RMID Index is valid.
7492  * Access: RW
7493  */
7494 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
7495
7496 /* reg_rigr2_rmid_index
7497  * RMID Index.
7498  * Range 0 .. max_mid - 1
7499  * Reserved when vrmid = '0'.
7500  * The index is to the Port Group Table (PGT)
7501  * Access: RW
7502  */
7503 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
7504
7505 /* reg_rigr2_erif_entry_v
7506  * Egress Router Interface is valid.
7507  * Note that low-entries must be set if high-entries are set. For
7508  * example: if erif_entry[2].v is set then erif_entry[1].v and
7509  * erif_entry[0].v must be set.
7510  * Index can be from 0 to cap_mc_erif_list_entries-1
7511  * Access: RW
7512  */
7513 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
7514
7515 /* reg_rigr2_erif_entry_erif
7516  * Egress Router Interface.
7517  * Valid range is from 0 to cap_max_router_interfaces - 1
7518  * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1
7519  * Access: RW
7520  */
7521 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
7522
7523 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
7524                                         bool vnext, u32 next_rigr_index)
7525 {
7526         MLXSW_REG_ZERO(rigr2, payload);
7527         mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
7528         mlxsw_reg_rigr2_vnext_set(payload, vnext);
7529         mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
7530         mlxsw_reg_rigr2_vrmid_set(payload, 0);
7531         mlxsw_reg_rigr2_rmid_index_set(payload, 0);
7532 }
7533
7534 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
7535                                                    bool v, u16 erif)
7536 {
7537         mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
7538         mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
7539 }
7540
7541 /* RECR-V2 - Router ECMP Configuration Version 2 Register
7542  * ------------------------------------------------------
7543  */
7544 #define MLXSW_REG_RECR2_ID 0x8025
7545 #define MLXSW_REG_RECR2_LEN 0x38
7546
7547 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
7548
7549 /* reg_recr2_pp
7550  * Per-port configuration
7551  * Access: Index
7552  */
7553 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
7554
7555 /* reg_recr2_sh
7556  * Symmetric hash
7557  * Access: RW
7558  */
7559 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
7560
7561 /* reg_recr2_seed
7562  * Seed
7563  * Access: RW
7564  */
7565 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
7566
7567 enum {
7568         /* Enable IPv4 fields if packet is not TCP and not UDP */
7569         MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3,
7570         /* Enable IPv4 fields if packet is TCP or UDP */
7571         MLXSW_REG_RECR2_IPV4_EN_TCP_UDP         = 4,
7572         /* Enable IPv6 fields if packet is not TCP and not UDP */
7573         MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5,
7574         /* Enable IPv6 fields if packet is TCP or UDP */
7575         MLXSW_REG_RECR2_IPV6_EN_TCP_UDP         = 6,
7576         /* Enable TCP/UDP header fields if packet is IPv4 */
7577         MLXSW_REG_RECR2_TCP_UDP_EN_IPV4         = 7,
7578         /* Enable TCP/UDP header fields if packet is IPv6 */
7579         MLXSW_REG_RECR2_TCP_UDP_EN_IPV6         = 8,
7580 };
7581
7582 /* reg_recr2_outer_header_enables
7583  * Bit mask where each bit enables a specific layer to be included in
7584  * the hash calculation.
7585  * Access: RW
7586  */
7587 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
7588
7589 enum {
7590         /* IPv4 Source IP */
7591         MLXSW_REG_RECR2_IPV4_SIP0                       = 9,
7592         MLXSW_REG_RECR2_IPV4_SIP3                       = 12,
7593         /* IPv4 Destination IP */
7594         MLXSW_REG_RECR2_IPV4_DIP0                       = 13,
7595         MLXSW_REG_RECR2_IPV4_DIP3                       = 16,
7596         /* IP Protocol */
7597         MLXSW_REG_RECR2_IPV4_PROTOCOL                   = 17,
7598         /* IPv6 Source IP */
7599         MLXSW_REG_RECR2_IPV6_SIP0_7                     = 21,
7600         MLXSW_REG_RECR2_IPV6_SIP8                       = 29,
7601         MLXSW_REG_RECR2_IPV6_SIP15                      = 36,
7602         /* IPv6 Destination IP */
7603         MLXSW_REG_RECR2_IPV6_DIP0_7                     = 37,
7604         MLXSW_REG_RECR2_IPV6_DIP8                       = 45,
7605         MLXSW_REG_RECR2_IPV6_DIP15                      = 52,
7606         /* IPv6 Next Header */
7607         MLXSW_REG_RECR2_IPV6_NEXT_HEADER                = 53,
7608         /* IPv6 Flow Label */
7609         MLXSW_REG_RECR2_IPV6_FLOW_LABEL                 = 57,
7610         /* TCP/UDP Source Port */
7611         MLXSW_REG_RECR2_TCP_UDP_SPORT                   = 74,
7612         /* TCP/UDP Destination Port */
7613         MLXSW_REG_RECR2_TCP_UDP_DPORT                   = 75,
7614 };
7615
7616 /* reg_recr2_outer_header_fields_enable
7617  * Packet fields to enable for ECMP hash subject to outer_header_enable.
7618  * Access: RW
7619  */
7620 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
7621
7622 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload)
7623 {
7624         int i;
7625
7626         for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++)
7627                 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7628                                                                true);
7629 }
7630
7631 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload)
7632 {
7633         int i;
7634
7635         for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++)
7636                 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7637                                                                true);
7638 }
7639
7640 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload)
7641 {
7642         int i = MLXSW_REG_RECR2_IPV6_SIP0_7;
7643
7644         mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7645
7646         i = MLXSW_REG_RECR2_IPV6_SIP8;
7647         for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++)
7648                 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7649                                                                true);
7650 }
7651
7652 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload)
7653 {
7654         int i = MLXSW_REG_RECR2_IPV6_DIP0_7;
7655
7656         mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7657
7658         i = MLXSW_REG_RECR2_IPV6_DIP8;
7659         for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++)
7660                 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7661                                                                true);
7662 }
7663
7664 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
7665 {
7666         MLXSW_REG_ZERO(recr2, payload);
7667         mlxsw_reg_recr2_pp_set(payload, false);
7668         mlxsw_reg_recr2_sh_set(payload, true);
7669         mlxsw_reg_recr2_seed_set(payload, seed);
7670 }
7671
7672 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register
7673  * --------------------------------------------------------------
7674  * The RMFT_V2 register is used to configure and query the multicast table.
7675  */
7676 #define MLXSW_REG_RMFT2_ID 0x8027
7677 #define MLXSW_REG_RMFT2_LEN 0x174
7678
7679 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
7680
7681 /* reg_rmft2_v
7682  * Valid
7683  * Access: RW
7684  */
7685 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
7686
7687 enum mlxsw_reg_rmft2_type {
7688         MLXSW_REG_RMFT2_TYPE_IPV4,
7689         MLXSW_REG_RMFT2_TYPE_IPV6
7690 };
7691
7692 /* reg_rmft2_type
7693  * Access: Index
7694  */
7695 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
7696
7697 enum mlxsw_sp_reg_rmft2_op {
7698         /* For Write:
7699          * Write operation. Used to write a new entry to the table. All RW
7700          * fields are relevant for new entry. Activity bit is set for new
7701          * entries - Note write with v (Valid) 0 will delete the entry.
7702          * For Query:
7703          * Read operation
7704          */
7705         MLXSW_REG_RMFT2_OP_READ_WRITE,
7706 };
7707
7708 /* reg_rmft2_op
7709  * Operation.
7710  * Access: OP
7711  */
7712 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
7713
7714 /* reg_rmft2_a
7715  * Activity. Set for new entries. Set if a packet lookup has hit on the specific
7716  * entry.
7717  * Access: RO
7718  */
7719 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
7720
7721 /* reg_rmft2_offset
7722  * Offset within the multicast forwarding table to write to.
7723  * Access: Index
7724  */
7725 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
7726
7727 /* reg_rmft2_virtual_router
7728  * Virtual Router ID. Range from 0..cap_max_virtual_routers-1
7729  * Access: RW
7730  */
7731 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
7732
7733 enum mlxsw_reg_rmft2_irif_mask {
7734         MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
7735         MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
7736 };
7737
7738 /* reg_rmft2_irif_mask
7739  * Ingress RIF mask.
7740  * Access: RW
7741  */
7742 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
7743
7744 /* reg_rmft2_irif
7745  * Ingress RIF index.
7746  * Access: RW
7747  */
7748 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
7749
7750 /* reg_rmft2_dip{4,6}
7751  * Destination IPv4/6 address
7752  * Access: RW
7753  */
7754 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
7755 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
7756
7757 /* reg_rmft2_dip{4,6}_mask
7758  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7759  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7760  * Access: RW
7761  */
7762 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
7763 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
7764
7765 /* reg_rmft2_sip{4,6}
7766  * Source IPv4/6 address
7767  * Access: RW
7768  */
7769 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
7770 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
7771
7772 /* reg_rmft2_sip{4,6}_mask
7773  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7774  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7775  * Access: RW
7776  */
7777 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
7778 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
7779
7780 /* reg_rmft2_flexible_action_set
7781  * ACL action set. The only supported action types in this field and in any
7782  * action-set pointed from here are as follows:
7783  * 00h: ACTION_NULL
7784  * 01h: ACTION_MAC_TTL, only TTL configuration is supported.
7785  * 03h: ACTION_TRAP
7786  * 06h: ACTION_QOS
7787  * 08h: ACTION_POLICING_MONITORING
7788  * 10h: ACTION_ROUTER_MC
7789  * Access: RW
7790  */
7791 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
7792                MLXSW_REG_FLEX_ACTION_SET_LEN);
7793
7794 static inline void
7795 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
7796                             u16 virtual_router,
7797                             enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7798                             const char *flex_action_set)
7799 {
7800         MLXSW_REG_ZERO(rmft2, payload);
7801         mlxsw_reg_rmft2_v_set(payload, v);
7802         mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
7803         mlxsw_reg_rmft2_offset_set(payload, offset);
7804         mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
7805         mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
7806         mlxsw_reg_rmft2_irif_set(payload, irif);
7807         if (flex_action_set)
7808                 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
7809                                                               flex_action_set);
7810 }
7811
7812 static inline void
7813 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7814                           enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7815                           u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
7816                           const char *flexible_action_set)
7817 {
7818         mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7819                                     irif_mask, irif, flexible_action_set);
7820         mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
7821         mlxsw_reg_rmft2_dip4_set(payload, dip4);
7822         mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
7823         mlxsw_reg_rmft2_sip4_set(payload, sip4);
7824         mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
7825 }
7826
7827 static inline void
7828 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7829                           enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7830                           struct in6_addr dip6, struct in6_addr dip6_mask,
7831                           struct in6_addr sip6, struct in6_addr sip6_mask,
7832                           const char *flexible_action_set)
7833 {
7834         mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7835                                     irif_mask, irif, flexible_action_set);
7836         mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
7837         mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
7838         mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
7839         mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
7840         mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
7841 }
7842
7843 /* MFCR - Management Fan Control Register
7844  * --------------------------------------
7845  * This register controls the settings of the Fan Speed PWM mechanism.
7846  */
7847 #define MLXSW_REG_MFCR_ID 0x9001
7848 #define MLXSW_REG_MFCR_LEN 0x08
7849
7850 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
7851
7852 enum mlxsw_reg_mfcr_pwm_frequency {
7853         MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
7854         MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
7855         MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
7856         MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
7857         MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
7858         MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
7859         MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
7860         MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
7861 };
7862
7863 /* reg_mfcr_pwm_frequency
7864  * Controls the frequency of the PWM signal.
7865  * Access: RW
7866  */
7867 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
7868
7869 #define MLXSW_MFCR_TACHOS_MAX 10
7870
7871 /* reg_mfcr_tacho_active
7872  * Indicates which of the tachometer is active (bit per tachometer).
7873  * Access: RO
7874  */
7875 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
7876
7877 #define MLXSW_MFCR_PWMS_MAX 5
7878
7879 /* reg_mfcr_pwm_active
7880  * Indicates which of the PWM control is active (bit per PWM).
7881  * Access: RO
7882  */
7883 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
7884
7885 static inline void
7886 mlxsw_reg_mfcr_pack(char *payload,
7887                     enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
7888 {
7889         MLXSW_REG_ZERO(mfcr, payload);
7890         mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
7891 }
7892
7893 static inline void
7894 mlxsw_reg_mfcr_unpack(char *payload,
7895                       enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
7896                       u16 *p_tacho_active, u8 *p_pwm_active)
7897 {
7898         *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
7899         *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
7900         *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
7901 }
7902
7903 /* MFSC - Management Fan Speed Control Register
7904  * --------------------------------------------
7905  * This register controls the settings of the Fan Speed PWM mechanism.
7906  */
7907 #define MLXSW_REG_MFSC_ID 0x9002
7908 #define MLXSW_REG_MFSC_LEN 0x08
7909
7910 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
7911
7912 /* reg_mfsc_pwm
7913  * Fan pwm to control / monitor.
7914  * Access: Index
7915  */
7916 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
7917
7918 /* reg_mfsc_pwm_duty_cycle
7919  * Controls the duty cycle of the PWM. Value range from 0..255 to
7920  * represent duty cycle of 0%...100%.
7921  * Access: RW
7922  */
7923 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
7924
7925 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
7926                                        u8 pwm_duty_cycle)
7927 {
7928         MLXSW_REG_ZERO(mfsc, payload);
7929         mlxsw_reg_mfsc_pwm_set(payload, pwm);
7930         mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
7931 }
7932
7933 /* MFSM - Management Fan Speed Measurement
7934  * ---------------------------------------
7935  * This register controls the settings of the Tacho measurements and
7936  * enables reading the Tachometer measurements.
7937  */
7938 #define MLXSW_REG_MFSM_ID 0x9003
7939 #define MLXSW_REG_MFSM_LEN 0x08
7940
7941 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
7942
7943 /* reg_mfsm_tacho
7944  * Fan tachometer index.
7945  * Access: Index
7946  */
7947 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
7948
7949 /* reg_mfsm_rpm
7950  * Fan speed (round per minute).
7951  * Access: RO
7952  */
7953 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
7954
7955 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
7956 {
7957         MLXSW_REG_ZERO(mfsm, payload);
7958         mlxsw_reg_mfsm_tacho_set(payload, tacho);
7959 }
7960
7961 /* MFSL - Management Fan Speed Limit Register
7962  * ------------------------------------------
7963  * The Fan Speed Limit register is used to configure the fan speed
7964  * event / interrupt notification mechanism. Fan speed threshold are
7965  * defined for both under-speed and over-speed.
7966  */
7967 #define MLXSW_REG_MFSL_ID 0x9004
7968 #define MLXSW_REG_MFSL_LEN 0x0C
7969
7970 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
7971
7972 /* reg_mfsl_tacho
7973  * Fan tachometer index.
7974  * Access: Index
7975  */
7976 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
7977
7978 /* reg_mfsl_tach_min
7979  * Tachometer minimum value (minimum RPM).
7980  * Access: RW
7981  */
7982 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
7983
7984 /* reg_mfsl_tach_max
7985  * Tachometer maximum value (maximum RPM).
7986  * Access: RW
7987  */
7988 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
7989
7990 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
7991                                        u16 tach_min, u16 tach_max)
7992 {
7993         MLXSW_REG_ZERO(mfsl, payload);
7994         mlxsw_reg_mfsl_tacho_set(payload, tacho);
7995         mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
7996         mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
7997 }
7998
7999 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
8000                                          u16 *p_tach_min, u16 *p_tach_max)
8001 {
8002         if (p_tach_min)
8003                 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
8004
8005         if (p_tach_max)
8006                 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
8007 }
8008
8009 /* FORE - Fan Out of Range Event Register
8010  * --------------------------------------
8011  * This register reports the status of the controlled fans compared to the
8012  * range defined by the MFSL register.
8013  */
8014 #define MLXSW_REG_FORE_ID 0x9007
8015 #define MLXSW_REG_FORE_LEN 0x0C
8016
8017 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);
8018
8019 /* fan_under_limit
8020  * Fan speed is below the low limit defined in MFSL register. Each bit relates
8021  * to a single tachometer and indicates the specific tachometer reading is
8022  * below the threshold.
8023  * Access: RO
8024  */
8025 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
8026
8027 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,
8028                                          bool *fault)
8029 {
8030         u16 limit;
8031
8032         if (fault) {
8033                 limit = mlxsw_reg_fore_fan_under_limit_get(payload);
8034                 *fault = limit & BIT(tacho);
8035         }
8036 }
8037
8038 /* MTCAP - Management Temperature Capabilities
8039  * -------------------------------------------
8040  * This register exposes the capabilities of the device and
8041  * system temperature sensing.
8042  */
8043 #define MLXSW_REG_MTCAP_ID 0x9009
8044 #define MLXSW_REG_MTCAP_LEN 0x08
8045
8046 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
8047
8048 /* reg_mtcap_sensor_count
8049  * Number of sensors supported by the device.
8050  * This includes the QSFP module sensors (if exists in the QSFP module).
8051  * Access: RO
8052  */
8053 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
8054
8055 /* MTMP - Management Temperature
8056  * -----------------------------
8057  * This register controls the settings of the temperature measurements
8058  * and enables reading the temperature measurements. Note that temperature
8059  * is in 0.125 degrees Celsius.
8060  */
8061 #define MLXSW_REG_MTMP_ID 0x900A
8062 #define MLXSW_REG_MTMP_LEN 0x20
8063
8064 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
8065
8066 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64
8067 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256
8068 /* reg_mtmp_sensor_index
8069  * Sensors index to access.
8070  * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
8071  * (module 0 is mapped to sensor_index 64).
8072  * Access: Index
8073  */
8074 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
8075
8076 /* Convert to milli degrees Celsius */
8077 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \
8078                                           ((v_) >= 0) ? ((v_) * 125) : \
8079                                           ((s16)((GENMASK(15, 0) + (v_) + 1) \
8080                                            * 125)); })
8081
8082 /* reg_mtmp_temperature
8083  * Temperature reading from the sensor. Reading is in 0.125 Celsius
8084  * degrees units.
8085  * Access: RO
8086  */
8087 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
8088
8089 /* reg_mtmp_mte
8090  * Max Temperature Enable - enables measuring the max temperature on a sensor.
8091  * Access: RW
8092  */
8093 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
8094
8095 /* reg_mtmp_mtr
8096  * Max Temperature Reset - clears the value of the max temperature register.
8097  * Access: WO
8098  */
8099 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
8100
8101 /* reg_mtmp_max_temperature
8102  * The highest measured temperature from the sensor.
8103  * When the bit mte is cleared, the field max_temperature is reserved.
8104  * Access: RO
8105  */
8106 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
8107
8108 /* reg_mtmp_tee
8109  * Temperature Event Enable.
8110  * 0 - Do not generate event
8111  * 1 - Generate event
8112  * 2 - Generate single event
8113  * Access: RW
8114  */
8115 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
8116
8117 #define MLXSW_REG_MTMP_THRESH_HI 0x348  /* 105 Celsius */
8118
8119 /* reg_mtmp_temperature_threshold_hi
8120  * High threshold for Temperature Warning Event. In 0.125 Celsius.
8121  * Access: RW
8122  */
8123 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
8124
8125 /* reg_mtmp_temperature_threshold_lo
8126  * Low threshold for Temperature Warning Event. In 0.125 Celsius.
8127  * Access: RW
8128  */
8129 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
8130
8131 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
8132
8133 /* reg_mtmp_sensor_name
8134  * Sensor Name
8135  * Access: RO
8136  */
8137 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
8138
8139 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index,
8140                                        bool max_temp_enable,
8141                                        bool max_temp_reset)
8142 {
8143         MLXSW_REG_ZERO(mtmp, payload);
8144         mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
8145         mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
8146         mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
8147         mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
8148                                                     MLXSW_REG_MTMP_THRESH_HI);
8149 }
8150
8151 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp,
8152                                          int *p_max_temp, char *sensor_name)
8153 {
8154         s16 temp;
8155
8156         if (p_temp) {
8157                 temp = mlxsw_reg_mtmp_temperature_get(payload);
8158                 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8159         }
8160         if (p_max_temp) {
8161                 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
8162                 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8163         }
8164         if (sensor_name)
8165                 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
8166 }
8167
8168 /* MTBR - Management Temperature Bulk Register
8169  * -------------------------------------------
8170  * This register is used for bulk temperature reading.
8171  */
8172 #define MLXSW_REG_MTBR_ID 0x900F
8173 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */
8174 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */
8175 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */
8176 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN +   \
8177                             MLXSW_REG_MTBR_REC_LEN *    \
8178                             MLXSW_REG_MTBR_REC_MAX_COUNT)
8179
8180 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);
8181
8182 /* reg_mtbr_base_sensor_index
8183  * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors,
8184  * 64-127 are mapped to the SFP+/QSFP modules sequentially).
8185  * Access: Index
8186  */
8187 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
8188
8189 /* reg_mtbr_num_rec
8190  * Request: Number of records to read
8191  * Response: Number of records read
8192  * See above description for more details.
8193  * Range 1..255
8194  * Access: RW
8195  */
8196 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
8197
8198 /* reg_mtbr_rec_max_temp
8199  * The highest measured temperature from the sensor.
8200  * When the bit mte is cleared, the field max_temperature is reserved.
8201  * Access: RO
8202  */
8203 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
8204                      16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8205
8206 /* reg_mtbr_rec_temp
8207  * Temperature reading from the sensor. Reading is in 0..125 Celsius
8208  * degrees units.
8209  * Access: RO
8210  */
8211 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
8212                      MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8213
8214 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index,
8215                                        u8 num_rec)
8216 {
8217         MLXSW_REG_ZERO(mtbr, payload);
8218         mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);
8219         mlxsw_reg_mtbr_num_rec_set(payload, num_rec);
8220 }
8221
8222 /* Error codes from temperatute reading */
8223 enum mlxsw_reg_mtbr_temp_status {
8224         MLXSW_REG_MTBR_NO_CONN          = 0x8000,
8225         MLXSW_REG_MTBR_NO_TEMP_SENS     = 0x8001,
8226         MLXSW_REG_MTBR_INDEX_NA         = 0x8002,
8227         MLXSW_REG_MTBR_BAD_SENS_INFO    = 0x8003,
8228 };
8229
8230 /* Base index for reading modules temperature */
8231 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64
8232
8233 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,
8234                                               u16 *p_temp, u16 *p_max_temp)
8235 {
8236         if (p_temp)
8237                 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);
8238         if (p_max_temp)
8239                 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);
8240 }
8241
8242 /* MCIA - Management Cable Info Access
8243  * -----------------------------------
8244  * MCIA register is used to access the SFP+ and QSFP connector's EPROM.
8245  */
8246
8247 #define MLXSW_REG_MCIA_ID 0x9014
8248 #define MLXSW_REG_MCIA_LEN 0x40
8249
8250 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
8251
8252 /* reg_mcia_l
8253  * Lock bit. Setting this bit will lock the access to the specific
8254  * cable. Used for updating a full page in a cable EPROM. Any access
8255  * other then subsequence writes will fail while the port is locked.
8256  * Access: RW
8257  */
8258 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
8259
8260 /* reg_mcia_module
8261  * Module number.
8262  * Access: Index
8263  */
8264 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
8265
8266 /* reg_mcia_status
8267  * Module status.
8268  * Access: RO
8269  */
8270 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
8271
8272 /* reg_mcia_i2c_device_address
8273  * I2C device address.
8274  * Access: RW
8275  */
8276 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
8277
8278 /* reg_mcia_page_number
8279  * Page number.
8280  * Access: RW
8281  */
8282 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
8283
8284 /* reg_mcia_device_address
8285  * Device address.
8286  * Access: RW
8287  */
8288 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
8289
8290 /* reg_mcia_size
8291  * Number of bytes to read/write (up to 48 bytes).
8292  * Access: RW
8293  */
8294 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
8295
8296 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH       256
8297 #define MLXSW_REG_MCIA_EEPROM_SIZE              48
8298 #define MLXSW_REG_MCIA_I2C_ADDR_LOW             0x50
8299 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH            0x51
8300 #define MLXSW_REG_MCIA_PAGE0_LO_OFF             0xa0
8301 #define MLXSW_REG_MCIA_TH_ITEM_SIZE             2
8302 #define MLXSW_REG_MCIA_TH_PAGE_NUM              3
8303 #define MLXSW_REG_MCIA_PAGE0_LO                 0
8304 #define MLXSW_REG_MCIA_TH_PAGE_OFF              0x80
8305
8306 enum mlxsw_reg_mcia_eeprom_module_info_rev_id {
8307         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC  = 0x00,
8308         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436   = 0x01,
8309         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636   = 0x03,
8310 };
8311
8312 enum mlxsw_reg_mcia_eeprom_module_info_id {
8313         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP        = 0x03,
8314         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP       = 0x0C,
8315         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS  = 0x0D,
8316         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28     = 0x11,
8317         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD    = 0x18,
8318 };
8319
8320 enum mlxsw_reg_mcia_eeprom_module_info {
8321         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,
8322         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,
8323         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,
8324 };
8325
8326 /* reg_mcia_eeprom
8327  * Bytes to read/write.
8328  * Access: RW
8329  */
8330 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE);
8331
8332 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
8333                                        u8 page_number, u16 device_addr,
8334                                        u8 size, u8 i2c_device_addr)
8335 {
8336         MLXSW_REG_ZERO(mcia, payload);
8337         mlxsw_reg_mcia_module_set(payload, module);
8338         mlxsw_reg_mcia_l_set(payload, lock);
8339         mlxsw_reg_mcia_page_number_set(payload, page_number);
8340         mlxsw_reg_mcia_device_address_set(payload, device_addr);
8341         mlxsw_reg_mcia_size_set(payload, size);
8342         mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
8343 }
8344
8345 /* MPAT - Monitoring Port Analyzer Table
8346  * -------------------------------------
8347  * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
8348  * For an enabled analyzer, all fields except e (enable) cannot be modified.
8349  */
8350 #define MLXSW_REG_MPAT_ID 0x901A
8351 #define MLXSW_REG_MPAT_LEN 0x78
8352
8353 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
8354
8355 /* reg_mpat_pa_id
8356  * Port Analyzer ID.
8357  * Access: Index
8358  */
8359 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
8360
8361 /* reg_mpat_system_port
8362  * A unique port identifier for the final destination of the packet.
8363  * Access: RW
8364  */
8365 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
8366
8367 /* reg_mpat_e
8368  * Enable. Indicating the Port Analyzer is enabled.
8369  * Access: RW
8370  */
8371 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
8372
8373 /* reg_mpat_qos
8374  * Quality Of Service Mode.
8375  * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
8376  * PCP, DEI, DSCP or VL) are configured.
8377  * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
8378  * same as in the original packet that has triggered the mirroring. For
8379  * SPAN also the pcp,dei are maintained.
8380  * Access: RW
8381  */
8382 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
8383
8384 /* reg_mpat_be
8385  * Best effort mode. Indicates mirroring traffic should not cause packet
8386  * drop or back pressure, but will discard the mirrored packets. Mirrored
8387  * packets will be forwarded on a best effort manner.
8388  * 0: Do not discard mirrored packets
8389  * 1: Discard mirrored packets if causing congestion
8390  * Access: RW
8391  */
8392 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
8393
8394 enum mlxsw_reg_mpat_span_type {
8395         /* Local SPAN Ethernet.
8396          * The original packet is not encapsulated.
8397          */
8398         MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
8399
8400         /* Remote SPAN Ethernet VLAN.
8401          * The packet is forwarded to the monitoring port on the monitoring
8402          * VLAN.
8403          */
8404         MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
8405
8406         /* Encapsulated Remote SPAN Ethernet L3 GRE.
8407          * The packet is encapsulated with GRE header.
8408          */
8409         MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
8410 };
8411
8412 /* reg_mpat_span_type
8413  * SPAN type.
8414  * Access: RW
8415  */
8416 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
8417
8418 /* Remote SPAN - Ethernet VLAN
8419  * - - - - - - - - - - - - - -
8420  */
8421
8422 /* reg_mpat_eth_rspan_vid
8423  * Encapsulation header VLAN ID.
8424  * Access: RW
8425  */
8426 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
8427
8428 /* Encapsulated Remote SPAN - Ethernet L2
8429  * - - - - - - - - - - - - - - - - - - -
8430  */
8431
8432 enum mlxsw_reg_mpat_eth_rspan_version {
8433         MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
8434 };
8435
8436 /* reg_mpat_eth_rspan_version
8437  * RSPAN mirror header version.
8438  * Access: RW
8439  */
8440 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
8441
8442 /* reg_mpat_eth_rspan_mac
8443  * Destination MAC address.
8444  * Access: RW
8445  */
8446 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
8447
8448 /* reg_mpat_eth_rspan_tp
8449  * Tag Packet. Indicates whether the mirroring header should be VLAN tagged.
8450  * Access: RW
8451  */
8452 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
8453
8454 /* Encapsulated Remote SPAN - Ethernet L3
8455  * - - - - - - - - - - - - - - - - - - -
8456  */
8457
8458 enum mlxsw_reg_mpat_eth_rspan_protocol {
8459         MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
8460         MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
8461 };
8462
8463 /* reg_mpat_eth_rspan_protocol
8464  * SPAN encapsulation protocol.
8465  * Access: RW
8466  */
8467 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
8468
8469 /* reg_mpat_eth_rspan_ttl
8470  * Encapsulation header Time-to-Live/HopLimit.
8471  * Access: RW
8472  */
8473 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
8474
8475 /* reg_mpat_eth_rspan_smac
8476  * Source MAC address
8477  * Access: RW
8478  */
8479 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
8480
8481 /* reg_mpat_eth_rspan_dip*
8482  * Destination IP address. The IP version is configured by protocol.
8483  * Access: RW
8484  */
8485 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
8486 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
8487
8488 /* reg_mpat_eth_rspan_sip*
8489  * Source IP address. The IP version is configured by protocol.
8490  * Access: RW
8491  */
8492 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
8493 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
8494
8495 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
8496                                        u16 system_port, bool e,
8497                                        enum mlxsw_reg_mpat_span_type span_type)
8498 {
8499         MLXSW_REG_ZERO(mpat, payload);
8500         mlxsw_reg_mpat_pa_id_set(payload, pa_id);
8501         mlxsw_reg_mpat_system_port_set(payload, system_port);
8502         mlxsw_reg_mpat_e_set(payload, e);
8503         mlxsw_reg_mpat_qos_set(payload, 1);
8504         mlxsw_reg_mpat_be_set(payload, 1);
8505         mlxsw_reg_mpat_span_type_set(payload, span_type);
8506 }
8507
8508 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
8509 {
8510         mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
8511 }
8512
8513 static inline void
8514 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
8515                                  enum mlxsw_reg_mpat_eth_rspan_version version,
8516                                  const char *mac,
8517                                  bool tp)
8518 {
8519         mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
8520         mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
8521         mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
8522 }
8523
8524 static inline void
8525 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
8526                                       const char *smac,
8527                                       u32 sip, u32 dip)
8528 {
8529         mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8530         mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8531         mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8532                                     MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
8533         mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
8534         mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
8535 }
8536
8537 static inline void
8538 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
8539                                       const char *smac,
8540                                       struct in6_addr sip, struct in6_addr dip)
8541 {
8542         mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8543         mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8544         mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8545                                     MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
8546         mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
8547         mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
8548 }
8549
8550 /* MPAR - Monitoring Port Analyzer Register
8551  * ----------------------------------------
8552  * MPAR register is used to query and configure the port analyzer port mirroring
8553  * properties.
8554  */
8555 #define MLXSW_REG_MPAR_ID 0x901B
8556 #define MLXSW_REG_MPAR_LEN 0x08
8557
8558 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
8559
8560 /* reg_mpar_local_port
8561  * The local port to mirror the packets from.
8562  * Access: Index
8563  */
8564 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
8565
8566 enum mlxsw_reg_mpar_i_e {
8567         MLXSW_REG_MPAR_TYPE_EGRESS,
8568         MLXSW_REG_MPAR_TYPE_INGRESS,
8569 };
8570
8571 /* reg_mpar_i_e
8572  * Ingress/Egress
8573  * Access: Index
8574  */
8575 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
8576
8577 /* reg_mpar_enable
8578  * Enable mirroring
8579  * By default, port mirroring is disabled for all ports.
8580  * Access: RW
8581  */
8582 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
8583
8584 /* reg_mpar_pa_id
8585  * Port Analyzer ID.
8586  * Access: RW
8587  */
8588 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
8589
8590 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
8591                                        enum mlxsw_reg_mpar_i_e i_e,
8592                                        bool enable, u8 pa_id)
8593 {
8594         MLXSW_REG_ZERO(mpar, payload);
8595         mlxsw_reg_mpar_local_port_set(payload, local_port);
8596         mlxsw_reg_mpar_enable_set(payload, enable);
8597         mlxsw_reg_mpar_i_e_set(payload, i_e);
8598         mlxsw_reg_mpar_pa_id_set(payload, pa_id);
8599 }
8600
8601 /* MGIR - Management General Information Register
8602  * ----------------------------------------------
8603  * MGIR register allows software to query the hardware and firmware general
8604  * information.
8605  */
8606 #define MLXSW_REG_MGIR_ID 0x9020
8607 #define MLXSW_REG_MGIR_LEN 0x9C
8608
8609 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);
8610
8611 /* reg_mgir_hw_info_device_hw_revision
8612  * Access: RO
8613  */
8614 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
8615
8616 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16
8617
8618 /* reg_mgir_fw_info_psid
8619  * PSID (ASCII string).
8620  * Access: RO
8621  */
8622 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
8623
8624 /* reg_mgir_fw_info_extended_major
8625  * Access: RO
8626  */
8627 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
8628
8629 /* reg_mgir_fw_info_extended_minor
8630  * Access: RO
8631  */
8632 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
8633
8634 /* reg_mgir_fw_info_extended_sub_minor
8635  * Access: RO
8636  */
8637 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
8638
8639 static inline void mlxsw_reg_mgir_pack(char *payload)
8640 {
8641         MLXSW_REG_ZERO(mgir, payload);
8642 }
8643
8644 static inline void
8645 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,
8646                       u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor)
8647 {
8648         *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);
8649         mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);
8650         *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);
8651         *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);
8652         *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);
8653 }
8654
8655 /* MRSR - Management Reset and Shutdown Register
8656  * ---------------------------------------------
8657  * MRSR register is used to reset or shutdown the switch or
8658  * the entire system (when applicable).
8659  */
8660 #define MLXSW_REG_MRSR_ID 0x9023
8661 #define MLXSW_REG_MRSR_LEN 0x08
8662
8663 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
8664
8665 /* reg_mrsr_command
8666  * Reset/shutdown command
8667  * 0 - do nothing
8668  * 1 - software reset
8669  * Access: WO
8670  */
8671 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
8672
8673 static inline void mlxsw_reg_mrsr_pack(char *payload)
8674 {
8675         MLXSW_REG_ZERO(mrsr, payload);
8676         mlxsw_reg_mrsr_command_set(payload, 1);
8677 }
8678
8679 /* MLCR - Management LED Control Register
8680  * --------------------------------------
8681  * Controls the system LEDs.
8682  */
8683 #define MLXSW_REG_MLCR_ID 0x902B
8684 #define MLXSW_REG_MLCR_LEN 0x0C
8685
8686 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
8687
8688 /* reg_mlcr_local_port
8689  * Local port number.
8690  * Access: RW
8691  */
8692 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
8693
8694 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
8695
8696 /* reg_mlcr_beacon_duration
8697  * Duration of the beacon to be active, in seconds.
8698  * 0x0 - Will turn off the beacon.
8699  * 0xFFFF - Will turn on the beacon until explicitly turned off.
8700  * Access: RW
8701  */
8702 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
8703
8704 /* reg_mlcr_beacon_remain
8705  * Remaining duration of the beacon, in seconds.
8706  * 0xFFFF indicates an infinite amount of time.
8707  * Access: RO
8708  */
8709 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
8710
8711 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
8712                                        bool active)
8713 {
8714         MLXSW_REG_ZERO(mlcr, payload);
8715         mlxsw_reg_mlcr_local_port_set(payload, local_port);
8716         mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
8717                                            MLXSW_REG_MLCR_DURATION_MAX : 0);
8718 }
8719
8720 /* MTPPS - Management Pulse Per Second Register
8721  * --------------------------------------------
8722  * This register provides the device PPS capabilities, configure the PPS in and
8723  * out modules and holds the PPS in time stamp.
8724  */
8725 #define MLXSW_REG_MTPPS_ID 0x9053
8726 #define MLXSW_REG_MTPPS_LEN 0x3C
8727
8728 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
8729
8730 /* reg_mtpps_enable
8731  * Enables the PPS functionality the specific pin.
8732  * A boolean variable.
8733  * Access: RW
8734  */
8735 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
8736
8737 enum mlxsw_reg_mtpps_pin_mode {
8738         MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
8739 };
8740
8741 /* reg_mtpps_pin_mode
8742  * Pin mode to be used. The mode must comply with the supported modes of the
8743  * requested pin.
8744  * Access: RW
8745  */
8746 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
8747
8748 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN      7
8749
8750 /* reg_mtpps_pin
8751  * Pin to be configured or queried out of the supported pins.
8752  * Access: Index
8753  */
8754 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
8755
8756 /* reg_mtpps_time_stamp
8757  * When pin_mode = pps_in, the latched device time when it was triggered from
8758  * the external GPIO pin.
8759  * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target
8760  * time to generate next output signal.
8761  * Time is in units of device clock.
8762  * Access: RW
8763  */
8764 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
8765
8766 static inline void
8767 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
8768 {
8769         MLXSW_REG_ZERO(mtpps, payload);
8770         mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
8771         mlxsw_reg_mtpps_pin_mode_set(payload,
8772                                      MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
8773         mlxsw_reg_mtpps_enable_set(payload, true);
8774         mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
8775 }
8776
8777 /* MTUTC - Management UTC Register
8778  * -------------------------------
8779  * Configures the HW UTC counter.
8780  */
8781 #define MLXSW_REG_MTUTC_ID 0x9055
8782 #define MLXSW_REG_MTUTC_LEN 0x1C
8783
8784 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);
8785
8786 enum mlxsw_reg_mtutc_operation {
8787         MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
8788         MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
8789 };
8790
8791 /* reg_mtutc_operation
8792  * Operation.
8793  * Access: OP
8794  */
8795 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
8796
8797 /* reg_mtutc_freq_adjustment
8798  * Frequency adjustment: Every PPS the HW frequency will be
8799  * adjusted by this value. Units of HW clock, where HW counts
8800  * 10^9 HW clocks for 1 HW second.
8801  * Access: RW
8802  */
8803 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
8804
8805 /* reg_mtutc_utc_sec
8806  * UTC seconds.
8807  * Access: WO
8808  */
8809 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
8810
8811 static inline void
8812 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
8813                      u32 freq_adj, u32 utc_sec)
8814 {
8815         MLXSW_REG_ZERO(mtutc, payload);
8816         mlxsw_reg_mtutc_operation_set(payload, oper);
8817         mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
8818         mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
8819 }
8820
8821 /* MCQI - Management Component Query Information
8822  * ---------------------------------------------
8823  * This register allows querying information about firmware components.
8824  */
8825 #define MLXSW_REG_MCQI_ID 0x9061
8826 #define MLXSW_REG_MCQI_BASE_LEN 0x18
8827 #define MLXSW_REG_MCQI_CAP_LEN 0x14
8828 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
8829
8830 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
8831
8832 /* reg_mcqi_component_index
8833  * Index of the accessed component.
8834  * Access: Index
8835  */
8836 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
8837
8838 enum mlxfw_reg_mcqi_info_type {
8839         MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
8840 };
8841
8842 /* reg_mcqi_info_type
8843  * Component properties set.
8844  * Access: RW
8845  */
8846 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
8847
8848 /* reg_mcqi_offset
8849  * The requested/returned data offset from the section start, given in bytes.
8850  * Must be DWORD aligned.
8851  * Access: RW
8852  */
8853 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
8854
8855 /* reg_mcqi_data_size
8856  * The requested/returned data size, given in bytes. If data_size is not DWORD
8857  * aligned, the last bytes are zero padded.
8858  * Access: RW
8859  */
8860 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
8861
8862 /* reg_mcqi_cap_max_component_size
8863  * Maximum size for this component, given in bytes.
8864  * Access: RO
8865  */
8866 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
8867
8868 /* reg_mcqi_cap_log_mcda_word_size
8869  * Log 2 of the access word size in bytes. Read and write access must be aligned
8870  * to the word size. Write access must be done for an integer number of words.
8871  * Access: RO
8872  */
8873 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
8874
8875 /* reg_mcqi_cap_mcda_max_write_size
8876  * Maximal write size for MCDA register
8877  * Access: RO
8878  */
8879 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
8880
8881 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
8882 {
8883         MLXSW_REG_ZERO(mcqi, payload);
8884         mlxsw_reg_mcqi_component_index_set(payload, component_index);
8885         mlxsw_reg_mcqi_info_type_set(payload,
8886                                      MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
8887         mlxsw_reg_mcqi_offset_set(payload, 0);
8888         mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
8889 }
8890
8891 static inline void mlxsw_reg_mcqi_unpack(char *payload,
8892                                          u32 *p_cap_max_component_size,
8893                                          u8 *p_cap_log_mcda_word_size,
8894                                          u16 *p_cap_mcda_max_write_size)
8895 {
8896         *p_cap_max_component_size =
8897                 mlxsw_reg_mcqi_cap_max_component_size_get(payload);
8898         *p_cap_log_mcda_word_size =
8899                 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
8900         *p_cap_mcda_max_write_size =
8901                 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
8902 }
8903
8904 /* MCC - Management Component Control
8905  * ----------------------------------
8906  * Controls the firmware component and updates the FSM.
8907  */
8908 #define MLXSW_REG_MCC_ID 0x9062
8909 #define MLXSW_REG_MCC_LEN 0x1C
8910
8911 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
8912
8913 enum mlxsw_reg_mcc_instruction {
8914         MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
8915         MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
8916         MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
8917         MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
8918         MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
8919         MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
8920 };
8921
8922 /* reg_mcc_instruction
8923  * Command to be executed by the FSM.
8924  * Applicable for write operation only.
8925  * Access: RW
8926  */
8927 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
8928
8929 /* reg_mcc_component_index
8930  * Index of the accessed component. Applicable only for commands that
8931  * refer to components. Otherwise, this field is reserved.
8932  * Access: Index
8933  */
8934 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
8935
8936 /* reg_mcc_update_handle
8937  * Token representing the current flow executed by the FSM.
8938  * Access: WO
8939  */
8940 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
8941
8942 /* reg_mcc_error_code
8943  * Indicates the successful completion of the instruction, or the reason it
8944  * failed
8945  * Access: RO
8946  */
8947 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
8948
8949 /* reg_mcc_control_state
8950  * Current FSM state
8951  * Access: RO
8952  */
8953 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
8954
8955 /* reg_mcc_component_size
8956  * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying
8957  * the size may shorten the update time. Value 0x0 means that size is
8958  * unspecified.
8959  * Access: WO
8960  */
8961 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
8962
8963 static inline void mlxsw_reg_mcc_pack(char *payload,
8964                                       enum mlxsw_reg_mcc_instruction instr,
8965                                       u16 component_index, u32 update_handle,
8966                                       u32 component_size)
8967 {
8968         MLXSW_REG_ZERO(mcc, payload);
8969         mlxsw_reg_mcc_instruction_set(payload, instr);
8970         mlxsw_reg_mcc_component_index_set(payload, component_index);
8971         mlxsw_reg_mcc_update_handle_set(payload, update_handle);
8972         mlxsw_reg_mcc_component_size_set(payload, component_size);
8973 }
8974
8975 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
8976                                         u8 *p_error_code, u8 *p_control_state)
8977 {
8978         if (p_update_handle)
8979                 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
8980         if (p_error_code)
8981                 *p_error_code = mlxsw_reg_mcc_error_code_get(payload);
8982         if (p_control_state)
8983                 *p_control_state = mlxsw_reg_mcc_control_state_get(payload);
8984 }
8985
8986 /* MCDA - Management Component Data Access
8987  * ---------------------------------------
8988  * This register allows reading and writing a firmware component.
8989  */
8990 #define MLXSW_REG_MCDA_ID 0x9063
8991 #define MLXSW_REG_MCDA_BASE_LEN 0x10
8992 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
8993 #define MLXSW_REG_MCDA_LEN \
8994                 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
8995
8996 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
8997
8998 /* reg_mcda_update_handle
8999  * Token representing the current flow executed by the FSM.
9000  * Access: RW
9001  */
9002 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
9003
9004 /* reg_mcda_offset
9005  * Offset of accessed address relative to component start. Accesses must be in
9006  * accordance to log_mcda_word_size in MCQI reg.
9007  * Access: RW
9008  */
9009 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
9010
9011 /* reg_mcda_size
9012  * Size of the data accessed, given in bytes.
9013  * Access: RW
9014  */
9015 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
9016
9017 /* reg_mcda_data
9018  * Data block accessed.
9019  * Access: RW
9020  */
9021 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
9022
9023 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
9024                                        u32 offset, u16 size, u8 *data)
9025 {
9026         int i;
9027
9028         MLXSW_REG_ZERO(mcda, payload);
9029         mlxsw_reg_mcda_update_handle_set(payload, update_handle);
9030         mlxsw_reg_mcda_offset_set(payload, offset);
9031         mlxsw_reg_mcda_size_set(payload, size);
9032
9033         for (i = 0; i < size / 4; i++)
9034                 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
9035 }
9036
9037 /* MPSC - Monitoring Packet Sampling Configuration Register
9038  * --------------------------------------------------------
9039  * MPSC Register is used to configure the Packet Sampling mechanism.
9040  */
9041 #define MLXSW_REG_MPSC_ID 0x9080
9042 #define MLXSW_REG_MPSC_LEN 0x1C
9043
9044 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
9045
9046 /* reg_mpsc_local_port
9047  * Local port number
9048  * Not supported for CPU port
9049  * Access: Index
9050  */
9051 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8);
9052
9053 /* reg_mpsc_e
9054  * Enable sampling on port local_port
9055  * Access: RW
9056  */
9057 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
9058
9059 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
9060
9061 /* reg_mpsc_rate
9062  * Sampling rate = 1 out of rate packets (with randomization around
9063  * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
9064  * Access: RW
9065  */
9066 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
9067
9068 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e,
9069                                        u32 rate)
9070 {
9071         MLXSW_REG_ZERO(mpsc, payload);
9072         mlxsw_reg_mpsc_local_port_set(payload, local_port);
9073         mlxsw_reg_mpsc_e_set(payload, e);
9074         mlxsw_reg_mpsc_rate_set(payload, rate);
9075 }
9076
9077 /* MGPC - Monitoring General Purpose Counter Set Register
9078  * The MGPC register retrieves and sets the General Purpose Counter Set.
9079  */
9080 #define MLXSW_REG_MGPC_ID 0x9081
9081 #define MLXSW_REG_MGPC_LEN 0x18
9082
9083 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
9084
9085 /* reg_mgpc_counter_set_type
9086  * Counter set type.
9087  * Access: OP
9088  */
9089 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
9090
9091 /* reg_mgpc_counter_index
9092  * Counter index.
9093  * Access: Index
9094  */
9095 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
9096
9097 enum mlxsw_reg_mgpc_opcode {
9098         /* Nop */
9099         MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
9100         /* Clear counters */
9101         MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
9102 };
9103
9104 /* reg_mgpc_opcode
9105  * Opcode.
9106  * Access: OP
9107  */
9108 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
9109
9110 /* reg_mgpc_byte_counter
9111  * Byte counter value.
9112  * Access: RW
9113  */
9114 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
9115
9116 /* reg_mgpc_packet_counter
9117  * Packet counter value.
9118  * Access: RW
9119  */
9120 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
9121
9122 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
9123                                        enum mlxsw_reg_mgpc_opcode opcode,
9124                                        enum mlxsw_reg_flow_counter_set_type set_type)
9125 {
9126         MLXSW_REG_ZERO(mgpc, payload);
9127         mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
9128         mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
9129         mlxsw_reg_mgpc_opcode_set(payload, opcode);
9130 }
9131
9132 /* MPRS - Monitoring Parsing State Register
9133  * ----------------------------------------
9134  * The MPRS register is used for setting up the parsing for hash,
9135  * policy-engine and routing.
9136  */
9137 #define MLXSW_REG_MPRS_ID 0x9083
9138 #define MLXSW_REG_MPRS_LEN 0x14
9139
9140 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
9141
9142 /* reg_mprs_parsing_depth
9143  * Minimum parsing depth.
9144  * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL
9145  * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.
9146  * Access: RW
9147  */
9148 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
9149
9150 /* reg_mprs_parsing_en
9151  * Parsing enable.
9152  * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and
9153  * NVGRE. Default is enabled. Reserved when SwitchX-2.
9154  * Access: RW
9155  */
9156 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
9157
9158 /* reg_mprs_vxlan_udp_dport
9159  * VxLAN UDP destination port.
9160  * Used for identifying VxLAN packets and for dport field in
9161  * encapsulation. Default is 4789.
9162  * Access: RW
9163  */
9164 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
9165
9166 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
9167                                        u16 vxlan_udp_dport)
9168 {
9169         MLXSW_REG_ZERO(mprs, payload);
9170         mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
9171         mlxsw_reg_mprs_parsing_en_set(payload, true);
9172         mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
9173 }
9174
9175 /* MOGCR - Monitoring Global Configuration Register
9176  * ------------------------------------------------
9177  */
9178 #define MLXSW_REG_MOGCR_ID 0x9086
9179 #define MLXSW_REG_MOGCR_LEN 0x20
9180
9181 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
9182
9183 /* reg_mogcr_ptp_iftc
9184  * PTP Ingress FIFO Trap Clear
9185  * The PTP_ING_FIFO trap provides MTPPTR with clr according
9186  * to this value. Default 0.
9187  * Reserved when IB switches and when SwitchX/-2, Spectrum-2
9188  * Access: RW
9189  */
9190 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
9191
9192 /* reg_mogcr_ptp_eftc
9193  * PTP Egress FIFO Trap Clear
9194  * The PTP_EGR_FIFO trap provides MTPPTR with clr according
9195  * to this value. Default 0.
9196  * Reserved when IB switches and when SwitchX/-2, Spectrum-2
9197  * Access: RW
9198  */
9199 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
9200
9201 /* MTPPPC - Time Precision Packet Port Configuration
9202  * -------------------------------------------------
9203  * This register serves for configuration of which PTP messages should be
9204  * timestamped. This is a global configuration, despite the register name.
9205  *
9206  * Reserved when Spectrum-2.
9207  */
9208 #define MLXSW_REG_MTPPPC_ID 0x9090
9209 #define MLXSW_REG_MTPPPC_LEN 0x28
9210
9211 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);
9212
9213 /* reg_mtpppc_ing_timestamp_message_type
9214  * Bitwise vector of PTP message types to timestamp at ingress.
9215  * MessageType field as defined by IEEE 1588
9216  * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
9217  * Default all 0
9218  * Access: RW
9219  */
9220 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
9221
9222 /* reg_mtpppc_egr_timestamp_message_type
9223  * Bitwise vector of PTP message types to timestamp at egress.
9224  * MessageType field as defined by IEEE 1588
9225  * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
9226  * Default all 0
9227  * Access: RW
9228  */
9229 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
9230
9231 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)
9232 {
9233         MLXSW_REG_ZERO(mtpppc, payload);
9234         mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);
9235         mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);
9236 }
9237
9238 /* MTPPTR - Time Precision Packet Timestamping Reading
9239  * ---------------------------------------------------
9240  * The MTPPTR is used for reading the per port PTP timestamp FIFO.
9241  * There is a trap for packets which are latched to the timestamp FIFO, thus the
9242  * SW knows which FIFO to read. Note that packets enter the FIFO before been
9243  * trapped. The sequence number is used to synchronize the timestamp FIFO
9244  * entries and the trapped packets.
9245  * Reserved when Spectrum-2.
9246  */
9247
9248 #define MLXSW_REG_MTPPTR_ID 0x9091
9249 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */
9250 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */
9251 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4
9252 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN +               \
9253                     MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
9254
9255 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);
9256
9257 /* reg_mtpptr_local_port
9258  * Not supported for CPU port.
9259  * Access: Index
9260  */
9261 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8);
9262
9263 enum mlxsw_reg_mtpptr_dir {
9264         MLXSW_REG_MTPPTR_DIR_INGRESS,
9265         MLXSW_REG_MTPPTR_DIR_EGRESS,
9266 };
9267
9268 /* reg_mtpptr_dir
9269  * Direction.
9270  * Access: Index
9271  */
9272 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
9273
9274 /* reg_mtpptr_clr
9275  * Clear the records.
9276  * Access: OP
9277  */
9278 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
9279
9280 /* reg_mtpptr_num_rec
9281  * Number of valid records in the response
9282  * Range 0.. cap_ptp_timestamp_fifo
9283  * Access: RO
9284  */
9285 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
9286
9287 /* reg_mtpptr_rec_message_type
9288  * MessageType field as defined by IEEE 1588 Each bit corresponds to a value
9289  * (e.g. Bit0: Sync, Bit1: Delay_Req)
9290  * Access: RO
9291  */
9292 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
9293                      MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
9294                      MLXSW_REG_MTPPTR_REC_LEN, 0, false);
9295
9296 /* reg_mtpptr_rec_domain_number
9297  * DomainNumber field as defined by IEEE 1588
9298  * Access: RO
9299  */
9300 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
9301                      MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
9302                      MLXSW_REG_MTPPTR_REC_LEN, 0, false);
9303
9304 /* reg_mtpptr_rec_sequence_id
9305  * SequenceId field as defined by IEEE 1588
9306  * Access: RO
9307  */
9308 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
9309                      MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
9310                      MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
9311
9312 /* reg_mtpptr_rec_timestamp_high
9313  * Timestamp of when the PTP packet has passed through the port Units of PLL
9314  * clock time.
9315  * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec.
9316  * Access: RO
9317  */
9318 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
9319                      MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
9320                      MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
9321
9322 /* reg_mtpptr_rec_timestamp_low
9323  * See rec_timestamp_high.
9324  * Access: RO
9325  */
9326 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
9327                      MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
9328                      MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);
9329
9330 static inline void mlxsw_reg_mtpptr_unpack(const char *payload,
9331                                            unsigned int rec,
9332                                            u8 *p_message_type,
9333                                            u8 *p_domain_number,
9334                                            u16 *p_sequence_id,
9335                                            u64 *p_timestamp)
9336 {
9337         u32 timestamp_high, timestamp_low;
9338
9339         *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);
9340         *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);
9341         *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);
9342         timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);
9343         timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);
9344         *p_timestamp = (u64)timestamp_high << 32 | timestamp_low;
9345 }
9346
9347 /* MTPTPT - Monitoring Precision Time Protocol Trap Register
9348  * ---------------------------------------------------------
9349  * This register is used for configuring under which trap to deliver PTP
9350  * packets depending on type of the packet.
9351  */
9352 #define MLXSW_REG_MTPTPT_ID 0x9092
9353 #define MLXSW_REG_MTPTPT_LEN 0x08
9354
9355 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);
9356
9357 enum mlxsw_reg_mtptpt_trap_id {
9358         MLXSW_REG_MTPTPT_TRAP_ID_PTP0,
9359         MLXSW_REG_MTPTPT_TRAP_ID_PTP1,
9360 };
9361
9362 /* reg_mtptpt_trap_id
9363  * Trap id.
9364  * Access: Index
9365  */
9366 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
9367
9368 /* reg_mtptpt_message_type
9369  * Bitwise vector of PTP message types to trap. This is a necessary but
9370  * non-sufficient condition since need to enable also per port. See MTPPPC.
9371  * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g.
9372  * Bit0: Sync, Bit1: Delay_Req)
9373  */
9374 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
9375
9376 static inline void mlxsw_reg_mtptptp_pack(char *payload,
9377                                           enum mlxsw_reg_mtptpt_trap_id trap_id,
9378                                           u16 message_type)
9379 {
9380         MLXSW_REG_ZERO(mtptpt, payload);
9381         mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);
9382         mlxsw_reg_mtptpt_message_type_set(payload, message_type);
9383 }
9384
9385 /* MGPIR - Management General Peripheral Information Register
9386  * ----------------------------------------------------------
9387  * MGPIR register allows software to query the hardware and
9388  * firmware general information of peripheral entities.
9389  */
9390 #define MLXSW_REG_MGPIR_ID 0x9100
9391 #define MLXSW_REG_MGPIR_LEN 0xA0
9392
9393 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN);
9394
9395 enum mlxsw_reg_mgpir_device_type {
9396         MLXSW_REG_MGPIR_DEVICE_TYPE_NONE,
9397         MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE,
9398 };
9399
9400 /* device_type
9401  * Access: RO
9402  */
9403 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);
9404
9405 /* devices_per_flash
9406  * Number of devices of device_type per flash (can be shared by few devices).
9407  * Access: RO
9408  */
9409 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
9410
9411 /* num_of_devices
9412  * Number of devices of device_type.
9413  * Access: RO
9414  */
9415 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
9416
9417 static inline void mlxsw_reg_mgpir_pack(char *payload)
9418 {
9419         MLXSW_REG_ZERO(mgpir, payload);
9420 }
9421
9422 static inline void
9423 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
9424                        enum mlxsw_reg_mgpir_device_type *device_type,
9425                        u8 *devices_per_flash)
9426 {
9427         if (num_of_devices)
9428                 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload);
9429         if (device_type)
9430                 *device_type = mlxsw_reg_mgpir_device_type_get(payload);
9431         if (devices_per_flash)
9432                 *devices_per_flash =
9433                                 mlxsw_reg_mgpir_devices_per_flash_get(payload);
9434 }
9435
9436 /* TNGCR - Tunneling NVE General Configuration Register
9437  * ----------------------------------------------------
9438  * The TNGCR register is used for setting up the NVE Tunneling configuration.
9439  */
9440 #define MLXSW_REG_TNGCR_ID 0xA001
9441 #define MLXSW_REG_TNGCR_LEN 0x44
9442
9443 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
9444
9445 enum mlxsw_reg_tngcr_type {
9446         MLXSW_REG_TNGCR_TYPE_VXLAN,
9447         MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
9448         MLXSW_REG_TNGCR_TYPE_GENEVE,
9449         MLXSW_REG_TNGCR_TYPE_NVGRE,
9450 };
9451
9452 /* reg_tngcr_type
9453  * Tunnel type for encapsulation and decapsulation. The types are mutually
9454  * exclusive.
9455  * Note: For Spectrum the NVE parsing must be enabled in MPRS.
9456  * Access: RW
9457  */
9458 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
9459
9460 /* reg_tngcr_nve_valid
9461  * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation.
9462  * Access: RW
9463  */
9464 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
9465
9466 /* reg_tngcr_nve_ttl_uc
9467  * The TTL for NVE tunnel encapsulation underlay unicast packets.
9468  * Access: RW
9469  */
9470 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
9471
9472 /* reg_tngcr_nve_ttl_mc
9473  * The TTL for NVE tunnel encapsulation underlay multicast packets.
9474  * Access: RW
9475  */
9476 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
9477
9478 enum {
9479         /* Do not copy flow label. Calculate flow label using nve_flh. */
9480         MLXSW_REG_TNGCR_FL_NO_COPY,
9481         /* Copy flow label from inner packet if packet is IPv6 and
9482          * encapsulation is by IPv6. Otherwise, calculate flow label using
9483          * nve_flh.
9484          */
9485         MLXSW_REG_TNGCR_FL_COPY,
9486 };
9487
9488 /* reg_tngcr_nve_flc
9489  * For NVE tunnel encapsulation: Flow label copy from inner packet.
9490  * Access: RW
9491  */
9492 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
9493
9494 enum {
9495         /* Flow label is static. In Spectrum this means '0'. Spectrum-2
9496          * uses {nve_fl_prefix, nve_fl_suffix}.
9497          */
9498         MLXSW_REG_TNGCR_FL_NO_HASH,
9499         /* 8 LSBs of the flow label are calculated from ECMP hash of the
9500          * inner packet. 12 MSBs are configured by nve_fl_prefix.
9501          */
9502         MLXSW_REG_TNGCR_FL_HASH,
9503 };
9504
9505 /* reg_tngcr_nve_flh
9506  * NVE flow label hash.
9507  * Access: RW
9508  */
9509 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
9510
9511 /* reg_tngcr_nve_fl_prefix
9512  * NVE flow label prefix. Constant 12 MSBs of the flow label.
9513  * Access: RW
9514  */
9515 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
9516
9517 /* reg_tngcr_nve_fl_suffix
9518  * NVE flow label suffix. Constant 8 LSBs of the flow label.
9519  * Reserved when nve_flh=1 and for Spectrum.
9520  * Access: RW
9521  */
9522 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
9523
9524 enum {
9525         /* Source UDP port is fixed (default '0') */
9526         MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
9527         /* Source UDP port is calculated based on hash */
9528         MLXSW_REG_TNGCR_UDP_SPORT_HASH,
9529 };
9530
9531 /* reg_tngcr_nve_udp_sport_type
9532  * NVE UDP source port type.
9533  * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2).
9534  * When the source UDP port is calculated based on hash, then the 8 LSBs
9535  * are calculated from hash the 8 MSBs are configured by
9536  * nve_udp_sport_prefix.
9537  * Access: RW
9538  */
9539 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
9540
9541 /* reg_tngcr_nve_udp_sport_prefix
9542  * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port.
9543  * Reserved when NVE type is NVGRE.
9544  * Access: RW
9545  */
9546 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
9547
9548 /* reg_tngcr_nve_group_size_mc
9549  * The amount of sequential linked lists of MC entries. The first linked
9550  * list is configured by SFD.underlay_mc_ptr.
9551  * Valid values: 1, 2, 4, 8, 16, 32, 64
9552  * The linked list are configured by TNUMT.
9553  * The hash is set by LAG hash.
9554  * Access: RW
9555  */
9556 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
9557
9558 /* reg_tngcr_nve_group_size_flood
9559  * The amount of sequential linked lists of flooding entries. The first
9560  * linked list is configured by SFMR.nve_tunnel_flood_ptr
9561  * Valid values: 1, 2, 4, 8, 16, 32, 64
9562  * The linked list are configured by TNUMT.
9563  * The hash is set by LAG hash.
9564  * Access: RW
9565  */
9566 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
9567
9568 /* reg_tngcr_learn_enable
9569  * During decapsulation, whether to learn from NVE port.
9570  * Reserved when Spectrum-2. See TNPC.
9571  * Access: RW
9572  */
9573 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
9574
9575 /* reg_tngcr_underlay_virtual_router
9576  * Underlay virtual router.
9577  * Reserved when Spectrum-2.
9578  * Access: RW
9579  */
9580 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
9581
9582 /* reg_tngcr_underlay_rif
9583  * Underlay ingress router interface. RIF type should be loopback generic.
9584  * Reserved when Spectrum.
9585  * Access: RW
9586  */
9587 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
9588
9589 /* reg_tngcr_usipv4
9590  * Underlay source IPv4 address of the NVE.
9591  * Access: RW
9592  */
9593 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
9594
9595 /* reg_tngcr_usipv6
9596  * Underlay source IPv6 address of the NVE. For Spectrum, must not be
9597  * modified under traffic of NVE tunneling encapsulation.
9598  * Access: RW
9599  */
9600 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
9601
9602 static inline void mlxsw_reg_tngcr_pack(char *payload,
9603                                         enum mlxsw_reg_tngcr_type type,
9604                                         bool valid, u8 ttl)
9605 {
9606         MLXSW_REG_ZERO(tngcr, payload);
9607         mlxsw_reg_tngcr_type_set(payload, type);
9608         mlxsw_reg_tngcr_nve_valid_set(payload, valid);
9609         mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
9610         mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
9611         mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
9612         mlxsw_reg_tngcr_nve_flh_set(payload, 0);
9613         mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
9614                                                MLXSW_REG_TNGCR_UDP_SPORT_HASH);
9615         mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
9616         mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
9617         mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
9618 }
9619
9620 /* TNUMT - Tunneling NVE Underlay Multicast Table Register
9621  * -------------------------------------------------------
9622  * The TNUMT register is for building the underlay MC table. It is used
9623  * for MC, flooding and BC traffic into the NVE tunnel.
9624  */
9625 #define MLXSW_REG_TNUMT_ID 0xA003
9626 #define MLXSW_REG_TNUMT_LEN 0x20
9627
9628 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
9629
9630 enum mlxsw_reg_tnumt_record_type {
9631         MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
9632         MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
9633         MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
9634 };
9635
9636 /* reg_tnumt_record_type
9637  * Record type.
9638  * Access: RW
9639  */
9640 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
9641
9642 enum mlxsw_reg_tnumt_tunnel_port {
9643         MLXSW_REG_TNUMT_TUNNEL_PORT_NVE,
9644         MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS,
9645         MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0,
9646         MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1,
9647 };
9648
9649 /* reg_tnumt_tunnel_port
9650  * Tunnel port.
9651  * Access: RW
9652  */
9653 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
9654
9655 /* reg_tnumt_underlay_mc_ptr
9656  * Index to the underlay multicast table.
9657  * For Spectrum the index is to the KVD linear.
9658  * Access: Index
9659  */
9660 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
9661
9662 /* reg_tnumt_vnext
9663  * The next_underlay_mc_ptr is valid.
9664  * Access: RW
9665  */
9666 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
9667
9668 /* reg_tnumt_next_underlay_mc_ptr
9669  * The next index to the underlay multicast table.
9670  * Access: RW
9671  */
9672 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
9673
9674 /* reg_tnumt_record_size
9675  * Number of IP addresses in the record.
9676  * Range is 1..cap_max_nve_mc_entries_ipv{4,6}
9677  * Access: RW
9678  */
9679 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
9680
9681 /* reg_tnumt_udip
9682  * The underlay IPv4 addresses. udip[i] is reserved if i >= size
9683  * Access: RW
9684  */
9685 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
9686
9687 /* reg_tnumt_udip_ptr
9688  * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if
9689  * i >= size. The IPv6 addresses are configured by RIPS.
9690  * Access: RW
9691  */
9692 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
9693
9694 static inline void mlxsw_reg_tnumt_pack(char *payload,
9695                                         enum mlxsw_reg_tnumt_record_type type,
9696                                         enum mlxsw_reg_tnumt_tunnel_port tport,
9697                                         u32 underlay_mc_ptr, bool vnext,
9698                                         u32 next_underlay_mc_ptr,
9699                                         u8 record_size)
9700 {
9701         MLXSW_REG_ZERO(tnumt, payload);
9702         mlxsw_reg_tnumt_record_type_set(payload, type);
9703         mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
9704         mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
9705         mlxsw_reg_tnumt_vnext_set(payload, vnext);
9706         mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
9707         mlxsw_reg_tnumt_record_size_set(payload, record_size);
9708 }
9709
9710 /* TNQCR - Tunneling NVE QoS Configuration Register
9711  * ------------------------------------------------
9712  * The TNQCR register configures how QoS is set in encapsulation into the
9713  * underlay network.
9714  */
9715 #define MLXSW_REG_TNQCR_ID 0xA010
9716 #define MLXSW_REG_TNQCR_LEN 0x0C
9717
9718 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
9719
9720 /* reg_tnqcr_enc_set_dscp
9721  * For encapsulation: How to set DSCP field:
9722  * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay
9723  * (outer) IP header. If there is no IP header, use TNQDR.dscp
9724  * 1 - Set the DSCP field as TNQDR.dscp
9725  * Access: RW
9726  */
9727 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
9728
9729 static inline void mlxsw_reg_tnqcr_pack(char *payload)
9730 {
9731         MLXSW_REG_ZERO(tnqcr, payload);
9732         mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
9733 }
9734
9735 /* TNQDR - Tunneling NVE QoS Default Register
9736  * ------------------------------------------
9737  * The TNQDR register configures the default QoS settings for NVE
9738  * encapsulation.
9739  */
9740 #define MLXSW_REG_TNQDR_ID 0xA011
9741 #define MLXSW_REG_TNQDR_LEN 0x08
9742
9743 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
9744
9745 /* reg_tnqdr_local_port
9746  * Local port number (receive port). CPU port is supported.
9747  * Access: Index
9748  */
9749 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8);
9750
9751 /* reg_tnqdr_dscp
9752  * For encapsulation, the default DSCP.
9753  * Access: RW
9754  */
9755 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
9756
9757 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
9758 {
9759         MLXSW_REG_ZERO(tnqdr, payload);
9760         mlxsw_reg_tnqdr_local_port_set(payload, local_port);
9761         mlxsw_reg_tnqdr_dscp_set(payload, 0);
9762 }
9763
9764 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
9765  * --------------------------------------------------------
9766  * The TNEEM register maps ECN of the IP header at the ingress to the
9767  * encapsulation to the ECN of the underlay network.
9768  */
9769 #define MLXSW_REG_TNEEM_ID 0xA012
9770 #define MLXSW_REG_TNEEM_LEN 0x0C
9771
9772 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
9773
9774 /* reg_tneem_overlay_ecn
9775  * ECN of the IP header in the overlay network.
9776  * Access: Index
9777  */
9778 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
9779
9780 /* reg_tneem_underlay_ecn
9781  * ECN of the IP header in the underlay network.
9782  * Access: RW
9783  */
9784 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
9785
9786 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
9787                                         u8 underlay_ecn)
9788 {
9789         MLXSW_REG_ZERO(tneem, payload);
9790         mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
9791         mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
9792 }
9793
9794 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register
9795  * --------------------------------------------------------
9796  * The TNDEM register configures the actions that are done in the
9797  * decapsulation.
9798  */
9799 #define MLXSW_REG_TNDEM_ID 0xA013
9800 #define MLXSW_REG_TNDEM_LEN 0x0C
9801
9802 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
9803
9804 /* reg_tndem_underlay_ecn
9805  * ECN field of the IP header in the underlay network.
9806  * Access: Index
9807  */
9808 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
9809
9810 /* reg_tndem_overlay_ecn
9811  * ECN field of the IP header in the overlay network.
9812  * Access: Index
9813  */
9814 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
9815
9816 /* reg_tndem_eip_ecn
9817  * Egress IP ECN. ECN field of the IP header of the packet which goes out
9818  * from the decapsulation.
9819  * Access: RW
9820  */
9821 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
9822
9823 /* reg_tndem_trap_en
9824  * Trap enable:
9825  * 0 - No trap due to decap ECN
9826  * 1 - Trap enable with trap_id
9827  * Access: RW
9828  */
9829 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
9830
9831 /* reg_tndem_trap_id
9832  * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
9833  * Reserved when trap_en is '0'.
9834  * Access: RW
9835  */
9836 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
9837
9838 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
9839                                         u8 overlay_ecn, u8 ecn, bool trap_en,
9840                                         u16 trap_id)
9841 {
9842         MLXSW_REG_ZERO(tndem, payload);
9843         mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
9844         mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
9845         mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
9846         mlxsw_reg_tndem_trap_en_set(payload, trap_en);
9847         mlxsw_reg_tndem_trap_id_set(payload, trap_id);
9848 }
9849
9850 /* TNPC - Tunnel Port Configuration Register
9851  * -----------------------------------------
9852  * The TNPC register is used for tunnel port configuration.
9853  * Reserved when Spectrum.
9854  */
9855 #define MLXSW_REG_TNPC_ID 0xA020
9856 #define MLXSW_REG_TNPC_LEN 0x18
9857
9858 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
9859
9860 enum mlxsw_reg_tnpc_tunnel_port {
9861         MLXSW_REG_TNPC_TUNNEL_PORT_NVE,
9862         MLXSW_REG_TNPC_TUNNEL_PORT_VPLS,
9863         MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0,
9864         MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1,
9865 };
9866
9867 /* reg_tnpc_tunnel_port
9868  * Tunnel port.
9869  * Access: Index
9870  */
9871 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
9872
9873 /* reg_tnpc_learn_enable_v6
9874  * During IPv6 underlay decapsulation, whether to learn from tunnel port.
9875  * Access: RW
9876  */
9877 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
9878
9879 /* reg_tnpc_learn_enable_v4
9880  * During IPv4 underlay decapsulation, whether to learn from tunnel port.
9881  * Access: RW
9882  */
9883 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
9884
9885 static inline void mlxsw_reg_tnpc_pack(char *payload,
9886                                        enum mlxsw_reg_tnpc_tunnel_port tport,
9887                                        bool learn_enable)
9888 {
9889         MLXSW_REG_ZERO(tnpc, payload);
9890         mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
9891         mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
9892         mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
9893 }
9894
9895 /* TIGCR - Tunneling IPinIP General Configuration Register
9896  * -------------------------------------------------------
9897  * The TIGCR register is used for setting up the IPinIP Tunnel configuration.
9898  */
9899 #define MLXSW_REG_TIGCR_ID 0xA801
9900 #define MLXSW_REG_TIGCR_LEN 0x10
9901
9902 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
9903
9904 /* reg_tigcr_ipip_ttlc
9905  * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet
9906  * header.
9907  * Access: RW
9908  */
9909 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
9910
9911 /* reg_tigcr_ipip_ttl_uc
9912  * The TTL for IPinIP Tunnel encapsulation of unicast packets if
9913  * reg_tigcr_ipip_ttlc is unset.
9914  * Access: RW
9915  */
9916 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
9917
9918 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
9919 {
9920         MLXSW_REG_ZERO(tigcr, payload);
9921         mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
9922         mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
9923 }
9924
9925 /* SBPR - Shared Buffer Pools Register
9926  * -----------------------------------
9927  * The SBPR configures and retrieves the shared buffer pools and configuration.
9928  */
9929 #define MLXSW_REG_SBPR_ID 0xB001
9930 #define MLXSW_REG_SBPR_LEN 0x14
9931
9932 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
9933
9934 /* shared direstion enum for SBPR, SBCM, SBPM */
9935 enum mlxsw_reg_sbxx_dir {
9936         MLXSW_REG_SBXX_DIR_INGRESS,
9937         MLXSW_REG_SBXX_DIR_EGRESS,
9938 };
9939
9940 /* reg_sbpr_dir
9941  * Direction.
9942  * Access: Index
9943  */
9944 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
9945
9946 /* reg_sbpr_pool
9947  * Pool index.
9948  * Access: Index
9949  */
9950 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
9951
9952 /* reg_sbpr_infi_size
9953  * Size is infinite.
9954  * Access: RW
9955  */
9956 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
9957
9958 /* reg_sbpr_size
9959  * Pool size in buffer cells.
9960  * Reserved when infi_size = 1.
9961  * Access: RW
9962  */
9963 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
9964
9965 enum mlxsw_reg_sbpr_mode {
9966         MLXSW_REG_SBPR_MODE_STATIC,
9967         MLXSW_REG_SBPR_MODE_DYNAMIC,
9968 };
9969
9970 /* reg_sbpr_mode
9971  * Pool quota calculation mode.
9972  * Access: RW
9973  */
9974 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
9975
9976 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
9977                                        enum mlxsw_reg_sbxx_dir dir,
9978                                        enum mlxsw_reg_sbpr_mode mode, u32 size,
9979                                        bool infi_size)
9980 {
9981         MLXSW_REG_ZERO(sbpr, payload);
9982         mlxsw_reg_sbpr_pool_set(payload, pool);
9983         mlxsw_reg_sbpr_dir_set(payload, dir);
9984         mlxsw_reg_sbpr_mode_set(payload, mode);
9985         mlxsw_reg_sbpr_size_set(payload, size);
9986         mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
9987 }
9988
9989 /* SBCM - Shared Buffer Class Management Register
9990  * ----------------------------------------------
9991  * The SBCM register configures and retrieves the shared buffer allocation
9992  * and configuration according to Port-PG, including the binding to pool
9993  * and definition of the associated quota.
9994  */
9995 #define MLXSW_REG_SBCM_ID 0xB002
9996 #define MLXSW_REG_SBCM_LEN 0x28
9997
9998 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
9999
10000 /* reg_sbcm_local_port
10001  * Local port number.
10002  * For Ingress: excludes CPU port and Router port
10003  * For Egress: excludes IP Router
10004  * Access: Index
10005  */
10006 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
10007
10008 /* reg_sbcm_pg_buff
10009  * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
10010  * For PG buffer: range is 0..cap_max_pg_buffers - 1
10011  * For traffic class: range is 0..cap_max_tclass - 1
10012  * Note that when traffic class is in MC aware mode then the traffic
10013  * classes which are MC aware cannot be configured.
10014  * Access: Index
10015  */
10016 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
10017
10018 /* reg_sbcm_dir
10019  * Direction.
10020  * Access: Index
10021  */
10022 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
10023
10024 /* reg_sbcm_min_buff
10025  * Minimum buffer size for the limiter, in cells.
10026  * Access: RW
10027  */
10028 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
10029
10030 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
10031 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
10032 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
10033
10034 /* reg_sbcm_infi_max
10035  * Max buffer is infinite.
10036  * Access: RW
10037  */
10038 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
10039
10040 /* reg_sbcm_max_buff
10041  * When the pool associated to the port-pg/tclass is configured to
10042  * static, Maximum buffer size for the limiter configured in cells.
10043  * When the pool associated to the port-pg/tclass is configured to
10044  * dynamic, the max_buff holds the "alpha" parameter, supporting
10045  * the following values:
10046  * 0: 0
10047  * i: (1/128)*2^(i-1), for i=1..14
10048  * 0xFF: Infinity
10049  * Reserved when infi_max = 1.
10050  * Access: RW
10051  */
10052 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
10053
10054 /* reg_sbcm_pool
10055  * Association of the port-priority to a pool.
10056  * Access: RW
10057  */
10058 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
10059
10060 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
10061                                        enum mlxsw_reg_sbxx_dir dir,
10062                                        u32 min_buff, u32 max_buff,
10063                                        bool infi_max, u8 pool)
10064 {
10065         MLXSW_REG_ZERO(sbcm, payload);
10066         mlxsw_reg_sbcm_local_port_set(payload, local_port);
10067         mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
10068         mlxsw_reg_sbcm_dir_set(payload, dir);
10069         mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
10070         mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
10071         mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
10072         mlxsw_reg_sbcm_pool_set(payload, pool);
10073 }
10074
10075 /* SBPM - Shared Buffer Port Management Register
10076  * ---------------------------------------------
10077  * The SBPM register configures and retrieves the shared buffer allocation
10078  * and configuration according to Port-Pool, including the definition
10079  * of the associated quota.
10080  */
10081 #define MLXSW_REG_SBPM_ID 0xB003
10082 #define MLXSW_REG_SBPM_LEN 0x28
10083
10084 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
10085
10086 /* reg_sbpm_local_port
10087  * Local port number.
10088  * For Ingress: excludes CPU port and Router port
10089  * For Egress: excludes IP Router
10090  * Access: Index
10091  */
10092 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
10093
10094 /* reg_sbpm_pool
10095  * The pool associated to quota counting on the local_port.
10096  * Access: Index
10097  */
10098 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
10099
10100 /* reg_sbpm_dir
10101  * Direction.
10102  * Access: Index
10103  */
10104 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
10105
10106 /* reg_sbpm_buff_occupancy
10107  * Current buffer occupancy in cells.
10108  * Access: RO
10109  */
10110 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
10111
10112 /* reg_sbpm_clr
10113  * Clear Max Buffer Occupancy
10114  * When this bit is set, max_buff_occupancy field is cleared (and a
10115  * new max value is tracked from the time the clear was performed).
10116  * Access: OP
10117  */
10118 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
10119
10120 /* reg_sbpm_max_buff_occupancy
10121  * Maximum value of buffer occupancy in cells monitored. Cleared by
10122  * writing to the clr field.
10123  * Access: RO
10124  */
10125 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
10126
10127 /* reg_sbpm_min_buff
10128  * Minimum buffer size for the limiter, in cells.
10129  * Access: RW
10130  */
10131 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
10132
10133 /* reg_sbpm_max_buff
10134  * When the pool associated to the port-pg/tclass is configured to
10135  * static, Maximum buffer size for the limiter configured in cells.
10136  * When the pool associated to the port-pg/tclass is configured to
10137  * dynamic, the max_buff holds the "alpha" parameter, supporting
10138  * the following values:
10139  * 0: 0
10140  * i: (1/128)*2^(i-1), for i=1..14
10141  * 0xFF: Infinity
10142  * Access: RW
10143  */
10144 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
10145
10146 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
10147                                        enum mlxsw_reg_sbxx_dir dir, bool clr,
10148                                        u32 min_buff, u32 max_buff)
10149 {
10150         MLXSW_REG_ZERO(sbpm, payload);
10151         mlxsw_reg_sbpm_local_port_set(payload, local_port);
10152         mlxsw_reg_sbpm_pool_set(payload, pool);
10153         mlxsw_reg_sbpm_dir_set(payload, dir);
10154         mlxsw_reg_sbpm_clr_set(payload, clr);
10155         mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
10156         mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
10157 }
10158
10159 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
10160                                          u32 *p_max_buff_occupancy)
10161 {
10162         *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
10163         *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
10164 }
10165
10166 /* SBMM - Shared Buffer Multicast Management Register
10167  * --------------------------------------------------
10168  * The SBMM register configures and retrieves the shared buffer allocation
10169  * and configuration for MC packets according to Switch-Priority, including
10170  * the binding to pool and definition of the associated quota.
10171  */
10172 #define MLXSW_REG_SBMM_ID 0xB004
10173 #define MLXSW_REG_SBMM_LEN 0x28
10174
10175 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
10176
10177 /* reg_sbmm_prio
10178  * Switch Priority.
10179  * Access: Index
10180  */
10181 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
10182
10183 /* reg_sbmm_min_buff
10184  * Minimum buffer size for the limiter, in cells.
10185  * Access: RW
10186  */
10187 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
10188
10189 /* reg_sbmm_max_buff
10190  * When the pool associated to the port-pg/tclass is configured to
10191  * static, Maximum buffer size for the limiter configured in cells.
10192  * When the pool associated to the port-pg/tclass is configured to
10193  * dynamic, the max_buff holds the "alpha" parameter, supporting
10194  * the following values:
10195  * 0: 0
10196  * i: (1/128)*2^(i-1), for i=1..14
10197  * 0xFF: Infinity
10198  * Access: RW
10199  */
10200 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
10201
10202 /* reg_sbmm_pool
10203  * Association of the port-priority to a pool.
10204  * Access: RW
10205  */
10206 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
10207
10208 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
10209                                        u32 max_buff, u8 pool)
10210 {
10211         MLXSW_REG_ZERO(sbmm, payload);
10212         mlxsw_reg_sbmm_prio_set(payload, prio);
10213         mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
10214         mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
10215         mlxsw_reg_sbmm_pool_set(payload, pool);
10216 }
10217
10218 /* SBSR - Shared Buffer Status Register
10219  * ------------------------------------
10220  * The SBSR register retrieves the shared buffer occupancy according to
10221  * Port-Pool. Note that this register enables reading a large amount of data.
10222  * It is the user's responsibility to limit the amount of data to ensure the
10223  * response can match the maximum transfer unit. In case the response exceeds
10224  * the maximum transport unit, it will be truncated with no special notice.
10225  */
10226 #define MLXSW_REG_SBSR_ID 0xB005
10227 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
10228 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
10229 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
10230 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN +   \
10231                             MLXSW_REG_SBSR_REC_LEN *    \
10232                             MLXSW_REG_SBSR_REC_MAX_COUNT)
10233
10234 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
10235
10236 /* reg_sbsr_clr
10237  * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
10238  * field is cleared (and a new max value is tracked from the time the clear
10239  * was performed).
10240  * Access: OP
10241  */
10242 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
10243
10244 /* reg_sbsr_ingress_port_mask
10245  * Bit vector for all ingress network ports.
10246  * Indicates which of the ports (for which the relevant bit is set)
10247  * are affected by the set operation. Configuration of any other port
10248  * does not change.
10249  * Access: Index
10250  */
10251 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
10252
10253 /* reg_sbsr_pg_buff_mask
10254  * Bit vector for all switch priority groups.
10255  * Indicates which of the priorities (for which the relevant bit is set)
10256  * are affected by the set operation. Configuration of any other priority
10257  * does not change.
10258  * Range is 0..cap_max_pg_buffers - 1
10259  * Access: Index
10260  */
10261 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
10262
10263 /* reg_sbsr_egress_port_mask
10264  * Bit vector for all egress network ports.
10265  * Indicates which of the ports (for which the relevant bit is set)
10266  * are affected by the set operation. Configuration of any other port
10267  * does not change.
10268  * Access: Index
10269  */
10270 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
10271
10272 /* reg_sbsr_tclass_mask
10273  * Bit vector for all traffic classes.
10274  * Indicates which of the traffic classes (for which the relevant bit is
10275  * set) are affected by the set operation. Configuration of any other
10276  * traffic class does not change.
10277  * Range is 0..cap_max_tclass - 1
10278  * Access: Index
10279  */
10280 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
10281
10282 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
10283 {
10284         MLXSW_REG_ZERO(sbsr, payload);
10285         mlxsw_reg_sbsr_clr_set(payload, clr);
10286 }
10287
10288 /* reg_sbsr_rec_buff_occupancy
10289  * Current buffer occupancy in cells.
10290  * Access: RO
10291  */
10292 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
10293                      0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
10294
10295 /* reg_sbsr_rec_max_buff_occupancy
10296  * Maximum value of buffer occupancy in cells monitored. Cleared by
10297  * writing to the clr field.
10298  * Access: RO
10299  */
10300 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
10301                      0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
10302
10303 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
10304                                              u32 *p_buff_occupancy,
10305                                              u32 *p_max_buff_occupancy)
10306 {
10307         *p_buff_occupancy =
10308                 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
10309         *p_max_buff_occupancy =
10310                 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
10311 }
10312
10313 /* SBIB - Shared Buffer Internal Buffer Register
10314  * ---------------------------------------------
10315  * The SBIB register configures per port buffers for internal use. The internal
10316  * buffers consume memory on the port buffers (note that the port buffers are
10317  * used also by PBMC).
10318  *
10319  * For Spectrum this is used for egress mirroring.
10320  */
10321 #define MLXSW_REG_SBIB_ID 0xB006
10322 #define MLXSW_REG_SBIB_LEN 0x10
10323
10324 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
10325
10326 /* reg_sbib_local_port
10327  * Local port number
10328  * Not supported for CPU port and router port
10329  * Access: Index
10330  */
10331 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
10332
10333 /* reg_sbib_buff_size
10334  * Units represented in cells
10335  * Allowed range is 0 to (cap_max_headroom_size - 1)
10336  * Default is 0
10337  * Access: RW
10338  */
10339 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
10340
10341 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
10342                                        u32 buff_size)
10343 {
10344         MLXSW_REG_ZERO(sbib, payload);
10345         mlxsw_reg_sbib_local_port_set(payload, local_port);
10346         mlxsw_reg_sbib_buff_size_set(payload, buff_size);
10347 }
10348
10349 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
10350         MLXSW_REG(sgcr),
10351         MLXSW_REG(spad),
10352         MLXSW_REG(smid),
10353         MLXSW_REG(sspr),
10354         MLXSW_REG(sfdat),
10355         MLXSW_REG(sfd),
10356         MLXSW_REG(sfn),
10357         MLXSW_REG(spms),
10358         MLXSW_REG(spvid),
10359         MLXSW_REG(spvm),
10360         MLXSW_REG(spaft),
10361         MLXSW_REG(sfgc),
10362         MLXSW_REG(sftr),
10363         MLXSW_REG(sfdf),
10364         MLXSW_REG(sldr),
10365         MLXSW_REG(slcr),
10366         MLXSW_REG(slcor),
10367         MLXSW_REG(spmlr),
10368         MLXSW_REG(svfa),
10369         MLXSW_REG(svpe),
10370         MLXSW_REG(sfmr),
10371         MLXSW_REG(spvmlr),
10372         MLXSW_REG(cwtp),
10373         MLXSW_REG(cwtpm),
10374         MLXSW_REG(pgcr),
10375         MLXSW_REG(ppbt),
10376         MLXSW_REG(pacl),
10377         MLXSW_REG(pagt),
10378         MLXSW_REG(ptar),
10379         MLXSW_REG(ppbs),
10380         MLXSW_REG(prcr),
10381         MLXSW_REG(pefa),
10382         MLXSW_REG(pemrbt),
10383         MLXSW_REG(ptce2),
10384         MLXSW_REG(perpt),
10385         MLXSW_REG(peabfe),
10386         MLXSW_REG(perar),
10387         MLXSW_REG(ptce3),
10388         MLXSW_REG(percr),
10389         MLXSW_REG(pererp),
10390         MLXSW_REG(iedr),
10391         MLXSW_REG(qpts),
10392         MLXSW_REG(qpcr),
10393         MLXSW_REG(qtct),
10394         MLXSW_REG(qeec),
10395         MLXSW_REG(qrwe),
10396         MLXSW_REG(qpdsm),
10397         MLXSW_REG(qpdpm),
10398         MLXSW_REG(qtctm),
10399         MLXSW_REG(pmlp),
10400         MLXSW_REG(pmtu),
10401         MLXSW_REG(ptys),
10402         MLXSW_REG(ppad),
10403         MLXSW_REG(paos),
10404         MLXSW_REG(pfcc),
10405         MLXSW_REG(ppcnt),
10406         MLXSW_REG(plib),
10407         MLXSW_REG(pptb),
10408         MLXSW_REG(pbmc),
10409         MLXSW_REG(pspa),
10410         MLXSW_REG(pplr),
10411         MLXSW_REG(htgt),
10412         MLXSW_REG(hpkt),
10413         MLXSW_REG(rgcr),
10414         MLXSW_REG(ritr),
10415         MLXSW_REG(rtar),
10416         MLXSW_REG(ratr),
10417         MLXSW_REG(rtdp),
10418         MLXSW_REG(rdpm),
10419         MLXSW_REG(ricnt),
10420         MLXSW_REG(rrcr),
10421         MLXSW_REG(ralta),
10422         MLXSW_REG(ralst),
10423         MLXSW_REG(raltb),
10424         MLXSW_REG(ralue),
10425         MLXSW_REG(rauht),
10426         MLXSW_REG(raleu),
10427         MLXSW_REG(rauhtd),
10428         MLXSW_REG(rigr2),
10429         MLXSW_REG(recr2),
10430         MLXSW_REG(rmft2),
10431         MLXSW_REG(mfcr),
10432         MLXSW_REG(mfsc),
10433         MLXSW_REG(mfsm),
10434         MLXSW_REG(mfsl),
10435         MLXSW_REG(fore),
10436         MLXSW_REG(mtcap),
10437         MLXSW_REG(mtmp),
10438         MLXSW_REG(mtbr),
10439         MLXSW_REG(mcia),
10440         MLXSW_REG(mpat),
10441         MLXSW_REG(mpar),
10442         MLXSW_REG(mgir),
10443         MLXSW_REG(mrsr),
10444         MLXSW_REG(mlcr),
10445         MLXSW_REG(mtpps),
10446         MLXSW_REG(mtutc),
10447         MLXSW_REG(mpsc),
10448         MLXSW_REG(mcqi),
10449         MLXSW_REG(mcc),
10450         MLXSW_REG(mcda),
10451         MLXSW_REG(mgpc),
10452         MLXSW_REG(mprs),
10453         MLXSW_REG(mogcr),
10454         MLXSW_REG(mtpppc),
10455         MLXSW_REG(mtpptr),
10456         MLXSW_REG(mtptpt),
10457         MLXSW_REG(mgpir),
10458         MLXSW_REG(tngcr),
10459         MLXSW_REG(tnumt),
10460         MLXSW_REG(tnqcr),
10461         MLXSW_REG(tnqdr),
10462         MLXSW_REG(tneem),
10463         MLXSW_REG(tndem),
10464         MLXSW_REG(tnpc),
10465         MLXSW_REG(tigcr),
10466         MLXSW_REG(sbpr),
10467         MLXSW_REG(sbcm),
10468         MLXSW_REG(sbpm),
10469         MLXSW_REG(sbmm),
10470         MLXSW_REG(sbsr),
10471         MLXSW_REG(sbib),
10472 };
10473
10474 static inline const char *mlxsw_reg_id_str(u16 reg_id)
10475 {
10476         const struct mlxsw_reg_info *reg_info;
10477         int i;
10478
10479         for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
10480                 reg_info = mlxsw_reg_infos[i];
10481                 if (reg_info->id == reg_id)
10482                         return reg_info->name;
10483         }
10484         return "*UNKNOWN*";
10485 }
10486
10487 /* PUDE - Port Up / Down Event
10488  * ---------------------------
10489  * Reports the operational state change of a port.
10490  */
10491 #define MLXSW_REG_PUDE_LEN 0x10
10492
10493 /* reg_pude_swid
10494  * Switch partition ID with which to associate the port.
10495  * Access: Index
10496  */
10497 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
10498
10499 /* reg_pude_local_port
10500  * Local port number.
10501  * Access: Index
10502  */
10503 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
10504
10505 /* reg_pude_admin_status
10506  * Port administrative state (the desired state).
10507  * 1 - Up.
10508  * 2 - Down.
10509  * 3 - Up once. This means that in case of link failure, the port won't go
10510  *     into polling mode, but will wait to be re-enabled by software.
10511  * 4 - Disabled by system. Can only be set by hardware.
10512  * Access: RO
10513  */
10514 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
10515
10516 /* reg_pude_oper_status
10517  * Port operatioanl state.
10518  * 1 - Up.
10519  * 2 - Down.
10520  * 3 - Down by port failure. This means that the device will not let the
10521  *     port up again until explicitly specified by software.
10522  * Access: RO
10523  */
10524 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
10525
10526 #endif