drivers/net/ethernet/mellanox/mlxsw/reg.h

   1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3
   4 #ifndef _MLXSW_REG_H
   5 #define _MLXSW_REG_H
   6
   7 #include <linux/kernel.h>
   8 #include <linux/string.h>
   9 #include <linux/bitops.h>
  10 #include <linux/if_vlan.h>
  11
  12 #include "item.h"
  13 #include "port.h"
  14
  15 struct mlxsw_reg_info {
  16         u16 id;
  17         u16 len; /* In u8 */
  18         const char *name;
  19 };
  20
  21 #define MLXSW_REG_DEFINE(_name, _id, _len)                              \
  22 static const struct mlxsw_reg_info mlxsw_reg_##_name = {                \
  23         .id = _id,                                                      \
  24         .len = _len,                                                    \
  25         .name = #_name,                                                 \
  26 }
  27
  28 #define MLXSW_REG(type) (&mlxsw_reg_##type)
  29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
  30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
  31
  32 /* SGCR - Switch General Configuration Register
  33  * --------------------------------------------
  34  * This register is used for configuration of the switch capabilities.
  35  */
  36 #define MLXSW_REG_SGCR_ID 0x2000
  37 #define MLXSW_REG_SGCR_LEN 0x10
  38
  39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
  40
  41 /* reg_sgcr_llb
  42  * Link Local Broadcast (Default=0)
  43  * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
  44  * packets and ignore the IGMP snooping entries.
  45  * Access: RW
  46  */
  47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
  48
  49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
  50 {
  51         MLXSW_REG_ZERO(sgcr, payload);
  52         mlxsw_reg_sgcr_llb_set(payload, !!llb);
  53 }
  54
  55 /* SPAD - Switch Physical Address Register
  56  * ---------------------------------------
  57  * The SPAD register configures the switch physical MAC address.
  58  */
  59 #define MLXSW_REG_SPAD_ID 0x2002
  60 #define MLXSW_REG_SPAD_LEN 0x10
  61
  62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
  63
  64 /* reg_spad_base_mac
  65  * Base MAC address for the switch partitions.
  66  * Per switch partition MAC address is equal to:
  67  * base_mac + swid
  68  * Access: RW
  69  */
  70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
  71
  72 /* SMID - Switch Multicast ID
  73  * --------------------------
  74  * The MID record maps from a MID (Multicast ID), which is a unique identifier
  75  * of the multicast group within the stacking domain, into a list of local
  76  * ports into which the packet is replicated.
  77  */
  78 #define MLXSW_REG_SMID_ID 0x2007
  79 #define MLXSW_REG_SMID_LEN 0x240
  80
  81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);
  82
  83 /* reg_smid_swid
  84  * Switch partition ID.
  85  * Access: Index
  86  */
  87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
  88
  89 /* reg_smid_mid
  90  * Multicast identifier - global identifier that represents the multicast group
  91  * across all devices.
  92  * Access: Index
  93  */
  94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
  95
  96 /* reg_smid_port
  97  * Local port memebership (1 bit per port).
  98  * Access: RW
  99  */
 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
 101
 102 /* reg_smid_port_mask
 103  * Local port mask (1 bit per port).
 104  * Access: W
 105  */
 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
 107
 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
 109                                        u8 port, bool set)
 110 {
 111         MLXSW_REG_ZERO(smid, payload);
 112         mlxsw_reg_smid_swid_set(payload, 0);
 113         mlxsw_reg_smid_mid_set(payload, mid);
 114         mlxsw_reg_smid_port_set(payload, port, set);
 115         mlxsw_reg_smid_port_mask_set(payload, port, 1);
 116 }
 117
 118 /* SSPR - Switch System Port Record Register
 119  * -----------------------------------------
 120  * Configures the system port to local port mapping.
 121  */
 122 #define MLXSW_REG_SSPR_ID 0x2008
 123 #define MLXSW_REG_SSPR_LEN 0x8
 124
 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
 126
 127 /* reg_sspr_m
 128  * Master - if set, then the record describes the master system port.
 129  * This is needed in case a local port is mapped into several system ports
 130  * (for multipathing). That number will be reported as the source system
 131  * port when packets are forwarded to the CPU. Only one master port is allowed
 132  * per local port.
 133  *
 134  * Note: Must be set for Spectrum.
 135  * Access: RW
 136  */
 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
 138
 139 /* reg_sspr_local_port
 140  * Local port number.
 141  *
 142  * Access: RW
 143  */
 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
 145
 146 /* reg_sspr_sub_port
 147  * Virtual port within the physical port.
 148  * Should be set to 0 when virtual ports are not enabled on the port.
 149  *
 150  * Access: RW
 151  */
 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
 153
 154 /* reg_sspr_system_port
 155  * Unique identifier within the stacking domain that represents all the ports
 156  * that are available in the system (external ports).
 157  *
 158  * Currently, only single-ASIC configurations are supported, so we default to
 159  * 1:1 mapping between system ports and local ports.
 160  * Access: Index
 161  */
 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
 163
 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
 165 {
 166         MLXSW_REG_ZERO(sspr, payload);
 167         mlxsw_reg_sspr_m_set(payload, 1);
 168         mlxsw_reg_sspr_local_port_set(payload, local_port);
 169         mlxsw_reg_sspr_sub_port_set(payload, 0);
 170         mlxsw_reg_sspr_system_port_set(payload, local_port);
 171 }
 172
 173 /* SFDAT - Switch Filtering Database Aging Time
 174  * --------------------------------------------
 175  * Controls the Switch aging time. Aging time is able to be set per Switch
 176  * Partition.
 177  */
 178 #define MLXSW_REG_SFDAT_ID 0x2009
 179 #define MLXSW_REG_SFDAT_LEN 0x8
 180
 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
 182
 183 /* reg_sfdat_swid
 184  * Switch partition ID.
 185  * Access: Index
 186  */
 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
 188
 189 /* reg_sfdat_age_time
 190  * Aging time in seconds
 191  * Min - 10 seconds
 192  * Max - 1,000,000 seconds
 193  * Default is 300 seconds.
 194  * Access: RW
 195  */
 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
 197
 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
 199 {
 200         MLXSW_REG_ZERO(sfdat, payload);
 201         mlxsw_reg_sfdat_swid_set(payload, 0);
 202         mlxsw_reg_sfdat_age_time_set(payload, age_time);
 203 }
 204
 205 /* SFD - Switch Filtering Database
 206  * -------------------------------
 207  * The following register defines the access to the filtering database.
 208  * The register supports querying, adding, removing and modifying the database.
 209  * The access is optimized for bulk updates in which case more than one
 210  * FDB record is present in the same command.
 211  */
 212 #define MLXSW_REG_SFD_ID 0x200A
 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN +     \
 217                            MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
 218
 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
 220
 221 /* reg_sfd_swid
 222  * Switch partition ID for queries. Reserved on Write.
 223  * Access: Index
 224  */
 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
 226
 227 enum mlxsw_reg_sfd_op {
 228         /* Dump entire FDB a (process according to record_locator) */
 229         MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
 230         /* Query records by {MAC, VID/FID} value */
 231         MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
 232         /* Query and clear activity. Query records by {MAC, VID/FID} value */
 233         MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
 234         /* Test. Response indicates if each of the records could be
 235          * added to the FDB.
 236          */
 237         MLXSW_REG_SFD_OP_WRITE_TEST = 0,
 238         /* Add/modify. Aged-out records cannot be added. This command removes
 239          * the learning notification of the {MAC, VID/FID}. Response includes
 240          * the entries that were added to the FDB.
 241          */
 242         MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
 243         /* Remove record by {MAC, VID/FID}. This command also removes
 244          * the learning notification and aged-out notifications
 245          * of the {MAC, VID/FID}. The response provides current (pre-removal)
 246          * entries as non-aged-out.
 247          */
 248         MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
 249         /* Remove learned notification by {MAC, VID/FID}. The response provides
 250          * the removed learning notification.
 251          */
 252         MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
 253 };
 254
 255 /* reg_sfd_op
 256  * Operation.
 257  * Access: OP
 258  */
 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
 260
 261 /* reg_sfd_record_locator
 262  * Used for querying the FDB. Use record_locator=0 to initiate the
 263  * query. When a record is returned, a new record_locator is
 264  * returned to be used in the subsequent query.
 265  * Reserved for database update.
 266  * Access: Index
 267  */
 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
 269
 270 /* reg_sfd_num_rec
 271  * Request: Number of records to read/add/modify/remove
 272  * Response: Number of records read/added/replaced/removed
 273  * See above description for more details.
 274  * Ranges 0..64
 275  * Access: RW
 276  */
 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
 278
 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
 280                                       u32 record_locator)
 281 {
 282         MLXSW_REG_ZERO(sfd, payload);
 283         mlxsw_reg_sfd_op_set(payload, op);
 284         mlxsw_reg_sfd_record_locator_set(payload, record_locator);
 285 }
 286
 287 /* reg_sfd_rec_swid
 288  * Switch partition ID.
 289  * Access: Index
 290  */
 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
 292                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 293
 294 enum mlxsw_reg_sfd_rec_type {
 295         MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
 296         MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
 297         MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
 298         MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
 299 };
 300
 301 /* reg_sfd_rec_type
 302  * FDB record type.
 303  * Access: RW
 304  */
 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
 306                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 307
 308 enum mlxsw_reg_sfd_rec_policy {
 309         /* Replacement disabled, aging disabled. */
 310         MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
 311         /* (mlag remote): Replacement enabled, aging disabled,
 312          * learning notification enabled on this port.
 313          */
 314         MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
 315         /* (ingress device): Replacement enabled, aging enabled. */
 316         MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
 317 };
 318
 319 /* reg_sfd_rec_policy
 320  * Policy.
 321  * Access: RW
 322  */
 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
 324                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 325
 326 /* reg_sfd_rec_a
 327  * Activity. Set for new static entries. Set for static entries if a frame SMAC
 328  * lookup hits on the entry.
 329  * To clear the a bit, use "query and clear activity" op.
 330  * Access: RO
 331  */
 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
 333                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 334
 335 /* reg_sfd_rec_mac
 336  * MAC address.
 337  * Access: Index
 338  */
 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
 340                        MLXSW_REG_SFD_REC_LEN, 0x02);
 341
 342 enum mlxsw_reg_sfd_rec_action {
 343         /* forward */
 344         MLXSW_REG_SFD_REC_ACTION_NOP = 0,
 345         /* forward and trap, trap_id is FDB_TRAP */
 346         MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
 347         /* trap and do not forward, trap_id is FDB_TRAP */
 348         MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
 349         /* forward to IP router */
 350         MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
 351         MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
 352 };
 353
 354 /* reg_sfd_rec_action
 355  * Action to apply on the packet.
 356  * Note: Dynamic entries can only be configured with NOP action.
 357  * Access: RW
 358  */
 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
 360                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 361
 362 /* reg_sfd_uc_sub_port
 363  * VEPA channel on local port.
 364  * Valid only if local port is a non-stacking port. Must be 0 if multichannel
 365  * VEPA is not enabled.
 366  * Access: RW
 367  */
 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
 369                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 370
 371 /* reg_sfd_uc_fid_vid
 372  * Filtering ID or VLAN ID
 373  * For SwitchX and SwitchX-2:
 374  * - Dynamic entries (policy 2,3) use FID
 375  * - Static entries (policy 0) use VID
 376  * - When independent learning is configured, VID=FID
 377  * For Spectrum: use FID for both Dynamic and Static entries.
 378  * VID should not be used.
 379  * Access: Index
 380  */
 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 382                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 383
 384 /* reg_sfd_uc_system_port
 385  * Unique port identifier for the final destination of the packet.
 386  * Access: RW
 387  */
 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 389                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 390
 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
 392                                           enum mlxsw_reg_sfd_rec_type rec_type,
 393                                           const char *mac,
 394                                           enum mlxsw_reg_sfd_rec_action action)
 395 {
 396         u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
 397
 398         if (rec_index >= num_rec)
 399                 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
 400         mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
 401         mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
 402         mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
 403         mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
 404 }
 405
 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
 407                                          enum mlxsw_reg_sfd_rec_policy policy,
 408                                          const char *mac, u16 fid_vid,
 409                                          enum mlxsw_reg_sfd_rec_action action,
 410                                          u8 local_port)
 411 {
 412         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 413                                MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
 414         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 415         mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
 416         mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
 417         mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
 418 }
 419
 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
 421                                            char *mac, u16 *p_fid_vid,
 422                                            u8 *p_local_port)
 423 {
 424         mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
 425         *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
 426         *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
 427 }
 428
 429 /* reg_sfd_uc_lag_sub_port
 430  * LAG sub port.
 431  * Must be 0 if multichannel VEPA is not enabled.
 432  * Access: RW
 433  */
 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
 435                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 436
 437 /* reg_sfd_uc_lag_fid_vid
 438  * Filtering ID or VLAN ID
 439  * For SwitchX and SwitchX-2:
 440  * - Dynamic entries (policy 2,3) use FID
 441  * - Static entries (policy 0) use VID
 442  * - When independent learning is configured, VID=FID
 443  * For Spectrum: use FID for both Dynamic and Static entries.
 444  * VID should not be used.
 445  * Access: Index
 446  */
 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 448                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 449
 450 /* reg_sfd_uc_lag_lag_vid
 451  * Indicates VID in case of vFIDs. Reserved for FIDs.
 452  * Access: RW
 453  */
 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
 455                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 456
 457 /* reg_sfd_uc_lag_lag_id
 458  * LAG Identifier - pointer into the LAG descriptor table.
 459  * Access: RW
 460  */
 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
 462                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 463
 464 static inline void
 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
 466                           enum mlxsw_reg_sfd_rec_policy policy,
 467                           const char *mac, u16 fid_vid,
 468                           enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
 469                           u16 lag_id)
 470 {
 471         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 472                                MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
 473                                mac, action);
 474         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 475         mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
 476         mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
 477         mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
 478         mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
 479 }
 480
 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
 482                                                char *mac, u16 *p_vid,
 483                                                u16 *p_lag_id)
 484 {
 485         mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
 486         *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
 487         *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
 488 }
 489
 490 /* reg_sfd_mc_pgi
 491  *
 492  * Multicast port group index - index into the port group table.
 493  * Value 0x1FFF indicates the pgi should point to the MID entry.
 494  * For Spectrum this value must be set to 0x1FFF
 495  * Access: RW
 496  */
 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
 498                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 499
 500 /* reg_sfd_mc_fid_vid
 501  *
 502  * Filtering ID or VLAN ID
 503  * Access: Index
 504  */
 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 506                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 507
 508 /* reg_sfd_mc_mid
 509  *
 510  * Multicast identifier - global identifier that represents the multicast
 511  * group across all devices.
 512  * Access: RW
 513  */
 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 515                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 516
 517 static inline void
 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
 519                       const char *mac, u16 fid_vid,
 520                       enum mlxsw_reg_sfd_rec_action action, u16 mid)
 521 {
 522         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 523                                MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
 524         mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
 525         mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
 526         mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
 527 }
 528
 529 /* reg_sfd_uc_tunnel_uip_msb
 530  * When protocol is IPv4, the most significant byte of the underlay IPv4
 531  * destination IP.
 532  * When protocol is IPv6, reserved.
 533  * Access: RW
 534  */
 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
 536                      8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
 537
 538 /* reg_sfd_uc_tunnel_fid
 539  * Filtering ID.
 540  * Access: Index
 541  */
 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 543                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 544
 545 enum mlxsw_reg_sfd_uc_tunnel_protocol {
 546         MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
 547         MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
 548 };
 549
 550 /* reg_sfd_uc_tunnel_protocol
 551  * IP protocol.
 552  * Access: RW
 553  */
 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
 555                      1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 556
 557 /* reg_sfd_uc_tunnel_uip_lsb
 558  * When protocol is IPv4, the least significant bytes of the underlay
 559  * IPv4 destination IP.
 560  * When protocol is IPv6, pointer to the underlay IPv6 destination IP
 561  * which is configured by RIPS.
 562  * Access: RW
 563  */
 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
 565                      24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 566
 567 static inline void
 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
 569                              enum mlxsw_reg_sfd_rec_policy policy,
 570                              const char *mac, u16 fid,
 571                              enum mlxsw_reg_sfd_rec_action action, u32 uip,
 572                              enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
 573 {
 574         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 575                                MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
 576                                action);
 577         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 578         mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
 579         mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
 580         mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
 581         mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
 582 }
 583
 584 /* SFN - Switch FDB Notification Register
 585  * -------------------------------------------
 586  * The switch provides notifications on newly learned FDB entries and
 587  * aged out entries. The notifications can be polled by software.
 588  */
 589 #define MLXSW_REG_SFN_ID 0x200B
 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN +     \
 594                            MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
 595
 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
 597
 598 /* reg_sfn_swid
 599  * Switch partition ID.
 600  * Access: Index
 601  */
 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
 603
 604 /* reg_sfn_end
 605  * Forces the current session to end.
 606  * Access: OP
 607  */
 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
 609
 610 /* reg_sfn_num_rec
 611  * Request: Number of learned notifications and aged-out notification
 612  * records requested.
 613  * Response: Number of notification records returned (must be smaller
 614  * than or equal to the value requested)
 615  * Ranges 0..64
 616  * Access: OP
 617  */
 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
 619
 620 static inline void mlxsw_reg_sfn_pack(char *payload)
 621 {
 622         MLXSW_REG_ZERO(sfn, payload);
 623         mlxsw_reg_sfn_swid_set(payload, 0);
 624         mlxsw_reg_sfn_end_set(payload, 1);
 625         mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
 626 }
 627
 628 /* reg_sfn_rec_swid
 629  * Switch partition ID.
 630  * Access: RO
 631  */
 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
 633                      MLXSW_REG_SFN_REC_LEN, 0x00, false);
 634
 635 enum mlxsw_reg_sfn_rec_type {
 636         /* MAC addresses learned on a regular port. */
 637         MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
 638         /* MAC addresses learned on a LAG port. */
 639         MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
 640         /* Aged-out MAC address on a regular port. */
 641         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
 642         /* Aged-out MAC address on a LAG port. */
 643         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
 644         /* Learned unicast tunnel record. */
 645         MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
 646         /* Aged-out unicast tunnel record. */
 647         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
 648 };
 649
 650 /* reg_sfn_rec_type
 651  * Notification record type.
 652  * Access: RO
 653  */
 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
 655                      MLXSW_REG_SFN_REC_LEN, 0x00, false);
 656
 657 /* reg_sfn_rec_mac
 658  * MAC address.
 659  * Access: RO
 660  */
 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
 662                        MLXSW_REG_SFN_REC_LEN, 0x02);
 663
 664 /* reg_sfn_mac_sub_port
 665  * VEPA channel on the local port.
 666  * 0 if multichannel VEPA is not enabled.
 667  * Access: RO
 668  */
 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
 670                      MLXSW_REG_SFN_REC_LEN, 0x08, false);
 671
 672 /* reg_sfn_mac_fid
 673  * Filtering identifier.
 674  * Access: RO
 675  */
 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
 677                      MLXSW_REG_SFN_REC_LEN, 0x08, false);
 678
 679 /* reg_sfn_mac_system_port
 680  * Unique port identifier for the final destination of the packet.
 681  * Access: RO
 682  */
 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
 684                      MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 685
 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
 687                                             char *mac, u16 *p_vid,
 688                                             u8 *p_local_port)
 689 {
 690         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 691         *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 692         *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
 693 }
 694
 695 /* reg_sfn_mac_lag_lag_id
 696  * LAG ID (pointer into the LAG descriptor table).
 697  * Access: RO
 698  */
 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
 700                      MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 701
 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
 703                                                 char *mac, u16 *p_vid,
 704                                                 u16 *p_lag_id)
 705 {
 706         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 707         *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 708         *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
 709 }
 710
 711 /* reg_sfn_uc_tunnel_uip_msb
 712  * When protocol is IPv4, the most significant byte of the underlay IPv4
 713  * address of the remote VTEP.
 714  * When protocol is IPv6, reserved.
 715  * Access: RO
 716  */
 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
 718                      8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
 719
 720 enum mlxsw_reg_sfn_uc_tunnel_protocol {
 721         MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
 722         MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
 723 };
 724
 725 /* reg_sfn_uc_tunnel_protocol
 726  * IP protocol.
 727  * Access: RO
 728  */
 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
 730                      1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 731
 732 /* reg_sfn_uc_tunnel_uip_lsb
 733  * When protocol is IPv4, the least significant bytes of the underlay
 734  * IPv4 address of the remote VTEP.
 735  * When protocol is IPv6, ipv6_id to be queried from TNIPSD.
 736  * Access: RO
 737  */
 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
 739                      24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 740
 741 enum mlxsw_reg_sfn_tunnel_port {
 742         MLXSW_REG_SFN_TUNNEL_PORT_NVE,
 743         MLXSW_REG_SFN_TUNNEL_PORT_VPLS,
 744         MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0,
 745         MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1,
 746 };
 747
 748 /* reg_sfn_uc_tunnel_port
 749  * Tunnel port.
 750  * Reserved on Spectrum.
 751  * Access: RO
 752  */
 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
 754                      MLXSW_REG_SFN_REC_LEN, 0x10, false);
 755
 756 static inline void
 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
 758                                u16 *p_fid, u32 *p_uip,
 759                                enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
 760 {
 761         u32 uip_msb, uip_lsb;
 762
 763         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 764         *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 765         uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
 766         uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
 767         *p_uip = uip_msb << 24 | uip_lsb;
 768         *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
 769 }
 770
 771 /* SPMS - Switch Port MSTP/RSTP State Register
 772  * -------------------------------------------
 773  * Configures the spanning tree state of a physical port.
 774  */
 775 #define MLXSW_REG_SPMS_ID 0x200D
 776 #define MLXSW_REG_SPMS_LEN 0x404
 777
 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
 779
 780 /* reg_spms_local_port
 781  * Local port number.
 782  * Access: Index
 783  */
 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
 785
 786 enum mlxsw_reg_spms_state {
 787         MLXSW_REG_SPMS_STATE_NO_CHANGE,
 788         MLXSW_REG_SPMS_STATE_DISCARDING,
 789         MLXSW_REG_SPMS_STATE_LEARNING,
 790         MLXSW_REG_SPMS_STATE_FORWARDING,
 791 };
 792
 793 /* reg_spms_state
 794  * Spanning tree state of each VLAN ID (VID) of the local port.
 795  * 0 - Do not change spanning tree state (used only when writing).
 796  * 1 - Discarding. No learning or forwarding to/from this port (default).
 797  * 2 - Learning. Port is learning, but not forwarding.
 798  * 3 - Forwarding. Port is learning and forwarding.
 799  * Access: RW
 800  */
 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
 802
 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
 804 {
 805         MLXSW_REG_ZERO(spms, payload);
 806         mlxsw_reg_spms_local_port_set(payload, local_port);
 807 }
 808
 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
 810                                            enum mlxsw_reg_spms_state state)
 811 {
 812         mlxsw_reg_spms_state_set(payload, vid, state);
 813 }
 814
 815 /* SPVID - Switch Port VID
 816  * -----------------------
 817  * The switch port VID configures the default VID for a port.
 818  */
 819 #define MLXSW_REG_SPVID_ID 0x200E
 820 #define MLXSW_REG_SPVID_LEN 0x08
 821
 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
 823
 824 /* reg_spvid_local_port
 825  * Local port number.
 826  * Access: Index
 827  */
 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
 829
 830 /* reg_spvid_sub_port
 831  * Virtual port within the physical port.
 832  * Should be set to 0 when virtual ports are not enabled on the port.
 833  * Access: Index
 834  */
 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
 836
 837 /* reg_spvid_pvid
 838  * Port default VID
 839  * Access: RW
 840  */
 841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
 842
 843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
 844 {
 845         MLXSW_REG_ZERO(spvid, payload);
 846         mlxsw_reg_spvid_local_port_set(payload, local_port);
 847         mlxsw_reg_spvid_pvid_set(payload, pvid);
 848 }
 849
 850 /* SPVM - Switch Port VLAN Membership
 851  * ----------------------------------
 852  * The Switch Port VLAN Membership register configures the VLAN membership
 853  * of a port in a VLAN denoted by VID. VLAN membership is managed per
 854  * virtual port. The register can be used to add and remove VID(s) from a port.
 855  */
 856 #define MLXSW_REG_SPVM_ID 0x200F
 857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
 858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
 859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255
 860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN +   \
 861                     MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
 862
 863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
 864
 865 /* reg_spvm_pt
 866  * Priority tagged. If this bit is set, packets forwarded to the port with
 867  * untagged VLAN membership (u bit is set) will be tagged with priority tag
 868  * (VID=0)
 869  * Access: RW
 870  */
 871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
 872
 873 /* reg_spvm_pte
 874  * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
 875  * the pt bit will NOT be updated. To update the pt bit, pte must be set.
 876  * Access: WO
 877  */
 878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
 879
 880 /* reg_spvm_local_port
 881  * Local port number.
 882  * Access: Index
 883  */
 884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
 885
 886 /* reg_spvm_sub_port
 887  * Virtual port within the physical port.
 888  * Should be set to 0 when virtual ports are not enabled on the port.
 889  * Access: Index
 890  */
 891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
 892
 893 /* reg_spvm_num_rec
 894  * Number of records to update. Each record contains: i, e, u, vid.
 895  * Access: OP
 896  */
 897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
 898
 899 /* reg_spvm_rec_i
 900  * Ingress membership in VLAN ID.
 901  * Access: Index
 902  */
 903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
 904                      MLXSW_REG_SPVM_BASE_LEN, 14, 1,
 905                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 906
 907 /* reg_spvm_rec_e
 908  * Egress membership in VLAN ID.
 909  * Access: Index
 910  */
 911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
 912                      MLXSW_REG_SPVM_BASE_LEN, 13, 1,
 913                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 914
 915 /* reg_spvm_rec_u
 916  * Untagged - port is an untagged member - egress transmission uses untagged
 917  * frames on VID<n>
 918  * Access: Index
 919  */
 920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
 921                      MLXSW_REG_SPVM_BASE_LEN, 12, 1,
 922                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 923
 924 /* reg_spvm_rec_vid
 925  * Egress membership in VLAN ID.
 926  * Access: Index
 927  */
 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
 929                      MLXSW_REG_SPVM_BASE_LEN, 0, 12,
 930                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 931
 932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
 933                                        u16 vid_begin, u16 vid_end,
 934                                        bool is_member, bool untagged)
 935 {
 936         int size = vid_end - vid_begin + 1;
 937         int i;
 938
 939         MLXSW_REG_ZERO(spvm, payload);
 940         mlxsw_reg_spvm_local_port_set(payload, local_port);
 941         mlxsw_reg_spvm_num_rec_set(payload, size);
 942
 943         for (i = 0; i < size; i++) {
 944                 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
 945                 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
 946                 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
 947                 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
 948         }
 949 }
 950
 951 /* SPAFT - Switch Port Acceptable Frame Types
 952  * ------------------------------------------
 953  * The Switch Port Acceptable Frame Types register configures the frame
 954  * admittance of the port.
 955  */
 956 #define MLXSW_REG_SPAFT_ID 0x2010
 957 #define MLXSW_REG_SPAFT_LEN 0x08
 958
 959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
 960
 961 /* reg_spaft_local_port
 962  * Local port number.
 963  * Access: Index
 964  *
 965  * Note: CPU port is not supported (all tag types are allowed).
 966  */
 967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
 968
 969 /* reg_spaft_sub_port
 970  * Virtual port within the physical port.
 971  * Should be set to 0 when virtual ports are not enabled on the port.
 972  * Access: RW
 973  */
 974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
 975
 976 /* reg_spaft_allow_untagged
 977  * When set, untagged frames on the ingress are allowed (default).
 978  * Access: RW
 979  */
 980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
 981
 982 /* reg_spaft_allow_prio_tagged
 983  * When set, priority tagged frames on the ingress are allowed (default).
 984  * Access: RW
 985  */
 986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
 987
 988 /* reg_spaft_allow_tagged
 989  * When set, tagged frames on the ingress are allowed (default).
 990  * Access: RW
 991  */
 992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
 993
 994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
 995                                         bool allow_untagged)
 996 {
 997         MLXSW_REG_ZERO(spaft, payload);
 998         mlxsw_reg_spaft_local_port_set(payload, local_port);
 999         mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
1000         mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
1001         mlxsw_reg_spaft_allow_tagged_set(payload, true);
1002 }
1003
1004 /* SFGC - Switch Flooding Group Configuration
1005  * ------------------------------------------
1006  * The following register controls the association of flooding tables and MIDs
1007  * to packet types used for flooding.
1008  */
1009 #define MLXSW_REG_SFGC_ID 0x2011
1010 #define MLXSW_REG_SFGC_LEN 0x10
1011
1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1013
1014 enum mlxsw_reg_sfgc_type {
1015         MLXSW_REG_SFGC_TYPE_BROADCAST,
1016         MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1017         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1018         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1019         MLXSW_REG_SFGC_TYPE_RESERVED,
1020         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1021         MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1022         MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1023         MLXSW_REG_SFGC_TYPE_MAX,
1024 };
1025
1026 /* reg_sfgc_type
1027  * The traffic type to reach the flooding table.
1028  * Access: Index
1029  */
1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1031
1032 enum mlxsw_reg_sfgc_bridge_type {
1033         MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
1034         MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
1035 };
1036
1037 /* reg_sfgc_bridge_type
1038  * Access: Index
1039  *
1040  * Note: SwitchX-2 only supports 802.1Q mode.
1041  */
1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1043
1044 enum mlxsw_flood_table_type {
1045         MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1046         MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1047         MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1048         MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1049         MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1050 };
1051
1052 /* reg_sfgc_table_type
1053  * See mlxsw_flood_table_type
1054  * Access: RW
1055  *
1056  * Note: FID offset and FID types are not supported in SwitchX-2.
1057  */
1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1059
1060 /* reg_sfgc_flood_table
1061  * Flooding table index to associate with the specific type on the specific
1062  * switch partition.
1063  * Access: RW
1064  */
1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1066
1067 /* reg_sfgc_mid
1068  * The multicast ID for the swid. Not supported for Spectrum
1069  * Access: RW
1070  */
1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1072
1073 /* reg_sfgc_counter_set_type
1074  * Counter Set Type for flow counters.
1075  * Access: RW
1076  */
1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1078
1079 /* reg_sfgc_counter_index
1080  * Counter Index for flow counters.
1081  * Access: RW
1082  */
1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1084
1085 static inline void
1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1087                     enum mlxsw_reg_sfgc_bridge_type bridge_type,
1088                     enum mlxsw_flood_table_type table_type,
1089                     unsigned int flood_table)
1090 {
1091         MLXSW_REG_ZERO(sfgc, payload);
1092         mlxsw_reg_sfgc_type_set(payload, type);
1093         mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1094         mlxsw_reg_sfgc_table_type_set(payload, table_type);
1095         mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1096         mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1097 }
1098
1099 /* SFTR - Switch Flooding Table Register
1100  * -------------------------------------
1101  * The switch flooding table is used for flooding packet replication. The table
1102  * defines a bit mask of ports for packet replication.
1103  */
1104 #define MLXSW_REG_SFTR_ID 0x2012
1105 #define MLXSW_REG_SFTR_LEN 0x420
1106
1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN);
1108
1109 /* reg_sftr_swid
1110  * Switch partition ID with which to associate the port.
1111  * Access: Index
1112  */
1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1114
1115 /* reg_sftr_flood_table
1116  * Flooding table index to associate with the specific type on the specific
1117  * switch partition.
1118  * Access: Index
1119  */
1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1121
1122 /* reg_sftr_index
1123  * Index. Used as an index into the Flooding Table in case the table is
1124  * configured to use VID / FID or FID Offset.
1125  * Access: Index
1126  */
1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1128
1129 /* reg_sftr_table_type
1130  * See mlxsw_flood_table_type
1131  * Access: RW
1132  */
1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1134
1135 /* reg_sftr_range
1136  * Range of entries to update
1137  * Access: Index
1138  */
1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1140
1141 /* reg_sftr_port
1142  * Local port membership (1 bit per port).
1143  * Access: RW
1144  */
1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1146
1147 /* reg_sftr_cpu_port_mask
1148  * CPU port mask (1 bit per port).
1149  * Access: W
1150  */
1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1152
1153 static inline void mlxsw_reg_sftr_pack(char *payload,
1154                                        unsigned int flood_table,
1155                                        unsigned int index,
1156                                        enum mlxsw_flood_table_type table_type,
1157                                        unsigned int range, u8 port, bool set)
1158 {
1159         MLXSW_REG_ZERO(sftr, payload);
1160         mlxsw_reg_sftr_swid_set(payload, 0);
1161         mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1162         mlxsw_reg_sftr_index_set(payload, index);
1163         mlxsw_reg_sftr_table_type_set(payload, table_type);
1164         mlxsw_reg_sftr_range_set(payload, range);
1165         mlxsw_reg_sftr_port_set(payload, port, set);
1166         mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1167 }
1168
1169 /* SFDF - Switch Filtering DB Flush
1170  * --------------------------------
1171  * The switch filtering DB flush register is used to flush the FDB.
1172  * Note that FDB notifications are flushed as well.
1173  */
1174 #define MLXSW_REG_SFDF_ID 0x2013
1175 #define MLXSW_REG_SFDF_LEN 0x14
1176
1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1178
1179 /* reg_sfdf_swid
1180  * Switch partition ID.
1181  * Access: Index
1182  */
1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1184
1185 enum mlxsw_reg_sfdf_flush_type {
1186         MLXSW_REG_SFDF_FLUSH_PER_SWID,
1187         MLXSW_REG_SFDF_FLUSH_PER_FID,
1188         MLXSW_REG_SFDF_FLUSH_PER_PORT,
1189         MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1190         MLXSW_REG_SFDF_FLUSH_PER_LAG,
1191         MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1192         MLXSW_REG_SFDF_FLUSH_PER_NVE,
1193         MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1194 };
1195
1196 /* reg_sfdf_flush_type
1197  * Flush type.
1198  * 0 - All SWID dynamic entries are flushed.
1199  * 1 - All FID dynamic entries are flushed.
1200  * 2 - All dynamic entries pointing to port are flushed.
1201  * 3 - All FID dynamic entries pointing to port are flushed.
1202  * 4 - All dynamic entries pointing to LAG are flushed.
1203  * 5 - All FID dynamic entries pointing to LAG are flushed.
1204  * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1205  *     flushed.
1206  * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1207  *     flushed, per FID.
1208  * Access: RW
1209  */
1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1211
1212 /* reg_sfdf_flush_static
1213  * Static.
1214  * 0 - Flush only dynamic entries.
1215  * 1 - Flush both dynamic and static entries.
1216  * Access: RW
1217  */
1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1219
1220 static inline void mlxsw_reg_sfdf_pack(char *payload,
1221                                        enum mlxsw_reg_sfdf_flush_type type)
1222 {
1223         MLXSW_REG_ZERO(sfdf, payload);
1224         mlxsw_reg_sfdf_flush_type_set(payload, type);
1225         mlxsw_reg_sfdf_flush_static_set(payload, true);
1226 }
1227
1228 /* reg_sfdf_fid
1229  * FID to flush.
1230  * Access: RW
1231  */
1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1233
1234 /* reg_sfdf_system_port
1235  * Port to flush.
1236  * Access: RW
1237  */
1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1239
1240 /* reg_sfdf_port_fid_system_port
1241  * Port to flush, pointed to by FID.
1242  * Access: RW
1243  */
1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1245
1246 /* reg_sfdf_lag_id
1247  * LAG ID to flush.
1248  * Access: RW
1249  */
1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1251
1252 /* reg_sfdf_lag_fid_lag_id
1253  * LAG ID to flush, pointed to by FID.
1254  * Access: RW
1255  */
1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1257
1258 /* SLDR - Switch LAG Descriptor Register
1259  * -----------------------------------------
1260  * The switch LAG descriptor register is populated by LAG descriptors.
1261  * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1262  * max_lag-1.
1263  */
1264 #define MLXSW_REG_SLDR_ID 0x2014
1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1266
1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1268
1269 enum mlxsw_reg_sldr_op {
1270         /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1271         MLXSW_REG_SLDR_OP_LAG_CREATE,
1272         MLXSW_REG_SLDR_OP_LAG_DESTROY,
1273         /* Ports that appear in the list have the Distributor enabled */
1274         MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1275         /* Removes ports from the disributor list */
1276         MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1277 };
1278
1279 /* reg_sldr_op
1280  * Operation.
1281  * Access: RW
1282  */
1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1284
1285 /* reg_sldr_lag_id
1286  * LAG identifier. The lag_id is the index into the LAG descriptor table.
1287  * Access: Index
1288  */
1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1290
1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1292 {
1293         MLXSW_REG_ZERO(sldr, payload);
1294         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1295         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1296 }
1297
1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1299 {
1300         MLXSW_REG_ZERO(sldr, payload);
1301         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1302         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1303 }
1304
1305 /* reg_sldr_num_ports
1306  * The number of member ports of the LAG.
1307  * Reserved for Create / Destroy operations
1308  * For Add / Remove operations - indicates the number of ports in the list.
1309  * Access: RW
1310  */
1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1312
1313 /* reg_sldr_system_port
1314  * System port.
1315  * Access: RW
1316  */
1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1318
1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1320                                                     u8 local_port)
1321 {
1322         MLXSW_REG_ZERO(sldr, payload);
1323         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1324         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1325         mlxsw_reg_sldr_num_ports_set(payload, 1);
1326         mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1327 }
1328
1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1330                                                        u8 local_port)
1331 {
1332         MLXSW_REG_ZERO(sldr, payload);
1333         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1334         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1335         mlxsw_reg_sldr_num_ports_set(payload, 1);
1336         mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1337 }
1338
1339 /* SLCR - Switch LAG Configuration 2 Register
1340  * -------------------------------------------
1341  * The Switch LAG Configuration register is used for configuring the
1342  * LAG properties of the switch.
1343  */
1344 #define MLXSW_REG_SLCR_ID 0x2015
1345 #define MLXSW_REG_SLCR_LEN 0x10
1346
1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1348
1349 enum mlxsw_reg_slcr_pp {
1350         /* Global Configuration (for all ports) */
1351         MLXSW_REG_SLCR_PP_GLOBAL,
1352         /* Per port configuration, based on local_port field */
1353         MLXSW_REG_SLCR_PP_PER_PORT,
1354 };
1355
1356 /* reg_slcr_pp
1357  * Per Port Configuration
1358  * Note: Reading at Global mode results in reading port 1 configuration.
1359  * Access: Index
1360  */
1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1362
1363 /* reg_slcr_local_port
1364  * Local port number
1365  * Supported from CPU port
1366  * Not supported from router port
1367  * Reserved when pp = Global Configuration
1368  * Access: Index
1369  */
1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1371
1372 enum mlxsw_reg_slcr_type {
1373         MLXSW_REG_SLCR_TYPE_CRC, /* default */
1374         MLXSW_REG_SLCR_TYPE_XOR,
1375         MLXSW_REG_SLCR_TYPE_RANDOM,
1376 };
1377
1378 /* reg_slcr_type
1379  * Hash type
1380  * Access: RW
1381  */
1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1383
1384 /* Ingress port */
1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT         BIT(0)
1386 /* SMAC - for IPv4 and IPv6 packets */
1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP         BIT(1)
1388 /* SMAC - for non-IP packets */
1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP      BIT(2)
1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1391         (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1392          MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1393 /* DMAC - for IPv4 and IPv6 packets */
1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP         BIT(3)
1395 /* DMAC - for non-IP packets */
1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP      BIT(4)
1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1398         (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1399          MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1400 /* Ethertype - for IPv4 and IPv6 packets */
1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP    BIT(5)
1402 /* Ethertype - for non-IP packets */
1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1405         (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1406          MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1407 /* VLAN ID - for IPv4 and IPv6 packets */
1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP       BIT(7)
1409 /* VLAN ID - for non-IP packets */
1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP    BIT(8)
1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1412         (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1413          MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1414 /* Source IP address (can be IPv4 or IPv6) */
1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP             BIT(9)
1416 /* Destination IP address (can be IPv4 or IPv6) */
1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP             BIT(10)
1418 /* TCP/UDP source port */
1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT           BIT(11)
1420 /* TCP/UDP destination port*/
1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT           BIT(12)
1422 /* IPv4 Protocol/IPv6 Next Header */
1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO         BIT(13)
1424 /* IPv6 Flow label */
1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL       BIT(14)
1426 /* SID - FCoE source ID */
1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID        BIT(15)
1428 /* DID - FCoE destination ID */
1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID        BIT(16)
1430 /* OXID - FCoE originator exchange ID */
1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID       BIT(17)
1432 /* Destination QP number - for RoCE packets */
1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP        BIT(19)
1434
1435 /* reg_slcr_lag_hash
1436  * LAG hashing configuration. This is a bitmask, in which each set
1437  * bit includes the corresponding item in the LAG hash calculation.
1438  * The default lag_hash contains SMAC, DMAC, VLANID and
1439  * Ethertype (for all packet types).
1440  * Access: RW
1441  */
1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1443
1444 /* reg_slcr_seed
1445  * LAG seed value. The seed is the same for all ports.
1446  * Access: RW
1447  */
1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1449
1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1451 {
1452         MLXSW_REG_ZERO(slcr, payload);
1453         mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1454         mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1455         mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1456         mlxsw_reg_slcr_seed_set(payload, seed);
1457 }
1458
1459 /* SLCOR - Switch LAG Collector Register
1460  * -------------------------------------
1461  * The Switch LAG Collector register controls the Local Port membership
1462  * in a LAG and enablement of the collector.
1463  */
1464 #define MLXSW_REG_SLCOR_ID 0x2016
1465 #define MLXSW_REG_SLCOR_LEN 0x10
1466
1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1468
1469 enum mlxsw_reg_slcor_col {
1470         /* Port is added with collector disabled */
1471         MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1472         MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1473         MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1474         MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1475 };
1476
1477 /* reg_slcor_col
1478  * Collector configuration
1479  * Access: RW
1480  */
1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1482
1483 /* reg_slcor_local_port
1484  * Local port number
1485  * Not supported for CPU port
1486  * Access: Index
1487  */
1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1489
1490 /* reg_slcor_lag_id
1491  * LAG Identifier. Index into the LAG descriptor table.
1492  * Access: Index
1493  */
1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1495
1496 /* reg_slcor_port_index
1497  * Port index in the LAG list. Only valid on Add Port to LAG col.
1498  * Valid range is from 0 to cap_max_lag_members-1
1499  * Access: RW
1500  */
1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1502
1503 static inline void mlxsw_reg_slcor_pack(char *payload,
1504                                         u8 local_port, u16 lag_id,
1505                                         enum mlxsw_reg_slcor_col col)
1506 {
1507         MLXSW_REG_ZERO(slcor, payload);
1508         mlxsw_reg_slcor_col_set(payload, col);
1509         mlxsw_reg_slcor_local_port_set(payload, local_port);
1510         mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1511 }
1512
1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1514                                                  u8 local_port, u16 lag_id,
1515                                                  u8 port_index)
1516 {
1517         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1518                              MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1519         mlxsw_reg_slcor_port_index_set(payload, port_index);
1520 }
1521
1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1523                                                     u8 local_port, u16 lag_id)
1524 {
1525         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1526                              MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1527 }
1528
1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1530                                                    u8 local_port, u16 lag_id)
1531 {
1532         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1533                              MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1534 }
1535
1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1537                                                     u8 local_port, u16 lag_id)
1538 {
1539         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1540                              MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1541 }
1542
1543 /* SPMLR - Switch Port MAC Learning Register
1544  * -----------------------------------------
1545  * Controls the Switch MAC learning policy per port.
1546  */
1547 #define MLXSW_REG_SPMLR_ID 0x2018
1548 #define MLXSW_REG_SPMLR_LEN 0x8
1549
1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1551
1552 /* reg_spmlr_local_port
1553  * Local port number.
1554  * Access: Index
1555  */
1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1557
1558 /* reg_spmlr_sub_port
1559  * Virtual port within the physical port.
1560  * Should be set to 0 when virtual ports are not enabled on the port.
1561  * Access: Index
1562  */
1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1564
1565 enum mlxsw_reg_spmlr_learn_mode {
1566         MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1567         MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1568         MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1569 };
1570
1571 /* reg_spmlr_learn_mode
1572  * Learning mode on the port.
1573  * 0 - Learning disabled.
1574  * 2 - Learning enabled.
1575  * 3 - Security mode.
1576  *
1577  * In security mode the switch does not learn MACs on the port, but uses the
1578  * SMAC to see if it exists on another ingress port. If so, the packet is
1579  * classified as a bad packet and is discarded unless the software registers
1580  * to receive port security error packets usign HPKT.
1581  */
1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1583
1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1585                                         enum mlxsw_reg_spmlr_learn_mode mode)
1586 {
1587         MLXSW_REG_ZERO(spmlr, payload);
1588         mlxsw_reg_spmlr_local_port_set(payload, local_port);
1589         mlxsw_reg_spmlr_sub_port_set(payload, 0);
1590         mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1591 }
1592
1593 /* SVFA - Switch VID to FID Allocation Register
1594  * --------------------------------------------
1595  * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1596  * virtualized ports.
1597  */
1598 #define MLXSW_REG_SVFA_ID 0x201C
1599 #define MLXSW_REG_SVFA_LEN 0x10
1600
1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1602
1603 /* reg_svfa_swid
1604  * Switch partition ID.
1605  * Access: Index
1606  */
1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1608
1609 /* reg_svfa_local_port
1610  * Local port number.
1611  * Access: Index
1612  *
1613  * Note: Reserved for 802.1Q FIDs.
1614  */
1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1616
1617 enum mlxsw_reg_svfa_mt {
1618         MLXSW_REG_SVFA_MT_VID_TO_FID,
1619         MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1620 };
1621
1622 /* reg_svfa_mapping_table
1623  * Mapping table:
1624  * 0 - VID to FID
1625  * 1 - {Port, VID} to FID
1626  * Access: Index
1627  *
1628  * Note: Reserved for SwitchX-2.
1629  */
1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1631
1632 /* reg_svfa_v
1633  * Valid.
1634  * Valid if set.
1635  * Access: RW
1636  *
1637  * Note: Reserved for SwitchX-2.
1638  */
1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1640
1641 /* reg_svfa_fid
1642  * Filtering ID.
1643  * Access: RW
1644  */
1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1646
1647 /* reg_svfa_vid
1648  * VLAN ID.
1649  * Access: Index
1650  */
1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1652
1653 /* reg_svfa_counter_set_type
1654  * Counter set type for flow counters.
1655  * Access: RW
1656  *
1657  * Note: Reserved for SwitchX-2.
1658  */
1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1660
1661 /* reg_svfa_counter_index
1662  * Counter index for flow counters.
1663  * Access: RW
1664  *
1665  * Note: Reserved for SwitchX-2.
1666  */
1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1668
1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1670                                        enum mlxsw_reg_svfa_mt mt, bool valid,
1671                                        u16 fid, u16 vid)
1672 {
1673         MLXSW_REG_ZERO(svfa, payload);
1674         local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1675         mlxsw_reg_svfa_swid_set(payload, 0);
1676         mlxsw_reg_svfa_local_port_set(payload, local_port);
1677         mlxsw_reg_svfa_mapping_table_set(payload, mt);
1678         mlxsw_reg_svfa_v_set(payload, valid);
1679         mlxsw_reg_svfa_fid_set(payload, fid);
1680         mlxsw_reg_svfa_vid_set(payload, vid);
1681 }
1682
1683 /* SVPE - Switch Virtual-Port Enabling Register
1684  * --------------------------------------------
1685  * Enables port virtualization.
1686  */
1687 #define MLXSW_REG_SVPE_ID 0x201E
1688 #define MLXSW_REG_SVPE_LEN 0x4
1689
1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1691
1692 /* reg_svpe_local_port
1693  * Local port number
1694  * Access: Index
1695  *
1696  * Note: CPU port is not supported (uses VLAN mode only).
1697  */
1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1699
1700 /* reg_svpe_vp_en
1701  * Virtual port enable.
1702  * 0 - Disable, VLAN mode (VID to FID).
1703  * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1704  * Access: RW
1705  */
1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1707
1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1709                                        bool enable)
1710 {
1711         MLXSW_REG_ZERO(svpe, payload);
1712         mlxsw_reg_svpe_local_port_set(payload, local_port);
1713         mlxsw_reg_svpe_vp_en_set(payload, enable);
1714 }
1715
1716 /* SFMR - Switch FID Management Register
1717  * -------------------------------------
1718  * Creates and configures FIDs.
1719  */
1720 #define MLXSW_REG_SFMR_ID 0x201F
1721 #define MLXSW_REG_SFMR_LEN 0x18
1722
1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1724
1725 enum mlxsw_reg_sfmr_op {
1726         MLXSW_REG_SFMR_OP_CREATE_FID,
1727         MLXSW_REG_SFMR_OP_DESTROY_FID,
1728 };
1729
1730 /* reg_sfmr_op
1731  * Operation.
1732  * 0 - Create or edit FID.
1733  * 1 - Destroy FID.
1734  * Access: WO
1735  */
1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1737
1738 /* reg_sfmr_fid
1739  * Filtering ID.
1740  * Access: Index
1741  */
1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1743
1744 /* reg_sfmr_fid_offset
1745  * FID offset.
1746  * Used to point into the flooding table selected by SFGC register if
1747  * the table is of type FID-Offset. Otherwise, this field is reserved.
1748  * Access: RW
1749  */
1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1751
1752 /* reg_sfmr_vtfp
1753  * Valid Tunnel Flood Pointer.
1754  * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1755  * Access: RW
1756  *
1757  * Note: Reserved for 802.1Q FIDs.
1758  */
1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1760
1761 /* reg_sfmr_nve_tunnel_flood_ptr
1762  * Underlay Flooding and BC Pointer.
1763  * Used as a pointer to the first entry of the group based link lists of
1764  * flooding or BC entries (for NVE tunnels).
1765  * Access: RW
1766  */
1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1768
1769 /* reg_sfmr_vv
1770  * VNI Valid.
1771  * If not set, then vni is reserved.
1772  * Access: RW
1773  *
1774  * Note: Reserved for 802.1Q FIDs.
1775  */
1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1777
1778 /* reg_sfmr_vni
1779  * Virtual Network Identifier.
1780  * Access: RW
1781  *
1782  * Note: A given VNI can only be assigned to one FID.
1783  */
1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1785
1786 static inline void mlxsw_reg_sfmr_pack(char *payload,
1787                                        enum mlxsw_reg_sfmr_op op, u16 fid,
1788                                        u16 fid_offset)
1789 {
1790         MLXSW_REG_ZERO(sfmr, payload);
1791         mlxsw_reg_sfmr_op_set(payload, op);
1792         mlxsw_reg_sfmr_fid_set(payload, fid);
1793         mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1794         mlxsw_reg_sfmr_vtfp_set(payload, false);
1795         mlxsw_reg_sfmr_vv_set(payload, false);
1796 }
1797
1798 /* SPVMLR - Switch Port VLAN MAC Learning Register
1799  * -----------------------------------------------
1800  * Controls the switch MAC learning policy per {Port, VID}.
1801  */
1802 #define MLXSW_REG_SPVMLR_ID 0x2020
1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1807                               MLXSW_REG_SPVMLR_REC_LEN * \
1808                               MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1809
1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1811
1812 /* reg_spvmlr_local_port
1813  * Local ingress port.
1814  * Access: Index
1815  *
1816  * Note: CPU port is not supported.
1817  */
1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1819
1820 /* reg_spvmlr_num_rec
1821  * Number of records to update.
1822  * Access: OP
1823  */
1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1825
1826 /* reg_spvmlr_rec_learn_enable
1827  * 0 - Disable learning for {Port, VID}.
1828  * 1 - Enable learning for {Port, VID}.
1829  * Access: RW
1830  */
1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1832                      31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1833
1834 /* reg_spvmlr_rec_vid
1835  * VLAN ID to be added/removed from port or for querying.
1836  * Access: Index
1837  */
1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1839                      MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1840
1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1842                                          u16 vid_begin, u16 vid_end,
1843                                          bool learn_enable)
1844 {
1845         int num_rec = vid_end - vid_begin + 1;
1846         int i;
1847
1848         WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1849
1850         MLXSW_REG_ZERO(spvmlr, payload);
1851         mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1852         mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1853
1854         for (i = 0; i < num_rec; i++) {
1855                 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1856                 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1857         }
1858 }
1859
1860 /* CWTP - Congetion WRED ECN TClass Profile
1861  * ----------------------------------------
1862  * Configures the profiles for queues of egress port and traffic class
1863  */
1864 #define MLXSW_REG_CWTP_ID 0x2802
1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28
1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
1867 #define MLXSW_REG_CWTP_LEN 0x40
1868
1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
1870
1871 /* reg_cwtp_local_port
1872  * Local port number
1873  * Not supported for CPU port
1874  * Access: Index
1875  */
1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
1877
1878 /* reg_cwtp_traffic_class
1879  * Traffic Class to configure
1880  * Access: Index
1881  */
1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
1883
1884 /* reg_cwtp_profile_min
1885  * Minimum Average Queue Size of the profile in cells.
1886  * Access: RW
1887  */
1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
1889                      0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
1890
1891 /* reg_cwtp_profile_percent
1892  * Percentage of WRED and ECN marking for maximum Average Queue size
1893  * Range is 0 to 100, units of integer percentage
1894  * Access: RW
1895  */
1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
1897                      24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1898
1899 /* reg_cwtp_profile_max
1900  * Maximum Average Queue size of the profile in cells
1901  * Access: RW
1902  */
1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
1904                      0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1905
1906 #define MLXSW_REG_CWTP_MIN_VALUE 64
1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2
1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
1909
1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
1911                                        u8 traffic_class)
1912 {
1913         int i;
1914
1915         MLXSW_REG_ZERO(cwtp, payload);
1916         mlxsw_reg_cwtp_local_port_set(payload, local_port);
1917         mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
1918
1919         for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
1920                 mlxsw_reg_cwtp_profile_min_set(payload, i,
1921                                                MLXSW_REG_CWTP_MIN_VALUE);
1922                 mlxsw_reg_cwtp_profile_max_set(payload, i,
1923                                                MLXSW_REG_CWTP_MIN_VALUE);
1924         }
1925 }
1926
1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
1928
1929 static inline void
1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
1931                             u32 probability)
1932 {
1933         u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
1934
1935         mlxsw_reg_cwtp_profile_min_set(payload, index, min);
1936         mlxsw_reg_cwtp_profile_max_set(payload, index, max);
1937         mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
1938 }
1939
1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping
1941  * ---------------------------------------------------
1942  * The CWTPM register maps each egress port and traffic class to profile num.
1943  */
1944 #define MLXSW_REG_CWTPM_ID 0x2803
1945 #define MLXSW_REG_CWTPM_LEN 0x44
1946
1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
1948
1949 /* reg_cwtpm_local_port
1950  * Local port number
1951  * Not supported for CPU port
1952  * Access: Index
1953  */
1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
1955
1956 /* reg_cwtpm_traffic_class
1957  * Traffic Class to configure
1958  * Access: Index
1959  */
1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
1961
1962 /* reg_cwtpm_ew
1963  * Control enablement of WRED for traffic class:
1964  * 0 - Disable
1965  * 1 - Enable
1966  * Access: RW
1967  */
1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
1969
1970 /* reg_cwtpm_ee
1971  * Control enablement of ECN for traffic class:
1972  * 0 - Disable
1973  * 1 - Enable
1974  * Access: RW
1975  */
1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
1977
1978 /* reg_cwtpm_tcp_g
1979  * TCP Green Profile.
1980  * Index of the profile within {port, traffic class} to use.
1981  * 0 for disabling both WRED and ECN for this type of traffic.
1982  * Access: RW
1983  */
1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
1985
1986 /* reg_cwtpm_tcp_y
1987  * TCP Yellow Profile.
1988  * Index of the profile within {port, traffic class} to use.
1989  * 0 for disabling both WRED and ECN for this type of traffic.
1990  * Access: RW
1991  */
1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
1993
1994 /* reg_cwtpm_tcp_r
1995  * TCP Red Profile.
1996  * Index of the profile within {port, traffic class} to use.
1997  * 0 for disabling both WRED and ECN for this type of traffic.
1998  * Access: RW
1999  */
2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2001
2002 /* reg_cwtpm_ntcp_g
2003  * Non-TCP Green Profile.
2004  * Index of the profile within {port, traffic class} to use.
2005  * 0 for disabling both WRED and ECN for this type of traffic.
2006  * Access: RW
2007  */
2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2009
2010 /* reg_cwtpm_ntcp_y
2011  * Non-TCP Yellow Profile.
2012  * Index of the profile within {port, traffic class} to use.
2013  * 0 for disabling both WRED and ECN for this type of traffic.
2014  * Access: RW
2015  */
2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2017
2018 /* reg_cwtpm_ntcp_r
2019  * Non-TCP Red Profile.
2020  * Index of the profile within {port, traffic class} to use.
2021  * 0 for disabling both WRED and ECN for this type of traffic.
2022  * Access: RW
2023  */
2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2025
2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0
2027
2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
2029                                         u8 traffic_class, u8 profile,
2030                                         bool wred, bool ecn)
2031 {
2032         MLXSW_REG_ZERO(cwtpm, payload);
2033         mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2034         mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2035         mlxsw_reg_cwtpm_ew_set(payload, wred);
2036         mlxsw_reg_cwtpm_ee_set(payload, ecn);
2037         mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
2038         mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
2039         mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
2040         mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
2041         mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
2042         mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
2043 }
2044
2045 /* PGCR - Policy-Engine General Configuration Register
2046  * ---------------------------------------------------
2047  * This register configures general Policy-Engine settings.
2048  */
2049 #define MLXSW_REG_PGCR_ID 0x3001
2050 #define MLXSW_REG_PGCR_LEN 0x20
2051
2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2053
2054 /* reg_pgcr_default_action_pointer_base
2055  * Default action pointer base. Each region has a default action pointer
2056  * which is equal to default_action_pointer_base + region_id.
2057  * Access: RW
2058  */
2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2060
2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2062 {
2063         MLXSW_REG_ZERO(pgcr, payload);
2064         mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2065 }
2066
2067 /* PPBT - Policy-Engine Port Binding Table
2068  * ---------------------------------------
2069  * This register is used for configuration of the Port Binding Table.
2070  */
2071 #define MLXSW_REG_PPBT_ID 0x3002
2072 #define MLXSW_REG_PPBT_LEN 0x14
2073
2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2075
2076 enum mlxsw_reg_pxbt_e {
2077         MLXSW_REG_PXBT_E_IACL,
2078         MLXSW_REG_PXBT_E_EACL,
2079 };
2080
2081 /* reg_ppbt_e
2082  * Access: Index
2083  */
2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2085
2086 enum mlxsw_reg_pxbt_op {
2087         MLXSW_REG_PXBT_OP_BIND,
2088         MLXSW_REG_PXBT_OP_UNBIND,
2089 };
2090
2091 /* reg_ppbt_op
2092  * Access: RW
2093  */
2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2095
2096 /* reg_ppbt_local_port
2097  * Local port. Not including CPU port.
2098  * Access: Index
2099  */
2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8);
2101
2102 /* reg_ppbt_g
2103  * group - When set, the binding is of an ACL group. When cleared,
2104  * the binding is of an ACL.
2105  * Must be set to 1 for Spectrum.
2106  * Access: RW
2107  */
2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2109
2110 /* reg_ppbt_acl_info
2111  * ACL/ACL group identifier. If the g bit is set, this field should hold
2112  * the acl_group_id, else it should hold the acl_id.
2113  * Access: RW
2114  */
2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2116
2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2118                                        enum mlxsw_reg_pxbt_op op,
2119                                        u8 local_port, u16 acl_info)
2120 {
2121         MLXSW_REG_ZERO(ppbt, payload);
2122         mlxsw_reg_ppbt_e_set(payload, e);
2123         mlxsw_reg_ppbt_op_set(payload, op);
2124         mlxsw_reg_ppbt_local_port_set(payload, local_port);
2125         mlxsw_reg_ppbt_g_set(payload, true);
2126         mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2127 }
2128
2129 /* PACL - Policy-Engine ACL Register
2130  * ---------------------------------
2131  * This register is used for configuration of the ACL.
2132  */
2133 #define MLXSW_REG_PACL_ID 0x3004
2134 #define MLXSW_REG_PACL_LEN 0x70
2135
2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2137
2138 /* reg_pacl_v
2139  * Valid. Setting the v bit makes the ACL valid. It should not be cleared
2140  * while the ACL is bounded to either a port, VLAN or ACL rule.
2141  * Access: RW
2142  */
2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2144
2145 /* reg_pacl_acl_id
2146  * An identifier representing the ACL (managed by software)
2147  * Range 0 .. cap_max_acl_regions - 1
2148  * Access: Index
2149  */
2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2151
2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2153
2154 /* reg_pacl_tcam_region_info
2155  * Opaque object that represents a TCAM region.
2156  * Obtained through PTAR register.
2157  * Access: RW
2158  */
2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2160                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2161
2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2163                                        bool valid, const char *tcam_region_info)
2164 {
2165         MLXSW_REG_ZERO(pacl, payload);
2166         mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2167         mlxsw_reg_pacl_v_set(payload, valid);
2168         mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2169 }
2170
2171 /* PAGT - Policy-Engine ACL Group Table
2172  * ------------------------------------
2173  * This register is used for configuration of the ACL Group Table.
2174  */
2175 #define MLXSW_REG_PAGT_ID 0x3005
2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30
2177 #define MLXSW_REG_PAGT_ACL_LEN 4
2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2180                 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2181
2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2183
2184 /* reg_pagt_size
2185  * Number of ACLs in the group.
2186  * Size 0 invalidates a group.
2187  * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
2188  * Total number of ACLs in all groups must be lower or equal
2189  * to cap_max_acl_tot_groups
2190  * Note: a group which is binded must not be invalidated
2191  * Access: Index
2192  */
2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2194
2195 /* reg_pagt_acl_group_id
2196  * An identifier (numbered from 0..cap_max_acl_groups-1) representing
2197  * the ACL Group identifier (managed by software).
2198  * Access: Index
2199  */
2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2201
2202 /* reg_pagt_multi
2203  * Multi-ACL
2204  * 0 - This ACL is the last ACL in the multi-ACL
2205  * 1 - This ACL is part of a multi-ACL
2206  * Access: RW
2207  */
2208 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2209
2210 /* reg_pagt_acl_id
2211  * ACL identifier
2212  * Access: RW
2213  */
2214 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2215
2216 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2217 {
2218         MLXSW_REG_ZERO(pagt, payload);
2219         mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2220 }
2221
2222 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2223                                               u16 acl_id, bool multi)
2224 {
2225         u8 size = mlxsw_reg_pagt_size_get(payload);
2226
2227         if (index >= size)
2228                 mlxsw_reg_pagt_size_set(payload, index + 1);
2229         mlxsw_reg_pagt_multi_set(payload, index, multi);
2230         mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2231 }
2232
2233 /* PTAR - Policy-Engine TCAM Allocation Register
2234  * ---------------------------------------------
2235  * This register is used for allocation of regions in the TCAM.
2236  * Note: Query method is not supported on this register.
2237  */
2238 #define MLXSW_REG_PTAR_ID 0x3006
2239 #define MLXSW_REG_PTAR_BASE_LEN 0x20
2240 #define MLXSW_REG_PTAR_KEY_ID_LEN 1
2241 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2242 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2243                 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2244
2245 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2246
2247 enum mlxsw_reg_ptar_op {
2248         /* allocate a TCAM region */
2249         MLXSW_REG_PTAR_OP_ALLOC,
2250         /* resize a TCAM region */
2251         MLXSW_REG_PTAR_OP_RESIZE,
2252         /* deallocate TCAM region */
2253         MLXSW_REG_PTAR_OP_FREE,
2254         /* test allocation */
2255         MLXSW_REG_PTAR_OP_TEST,
2256 };
2257
2258 /* reg_ptar_op
2259  * Access: OP
2260  */
2261 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2262
2263 /* reg_ptar_action_set_type
2264  * Type of action set to be used on this region.
2265  * For Spectrum and Spectrum-2, this is always type 2 - "flexible"
2266  * Access: WO
2267  */
2268 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2269
2270 enum mlxsw_reg_ptar_key_type {
2271         MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */
2272         MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */
2273 };
2274
2275 /* reg_ptar_key_type
2276  * TCAM key type for the region.
2277  * Access: WO
2278  */
2279 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2280
2281 /* reg_ptar_region_size
2282  * TCAM region size. When allocating/resizing this is the requested size,
2283  * the response is the actual size. Note that actual size may be
2284  * larger than requested.
2285  * Allowed range 1 .. cap_max_rules-1
2286  * Reserved during op deallocate.
2287  * Access: WO
2288  */
2289 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2290
2291 /* reg_ptar_region_id
2292  * Region identifier
2293  * Range 0 .. cap_max_regions-1
2294  * Access: Index
2295  */
2296 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2297
2298 /* reg_ptar_tcam_region_info
2299  * Opaque object that represents the TCAM region.
2300  * Returned when allocating a region.
2301  * Provided by software for ACL generation and region deallocation and resize.
2302  * Access: RW
2303  */
2304 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2305                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2306
2307 /* reg_ptar_flexible_key_id
2308  * Identifier of the Flexible Key.
2309  * Only valid if key_type == "FLEX_KEY"
2310  * The key size will be rounded up to one of the following values:
2311  * 9B, 18B, 36B, 54B.
2312  * This field is reserved for in resize operation.
2313  * Access: WO
2314  */
2315 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2316                     MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2317
2318 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2319                                        enum mlxsw_reg_ptar_key_type key_type,
2320                                        u16 region_size, u16 region_id,
2321                                        const char *tcam_region_info)
2322 {
2323         MLXSW_REG_ZERO(ptar, payload);
2324         mlxsw_reg_ptar_op_set(payload, op);
2325         mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */
2326         mlxsw_reg_ptar_key_type_set(payload, key_type);
2327         mlxsw_reg_ptar_region_size_set(payload, region_size);
2328         mlxsw_reg_ptar_region_id_set(payload, region_id);
2329         mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2330 }
2331
2332 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2333                                               u16 key_id)
2334 {
2335         mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2336 }
2337
2338 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2339 {
2340         mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2341 }
2342
2343 /* PPBS - Policy-Engine Policy Based Switching Register
2344  * ----------------------------------------------------
2345  * This register retrieves and sets Policy Based Switching Table entries.
2346  */
2347 #define MLXSW_REG_PPBS_ID 0x300C
2348 #define MLXSW_REG_PPBS_LEN 0x14
2349
2350 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2351
2352 /* reg_ppbs_pbs_ptr
2353  * Index into the PBS table.
2354  * For Spectrum, the index points to the KVD Linear.
2355  * Access: Index
2356  */
2357 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2358
2359 /* reg_ppbs_system_port
2360  * Unique port identifier for the final destination of the packet.
2361  * Access: RW
2362  */
2363 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2364
2365 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2366                                        u16 system_port)
2367 {
2368         MLXSW_REG_ZERO(ppbs, payload);
2369         mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2370         mlxsw_reg_ppbs_system_port_set(payload, system_port);
2371 }
2372
2373 /* PRCR - Policy-Engine Rules Copy Register
2374  * ----------------------------------------
2375  * This register is used for accessing rules within a TCAM region.
2376  */
2377 #define MLXSW_REG_PRCR_ID 0x300D
2378 #define MLXSW_REG_PRCR_LEN 0x40
2379
2380 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2381
2382 enum mlxsw_reg_prcr_op {
2383         /* Move rules. Moves the rules from "tcam_region_info" starting
2384          * at offset "offset" to "dest_tcam_region_info"
2385          * at offset "dest_offset."
2386          */
2387         MLXSW_REG_PRCR_OP_MOVE,
2388         /* Copy rules. Copies the rules from "tcam_region_info" starting
2389          * at offset "offset" to "dest_tcam_region_info"
2390          * at offset "dest_offset."
2391          */
2392         MLXSW_REG_PRCR_OP_COPY,
2393 };
2394
2395 /* reg_prcr_op
2396  * Access: OP
2397  */
2398 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2399
2400 /* reg_prcr_offset
2401  * Offset within the source region to copy/move from.
2402  * Access: Index
2403  */
2404 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2405
2406 /* reg_prcr_size
2407  * The number of rules to copy/move.
2408  * Access: WO
2409  */
2410 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2411
2412 /* reg_prcr_tcam_region_info
2413  * Opaque object that represents the source TCAM region.
2414  * Access: Index
2415  */
2416 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2417                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2418
2419 /* reg_prcr_dest_offset
2420  * Offset within the source region to copy/move to.
2421  * Access: Index
2422  */
2423 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2424
2425 /* reg_prcr_dest_tcam_region_info
2426  * Opaque object that represents the destination TCAM region.
2427  * Access: Index
2428  */
2429 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2430                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2431
2432 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2433                                        const char *src_tcam_region_info,
2434                                        u16 src_offset,
2435                                        const char *dest_tcam_region_info,
2436                                        u16 dest_offset, u16 size)
2437 {
2438         MLXSW_REG_ZERO(prcr, payload);
2439         mlxsw_reg_prcr_op_set(payload, op);
2440         mlxsw_reg_prcr_offset_set(payload, src_offset);
2441         mlxsw_reg_prcr_size_set(payload, size);
2442         mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2443                                                   src_tcam_region_info);
2444         mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2445         mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2446                                                        dest_tcam_region_info);
2447 }
2448
2449 /* PEFA - Policy-Engine Extended Flexible Action Register
2450  * ------------------------------------------------------
2451  * This register is used for accessing an extended flexible action entry
2452  * in the central KVD Linear Database.
2453  */
2454 #define MLXSW_REG_PEFA_ID 0x300F
2455 #define MLXSW_REG_PEFA_LEN 0xB0
2456
2457 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2458
2459 /* reg_pefa_index
2460  * Index in the KVD Linear Centralized Database.
2461  * Access: Index
2462  */
2463 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2464
2465 /* reg_pefa_a
2466  * Index in the KVD Linear Centralized Database.
2467  * Activity
2468  * For a new entry: set if ca=0, clear if ca=1
2469  * Set if a packet lookup has hit on the specific entry
2470  * Access: RO
2471  */
2472 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2473
2474 /* reg_pefa_ca
2475  * Clear activity
2476  * When write: activity is according to this field
2477  * When read: after reading the activity is cleared according to ca
2478  * Access: OP
2479  */
2480 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2481
2482 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2483
2484 /* reg_pefa_flex_action_set
2485  * Action-set to perform when rule is matched.
2486  * Must be zero padded if action set is shorter.
2487  * Access: RW
2488  */
2489 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2490
2491 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2492                                        const char *flex_action_set)
2493 {
2494         MLXSW_REG_ZERO(pefa, payload);
2495         mlxsw_reg_pefa_index_set(payload, index);
2496         mlxsw_reg_pefa_ca_set(payload, ca);
2497         if (flex_action_set)
2498                 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2499                                                          flex_action_set);
2500 }
2501
2502 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2503 {
2504         *p_a = mlxsw_reg_pefa_a_get(payload);
2505 }
2506
2507 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register
2508  * --------------------------------------------------------------
2509  * This register is used for binding Multicast router to an ACL group
2510  * that serves the MC router.
2511  * This register is not supported by SwitchX/-2 and Spectrum.
2512  */
2513 #define MLXSW_REG_PEMRBT_ID 0x3014
2514 #define MLXSW_REG_PEMRBT_LEN 0x14
2515
2516 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
2517
2518 enum mlxsw_reg_pemrbt_protocol {
2519         MLXSW_REG_PEMRBT_PROTO_IPV4,
2520         MLXSW_REG_PEMRBT_PROTO_IPV6,
2521 };
2522
2523 /* reg_pemrbt_protocol
2524  * Access: Index
2525  */
2526 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
2527
2528 /* reg_pemrbt_group_id
2529  * ACL group identifier.
2530  * Range 0..cap_max_acl_groups-1
2531  * Access: RW
2532  */
2533 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
2534
2535 static inline void
2536 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
2537                       u16 group_id)
2538 {
2539         MLXSW_REG_ZERO(pemrbt, payload);
2540         mlxsw_reg_pemrbt_protocol_set(payload, protocol);
2541         mlxsw_reg_pemrbt_group_id_set(payload, group_id);
2542 }
2543
2544 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
2545  * -----------------------------------------------------
2546  * This register is used for accessing rules within a TCAM region.
2547  * It is a new version of PTCE in order to support wider key,
2548  * mask and action within a TCAM region. This register is not supported
2549  * by SwitchX and SwitchX-2.
2550  */
2551 #define MLXSW_REG_PTCE2_ID 0x3017
2552 #define MLXSW_REG_PTCE2_LEN 0x1D8
2553
2554 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2555
2556 /* reg_ptce2_v
2557  * Valid.
2558  * Access: RW
2559  */
2560 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2561
2562 /* reg_ptce2_a
2563  * Activity. Set if a packet lookup has hit on the specific entry.
2564  * To clear the "a" bit, use "clear activity" op or "clear on read" op.
2565  * Access: RO
2566  */
2567 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2568
2569 enum mlxsw_reg_ptce2_op {
2570         /* Read operation. */
2571         MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2572         /* clear on read operation. Used to read entry
2573          * and clear Activity bit.
2574          */
2575         MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2576         /* Write operation. Used to write a new entry to the table.
2577          * All R/W fields are relevant for new entry. Activity bit is set
2578          * for new entries - Note write with v = 0 will delete the entry.
2579          */
2580         MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2581         /* Update action. Only action set will be updated. */
2582         MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2583         /* Clear activity. A bit is cleared for the entry. */
2584         MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2585 };
2586
2587 /* reg_ptce2_op
2588  * Access: OP
2589  */
2590 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2591
2592 /* reg_ptce2_offset
2593  * Access: Index
2594  */
2595 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2596
2597 /* reg_ptce2_priority
2598  * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.
2599  * Note: priority does not have to be unique per rule.
2600  * Within a region, higher priority should have lower offset (no limitation
2601  * between regions in a multi-region).
2602  * Access: RW
2603  */
2604 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2605
2606 /* reg_ptce2_tcam_region_info
2607  * Opaque object that represents the TCAM region.
2608  * Access: Index
2609  */
2610 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2611                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2612
2613 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2614
2615 /* reg_ptce2_flex_key_blocks
2616  * ACL Key.
2617  * Access: RW
2618  */
2619 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2620                MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2621
2622 /* reg_ptce2_mask
2623  * mask- in the same size as key. A bit that is set directs the TCAM
2624  * to compare the corresponding bit in key. A bit that is clear directs
2625  * the TCAM to ignore the corresponding bit in key.
2626  * Access: RW
2627  */
2628 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2629                MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2630
2631 /* reg_ptce2_flex_action_set
2632  * ACL action set.
2633  * Access: RW
2634  */
2635 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2636                MLXSW_REG_FLEX_ACTION_SET_LEN);
2637
2638 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2639                                         enum mlxsw_reg_ptce2_op op,
2640                                         const char *tcam_region_info,
2641                                         u16 offset, u32 priority)
2642 {
2643         MLXSW_REG_ZERO(ptce2, payload);
2644         mlxsw_reg_ptce2_v_set(payload, valid);
2645         mlxsw_reg_ptce2_op_set(payload, op);
2646         mlxsw_reg_ptce2_offset_set(payload, offset);
2647         mlxsw_reg_ptce2_priority_set(payload, priority);
2648         mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2649 }
2650
2651 /* PERPT - Policy-Engine ERP Table Register
2652  * ----------------------------------------
2653  * This register adds and removes eRPs from the eRP table.
2654  */
2655 #define MLXSW_REG_PERPT_ID 0x3021
2656 #define MLXSW_REG_PERPT_LEN 0x80
2657
2658 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2659
2660 /* reg_perpt_erpt_bank
2661  * eRP table bank.
2662  * Range 0 .. cap_max_erp_table_banks - 1
2663  * Access: Index
2664  */
2665 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2666
2667 /* reg_perpt_erpt_index
2668  * Index to eRP table within the eRP bank.
2669  * Range is 0 .. cap_max_erp_table_bank_size - 1
2670  * Access: Index
2671  */
2672 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2673
2674 enum mlxsw_reg_perpt_key_size {
2675         MLXSW_REG_PERPT_KEY_SIZE_2KB,
2676         MLXSW_REG_PERPT_KEY_SIZE_4KB,
2677         MLXSW_REG_PERPT_KEY_SIZE_8KB,
2678         MLXSW_REG_PERPT_KEY_SIZE_12KB,
2679 };
2680
2681 /* reg_perpt_key_size
2682  * Access: OP
2683  */
2684 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2685
2686 /* reg_perpt_bf_bypass
2687  * 0 - The eRP is used only if bloom filter state is set for the given
2688  * rule.
2689  * 1 - The eRP is used regardless of bloom filter state.
2690  * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass
2691  * Access: RW
2692  */
2693 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2694
2695 /* reg_perpt_erp_id
2696  * eRP ID for use by the rules.
2697  * Access: RW
2698  */
2699 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2700
2701 /* reg_perpt_erpt_base_bank
2702  * Base eRP table bank, points to head of erp_vector
2703  * Range is 0 .. cap_max_erp_table_banks - 1
2704  * Access: OP
2705  */
2706 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2707
2708 /* reg_perpt_erpt_base_index
2709  * Base index to eRP table within the eRP bank
2710  * Range is 0 .. cap_max_erp_table_bank_size - 1
2711  * Access: OP
2712  */
2713 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2714
2715 /* reg_perpt_erp_index_in_vector
2716  * eRP index in the vector.
2717  * Access: OP
2718  */
2719 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2720
2721 /* reg_perpt_erp_vector
2722  * eRP vector.
2723  * Access: OP
2724  */
2725 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2726
2727 /* reg_perpt_mask
2728  * Mask
2729  * 0 - A-TCAM will ignore the bit in key
2730  * 1 - A-TCAM will compare the bit in key
2731  * Access: RW
2732  */
2733 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2734
2735 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
2736                                                    unsigned long *erp_vector,
2737                                                    unsigned long size)
2738 {
2739         unsigned long bit;
2740
2741         for_each_set_bit(bit, erp_vector, size)
2742                 mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
2743 }
2744
2745 static inline void
2746 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
2747                      enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
2748                      u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
2749                      char *mask)
2750 {
2751         MLXSW_REG_ZERO(perpt, payload);
2752         mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
2753         mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
2754         mlxsw_reg_perpt_key_size_set(payload, key_size);
2755         mlxsw_reg_perpt_bf_bypass_set(payload, false);
2756         mlxsw_reg_perpt_erp_id_set(payload, erp_id);
2757         mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
2758         mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
2759         mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
2760         mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
2761 }
2762
2763 /* PERAR - Policy-Engine Region Association Register
2764  * -------------------------------------------------
2765  * This register associates a hw region for region_id's. Changing on the fly
2766  * is supported by the device.
2767  */
2768 #define MLXSW_REG_PERAR_ID 0x3026
2769 #define MLXSW_REG_PERAR_LEN 0x08
2770
2771 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
2772
2773 /* reg_perar_region_id
2774  * Region identifier
2775  * Range 0 .. cap_max_regions-1
2776  * Access: Index
2777  */
2778 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
2779
2780 static inline unsigned int
2781 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
2782 {
2783         return DIV_ROUND_UP(block_num, 4);
2784 }
2785
2786 /* reg_perar_hw_region
2787  * HW Region
2788  * Range 0 .. cap_max_regions-1
2789  * Default: hw_region = region_id
2790  * For a 8 key block region, 2 consecutive regions are used
2791  * For a 12 key block region, 3 consecutive regions are used
2792  * Access: RW
2793  */
2794 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
2795
2796 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
2797                                         u16 hw_region)
2798 {
2799         MLXSW_REG_ZERO(perar, payload);
2800         mlxsw_reg_perar_region_id_set(payload, region_id);
2801         mlxsw_reg_perar_hw_region_set(payload, hw_region);
2802 }
2803
2804 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3
2805  * -----------------------------------------------------
2806  * This register is a new version of PTCE-V2 in order to support the
2807  * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
2808  */
2809 #define MLXSW_REG_PTCE3_ID 0x3027
2810 #define MLXSW_REG_PTCE3_LEN 0xF0
2811
2812 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
2813
2814 /* reg_ptce3_v
2815  * Valid.
2816  * Access: RW
2817  */
2818 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
2819
2820 enum mlxsw_reg_ptce3_op {
2821         /* Write operation. Used to write a new entry to the table.
2822          * All R/W fields are relevant for new entry. Activity bit is set
2823          * for new entries. Write with v = 0 will delete the entry. Must
2824          * not be used if an entry exists.
2825          */
2826          MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
2827          /* Update operation */
2828          MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
2829          /* Read operation */
2830          MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
2831 };
2832
2833 /* reg_ptce3_op
2834  * Access: OP
2835  */
2836 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
2837
2838 /* reg_ptce3_priority
2839  * Priority of the rule. Higher values win.
2840  * For Spectrum-2 range is 1..cap_kvd_size - 1
2841  * Note: Priority does not have to be unique per rule.
2842  * Access: RW
2843  */
2844 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
2845
2846 /* reg_ptce3_tcam_region_info
2847  * Opaque object that represents the TCAM region.
2848  * Access: Index
2849  */
2850 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
2851                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2852
2853 /* reg_ptce3_flex2_key_blocks
2854  * ACL key. The key must be masked according to eRP (if exists) or
2855  * according to master mask.
2856  * Access: Index
2857  */
2858 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
2859                MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2860
2861 /* reg_ptce3_erp_id
2862  * eRP ID.
2863  * Access: Index
2864  */
2865 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
2866
2867 /* reg_ptce3_delta_start
2868  * Start point of delta_value and delta_mask, in bits. Must not exceed
2869  * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.
2870  * Access: Index
2871  */
2872 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
2873
2874 /* reg_ptce3_delta_mask
2875  * Delta mask.
2876  * 0 - Ignore relevant bit in delta_value
2877  * 1 - Compare relevant bit in delta_value
2878  * Delta mask must not be set for reserved fields in the key blocks.
2879  * Note: No delta when no eRPs. Thus, for regions with
2880  * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.
2881  * Access: Index
2882  */
2883 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
2884
2885 /* reg_ptce3_delta_value
2886  * Delta value.
2887  * Bits which are masked by delta_mask must be 0.
2888  * Access: Index
2889  */
2890 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
2891
2892 /* reg_ptce3_prune_vector
2893  * Pruning vector relative to the PERPT.erp_id.
2894  * Used for reducing lookups.
2895  * 0 - NEED: Do a lookup using the eRP.
2896  * 1 - PRUNE: Do not perform a lookup using the eRP.
2897  * Maybe be modified by PEAPBL and PEAPBM.
2898  * Note: In Spectrum-2, a region of 8 key blocks must be set to either
2899  * all 1's or all 0's.
2900  * Access: RW
2901  */
2902 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
2903
2904 /* reg_ptce3_prune_ctcam
2905  * Pruning on C-TCAM. Used for reducing lookups.
2906  * 0 - NEED: Do a lookup in the C-TCAM.
2907  * 1 - PRUNE: Do not perform a lookup in the C-TCAM.
2908  * Access: RW
2909  */
2910 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
2911
2912 /* reg_ptce3_large_exists
2913  * Large entry key ID exists.
2914  * Within the region:
2915  * 0 - SINGLE: The large_entry_key_id is not currently in use.
2916  * For rule insert: The MSB of the key (blocks 6..11) will be added.
2917  * For rule delete: The MSB of the key will be removed.
2918  * 1 - NON_SINGLE: The large_entry_key_id is currently in use.
2919  * For rule insert: The MSB of the key (blocks 6..11) will not be added.
2920  * For rule delete: The MSB of the key will not be removed.
2921  * Access: WO
2922  */
2923 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
2924
2925 /* reg_ptce3_large_entry_key_id
2926  * Large entry key ID.
2927  * A key for 12 key blocks rules. Reserved when region has less than 12 key
2928  * blocks. Must be different for different keys which have the same common
2929  * 6 key blocks (MSB, blocks 6..11) key within a region.
2930  * Range is 0..cap_max_pe_large_key_id - 1
2931  * Access: RW
2932  */
2933 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
2934
2935 /* reg_ptce3_action_pointer
2936  * Pointer to action.
2937  * Range is 0..cap_max_kvd_action_sets - 1
2938  * Access: RW
2939  */
2940 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
2941
2942 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
2943                                         enum mlxsw_reg_ptce3_op op,
2944                                         u32 priority,
2945                                         const char *tcam_region_info,
2946                                         const char *key, u8 erp_id,
2947                                         u16 delta_start, u8 delta_mask,
2948                                         u8 delta_value, bool large_exists,
2949                                         u32 lkey_id, u32 action_pointer)
2950 {
2951         MLXSW_REG_ZERO(ptce3, payload);
2952         mlxsw_reg_ptce3_v_set(payload, valid);
2953         mlxsw_reg_ptce3_op_set(payload, op);
2954         mlxsw_reg_ptce3_priority_set(payload, priority);
2955         mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
2956         mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
2957         mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
2958         mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
2959         mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
2960         mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
2961         mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
2962         mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
2963         mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
2964 }
2965
2966 /* PERCR - Policy-Engine Region Configuration Register
2967  * ---------------------------------------------------
2968  * This register configures the region parameters. The region_id must be
2969  * allocated.
2970  */
2971 #define MLXSW_REG_PERCR_ID 0x302A
2972 #define MLXSW_REG_PERCR_LEN 0x80
2973
2974 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
2975
2976 /* reg_percr_region_id
2977  * Region identifier.
2978  * Range 0..cap_max_regions-1
2979  * Access: Index
2980  */
2981 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
2982
2983 /* reg_percr_atcam_ignore_prune
2984  * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.
2985  * Access: RW
2986  */
2987 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
2988
2989 /* reg_percr_ctcam_ignore_prune
2990  * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.
2991  * Access: RW
2992  */
2993 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
2994
2995 /* reg_percr_bf_bypass
2996  * Bloom filter bypass.
2997  * 0 - Bloom filter is used (default)
2998  * 1 - Bloom filter is bypassed. The bypass is an OR condition of
2999  * region_id or eRP. See PERPT.bf_bypass
3000  * Access: RW
3001  */
3002 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3003
3004 /* reg_percr_master_mask
3005  * Master mask. Logical OR mask of all masks of all rules of a region
3006  * (both A-TCAM and C-TCAM). When there are no eRPs
3007  * (erpt_pointer_valid = 0), then this provides the mask.
3008  * Access: RW
3009  */
3010 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3011
3012 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3013 {
3014         MLXSW_REG_ZERO(percr, payload);
3015         mlxsw_reg_percr_region_id_set(payload, region_id);
3016         mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
3017         mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
3018         mlxsw_reg_percr_bf_bypass_set(payload, false);
3019 }
3020
3021 /* PERERP - Policy-Engine Region eRP Register
3022  * ------------------------------------------
3023  * This register configures the region eRP. The region_id must be
3024  * allocated.
3025  */
3026 #define MLXSW_REG_PERERP_ID 0x302B
3027 #define MLXSW_REG_PERERP_LEN 0x1C
3028
3029 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3030
3031 /* reg_pererp_region_id
3032  * Region identifier.
3033  * Range 0..cap_max_regions-1
3034  * Access: Index
3035  */
3036 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3037
3038 /* reg_pererp_ctcam_le
3039  * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
3040  * Access: RW
3041  */
3042 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3043
3044 /* reg_pererp_erpt_pointer_valid
3045  * erpt_pointer is valid.
3046  * Access: RW
3047  */
3048 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3049
3050 /* reg_pererp_erpt_bank_pointer
3051  * Pointer to eRP table bank. May be modified at any time.
3052  * Range 0..cap_max_erp_table_banks-1
3053  * Reserved when erpt_pointer_valid = 0
3054  */
3055 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3056
3057 /* reg_pererp_erpt_pointer
3058  * Pointer to eRP table within the eRP bank. Can be changed for an
3059  * existing region.
3060  * Range 0..cap_max_erp_table_size-1
3061  * Reserved when erpt_pointer_valid = 0
3062  * Access: RW
3063  */
3064 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3065
3066 /* reg_pererp_erpt_vector
3067  * Vector of allowed eRP indexes starting from erpt_pointer within the
3068  * erpt_bank_pointer. Next entries will be in next bank.
3069  * Note that eRP index is used and not eRP ID.
3070  * Reserved when erpt_pointer_valid = 0
3071  * Access: RW
3072  */
3073 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3074
3075 /* reg_pererp_master_rp_id
3076  * Master RP ID. When there are no eRPs, then this provides the eRP ID
3077  * for the lookup. Can be changed for an existing region.
3078  * Reserved when erpt_pointer_valid = 1
3079  * Access: RW
3080  */
3081 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3082
3083 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3084                                                     unsigned long *erp_vector,
3085                                                     unsigned long size)
3086 {
3087         unsigned long bit;
3088
3089         for_each_set_bit(bit, erp_vector, size)
3090                 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
3091 }
3092
3093 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3094                                          bool ctcam_le, bool erpt_pointer_valid,
3095                                          u8 erpt_bank_pointer, u8 erpt_pointer,
3096                                          u8 master_rp_id)
3097 {
3098         MLXSW_REG_ZERO(pererp, payload);
3099         mlxsw_reg_pererp_region_id_set(payload, region_id);
3100         mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
3101         mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
3102         mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
3103         mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
3104         mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
3105 }
3106
3107 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register
3108  * ----------------------------------------------------------------
3109  * This register configures the Bloom filter entries.
3110  */
3111 #define MLXSW_REG_PEABFE_ID 0x3022
3112 #define MLXSW_REG_PEABFE_BASE_LEN 0x10
3113 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3114 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3115 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3116                               MLXSW_REG_PEABFE_BF_REC_LEN * \
3117                               MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3118
3119 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3120
3121 /* reg_peabfe_size
3122  * Number of BF entries to be updated.
3123  * Range 1..256
3124  * Access: Op
3125  */
3126 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3127
3128 /* reg_peabfe_bf_entry_state
3129  * Bloom filter state
3130  * 0 - Clear
3131  * 1 - Set
3132  * Access: RW
3133  */
3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3135                      MLXSW_REG_PEABFE_BASE_LEN, 31, 1,
3136                      MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3137
3138 /* reg_peabfe_bf_entry_bank
3139  * Bloom filter bank ID
3140  * Range 0..cap_max_erp_table_banks-1
3141  * Access: Index
3142  */
3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3144                      MLXSW_REG_PEABFE_BASE_LEN, 24, 4,
3145                      MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3146
3147 /* reg_peabfe_bf_entry_index
3148  * Bloom filter entry index
3149  * Range 0..2^cap_max_bf_log-1
3150  * Access: Index
3151  */
3152 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3153                      MLXSW_REG_PEABFE_BASE_LEN, 0, 24,
3154                      MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3155
3156 static inline void mlxsw_reg_peabfe_pack(char *payload)
3157 {
3158         MLXSW_REG_ZERO(peabfe, payload);
3159 }
3160
3161 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3162                                              u8 state, u8 bank, u32 bf_index)
3163 {
3164         u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
3165
3166         if (rec_index >= num_rec)
3167                 mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
3168         mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
3169         mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
3170         mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
3171 }
3172
3173 /* IEDR - Infrastructure Entry Delete Register
3174  * ----------------------------------------------------
3175  * This register is used for deleting entries from the entry tables.
3176  * It is legitimate to attempt to delete a nonexisting entry (the device will
3177  * respond as a good flow).
3178  */
3179 #define MLXSW_REG_IEDR_ID 0x3804
3180 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */
3181 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */
3182 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3183 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN +   \
3184                             MLXSW_REG_IEDR_REC_LEN *    \
3185                             MLXSW_REG_IEDR_REC_MAX_COUNT)
3186
3187 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3188
3189 /* reg_iedr_num_rec
3190  * Number of records.
3191  * Access: OP
3192  */
3193 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3194
3195 /* reg_iedr_rec_type
3196  * Resource type.
3197  * Access: OP
3198  */
3199 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3200                      MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3201
3202 /* reg_iedr_rec_size
3203  * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
3204  * Access: OP
3205  */
3206 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11,
3207                      MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3208
3209 /* reg_iedr_rec_index_start
3210  * Resource index start.
3211  * Access: OP
3212  */
3213 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3214                      MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3215
3216 static inline void mlxsw_reg_iedr_pack(char *payload)
3217 {
3218         MLXSW_REG_ZERO(iedr, payload);
3219 }
3220
3221 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3222                                            u8 rec_type, u16 rec_size,
3223                                            u32 rec_index_start)
3224 {
3225         u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3226
3227         if (rec_index >= num_rec)
3228                 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3229         mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3230         mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3231         mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3232 }
3233
3234 /* QPTS - QoS Priority Trust State Register
3235  * ----------------------------------------
3236  * This register controls the port policy to calculate the switch priority and
3237  * packet color based on incoming packet fields.
3238  */
3239 #define MLXSW_REG_QPTS_ID 0x4002
3240 #define MLXSW_REG_QPTS_LEN 0x8
3241
3242 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3243
3244 /* reg_qpts_local_port
3245  * Local port number.
3246  * Access: Index
3247  *
3248  * Note: CPU port is supported.
3249  */
3250 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8);
3251
3252 enum mlxsw_reg_qpts_trust_state {
3253         MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3254         MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */
3255 };
3256
3257 /* reg_qpts_trust_state
3258  * Trust state for a given port.
3259  * Access: RW
3260  */
3261 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3262
3263 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port,
3264                                        enum mlxsw_reg_qpts_trust_state ts)
3265 {
3266         MLXSW_REG_ZERO(qpts, payload);
3267
3268         mlxsw_reg_qpts_local_port_set(payload, local_port);
3269         mlxsw_reg_qpts_trust_state_set(payload, ts);
3270 }
3271
3272 /* QPCR - QoS Policer Configuration Register
3273  * -----------------------------------------
3274  * The QPCR register is used to create policers - that limit
3275  * the rate of bytes or packets via some trap group.
3276  */
3277 #define MLXSW_REG_QPCR_ID 0x4004
3278 #define MLXSW_REG_QPCR_LEN 0x28
3279
3280 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3281
3282 enum mlxsw_reg_qpcr_g {
3283         MLXSW_REG_QPCR_G_GLOBAL = 2,
3284         MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3285 };
3286
3287 /* reg_qpcr_g
3288  * The policer type.
3289  * Access: Index
3290  */
3291 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3292
3293 /* reg_qpcr_pid
3294  * Policer ID.
3295  * Access: Index
3296  */
3297 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3298
3299 /* reg_qpcr_color_aware
3300  * Is the policer aware of colors.
3301  * Must be 0 (unaware) for cpu port.
3302  * Access: RW for unbounded policer. RO for bounded policer.
3303  */
3304 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3305
3306 /* reg_qpcr_bytes
3307  * Is policer limit is for bytes per sec or packets per sec.
3308  * 0 - packets
3309  * 1 - bytes
3310  * Access: RW for unbounded policer. RO for bounded policer.
3311  */
3312 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3313
3314 enum mlxsw_reg_qpcr_ir_units {
3315         MLXSW_REG_QPCR_IR_UNITS_M,
3316         MLXSW_REG_QPCR_IR_UNITS_K,
3317 };
3318
3319 /* reg_qpcr_ir_units
3320  * Policer's units for cir and eir fields (for bytes limits only)
3321  * 1 - 10^3
3322  * 0 - 10^6
3323  * Access: OP
3324  */
3325 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3326
3327 enum mlxsw_reg_qpcr_rate_type {
3328         MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3329         MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3330 };
3331
3332 /* reg_qpcr_rate_type
3333  * Policer can have one limit (single rate) or 2 limits with specific operation
3334  * for packets that exceed the lower rate but not the upper one.
3335  * (For cpu port must be single rate)
3336  * Access: RW for unbounded policer. RO for bounded policer.
3337  */
3338 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3339
3340 /* reg_qpc_cbs
3341  * Policer's committed burst size.
3342  * The policer is working with time slices of 50 nano sec. By default every
3343  * slice is granted the proportionate share of the committed rate. If we want to
3344  * allow a slice to exceed that share (while still keeping the rate per sec) we
3345  * can allow burst. The burst size is between the default proportionate share
3346  * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
3347  * committed rate will result in exceeding the rate). The burst size must be a
3348  * log of 2 and will be determined by 2^cbs.
3349  * Access: RW
3350  */
3351 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3352
3353 /* reg_qpcr_cir
3354  * Policer's committed rate.
3355  * The rate used for sungle rate, the lower rate for double rate.
3356  * For bytes limits, the rate will be this value * the unit from ir_units.
3357  * (Resolution error is up to 1%).
3358  * Access: RW
3359  */
3360 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3361
3362 /* reg_qpcr_eir
3363  * Policer's exceed rate.
3364  * The higher rate for double rate, reserved for single rate.
3365  * Lower rate for double rate policer.
3366  * For bytes limits, the rate will be this value * the unit from ir_units.
3367  * (Resolution error is up to 1%).
3368  * Access: RW
3369  */
3370 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3371
3372 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3373
3374 /* reg_qpcr_exceed_action.
3375  * What to do with packets between the 2 limits for double rate.
3376  * Access: RW for unbounded policer. RO for bounded policer.
3377  */
3378 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3379
3380 enum mlxsw_reg_qpcr_action {
3381         /* Discard */
3382         MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3383         /* Forward and set color to red.
3384          * If the packet is intended to cpu port, it will be dropped.
3385          */
3386         MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3387 };
3388
3389 /* reg_qpcr_violate_action
3390  * What to do with packets that cross the cir limit (for single rate) or the eir
3391  * limit (for double rate).
3392  * Access: RW for unbounded policer. RO for bounded policer.
3393  */
3394 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3395
3396 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3397                                        enum mlxsw_reg_qpcr_ir_units ir_units,
3398                                        bool bytes, u32 cir, u16 cbs)
3399 {
3400         MLXSW_REG_ZERO(qpcr, payload);
3401         mlxsw_reg_qpcr_pid_set(payload, pid);
3402         mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3403         mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3404         mlxsw_reg_qpcr_violate_action_set(payload,
3405                                           MLXSW_REG_QPCR_ACTION_DISCARD);
3406         mlxsw_reg_qpcr_cir_set(payload, cir);
3407         mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3408         mlxsw_reg_qpcr_bytes_set(payload, bytes);
3409         mlxsw_reg_qpcr_cbs_set(payload, cbs);
3410 }
3411
3412 /* QTCT - QoS Switch Traffic Class Table
3413  * -------------------------------------
3414  * Configures the mapping between the packet switch priority and the
3415  * traffic class on the transmit port.
3416  */
3417 #define MLXSW_REG_QTCT_ID 0x400A
3418 #define MLXSW_REG_QTCT_LEN 0x08
3419
3420 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3421
3422 /* reg_qtct_local_port
3423  * Local port number.
3424  * Access: Index
3425  *
3426  * Note: CPU port is not supported.
3427  */
3428 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
3429
3430 /* reg_qtct_sub_port
3431  * Virtual port within the physical port.
3432  * Should be set to 0 when virtual ports are not enabled on the port.
3433  * Access: Index
3434  */
3435 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3436
3437 /* reg_qtct_switch_prio
3438  * Switch priority.
3439  * Access: Index
3440  */
3441 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3442
3443 /* reg_qtct_tclass
3444  * Traffic class.
3445  * Default values:
3446  * switch_prio 0 : tclass 1
3447  * switch_prio 1 : tclass 0
3448  * switch_prio i : tclass i, for i > 1
3449  * Access: RW
3450  */
3451 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3452
3453 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
3454                                        u8 switch_prio, u8 tclass)
3455 {
3456         MLXSW_REG_ZERO(qtct, payload);
3457         mlxsw_reg_qtct_local_port_set(payload, local_port);
3458         mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3459         mlxsw_reg_qtct_tclass_set(payload, tclass);
3460 }
3461
3462 /* QEEC - QoS ETS Element Configuration Register
3463  * ---------------------------------------------
3464  * Configures the ETS elements.
3465  */
3466 #define MLXSW_REG_QEEC_ID 0x400D
3467 #define MLXSW_REG_QEEC_LEN 0x20
3468
3469 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3470
3471 /* reg_qeec_local_port
3472  * Local port number.
3473  * Access: Index
3474  *
3475  * Note: CPU port is supported.
3476  */
3477 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
3478
3479 enum mlxsw_reg_qeec_hr {
3480         MLXSW_REG_QEEC_HIERARCY_PORT,
3481         MLXSW_REG_QEEC_HIERARCY_GROUP,
3482         MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3483         MLXSW_REG_QEEC_HIERARCY_TC,
3484 };
3485
3486 /* reg_qeec_element_hierarchy
3487  * 0 - Port
3488  * 1 - Group
3489  * 2 - Subgroup
3490  * 3 - Traffic Class
3491  * Access: Index
3492  */
3493 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3494
3495 /* reg_qeec_element_index
3496  * The index of the element in the hierarchy.
3497  * Access: Index
3498  */
3499 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3500
3501 /* reg_qeec_next_element_index
3502  * The index of the next (lower) element in the hierarchy.
3503  * Access: RW
3504  *
3505  * Note: Reserved for element_hierarchy 0.
3506  */
3507 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3508
3509 /* reg_qeec_mise
3510  * Min shaper configuration enable. Enables configuration of the min
3511  * shaper on this ETS element
3512  * 0 - Disable
3513  * 1 - Enable
3514  * Access: RW
3515  */
3516 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3517
3518 /* reg_qeec_ptps
3519  * PTP shaper
3520  * 0: regular shaper mode
3521  * 1: PTP oriented shaper
3522  * Allowed only for hierarchy 0
3523  * Not supported for CPU port
3524  * Note that ptps mode may affect the shaper rates of all hierarchies
3525  * Supported only on Spectrum-1
3526  * Access: RW
3527  */
3528 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
3529
3530 enum {
3531         MLXSW_REG_QEEC_BYTES_MODE,
3532         MLXSW_REG_QEEC_PACKETS_MODE,
3533 };
3534
3535 /* reg_qeec_pb
3536  * Packets or bytes mode.
3537  * 0 - Bytes mode
3538  * 1 - Packets mode
3539  * Access: RW
3540  *
3541  * Note: Used for max shaper configuration. For Spectrum, packets mode
3542  * is supported only for traffic classes of CPU port.
3543  */
3544 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3545
3546 /* The smallest permitted min shaper rate. */
3547 #define MLXSW_REG_QEEC_MIS_MIN  200000          /* Kbps */
3548
3549 /* reg_qeec_min_shaper_rate
3550  * Min shaper information rate.
3551  * For CPU port, can only be configured for port hierarchy.
3552  * When in bytes mode, value is specified in units of 1000bps.
3553  * Access: RW
3554  */
3555 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3556
3557 /* reg_qeec_mase
3558  * Max shaper configuration enable. Enables configuration of the max
3559  * shaper on this ETS element.
3560  * 0 - Disable
3561  * 1 - Enable
3562  * Access: RW
3563  */
3564 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3565
3566 /* A large max rate will disable the max shaper. */
3567 #define MLXSW_REG_QEEC_MAS_DIS  200000000       /* Kbps */
3568
3569 /* reg_qeec_max_shaper_rate
3570  * Max shaper information rate.
3571  * For CPU port, can only be configured for port hierarchy.
3572  * When in bytes mode, value is specified in units of 1000bps.
3573  * Access: RW
3574  */
3575 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
3576
3577 /* reg_qeec_de
3578  * DWRR configuration enable. Enables configuration of the dwrr and
3579  * dwrr_weight.
3580  * 0 - Disable
3581  * 1 - Enable
3582  * Access: RW
3583  */
3584 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3585
3586 /* reg_qeec_dwrr
3587  * Transmission selection algorithm to use on the link going down from
3588  * the ETS element.
3589  * 0 - Strict priority
3590  * 1 - DWRR
3591  * Access: RW
3592  */
3593 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3594
3595 /* reg_qeec_dwrr_weight
3596  * DWRR weight on the link going down from the ETS element. The
3597  * percentage of bandwidth guaranteed to an ETS element within
3598  * its hierarchy. The sum of all weights across all ETS elements
3599  * within one hierarchy should be equal to 100. Reserved when
3600  * transmission selection algorithm is strict priority.
3601  * Access: RW
3602  */
3603 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3604
3605 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3606                                        enum mlxsw_reg_qeec_hr hr, u8 index,
3607                                        u8 next_index)
3608 {
3609         MLXSW_REG_ZERO(qeec, payload);
3610         mlxsw_reg_qeec_local_port_set(payload, local_port);
3611         mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3612         mlxsw_reg_qeec_element_index_set(payload, index);
3613         mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3614 }
3615
3616 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port,
3617                                             bool ptps)
3618 {
3619         MLXSW_REG_ZERO(qeec, payload);
3620         mlxsw_reg_qeec_local_port_set(payload, local_port);
3621         mlxsw_reg_qeec_element_hierarchy_set(payload,
3622                                              MLXSW_REG_QEEC_HIERARCY_PORT);
3623         mlxsw_reg_qeec_ptps_set(payload, ptps);
3624 }
3625
3626 /* QRWE - QoS ReWrite Enable
3627  * -------------------------
3628  * This register configures the rewrite enable per receive port.
3629  */
3630 #define MLXSW_REG_QRWE_ID 0x400F
3631 #define MLXSW_REG_QRWE_LEN 0x08
3632
3633 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3634
3635 /* reg_qrwe_local_port
3636  * Local port number.
3637  * Access: Index
3638  *
3639  * Note: CPU port is supported. No support for router port.
3640  */
3641 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8);
3642
3643 /* reg_qrwe_dscp
3644  * Whether to enable DSCP rewrite (default is 0, don't rewrite).
3645  * Access: RW
3646  */
3647 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3648
3649 /* reg_qrwe_pcp
3650  * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
3651  * Access: RW
3652  */
3653 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3654
3655 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port,
3656                                        bool rewrite_pcp, bool rewrite_dscp)
3657 {
3658         MLXSW_REG_ZERO(qrwe, payload);
3659         mlxsw_reg_qrwe_local_port_set(payload, local_port);
3660         mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3661         mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3662 }
3663
3664 /* QPDSM - QoS Priority to DSCP Mapping
3665  * ------------------------------------
3666  * QoS Priority to DSCP Mapping Register
3667  */
3668 #define MLXSW_REG_QPDSM_ID 0x4011
3669 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */
3670 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */
3671 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3672 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN +                 \
3673                              MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN *       \
3674                              MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3675
3676 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3677
3678 /* reg_qpdsm_local_port
3679  * Local Port. Supported for data packets from CPU port.
3680  * Access: Index
3681  */
3682 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8);
3683
3684 /* reg_qpdsm_prio_entry_color0_e
3685  * Enable update of the entry for color 0 and a given port.
3686  * Access: WO
3687  */
3688 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
3689                      MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
3690                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3691
3692 /* reg_qpdsm_prio_entry_color0_dscp
3693  * DSCP field in the outer label of the packet for color 0 and a given port.
3694  * Reserved when e=0.
3695  * Access: RW
3696  */
3697 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
3698                      MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
3699                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3700
3701 /* reg_qpdsm_prio_entry_color1_e
3702  * Enable update of the entry for color 1 and a given port.
3703  * Access: WO
3704  */
3705 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
3706                      MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
3707                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3708
3709 /* reg_qpdsm_prio_entry_color1_dscp
3710  * DSCP field in the outer label of the packet for color 1 and a given port.
3711  * Reserved when e=0.
3712  * Access: RW
3713  */
3714 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
3715                      MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
3716                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3717
3718 /* reg_qpdsm_prio_entry_color2_e
3719  * Enable update of the entry for color 2 and a given port.
3720  * Access: WO
3721  */
3722 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
3723                      MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
3724                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3725
3726 /* reg_qpdsm_prio_entry_color2_dscp
3727  * DSCP field in the outer label of the packet for color 2 and a given port.
3728  * Reserved when e=0.
3729  * Access: RW
3730  */
3731 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
3732                      MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
3733                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3734
3735 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port)
3736 {
3737         MLXSW_REG_ZERO(qpdsm, payload);
3738         mlxsw_reg_qpdsm_local_port_set(payload, local_port);
3739 }
3740
3741 static inline void
3742 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
3743 {
3744         mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
3745         mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
3746         mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
3747         mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
3748         mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
3749         mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
3750 }
3751
3752 /* QPDPM - QoS Port DSCP to Priority Mapping Register
3753  * --------------------------------------------------
3754  * This register controls the mapping from DSCP field to
3755  * Switch Priority for IP packets.
3756  */
3757 #define MLXSW_REG_QPDPM_ID 0x4013
3758 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */
3759 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */
3760 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
3761 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN +                 \
3762                              MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN *       \
3763                              MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
3764
3765 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
3766
3767 /* reg_qpdpm_local_port
3768  * Local Port. Supported for data packets from CPU port.
3769  * Access: Index
3770  */
3771 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8);
3772
3773 /* reg_qpdpm_dscp_e
3774  * Enable update of the specific entry. When cleared, the switch_prio and color
3775  * fields are ignored and the previous switch_prio and color values are
3776  * preserved.
3777  * Access: WO
3778  */
3779 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
3780                      MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3781
3782 /* reg_qpdpm_dscp_prio
3783  * The new Switch Priority value for the relevant DSCP value.
3784  * Access: RW
3785  */
3786 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
3787                      MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
3788                      MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3789
3790 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port)
3791 {
3792         MLXSW_REG_ZERO(qpdpm, payload);
3793         mlxsw_reg_qpdpm_local_port_set(payload, local_port);
3794 }
3795
3796 static inline void
3797 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
3798 {
3799         mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
3800         mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
3801 }
3802
3803 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register
3804  * ------------------------------------------------------------------
3805  * This register configures if the Switch Priority to Traffic Class mapping is
3806  * based on Multicast packet indication. If so, then multicast packets will get
3807  * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by
3808  * QTCT.
3809  * By default, Switch Priority to Traffic Class mapping is not based on
3810  * Multicast packet indication.
3811  */
3812 #define MLXSW_REG_QTCTM_ID 0x401A
3813 #define MLXSW_REG_QTCTM_LEN 0x08
3814
3815 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
3816
3817 /* reg_qtctm_local_port
3818  * Local port number.
3819  * No support for CPU port.
3820  * Access: Index
3821  */
3822 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8);
3823
3824 /* reg_qtctm_mc
3825  * Multicast Mode
3826  * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
3827  * indication (default is 0, not based on Multicast packet indication).
3828  */
3829 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
3830
3831 static inline void
3832 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc)
3833 {
3834         MLXSW_REG_ZERO(qtctm, payload);
3835         mlxsw_reg_qtctm_local_port_set(payload, local_port);
3836         mlxsw_reg_qtctm_mc_set(payload, mc);
3837 }
3838
3839 /* QPSC - QoS PTP Shaper Configuration Register
3840  * --------------------------------------------
3841  * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1.
3842  * Supported only on Spectrum-1.
3843  */
3844 #define MLXSW_REG_QPSC_ID 0x401B
3845 #define MLXSW_REG_QPSC_LEN 0x28
3846
3847 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN);
3848
3849 enum mlxsw_reg_qpsc_port_speed {
3850         MLXSW_REG_QPSC_PORT_SPEED_100M,
3851         MLXSW_REG_QPSC_PORT_SPEED_1G,
3852         MLXSW_REG_QPSC_PORT_SPEED_10G,
3853         MLXSW_REG_QPSC_PORT_SPEED_25G,
3854 };
3855
3856 /* reg_qpsc_port_speed
3857  * Port speed.
3858  * Access: Index
3859  */
3860 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);
3861
3862 /* reg_qpsc_shaper_time_exp
3863  * The base-time-interval for updating the shapers tokens (for all hierarchies).
3864  * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
3865  * shaper_rate = 64bit * shaper_inc / shaper_update_rate
3866  * Access: RW
3867  */
3868 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);
3869
3870 /* reg_qpsc_shaper_time_mantissa
3871  * The base-time-interval for updating the shapers tokens (for all hierarchies).
3872  * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
3873  * shaper_rate = 64bit * shaper_inc / shaper_update_rate
3874  * Access: RW
3875  */
3876 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);
3877
3878 /* reg_qpsc_shaper_inc
3879  * Number of tokens added to shaper on each update.
3880  * Units of 8B.
3881  * Access: RW
3882  */
3883 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
3884
3885 /* reg_qpsc_shaper_bs
3886  * Max shaper Burst size.
3887  * Burst size is 2 ^ max_shaper_bs * 512 [bits]
3888  * Range is: 5..25 (from 2KB..2GB)
3889  * Access: RW
3890  */
3891 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
3892
3893 /* reg_qpsc_ptsc_we
3894  * Write enable to port_to_shaper_credits.
3895  * Access: WO
3896  */
3897 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
3898
3899 /* reg_qpsc_port_to_shaper_credits
3900  * For split ports: range 1..57
3901  * For non-split ports: range 1..112
3902  * Written only when ptsc_we is set.
3903  * Access: RW
3904  */
3905 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
3906
3907 /* reg_qpsc_ing_timestamp_inc
3908  * Ingress timestamp increment.
3909  * 2's complement.
3910  * The timestamp of MTPPTR at ingress will be incremented by this value. Global
3911  * value for all ports.
3912  * Same units as used by MTPPTR.
3913  * Access: RW
3914  */
3915 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
3916
3917 /* reg_qpsc_egr_timestamp_inc
3918  * Egress timestamp increment.
3919  * 2's complement.
3920  * The timestamp of MTPPTR at egress will be incremented by this value. Global
3921  * value for all ports.
3922  * Same units as used by MTPPTR.
3923  * Access: RW
3924  */
3925 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
3926
3927 static inline void
3928 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed,
3929                     u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc,
3930                     u8 shaper_bs, u8 port_to_shaper_credits,
3931                     int ing_timestamp_inc, int egr_timestamp_inc)
3932 {
3933         MLXSW_REG_ZERO(qpsc, payload);
3934         mlxsw_reg_qpsc_port_speed_set(payload, port_speed);
3935         mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp);
3936         mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa);
3937         mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc);
3938         mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs);
3939         mlxsw_reg_qpsc_ptsc_we_set(payload, true);
3940         mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits);
3941         mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc);
3942         mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc);
3943 }
3944
3945 /* PMLP - Ports Module to Local Port Register
3946  * ------------------------------------------
3947  * Configures the assignment of modules to local ports.
3948  */
3949 #define MLXSW_REG_PMLP_ID 0x5002
3950 #define MLXSW_REG_PMLP_LEN 0x40
3951
3952 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
3953
3954 /* reg_pmlp_rxtx
3955  * 0 - Tx value is used for both Tx and Rx.
3956  * 1 - Rx value is taken from a separte field.
3957  * Access: RW
3958  */
3959 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
3960
3961 /* reg_pmlp_local_port
3962  * Local port number.
3963  * Access: Index
3964  */
3965 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
3966
3967 /* reg_pmlp_width
3968  * 0 - Unmap local port.
3969  * 1 - Lane 0 is used.
3970  * 2 - Lanes 0 and 1 are used.
3971  * 4 - Lanes 0, 1, 2 and 3 are used.
3972  * Access: RW
3973  */
3974 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
3975
3976 /* reg_pmlp_module
3977  * Module number.
3978  * Access: RW
3979  */
3980 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
3981
3982 /* reg_pmlp_tx_lane
3983  * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
3984  * Access: RW
3985  */
3986 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
3987
3988 /* reg_pmlp_rx_lane
3989  * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
3990  * equal to Tx lane.
3991  * Access: RW
3992  */
3993 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
3994
3995 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
3996 {
3997         MLXSW_REG_ZERO(pmlp, payload);
3998         mlxsw_reg_pmlp_local_port_set(payload, local_port);
3999 }
4000
4001 /* PMTU - Port MTU Register
4002  * ------------------------
4003  * Configures and reports the port MTU.
4004  */
4005 #define MLXSW_REG_PMTU_ID 0x5003
4006 #define MLXSW_REG_PMTU_LEN 0x10
4007
4008 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
4009
4010 /* reg_pmtu_local_port
4011  * Local port number.
4012  * Access: Index
4013  */
4014 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
4015
4016 /* reg_pmtu_max_mtu
4017  * Maximum MTU.
4018  * When port type (e.g. Ethernet) is configured, the relevant MTU is
4019  * reported, otherwise the minimum between the max_mtu of the different
4020  * types is reported.
4021  * Access: RO
4022  */
4023 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
4024
4025 /* reg_pmtu_admin_mtu
4026  * MTU value to set port to. Must be smaller or equal to max_mtu.
4027  * Note: If port type is Infiniband, then port must be disabled, when its
4028  * MTU is set.
4029  * Access: RW
4030  */
4031 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
4032
4033 /* reg_pmtu_oper_mtu
4034  * The actual MTU configured on the port. Packets exceeding this size
4035  * will be dropped.
4036  * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
4037  * oper_mtu might be smaller than admin_mtu.
4038  * Access: RO
4039  */
4040 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4041
4042 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
4043                                        u16 new_mtu)
4044 {
4045         MLXSW_REG_ZERO(pmtu, payload);
4046         mlxsw_reg_pmtu_local_port_set(payload, local_port);
4047         mlxsw_reg_pmtu_max_mtu_set(payload, 0);
4048         mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
4049         mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
4050 }
4051
4052 /* PTYS - Port Type and Speed Register
4053  * -----------------------------------
4054  * Configures and reports the port speed type.
4055  *
4056  * Note: When set while the link is up, the changes will not take effect
4057  * until the port transitions from down to up state.
4058  */
4059 #define MLXSW_REG_PTYS_ID 0x5004
4060 #define MLXSW_REG_PTYS_LEN 0x40
4061
4062 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
4063
4064 /* an_disable_admin
4065  * Auto negotiation disable administrative configuration
4066  * 0 - Device doesn't support AN disable.
4067  * 1 - Device supports AN disable.
4068  * Access: RW
4069  */
4070 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
4071
4072 /* reg_ptys_local_port
4073  * Local port number.
4074  * Access: Index
4075  */
4076 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
4077
4078 #define MLXSW_REG_PTYS_PROTO_MASK_IB    BIT(0)
4079 #define MLXSW_REG_PTYS_PROTO_MASK_ETH   BIT(2)
4080
4081 /* reg_ptys_proto_mask
4082  * Protocol mask. Indicates which protocol is used.
4083  * 0 - Infiniband.
4084  * 1 - Fibre Channel.
4085  * 2 - Ethernet.
4086  * Access: Index
4087  */
4088 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
4089
4090 enum {
4091         MLXSW_REG_PTYS_AN_STATUS_NA,
4092         MLXSW_REG_PTYS_AN_STATUS_OK,
4093         MLXSW_REG_PTYS_AN_STATUS_FAIL,
4094 };
4095
4096 /* reg_ptys_an_status
4097  * Autonegotiation status.
4098  * Access: RO
4099  */
4100 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
4101
4102 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M                         BIT(0)
4103 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII                   BIT(1)
4104 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII                 BIT(2)
4105 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R                           BIT(3)
4106 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G                     BIT(4)
4107 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G                BIT(5)
4108 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR             BIT(6)
4109 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2    BIT(7)
4110 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR      BIT(8)
4111 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4            BIT(9)
4112 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2         BIT(10)
4113 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4         BIT(12)
4114
4115 /* reg_ptys_ext_eth_proto_cap
4116  * Extended Ethernet port supported speeds and protocols.
4117  * Access: RO
4118  */
4119 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
4120
4121 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII                  BIT(0)
4122 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX            BIT(1)
4123 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4            BIT(2)
4124 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4            BIT(3)
4125 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR             BIT(4)
4126 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2            BIT(5)
4127 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4            BIT(6)
4128 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4            BIT(7)
4129 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4             BIT(8)
4130 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR             BIT(12)
4131 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR             BIT(13)
4132 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR          BIT(14)
4133 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4            BIT(15)
4134 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4        BIT(16)
4135 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2            BIT(18)
4136 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4            BIT(19)
4137 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4           BIT(20)
4138 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4           BIT(21)
4139 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4           BIT(22)
4140 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4       BIT(23)
4141 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX             BIT(24)
4142 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T              BIT(25)
4143 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T              BIT(26)
4144 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR             BIT(27)
4145 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR             BIT(28)
4146 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR             BIT(29)
4147 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2            BIT(30)
4148 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2            BIT(31)
4149
4150 /* reg_ptys_eth_proto_cap
4151  * Ethernet port supported speeds and protocols.
4152  * Access: RO
4153  */
4154 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4155
4156 /* reg_ptys_ib_link_width_cap
4157  * IB port supported widths.
4158  * Access: RO
4159  */
4160 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
4161
4162 #define MLXSW_REG_PTYS_IB_SPEED_SDR     BIT(0)
4163 #define MLXSW_REG_PTYS_IB_SPEED_DDR     BIT(1)
4164 #define MLXSW_REG_PTYS_IB_SPEED_QDR     BIT(2)
4165 #define MLXSW_REG_PTYS_IB_SPEED_FDR10   BIT(3)
4166 #define MLXSW_REG_PTYS_IB_SPEED_FDR     BIT(4)
4167 #define MLXSW_REG_PTYS_IB_SPEED_EDR     BIT(5)
4168
4169 /* reg_ptys_ib_proto_cap
4170  * IB port supported speeds and protocols.
4171  * Access: RO
4172  */
4173 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
4174
4175 /* reg_ptys_ext_eth_proto_admin
4176  * Extended speed and protocol to set port to.
4177  * Access: RW
4178  */
4179 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4180
4181 /* reg_ptys_eth_proto_admin
4182  * Speed and protocol to set port to.
4183  * Access: RW
4184  */
4185 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4186
4187 /* reg_ptys_ib_link_width_admin
4188  * IB width to set port to.
4189  * Access: RW
4190  */
4191 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
4192
4193 /* reg_ptys_ib_proto_admin
4194  * IB speeds and protocols to set port to.
4195  * Access: RW
4196  */
4197 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
4198
4199 /* reg_ptys_ext_eth_proto_oper
4200  * The extended current speed and protocol configured for the port.
4201  * Access: RO
4202  */
4203 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4204
4205 /* reg_ptys_eth_proto_oper
4206  * The current speed and protocol configured for the port.
4207  * Access: RO
4208  */
4209 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4210
4211 /* reg_ptys_ib_link_width_oper
4212  * The current IB width to set port to.
4213  * Access: RO
4214  */
4215 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
4216
4217 /* reg_ptys_ib_proto_oper
4218  * The current IB speed and protocol.
4219  * Access: RO
4220  */
4221 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
4222
4223 enum mlxsw_reg_ptys_connector_type {
4224         MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4225         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4226         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4227         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4228         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4229         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4230         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4231         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4232         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4233 };
4234
4235 /* reg_ptys_connector_type
4236  * Connector type indication.
4237  * Access: RO
4238  */
4239 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4240
4241 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
4242                                            u32 proto_admin, bool autoneg)
4243 {
4244         MLXSW_REG_ZERO(ptys, payload);
4245         mlxsw_reg_ptys_local_port_set(payload, local_port);
4246         mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4247         mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4248         mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4249 }
4250
4251 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port,
4252                                                u32 proto_admin, bool autoneg)
4253 {
4254         MLXSW_REG_ZERO(ptys, payload);
4255         mlxsw_reg_ptys_local_port_set(payload, local_port);
4256         mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4257         mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4258         mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4259 }
4260
4261 static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
4262                                              u32 *p_eth_proto_cap,
4263                                              u32 *p_eth_proto_admin,
4264                                              u32 *p_eth_proto_oper)
4265 {
4266         if (p_eth_proto_cap)
4267                 *p_eth_proto_cap =
4268                         mlxsw_reg_ptys_eth_proto_cap_get(payload);
4269         if (p_eth_proto_admin)
4270                 *p_eth_proto_admin =
4271                         mlxsw_reg_ptys_eth_proto_admin_get(payload);
4272         if (p_eth_proto_oper)
4273                 *p_eth_proto_oper =
4274                         mlxsw_reg_ptys_eth_proto_oper_get(payload);
4275 }
4276
4277 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4278                                                  u32 *p_eth_proto_cap,
4279                                                  u32 *p_eth_proto_admin,
4280                                                  u32 *p_eth_proto_oper)
4281 {
4282         if (p_eth_proto_cap)
4283                 *p_eth_proto_cap =
4284                         mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4285         if (p_eth_proto_admin)
4286                 *p_eth_proto_admin =
4287                         mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4288         if (p_eth_proto_oper)
4289                 *p_eth_proto_oper =
4290                         mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4291 }
4292
4293 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
4294                                           u16 proto_admin, u16 link_width)
4295 {
4296         MLXSW_REG_ZERO(ptys, payload);
4297         mlxsw_reg_ptys_local_port_set(payload, local_port);
4298         mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
4299         mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
4300         mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
4301 }
4302
4303 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
4304                                             u16 *p_ib_link_width_cap,
4305                                             u16 *p_ib_proto_oper,
4306                                             u16 *p_ib_link_width_oper)
4307 {
4308         if (p_ib_proto_cap)
4309                 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
4310         if (p_ib_link_width_cap)
4311                 *p_ib_link_width_cap =
4312                         mlxsw_reg_ptys_ib_link_width_cap_get(payload);
4313         if (p_ib_proto_oper)
4314                 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
4315         if (p_ib_link_width_oper)
4316                 *p_ib_link_width_oper =
4317                         mlxsw_reg_ptys_ib_link_width_oper_get(payload);
4318 }
4319
4320 /* PPAD - Port Physical Address Register
4321  * -------------------------------------
4322  * The PPAD register configures the per port physical MAC address.
4323  */
4324 #define MLXSW_REG_PPAD_ID 0x5005
4325 #define MLXSW_REG_PPAD_LEN 0x10
4326
4327 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
4328
4329 /* reg_ppad_single_base_mac
4330  * 0: base_mac, local port should be 0 and mac[7:0] is
4331  * reserved. HW will set incremental
4332  * 1: single_mac - mac of the local_port
4333  * Access: RW
4334  */
4335 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4336
4337 /* reg_ppad_local_port
4338  * port number, if single_base_mac = 0 then local_port is reserved
4339  * Access: RW
4340  */
4341 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
4342
4343 /* reg_ppad_mac
4344  * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
4345  * If single_base_mac = 1 - the per port MAC address
4346  * Access: RW
4347  */
4348 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4349
4350 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4351                                        u8 local_port)
4352 {
4353         MLXSW_REG_ZERO(ppad, payload);
4354         mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4355         mlxsw_reg_ppad_local_port_set(payload, local_port);
4356 }
4357
4358 /* PAOS - Ports Administrative and Operational Status Register
4359  * -----------------------------------------------------------
4360  * Configures and retrieves per port administrative and operational status.
4361  */
4362 #define MLXSW_REG_PAOS_ID 0x5006
4363 #define MLXSW_REG_PAOS_LEN 0x10
4364
4365 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
4366
4367 /* reg_paos_swid
4368  * Switch partition ID with which to associate the port.
4369  * Note: while external ports uses unique local port numbers (and thus swid is
4370  * redundant), router ports use the same local port number where swid is the
4371  * only indication for the relevant port.
4372  * Access: Index
4373  */
4374 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4375
4376 /* reg_paos_local_port
4377  * Local port number.
4378  * Access: Index
4379  */
4380 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
4381
4382 /* reg_paos_admin_status
4383  * Port administrative state (the desired state of the port):
4384  * 1 - Up.
4385  * 2 - Down.
4386  * 3 - Up once. This means that in case of link failure, the port won't go
4387  *     into polling mode, but will wait to be re-enabled by software.
4388  * 4 - Disabled by system. Can only be set by hardware.
4389  * Access: RW
4390  */
4391 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4392
4393 /* reg_paos_oper_status
4394  * Port operational state (the current state):
4395  * 1 - Up.
4396  * 2 - Down.
4397  * 3 - Down by port failure. This means that the device will not let the
4398  *     port up again until explicitly specified by software.
4399  * Access: RO
4400  */
4401 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4402
4403 /* reg_paos_ase
4404  * Admin state update enabled.
4405  * Access: WO
4406  */
4407 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4408
4409 /* reg_paos_ee
4410  * Event update enable. If this bit is set, event generation will be
4411  * updated based on the e field.
4412  * Access: WO
4413  */
4414 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4415
4416 /* reg_paos_e
4417  * Event generation on operational state change:
4418  * 0 - Do not generate event.
4419  * 1 - Generate Event.
4420  * 2 - Generate Single Event.
4421  * Access: RW
4422  */
4423 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4424
4425 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
4426                                        enum mlxsw_port_admin_status status)
4427 {
4428         MLXSW_REG_ZERO(paos, payload);
4429         mlxsw_reg_paos_swid_set(payload, 0);
4430         mlxsw_reg_paos_local_port_set(payload, local_port);
4431         mlxsw_reg_paos_admin_status_set(payload, status);
4432         mlxsw_reg_paos_oper_status_set(payload, 0);
4433         mlxsw_reg_paos_ase_set(payload, 1);
4434         mlxsw_reg_paos_ee_set(payload, 1);
4435         mlxsw_reg_paos_e_set(payload, 1);
4436 }
4437
4438 /* PFCC - Ports Flow Control Configuration Register
4439  * ------------------------------------------------
4440  * Configures and retrieves the per port flow control configuration.
4441  */
4442 #define MLXSW_REG_PFCC_ID 0x5007
4443 #define MLXSW_REG_PFCC_LEN 0x20
4444
4445 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4446
4447 /* reg_pfcc_local_port
4448  * Local port number.
4449  * Access: Index
4450  */
4451 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
4452
4453 /* reg_pfcc_pnat
4454  * Port number access type. Determines the way local_port is interpreted:
4455  * 0 - Local port number.
4456  * 1 - IB / label port number.
4457  * Access: Index
4458  */
4459 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4460
4461 /* reg_pfcc_shl_cap
4462  * Send to higher layers capabilities:
4463  * 0 - No capability of sending Pause and PFC frames to higher layers.
4464  * 1 - Device has capability of sending Pause and PFC frames to higher
4465  *     layers.
4466  * Access: RO
4467  */
4468 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4469
4470 /* reg_pfcc_shl_opr
4471  * Send to higher layers operation:
4472  * 0 - Pause and PFC frames are handled by the port (default).
4473  * 1 - Pause and PFC frames are handled by the port and also sent to
4474  *     higher layers. Only valid if shl_cap = 1.
4475  * Access: RW
4476  */
4477 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4478
4479 /* reg_pfcc_ppan
4480  * Pause policy auto negotiation.
4481  * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
4482  * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
4483  *     based on the auto-negotiation resolution.
4484  * Access: RW
4485  *
4486  * Note: The auto-negotiation advertisement is set according to pptx and
4487  * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
4488  */
4489 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4490
4491 /* reg_pfcc_prio_mask_tx
4492  * Bit per priority indicating if Tx flow control policy should be
4493  * updated based on bit pfctx.
4494  * Access: WO
4495  */
4496 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4497
4498 /* reg_pfcc_prio_mask_rx
4499  * Bit per priority indicating if Rx flow control policy should be
4500  * updated based on bit pfcrx.
4501  * Access: WO
4502  */
4503 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4504
4505 /* reg_pfcc_pptx
4506  * Admin Pause policy on Tx.
4507  * 0 - Never generate Pause frames (default).
4508  * 1 - Generate Pause frames according to Rx buffer threshold.
4509  * Access: RW
4510  */
4511 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4512
4513 /* reg_pfcc_aptx
4514  * Active (operational) Pause policy on Tx.
4515  * 0 - Never generate Pause frames.
4516  * 1 - Generate Pause frames according to Rx buffer threshold.
4517  * Access: RO
4518  */
4519 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4520
4521 /* reg_pfcc_pfctx
4522  * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
4523  * 0 - Never generate priority Pause frames on the specified priority
4524  *     (default).
4525  * 1 - Generate priority Pause frames according to Rx buffer threshold on
4526  *     the specified priority.
4527  * Access: RW
4528  *
4529  * Note: pfctx and pptx must be mutually exclusive.
4530  */
4531 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4532
4533 /* reg_pfcc_pprx
4534  * Admin Pause policy on Rx.
4535  * 0 - Ignore received Pause frames (default).
4536  * 1 - Respect received Pause frames.
4537  * Access: RW
4538  */
4539 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4540
4541 /* reg_pfcc_aprx
4542  * Active (operational) Pause policy on Rx.
4543  * 0 - Ignore received Pause frames.
4544  * 1 - Respect received Pause frames.
4545  * Access: RO
4546  */
4547 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4548
4549 /* reg_pfcc_pfcrx
4550  * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
4551  * 0 - Ignore incoming priority Pause frames on the specified priority
4552  *     (default).
4553  * 1 - Respect incoming priority Pause frames on the specified priority.
4554  * Access: RW
4555  */
4556 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4557
4558 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4559
4560 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4561 {
4562         mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4563         mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4564         mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4565         mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4566 }
4567
4568 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
4569 {
4570         MLXSW_REG_ZERO(pfcc, payload);
4571         mlxsw_reg_pfcc_local_port_set(payload, local_port);
4572 }
4573
4574 /* PPCNT - Ports Performance Counters Register
4575  * -------------------------------------------
4576  * The PPCNT register retrieves per port performance counters.
4577  */
4578 #define MLXSW_REG_PPCNT_ID 0x5008
4579 #define MLXSW_REG_PPCNT_LEN 0x100
4580 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4581
4582 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4583
4584 /* reg_ppcnt_swid
4585  * For HCA: must be always 0.
4586  * Switch partition ID to associate port with.
4587  * Switch partitions are numbered from 0 to 7 inclusively.
4588  * Switch partition 254 indicates stacking ports.
4589  * Switch partition 255 indicates all switch partitions.
4590  * Only valid on Set() operation with local_port=255.
4591  * Access: Index
4592  */
4593 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4594
4595 /* reg_ppcnt_local_port
4596  * Local port number.
4597  * 255 indicates all ports on the device, and is only allowed
4598  * for Set() operation.
4599  * Access: Index
4600  */
4601 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
4602
4603 /* reg_ppcnt_pnat
4604  * Port number access type:
4605  * 0 - Local port number
4606  * 1 - IB port number
4607  * Access: Index
4608  */
4609 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4610
4611 enum mlxsw_reg_ppcnt_grp {
4612         MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4613         MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
4614         MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4615         MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
4616         MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4617         MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
4618         MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4619         MLXSW_REG_PPCNT_TC_CNT = 0x11,
4620         MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
4621 };
4622
4623 /* reg_ppcnt_grp
4624  * Performance counter group.
4625  * Group 63 indicates all groups. Only valid on Set() operation with
4626  * clr bit set.
4627  * 0x0: IEEE 802.3 Counters
4628  * 0x1: RFC 2863 Counters
4629  * 0x2: RFC 2819 Counters
4630  * 0x3: RFC 3635 Counters
4631  * 0x5: Ethernet Extended Counters
4632  * 0x6: Ethernet Discard Counters
4633  * 0x8: Link Level Retransmission Counters
4634  * 0x10: Per Priority Counters
4635  * 0x11: Per Traffic Class Counters
4636  * 0x12: Physical Layer Counters
4637  * 0x13: Per Traffic Class Congestion Counters
4638  * Access: Index
4639  */
4640 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4641
4642 /* reg_ppcnt_clr
4643  * Clear counters. Setting the clr bit will reset the counter value
4644  * for all counters in the counter group. This bit can be set
4645  * for both Set() and Get() operation.
4646  * Access: OP
4647  */
4648 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4649
4650 /* reg_ppcnt_prio_tc
4651  * Priority for counter set that support per priority, valid values: 0-7.
4652  * Traffic class for counter set that support per traffic class,
4653  * valid values: 0- cap_max_tclass-1 .
4654  * For HCA: cap_max_tclass is always 8.
4655  * Otherwise must be 0.
4656  * Access: Index
4657  */
4658 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
4659
4660 /* Ethernet IEEE 802.3 Counter Group */
4661
4662 /* reg_ppcnt_a_frames_transmitted_ok
4663  * Access: RO
4664  */
4665 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
4666              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4667
4668 /* reg_ppcnt_a_frames_received_ok
4669  * Access: RO
4670  */
4671 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
4672              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4673
4674 /* reg_ppcnt_a_frame_check_sequence_errors
4675  * Access: RO
4676  */
4677 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
4678              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4679
4680 /* reg_ppcnt_a_alignment_errors
4681  * Access: RO
4682  */
4683 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
4684              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4685
4686 /* reg_ppcnt_a_octets_transmitted_ok
4687  * Access: RO
4688  */
4689 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
4690              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4691
4692 /* reg_ppcnt_a_octets_received_ok
4693  * Access: RO
4694  */
4695 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
4696              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4697
4698 /* reg_ppcnt_a_multicast_frames_xmitted_ok
4699  * Access: RO
4700  */
4701 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
4702              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4703
4704 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
4705  * Access: RO
4706  */
4707 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
4708              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4709
4710 /* reg_ppcnt_a_multicast_frames_received_ok
4711  * Access: RO
4712  */
4713 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
4714              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4715
4716 /* reg_ppcnt_a_broadcast_frames_received_ok
4717  * Access: RO
4718  */
4719 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
4720              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4721
4722 /* reg_ppcnt_a_in_range_length_errors
4723  * Access: RO
4724  */
4725 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
4726              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4727
4728 /* reg_ppcnt_a_out_of_range_length_field
4729  * Access: RO
4730  */
4731 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
4732              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4733
4734 /* reg_ppcnt_a_frame_too_long_errors
4735  * Access: RO
4736  */
4737 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
4738              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4739
4740 /* reg_ppcnt_a_symbol_error_during_carrier
4741  * Access: RO
4742  */
4743 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
4744              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4745
4746 /* reg_ppcnt_a_mac_control_frames_transmitted
4747  * Access: RO
4748  */
4749 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
4750              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4751
4752 /* reg_ppcnt_a_mac_control_frames_received
4753  * Access: RO
4754  */
4755 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
4756              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4757
4758 /* reg_ppcnt_a_unsupported_opcodes_received
4759  * Access: RO
4760  */
4761 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
4762              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4763
4764 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
4765  * Access: RO
4766  */
4767 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
4768              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4769
4770 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
4771  * Access: RO
4772  */
4773 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
4774              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4775
4776 /* Ethernet RFC 2863 Counter Group */
4777
4778 /* reg_ppcnt_if_in_discards
4779  * Access: RO
4780  */
4781 MLXSW_ITEM64(reg, ppcnt, if_in_discards,
4782              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4783
4784 /* reg_ppcnt_if_out_discards
4785  * Access: RO
4786  */
4787 MLXSW_ITEM64(reg, ppcnt, if_out_discards,
4788              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4789
4790 /* reg_ppcnt_if_out_errors
4791  * Access: RO
4792  */
4793 MLXSW_ITEM64(reg, ppcnt, if_out_errors,
4794              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4795
4796 /* Ethernet RFC 2819 Counter Group */
4797
4798 /* reg_ppcnt_ether_stats_undersize_pkts
4799  * Access: RO
4800  */
4801 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
4802              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4803
4804 /* reg_ppcnt_ether_stats_oversize_pkts
4805  * Access: RO
4806  */
4807 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
4808              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4809
4810 /* reg_ppcnt_ether_stats_fragments
4811  * Access: RO
4812  */
4813 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
4814              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4815
4816 /* reg_ppcnt_ether_stats_pkts64octets
4817  * Access: RO
4818  */
4819 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
4820              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4821
4822 /* reg_ppcnt_ether_stats_pkts65to127octets
4823  * Access: RO
4824  */
4825 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
4826              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4827
4828 /* reg_ppcnt_ether_stats_pkts128to255octets
4829  * Access: RO
4830  */
4831 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
4832              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4833
4834 /* reg_ppcnt_ether_stats_pkts256to511octets
4835  * Access: RO
4836  */
4837 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
4838              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4839
4840 /* reg_ppcnt_ether_stats_pkts512to1023octets
4841  * Access: RO
4842  */
4843 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
4844              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4845
4846 /* reg_ppcnt_ether_stats_pkts1024to1518octets
4847  * Access: RO
4848  */
4849 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
4850              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4851
4852 /* reg_ppcnt_ether_stats_pkts1519to2047octets
4853  * Access: RO
4854  */
4855 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
4856              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4857
4858 /* reg_ppcnt_ether_stats_pkts2048to4095octets
4859  * Access: RO
4860  */
4861 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
4862              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4863
4864 /* reg_ppcnt_ether_stats_pkts4096to8191octets
4865  * Access: RO
4866  */
4867 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
4868              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
4869
4870 /* reg_ppcnt_ether_stats_pkts8192to10239octets
4871  * Access: RO
4872  */
4873 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
4874              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
4875
4876 /* Ethernet RFC 3635 Counter Group */
4877
4878 /* reg_ppcnt_dot3stats_fcs_errors
4879  * Access: RO
4880  */
4881 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
4882              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4883
4884 /* reg_ppcnt_dot3stats_symbol_errors
4885  * Access: RO
4886  */
4887 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
4888              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4889
4890 /* reg_ppcnt_dot3control_in_unknown_opcodes
4891  * Access: RO
4892  */
4893 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
4894              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4895
4896 /* reg_ppcnt_dot3in_pause_frames
4897  * Access: RO
4898  */
4899 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
4900              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4901
4902 /* Ethernet Extended Counter Group Counters */
4903
4904 /* reg_ppcnt_ecn_marked
4905  * Access: RO
4906  */
4907 MLXSW_ITEM64(reg, ppcnt, ecn_marked,
4908              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4909
4910 /* Ethernet Discard Counter Group Counters */
4911
4912 /* reg_ppcnt_ingress_general
4913  * Access: RO
4914  */
4915 MLXSW_ITEM64(reg, ppcnt, ingress_general,
4916              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4917
4918 /* reg_ppcnt_ingress_policy_engine
4919  * Access: RO
4920  */
4921 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
4922              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4923
4924 /* reg_ppcnt_ingress_vlan_membership
4925  * Access: RO
4926  */
4927 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
4928              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4929
4930 /* reg_ppcnt_ingress_tag_frame_type
4931  * Access: RO
4932  */
4933 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
4934              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4935
4936 /* reg_ppcnt_egress_vlan_membership
4937  * Access: RO
4938  */
4939 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
4940              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4941
4942 /* reg_ppcnt_loopback_filter
4943  * Access: RO
4944  */
4945 MLXSW_ITEM64(reg, ppcnt, loopback_filter,
4946              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4947
4948 /* reg_ppcnt_egress_general
4949  * Access: RO
4950  */
4951 MLXSW_ITEM64(reg, ppcnt, egress_general,
4952              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4953
4954 /* reg_ppcnt_egress_hoq
4955  * Access: RO
4956  */
4957 MLXSW_ITEM64(reg, ppcnt, egress_hoq,
4958              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4959
4960 /* reg_ppcnt_egress_policy_engine
4961  * Access: RO
4962  */
4963 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
4964              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4965
4966 /* reg_ppcnt_ingress_tx_link_down
4967  * Access: RO
4968  */
4969 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
4970              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4971
4972 /* reg_ppcnt_egress_stp_filter
4973  * Access: RO
4974  */
4975 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
4976              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4977
4978 /* reg_ppcnt_egress_sll
4979  * Access: RO
4980  */
4981 MLXSW_ITEM64(reg, ppcnt, egress_sll,
4982              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4983
4984 /* Ethernet Per Priority Group Counters */
4985
4986 /* reg_ppcnt_rx_octets
4987  * Access: RO
4988  */
4989 MLXSW_ITEM64(reg, ppcnt, rx_octets,
4990              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4991
4992 /* reg_ppcnt_rx_frames
4993  * Access: RO
4994  */
4995 MLXSW_ITEM64(reg, ppcnt, rx_frames,
4996              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4997
4998 /* reg_ppcnt_tx_octets
4999  * Access: RO
5000  */
5001 MLXSW_ITEM64(reg, ppcnt, tx_octets,
5002              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5003
5004 /* reg_ppcnt_tx_frames
5005  * Access: RO
5006  */
5007 MLXSW_ITEM64(reg, ppcnt, tx_frames,
5008              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5009
5010 /* reg_ppcnt_rx_pause
5011  * Access: RO
5012  */
5013 MLXSW_ITEM64(reg, ppcnt, rx_pause,
5014              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5015
5016 /* reg_ppcnt_rx_pause_duration
5017  * Access: RO
5018  */
5019 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
5020              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5021
5022 /* reg_ppcnt_tx_pause
5023  * Access: RO
5024  */
5025 MLXSW_ITEM64(reg, ppcnt, tx_pause,
5026              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5027
5028 /* reg_ppcnt_tx_pause_duration
5029  * Access: RO
5030  */
5031 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
5032              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5033
5034 /* reg_ppcnt_rx_pause_transition
5035  * Access: RO
5036  */
5037 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
5038              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5039
5040 /* Ethernet Per Traffic Group Counters */
5041
5042 /* reg_ppcnt_tc_transmit_queue
5043  * Contains the transmit queue depth in cells of traffic class
5044  * selected by prio_tc and the port selected by local_port.
5045  * The field cannot be cleared.
5046  * Access: RO
5047  */
5048 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
5049              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5050
5051 /* reg_ppcnt_tc_no_buffer_discard_uc
5052  * The number of unicast packets dropped due to lack of shared
5053  * buffer resources.
5054  * Access: RO
5055  */
5056 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
5057              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5058
5059 /* Ethernet Per Traffic Class Congestion Group Counters */
5060
5061 /* reg_ppcnt_wred_discard
5062  * Access: RO
5063  */
5064 MLXSW_ITEM64(reg, ppcnt, wred_discard,
5065              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5066
5067 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
5068                                         enum mlxsw_reg_ppcnt_grp grp,
5069                                         u8 prio_tc)
5070 {
5071         MLXSW_REG_ZERO(ppcnt, payload);
5072         mlxsw_reg_ppcnt_swid_set(payload, 0);
5073         mlxsw_reg_ppcnt_local_port_set(payload, local_port);
5074         mlxsw_reg_ppcnt_pnat_set(payload, 0);
5075         mlxsw_reg_ppcnt_grp_set(payload, grp);
5076         mlxsw_reg_ppcnt_clr_set(payload, 0);
5077         mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
5078 }
5079
5080 /* PLIB - Port Local to InfiniBand Port
5081  * ------------------------------------
5082  * The PLIB register performs mapping from Local Port into InfiniBand Port.
5083  */
5084 #define MLXSW_REG_PLIB_ID 0x500A
5085 #define MLXSW_REG_PLIB_LEN 0x10
5086
5087 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
5088
5089 /* reg_plib_local_port
5090  * Local port number.
5091  * Access: Index
5092  */
5093 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8);
5094
5095 /* reg_plib_ib_port
5096  * InfiniBand port remapping for local_port.
5097  * Access: RW
5098  */
5099 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
5100
5101 /* PPTB - Port Prio To Buffer Register
5102  * -----------------------------------
5103  * Configures the switch priority to buffer table.
5104  */
5105 #define MLXSW_REG_PPTB_ID 0x500B
5106 #define MLXSW_REG_PPTB_LEN 0x10
5107
5108 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
5109
5110 enum {
5111         MLXSW_REG_PPTB_MM_UM,
5112         MLXSW_REG_PPTB_MM_UNICAST,
5113         MLXSW_REG_PPTB_MM_MULTICAST,
5114 };
5115
5116 /* reg_pptb_mm
5117  * Mapping mode.
5118  * 0 - Map both unicast and multicast packets to the same buffer.
5119  * 1 - Map only unicast packets.
5120  * 2 - Map only multicast packets.
5121  * Access: Index
5122  *
5123  * Note: SwitchX-2 only supports the first option.
5124  */
5125 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
5126
5127 /* reg_pptb_local_port
5128  * Local port number.
5129  * Access: Index
5130  */
5131 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
5132
5133 /* reg_pptb_um
5134  * Enables the update of the untagged_buf field.
5135  * Access: RW
5136  */
5137 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
5138
5139 /* reg_pptb_pm
5140  * Enables the update of the prio_to_buff field.
5141  * Bit <i> is a flag for updating the mapping for switch priority <i>.
5142  * Access: RW
5143  */
5144 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
5145
5146 /* reg_pptb_prio_to_buff
5147  * Mapping of switch priority <i> to one of the allocated receive port
5148  * buffers.
5149  * Access: RW
5150  */
5151 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
5152
5153 /* reg_pptb_pm_msb
5154  * Enables the update of the prio_to_buff field.
5155  * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
5156  * Access: RW
5157  */
5158 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
5159
5160 /* reg_pptb_untagged_buff
5161  * Mapping of untagged frames to one of the allocated receive port buffers.
5162  * Access: RW
5163  *
5164  * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
5165  * Spectrum, as it maps untagged packets based on the default switch priority.
5166  */
5167 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
5168
5169 /* reg_pptb_prio_to_buff_msb
5170  * Mapping of switch priority <i+8> to one of the allocated receive port
5171  * buffers.
5172  * Access: RW
5173  */
5174 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5175
5176 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5177
5178 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
5179 {
5180         MLXSW_REG_ZERO(pptb, payload);
5181         mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5182         mlxsw_reg_pptb_local_port_set(payload, local_port);
5183         mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5184         mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5185 }
5186
5187 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
5188                                                     u8 buff)
5189 {
5190         mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
5191         mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
5192 }
5193
5194 /* PBMC - Port Buffer Management Control Register
5195  * ----------------------------------------------
5196  * The PBMC register configures and retrieves the port packet buffer
5197  * allocation for different Prios, and the Pause threshold management.
5198  */
5199 #define MLXSW_REG_PBMC_ID 0x500C
5200 #define MLXSW_REG_PBMC_LEN 0x6C
5201
5202 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
5203
5204 /* reg_pbmc_local_port
5205  * Local port number.
5206  * Access: Index
5207  */
5208 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
5209
5210 /* reg_pbmc_xoff_timer_value
5211  * When device generates a pause frame, it uses this value as the pause
5212  * timer (time for the peer port to pause in quota-512 bit time).
5213  * Access: RW
5214  */
5215 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
5216
5217 /* reg_pbmc_xoff_refresh
5218  * The time before a new pause frame should be sent to refresh the pause RW
5219  * state. Using the same units as xoff_timer_value above (in quota-512 bit
5220  * time).
5221  * Access: RW
5222  */
5223 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
5224
5225 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
5226
5227 /* reg_pbmc_buf_lossy
5228  * The field indicates if the buffer is lossy.
5229  * 0 - Lossless
5230  * 1 - Lossy
5231  * Access: RW
5232  */
5233 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
5234
5235 /* reg_pbmc_buf_epsb
5236  * Eligible for Port Shared buffer.
5237  * If epsb is set, packets assigned to buffer are allowed to insert the port
5238  * shared buffer.
5239  * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
5240  * Access: RW
5241  */
5242 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
5243
5244 /* reg_pbmc_buf_size
5245  * The part of the packet buffer array is allocated for the specific buffer.
5246  * Units are represented in cells.
5247  * Access: RW
5248  */
5249 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
5250
5251 /* reg_pbmc_buf_xoff_threshold
5252  * Once the amount of data in the buffer goes above this value, device
5253  * starts sending PFC frames for all priorities associated with the
5254  * buffer. Units are represented in cells. Reserved in case of lossy
5255  * buffer.
5256  * Access: RW
5257  *
5258  * Note: In Spectrum, reserved for buffer[9].
5259  */
5260 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
5261                      0x08, 0x04, false);
5262
5263 /* reg_pbmc_buf_xon_threshold
5264  * When the amount of data in the buffer goes below this value, device
5265  * stops sending PFC frames for the priorities associated with the
5266  * buffer. Units are represented in cells. Reserved in case of lossy
5267  * buffer.
5268  * Access: RW
5269  *
5270  * Note: In Spectrum, reserved for buffer[9].
5271  */
5272 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5273                      0x08, 0x04, false);
5274
5275 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
5276                                        u16 xoff_timer_value, u16 xoff_refresh)
5277 {
5278         MLXSW_REG_ZERO(pbmc, payload);
5279         mlxsw_reg_pbmc_local_port_set(payload, local_port);
5280         mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5281         mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5282 }
5283
5284 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
5285                                                     int buf_index,
5286                                                     u16 size)
5287 {
5288         mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
5289         mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5290         mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5291 }
5292
5293 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
5294                                                        int buf_index, u16 size,
5295                                                        u16 threshold)
5296 {
5297         mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
5298         mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5299         mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5300         mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
5301         mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
5302 }
5303
5304 /* PSPA - Port Switch Partition Allocation
5305  * ---------------------------------------
5306  * Controls the association of a port with a switch partition and enables
5307  * configuring ports as stacking ports.
5308  */
5309 #define MLXSW_REG_PSPA_ID 0x500D
5310 #define MLXSW_REG_PSPA_LEN 0x8
5311
5312 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
5313
5314 /* reg_pspa_swid
5315  * Switch partition ID.
5316  * Access: RW
5317  */
5318 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
5319
5320 /* reg_pspa_local_port
5321  * Local port number.
5322  * Access: Index
5323  */
5324 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
5325
5326 /* reg_pspa_sub_port
5327  * Virtual port within the local port. Set to 0 when virtual ports are
5328  * disabled on the local port.
5329  * Access: Index
5330  */
5331 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5332
5333 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
5334 {
5335         MLXSW_REG_ZERO(pspa, payload);
5336         mlxsw_reg_pspa_swid_set(payload, swid);
5337         mlxsw_reg_pspa_local_port_set(payload, local_port);
5338         mlxsw_reg_pspa_sub_port_set(payload, 0);
5339 }
5340
5341 /* PPLR - Port Physical Loopback Register
5342  * --------------------------------------
5343  * This register allows configuration of the port's loopback mode.
5344  */
5345 #define MLXSW_REG_PPLR_ID 0x5018
5346 #define MLXSW_REG_PPLR_LEN 0x8
5347
5348 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);
5349
5350 /* reg_pplr_local_port
5351  * Local port number.
5352  * Access: Index
5353  */
5354 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8);
5355
5356 /* Phy local loopback. When set the port's egress traffic is looped back
5357  * to the receiver and the port transmitter is disabled.
5358  */
5359 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
5360
5361 /* reg_pplr_lb_en
5362  * Loopback enable.
5363  * Access: RW
5364  */
5365 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5366
5367 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port,
5368                                        bool phy_local)
5369 {
5370         MLXSW_REG_ZERO(pplr, payload);
5371         mlxsw_reg_pplr_local_port_set(payload, local_port);
5372         mlxsw_reg_pplr_lb_en_set(payload,
5373                                  phy_local ?
5374                                  MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
5375 }
5376
5377 /* HTGT - Host Trap Group Table
5378  * ----------------------------
5379  * Configures the properties for forwarding to CPU.
5380  */
5381 #define MLXSW_REG_HTGT_ID 0x7002
5382 #define MLXSW_REG_HTGT_LEN 0x20
5383
5384 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
5385
5386 /* reg_htgt_swid
5387  * Switch partition ID.
5388  * Access: Index
5389  */
5390 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
5391
5392 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0      /* For locally attached CPU */
5393
5394 /* reg_htgt_type
5395  * CPU path type.
5396  * Access: RW
5397  */
5398 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
5399
5400 enum mlxsw_reg_htgt_trap_group {
5401         MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
5402         MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
5403         MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
5404         MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
5405         MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
5406         MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
5407         MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP,
5408         MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
5409         MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
5410         MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
5411         MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
5412         MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP,
5413         MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS,
5414         MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
5415         MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE,
5416         MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
5417         MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
5418         MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF,
5419         MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
5420         MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,
5421         MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,
5422         MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
5423         MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,
5424         MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,
5425 };
5426
5427 /* reg_htgt_trap_group
5428  * Trap group number. User defined number specifying which trap groups
5429  * should be forwarded to the CPU. The mapping between trap IDs and trap
5430  * groups is configured using HPKT register.
5431  * Access: Index
5432  */
5433 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
5434
5435 enum {
5436         MLXSW_REG_HTGT_POLICER_DISABLE,
5437         MLXSW_REG_HTGT_POLICER_ENABLE,
5438 };
5439
5440 /* reg_htgt_pide
5441  * Enable policer ID specified using 'pid' field.
5442  * Access: RW
5443  */
5444 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
5445
5446 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff
5447
5448 /* reg_htgt_pid
5449  * Policer ID for the trap group.
5450  * Access: RW
5451  */
5452 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
5453
5454 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
5455
5456 /* reg_htgt_mirror_action
5457  * Mirror action to use.
5458  * 0 - Trap to CPU.
5459  * 1 - Trap to CPU and mirror to a mirroring agent.
5460  * 2 - Mirror to a mirroring agent and do not trap to CPU.
5461  * Access: RW
5462  *
5463  * Note: Mirroring to a mirroring agent is only supported in Spectrum.
5464  */
5465 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
5466
5467 /* reg_htgt_mirroring_agent
5468  * Mirroring agent.
5469  * Access: RW
5470  */
5471 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
5472
5473 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
5474
5475 /* reg_htgt_priority
5476  * Trap group priority.
5477  * In case a packet matches multiple classification rules, the packet will
5478  * only be trapped once, based on the trap ID associated with the group (via
5479  * register HPKT) with the highest priority.
5480  * Supported values are 0-7, with 7 represnting the highest priority.
5481  * Access: RW
5482  *
5483  * Note: In SwitchX-2 this field is ignored and the priority value is replaced
5484  * by the 'trap_group' field.
5485  */
5486 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
5487
5488 #define MLXSW_REG_HTGT_DEFAULT_TC 7
5489
5490 /* reg_htgt_local_path_cpu_tclass
5491  * CPU ingress traffic class for the trap group.
5492  * Access: RW
5493  */
5494 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
5495
5496 enum mlxsw_reg_htgt_local_path_rdq {
5497         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
5498         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
5499         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
5500         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
5501 };
5502 /* reg_htgt_local_path_rdq
5503  * Receive descriptor queue (RDQ) to use for the trap group.
5504  * Access: RW
5505  */
5506 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
5507
5508 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
5509                                        u8 priority, u8 tc)
5510 {
5511         MLXSW_REG_ZERO(htgt, payload);
5512
5513         if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
5514                 mlxsw_reg_htgt_pide_set(payload,
5515                                         MLXSW_REG_HTGT_POLICER_DISABLE);
5516         } else {
5517                 mlxsw_reg_htgt_pide_set(payload,
5518                                         MLXSW_REG_HTGT_POLICER_ENABLE);
5519                 mlxsw_reg_htgt_pid_set(payload, policer_id);
5520         }
5521
5522         mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
5523         mlxsw_reg_htgt_trap_group_set(payload, group);
5524         mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
5525         mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
5526         mlxsw_reg_htgt_priority_set(payload, priority);
5527         mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
5528         mlxsw_reg_htgt_local_path_rdq_set(payload, group);
5529 }
5530
5531 /* HPKT - Host Packet Trap
5532  * -----------------------
5533  * Configures trap IDs inside trap groups.
5534  */
5535 #define MLXSW_REG_HPKT_ID 0x7003
5536 #define MLXSW_REG_HPKT_LEN 0x10
5537
5538 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
5539
5540 enum {
5541         MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
5542         MLXSW_REG_HPKT_ACK_REQUIRED,
5543 };
5544
5545 /* reg_hpkt_ack
5546  * Require acknowledgements from the host for events.
5547  * If set, then the device will wait for the event it sent to be acknowledged
5548  * by the host. This option is only relevant for event trap IDs.
5549  * Access: RW
5550  *
5551  * Note: Currently not supported by firmware.
5552  */
5553 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
5554
5555 enum mlxsw_reg_hpkt_action {
5556         MLXSW_REG_HPKT_ACTION_FORWARD,
5557         MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
5558         MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
5559         MLXSW_REG_HPKT_ACTION_DISCARD,
5560         MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
5561         MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
5562 };
5563
5564 /* reg_hpkt_action
5565  * Action to perform on packet when trapped.
5566  * 0 - No action. Forward to CPU based on switching rules.
5567  * 1 - Trap to CPU (CPU receives sole copy).
5568  * 2 - Mirror to CPU (CPU receives a replica of the packet).
5569  * 3 - Discard.
5570  * 4 - Soft discard (allow other traps to act on the packet).
5571  * 5 - Trap and soft discard (allow other traps to overwrite this trap).
5572  * Access: RW
5573  *
5574  * Note: Must be set to 0 (forward) for event trap IDs, as they are already
5575  * addressed to the CPU.
5576  */
5577 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
5578
5579 /* reg_hpkt_trap_group
5580  * Trap group to associate the trap with.
5581  * Access: RW
5582  */
5583 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
5584
5585 /* reg_hpkt_trap_id
5586  * Trap ID.
5587  * Access: Index
5588  *
5589  * Note: A trap ID can only be associated with a single trap group. The device
5590  * will associate the trap ID with the last trap group configured.
5591  */
5592 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
5593
5594 enum {
5595         MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
5596         MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
5597         MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
5598 };
5599
5600 /* reg_hpkt_ctrl
5601  * Configure dedicated buffer resources for control packets.
5602  * Ignored by SwitchX-2.
5603  * 0 - Keep factory defaults.
5604  * 1 - Do not use control buffer for this trap ID.
5605  * 2 - Use control buffer for this trap ID.
5606  * Access: RW
5607  */
5608 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
5609
5610 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
5611                                        enum mlxsw_reg_htgt_trap_group trap_group,
5612                                        bool is_ctrl)
5613 {
5614         MLXSW_REG_ZERO(hpkt, payload);
5615         mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
5616         mlxsw_reg_hpkt_action_set(payload, action);
5617         mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
5618         mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
5619         mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
5620                                 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
5621                                 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
5622 }
5623
5624 /* RGCR - Router General Configuration Register
5625  * --------------------------------------------
5626  * The register is used for setting up the router configuration.
5627  */
5628 #define MLXSW_REG_RGCR_ID 0x8001
5629 #define MLXSW_REG_RGCR_LEN 0x28
5630
5631 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
5632
5633 /* reg_rgcr_ipv4_en
5634  * IPv4 router enable.
5635  * Access: RW
5636  */
5637 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
5638
5639 /* reg_rgcr_ipv6_en
5640  * IPv6 router enable.
5641  * Access: RW
5642  */
5643 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
5644
5645 /* reg_rgcr_max_router_interfaces
5646  * Defines the maximum number of active router interfaces for all virtual
5647  * routers.
5648  * Access: RW
5649  */
5650 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
5651
5652 /* reg_rgcr_usp
5653  * Update switch priority and packet color.
5654  * 0 - Preserve the value of Switch Priority and packet color.
5655  * 1 - Recalculate the value of Switch Priority and packet color.
5656  * Access: RW
5657  *
5658  * Note: Not supported by SwitchX and SwitchX-2.
5659  */
5660 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
5661
5662 /* reg_rgcr_pcp_rw
5663  * Indicates how to handle the pcp_rewrite_en value:
5664  * 0 - Preserve the value of pcp_rewrite_en.
5665  * 2 - Disable PCP rewrite.
5666  * 3 - Enable PCP rewrite.
5667  * Access: RW
5668  *
5669  * Note: Not supported by SwitchX and SwitchX-2.
5670  */
5671 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
5672
5673 /* reg_rgcr_activity_dis
5674  * Activity disable:
5675  * 0 - Activity will be set when an entry is hit (default).
5676  * 1 - Activity will not be set when an entry is hit.
5677  *
5678  * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
5679  * (RALUE).
5680  * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
5681  * Entry (RAUHT).
5682  * Bits 2:7 are reserved.
5683  * Access: RW
5684  *
5685  * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
5686  */
5687 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
5688
5689 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
5690                                        bool ipv6_en)
5691 {
5692         MLXSW_REG_ZERO(rgcr, payload);
5693         mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
5694         mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
5695 }
5696
5697 /* RITR - Router Interface Table Register
5698  * --------------------------------------
5699  * The register is used to configure the router interface table.
5700  */
5701 #define MLXSW_REG_RITR_ID 0x8002
5702 #define MLXSW_REG_RITR_LEN 0x40
5703
5704 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
5705
5706 /* reg_ritr_enable
5707  * Enables routing on the router interface.
5708  * Access: RW
5709  */
5710 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
5711
5712 /* reg_ritr_ipv4
5713  * IPv4 routing enable. Enables routing of IPv4 traffic on the router
5714  * interface.
5715  * Access: RW
5716  */
5717 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
5718
5719 /* reg_ritr_ipv6
5720  * IPv6 routing enable. Enables routing of IPv6 traffic on the router
5721  * interface.
5722  * Access: RW
5723  */
5724 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
5725
5726 /* reg_ritr_ipv4_mc
5727  * IPv4 multicast routing enable.
5728  * Access: RW
5729  */
5730 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
5731
5732 /* reg_ritr_ipv6_mc
5733  * IPv6 multicast routing enable.
5734  * Access: RW
5735  */
5736 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
5737
5738 enum mlxsw_reg_ritr_if_type {
5739         /* VLAN interface. */
5740         MLXSW_REG_RITR_VLAN_IF,
5741         /* FID interface. */
5742         MLXSW_REG_RITR_FID_IF,
5743         /* Sub-port interface. */
5744         MLXSW_REG_RITR_SP_IF,
5745         /* Loopback Interface. */
5746         MLXSW_REG_RITR_LOOPBACK_IF,
5747 };
5748
5749 /* reg_ritr_type
5750  * Router interface type as per enum mlxsw_reg_ritr_if_type.
5751  * Access: RW
5752  */
5753 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
5754
5755 enum {
5756         MLXSW_REG_RITR_RIF_CREATE,
5757         MLXSW_REG_RITR_RIF_DEL,
5758 };
5759
5760 /* reg_ritr_op
5761  * Opcode:
5762  * 0 - Create or edit RIF.
5763  * 1 - Delete RIF.
5764  * Reserved for SwitchX-2. For Spectrum, editing of interface properties
5765  * is not supported. An interface must be deleted and re-created in order
5766  * to update properties.
5767  * Access: WO
5768  */
5769 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
5770
5771 /* reg_ritr_rif
5772  * Router interface index. A pointer to the Router Interface Table.
5773  * Access: Index
5774  */
5775 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
5776
5777 /* reg_ritr_ipv4_fe
5778  * IPv4 Forwarding Enable.
5779  * Enables routing of IPv4 traffic on the router interface. When disabled,
5780  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5781  * Not supported in SwitchX-2.
5782  * Access: RW
5783  */
5784 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
5785
5786 /* reg_ritr_ipv6_fe
5787  * IPv6 Forwarding Enable.
5788  * Enables routing of IPv6 traffic on the router interface. When disabled,
5789  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5790  * Not supported in SwitchX-2.
5791  * Access: RW
5792  */
5793 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
5794
5795 /* reg_ritr_ipv4_mc_fe
5796  * IPv4 Multicast Forwarding Enable.
5797  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5798  * will be enabled.
5799  * Access: RW
5800  */
5801 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
5802
5803 /* reg_ritr_ipv6_mc_fe
5804  * IPv6 Multicast Forwarding Enable.
5805  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5806  * will be enabled.
5807  * Access: RW
5808  */
5809 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
5810
5811 /* reg_ritr_lb_en
5812  * Loop-back filter enable for unicast packets.
5813  * If the flag is set then loop-back filter for unicast packets is
5814  * implemented on the RIF. Multicast packets are always subject to
5815  * loop-back filtering.
5816  * Access: RW
5817  */
5818 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
5819
5820 /* reg_ritr_virtual_router
5821  * Virtual router ID associated with the router interface.
5822  * Access: RW
5823  */
5824 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
5825
5826 /* reg_ritr_mtu
5827  * Router interface MTU.
5828  * Access: RW
5829  */
5830 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
5831
5832 /* reg_ritr_if_swid
5833  * Switch partition ID.
5834  * Access: RW
5835  */
5836 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
5837
5838 /* reg_ritr_if_mac
5839  * Router interface MAC address.
5840  * In Spectrum, all MAC addresses must have the same 38 MSBits.
5841  * Access: RW
5842  */
5843 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
5844
5845 /* reg_ritr_if_vrrp_id_ipv6
5846  * VRRP ID for IPv6
5847  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5848  * Access: RW
5849  */
5850 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
5851
5852 /* reg_ritr_if_vrrp_id_ipv4
5853  * VRRP ID for IPv4
5854  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5855  * Access: RW
5856  */
5857 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
5858
5859 /* VLAN Interface */
5860
5861 /* reg_ritr_vlan_if_vid
5862  * VLAN ID.
5863  * Access: RW
5864  */
5865 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
5866
5867 /* FID Interface */
5868
5869 /* reg_ritr_fid_if_fid
5870  * Filtering ID. Used to connect a bridge to the router. Only FIDs from
5871  * the vFID range are supported.
5872  * Access: RW
5873  */
5874 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
5875
5876 static inline void mlxsw_reg_ritr_fid_set(char *payload,
5877                                           enum mlxsw_reg_ritr_if_type rif_type,
5878                                           u16 fid)
5879 {
5880         if (rif_type == MLXSW_REG_RITR_FID_IF)
5881                 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
5882         else
5883                 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
5884 }
5885
5886 /* Sub-port Interface */
5887
5888 /* reg_ritr_sp_if_lag
5889  * LAG indication. When this bit is set the system_port field holds the
5890  * LAG identifier.
5891  * Access: RW
5892  */
5893 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
5894
5895 /* reg_ritr_sp_system_port
5896  * Port unique indentifier. When lag bit is set, this field holds the
5897  * lag_id in bits 0:9.
5898  * Access: RW
5899  */
5900 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
5901
5902 /* reg_ritr_sp_if_vid
5903  * VLAN ID.
5904  * Access: RW
5905  */
5906 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
5907
5908 /* Loopback Interface */
5909
5910 enum mlxsw_reg_ritr_loopback_protocol {
5911         /* IPinIP IPv4 underlay Unicast */
5912         MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
5913         /* IPinIP IPv6 underlay Unicast */
5914         MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
5915         /* IPinIP generic - used for Spectrum-2 underlay RIF */
5916         MLXSW_REG_RITR_LOOPBACK_GENERIC,
5917 };
5918
5919 /* reg_ritr_loopback_protocol
5920  * Access: RW
5921  */
5922 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
5923
5924 enum mlxsw_reg_ritr_loopback_ipip_type {
5925         /* Tunnel is IPinIP. */
5926         MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
5927         /* Tunnel is GRE, no key. */
5928         MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
5929         /* Tunnel is GRE, with a key. */
5930         MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
5931 };
5932
5933 /* reg_ritr_loopback_ipip_type
5934  * Encapsulation type.
5935  * Access: RW
5936  */
5937 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
5938
5939 enum mlxsw_reg_ritr_loopback_ipip_options {
5940         /* The key is defined by gre_key. */
5941         MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
5942 };
5943
5944 /* reg_ritr_loopback_ipip_options
5945  * Access: RW
5946  */
5947 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
5948
5949 /* reg_ritr_loopback_ipip_uvr
5950  * Underlay Virtual Router ID.
5951  * Range is 0..cap_max_virtual_routers-1.
5952  * Reserved for Spectrum-2.
5953  * Access: RW
5954  */
5955 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
5956
5957 /* reg_ritr_loopback_ipip_underlay_rif
5958  * Underlay ingress router interface.
5959  * Reserved for Spectrum.
5960  * Access: RW
5961  */
5962 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
5963
5964 /* reg_ritr_loopback_ipip_usip*
5965  * Encapsulation Underlay source IP.
5966  * Access: RW
5967  */
5968 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
5969 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
5970
5971 /* reg_ritr_loopback_ipip_gre_key
5972  * GRE Key.
5973  * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP.
5974  * Access: RW
5975  */
5976 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
5977
5978 /* Shared between ingress/egress */
5979 enum mlxsw_reg_ritr_counter_set_type {
5980         /* No Count. */
5981         MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
5982         /* Basic. Used for router interfaces, counting the following:
5983          *      - Error and Discard counters.
5984          *      - Unicast, Multicast and Broadcast counters. Sharing the
5985          *        same set of counters for the different type of traffic
5986          *        (IPv4, IPv6 and mpls).
5987          */
5988         MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
5989 };
5990
5991 /* reg_ritr_ingress_counter_index
5992  * Counter Index for flow counter.
5993  * Access: RW
5994  */
5995 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
5996
5997 /* reg_ritr_ingress_counter_set_type
5998  * Igress Counter Set Type for router interface counter.
5999  * Access: RW
6000  */
6001 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
6002
6003 /* reg_ritr_egress_counter_index
6004  * Counter Index for flow counter.
6005  * Access: RW
6006  */
6007 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
6008
6009 /* reg_ritr_egress_counter_set_type
6010  * Egress Counter Set Type for router interface counter.
6011  * Access: RW
6012  */
6013 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
6014
6015 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
6016                                                bool enable, bool egress)
6017 {
6018         enum mlxsw_reg_ritr_counter_set_type set_type;
6019
6020         if (enable)
6021                 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
6022         else
6023                 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
6024         mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
6025
6026         if (egress)
6027                 mlxsw_reg_ritr_egress_counter_index_set(payload, index);
6028         else
6029                 mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
6030 }
6031
6032 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
6033 {
6034         MLXSW_REG_ZERO(ritr, payload);
6035         mlxsw_reg_ritr_rif_set(payload, rif);
6036 }
6037
6038 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
6039                                              u16 system_port, u16 vid)
6040 {
6041         mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
6042         mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
6043         mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
6044 }
6045
6046 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
6047                                        enum mlxsw_reg_ritr_if_type type,
6048                                        u16 rif, u16 vr_id, u16 mtu)
6049 {
6050         bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
6051
6052         MLXSW_REG_ZERO(ritr, payload);
6053         mlxsw_reg_ritr_enable_set(payload, enable);
6054         mlxsw_reg_ritr_ipv4_set(payload, 1);
6055         mlxsw_reg_ritr_ipv6_set(payload, 1);
6056         mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
6057         mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
6058         mlxsw_reg_ritr_type_set(payload, type);
6059         mlxsw_reg_ritr_op_set(payload, op);
6060         mlxsw_reg_ritr_rif_set(payload, rif);
6061         mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
6062         mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
6063         mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
6064         mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
6065         mlxsw_reg_ritr_lb_en_set(payload, 1);
6066         mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
6067         mlxsw_reg_ritr_mtu_set(payload, mtu);
6068 }
6069
6070 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
6071 {
6072         mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
6073 }
6074
6075 static inline void
6076 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
6077                             enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6078                             enum mlxsw_reg_ritr_loopback_ipip_options options,
6079                             u16 uvr_id, u16 underlay_rif, u32 gre_key)
6080 {
6081         mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
6082         mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
6083         mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
6084         mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);
6085         mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
6086 }
6087
6088 static inline void
6089 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
6090                             enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6091                             enum mlxsw_reg_ritr_loopback_ipip_options options,
6092                             u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)
6093 {
6094         mlxsw_reg_ritr_loopback_protocol_set(payload,
6095                                     MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
6096         mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
6097                                                  uvr_id, underlay_rif, gre_key);
6098         mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
6099 }
6100
6101 /* RTAR - Router TCAM Allocation Register
6102  * --------------------------------------
6103  * This register is used for allocation of regions in the TCAM table.
6104  */
6105 #define MLXSW_REG_RTAR_ID 0x8004
6106 #define MLXSW_REG_RTAR_LEN 0x20
6107
6108 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
6109
6110 enum mlxsw_reg_rtar_op {
6111         MLXSW_REG_RTAR_OP_ALLOCATE,
6112         MLXSW_REG_RTAR_OP_RESIZE,
6113         MLXSW_REG_RTAR_OP_DEALLOCATE,
6114 };
6115
6116 /* reg_rtar_op
6117  * Access: WO
6118  */
6119 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
6120
6121 enum mlxsw_reg_rtar_key_type {
6122         MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
6123         MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
6124 };
6125
6126 /* reg_rtar_key_type
6127  * TCAM key type for the region.
6128  * Access: WO
6129  */
6130 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
6131
6132 /* reg_rtar_region_size
6133  * TCAM region size. When allocating/resizing this is the requested
6134  * size, the response is the actual size.
6135  * Note: Actual size may be larger than requested.
6136  * Reserved for op = Deallocate
6137  * Access: WO
6138  */
6139 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
6140
6141 static inline void mlxsw_reg_rtar_pack(char *payload,
6142                                        enum mlxsw_reg_rtar_op op,
6143                                        enum mlxsw_reg_rtar_key_type key_type,
6144                                        u16 region_size)
6145 {
6146         MLXSW_REG_ZERO(rtar, payload);
6147         mlxsw_reg_rtar_op_set(payload, op);
6148         mlxsw_reg_rtar_key_type_set(payload, key_type);
6149         mlxsw_reg_rtar_region_size_set(payload, region_size);
6150 }
6151
6152 /* RATR - Router Adjacency Table Register
6153  * --------------------------------------
6154  * The RATR register is used to configure the Router Adjacency (next-hop)
6155  * Table.
6156  */
6157 #define MLXSW_REG_RATR_ID 0x8008
6158 #define MLXSW_REG_RATR_LEN 0x2C
6159
6160 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
6161
6162 enum mlxsw_reg_ratr_op {
6163         /* Read */
6164         MLXSW_REG_RATR_OP_QUERY_READ = 0,
6165         /* Read and clear activity */
6166         MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
6167         /* Write Adjacency entry */
6168         MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
6169         /* Write Adjacency entry only if the activity is cleared.
6170          * The write may not succeed if the activity is set. There is not
6171          * direct feedback if the write has succeeded or not, however
6172          * the get will reveal the actual entry (SW can compare the get
6173          * response to the set command).
6174          */
6175         MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
6176 };
6177
6178 /* reg_ratr_op
6179  * Note that Write operation may also be used for updating
6180  * counter_set_type and counter_index. In this case all other
6181  * fields must not be updated.
6182  * Access: OP
6183  */
6184 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
6185
6186 /* reg_ratr_v
6187  * Valid bit. Indicates if the adjacency entry is valid.
6188  * Note: the device may need some time before reusing an invalidated
6189  * entry. During this time the entry can not be reused. It is
6190  * recommended to use another entry before reusing an invalidated
6191  * entry (e.g. software can put it at the end of the list for
6192  * reusing). Trying to access an invalidated entry not yet cleared
6193  * by the device results with failure indicating "Try Again" status.
6194  * When valid is '0' then egress_router_interface,trap_action,
6195  * adjacency_parameters and counters are reserved
6196  * Access: RW
6197  */
6198 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
6199
6200 /* reg_ratr_a
6201  * Activity. Set for new entries. Set if a packet lookup has hit on
6202  * the specific entry. To clear the a bit, use "clear activity".
6203  * Access: RO
6204  */
6205 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
6206
6207 enum mlxsw_reg_ratr_type {
6208         /* Ethernet */
6209         MLXSW_REG_RATR_TYPE_ETHERNET,
6210         /* IPoIB Unicast without GRH.
6211          * Reserved for Spectrum.
6212          */
6213         MLXSW_REG_RATR_TYPE_IPOIB_UC,
6214         /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast
6215          * adjacency).
6216          * Reserved for Spectrum.
6217          */
6218         MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
6219         /* IPoIB Multicast.
6220          * Reserved for Spectrum.
6221          */
6222         MLXSW_REG_RATR_TYPE_IPOIB_MC,
6223         /* MPLS.
6224          * Reserved for SwitchX/-2.
6225          */
6226         MLXSW_REG_RATR_TYPE_MPLS,
6227         /* IPinIP Encap.
6228          * Reserved for SwitchX/-2.
6229          */
6230         MLXSW_REG_RATR_TYPE_IPIP,
6231 };
6232
6233 /* reg_ratr_type
6234  * Adjacency entry type.
6235  * Access: RW
6236  */
6237 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
6238
6239 /* reg_ratr_adjacency_index_low
6240  * Bits 15:0 of index into the adjacency table.
6241  * For SwitchX and SwitchX-2, the adjacency table is linear and
6242  * used for adjacency entries only.
6243  * For Spectrum, the index is to the KVD linear.
6244  * Access: Index
6245  */
6246 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
6247
6248 /* reg_ratr_egress_router_interface
6249  * Range is 0 .. cap_max_router_interfaces - 1
6250  * Access: RW
6251  */
6252 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
6253
6254 enum mlxsw_reg_ratr_trap_action {
6255         MLXSW_REG_RATR_TRAP_ACTION_NOP,
6256         MLXSW_REG_RATR_TRAP_ACTION_TRAP,
6257         MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
6258         MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
6259         MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
6260 };
6261
6262 /* reg_ratr_trap_action
6263  * see mlxsw_reg_ratr_trap_action
6264  * Access: RW
6265  */
6266 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
6267
6268 /* reg_ratr_adjacency_index_high
6269  * Bits 23:16 of the adjacency_index.
6270  * Access: Index
6271  */
6272 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
6273
6274 enum mlxsw_reg_ratr_trap_id {
6275         MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
6276         MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
6277 };
6278
6279 /* reg_ratr_trap_id
6280  * Trap ID to be reported to CPU.
6281  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
6282  * For trap_action of NOP, MIRROR and DISCARD_ERROR
6283  * Access: RW
6284  */
6285 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
6286
6287 /* reg_ratr_eth_destination_mac
6288  * MAC address of the destination next-hop.
6289  * Access: RW
6290  */
6291 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
6292
6293 enum mlxsw_reg_ratr_ipip_type {
6294         /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */
6295         MLXSW_REG_RATR_IPIP_TYPE_IPV4,
6296         /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */
6297         MLXSW_REG_RATR_IPIP_TYPE_IPV6,
6298 };
6299
6300 /* reg_ratr_ipip_type
6301  * Underlay destination ip type.
6302  * Note: the type field must match the protocol of the router interface.
6303  * Access: RW
6304  */
6305 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
6306
6307 /* reg_ratr_ipip_ipv4_udip
6308  * Underlay ipv4 dip.
6309  * Reserved when ipip_type is IPv6.
6310  * Access: RW
6311  */
6312 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
6313
6314 /* reg_ratr_ipip_ipv6_ptr
6315  * Pointer to IPv6 underlay destination ip address.
6316  * For Spectrum: Pointer to KVD linear space.
6317  * Access: RW
6318  */
6319 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
6320
6321 enum mlxsw_reg_flow_counter_set_type {
6322         /* No count */
6323         MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6324         /* Count packets and bytes */
6325         MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
6326         /* Count only packets */
6327         MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
6328 };
6329
6330 /* reg_ratr_counter_set_type
6331  * Counter set type for flow counters
6332  * Access: RW
6333  */
6334 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
6335
6336 /* reg_ratr_counter_index
6337  * Counter index for flow counters
6338  * Access: RW
6339  */
6340 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
6341
6342 static inline void
6343 mlxsw_reg_ratr_pack(char *payload,
6344                     enum mlxsw_reg_ratr_op op, bool valid,
6345                     enum mlxsw_reg_ratr_type type,
6346                     u32 adjacency_index, u16 egress_rif)
6347 {
6348         MLXSW_REG_ZERO(ratr, payload);
6349         mlxsw_reg_ratr_op_set(payload, op);
6350         mlxsw_reg_ratr_v_set(payload, valid);
6351         mlxsw_reg_ratr_type_set(payload, type);
6352         mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
6353         mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
6354         mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
6355 }
6356
6357 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
6358                                                  const char *dest_mac)
6359 {
6360         mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
6361 }
6362
6363 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
6364 {
6365         mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
6366         mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
6367 }
6368
6369 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
6370                                                bool counter_enable)
6371 {
6372         enum mlxsw_reg_flow_counter_set_type set_type;
6373
6374         if (counter_enable)
6375                 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
6376         else
6377                 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
6378
6379         mlxsw_reg_ratr_counter_index_set(payload, counter_index);
6380         mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
6381 }
6382
6383 /* RDPM - Router DSCP to Priority Mapping
6384  * --------------------------------------
6385  * Controls the mapping from DSCP field to switch priority on routed packets
6386  */
6387 #define MLXSW_REG_RDPM_ID 0x8009
6388 #define MLXSW_REG_RDPM_BASE_LEN 0x00
6389 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
6390 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
6391 #define MLXSW_REG_RDPM_LEN 0x40
6392 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
6393                                    MLXSW_REG_RDPM_LEN - \
6394                                    MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
6395
6396 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
6397
6398 /* reg_dscp_entry_e
6399  * Enable update of the specific entry
6400  * Access: Index
6401  */
6402 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
6403                     -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6404
6405 /* reg_dscp_entry_prio
6406  * Switch Priority
6407  * Access: RW
6408  */
6409 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
6410                     -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6411
6412 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
6413                                        u8 prio)
6414 {
6415         mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
6416         mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
6417 }
6418
6419 /* RICNT - Router Interface Counter Register
6420  * -----------------------------------------
6421  * The RICNT register retrieves per port performance counters
6422  */
6423 #define MLXSW_REG_RICNT_ID 0x800B
6424 #define MLXSW_REG_RICNT_LEN 0x100
6425
6426 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
6427
6428 /* reg_ricnt_counter_index
6429  * Counter index
6430  * Access: RW
6431  */
6432 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
6433
6434 enum mlxsw_reg_ricnt_counter_set_type {
6435         /* No Count. */
6436         MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6437         /* Basic. Used for router interfaces, counting the following:
6438          *      - Error and Discard counters.
6439          *      - Unicast, Multicast and Broadcast counters. Sharing the
6440          *        same set of counters for the different type of traffic
6441          *        (IPv4, IPv6 and mpls).
6442          */
6443         MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
6444 };
6445
6446 /* reg_ricnt_counter_set_type
6447  * Counter Set Type for router interface counter
6448  * Access: RW
6449  */
6450 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
6451
6452 enum mlxsw_reg_ricnt_opcode {
6453         /* Nop. Supported only for read access*/
6454         MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
6455         /* Clear. Setting the clr bit will reset the counter value for
6456          * all counters of the specified Router Interface.
6457          */
6458         MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
6459 };
6460
6461 /* reg_ricnt_opcode
6462  * Opcode
6463  * Access: RW
6464  */
6465 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
6466
6467 /* reg_ricnt_good_unicast_packets
6468  * good unicast packets.
6469  * Access: RW
6470  */
6471 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
6472
6473 /* reg_ricnt_good_multicast_packets
6474  * good multicast packets.
6475  * Access: RW
6476  */
6477 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
6478
6479 /* reg_ricnt_good_broadcast_packets
6480  * good broadcast packets
6481  * Access: RW
6482  */
6483 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
6484
6485 /* reg_ricnt_good_unicast_bytes
6486  * A count of L3 data and padding octets not including L2 headers
6487  * for good unicast frames.
6488  * Access: RW
6489  */
6490 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
6491
6492 /* reg_ricnt_good_multicast_bytes
6493  * A count of L3 data and padding octets not including L2 headers
6494  * for good multicast frames.
6495  * Access: RW
6496  */
6497 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
6498
6499 /* reg_ritr_good_broadcast_bytes
6500  * A count of L3 data and padding octets not including L2 headers
6501  * for good broadcast frames.
6502  * Access: RW
6503  */
6504 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
6505
6506 /* reg_ricnt_error_packets
6507  * A count of errored frames that do not pass the router checks.
6508  * Access: RW
6509  */
6510 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
6511
6512 /* reg_ricnt_discrad_packets
6513  * A count of non-errored frames that do not pass the router checks.
6514  * Access: RW
6515  */
6516 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
6517
6518 /* reg_ricnt_error_bytes
6519  * A count of L3 data and padding octets not including L2 headers
6520  * for errored frames.
6521  * Access: RW
6522  */
6523 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
6524
6525 /* reg_ricnt_discard_bytes
6526  * A count of L3 data and padding octets not including L2 headers
6527  * for non-errored frames that do not pass the router checks.
6528  * Access: RW
6529  */
6530 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
6531
6532 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
6533                                         enum mlxsw_reg_ricnt_opcode op)
6534 {
6535         MLXSW_REG_ZERO(ricnt, payload);
6536         mlxsw_reg_ricnt_op_set(payload, op);
6537         mlxsw_reg_ricnt_counter_index_set(payload, index);
6538         mlxsw_reg_ricnt_counter_set_type_set(payload,
6539                                              MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
6540 }
6541
6542 /* RRCR - Router Rules Copy Register Layout
6543  * ----------------------------------------
6544  * This register is used for moving and copying route entry rules.
6545  */
6546 #define MLXSW_REG_RRCR_ID 0x800F
6547 #define MLXSW_REG_RRCR_LEN 0x24
6548
6549 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
6550
6551 enum mlxsw_reg_rrcr_op {
6552         /* Move rules */
6553         MLXSW_REG_RRCR_OP_MOVE,
6554         /* Copy rules */
6555         MLXSW_REG_RRCR_OP_COPY,
6556 };
6557
6558 /* reg_rrcr_op
6559  * Access: WO
6560  */
6561 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
6562
6563 /* reg_rrcr_offset
6564  * Offset within the region from which to copy/move.
6565  * Access: Index
6566  */
6567 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
6568
6569 /* reg_rrcr_size
6570  * The number of rules to copy/move.
6571  * Access: WO
6572  */
6573 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
6574
6575 /* reg_rrcr_table_id
6576  * Identifier of the table on which to perform the operation. Encoding is the
6577  * same as in RTAR.key_type
6578  * Access: Index
6579  */
6580 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
6581
6582 /* reg_rrcr_dest_offset
6583  * Offset within the region to which to copy/move
6584  * Access: Index
6585  */
6586 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
6587
6588 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
6589                                        u16 offset, u16 size,
6590                                        enum mlxsw_reg_rtar_key_type table_id,
6591                                        u16 dest_offset)
6592 {
6593         MLXSW_REG_ZERO(rrcr, payload);
6594         mlxsw_reg_rrcr_op_set(payload, op);
6595         mlxsw_reg_rrcr_offset_set(payload, offset);
6596         mlxsw_reg_rrcr_size_set(payload, size);
6597         mlxsw_reg_rrcr_table_id_set(payload, table_id);
6598         mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
6599 }
6600
6601 /* RALTA - Router Algorithmic LPM Tree Allocation Register
6602  * -------------------------------------------------------
6603  * RALTA is used to allocate the LPM trees of the SHSPM method.
6604  */
6605 #define MLXSW_REG_RALTA_ID 0x8010
6606 #define MLXSW_REG_RALTA_LEN 0x04
6607
6608 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
6609
6610 /* reg_ralta_op
6611  * opcode (valid for Write, must be 0 on Read)
6612  * 0 - allocate a tree
6613  * 1 - deallocate a tree
6614  * Access: OP
6615  */
6616 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
6617
6618 enum mlxsw_reg_ralxx_protocol {
6619         MLXSW_REG_RALXX_PROTOCOL_IPV4,
6620         MLXSW_REG_RALXX_PROTOCOL_IPV6,
6621 };
6622
6623 /* reg_ralta_protocol
6624  * Protocol.
6625  * Deallocation opcode: Reserved.
6626  * Access: RW
6627  */
6628 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
6629
6630 /* reg_ralta_tree_id
6631  * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
6632  * the tree identifier (managed by software).
6633  * Note that tree_id 0 is allocated for a default-route tree.
6634  * Access: Index
6635  */
6636 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
6637
6638 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
6639                                         enum mlxsw_reg_ralxx_protocol protocol,
6640                                         u8 tree_id)
6641 {
6642         MLXSW_REG_ZERO(ralta, payload);
6643         mlxsw_reg_ralta_op_set(payload, !alloc);
6644         mlxsw_reg_ralta_protocol_set(payload, protocol);
6645         mlxsw_reg_ralta_tree_id_set(payload, tree_id);
6646 }
6647
6648 /* RALST - Router Algorithmic LPM Structure Tree Register
6649  * ------------------------------------------------------
6650  * RALST is used to set and query the structure of an LPM tree.
6651  * The structure of the tree must be sorted as a sorted binary tree, while
6652  * each node is a bin that is tagged as the length of the prefixes the lookup
6653  * will refer to. Therefore, bin X refers to a set of entries with prefixes
6654  * of X bits to match with the destination address. The bin 0 indicates
6655  * the default action, when there is no match of any prefix.
6656  */
6657 #define MLXSW_REG_RALST_ID 0x8011
6658 #define MLXSW_REG_RALST_LEN 0x104
6659
6660 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
6661
6662 /* reg_ralst_root_bin
6663  * The bin number of the root bin.
6664  * 0<root_bin=<(length of IP address)
6665  * For a default-route tree configure 0xff
6666  * Access: RW
6667  */
6668 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
6669
6670 /* reg_ralst_tree_id
6671  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6672  * Access: Index
6673  */
6674 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
6675
6676 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
6677 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
6678 #define MLXSW_REG_RALST_BIN_COUNT 128
6679
6680 /* reg_ralst_left_child_bin
6681  * Holding the children of the bin according to the stored tree's structure.
6682  * For trees composed of less than 4 blocks, the bins in excess are reserved.
6683  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6684  * Access: RW
6685  */
6686 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
6687
6688 /* reg_ralst_right_child_bin
6689  * Holding the children of the bin according to the stored tree's structure.
6690  * For trees composed of less than 4 blocks, the bins in excess are reserved.
6691  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6692  * Access: RW
6693  */
6694 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
6695                      false);
6696
6697 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
6698 {
6699         MLXSW_REG_ZERO(ralst, payload);
6700
6701         /* Initialize all bins to have no left or right child */
6702         memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
6703                MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
6704
6705         mlxsw_reg_ralst_root_bin_set(payload, root_bin);
6706         mlxsw_reg_ralst_tree_id_set(payload, tree_id);
6707 }
6708
6709 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
6710                                             u8 left_child_bin,
6711                                             u8 right_child_bin)
6712 {
6713         int bin_index = bin_number - 1;
6714
6715         mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
6716         mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
6717                                             right_child_bin);
6718 }
6719
6720 /* RALTB - Router Algorithmic LPM Tree Binding Register
6721  * ----------------------------------------------------
6722  * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
6723  */
6724 #define MLXSW_REG_RALTB_ID 0x8012
6725 #define MLXSW_REG_RALTB_LEN 0x04
6726
6727 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
6728
6729 /* reg_raltb_virtual_router
6730  * Virtual Router ID
6731  * Range is 0..cap_max_virtual_routers-1
6732  * Access: Index
6733  */
6734 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
6735
6736 /* reg_raltb_protocol
6737  * Protocol.
6738  * Access: Index
6739  */
6740 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
6741
6742 /* reg_raltb_tree_id
6743  * Tree to be used for the {virtual_router, protocol}
6744  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6745  * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
6746  * Access: RW
6747  */
6748 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
6749
6750 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
6751                                         enum mlxsw_reg_ralxx_protocol protocol,
6752                                         u8 tree_id)
6753 {
6754         MLXSW_REG_ZERO(raltb, payload);
6755         mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
6756         mlxsw_reg_raltb_protocol_set(payload, protocol);
6757         mlxsw_reg_raltb_tree_id_set(payload, tree_id);
6758 }
6759
6760 /* RALUE - Router Algorithmic LPM Unicast Entry Register
6761  * -----------------------------------------------------
6762  * RALUE is used to configure and query LPM entries that serve
6763  * the Unicast protocols.
6764  */
6765 #define MLXSW_REG_RALUE_ID 0x8013
6766 #define MLXSW_REG_RALUE_LEN 0x38
6767
6768 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
6769
6770 /* reg_ralue_protocol
6771  * Protocol.
6772  * Access: Index
6773  */
6774 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
6775
6776 enum mlxsw_reg_ralue_op {
6777         /* Read operation. If entry doesn't exist, the operation fails. */
6778         MLXSW_REG_RALUE_OP_QUERY_READ = 0,
6779         /* Clear on read operation. Used to read entry and
6780          * clear Activity bit.
6781          */
6782         MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
6783         /* Write operation. Used to write a new entry to the table. All RW
6784          * fields are written for new entry. Activity bit is set
6785          * for new entries.
6786          */
6787         MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
6788         /* Update operation. Used to update an existing route entry and
6789          * only update the RW fields that are detailed in the field
6790          * op_u_mask. If entry doesn't exist, the operation fails.
6791          */
6792         MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
6793         /* Clear activity. The Activity bit (the field a) is cleared
6794          * for the entry.
6795          */
6796         MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
6797         /* Delete operation. Used to delete an existing entry. If entry
6798          * doesn't exist, the operation fails.
6799          */
6800         MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
6801 };
6802
6803 /* reg_ralue_op
6804  * Operation.
6805  * Access: OP
6806  */
6807 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
6808
6809 /* reg_ralue_a
6810  * Activity. Set for new entries. Set if a packet lookup has hit on the
6811  * specific entry, only if the entry is a route. To clear the a bit, use
6812  * "clear activity" op.
6813  * Enabled by activity_dis in RGCR
6814  * Access: RO
6815  */
6816 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
6817
6818 /* reg_ralue_virtual_router
6819  * Virtual Router ID
6820  * Range is 0..cap_max_virtual_routers-1
6821  * Access: Index
6822  */
6823 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
6824
6825 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE    BIT(0)
6826 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN       BIT(1)
6827 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION        BIT(2)
6828
6829 /* reg_ralue_op_u_mask
6830  * opcode update mask.
6831  * On read operation, this field is reserved.
6832  * This field is valid for update opcode, otherwise - reserved.
6833  * This field is a bitmask of the fields that should be updated.
6834  * Access: WO
6835  */
6836 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
6837
6838 /* reg_ralue_prefix_len
6839  * Number of bits in the prefix of the LPM route.
6840  * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
6841  * two entries in the physical HW table.
6842  * Access: Index
6843  */
6844 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
6845
6846 /* reg_ralue_dip*
6847  * The prefix of the route or of the marker that the object of the LPM
6848  * is compared with. The most significant bits of the dip are the prefix.
6849  * The least significant bits must be '0' if the prefix_len is smaller
6850  * than 128 for IPv6 or smaller than 32 for IPv4.
6851  * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
6852  * Access: Index
6853  */
6854 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
6855 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
6856
6857 enum mlxsw_reg_ralue_entry_type {
6858         MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
6859         MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
6860         MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
6861 };
6862
6863 /* reg_ralue_entry_type
6864  * Entry type.
6865  * Note - for Marker entries, the action_type and action fields are reserved.
6866  * Access: RW
6867  */
6868 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
6869
6870 /* reg_ralue_bmp_len
6871  * The best match prefix length in the case that there is no match for
6872  * longer prefixes.
6873  * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
6874  * Note for any update operation with entry_type modification this
6875  * field must be set.
6876  * Access: RW
6877  */
6878 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
6879
6880 enum mlxsw_reg_ralue_action_type {
6881         MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
6882         MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
6883         MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
6884 };
6885
6886 /* reg_ralue_action_type
6887  * Action Type
6888  * Indicates how the IP address is connected.
6889  * It can be connected to a local subnet through local_erif or can be
6890  * on a remote subnet connected through a next-hop router,
6891  * or transmitted to the CPU.
6892  * Reserved when entry_type = MARKER_ENTRY
6893  * Access: RW
6894  */
6895 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
6896
6897 enum mlxsw_reg_ralue_trap_action {
6898         MLXSW_REG_RALUE_TRAP_ACTION_NOP,
6899         MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
6900         MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
6901         MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
6902         MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
6903 };
6904
6905 /* reg_ralue_trap_action
6906  * Trap action.
6907  * For IP2ME action, only NOP and MIRROR are possible.
6908  * Access: RW
6909  */
6910 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
6911
6912 /* reg_ralue_trap_id
6913  * Trap ID to be reported to CPU.
6914  * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
6915  * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
6916  * Access: RW
6917  */
6918 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
6919
6920 /* reg_ralue_adjacency_index
6921  * Points to the first entry of the group-based ECMP.
6922  * Only relevant in case of REMOTE action.
6923  * Access: RW
6924  */
6925 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
6926
6927 /* reg_ralue_ecmp_size
6928  * Amount of sequential entries starting
6929  * from the adjacency_index (the number of ECMPs).
6930  * The valid range is 1-64, 512, 1024, 2048 and 4096.
6931  * Reserved when trap_action is TRAP or DISCARD_ERROR.
6932  * Only relevant in case of REMOTE action.
6933  * Access: RW
6934  */
6935 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
6936
6937 /* reg_ralue_local_erif
6938  * Egress Router Interface.
6939  * Only relevant in case of LOCAL action.
6940  * Access: RW
6941  */
6942 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
6943
6944 /* reg_ralue_ip2me_v
6945  * Valid bit for the tunnel_ptr field.
6946  * If valid = 0 then trap to CPU as IP2ME trap ID.
6947  * If valid = 1 and the packet format allows NVE or IPinIP tunnel
6948  * decapsulation then tunnel decapsulation is done.
6949  * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
6950  * decapsulation then trap as IP2ME trap ID.
6951  * Only relevant in case of IP2ME action.
6952  * Access: RW
6953  */
6954 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
6955
6956 /* reg_ralue_ip2me_tunnel_ptr
6957  * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
6958  * For Spectrum, pointer to KVD Linear.
6959  * Only relevant in case of IP2ME action.
6960  * Access: RW
6961  */
6962 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
6963
6964 static inline void mlxsw_reg_ralue_pack(char *payload,
6965                                         enum mlxsw_reg_ralxx_protocol protocol,
6966                                         enum mlxsw_reg_ralue_op op,
6967                                         u16 virtual_router, u8 prefix_len)
6968 {
6969         MLXSW_REG_ZERO(ralue, payload);
6970         mlxsw_reg_ralue_protocol_set(payload, protocol);
6971         mlxsw_reg_ralue_op_set(payload, op);
6972         mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
6973         mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
6974         mlxsw_reg_ralue_entry_type_set(payload,
6975                                        MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
6976         mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
6977 }
6978
6979 static inline void mlxsw_reg_ralue_pack4(char *payload,
6980                                          enum mlxsw_reg_ralxx_protocol protocol,
6981                                          enum mlxsw_reg_ralue_op op,
6982                                          u16 virtual_router, u8 prefix_len,
6983                                          u32 dip)
6984 {
6985         mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6986         mlxsw_reg_ralue_dip4_set(payload, dip);
6987 }
6988
6989 static inline void mlxsw_reg_ralue_pack6(char *payload,
6990                                          enum mlxsw_reg_ralxx_protocol protocol,
6991                                          enum mlxsw_reg_ralue_op op,
6992                                          u16 virtual_router, u8 prefix_len,
6993                                          const void *dip)
6994 {
6995         mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6996         mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
6997 }
6998
6999 static inline void
7000 mlxsw_reg_ralue_act_remote_pack(char *payload,
7001                                 enum mlxsw_reg_ralue_trap_action trap_action,
7002                                 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
7003 {
7004         mlxsw_reg_ralue_action_type_set(payload,
7005                                         MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
7006         mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7007         mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7008         mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
7009         mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
7010 }
7011
7012 static inline void
7013 mlxsw_reg_ralue_act_local_pack(char *payload,
7014                                enum mlxsw_reg_ralue_trap_action trap_action,
7015                                u16 trap_id, u16 local_erif)
7016 {
7017         mlxsw_reg_ralue_action_type_set(payload,
7018                                         MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
7019         mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7020         mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7021         mlxsw_reg_ralue_local_erif_set(payload, local_erif);
7022 }
7023
7024 static inline void
7025 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
7026 {
7027         mlxsw_reg_ralue_action_type_set(payload,
7028                                         MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7029 }
7030
7031 static inline void
7032 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
7033 {
7034         mlxsw_reg_ralue_action_type_set(payload,
7035                                         MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7036         mlxsw_reg_ralue_ip2me_v_set(payload, 1);
7037         mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
7038 }
7039
7040 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
7041  * ----------------------------------------------------------
7042  * The RAUHT register is used to configure and query the Unicast Host table in
7043  * devices that implement the Algorithmic LPM.
7044  */
7045 #define MLXSW_REG_RAUHT_ID 0x8014
7046 #define MLXSW_REG_RAUHT_LEN 0x74
7047
7048 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
7049
7050 enum mlxsw_reg_rauht_type {
7051         MLXSW_REG_RAUHT_TYPE_IPV4,
7052         MLXSW_REG_RAUHT_TYPE_IPV6,
7053 };
7054
7055 /* reg_rauht_type
7056  * Access: Index
7057  */
7058 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
7059
7060 enum mlxsw_reg_rauht_op {
7061         MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
7062         /* Read operation */
7063         MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
7064         /* Clear on read operation. Used to read entry and clear
7065          * activity bit.
7066          */
7067         MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
7068         /* Add. Used to write a new entry to the table. All R/W fields are
7069          * relevant for new entry. Activity bit is set for new entries.
7070          */
7071         MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
7072         /* Update action. Used to update an existing route entry and
7073          * only update the following fields:
7074          * trap_action, trap_id, mac, counter_set_type, counter_index
7075          */
7076         MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
7077         /* Clear activity. A bit is cleared for the entry. */
7078         MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
7079         /* Delete entry */
7080         MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
7081         /* Delete all host entries on a RIF. In this command, dip
7082          * field is reserved.
7083          */
7084 };
7085
7086 /* reg_rauht_op
7087  * Access: OP
7088  */
7089 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
7090
7091 /* reg_rauht_a
7092  * Activity. Set for new entries. Set if a packet lookup has hit on
7093  * the specific entry.
7094  * To clear the a bit, use "clear activity" op.
7095  * Enabled by activity_dis in RGCR
7096  * Access: RO
7097  */
7098 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
7099
7100 /* reg_rauht_rif
7101  * Router Interface
7102  * Access: Index
7103  */
7104 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
7105
7106 /* reg_rauht_dip*
7107  * Destination address.
7108  * Access: Index
7109  */
7110 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
7111 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
7112
7113 enum mlxsw_reg_rauht_trap_action {
7114         MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
7115         MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
7116         MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
7117         MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
7118         MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
7119 };
7120
7121 /* reg_rauht_trap_action
7122  * Access: RW
7123  */
7124 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
7125
7126 enum mlxsw_reg_rauht_trap_id {
7127         MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
7128         MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
7129 };
7130
7131 /* reg_rauht_trap_id
7132  * Trap ID to be reported to CPU.
7133  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
7134  * For trap_action of NOP, MIRROR and DISCARD_ERROR,
7135  * trap_id is reserved.
7136  * Access: RW
7137  */
7138 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
7139
7140 /* reg_rauht_counter_set_type
7141  * Counter set type for flow counters
7142  * Access: RW
7143  */
7144 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
7145
7146 /* reg_rauht_counter_index
7147  * Counter index for flow counters
7148  * Access: RW
7149  */
7150 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
7151
7152 /* reg_rauht_mac
7153  * MAC address.
7154  * Access: RW
7155  */
7156 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
7157
7158 static inline void mlxsw_reg_rauht_pack(char *payload,
7159                                         enum mlxsw_reg_rauht_op op, u16 rif,
7160                                         const char *mac)
7161 {
7162         MLXSW_REG_ZERO(rauht, payload);
7163         mlxsw_reg_rauht_op_set(payload, op);
7164         mlxsw_reg_rauht_rif_set(payload, rif);
7165         mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
7166 }
7167
7168 static inline void mlxsw_reg_rauht_pack4(char *payload,
7169                                          enum mlxsw_reg_rauht_op op, u16 rif,
7170                                          const char *mac, u32 dip)
7171 {
7172         mlxsw_reg_rauht_pack(payload, op, rif, mac);
7173         mlxsw_reg_rauht_dip4_set(payload, dip);
7174 }
7175
7176 static inline void mlxsw_reg_rauht_pack6(char *payload,
7177                                          enum mlxsw_reg_rauht_op op, u16 rif,
7178                                          const char *mac, const char *dip)
7179 {
7180         mlxsw_reg_rauht_pack(payload, op, rif, mac);
7181         mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
7182         mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
7183 }
7184
7185 static inline void mlxsw_reg_rauht_pack_counter(char *payload,
7186                                                 u64 counter_index)
7187 {
7188         mlxsw_reg_rauht_counter_index_set(payload, counter_index);
7189         mlxsw_reg_rauht_counter_set_type_set(payload,
7190                                              MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
7191 }
7192
7193 /* RALEU - Router Algorithmic LPM ECMP Update Register
7194  * ---------------------------------------------------
7195  * The register enables updating the ECMP section in the action for multiple
7196  * LPM Unicast entries in a single operation. The update is executed to
7197  * all entries of a {virtual router, protocol} tuple using the same ECMP group.
7198  */
7199 #define MLXSW_REG_RALEU_ID 0x8015
7200 #define MLXSW_REG_RALEU_LEN 0x28
7201
7202 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
7203
7204 /* reg_raleu_protocol
7205  * Protocol.
7206  * Access: Index
7207  */
7208 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
7209
7210 /* reg_raleu_virtual_router
7211  * Virtual Router ID
7212  * Range is 0..cap_max_virtual_routers-1
7213  * Access: Index
7214  */
7215 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
7216
7217 /* reg_raleu_adjacency_index
7218  * Adjacency Index used for matching on the existing entries.
7219  * Access: Index
7220  */
7221 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
7222
7223 /* reg_raleu_ecmp_size
7224  * ECMP Size used for matching on the existing entries.
7225  * Access: Index
7226  */
7227 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
7228
7229 /* reg_raleu_new_adjacency_index
7230  * New Adjacency Index.
7231  * Access: WO
7232  */
7233 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
7234
7235 /* reg_raleu_new_ecmp_size
7236  * New ECMP Size.
7237  * Access: WO
7238  */
7239 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
7240
7241 static inline void mlxsw_reg_raleu_pack(char *payload,
7242                                         enum mlxsw_reg_ralxx_protocol protocol,
7243                                         u16 virtual_router,
7244                                         u32 adjacency_index, u16 ecmp_size,
7245                                         u32 new_adjacency_index,
7246                                         u16 new_ecmp_size)
7247 {
7248         MLXSW_REG_ZERO(raleu, payload);
7249         mlxsw_reg_raleu_protocol_set(payload, protocol);
7250         mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
7251         mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
7252         mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
7253         mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
7254         mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
7255 }
7256
7257 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
7258  * ----------------------------------------------------------------
7259  * The RAUHTD register allows dumping entries from the Router Unicast Host
7260  * Table. For a given session an entry is dumped no more than one time. The
7261  * first RAUHTD access after reset is a new session. A session ends when the
7262  * num_rec response is smaller than num_rec request or for IPv4 when the
7263  * num_entries is smaller than 4. The clear activity affect the current session
7264  * or the last session if a new session has not started.
7265  */
7266 #define MLXSW_REG_RAUHTD_ID 0x8018
7267 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
7268 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
7269 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
7270 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
7271                 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
7272 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
7273
7274 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
7275
7276 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
7277 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
7278
7279 /* reg_rauhtd_filter_fields
7280  * if a bit is '0' then the relevant field is ignored and dump is done
7281  * regardless of the field value
7282  * Bit0 - filter by activity: entry_a
7283  * Bit3 - filter by entry rip: entry_rif
7284  * Access: Index
7285  */
7286 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
7287
7288 enum mlxsw_reg_rauhtd_op {
7289         MLXSW_REG_RAUHTD_OP_DUMP,
7290         MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
7291 };
7292
7293 /* reg_rauhtd_op
7294  * Access: OP
7295  */
7296 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
7297
7298 /* reg_rauhtd_num_rec
7299  * At request: number of records requested
7300  * At response: number of records dumped
7301  * For IPv4, each record has 4 entries at request and up to 4 entries
7302  * at response
7303  * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
7304  * Access: Index
7305  */
7306 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
7307
7308 /* reg_rauhtd_entry_a
7309  * Dump only if activity has value of entry_a
7310  * Reserved if filter_fields bit0 is '0'
7311  * Access: Index
7312  */
7313 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
7314
7315 enum mlxsw_reg_rauhtd_type {
7316         MLXSW_REG_RAUHTD_TYPE_IPV4,
7317         MLXSW_REG_RAUHTD_TYPE_IPV6,
7318 };
7319
7320 /* reg_rauhtd_type
7321  * Dump only if record type is:
7322  * 0 - IPv4
7323  * 1 - IPv6
7324  * Access: Index
7325  */
7326 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
7327
7328 /* reg_rauhtd_entry_rif
7329  * Dump only if RIF has value of entry_rif
7330  * Reserved if filter_fields bit3 is '0'
7331  * Access: Index
7332  */
7333 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
7334
7335 static inline void mlxsw_reg_rauhtd_pack(char *payload,
7336                                          enum mlxsw_reg_rauhtd_type type)
7337 {
7338         MLXSW_REG_ZERO(rauhtd, payload);
7339         mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
7340         mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
7341         mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
7342         mlxsw_reg_rauhtd_entry_a_set(payload, 1);
7343         mlxsw_reg_rauhtd_type_set(payload, type);
7344 }
7345
7346 /* reg_rauhtd_ipv4_rec_num_entries
7347  * Number of valid entries in this record:
7348  * 0 - 1 valid entry
7349  * 1 - 2 valid entries
7350  * 2 - 3 valid entries
7351  * 3 - 4 valid entries
7352  * Access: RO
7353  */
7354 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
7355                      MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
7356                      MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7357
7358 /* reg_rauhtd_rec_type
7359  * Record type.
7360  * 0 - IPv4
7361  * 1 - IPv6
7362  * Access: RO
7363  */
7364 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
7365                      MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7366
7367 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
7368
7369 /* reg_rauhtd_ipv4_ent_a
7370  * Activity. Set for new entries. Set if a packet lookup has hit on the
7371  * specific entry.
7372  * Access: RO
7373  */
7374 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7375                      MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7376
7377 /* reg_rauhtd_ipv4_ent_rif
7378  * Router interface.
7379  * Access: RO
7380  */
7381 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7382                      16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7383
7384 /* reg_rauhtd_ipv4_ent_dip
7385  * Destination IPv4 address.
7386  * Access: RO
7387  */
7388 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7389                      32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
7390
7391 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
7392
7393 /* reg_rauhtd_ipv6_ent_a
7394  * Activity. Set for new entries. Set if a packet lookup has hit on the
7395  * specific entry.
7396  * Access: RO
7397  */
7398 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7399                      MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7400
7401 /* reg_rauhtd_ipv6_ent_rif
7402  * Router interface.
7403  * Access: RO
7404  */
7405 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7406                      16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7407
7408 /* reg_rauhtd_ipv6_ent_dip
7409  * Destination IPv6 address.
7410  * Access: RO
7411  */
7412 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
7413                        16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
7414
7415 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
7416                                                     int ent_index, u16 *p_rif,
7417                                                     u32 *p_dip)
7418 {
7419         *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
7420         *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
7421 }
7422
7423 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
7424                                                     int rec_index, u16 *p_rif,
7425                                                     char *p_dip)
7426 {
7427         *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
7428         mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
7429 }
7430
7431 /* RTDP - Routing Tunnel Decap Properties Register
7432  * -----------------------------------------------
7433  * The RTDP register is used for configuring the tunnel decap properties of NVE
7434  * and IPinIP.
7435  */
7436 #define MLXSW_REG_RTDP_ID 0x8020
7437 #define MLXSW_REG_RTDP_LEN 0x44
7438
7439 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
7440
7441 enum mlxsw_reg_rtdp_type {
7442         MLXSW_REG_RTDP_TYPE_NVE,
7443         MLXSW_REG_RTDP_TYPE_IPIP,
7444 };
7445
7446 /* reg_rtdp_type
7447  * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type.
7448  * Access: RW
7449  */
7450 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
7451
7452 /* reg_rtdp_tunnel_index
7453  * Index to the Decap entry.
7454  * For Spectrum, Index to KVD Linear.
7455  * Access: Index
7456  */
7457 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
7458
7459 /* reg_rtdp_egress_router_interface
7460  * Underlay egress router interface.
7461  * Valid range is from 0 to cap_max_router_interfaces - 1
7462  * Access: RW
7463  */
7464 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
7465
7466 /* IPinIP */
7467
7468 /* reg_rtdp_ipip_irif
7469  * Ingress Router Interface for the overlay router
7470  * Access: RW
7471  */
7472 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
7473
7474 enum mlxsw_reg_rtdp_ipip_sip_check {
7475         /* No sip checks. */
7476         MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
7477         /* Filter packet if underlay is not IPv4 or if underlay SIP does not
7478          * equal ipv4_usip.
7479          */
7480         MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
7481         /* Filter packet if underlay is not IPv6 or if underlay SIP does not
7482          * equal ipv6_usip.
7483          */
7484         MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
7485 };
7486
7487 /* reg_rtdp_ipip_sip_check
7488  * SIP check to perform. If decapsulation failed due to these configurations
7489  * then trap_id is IPIP_DECAP_ERROR.
7490  * Access: RW
7491  */
7492 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
7493
7494 /* If set, allow decapsulation of IPinIP (without GRE). */
7495 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP       BIT(0)
7496 /* If set, allow decapsulation of IPinGREinIP without a key. */
7497 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE        BIT(1)
7498 /* If set, allow decapsulation of IPinGREinIP with a key. */
7499 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY    BIT(2)
7500
7501 /* reg_rtdp_ipip_type_check
7502  * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to
7503  * these configurations then trap_id is IPIP_DECAP_ERROR.
7504  * Access: RW
7505  */
7506 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
7507
7508 /* reg_rtdp_ipip_gre_key_check
7509  * Whether GRE key should be checked. When check is enabled:
7510  * - A packet received as IPinIP (without GRE) will always pass.
7511  * - A packet received as IPinGREinIP without a key will not pass the check.
7512  * - A packet received as IPinGREinIP with a key will pass the check only if the
7513  *   key in the packet is equal to expected_gre_key.
7514  * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR.
7515  * Access: RW
7516  */
7517 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
7518
7519 /* reg_rtdp_ipip_ipv4_usip
7520  * Underlay IPv4 address for ipv4 source address check.
7521  * Reserved when sip_check is not '1'.
7522  * Access: RW
7523  */
7524 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
7525
7526 /* reg_rtdp_ipip_ipv6_usip_ptr
7527  * This field is valid when sip_check is "sipv6 check explicitly". This is a
7528  * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index
7529  * is to the KVD linear.
7530  * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6.
7531  * Access: RW
7532  */
7533 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
7534
7535 /* reg_rtdp_ipip_expected_gre_key
7536  * GRE key for checking.
7537  * Reserved when gre_key_check is '0'.
7538  * Access: RW
7539  */
7540 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
7541
7542 static inline void mlxsw_reg_rtdp_pack(char *payload,
7543                                        enum mlxsw_reg_rtdp_type type,
7544                                        u32 tunnel_index)
7545 {
7546         MLXSW_REG_ZERO(rtdp, payload);
7547         mlxsw_reg_rtdp_type_set(payload, type);
7548         mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
7549 }
7550
7551 static inline void
7552 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
7553                           enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
7554                           unsigned int type_check, bool gre_key_check,
7555                           u32 ipv4_usip, u32 expected_gre_key)
7556 {
7557         mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
7558         mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
7559         mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
7560         mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
7561         mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
7562         mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
7563 }
7564
7565 /* RIGR-V2 - Router Interface Group Register Version 2
7566  * ---------------------------------------------------
7567  * The RIGR_V2 register is used to add, remove and query egress interface list
7568  * of a multicast forwarding entry.
7569  */
7570 #define MLXSW_REG_RIGR2_ID 0x8023
7571 #define MLXSW_REG_RIGR2_LEN 0xB0
7572
7573 #define MLXSW_REG_RIGR2_MAX_ERIFS 32
7574
7575 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
7576
7577 /* reg_rigr2_rigr_index
7578  * KVD Linear index.
7579  * Access: Index
7580  */
7581 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
7582
7583 /* reg_rigr2_vnext
7584  * Next RIGR Index is valid.
7585  * Access: RW
7586  */
7587 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
7588
7589 /* reg_rigr2_next_rigr_index
7590  * Next RIGR Index. The index is to the KVD linear.
7591  * Reserved when vnxet = '0'.
7592  * Access: RW
7593  */
7594 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
7595
7596 /* reg_rigr2_vrmid
7597  * RMID Index is valid.
7598  * Access: RW
7599  */
7600 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
7601
7602 /* reg_rigr2_rmid_index
7603  * RMID Index.
7604  * Range 0 .. max_mid - 1
7605  * Reserved when vrmid = '0'.
7606  * The index is to the Port Group Table (PGT)
7607  * Access: RW
7608  */
7609 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
7610
7611 /* reg_rigr2_erif_entry_v
7612  * Egress Router Interface is valid.
7613  * Note that low-entries must be set if high-entries are set. For
7614  * example: if erif_entry[2].v is set then erif_entry[1].v and
7615  * erif_entry[0].v must be set.
7616  * Index can be from 0 to cap_mc_erif_list_entries-1
7617  * Access: RW
7618  */
7619 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
7620
7621 /* reg_rigr2_erif_entry_erif
7622  * Egress Router Interface.
7623  * Valid range is from 0 to cap_max_router_interfaces - 1
7624  * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1
7625  * Access: RW
7626  */
7627 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
7628
7629 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
7630                                         bool vnext, u32 next_rigr_index)
7631 {
7632         MLXSW_REG_ZERO(rigr2, payload);
7633         mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
7634         mlxsw_reg_rigr2_vnext_set(payload, vnext);
7635         mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
7636         mlxsw_reg_rigr2_vrmid_set(payload, 0);
7637         mlxsw_reg_rigr2_rmid_index_set(payload, 0);
7638 }
7639
7640 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
7641                                                    bool v, u16 erif)
7642 {
7643         mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
7644         mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
7645 }
7646
7647 /* RECR-V2 - Router ECMP Configuration Version 2 Register
7648  * ------------------------------------------------------
7649  */
7650 #define MLXSW_REG_RECR2_ID 0x8025
7651 #define MLXSW_REG_RECR2_LEN 0x38
7652
7653 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
7654
7655 /* reg_recr2_pp
7656  * Per-port configuration
7657  * Access: Index
7658  */
7659 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
7660
7661 /* reg_recr2_sh
7662  * Symmetric hash
7663  * Access: RW
7664  */
7665 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
7666
7667 /* reg_recr2_seed
7668  * Seed
7669  * Access: RW
7670  */
7671 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
7672
7673 enum {
7674         /* Enable IPv4 fields if packet is not TCP and not UDP */
7675         MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3,
7676         /* Enable IPv4 fields if packet is TCP or UDP */
7677         MLXSW_REG_RECR2_IPV4_EN_TCP_UDP         = 4,
7678         /* Enable IPv6 fields if packet is not TCP and not UDP */
7679         MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5,
7680         /* Enable IPv6 fields if packet is TCP or UDP */
7681         MLXSW_REG_RECR2_IPV6_EN_TCP_UDP         = 6,
7682         /* Enable TCP/UDP header fields if packet is IPv4 */
7683         MLXSW_REG_RECR2_TCP_UDP_EN_IPV4         = 7,
7684         /* Enable TCP/UDP header fields if packet is IPv6 */
7685         MLXSW_REG_RECR2_TCP_UDP_EN_IPV6         = 8,
7686 };
7687
7688 /* reg_recr2_outer_header_enables
7689  * Bit mask where each bit enables a specific layer to be included in
7690  * the hash calculation.
7691  * Access: RW
7692  */
7693 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
7694
7695 enum {
7696         /* IPv4 Source IP */
7697         MLXSW_REG_RECR2_IPV4_SIP0                       = 9,
7698         MLXSW_REG_RECR2_IPV4_SIP3                       = 12,
7699         /* IPv4 Destination IP */
7700         MLXSW_REG_RECR2_IPV4_DIP0                       = 13,
7701         MLXSW_REG_RECR2_IPV4_DIP3                       = 16,
7702         /* IP Protocol */
7703         MLXSW_REG_RECR2_IPV4_PROTOCOL                   = 17,
7704         /* IPv6 Source IP */
7705         MLXSW_REG_RECR2_IPV6_SIP0_7                     = 21,
7706         MLXSW_REG_RECR2_IPV6_SIP8                       = 29,
7707         MLXSW_REG_RECR2_IPV6_SIP15                      = 36,
7708         /* IPv6 Destination IP */
7709         MLXSW_REG_RECR2_IPV6_DIP0_7                     = 37,
7710         MLXSW_REG_RECR2_IPV6_DIP8                       = 45,
7711         MLXSW_REG_RECR2_IPV6_DIP15                      = 52,
7712         /* IPv6 Next Header */
7713         MLXSW_REG_RECR2_IPV6_NEXT_HEADER                = 53,
7714         /* IPv6 Flow Label */
7715         MLXSW_REG_RECR2_IPV6_FLOW_LABEL                 = 57,
7716         /* TCP/UDP Source Port */
7717         MLXSW_REG_RECR2_TCP_UDP_SPORT                   = 74,
7718         /* TCP/UDP Destination Port */
7719         MLXSW_REG_RECR2_TCP_UDP_DPORT                   = 75,
7720 };
7721
7722 /* reg_recr2_outer_header_fields_enable
7723  * Packet fields to enable for ECMP hash subject to outer_header_enable.
7724  * Access: RW
7725  */
7726 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
7727
7728 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload)
7729 {
7730         int i;
7731
7732         for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++)
7733                 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7734                                                                true);
7735 }
7736
7737 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload)
7738 {
7739         int i;
7740
7741         for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++)
7742                 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7743                                                                true);
7744 }
7745
7746 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload)
7747 {
7748         int i = MLXSW_REG_RECR2_IPV6_SIP0_7;
7749
7750         mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7751
7752         i = MLXSW_REG_RECR2_IPV6_SIP8;
7753         for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++)
7754                 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7755                                                                true);
7756 }
7757
7758 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload)
7759 {
7760         int i = MLXSW_REG_RECR2_IPV6_DIP0_7;
7761
7762         mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7763
7764         i = MLXSW_REG_RECR2_IPV6_DIP8;
7765         for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++)
7766                 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7767                                                                true);
7768 }
7769
7770 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
7771 {
7772         MLXSW_REG_ZERO(recr2, payload);
7773         mlxsw_reg_recr2_pp_set(payload, false);
7774         mlxsw_reg_recr2_sh_set(payload, true);
7775         mlxsw_reg_recr2_seed_set(payload, seed);
7776 }
7777
7778 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register
7779  * --------------------------------------------------------------
7780  * The RMFT_V2 register is used to configure and query the multicast table.
7781  */
7782 #define MLXSW_REG_RMFT2_ID 0x8027
7783 #define MLXSW_REG_RMFT2_LEN 0x174
7784
7785 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
7786
7787 /* reg_rmft2_v
7788  * Valid
7789  * Access: RW
7790  */
7791 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
7792
7793 enum mlxsw_reg_rmft2_type {
7794         MLXSW_REG_RMFT2_TYPE_IPV4,
7795         MLXSW_REG_RMFT2_TYPE_IPV6
7796 };
7797
7798 /* reg_rmft2_type
7799  * Access: Index
7800  */
7801 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
7802
7803 enum mlxsw_sp_reg_rmft2_op {
7804         /* For Write:
7805          * Write operation. Used to write a new entry to the table. All RW
7806          * fields are relevant for new entry. Activity bit is set for new
7807          * entries - Note write with v (Valid) 0 will delete the entry.
7808          * For Query:
7809          * Read operation
7810          */
7811         MLXSW_REG_RMFT2_OP_READ_WRITE,
7812 };
7813
7814 /* reg_rmft2_op
7815  * Operation.
7816  * Access: OP
7817  */
7818 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
7819
7820 /* reg_rmft2_a
7821  * Activity. Set for new entries. Set if a packet lookup has hit on the specific
7822  * entry.
7823  * Access: RO
7824  */
7825 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
7826
7827 /* reg_rmft2_offset
7828  * Offset within the multicast forwarding table to write to.
7829  * Access: Index
7830  */
7831 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
7832
7833 /* reg_rmft2_virtual_router
7834  * Virtual Router ID. Range from 0..cap_max_virtual_routers-1
7835  * Access: RW
7836  */
7837 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
7838
7839 enum mlxsw_reg_rmft2_irif_mask {
7840         MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
7841         MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
7842 };
7843
7844 /* reg_rmft2_irif_mask
7845  * Ingress RIF mask.
7846  * Access: RW
7847  */
7848 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
7849
7850 /* reg_rmft2_irif
7851  * Ingress RIF index.
7852  * Access: RW
7853  */
7854 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
7855
7856 /* reg_rmft2_dip{4,6}
7857  * Destination IPv4/6 address
7858  * Access: RW
7859  */
7860 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
7861 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
7862
7863 /* reg_rmft2_dip{4,6}_mask
7864  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7865  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7866  * Access: RW
7867  */
7868 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
7869 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
7870
7871 /* reg_rmft2_sip{4,6}
7872  * Source IPv4/6 address
7873  * Access: RW
7874  */
7875 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
7876 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
7877
7878 /* reg_rmft2_sip{4,6}_mask
7879  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7880  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7881  * Access: RW
7882  */
7883 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
7884 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
7885
7886 /* reg_rmft2_flexible_action_set
7887  * ACL action set. The only supported action types in this field and in any
7888  * action-set pointed from here are as follows:
7889  * 00h: ACTION_NULL
7890  * 01h: ACTION_MAC_TTL, only TTL configuration is supported.
7891  * 03h: ACTION_TRAP
7892  * 06h: ACTION_QOS
7893  * 08h: ACTION_POLICING_MONITORING
7894  * 10h: ACTION_ROUTER_MC
7895  * Access: RW
7896  */
7897 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
7898                MLXSW_REG_FLEX_ACTION_SET_LEN);
7899
7900 static inline void
7901 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
7902                             u16 virtual_router,
7903                             enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7904                             const char *flex_action_set)
7905 {
7906         MLXSW_REG_ZERO(rmft2, payload);
7907         mlxsw_reg_rmft2_v_set(payload, v);
7908         mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
7909         mlxsw_reg_rmft2_offset_set(payload, offset);
7910         mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
7911         mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
7912         mlxsw_reg_rmft2_irif_set(payload, irif);
7913         if (flex_action_set)
7914                 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
7915                                                               flex_action_set);
7916 }
7917
7918 static inline void
7919 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7920                           enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7921                           u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
7922                           const char *flexible_action_set)
7923 {
7924         mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7925                                     irif_mask, irif, flexible_action_set);
7926         mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
7927         mlxsw_reg_rmft2_dip4_set(payload, dip4);
7928         mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
7929         mlxsw_reg_rmft2_sip4_set(payload, sip4);
7930         mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
7931 }
7932
7933 static inline void
7934 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7935                           enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7936                           struct in6_addr dip6, struct in6_addr dip6_mask,
7937                           struct in6_addr sip6, struct in6_addr sip6_mask,
7938                           const char *flexible_action_set)
7939 {
7940         mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7941                                     irif_mask, irif, flexible_action_set);
7942         mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
7943         mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
7944         mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
7945         mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
7946         mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
7947 }
7948
7949 /* MFCR - Management Fan Control Register
7950  * --------------------------------------
7951  * This register controls the settings of the Fan Speed PWM mechanism.
7952  */
7953 #define MLXSW_REG_MFCR_ID 0x9001
7954 #define MLXSW_REG_MFCR_LEN 0x08
7955
7956 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
7957
7958 enum mlxsw_reg_mfcr_pwm_frequency {
7959         MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
7960         MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
7961         MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
7962         MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
7963         MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
7964         MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
7965         MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
7966         MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
7967 };
7968
7969 /* reg_mfcr_pwm_frequency
7970  * Controls the frequency of the PWM signal.
7971  * Access: RW
7972  */
7973 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
7974
7975 #define MLXSW_MFCR_TACHOS_MAX 10
7976
7977 /* reg_mfcr_tacho_active
7978  * Indicates which of the tachometer is active (bit per tachometer).
7979  * Access: RO
7980  */
7981 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
7982
7983 #define MLXSW_MFCR_PWMS_MAX 5
7984
7985 /* reg_mfcr_pwm_active
7986  * Indicates which of the PWM control is active (bit per PWM).
7987  * Access: RO
7988  */
7989 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
7990
7991 static inline void
7992 mlxsw_reg_mfcr_pack(char *payload,
7993                     enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
7994 {
7995         MLXSW_REG_ZERO(mfcr, payload);
7996         mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
7997 }
7998
7999 static inline void
8000 mlxsw_reg_mfcr_unpack(char *payload,
8001                       enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
8002                       u16 *p_tacho_active, u8 *p_pwm_active)
8003 {
8004         *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
8005         *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
8006         *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
8007 }
8008
8009 /* MFSC - Management Fan Speed Control Register
8010  * --------------------------------------------
8011  * This register controls the settings of the Fan Speed PWM mechanism.
8012  */
8013 #define MLXSW_REG_MFSC_ID 0x9002
8014 #define MLXSW_REG_MFSC_LEN 0x08
8015
8016 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
8017
8018 /* reg_mfsc_pwm
8019  * Fan pwm to control / monitor.
8020  * Access: Index
8021  */
8022 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
8023
8024 /* reg_mfsc_pwm_duty_cycle
8025  * Controls the duty cycle of the PWM. Value range from 0..255 to
8026  * represent duty cycle of 0%...100%.
8027  * Access: RW
8028  */
8029 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
8030
8031 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
8032                                        u8 pwm_duty_cycle)
8033 {
8034         MLXSW_REG_ZERO(mfsc, payload);
8035         mlxsw_reg_mfsc_pwm_set(payload, pwm);
8036         mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
8037 }
8038
8039 /* MFSM - Management Fan Speed Measurement
8040  * ---------------------------------------
8041  * This register controls the settings of the Tacho measurements and
8042  * enables reading the Tachometer measurements.
8043  */
8044 #define MLXSW_REG_MFSM_ID 0x9003
8045 #define MLXSW_REG_MFSM_LEN 0x08
8046
8047 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
8048
8049 /* reg_mfsm_tacho
8050  * Fan tachometer index.
8051  * Access: Index
8052  */
8053 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
8054
8055 /* reg_mfsm_rpm
8056  * Fan speed (round per minute).
8057  * Access: RO
8058  */
8059 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
8060
8061 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
8062 {
8063         MLXSW_REG_ZERO(mfsm, payload);
8064         mlxsw_reg_mfsm_tacho_set(payload, tacho);
8065 }
8066
8067 /* MFSL - Management Fan Speed Limit Register
8068  * ------------------------------------------
8069  * The Fan Speed Limit register is used to configure the fan speed
8070  * event / interrupt notification mechanism. Fan speed threshold are
8071  * defined for both under-speed and over-speed.
8072  */
8073 #define MLXSW_REG_MFSL_ID 0x9004
8074 #define MLXSW_REG_MFSL_LEN 0x0C
8075
8076 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
8077
8078 /* reg_mfsl_tacho
8079  * Fan tachometer index.
8080  * Access: Index
8081  */
8082 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
8083
8084 /* reg_mfsl_tach_min
8085  * Tachometer minimum value (minimum RPM).
8086  * Access: RW
8087  */
8088 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
8089
8090 /* reg_mfsl_tach_max
8091  * Tachometer maximum value (maximum RPM).
8092  * Access: RW
8093  */
8094 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
8095
8096 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
8097                                        u16 tach_min, u16 tach_max)
8098 {
8099         MLXSW_REG_ZERO(mfsl, payload);
8100         mlxsw_reg_mfsl_tacho_set(payload, tacho);
8101         mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
8102         mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
8103 }
8104
8105 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
8106                                          u16 *p_tach_min, u16 *p_tach_max)
8107 {
8108         if (p_tach_min)
8109                 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
8110
8111         if (p_tach_max)
8112                 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
8113 }
8114
8115 /* FORE - Fan Out of Range Event Register
8116  * --------------------------------------
8117  * This register reports the status of the controlled fans compared to the
8118  * range defined by the MFSL register.
8119  */
8120 #define MLXSW_REG_FORE_ID 0x9007
8121 #define MLXSW_REG_FORE_LEN 0x0C
8122
8123 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);
8124
8125 /* fan_under_limit
8126  * Fan speed is below the low limit defined in MFSL register. Each bit relates
8127  * to a single tachometer and indicates the specific tachometer reading is
8128  * below the threshold.
8129  * Access: RO
8130  */
8131 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
8132
8133 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,
8134                                          bool *fault)
8135 {
8136         u16 limit;
8137
8138         if (fault) {
8139                 limit = mlxsw_reg_fore_fan_under_limit_get(payload);
8140                 *fault = limit & BIT(tacho);
8141         }
8142 }
8143
8144 /* MTCAP - Management Temperature Capabilities
8145  * -------------------------------------------
8146  * This register exposes the capabilities of the device and
8147  * system temperature sensing.
8148  */
8149 #define MLXSW_REG_MTCAP_ID 0x9009
8150 #define MLXSW_REG_MTCAP_LEN 0x08
8151
8152 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
8153
8154 /* reg_mtcap_sensor_count
8155  * Number of sensors supported by the device.
8156  * This includes the QSFP module sensors (if exists in the QSFP module).
8157  * Access: RO
8158  */
8159 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
8160
8161 /* MTMP - Management Temperature
8162  * -----------------------------
8163  * This register controls the settings of the temperature measurements
8164  * and enables reading the temperature measurements. Note that temperature
8165  * is in 0.125 degrees Celsius.
8166  */
8167 #define MLXSW_REG_MTMP_ID 0x900A
8168 #define MLXSW_REG_MTMP_LEN 0x20
8169
8170 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
8171
8172 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64
8173 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256
8174 /* reg_mtmp_sensor_index
8175  * Sensors index to access.
8176  * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
8177  * (module 0 is mapped to sensor_index 64).
8178  * Access: Index
8179  */
8180 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
8181
8182 /* Convert to milli degrees Celsius */
8183 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \
8184                                           ((v_) >= 0) ? ((v_) * 125) : \
8185                                           ((s16)((GENMASK(15, 0) + (v_) + 1) \
8186                                            * 125)); })
8187
8188 /* reg_mtmp_temperature
8189  * Temperature reading from the sensor. Reading is in 0.125 Celsius
8190  * degrees units.
8191  * Access: RO
8192  */
8193 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
8194
8195 /* reg_mtmp_mte
8196  * Max Temperature Enable - enables measuring the max temperature on a sensor.
8197  * Access: RW
8198  */
8199 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
8200
8201 /* reg_mtmp_mtr
8202  * Max Temperature Reset - clears the value of the max temperature register.
8203  * Access: WO
8204  */
8205 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
8206
8207 /* reg_mtmp_max_temperature
8208  * The highest measured temperature from the sensor.
8209  * When the bit mte is cleared, the field max_temperature is reserved.
8210  * Access: RO
8211  */
8212 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
8213
8214 /* reg_mtmp_tee
8215  * Temperature Event Enable.
8216  * 0 - Do not generate event
8217  * 1 - Generate event
8218  * 2 - Generate single event
8219  * Access: RW
8220  */
8221 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
8222
8223 #define MLXSW_REG_MTMP_THRESH_HI 0x348  /* 105 Celsius */
8224
8225 /* reg_mtmp_temperature_threshold_hi
8226  * High threshold for Temperature Warning Event. In 0.125 Celsius.
8227  * Access: RW
8228  */
8229 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
8230
8231 /* reg_mtmp_temperature_threshold_lo
8232  * Low threshold for Temperature Warning Event. In 0.125 Celsius.
8233  * Access: RW
8234  */
8235 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
8236
8237 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
8238
8239 /* reg_mtmp_sensor_name
8240  * Sensor Name
8241  * Access: RO
8242  */
8243 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
8244
8245 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index,
8246                                        bool max_temp_enable,
8247                                        bool max_temp_reset)
8248 {
8249         MLXSW_REG_ZERO(mtmp, payload);
8250         mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
8251         mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
8252         mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
8253         mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
8254                                                     MLXSW_REG_MTMP_THRESH_HI);
8255 }
8256
8257 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp,
8258                                          int *p_max_temp, char *sensor_name)
8259 {
8260         s16 temp;
8261
8262         if (p_temp) {
8263                 temp = mlxsw_reg_mtmp_temperature_get(payload);
8264                 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8265         }
8266         if (p_max_temp) {
8267                 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
8268                 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8269         }
8270         if (sensor_name)
8271                 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
8272 }
8273
8274 /* MTBR - Management Temperature Bulk Register
8275  * -------------------------------------------
8276  * This register is used for bulk temperature reading.
8277  */
8278 #define MLXSW_REG_MTBR_ID 0x900F
8279 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */
8280 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */
8281 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */
8282 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN +   \
8283                             MLXSW_REG_MTBR_REC_LEN *    \
8284                             MLXSW_REG_MTBR_REC_MAX_COUNT)
8285
8286 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);
8287
8288 /* reg_mtbr_base_sensor_index
8289  * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors,
8290  * 64-127 are mapped to the SFP+/QSFP modules sequentially).
8291  * Access: Index
8292  */
8293 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
8294
8295 /* reg_mtbr_num_rec
8296  * Request: Number of records to read
8297  * Response: Number of records read
8298  * See above description for more details.
8299  * Range 1..255
8300  * Access: RW
8301  */
8302 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
8303
8304 /* reg_mtbr_rec_max_temp
8305  * The highest measured temperature from the sensor.
8306  * When the bit mte is cleared, the field max_temperature is reserved.
8307  * Access: RO
8308  */
8309 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
8310                      16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8311
8312 /* reg_mtbr_rec_temp
8313  * Temperature reading from the sensor. Reading is in 0..125 Celsius
8314  * degrees units.
8315  * Access: RO
8316  */
8317 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
8318                      MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8319
8320 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index,
8321                                        u8 num_rec)
8322 {
8323         MLXSW_REG_ZERO(mtbr, payload);
8324         mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);
8325         mlxsw_reg_mtbr_num_rec_set(payload, num_rec);
8326 }
8327
8328 /* Error codes from temperatute reading */
8329 enum mlxsw_reg_mtbr_temp_status {
8330         MLXSW_REG_MTBR_NO_CONN          = 0x8000,
8331         MLXSW_REG_MTBR_NO_TEMP_SENS     = 0x8001,
8332         MLXSW_REG_MTBR_INDEX_NA         = 0x8002,
8333         MLXSW_REG_MTBR_BAD_SENS_INFO    = 0x8003,
8334 };
8335
8336 /* Base index for reading modules temperature */
8337 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64
8338
8339 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,
8340                                               u16 *p_temp, u16 *p_max_temp)
8341 {
8342         if (p_temp)
8343                 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);
8344         if (p_max_temp)
8345                 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);
8346 }
8347
8348 /* MCIA - Management Cable Info Access
8349  * -----------------------------------
8350  * MCIA register is used to access the SFP+ and QSFP connector's EPROM.
8351  */
8352
8353 #define MLXSW_REG_MCIA_ID 0x9014
8354 #define MLXSW_REG_MCIA_LEN 0x40
8355
8356 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
8357
8358 /* reg_mcia_l
8359  * Lock bit. Setting this bit will lock the access to the specific
8360  * cable. Used for updating a full page in a cable EPROM. Any access
8361  * other then subsequence writes will fail while the port is locked.
8362  * Access: RW
8363  */
8364 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
8365
8366 /* reg_mcia_module
8367  * Module number.
8368  * Access: Index
8369  */
8370 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
8371
8372 /* reg_mcia_status
8373  * Module status.
8374  * Access: RO
8375  */
8376 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
8377
8378 /* reg_mcia_i2c_device_address
8379  * I2C device address.
8380  * Access: RW
8381  */
8382 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
8383
8384 /* reg_mcia_page_number
8385  * Page number.
8386  * Access: RW
8387  */
8388 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
8389
8390 /* reg_mcia_device_address
8391  * Device address.
8392  * Access: RW
8393  */
8394 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
8395
8396 /* reg_mcia_size
8397  * Number of bytes to read/write (up to 48 bytes).
8398  * Access: RW
8399  */
8400 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
8401
8402 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH       256
8403 #define MLXSW_REG_MCIA_EEPROM_SIZE              48
8404 #define MLXSW_REG_MCIA_I2C_ADDR_LOW             0x50
8405 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH            0x51
8406 #define MLXSW_REG_MCIA_PAGE0_LO_OFF             0xa0
8407 #define MLXSW_REG_MCIA_TH_ITEM_SIZE             2
8408 #define MLXSW_REG_MCIA_TH_PAGE_NUM              3
8409 #define MLXSW_REG_MCIA_PAGE0_LO                 0
8410 #define MLXSW_REG_MCIA_TH_PAGE_OFF              0x80
8411
8412 enum mlxsw_reg_mcia_eeprom_module_info_rev_id {
8413         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC  = 0x00,
8414         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436   = 0x01,
8415         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636   = 0x03,
8416 };
8417
8418 enum mlxsw_reg_mcia_eeprom_module_info_id {
8419         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP        = 0x03,
8420         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP       = 0x0C,
8421         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS  = 0x0D,
8422         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28     = 0x11,
8423         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD    = 0x18,
8424 };
8425
8426 enum mlxsw_reg_mcia_eeprom_module_info {
8427         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,
8428         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,
8429         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,
8430 };
8431
8432 /* reg_mcia_eeprom
8433  * Bytes to read/write.
8434  * Access: RW
8435  */
8436 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE);
8437
8438 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
8439                                        u8 page_number, u16 device_addr,
8440                                        u8 size, u8 i2c_device_addr)
8441 {
8442         MLXSW_REG_ZERO(mcia, payload);
8443         mlxsw_reg_mcia_module_set(payload, module);
8444         mlxsw_reg_mcia_l_set(payload, lock);
8445         mlxsw_reg_mcia_page_number_set(payload, page_number);
8446         mlxsw_reg_mcia_device_address_set(payload, device_addr);
8447         mlxsw_reg_mcia_size_set(payload, size);
8448         mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
8449 }
8450
8451 /* MPAT - Monitoring Port Analyzer Table
8452  * -------------------------------------
8453  * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
8454  * For an enabled analyzer, all fields except e (enable) cannot be modified.
8455  */
8456 #define MLXSW_REG_MPAT_ID 0x901A
8457 #define MLXSW_REG_MPAT_LEN 0x78
8458
8459 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
8460
8461 /* reg_mpat_pa_id
8462  * Port Analyzer ID.
8463  * Access: Index
8464  */
8465 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
8466
8467 /* reg_mpat_system_port
8468  * A unique port identifier for the final destination of the packet.
8469  * Access: RW
8470  */
8471 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
8472
8473 /* reg_mpat_e
8474  * Enable. Indicating the Port Analyzer is enabled.
8475  * Access: RW
8476  */
8477 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
8478
8479 /* reg_mpat_qos
8480  * Quality Of Service Mode.
8481  * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
8482  * PCP, DEI, DSCP or VL) are configured.
8483  * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
8484  * same as in the original packet that has triggered the mirroring. For
8485  * SPAN also the pcp,dei are maintained.
8486  * Access: RW
8487  */
8488 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
8489
8490 /* reg_mpat_be
8491  * Best effort mode. Indicates mirroring traffic should not cause packet
8492  * drop or back pressure, but will discard the mirrored packets. Mirrored
8493  * packets will be forwarded on a best effort manner.
8494  * 0: Do not discard mirrored packets
8495  * 1: Discard mirrored packets if causing congestion
8496  * Access: RW
8497  */
8498 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
8499
8500 enum mlxsw_reg_mpat_span_type {
8501         /* Local SPAN Ethernet.
8502          * The original packet is not encapsulated.
8503          */
8504         MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
8505
8506         /* Remote SPAN Ethernet VLAN.
8507          * The packet is forwarded to the monitoring port on the monitoring
8508          * VLAN.
8509          */
8510         MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
8511
8512         /* Encapsulated Remote SPAN Ethernet L3 GRE.
8513          * The packet is encapsulated with GRE header.
8514          */
8515         MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
8516 };
8517
8518 /* reg_mpat_span_type
8519  * SPAN type.
8520  * Access: RW
8521  */
8522 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
8523
8524 /* Remote SPAN - Ethernet VLAN
8525  * - - - - - - - - - - - - - -
8526  */
8527
8528 /* reg_mpat_eth_rspan_vid
8529  * Encapsulation header VLAN ID.
8530  * Access: RW
8531  */
8532 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
8533
8534 /* Encapsulated Remote SPAN - Ethernet L2
8535  * - - - - - - - - - - - - - - - - - - -
8536  */
8537
8538 enum mlxsw_reg_mpat_eth_rspan_version {
8539         MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
8540 };
8541
8542 /* reg_mpat_eth_rspan_version
8543  * RSPAN mirror header version.
8544  * Access: RW
8545  */
8546 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
8547
8548 /* reg_mpat_eth_rspan_mac
8549  * Destination MAC address.
8550  * Access: RW
8551  */
8552 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
8553
8554 /* reg_mpat_eth_rspan_tp
8555  * Tag Packet. Indicates whether the mirroring header should be VLAN tagged.
8556  * Access: RW
8557  */
8558 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
8559
8560 /* Encapsulated Remote SPAN - Ethernet L3
8561  * - - - - - - - - - - - - - - - - - - -
8562  */
8563
8564 enum mlxsw_reg_mpat_eth_rspan_protocol {
8565         MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
8566         MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
8567 };
8568
8569 /* reg_mpat_eth_rspan_protocol
8570  * SPAN encapsulation protocol.
8571  * Access: RW
8572  */
8573 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
8574
8575 /* reg_mpat_eth_rspan_ttl
8576  * Encapsulation header Time-to-Live/HopLimit.
8577  * Access: RW
8578  */
8579 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
8580
8581 /* reg_mpat_eth_rspan_smac
8582  * Source MAC address
8583  * Access: RW
8584  */
8585 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
8586
8587 /* reg_mpat_eth_rspan_dip*
8588  * Destination IP address. The IP version is configured by protocol.
8589  * Access: RW
8590  */
8591 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
8592 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
8593
8594 /* reg_mpat_eth_rspan_sip*
8595  * Source IP address. The IP version is configured by protocol.
8596  * Access: RW
8597  */
8598 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
8599 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
8600
8601 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
8602                                        u16 system_port, bool e,
8603                                        enum mlxsw_reg_mpat_span_type span_type)
8604 {
8605         MLXSW_REG_ZERO(mpat, payload);
8606         mlxsw_reg_mpat_pa_id_set(payload, pa_id);
8607         mlxsw_reg_mpat_system_port_set(payload, system_port);
8608         mlxsw_reg_mpat_e_set(payload, e);
8609         mlxsw_reg_mpat_qos_set(payload, 1);
8610         mlxsw_reg_mpat_be_set(payload, 1);
8611         mlxsw_reg_mpat_span_type_set(payload, span_type);
8612 }
8613
8614 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
8615 {
8616         mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
8617 }
8618
8619 static inline void
8620 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
8621                                  enum mlxsw_reg_mpat_eth_rspan_version version,
8622                                  const char *mac,
8623                                  bool tp)
8624 {
8625         mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
8626         mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
8627         mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
8628 }
8629
8630 static inline void
8631 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
8632                                       const char *smac,
8633                                       u32 sip, u32 dip)
8634 {
8635         mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8636         mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8637         mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8638                                     MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
8639         mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
8640         mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
8641 }
8642
8643 static inline void
8644 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
8645                                       const char *smac,
8646                                       struct in6_addr sip, struct in6_addr dip)
8647 {
8648         mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8649         mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8650         mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8651                                     MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
8652         mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
8653         mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
8654 }
8655
8656 /* MPAR - Monitoring Port Analyzer Register
8657  * ----------------------------------------
8658  * MPAR register is used to query and configure the port analyzer port mirroring
8659  * properties.
8660  */
8661 #define MLXSW_REG_MPAR_ID 0x901B
8662 #define MLXSW_REG_MPAR_LEN 0x08
8663
8664 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
8665
8666 /* reg_mpar_local_port
8667  * The local port to mirror the packets from.
8668  * Access: Index
8669  */
8670 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
8671
8672 enum mlxsw_reg_mpar_i_e {
8673         MLXSW_REG_MPAR_TYPE_EGRESS,
8674         MLXSW_REG_MPAR_TYPE_INGRESS,
8675 };
8676
8677 /* reg_mpar_i_e
8678  * Ingress/Egress
8679  * Access: Index
8680  */
8681 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
8682
8683 /* reg_mpar_enable
8684  * Enable mirroring
8685  * By default, port mirroring is disabled for all ports.
8686  * Access: RW
8687  */
8688 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
8689
8690 /* reg_mpar_pa_id
8691  * Port Analyzer ID.
8692  * Access: RW
8693  */
8694 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
8695
8696 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
8697                                        enum mlxsw_reg_mpar_i_e i_e,
8698                                        bool enable, u8 pa_id)
8699 {
8700         MLXSW_REG_ZERO(mpar, payload);
8701         mlxsw_reg_mpar_local_port_set(payload, local_port);
8702         mlxsw_reg_mpar_enable_set(payload, enable);
8703         mlxsw_reg_mpar_i_e_set(payload, i_e);
8704         mlxsw_reg_mpar_pa_id_set(payload, pa_id);
8705 }
8706
8707 /* MGIR - Management General Information Register
8708  * ----------------------------------------------
8709  * MGIR register allows software to query the hardware and firmware general
8710  * information.
8711  */
8712 #define MLXSW_REG_MGIR_ID 0x9020
8713 #define MLXSW_REG_MGIR_LEN 0x9C
8714
8715 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);
8716
8717 /* reg_mgir_hw_info_device_hw_revision
8718  * Access: RO
8719  */
8720 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
8721
8722 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16
8723
8724 /* reg_mgir_fw_info_psid
8725  * PSID (ASCII string).
8726  * Access: RO
8727  */
8728 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
8729
8730 /* reg_mgir_fw_info_extended_major
8731  * Access: RO
8732  */
8733 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
8734
8735 /* reg_mgir_fw_info_extended_minor
8736  * Access: RO
8737  */
8738 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
8739
8740 /* reg_mgir_fw_info_extended_sub_minor
8741  * Access: RO
8742  */
8743 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
8744
8745 static inline void mlxsw_reg_mgir_pack(char *payload)
8746 {
8747         MLXSW_REG_ZERO(mgir, payload);
8748 }
8749
8750 static inline void
8751 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,
8752                       u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor)
8753 {
8754         *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);
8755         mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);
8756         *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);
8757         *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);
8758         *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);
8759 }
8760
8761 /* MRSR - Management Reset and Shutdown Register
8762  * ---------------------------------------------
8763  * MRSR register is used to reset or shutdown the switch or
8764  * the entire system (when applicable).
8765  */
8766 #define MLXSW_REG_MRSR_ID 0x9023
8767 #define MLXSW_REG_MRSR_LEN 0x08
8768
8769 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
8770
8771 /* reg_mrsr_command
8772  * Reset/shutdown command
8773  * 0 - do nothing
8774  * 1 - software reset
8775  * Access: WO
8776  */
8777 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
8778
8779 static inline void mlxsw_reg_mrsr_pack(char *payload)
8780 {
8781         MLXSW_REG_ZERO(mrsr, payload);
8782         mlxsw_reg_mrsr_command_set(payload, 1);
8783 }
8784
8785 /* MLCR - Management LED Control Register
8786  * --------------------------------------
8787  * Controls the system LEDs.
8788  */
8789 #define MLXSW_REG_MLCR_ID 0x902B
8790 #define MLXSW_REG_MLCR_LEN 0x0C
8791
8792 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
8793
8794 /* reg_mlcr_local_port
8795  * Local port number.
8796  * Access: RW
8797  */
8798 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
8799
8800 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
8801
8802 /* reg_mlcr_beacon_duration
8803  * Duration of the beacon to be active, in seconds.
8804  * 0x0 - Will turn off the beacon.
8805  * 0xFFFF - Will turn on the beacon until explicitly turned off.
8806  * Access: RW
8807  */
8808 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
8809
8810 /* reg_mlcr_beacon_remain
8811  * Remaining duration of the beacon, in seconds.
8812  * 0xFFFF indicates an infinite amount of time.
8813  * Access: RO
8814  */
8815 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
8816
8817 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
8818                                        bool active)
8819 {
8820         MLXSW_REG_ZERO(mlcr, payload);
8821         mlxsw_reg_mlcr_local_port_set(payload, local_port);
8822         mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
8823                                            MLXSW_REG_MLCR_DURATION_MAX : 0);
8824 }
8825
8826 /* MTPPS - Management Pulse Per Second Register
8827  * --------------------------------------------
8828  * This register provides the device PPS capabilities, configure the PPS in and
8829  * out modules and holds the PPS in time stamp.
8830  */
8831 #define MLXSW_REG_MTPPS_ID 0x9053
8832 #define MLXSW_REG_MTPPS_LEN 0x3C
8833
8834 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
8835
8836 /* reg_mtpps_enable
8837  * Enables the PPS functionality the specific pin.
8838  * A boolean variable.
8839  * Access: RW
8840  */
8841 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
8842
8843 enum mlxsw_reg_mtpps_pin_mode {
8844         MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
8845 };
8846
8847 /* reg_mtpps_pin_mode
8848  * Pin mode to be used. The mode must comply with the supported modes of the
8849  * requested pin.
8850  * Access: RW
8851  */
8852 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
8853
8854 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN      7
8855
8856 /* reg_mtpps_pin
8857  * Pin to be configured or queried out of the supported pins.
8858  * Access: Index
8859  */
8860 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
8861
8862 /* reg_mtpps_time_stamp
8863  * When pin_mode = pps_in, the latched device time when it was triggered from
8864  * the external GPIO pin.
8865  * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target
8866  * time to generate next output signal.
8867  * Time is in units of device clock.
8868  * Access: RW
8869  */
8870 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
8871
8872 static inline void
8873 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
8874 {
8875         MLXSW_REG_ZERO(mtpps, payload);
8876         mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
8877         mlxsw_reg_mtpps_pin_mode_set(payload,
8878                                      MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
8879         mlxsw_reg_mtpps_enable_set(payload, true);
8880         mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
8881 }
8882
8883 /* MTUTC - Management UTC Register
8884  * -------------------------------
8885  * Configures the HW UTC counter.
8886  */
8887 #define MLXSW_REG_MTUTC_ID 0x9055
8888 #define MLXSW_REG_MTUTC_LEN 0x1C
8889
8890 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);
8891
8892 enum mlxsw_reg_mtutc_operation {
8893         MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
8894         MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
8895 };
8896
8897 /* reg_mtutc_operation
8898  * Operation.
8899  * Access: OP
8900  */
8901 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
8902
8903 /* reg_mtutc_freq_adjustment
8904  * Frequency adjustment: Every PPS the HW frequency will be
8905  * adjusted by this value. Units of HW clock, where HW counts
8906  * 10^9 HW clocks for 1 HW second.
8907  * Access: RW
8908  */
8909 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
8910
8911 /* reg_mtutc_utc_sec
8912  * UTC seconds.
8913  * Access: WO
8914  */
8915 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
8916
8917 static inline void
8918 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
8919                      u32 freq_adj, u32 utc_sec)
8920 {
8921         MLXSW_REG_ZERO(mtutc, payload);
8922         mlxsw_reg_mtutc_operation_set(payload, oper);
8923         mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
8924         mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
8925 }
8926
8927 /* MCQI - Management Component Query Information
8928  * ---------------------------------------------
8929  * This register allows querying information about firmware components.
8930  */
8931 #define MLXSW_REG_MCQI_ID 0x9061
8932 #define MLXSW_REG_MCQI_BASE_LEN 0x18
8933 #define MLXSW_REG_MCQI_CAP_LEN 0x14
8934 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
8935
8936 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
8937
8938 /* reg_mcqi_component_index
8939  * Index of the accessed component.
8940  * Access: Index
8941  */
8942 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
8943
8944 enum mlxfw_reg_mcqi_info_type {
8945         MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
8946 };
8947
8948 /* reg_mcqi_info_type
8949  * Component properties set.
8950  * Access: RW
8951  */
8952 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
8953
8954 /* reg_mcqi_offset
8955  * The requested/returned data offset from the section start, given in bytes.
8956  * Must be DWORD aligned.
8957  * Access: RW
8958  */
8959 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
8960
8961 /* reg_mcqi_data_size
8962  * The requested/returned data size, given in bytes. If data_size is not DWORD
8963  * aligned, the last bytes are zero padded.
8964  * Access: RW
8965  */
8966 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
8967
8968 /* reg_mcqi_cap_max_component_size
8969  * Maximum size for this component, given in bytes.
8970  * Access: RO
8971  */
8972 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
8973
8974 /* reg_mcqi_cap_log_mcda_word_size
8975  * Log 2 of the access word size in bytes. Read and write access must be aligned
8976  * to the word size. Write access must be done for an integer number of words.
8977  * Access: RO
8978  */
8979 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
8980
8981 /* reg_mcqi_cap_mcda_max_write_size
8982  * Maximal write size for MCDA register
8983  * Access: RO
8984  */
8985 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
8986
8987 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
8988 {
8989         MLXSW_REG_ZERO(mcqi, payload);
8990         mlxsw_reg_mcqi_component_index_set(payload, component_index);
8991         mlxsw_reg_mcqi_info_type_set(payload,
8992                                      MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
8993         mlxsw_reg_mcqi_offset_set(payload, 0);
8994         mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
8995 }
8996
8997 static inline void mlxsw_reg_mcqi_unpack(char *payload,
8998                                          u32 *p_cap_max_component_size,
8999                                          u8 *p_cap_log_mcda_word_size,
9000                                          u16 *p_cap_mcda_max_write_size)
9001 {
9002         *p_cap_max_component_size =
9003                 mlxsw_reg_mcqi_cap_max_component_size_get(payload);
9004         *p_cap_log_mcda_word_size =
9005                 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
9006         *p_cap_mcda_max_write_size =
9007                 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
9008 }
9009
9010 /* MCC - Management Component Control
9011  * ----------------------------------
9012  * Controls the firmware component and updates the FSM.
9013  */
9014 #define MLXSW_REG_MCC_ID 0x9062
9015 #define MLXSW_REG_MCC_LEN 0x1C
9016
9017 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
9018
9019 enum mlxsw_reg_mcc_instruction {
9020         MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
9021         MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
9022         MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
9023         MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
9024         MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
9025         MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
9026 };
9027
9028 /* reg_mcc_instruction
9029  * Command to be executed by the FSM.
9030  * Applicable for write operation only.
9031  * Access: RW
9032  */
9033 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
9034
9035 /* reg_mcc_component_index
9036  * Index of the accessed component. Applicable only for commands that
9037  * refer to components. Otherwise, this field is reserved.
9038  * Access: Index
9039  */
9040 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
9041
9042 /* reg_mcc_update_handle
9043  * Token representing the current flow executed by the FSM.
9044  * Access: WO
9045  */
9046 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
9047
9048 /* reg_mcc_error_code
9049  * Indicates the successful completion of the instruction, or the reason it
9050  * failed
9051  * Access: RO
9052  */
9053 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
9054
9055 /* reg_mcc_control_state
9056  * Current FSM state
9057  * Access: RO
9058  */
9059 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
9060
9061 /* reg_mcc_component_size
9062  * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying
9063  * the size may shorten the update time. Value 0x0 means that size is
9064  * unspecified.
9065  * Access: WO
9066  */
9067 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
9068
9069 static inline void mlxsw_reg_mcc_pack(char *payload,
9070                                       enum mlxsw_reg_mcc_instruction instr,
9071                                       u16 component_index, u32 update_handle,
9072                                       u32 component_size)
9073 {
9074         MLXSW_REG_ZERO(mcc, payload);
9075         mlxsw_reg_mcc_instruction_set(payload, instr);
9076         mlxsw_reg_mcc_component_index_set(payload, component_index);
9077         mlxsw_reg_mcc_update_handle_set(payload, update_handle);
9078         mlxsw_reg_mcc_component_size_set(payload, component_size);
9079 }
9080
9081 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
9082                                         u8 *p_error_code, u8 *p_control_state)
9083 {
9084         if (p_update_handle)
9085                 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
9086         if (p_error_code)
9087                 *p_error_code = mlxsw_reg_mcc_error_code_get(payload);
9088         if (p_control_state)
9089                 *p_control_state = mlxsw_reg_mcc_control_state_get(payload);
9090 }
9091
9092 /* MCDA - Management Component Data Access
9093  * ---------------------------------------
9094  * This register allows reading and writing a firmware component.
9095  */
9096 #define MLXSW_REG_MCDA_ID 0x9063
9097 #define MLXSW_REG_MCDA_BASE_LEN 0x10
9098 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
9099 #define MLXSW_REG_MCDA_LEN \
9100                 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
9101
9102 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
9103
9104 /* reg_mcda_update_handle
9105  * Token representing the current flow executed by the FSM.
9106  * Access: RW
9107  */
9108 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
9109
9110 /* reg_mcda_offset
9111  * Offset of accessed address relative to component start. Accesses must be in
9112  * accordance to log_mcda_word_size in MCQI reg.
9113  * Access: RW
9114  */
9115 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
9116
9117 /* reg_mcda_size
9118  * Size of the data accessed, given in bytes.
9119  * Access: RW
9120  */
9121 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
9122
9123 /* reg_mcda_data
9124  * Data block accessed.
9125  * Access: RW
9126  */
9127 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
9128
9129 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
9130                                        u32 offset, u16 size, u8 *data)
9131 {
9132         int i;
9133
9134         MLXSW_REG_ZERO(mcda, payload);
9135         mlxsw_reg_mcda_update_handle_set(payload, update_handle);
9136         mlxsw_reg_mcda_offset_set(payload, offset);
9137         mlxsw_reg_mcda_size_set(payload, size);
9138
9139         for (i = 0; i < size / 4; i++)
9140                 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
9141 }
9142
9143 /* MPSC - Monitoring Packet Sampling Configuration Register
9144  * --------------------------------------------------------
9145  * MPSC Register is used to configure the Packet Sampling mechanism.
9146  */
9147 #define MLXSW_REG_MPSC_ID 0x9080
9148 #define MLXSW_REG_MPSC_LEN 0x1C
9149
9150 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
9151
9152 /* reg_mpsc_local_port
9153  * Local port number
9154  * Not supported for CPU port
9155  * Access: Index
9156  */
9157 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8);
9158
9159 /* reg_mpsc_e
9160  * Enable sampling on port local_port
9161  * Access: RW
9162  */
9163 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
9164
9165 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
9166
9167 /* reg_mpsc_rate
9168  * Sampling rate = 1 out of rate packets (with randomization around
9169  * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
9170  * Access: RW
9171  */
9172 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
9173
9174 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e,
9175                                        u32 rate)
9176 {
9177         MLXSW_REG_ZERO(mpsc, payload);
9178         mlxsw_reg_mpsc_local_port_set(payload, local_port);
9179         mlxsw_reg_mpsc_e_set(payload, e);
9180         mlxsw_reg_mpsc_rate_set(payload, rate);
9181 }
9182
9183 /* MGPC - Monitoring General Purpose Counter Set Register
9184  * The MGPC register retrieves and sets the General Purpose Counter Set.
9185  */
9186 #define MLXSW_REG_MGPC_ID 0x9081
9187 #define MLXSW_REG_MGPC_LEN 0x18
9188
9189 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
9190
9191 /* reg_mgpc_counter_set_type
9192  * Counter set type.
9193  * Access: OP
9194  */
9195 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
9196
9197 /* reg_mgpc_counter_index
9198  * Counter index.
9199  * Access: Index
9200  */
9201 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
9202
9203 enum mlxsw_reg_mgpc_opcode {
9204         /* Nop */
9205         MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
9206         /* Clear counters */
9207         MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
9208 };
9209
9210 /* reg_mgpc_opcode
9211  * Opcode.
9212  * Access: OP
9213  */
9214 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
9215
9216 /* reg_mgpc_byte_counter
9217  * Byte counter value.
9218  * Access: RW
9219  */
9220 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
9221
9222 /* reg_mgpc_packet_counter
9223  * Packet counter value.
9224  * Access: RW
9225  */
9226 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
9227
9228 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
9229                                        enum mlxsw_reg_mgpc_opcode opcode,
9230                                        enum mlxsw_reg_flow_counter_set_type set_type)
9231 {
9232         MLXSW_REG_ZERO(mgpc, payload);
9233         mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
9234         mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
9235         mlxsw_reg_mgpc_opcode_set(payload, opcode);
9236 }
9237
9238 /* MPRS - Monitoring Parsing State Register
9239  * ----------------------------------------
9240  * The MPRS register is used for setting up the parsing for hash,
9241  * policy-engine and routing.
9242  */
9243 #define MLXSW_REG_MPRS_ID 0x9083
9244 #define MLXSW_REG_MPRS_LEN 0x14
9245
9246 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
9247
9248 /* reg_mprs_parsing_depth
9249  * Minimum parsing depth.
9250  * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL
9251  * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.
9252  * Access: RW
9253  */
9254 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
9255
9256 /* reg_mprs_parsing_en
9257  * Parsing enable.
9258  * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and
9259  * NVGRE. Default is enabled. Reserved when SwitchX-2.
9260  * Access: RW
9261  */
9262 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
9263
9264 /* reg_mprs_vxlan_udp_dport
9265  * VxLAN UDP destination port.
9266  * Used for identifying VxLAN packets and for dport field in
9267  * encapsulation. Default is 4789.
9268  * Access: RW
9269  */
9270 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
9271
9272 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
9273                                        u16 vxlan_udp_dport)
9274 {
9275         MLXSW_REG_ZERO(mprs, payload);
9276         mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
9277         mlxsw_reg_mprs_parsing_en_set(payload, true);
9278         mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
9279 }
9280
9281 /* MOGCR - Monitoring Global Configuration Register
9282  * ------------------------------------------------
9283  */
9284 #define MLXSW_REG_MOGCR_ID 0x9086
9285 #define MLXSW_REG_MOGCR_LEN 0x20
9286
9287 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
9288
9289 /* reg_mogcr_ptp_iftc
9290  * PTP Ingress FIFO Trap Clear
9291  * The PTP_ING_FIFO trap provides MTPPTR with clr according
9292  * to this value. Default 0.
9293  * Reserved when IB switches and when SwitchX/-2, Spectrum-2
9294  * Access: RW
9295  */
9296 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
9297
9298 /* reg_mogcr_ptp_eftc
9299  * PTP Egress FIFO Trap Clear
9300  * The PTP_EGR_FIFO trap provides MTPPTR with clr according
9301  * to this value. Default 0.
9302  * Reserved when IB switches and when SwitchX/-2, Spectrum-2
9303  * Access: RW
9304  */
9305 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
9306
9307 /* MTPPPC - Time Precision Packet Port Configuration
9308  * -------------------------------------------------
9309  * This register serves for configuration of which PTP messages should be
9310  * timestamped. This is a global configuration, despite the register name.
9311  *
9312  * Reserved when Spectrum-2.
9313  */
9314 #define MLXSW_REG_MTPPPC_ID 0x9090
9315 #define MLXSW_REG_MTPPPC_LEN 0x28
9316
9317 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);
9318
9319 /* reg_mtpppc_ing_timestamp_message_type
9320  * Bitwise vector of PTP message types to timestamp at ingress.
9321  * MessageType field as defined by IEEE 1588
9322  * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
9323  * Default all 0
9324  * Access: RW
9325  */
9326 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
9327
9328 /* reg_mtpppc_egr_timestamp_message_type
9329  * Bitwise vector of PTP message types to timestamp at egress.
9330  * MessageType field as defined by IEEE 1588
9331  * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
9332  * Default all 0
9333  * Access: RW
9334  */
9335 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
9336
9337 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)
9338 {
9339         MLXSW_REG_ZERO(mtpppc, payload);
9340         mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);
9341         mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);
9342 }
9343
9344 /* MTPPTR - Time Precision Packet Timestamping Reading
9345  * ---------------------------------------------------
9346  * The MTPPTR is used for reading the per port PTP timestamp FIFO.
9347  * There is a trap for packets which are latched to the timestamp FIFO, thus the
9348  * SW knows which FIFO to read. Note that packets enter the FIFO before been
9349  * trapped. The sequence number is used to synchronize the timestamp FIFO
9350  * entries and the trapped packets.
9351  * Reserved when Spectrum-2.
9352  */
9353
9354 #define MLXSW_REG_MTPPTR_ID 0x9091
9355 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */
9356 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */
9357 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4
9358 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN +               \
9359                     MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
9360
9361 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);
9362
9363 /* reg_mtpptr_local_port
9364  * Not supported for CPU port.
9365  * Access: Index
9366  */
9367 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8);
9368
9369 enum mlxsw_reg_mtpptr_dir {
9370         MLXSW_REG_MTPPTR_DIR_INGRESS,
9371         MLXSW_REG_MTPPTR_DIR_EGRESS,
9372 };
9373
9374 /* reg_mtpptr_dir
9375  * Direction.
9376  * Access: Index
9377  */
9378 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
9379
9380 /* reg_mtpptr_clr
9381  * Clear the records.
9382  * Access: OP
9383  */
9384 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
9385
9386 /* reg_mtpptr_num_rec
9387  * Number of valid records in the response
9388  * Range 0.. cap_ptp_timestamp_fifo
9389  * Access: RO
9390  */
9391 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
9392
9393 /* reg_mtpptr_rec_message_type
9394  * MessageType field as defined by IEEE 1588 Each bit corresponds to a value
9395  * (e.g. Bit0: Sync, Bit1: Delay_Req)
9396  * Access: RO
9397  */
9398 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
9399                      MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
9400                      MLXSW_REG_MTPPTR_REC_LEN, 0, false);
9401
9402 /* reg_mtpptr_rec_domain_number
9403  * DomainNumber field as defined by IEEE 1588
9404  * Access: RO
9405  */
9406 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
9407                      MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
9408                      MLXSW_REG_MTPPTR_REC_LEN, 0, false);
9409
9410 /* reg_mtpptr_rec_sequence_id
9411  * SequenceId field as defined by IEEE 1588
9412  * Access: RO
9413  */
9414 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
9415                      MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
9416                      MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
9417
9418 /* reg_mtpptr_rec_timestamp_high
9419  * Timestamp of when the PTP packet has passed through the port Units of PLL
9420  * clock time.
9421  * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec.
9422  * Access: RO
9423  */
9424 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
9425                      MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
9426                      MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
9427
9428 /* reg_mtpptr_rec_timestamp_low
9429  * See rec_timestamp_high.
9430  * Access: RO
9431  */
9432 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
9433                      MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
9434                      MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);
9435
9436 static inline void mlxsw_reg_mtpptr_unpack(const char *payload,
9437                                            unsigned int rec,
9438                                            u8 *p_message_type,
9439                                            u8 *p_domain_number,
9440                                            u16 *p_sequence_id,
9441                                            u64 *p_timestamp)
9442 {
9443         u32 timestamp_high, timestamp_low;
9444
9445         *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);
9446         *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);
9447         *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);
9448         timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);
9449         timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);
9450         *p_timestamp = (u64)timestamp_high << 32 | timestamp_low;
9451 }
9452
9453 /* MTPTPT - Monitoring Precision Time Protocol Trap Register
9454  * ---------------------------------------------------------
9455  * This register is used for configuring under which trap to deliver PTP
9456  * packets depending on type of the packet.
9457  */
9458 #define MLXSW_REG_MTPTPT_ID 0x9092
9459 #define MLXSW_REG_MTPTPT_LEN 0x08
9460
9461 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);
9462
9463 enum mlxsw_reg_mtptpt_trap_id {
9464         MLXSW_REG_MTPTPT_TRAP_ID_PTP0,
9465         MLXSW_REG_MTPTPT_TRAP_ID_PTP1,
9466 };
9467
9468 /* reg_mtptpt_trap_id
9469  * Trap id.
9470  * Access: Index
9471  */
9472 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
9473
9474 /* reg_mtptpt_message_type
9475  * Bitwise vector of PTP message types to trap. This is a necessary but
9476  * non-sufficient condition since need to enable also per port. See MTPPPC.
9477  * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g.
9478  * Bit0: Sync, Bit1: Delay_Req)
9479  */
9480 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
9481
9482 static inline void mlxsw_reg_mtptptp_pack(char *payload,
9483                                           enum mlxsw_reg_mtptpt_trap_id trap_id,
9484                                           u16 message_type)
9485 {
9486         MLXSW_REG_ZERO(mtptpt, payload);
9487         mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);
9488         mlxsw_reg_mtptpt_message_type_set(payload, message_type);
9489 }
9490
9491 /* MGPIR - Management General Peripheral Information Register
9492  * ----------------------------------------------------------
9493  * MGPIR register allows software to query the hardware and
9494  * firmware general information of peripheral entities.
9495  */
9496 #define MLXSW_REG_MGPIR_ID 0x9100
9497 #define MLXSW_REG_MGPIR_LEN 0xA0
9498
9499 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN);
9500
9501 enum mlxsw_reg_mgpir_device_type {
9502         MLXSW_REG_MGPIR_DEVICE_TYPE_NONE,
9503         MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE,
9504 };
9505
9506 /* device_type
9507  * Access: RO
9508  */
9509 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);
9510
9511 /* devices_per_flash
9512  * Number of devices of device_type per flash (can be shared by few devices).
9513  * Access: RO
9514  */
9515 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
9516
9517 /* num_of_devices
9518  * Number of devices of device_type.
9519  * Access: RO
9520  */
9521 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
9522
9523 static inline void mlxsw_reg_mgpir_pack(char *payload)
9524 {
9525         MLXSW_REG_ZERO(mgpir, payload);
9526 }
9527
9528 static inline void
9529 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
9530                        enum mlxsw_reg_mgpir_device_type *device_type,
9531                        u8 *devices_per_flash)
9532 {
9533         if (num_of_devices)
9534                 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload);
9535         if (device_type)
9536                 *device_type = mlxsw_reg_mgpir_device_type_get(payload);
9537         if (devices_per_flash)
9538                 *devices_per_flash =
9539                                 mlxsw_reg_mgpir_devices_per_flash_get(payload);
9540 }
9541
9542 /* TNGCR - Tunneling NVE General Configuration Register
9543  * ----------------------------------------------------
9544  * The TNGCR register is used for setting up the NVE Tunneling configuration.
9545  */
9546 #define MLXSW_REG_TNGCR_ID 0xA001
9547 #define MLXSW_REG_TNGCR_LEN 0x44
9548
9549 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
9550
9551 enum mlxsw_reg_tngcr_type {
9552         MLXSW_REG_TNGCR_TYPE_VXLAN,
9553         MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
9554         MLXSW_REG_TNGCR_TYPE_GENEVE,
9555         MLXSW_REG_TNGCR_TYPE_NVGRE,
9556 };
9557
9558 /* reg_tngcr_type
9559  * Tunnel type for encapsulation and decapsulation. The types are mutually
9560  * exclusive.
9561  * Note: For Spectrum the NVE parsing must be enabled in MPRS.
9562  * Access: RW
9563  */
9564 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
9565
9566 /* reg_tngcr_nve_valid
9567  * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation.
9568  * Access: RW
9569  */
9570 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
9571
9572 /* reg_tngcr_nve_ttl_uc
9573  * The TTL for NVE tunnel encapsulation underlay unicast packets.
9574  * Access: RW
9575  */
9576 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
9577
9578 /* reg_tngcr_nve_ttl_mc
9579  * The TTL for NVE tunnel encapsulation underlay multicast packets.
9580  * Access: RW
9581  */
9582 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
9583
9584 enum {
9585         /* Do not copy flow label. Calculate flow label using nve_flh. */
9586         MLXSW_REG_TNGCR_FL_NO_COPY,
9587         /* Copy flow label from inner packet if packet is IPv6 and
9588          * encapsulation is by IPv6. Otherwise, calculate flow label using
9589          * nve_flh.
9590          */
9591         MLXSW_REG_TNGCR_FL_COPY,
9592 };
9593
9594 /* reg_tngcr_nve_flc
9595  * For NVE tunnel encapsulation: Flow label copy from inner packet.
9596  * Access: RW
9597  */
9598 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
9599
9600 enum {
9601         /* Flow label is static. In Spectrum this means '0'. Spectrum-2
9602          * uses {nve_fl_prefix, nve_fl_suffix}.
9603          */
9604         MLXSW_REG_TNGCR_FL_NO_HASH,
9605         /* 8 LSBs of the flow label are calculated from ECMP hash of the
9606          * inner packet. 12 MSBs are configured by nve_fl_prefix.
9607          */
9608         MLXSW_REG_TNGCR_FL_HASH,
9609 };
9610
9611 /* reg_tngcr_nve_flh
9612  * NVE flow label hash.
9613  * Access: RW
9614  */
9615 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
9616
9617 /* reg_tngcr_nve_fl_prefix
9618  * NVE flow label prefix. Constant 12 MSBs of the flow label.
9619  * Access: RW
9620  */
9621 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
9622
9623 /* reg_tngcr_nve_fl_suffix
9624  * NVE flow label suffix. Constant 8 LSBs of the flow label.
9625  * Reserved when nve_flh=1 and for Spectrum.
9626  * Access: RW
9627  */
9628 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
9629
9630 enum {
9631         /* Source UDP port is fixed (default '0') */
9632         MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
9633         /* Source UDP port is calculated based on hash */
9634         MLXSW_REG_TNGCR_UDP_SPORT_HASH,
9635 };
9636
9637 /* reg_tngcr_nve_udp_sport_type
9638  * NVE UDP source port type.
9639  * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2).
9640  * When the source UDP port is calculated based on hash, then the 8 LSBs
9641  * are calculated from hash the 8 MSBs are configured by
9642  * nve_udp_sport_prefix.
9643  * Access: RW
9644  */
9645 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
9646
9647 /* reg_tngcr_nve_udp_sport_prefix
9648  * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port.
9649  * Reserved when NVE type is NVGRE.
9650  * Access: RW
9651  */
9652 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
9653
9654 /* reg_tngcr_nve_group_size_mc
9655  * The amount of sequential linked lists of MC entries. The first linked
9656  * list is configured by SFD.underlay_mc_ptr.
9657  * Valid values: 1, 2, 4, 8, 16, 32, 64
9658  * The linked list are configured by TNUMT.
9659  * The hash is set by LAG hash.
9660  * Access: RW
9661  */
9662 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
9663
9664 /* reg_tngcr_nve_group_size_flood
9665  * The amount of sequential linked lists of flooding entries. The first
9666  * linked list is configured by SFMR.nve_tunnel_flood_ptr
9667  * Valid values: 1, 2, 4, 8, 16, 32, 64
9668  * The linked list are configured by TNUMT.
9669  * The hash is set by LAG hash.
9670  * Access: RW
9671  */
9672 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
9673
9674 /* reg_tngcr_learn_enable
9675  * During decapsulation, whether to learn from NVE port.
9676  * Reserved when Spectrum-2. See TNPC.
9677  * Access: RW
9678  */
9679 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
9680
9681 /* reg_tngcr_underlay_virtual_router
9682  * Underlay virtual router.
9683  * Reserved when Spectrum-2.
9684  * Access: RW
9685  */
9686 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
9687
9688 /* reg_tngcr_underlay_rif
9689  * Underlay ingress router interface. RIF type should be loopback generic.
9690  * Reserved when Spectrum.
9691  * Access: RW
9692  */
9693 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
9694
9695 /* reg_tngcr_usipv4
9696  * Underlay source IPv4 address of the NVE.
9697  * Access: RW
9698  */
9699 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
9700
9701 /* reg_tngcr_usipv6
9702  * Underlay source IPv6 address of the NVE. For Spectrum, must not be
9703  * modified under traffic of NVE tunneling encapsulation.
9704  * Access: RW
9705  */
9706 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
9707
9708 static inline void mlxsw_reg_tngcr_pack(char *payload,
9709                                         enum mlxsw_reg_tngcr_type type,
9710                                         bool valid, u8 ttl)
9711 {
9712         MLXSW_REG_ZERO(tngcr, payload);
9713         mlxsw_reg_tngcr_type_set(payload, type);
9714         mlxsw_reg_tngcr_nve_valid_set(payload, valid);
9715         mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
9716         mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
9717         mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
9718         mlxsw_reg_tngcr_nve_flh_set(payload, 0);
9719         mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
9720                                                MLXSW_REG_TNGCR_UDP_SPORT_HASH);
9721         mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
9722         mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
9723         mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
9724 }
9725
9726 /* TNUMT - Tunneling NVE Underlay Multicast Table Register
9727  * -------------------------------------------------------
9728  * The TNUMT register is for building the underlay MC table. It is used
9729  * for MC, flooding and BC traffic into the NVE tunnel.
9730  */
9731 #define MLXSW_REG_TNUMT_ID 0xA003
9732 #define MLXSW_REG_TNUMT_LEN 0x20
9733
9734 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
9735
9736 enum mlxsw_reg_tnumt_record_type {
9737         MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
9738         MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
9739         MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
9740 };
9741
9742 /* reg_tnumt_record_type
9743  * Record type.
9744  * Access: RW
9745  */
9746 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
9747
9748 enum mlxsw_reg_tnumt_tunnel_port {
9749         MLXSW_REG_TNUMT_TUNNEL_PORT_NVE,
9750         MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS,
9751         MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0,
9752         MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1,
9753 };
9754
9755 /* reg_tnumt_tunnel_port
9756  * Tunnel port.
9757  * Access: RW
9758  */
9759 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
9760
9761 /* reg_tnumt_underlay_mc_ptr
9762  * Index to the underlay multicast table.
9763  * For Spectrum the index is to the KVD linear.
9764  * Access: Index
9765  */
9766 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
9767
9768 /* reg_tnumt_vnext
9769  * The next_underlay_mc_ptr is valid.
9770  * Access: RW
9771  */
9772 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
9773
9774 /* reg_tnumt_next_underlay_mc_ptr
9775  * The next index to the underlay multicast table.
9776  * Access: RW
9777  */
9778 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
9779
9780 /* reg_tnumt_record_size
9781  * Number of IP addresses in the record.
9782  * Range is 1..cap_max_nve_mc_entries_ipv{4,6}
9783  * Access: RW
9784  */
9785 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
9786
9787 /* reg_tnumt_udip
9788  * The underlay IPv4 addresses. udip[i] is reserved if i >= size
9789  * Access: RW
9790  */
9791 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
9792
9793 /* reg_tnumt_udip_ptr
9794  * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if
9795  * i >= size. The IPv6 addresses are configured by RIPS.
9796  * Access: RW
9797  */
9798 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
9799
9800 static inline void mlxsw_reg_tnumt_pack(char *payload,
9801                                         enum mlxsw_reg_tnumt_record_type type,
9802                                         enum mlxsw_reg_tnumt_tunnel_port tport,
9803                                         u32 underlay_mc_ptr, bool vnext,
9804                                         u32 next_underlay_mc_ptr,
9805                                         u8 record_size)
9806 {
9807         MLXSW_REG_ZERO(tnumt, payload);
9808         mlxsw_reg_tnumt_record_type_set(payload, type);
9809         mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
9810         mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
9811         mlxsw_reg_tnumt_vnext_set(payload, vnext);
9812         mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
9813         mlxsw_reg_tnumt_record_size_set(payload, record_size);
9814 }
9815
9816 /* TNQCR - Tunneling NVE QoS Configuration Register
9817  * ------------------------------------------------
9818  * The TNQCR register configures how QoS is set in encapsulation into the
9819  * underlay network.
9820  */
9821 #define MLXSW_REG_TNQCR_ID 0xA010
9822 #define MLXSW_REG_TNQCR_LEN 0x0C
9823
9824 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
9825
9826 /* reg_tnqcr_enc_set_dscp
9827  * For encapsulation: How to set DSCP field:
9828  * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay
9829  * (outer) IP header. If there is no IP header, use TNQDR.dscp
9830  * 1 - Set the DSCP field as TNQDR.dscp
9831  * Access: RW
9832  */
9833 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
9834
9835 static inline void mlxsw_reg_tnqcr_pack(char *payload)
9836 {
9837         MLXSW_REG_ZERO(tnqcr, payload);
9838         mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
9839 }
9840
9841 /* TNQDR - Tunneling NVE QoS Default Register
9842  * ------------------------------------------
9843  * The TNQDR register configures the default QoS settings for NVE
9844  * encapsulation.
9845  */
9846 #define MLXSW_REG_TNQDR_ID 0xA011
9847 #define MLXSW_REG_TNQDR_LEN 0x08
9848
9849 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
9850
9851 /* reg_tnqdr_local_port
9852  * Local port number (receive port). CPU port is supported.
9853  * Access: Index
9854  */
9855 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8);
9856
9857 /* reg_tnqdr_dscp
9858  * For encapsulation, the default DSCP.
9859  * Access: RW
9860  */
9861 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
9862
9863 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
9864 {
9865         MLXSW_REG_ZERO(tnqdr, payload);
9866         mlxsw_reg_tnqdr_local_port_set(payload, local_port);
9867         mlxsw_reg_tnqdr_dscp_set(payload, 0);
9868 }
9869
9870 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
9871  * --------------------------------------------------------
9872  * The TNEEM register maps ECN of the IP header at the ingress to the
9873  * encapsulation to the ECN of the underlay network.
9874  */
9875 #define MLXSW_REG_TNEEM_ID 0xA012
9876 #define MLXSW_REG_TNEEM_LEN 0x0C
9877
9878 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
9879
9880 /* reg_tneem_overlay_ecn
9881  * ECN of the IP header in the overlay network.
9882  * Access: Index
9883  */
9884 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
9885
9886 /* reg_tneem_underlay_ecn
9887  * ECN of the IP header in the underlay network.
9888  * Access: RW
9889  */
9890 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
9891
9892 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
9893                                         u8 underlay_ecn)
9894 {
9895         MLXSW_REG_ZERO(tneem, payload);
9896         mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
9897         mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
9898 }
9899
9900 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register
9901  * --------------------------------------------------------
9902  * The TNDEM register configures the actions that are done in the
9903  * decapsulation.
9904  */
9905 #define MLXSW_REG_TNDEM_ID 0xA013
9906 #define MLXSW_REG_TNDEM_LEN 0x0C
9907
9908 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
9909
9910 /* reg_tndem_underlay_ecn
9911  * ECN field of the IP header in the underlay network.
9912  * Access: Index
9913  */
9914 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
9915
9916 /* reg_tndem_overlay_ecn
9917  * ECN field of the IP header in the overlay network.
9918  * Access: Index
9919  */
9920 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
9921
9922 /* reg_tndem_eip_ecn
9923  * Egress IP ECN. ECN field of the IP header of the packet which goes out
9924  * from the decapsulation.
9925  * Access: RW
9926  */
9927 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
9928
9929 /* reg_tndem_trap_en
9930  * Trap enable:
9931  * 0 - No trap due to decap ECN
9932  * 1 - Trap enable with trap_id
9933  * Access: RW
9934  */
9935 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
9936
9937 /* reg_tndem_trap_id
9938  * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
9939  * Reserved when trap_en is '0'.
9940  * Access: RW
9941  */
9942 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
9943
9944 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
9945                                         u8 overlay_ecn, u8 ecn, bool trap_en,
9946                                         u16 trap_id)
9947 {
9948         MLXSW_REG_ZERO(tndem, payload);
9949         mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
9950         mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
9951         mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
9952         mlxsw_reg_tndem_trap_en_set(payload, trap_en);
9953         mlxsw_reg_tndem_trap_id_set(payload, trap_id);
9954 }
9955
9956 /* TNPC - Tunnel Port Configuration Register
9957  * -----------------------------------------
9958  * The TNPC register is used for tunnel port configuration.
9959  * Reserved when Spectrum.
9960  */
9961 #define MLXSW_REG_TNPC_ID 0xA020
9962 #define MLXSW_REG_TNPC_LEN 0x18
9963
9964 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
9965
9966 enum mlxsw_reg_tnpc_tunnel_port {
9967         MLXSW_REG_TNPC_TUNNEL_PORT_NVE,
9968         MLXSW_REG_TNPC_TUNNEL_PORT_VPLS,
9969         MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0,
9970         MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1,
9971 };
9972
9973 /* reg_tnpc_tunnel_port
9974  * Tunnel port.
9975  * Access: Index
9976  */
9977 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
9978
9979 /* reg_tnpc_learn_enable_v6
9980  * During IPv6 underlay decapsulation, whether to learn from tunnel port.
9981  * Access: RW
9982  */
9983 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
9984
9985 /* reg_tnpc_learn_enable_v4
9986  * During IPv4 underlay decapsulation, whether to learn from tunnel port.
9987  * Access: RW
9988  */
9989 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
9990
9991 static inline void mlxsw_reg_tnpc_pack(char *payload,
9992                                        enum mlxsw_reg_tnpc_tunnel_port tport,
9993                                        bool learn_enable)
9994 {
9995         MLXSW_REG_ZERO(tnpc, payload);
9996         mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
9997         mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
9998         mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
9999 }
10000
10001 /* TIGCR - Tunneling IPinIP General Configuration Register
10002  * -------------------------------------------------------
10003  * The TIGCR register is used for setting up the IPinIP Tunnel configuration.
10004  */
10005 #define MLXSW_REG_TIGCR_ID 0xA801
10006 #define MLXSW_REG_TIGCR_LEN 0x10
10007
10008 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
10009
10010 /* reg_tigcr_ipip_ttlc
10011  * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet
10012  * header.
10013  * Access: RW
10014  */
10015 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
10016
10017 /* reg_tigcr_ipip_ttl_uc
10018  * The TTL for IPinIP Tunnel encapsulation of unicast packets if
10019  * reg_tigcr_ipip_ttlc is unset.
10020  * Access: RW
10021  */
10022 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
10023
10024 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
10025 {
10026         MLXSW_REG_ZERO(tigcr, payload);
10027         mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
10028         mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
10029 }
10030
10031 /* SBPR - Shared Buffer Pools Register
10032  * -----------------------------------
10033  * The SBPR configures and retrieves the shared buffer pools and configuration.
10034  */
10035 #define MLXSW_REG_SBPR_ID 0xB001
10036 #define MLXSW_REG_SBPR_LEN 0x14
10037
10038 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
10039
10040 /* shared direstion enum for SBPR, SBCM, SBPM */
10041 enum mlxsw_reg_sbxx_dir {
10042         MLXSW_REG_SBXX_DIR_INGRESS,
10043         MLXSW_REG_SBXX_DIR_EGRESS,
10044 };
10045
10046 /* reg_sbpr_dir
10047  * Direction.
10048  * Access: Index
10049  */
10050 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
10051
10052 /* reg_sbpr_pool
10053  * Pool index.
10054  * Access: Index
10055  */
10056 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
10057
10058 /* reg_sbpr_infi_size
10059  * Size is infinite.
10060  * Access: RW
10061  */
10062 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
10063
10064 /* reg_sbpr_size
10065  * Pool size in buffer cells.
10066  * Reserved when infi_size = 1.
10067  * Access: RW
10068  */
10069 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
10070
10071 enum mlxsw_reg_sbpr_mode {
10072         MLXSW_REG_SBPR_MODE_STATIC,
10073         MLXSW_REG_SBPR_MODE_DYNAMIC,
10074 };
10075
10076 /* reg_sbpr_mode
10077  * Pool quota calculation mode.
10078  * Access: RW
10079  */
10080 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
10081
10082 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
10083                                        enum mlxsw_reg_sbxx_dir dir,
10084                                        enum mlxsw_reg_sbpr_mode mode, u32 size,
10085                                        bool infi_size)
10086 {
10087         MLXSW_REG_ZERO(sbpr, payload);
10088         mlxsw_reg_sbpr_pool_set(payload, pool);
10089         mlxsw_reg_sbpr_dir_set(payload, dir);
10090         mlxsw_reg_sbpr_mode_set(payload, mode);
10091         mlxsw_reg_sbpr_size_set(payload, size);
10092         mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
10093 }
10094
10095 /* SBCM - Shared Buffer Class Management Register
10096  * ----------------------------------------------
10097  * The SBCM register configures and retrieves the shared buffer allocation
10098  * and configuration according to Port-PG, including the binding to pool
10099  * and definition of the associated quota.
10100  */
10101 #define MLXSW_REG_SBCM_ID 0xB002
10102 #define MLXSW_REG_SBCM_LEN 0x28
10103
10104 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
10105
10106 /* reg_sbcm_local_port
10107  * Local port number.
10108  * For Ingress: excludes CPU port and Router port
10109  * For Egress: excludes IP Router
10110  * Access: Index
10111  */
10112 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
10113
10114 /* reg_sbcm_pg_buff
10115  * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
10116  * For PG buffer: range is 0..cap_max_pg_buffers - 1
10117  * For traffic class: range is 0..cap_max_tclass - 1
10118  * Note that when traffic class is in MC aware mode then the traffic
10119  * classes which are MC aware cannot be configured.
10120  * Access: Index
10121  */
10122 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
10123
10124 /* reg_sbcm_dir
10125  * Direction.
10126  * Access: Index
10127  */
10128 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
10129
10130 /* reg_sbcm_min_buff
10131  * Minimum buffer size for the limiter, in cells.
10132  * Access: RW
10133  */
10134 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
10135
10136 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
10137 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
10138 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
10139
10140 /* reg_sbcm_infi_max
10141  * Max buffer is infinite.
10142  * Access: RW
10143  */
10144 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
10145
10146 /* reg_sbcm_max_buff
10147  * When the pool associated to the port-pg/tclass is configured to
10148  * static, Maximum buffer size for the limiter configured in cells.
10149  * When the pool associated to the port-pg/tclass is configured to
10150  * dynamic, the max_buff holds the "alpha" parameter, supporting
10151  * the following values:
10152  * 0: 0
10153  * i: (1/128)*2^(i-1), for i=1..14
10154  * 0xFF: Infinity
10155  * Reserved when infi_max = 1.
10156  * Access: RW
10157  */
10158 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
10159
10160 /* reg_sbcm_pool
10161  * Association of the port-priority to a pool.
10162  * Access: RW
10163  */
10164 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
10165
10166 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
10167                                        enum mlxsw_reg_sbxx_dir dir,
10168                                        u32 min_buff, u32 max_buff,
10169                                        bool infi_max, u8 pool)
10170 {
10171         MLXSW_REG_ZERO(sbcm, payload);
10172         mlxsw_reg_sbcm_local_port_set(payload, local_port);
10173         mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
10174         mlxsw_reg_sbcm_dir_set(payload, dir);
10175         mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
10176         mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
10177         mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
10178         mlxsw_reg_sbcm_pool_set(payload, pool);
10179 }
10180
10181 /* SBPM - Shared Buffer Port Management Register
10182  * ---------------------------------------------
10183  * The SBPM register configures and retrieves the shared buffer allocation
10184  * and configuration according to Port-Pool, including the definition
10185  * of the associated quota.
10186  */
10187 #define MLXSW_REG_SBPM_ID 0xB003
10188 #define MLXSW_REG_SBPM_LEN 0x28
10189
10190 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
10191
10192 /* reg_sbpm_local_port
10193  * Local port number.
10194  * For Ingress: excludes CPU port and Router port
10195  * For Egress: excludes IP Router
10196  * Access: Index
10197  */
10198 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
10199
10200 /* reg_sbpm_pool
10201  * The pool associated to quota counting on the local_port.
10202  * Access: Index
10203  */
10204 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
10205
10206 /* reg_sbpm_dir
10207  * Direction.
10208  * Access: Index
10209  */
10210 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
10211
10212 /* reg_sbpm_buff_occupancy
10213  * Current buffer occupancy in cells.
10214  * Access: RO
10215  */
10216 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
10217
10218 /* reg_sbpm_clr
10219  * Clear Max Buffer Occupancy
10220  * When this bit is set, max_buff_occupancy field is cleared (and a
10221  * new max value is tracked from the time the clear was performed).
10222  * Access: OP
10223  */
10224 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
10225
10226 /* reg_sbpm_max_buff_occupancy
10227  * Maximum value of buffer occupancy in cells monitored. Cleared by
10228  * writing to the clr field.
10229  * Access: RO
10230  */
10231 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
10232
10233 /* reg_sbpm_min_buff
10234  * Minimum buffer size for the limiter, in cells.
10235  * Access: RW
10236  */
10237 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
10238
10239 /* reg_sbpm_max_buff
10240  * When the pool associated to the port-pg/tclass is configured to
10241  * static, Maximum buffer size for the limiter configured in cells.
10242  * When the pool associated to the port-pg/tclass is configured to
10243  * dynamic, the max_buff holds the "alpha" parameter, supporting
10244  * the following values:
10245  * 0: 0
10246  * i: (1/128)*2^(i-1), for i=1..14
10247  * 0xFF: Infinity
10248  * Access: RW
10249  */
10250 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
10251
10252 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
10253                                        enum mlxsw_reg_sbxx_dir dir, bool clr,
10254                                        u32 min_buff, u32 max_buff)
10255 {
10256         MLXSW_REG_ZERO(sbpm, payload);
10257         mlxsw_reg_sbpm_local_port_set(payload, local_port);
10258         mlxsw_reg_sbpm_pool_set(payload, pool);
10259         mlxsw_reg_sbpm_dir_set(payload, dir);
10260         mlxsw_reg_sbpm_clr_set(payload, clr);
10261         mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
10262         mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
10263 }
10264
10265 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
10266                                          u32 *p_max_buff_occupancy)
10267 {
10268         *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
10269         *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
10270 }
10271
10272 /* SBMM - Shared Buffer Multicast Management Register
10273  * --------------------------------------------------
10274  * The SBMM register configures and retrieves the shared buffer allocation
10275  * and configuration for MC packets according to Switch-Priority, including
10276  * the binding to pool and definition of the associated quota.
10277  */
10278 #define MLXSW_REG_SBMM_ID 0xB004
10279 #define MLXSW_REG_SBMM_LEN 0x28
10280
10281 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
10282
10283 /* reg_sbmm_prio
10284  * Switch Priority.
10285  * Access: Index
10286  */
10287 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
10288
10289 /* reg_sbmm_min_buff
10290  * Minimum buffer size for the limiter, in cells.
10291  * Access: RW
10292  */
10293 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
10294
10295 /* reg_sbmm_max_buff
10296  * When the pool associated to the port-pg/tclass is configured to
10297  * static, Maximum buffer size for the limiter configured in cells.
10298  * When the pool associated to the port-pg/tclass is configured to
10299  * dynamic, the max_buff holds the "alpha" parameter, supporting
10300  * the following values:
10301  * 0: 0
10302  * i: (1/128)*2^(i-1), for i=1..14
10303  * 0xFF: Infinity
10304  * Access: RW
10305  */
10306 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
10307
10308 /* reg_sbmm_pool
10309  * Association of the port-priority to a pool.
10310  * Access: RW
10311  */
10312 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
10313
10314 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
10315                                        u32 max_buff, u8 pool)
10316 {
10317         MLXSW_REG_ZERO(sbmm, payload);
10318         mlxsw_reg_sbmm_prio_set(payload, prio);
10319         mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
10320         mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
10321         mlxsw_reg_sbmm_pool_set(payload, pool);
10322 }
10323
10324 /* SBSR - Shared Buffer Status Register
10325  * ------------------------------------
10326  * The SBSR register retrieves the shared buffer occupancy according to
10327  * Port-Pool. Note that this register enables reading a large amount of data.
10328  * It is the user's responsibility to limit the amount of data to ensure the
10329  * response can match the maximum transfer unit. In case the response exceeds
10330  * the maximum transport unit, it will be truncated with no special notice.
10331  */
10332 #define MLXSW_REG_SBSR_ID 0xB005
10333 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
10334 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
10335 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
10336 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN +   \
10337                             MLXSW_REG_SBSR_REC_LEN *    \
10338                             MLXSW_REG_SBSR_REC_MAX_COUNT)
10339
10340 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
10341
10342 /* reg_sbsr_clr
10343  * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
10344  * field is cleared (and a new max value is tracked from the time the clear
10345  * was performed).
10346  * Access: OP
10347  */
10348 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
10349
10350 /* reg_sbsr_ingress_port_mask
10351  * Bit vector for all ingress network ports.
10352  * Indicates which of the ports (for which the relevant bit is set)
10353  * are affected by the set operation. Configuration of any other port
10354  * does not change.
10355  * Access: Index
10356  */
10357 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
10358
10359 /* reg_sbsr_pg_buff_mask
10360  * Bit vector for all switch priority groups.
10361  * Indicates which of the priorities (for which the relevant bit is set)
10362  * are affected by the set operation. Configuration of any other priority
10363  * does not change.
10364  * Range is 0..cap_max_pg_buffers - 1
10365  * Access: Index
10366  */
10367 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
10368
10369 /* reg_sbsr_egress_port_mask
10370  * Bit vector for all egress network ports.
10371  * Indicates which of the ports (for which the relevant bit is set)
10372  * are affected by the set operation. Configuration of any other port
10373  * does not change.
10374  * Access: Index
10375  */
10376 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
10377
10378 /* reg_sbsr_tclass_mask
10379  * Bit vector for all traffic classes.
10380  * Indicates which of the traffic classes (for which the relevant bit is
10381  * set) are affected by the set operation. Configuration of any other
10382  * traffic class does not change.
10383  * Range is 0..cap_max_tclass - 1
10384  * Access: Index
10385  */
10386 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
10387
10388 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
10389 {
10390         MLXSW_REG_ZERO(sbsr, payload);
10391         mlxsw_reg_sbsr_clr_set(payload, clr);
10392 }
10393
10394 /* reg_sbsr_rec_buff_occupancy
10395  * Current buffer occupancy in cells.
10396  * Access: RO
10397  */
10398 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
10399                      0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
10400
10401 /* reg_sbsr_rec_max_buff_occupancy
10402  * Maximum value of buffer occupancy in cells monitored. Cleared by
10403  * writing to the clr field.
10404  * Access: RO
10405  */
10406 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
10407                      0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
10408
10409 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
10410                                              u32 *p_buff_occupancy,
10411                                              u32 *p_max_buff_occupancy)
10412 {
10413         *p_buff_occupancy =
10414                 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
10415         *p_max_buff_occupancy =
10416                 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
10417 }
10418
10419 /* SBIB - Shared Buffer Internal Buffer Register
10420  * ---------------------------------------------
10421  * The SBIB register configures per port buffers for internal use. The internal
10422  * buffers consume memory on the port buffers (note that the port buffers are
10423  * used also by PBMC).
10424  *
10425  * For Spectrum this is used for egress mirroring.
10426  */
10427 #define MLXSW_REG_SBIB_ID 0xB006
10428 #define MLXSW_REG_SBIB_LEN 0x10
10429
10430 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
10431
10432 /* reg_sbib_local_port
10433  * Local port number
10434  * Not supported for CPU port and router port
10435  * Access: Index
10436  */
10437 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
10438
10439 /* reg_sbib_buff_size
10440  * Units represented in cells
10441  * Allowed range is 0 to (cap_max_headroom_size - 1)
10442  * Default is 0
10443  * Access: RW
10444  */
10445 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
10446
10447 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
10448                                        u32 buff_size)
10449 {
10450         MLXSW_REG_ZERO(sbib, payload);
10451         mlxsw_reg_sbib_local_port_set(payload, local_port);
10452         mlxsw_reg_sbib_buff_size_set(payload, buff_size);
10453 }
10454
10455 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
10456         MLXSW_REG(sgcr),
10457         MLXSW_REG(spad),
10458         MLXSW_REG(smid),
10459         MLXSW_REG(sspr),
10460         MLXSW_REG(sfdat),
10461         MLXSW_REG(sfd),
10462         MLXSW_REG(sfn),
10463         MLXSW_REG(spms),
10464         MLXSW_REG(spvid),
10465         MLXSW_REG(spvm),
10466         MLXSW_REG(spaft),
10467         MLXSW_REG(sfgc),
10468         MLXSW_REG(sftr),
10469         MLXSW_REG(sfdf),
10470         MLXSW_REG(sldr),
10471         MLXSW_REG(slcr),
10472         MLXSW_REG(slcor),
10473         MLXSW_REG(spmlr),
10474         MLXSW_REG(svfa),
10475         MLXSW_REG(svpe),
10476         MLXSW_REG(sfmr),
10477         MLXSW_REG(spvmlr),
10478         MLXSW_REG(cwtp),
10479         MLXSW_REG(cwtpm),
10480         MLXSW_REG(pgcr),
10481         MLXSW_REG(ppbt),
10482         MLXSW_REG(pacl),
10483         MLXSW_REG(pagt),
10484         MLXSW_REG(ptar),
10485         MLXSW_REG(ppbs),
10486         MLXSW_REG(prcr),
10487         MLXSW_REG(pefa),
10488         MLXSW_REG(pemrbt),
10489         MLXSW_REG(ptce2),
10490         MLXSW_REG(perpt),
10491         MLXSW_REG(peabfe),
10492         MLXSW_REG(perar),
10493         MLXSW_REG(ptce3),
10494         MLXSW_REG(percr),
10495         MLXSW_REG(pererp),
10496         MLXSW_REG(iedr),
10497         MLXSW_REG(qpts),
10498         MLXSW_REG(qpcr),
10499         MLXSW_REG(qtct),
10500         MLXSW_REG(qeec),
10501         MLXSW_REG(qrwe),
10502         MLXSW_REG(qpdsm),
10503         MLXSW_REG(qpdpm),
10504         MLXSW_REG(qtctm),
10505         MLXSW_REG(qpsc),
10506         MLXSW_REG(pmlp),
10507         MLXSW_REG(pmtu),
10508         MLXSW_REG(ptys),
10509         MLXSW_REG(ppad),
10510         MLXSW_REG(paos),
10511         MLXSW_REG(pfcc),
10512         MLXSW_REG(ppcnt),
10513         MLXSW_REG(plib),
10514         MLXSW_REG(pptb),
10515         MLXSW_REG(pbmc),
10516         MLXSW_REG(pspa),
10517         MLXSW_REG(pplr),
10518         MLXSW_REG(htgt),
10519         MLXSW_REG(hpkt),
10520         MLXSW_REG(rgcr),
10521         MLXSW_REG(ritr),
10522         MLXSW_REG(rtar),
10523         MLXSW_REG(ratr),
10524         MLXSW_REG(rtdp),
10525         MLXSW_REG(rdpm),
10526         MLXSW_REG(ricnt),
10527         MLXSW_REG(rrcr),
10528         MLXSW_REG(ralta),
10529         MLXSW_REG(ralst),
10530         MLXSW_REG(raltb),
10531         MLXSW_REG(ralue),
10532         MLXSW_REG(rauht),
10533         MLXSW_REG(raleu),
10534         MLXSW_REG(rauhtd),
10535         MLXSW_REG(rigr2),
10536         MLXSW_REG(recr2),
10537         MLXSW_REG(rmft2),
10538         MLXSW_REG(mfcr),
10539         MLXSW_REG(mfsc),
10540         MLXSW_REG(mfsm),
10541         MLXSW_REG(mfsl),
10542         MLXSW_REG(fore),
10543         MLXSW_REG(mtcap),
10544         MLXSW_REG(mtmp),
10545         MLXSW_REG(mtbr),
10546         MLXSW_REG(mcia),
10547         MLXSW_REG(mpat),
10548         MLXSW_REG(mpar),
10549         MLXSW_REG(mgir),
10550         MLXSW_REG(mrsr),
10551         MLXSW_REG(mlcr),
10552         MLXSW_REG(mtpps),
10553         MLXSW_REG(mtutc),
10554         MLXSW_REG(mpsc),
10555         MLXSW_REG(mcqi),
10556         MLXSW_REG(mcc),
10557         MLXSW_REG(mcda),
10558         MLXSW_REG(mgpc),
10559         MLXSW_REG(mprs),
10560         MLXSW_REG(mogcr),
10561         MLXSW_REG(mtpppc),
10562         MLXSW_REG(mtpptr),
10563         MLXSW_REG(mtptpt),
10564         MLXSW_REG(mgpir),
10565         MLXSW_REG(tngcr),
10566         MLXSW_REG(tnumt),
10567         MLXSW_REG(tnqcr),
10568         MLXSW_REG(tnqdr),
10569         MLXSW_REG(tneem),
10570         MLXSW_REG(tndem),
10571         MLXSW_REG(tnpc),
10572         MLXSW_REG(tigcr),
10573         MLXSW_REG(sbpr),
10574         MLXSW_REG(sbcm),
10575         MLXSW_REG(sbpm),
10576         MLXSW_REG(sbmm),
10577         MLXSW_REG(sbsr),
10578         MLXSW_REG(sbib),
10579 };
10580
10581 static inline const char *mlxsw_reg_id_str(u16 reg_id)
10582 {
10583         const struct mlxsw_reg_info *reg_info;
10584         int i;
10585
10586         for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
10587                 reg_info = mlxsw_reg_infos[i];
10588                 if (reg_info->id == reg_id)
10589                         return reg_info->name;
10590         }
10591         return "*UNKNOWN*";
10592 }
10593
10594 /* PUDE - Port Up / Down Event
10595  * ---------------------------
10596  * Reports the operational state change of a port.
10597  */
10598 #define MLXSW_REG_PUDE_LEN 0x10
10599
10600 /* reg_pude_swid
10601  * Switch partition ID with which to associate the port.
10602  * Access: Index
10603  */
10604 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
10605
10606 /* reg_pude_local_port
10607  * Local port number.
10608  * Access: Index
10609  */
10610 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
10611
10612 /* reg_pude_admin_status
10613  * Port administrative state (the desired state).
10614  * 1 - Up.
10615  * 2 - Down.
10616  * 3 - Up once. This means that in case of link failure, the port won't go
10617  *     into polling mode, but will wait to be re-enabled by software.
10618  * 4 - Disabled by system. Can only be set by hardware.
10619  * Access: RO
10620  */
10621 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
10622
10623 /* reg_pude_oper_status
10624  * Port operatioanl state.
10625  * 1 - Up.
10626  * 2 - Down.
10627  * 3 - Down by port failure. This means that the device will not let the
10628  *     port up again until explicitly specified by software.
10629  * Access: RO
10630  */
10631 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
10632
10633 #endif