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mlxsw: spectrum: Send untagged packets through a port netdev
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
1 /*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/ethtool.h>
43 #include <linux/slab.h>
44 #include <linux/device.h>
45 #include <linux/skbuff.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/workqueue.h>
49 #include <linux/jiffies.h>
50 #include <linux/bitops.h>
51 #include <linux/list.h>
52 #include <linux/notifier.h>
53 #include <linux/dcbnl.h>
54 #include <net/switchdev.h>
55 #include <generated/utsrelease.h>
56
57 #include "spectrum.h"
58 #include "core.h"
59 #include "reg.h"
60 #include "port.h"
61 #include "trap.h"
62 #include "txheader.h"
63
64 static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
65 static const char mlxsw_sp_driver_version[] = "1.0";
66
67 /* tx_hdr_version
68 * Tx header version.
69 * Must be set to 1.
70 */
71 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
72
73 /* tx_hdr_ctl
74 * Packet control type.
75 * 0 - Ethernet control (e.g. EMADs, LACP)
76 * 1 - Ethernet data
77 */
78 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
79
80 /* tx_hdr_proto
81 * Packet protocol type. Must be set to 1 (Ethernet).
82 */
83 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
84
85 /* tx_hdr_rx_is_router
86 * Packet is sent from the router. Valid for data packets only.
87 */
88 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
89
90 /* tx_hdr_fid_valid
91 * Indicates if the 'fid' field is valid and should be used for
92 * forwarding lookup. Valid for data packets only.
93 */
94 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
95
96 /* tx_hdr_swid
97 * Switch partition ID. Must be set to 0.
98 */
99 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
100
101 /* tx_hdr_control_tclass
102 * Indicates if the packet should use the control TClass and not one
103 * of the data TClasses.
104 */
105 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
106
107 /* tx_hdr_etclass
108 * Egress TClass to be used on the egress device on the egress port.
109 */
110 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
111
112 /* tx_hdr_port_mid
113 * Destination local port for unicast packets.
114 * Destination multicast ID for multicast packets.
115 *
116 * Control packets are directed to a specific egress port, while data
117 * packets are transmitted through the CPU port (0) into the switch partition,
118 * where forwarding rules are applied.
119 */
120 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
121
122 /* tx_hdr_fid
123 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
124 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
125 * Valid for data packets only.
126 */
127 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
128
129 /* tx_hdr_type
130 * 0 - Data packets
131 * 6 - Control packets
132 */
133 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
134
135 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
136 const struct mlxsw_tx_info *tx_info)
137 {
138 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
139
140 memset(txhdr, 0, MLXSW_TXHDR_LEN);
141
142 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
143 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
144 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
145 mlxsw_tx_hdr_swid_set(txhdr, 0);
146 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
149 }
150
151 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
152 {
153 char spad_pl[MLXSW_REG_SPAD_LEN];
154 int err;
155
156 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
157 if (err)
158 return err;
159 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
160 return 0;
161 }
162
163 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
164 bool is_up)
165 {
166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
167 char paos_pl[MLXSW_REG_PAOS_LEN];
168
169 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
170 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
171 MLXSW_PORT_ADMIN_STATUS_DOWN);
172 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
173 }
174
175 static int mlxsw_sp_port_oper_status_get(struct mlxsw_sp_port *mlxsw_sp_port,
176 bool *p_is_up)
177 {
178 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
179 char paos_pl[MLXSW_REG_PAOS_LEN];
180 u8 oper_status;
181 int err;
182
183 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 0);
184 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
185 if (err)
186 return err;
187 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
188 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
189 return 0;
190 }
191
192 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
193 unsigned char *addr)
194 {
195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
196 char ppad_pl[MLXSW_REG_PPAD_LEN];
197
198 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
199 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
201 }
202
203 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
204 {
205 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
206 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
207
208 ether_addr_copy(addr, mlxsw_sp->base_mac);
209 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
210 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
211 }
212
213 static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
214 u16 vid, enum mlxsw_reg_spms_state state)
215 {
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
217 char *spms_pl;
218 int err;
219
220 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
221 if (!spms_pl)
222 return -ENOMEM;
223 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
224 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
225 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
226 kfree(spms_pl);
227 return err;
228 }
229
230 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
231 {
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
233 char pmtu_pl[MLXSW_REG_PMTU_LEN];
234 int max_mtu;
235 int err;
236
237 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
238 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
239 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
240 if (err)
241 return err;
242 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
243
244 if (mtu > max_mtu)
245 return -EINVAL;
246
247 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
249 }
250
251 static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
252 u8 swid)
253 {
254 char pspa_pl[MLXSW_REG_PSPA_LEN];
255
256 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
257 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
258 }
259
260 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
261 {
262 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
263
264 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
265 swid);
266 }
267
268 static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
269 bool enable)
270 {
271 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
272 char svpe_pl[MLXSW_REG_SVPE_LEN];
273
274 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
275 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
276 }
277
278 int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
279 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
280 u16 vid)
281 {
282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
283 char svfa_pl[MLXSW_REG_SVFA_LEN];
284
285 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
286 fid, vid);
287 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
288 }
289
290 static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
291 u16 vid, bool learn_enable)
292 {
293 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
294 char *spvmlr_pl;
295 int err;
296
297 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
298 if (!spvmlr_pl)
299 return -ENOMEM;
300 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
301 learn_enable);
302 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
303 kfree(spvmlr_pl);
304 return err;
305 }
306
307 static int
308 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
309 {
310 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
311 char sspr_pl[MLXSW_REG_SSPR_LEN];
312
313 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
314 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
315 }
316
317 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
318 u8 local_port, u8 *p_module,
319 u8 *p_width, u8 *p_lane)
320 {
321 char pmlp_pl[MLXSW_REG_PMLP_LEN];
322 int err;
323
324 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
325 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
326 if (err)
327 return err;
328 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
329 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
330 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
331 return 0;
332 }
333
334 static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
335 u8 module, u8 width, u8 lane)
336 {
337 char pmlp_pl[MLXSW_REG_PMLP_LEN];
338 int i;
339
340 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
341 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
342 for (i = 0; i < width; i++) {
343 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
344 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
345 }
346
347 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
348 }
349
350 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
351 {
352 char pmlp_pl[MLXSW_REG_PMLP_LEN];
353
354 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
355 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
356 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
357 }
358
359 static int mlxsw_sp_port_open(struct net_device *dev)
360 {
361 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
362 int err;
363
364 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
365 if (err)
366 return err;
367 netif_start_queue(dev);
368 return 0;
369 }
370
371 static int mlxsw_sp_port_stop(struct net_device *dev)
372 {
373 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
374
375 netif_stop_queue(dev);
376 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
377 }
378
379 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
380 struct net_device *dev)
381 {
382 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
383 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
384 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
385 const struct mlxsw_tx_info tx_info = {
386 .local_port = mlxsw_sp_port->local_port,
387 .is_emad = false,
388 };
389 u64 len;
390 int err;
391
392 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
393 return NETDEV_TX_BUSY;
394
395 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
396 struct sk_buff *skb_orig = skb;
397
398 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
399 if (!skb) {
400 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
401 dev_kfree_skb_any(skb_orig);
402 return NETDEV_TX_OK;
403 }
404 }
405
406 if (eth_skb_pad(skb)) {
407 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
408 return NETDEV_TX_OK;
409 }
410
411 mlxsw_sp_txhdr_construct(skb, &tx_info);
412 /* TX header is consumed by HW on the way so we shouldn't count its
413 * bytes as being sent.
414 */
415 len = skb->len - MLXSW_TXHDR_LEN;
416
417 /* Due to a race we might fail here because of a full queue. In that
418 * unlikely case we simply drop the packet.
419 */
420 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
421
422 if (!err) {
423 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
424 u64_stats_update_begin(&pcpu_stats->syncp);
425 pcpu_stats->tx_packets++;
426 pcpu_stats->tx_bytes += len;
427 u64_stats_update_end(&pcpu_stats->syncp);
428 } else {
429 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
430 dev_kfree_skb_any(skb);
431 }
432 return NETDEV_TX_OK;
433 }
434
435 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
436 {
437 }
438
439 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
440 {
441 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
442 struct sockaddr *addr = p;
443 int err;
444
445 if (!is_valid_ether_addr(addr->sa_data))
446 return -EADDRNOTAVAIL;
447
448 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
449 if (err)
450 return err;
451 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
452 return 0;
453 }
454
455 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
456 bool pause_en, bool pfc_en, u16 delay)
457 {
458 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
459
460 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
461 MLXSW_SP_PAUSE_DELAY;
462
463 if (pause_en || pfc_en)
464 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
465 pg_size + delay, pg_size);
466 else
467 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
468 }
469
470 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
471 u8 *prio_tc, bool pause_en,
472 struct ieee_pfc *my_pfc)
473 {
474 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
475 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
476 u16 delay = !!my_pfc ? my_pfc->delay : 0;
477 char pbmc_pl[MLXSW_REG_PBMC_LEN];
478 int i, j, err;
479
480 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
481 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
482 if (err)
483 return err;
484
485 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
486 bool configure = false;
487 bool pfc = false;
488
489 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
490 if (prio_tc[j] == i) {
491 pfc = pfc_en & BIT(j);
492 configure = true;
493 break;
494 }
495 }
496
497 if (!configure)
498 continue;
499 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
500 }
501
502 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
503 }
504
505 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
506 int mtu, bool pause_en)
507 {
508 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
509 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
510 struct ieee_pfc *my_pfc;
511 u8 *prio_tc;
512
513 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
514 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
515
516 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
517 pause_en, my_pfc);
518 }
519
520 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
521 {
522 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
523 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
524 int err;
525
526 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
527 if (err)
528 return err;
529 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
530 if (err)
531 goto err_port_mtu_set;
532 dev->mtu = mtu;
533 return 0;
534
535 err_port_mtu_set:
536 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
537 return err;
538 }
539
540 static struct rtnl_link_stats64 *
541 mlxsw_sp_port_get_stats64(struct net_device *dev,
542 struct rtnl_link_stats64 *stats)
543 {
544 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
545 struct mlxsw_sp_port_pcpu_stats *p;
546 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
547 u32 tx_dropped = 0;
548 unsigned int start;
549 int i;
550
551 for_each_possible_cpu(i) {
552 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
553 do {
554 start = u64_stats_fetch_begin_irq(&p->syncp);
555 rx_packets = p->rx_packets;
556 rx_bytes = p->rx_bytes;
557 tx_packets = p->tx_packets;
558 tx_bytes = p->tx_bytes;
559 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
560
561 stats->rx_packets += rx_packets;
562 stats->rx_bytes += rx_bytes;
563 stats->tx_packets += tx_packets;
564 stats->tx_bytes += tx_bytes;
565 /* tx_dropped is u32, updated without syncp protection. */
566 tx_dropped += p->tx_dropped;
567 }
568 stats->tx_dropped = tx_dropped;
569 return stats;
570 }
571
572 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
573 u16 vid_end, bool is_member, bool untagged)
574 {
575 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
576 char *spvm_pl;
577 int err;
578
579 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
580 if (!spvm_pl)
581 return -ENOMEM;
582
583 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
584 vid_end, is_member, untagged);
585 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
586 kfree(spvm_pl);
587 return err;
588 }
589
590 static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
591 {
592 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
593 u16 vid, last_visited_vid;
594 int err;
595
596 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
597 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
598 vid);
599 if (err) {
600 last_visited_vid = vid;
601 goto err_port_vid_to_fid_set;
602 }
603 }
604
605 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
606 if (err) {
607 last_visited_vid = VLAN_N_VID;
608 goto err_port_vid_to_fid_set;
609 }
610
611 return 0;
612
613 err_port_vid_to_fid_set:
614 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
615 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
616 vid);
617 return err;
618 }
619
620 static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
621 {
622 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
623 u16 vid;
624 int err;
625
626 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
627 if (err)
628 return err;
629
630 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
631 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
632 vid, vid);
633 if (err)
634 return err;
635 }
636
637 return 0;
638 }
639
640 static struct mlxsw_sp_fid *
641 mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, u16 vid)
642 {
643 struct mlxsw_sp_fid *f;
644
645 list_for_each_entry(f, &mlxsw_sp->port_vfids.list, list) {
646 if (f->vid == vid)
647 return f;
648 }
649
650 return NULL;
651 }
652
653 static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
654 {
655 return find_first_zero_bit(mlxsw_sp->port_vfids.mapped,
656 MLXSW_SP_VFID_PORT_MAX);
657 }
658
659 static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
660 {
661 char sfmr_pl[MLXSW_REG_SFMR_LEN];
662
663 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
664 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
665 }
666
667 static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
668
669 static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
670 u16 vid)
671 {
672 struct device *dev = mlxsw_sp->bus_info->dev;
673 struct mlxsw_sp_fid *f;
674 u16 vfid, fid;
675 int err;
676
677 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
678 if (vfid == MLXSW_SP_VFID_PORT_MAX) {
679 dev_err(dev, "No available vFIDs\n");
680 return ERR_PTR(-ERANGE);
681 }
682
683 fid = mlxsw_sp_vfid_to_fid(vfid);
684 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
685 if (err) {
686 dev_err(dev, "Failed to create FID=%d\n", fid);
687 return ERR_PTR(err);
688 }
689
690 f = kzalloc(sizeof(*f), GFP_KERNEL);
691 if (!f)
692 goto err_allocate_vfid;
693
694 f->leave = mlxsw_sp_vport_vfid_leave;
695 f->fid = fid;
696 f->vid = vid;
697
698 list_add(&f->list, &mlxsw_sp->port_vfids.list);
699 set_bit(vfid, mlxsw_sp->port_vfids.mapped);
700
701 return f;
702
703 err_allocate_vfid:
704 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
705 return ERR_PTR(-ENOMEM);
706 }
707
708 static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
709 struct mlxsw_sp_fid *f)
710 {
711 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
712
713 clear_bit(vfid, mlxsw_sp->port_vfids.mapped);
714 list_del(&f->list);
715
716 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
717
718 kfree(f);
719 }
720
721 static struct mlxsw_sp_port *
722 mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
723 {
724 struct mlxsw_sp_port *mlxsw_sp_vport;
725
726 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
727 if (!mlxsw_sp_vport)
728 return NULL;
729
730 /* dev will be set correctly after the VLAN device is linked
731 * with the real device. In case of bridge SELF invocation, dev
732 * will remain as is.
733 */
734 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
735 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
736 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
737 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
738 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
739 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
740 mlxsw_sp_vport->vport.vid = vid;
741
742 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
743
744 return mlxsw_sp_vport;
745 }
746
747 static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
748 {
749 list_del(&mlxsw_sp_vport->vport.list);
750 kfree(mlxsw_sp_vport);
751 }
752
753 static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
754 bool valid)
755 {
756 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
757 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
758
759 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
760 vid);
761 }
762
763 static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport)
764 {
765 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
766 struct mlxsw_sp_fid *f;
767 int err;
768
769 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, vid);
770 if (!f) {
771 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, vid);
772 if (IS_ERR(f))
773 return PTR_ERR(f);
774 }
775
776 if (!f->ref_count) {
777 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
778 if (err)
779 goto err_vport_flood_set;
780 }
781
782 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
783 if (err)
784 goto err_vport_fid_map;
785
786 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
787 f->ref_count++;
788
789 return 0;
790
791 err_vport_fid_map:
792 if (!f->ref_count)
793 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
794 err_vport_flood_set:
795 if (!f->ref_count)
796 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
797 return err;
798 }
799
800 static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
801 {
802 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
803
804 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
805
806 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
807
808 if (--f->ref_count == 0) {
809 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
810 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
811 }
812 }
813
814 int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
815 u16 vid)
816 {
817 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
818 struct mlxsw_sp_port *mlxsw_sp_vport;
819 bool untagged = vid == 1;
820 int err;
821
822 /* VLAN 0 is added to HW filter when device goes up, but it is
823 * reserved in our case, so simply return.
824 */
825 if (!vid)
826 return 0;
827
828 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid)) {
829 netdev_warn(dev, "VID=%d already configured\n", vid);
830 return 0;
831 }
832
833 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
834 if (!mlxsw_sp_vport) {
835 netdev_err(dev, "Failed to create vPort for VID=%d\n", vid);
836 return -ENOMEM;
837 }
838
839 /* When adding the first VLAN interface on a bridged port we need to
840 * transition all the active 802.1Q bridge VLANs to use explicit
841 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
842 */
843 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
844 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
845 if (err) {
846 netdev_err(dev, "Failed to set to Virtual mode\n");
847 goto err_port_vp_mode_trans;
848 }
849 }
850
851 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
852 if (err) {
853 netdev_err(dev, "Failed to join vFID\n");
854 goto err_vport_vfid_join;
855 }
856
857 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
858 if (err) {
859 netdev_err(dev, "Failed to disable learning for VID=%d\n", vid);
860 goto err_port_vid_learning_set;
861 }
862
863 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
864 if (err) {
865 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
866 vid);
867 goto err_port_add_vid;
868 }
869
870 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
871 MLXSW_REG_SPMS_STATE_FORWARDING);
872 if (err) {
873 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
874 goto err_port_stp_state_set;
875 }
876
877 return 0;
878
879 err_port_stp_state_set:
880 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
881 err_port_add_vid:
882 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
883 err_port_vid_learning_set:
884 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
885 err_vport_vfid_join:
886 if (list_is_singular(&mlxsw_sp_port->vports_list))
887 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
888 err_port_vp_mode_trans:
889 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
890 return err;
891 }
892
893 int mlxsw_sp_port_kill_vid(struct net_device *dev,
894 __be16 __always_unused proto, u16 vid)
895 {
896 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
897 struct mlxsw_sp_port *mlxsw_sp_vport;
898 struct mlxsw_sp_fid *f;
899 int err;
900
901 /* VLAN 0 is removed from HW filter when device goes down, but
902 * it is reserved in our case, so simply return.
903 */
904 if (!vid)
905 return 0;
906
907 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
908 if (!mlxsw_sp_vport) {
909 netdev_warn(dev, "VID=%d does not exist\n", vid);
910 return 0;
911 }
912
913 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
914 MLXSW_REG_SPMS_STATE_DISCARDING);
915 if (err) {
916 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
917 return err;
918 }
919
920 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
921 if (err) {
922 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
923 vid);
924 return err;
925 }
926
927 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
928 if (err) {
929 netdev_err(dev, "Failed to enable learning for VID=%d\n", vid);
930 return err;
931 }
932
933 /* Drop FID reference. If this was the last reference the
934 * resources will be freed.
935 */
936 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
937 if (f && !WARN_ON(!f->leave))
938 f->leave(mlxsw_sp_vport);
939
940 /* When removing the last VLAN interface on a bridged port we need to
941 * transition all active 802.1Q bridge VLANs to use VID to FID
942 * mappings and set port's mode to VLAN mode.
943 */
944 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
945 err = mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
946 if (err) {
947 netdev_err(dev, "Failed to set to VLAN mode\n");
948 return err;
949 }
950 }
951
952 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
953
954 return 0;
955 }
956
957 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
958 size_t len)
959 {
960 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
961 u8 module = mlxsw_sp_port->mapping.module;
962 u8 width = mlxsw_sp_port->mapping.width;
963 u8 lane = mlxsw_sp_port->mapping.lane;
964 int err;
965
966 if (!mlxsw_sp_port->split)
967 err = snprintf(name, len, "p%d", module + 1);
968 else
969 err = snprintf(name, len, "p%ds%d", module + 1,
970 lane / width);
971
972 if (err >= len)
973 return -EINVAL;
974
975 return 0;
976 }
977
978 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
979 .ndo_open = mlxsw_sp_port_open,
980 .ndo_stop = mlxsw_sp_port_stop,
981 .ndo_start_xmit = mlxsw_sp_port_xmit,
982 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
983 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
984 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
985 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
986 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
987 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
988 .ndo_fdb_add = switchdev_port_fdb_add,
989 .ndo_fdb_del = switchdev_port_fdb_del,
990 .ndo_fdb_dump = switchdev_port_fdb_dump,
991 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
992 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
993 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
994 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
995 };
996
997 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
998 struct ethtool_drvinfo *drvinfo)
999 {
1000 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1001 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1002
1003 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1004 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1005 sizeof(drvinfo->version));
1006 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1007 "%d.%d.%d",
1008 mlxsw_sp->bus_info->fw_rev.major,
1009 mlxsw_sp->bus_info->fw_rev.minor,
1010 mlxsw_sp->bus_info->fw_rev.subminor);
1011 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1012 sizeof(drvinfo->bus_info));
1013 }
1014
1015 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1016 struct ethtool_pauseparam *pause)
1017 {
1018 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1019
1020 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1021 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1022 }
1023
1024 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1025 struct ethtool_pauseparam *pause)
1026 {
1027 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1028
1029 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1030 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1031 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1032
1033 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1034 pfcc_pl);
1035 }
1036
1037 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1038 struct ethtool_pauseparam *pause)
1039 {
1040 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1041 bool pause_en = pause->tx_pause || pause->rx_pause;
1042 int err;
1043
1044 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1045 netdev_err(dev, "PFC already enabled on port\n");
1046 return -EINVAL;
1047 }
1048
1049 if (pause->autoneg) {
1050 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1051 return -EINVAL;
1052 }
1053
1054 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1055 if (err) {
1056 netdev_err(dev, "Failed to configure port's headroom\n");
1057 return err;
1058 }
1059
1060 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1061 if (err) {
1062 netdev_err(dev, "Failed to set PAUSE parameters\n");
1063 goto err_port_pause_configure;
1064 }
1065
1066 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1067 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1068
1069 return 0;
1070
1071 err_port_pause_configure:
1072 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1073 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1074 return err;
1075 }
1076
1077 struct mlxsw_sp_port_hw_stats {
1078 char str[ETH_GSTRING_LEN];
1079 u64 (*getter)(char *payload);
1080 };
1081
1082 static const struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1083 {
1084 .str = "a_frames_transmitted_ok",
1085 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1086 },
1087 {
1088 .str = "a_frames_received_ok",
1089 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1090 },
1091 {
1092 .str = "a_frame_check_sequence_errors",
1093 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1094 },
1095 {
1096 .str = "a_alignment_errors",
1097 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1098 },
1099 {
1100 .str = "a_octets_transmitted_ok",
1101 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1102 },
1103 {
1104 .str = "a_octets_received_ok",
1105 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1106 },
1107 {
1108 .str = "a_multicast_frames_xmitted_ok",
1109 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1110 },
1111 {
1112 .str = "a_broadcast_frames_xmitted_ok",
1113 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1114 },
1115 {
1116 .str = "a_multicast_frames_received_ok",
1117 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1118 },
1119 {
1120 .str = "a_broadcast_frames_received_ok",
1121 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1122 },
1123 {
1124 .str = "a_in_range_length_errors",
1125 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1126 },
1127 {
1128 .str = "a_out_of_range_length_field",
1129 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1130 },
1131 {
1132 .str = "a_frame_too_long_errors",
1133 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1134 },
1135 {
1136 .str = "a_symbol_error_during_carrier",
1137 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1138 },
1139 {
1140 .str = "a_mac_control_frames_transmitted",
1141 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1142 },
1143 {
1144 .str = "a_mac_control_frames_received",
1145 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1146 },
1147 {
1148 .str = "a_unsupported_opcodes_received",
1149 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1150 },
1151 {
1152 .str = "a_pause_mac_ctrl_frames_received",
1153 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1154 },
1155 {
1156 .str = "a_pause_mac_ctrl_frames_xmitted",
1157 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1158 },
1159 };
1160
1161 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1162
1163 static void mlxsw_sp_port_get_strings(struct net_device *dev,
1164 u32 stringset, u8 *data)
1165 {
1166 u8 *p = data;
1167 int i;
1168
1169 switch (stringset) {
1170 case ETH_SS_STATS:
1171 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1172 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1173 ETH_GSTRING_LEN);
1174 p += ETH_GSTRING_LEN;
1175 }
1176 break;
1177 }
1178 }
1179
1180 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1181 enum ethtool_phys_id_state state)
1182 {
1183 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1184 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1185 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1186 bool active;
1187
1188 switch (state) {
1189 case ETHTOOL_ID_ACTIVE:
1190 active = true;
1191 break;
1192 case ETHTOOL_ID_INACTIVE:
1193 active = false;
1194 break;
1195 default:
1196 return -EOPNOTSUPP;
1197 }
1198
1199 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1201 }
1202
1203 static void mlxsw_sp_port_get_stats(struct net_device *dev,
1204 struct ethtool_stats *stats, u64 *data)
1205 {
1206 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1207 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1208 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1209 int i;
1210 int err;
1211
1212 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port,
1213 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
1214 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1215 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++)
1216 data[i] = !err ? mlxsw_sp_port_hw_stats[i].getter(ppcnt_pl) : 0;
1217 }
1218
1219 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1220 {
1221 switch (sset) {
1222 case ETH_SS_STATS:
1223 return MLXSW_SP_PORT_HW_STATS_LEN;
1224 default:
1225 return -EOPNOTSUPP;
1226 }
1227 }
1228
1229 struct mlxsw_sp_port_link_mode {
1230 u32 mask;
1231 u32 supported;
1232 u32 advertised;
1233 u32 speed;
1234 };
1235
1236 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1237 {
1238 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1239 .supported = SUPPORTED_100baseT_Full,
1240 .advertised = ADVERTISED_100baseT_Full,
1241 .speed = 100,
1242 },
1243 {
1244 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
1245 .speed = 100,
1246 },
1247 {
1248 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1249 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1250 .supported = SUPPORTED_1000baseKX_Full,
1251 .advertised = ADVERTISED_1000baseKX_Full,
1252 .speed = 1000,
1253 },
1254 {
1255 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1256 .supported = SUPPORTED_10000baseT_Full,
1257 .advertised = ADVERTISED_10000baseT_Full,
1258 .speed = 10000,
1259 },
1260 {
1261 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1262 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1263 .supported = SUPPORTED_10000baseKX4_Full,
1264 .advertised = ADVERTISED_10000baseKX4_Full,
1265 .speed = 10000,
1266 },
1267 {
1268 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1269 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1270 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1271 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1272 .supported = SUPPORTED_10000baseKR_Full,
1273 .advertised = ADVERTISED_10000baseKR_Full,
1274 .speed = 10000,
1275 },
1276 {
1277 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1278 .supported = SUPPORTED_20000baseKR2_Full,
1279 .advertised = ADVERTISED_20000baseKR2_Full,
1280 .speed = 20000,
1281 },
1282 {
1283 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1284 .supported = SUPPORTED_40000baseCR4_Full,
1285 .advertised = ADVERTISED_40000baseCR4_Full,
1286 .speed = 40000,
1287 },
1288 {
1289 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1290 .supported = SUPPORTED_40000baseKR4_Full,
1291 .advertised = ADVERTISED_40000baseKR4_Full,
1292 .speed = 40000,
1293 },
1294 {
1295 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1296 .supported = SUPPORTED_40000baseSR4_Full,
1297 .advertised = ADVERTISED_40000baseSR4_Full,
1298 .speed = 40000,
1299 },
1300 {
1301 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1302 .supported = SUPPORTED_40000baseLR4_Full,
1303 .advertised = ADVERTISED_40000baseLR4_Full,
1304 .speed = 40000,
1305 },
1306 {
1307 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
1308 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
1309 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1310 .speed = 25000,
1311 },
1312 {
1313 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
1314 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
1315 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1316 .speed = 50000,
1317 },
1318 {
1319 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1320 .supported = SUPPORTED_56000baseKR4_Full,
1321 .advertised = ADVERTISED_56000baseKR4_Full,
1322 .speed = 56000,
1323 },
1324 {
1325 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
1326 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1327 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1328 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1329 .speed = 100000,
1330 },
1331 };
1332
1333 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1334
1335 static u32 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto)
1336 {
1337 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1338 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1339 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1340 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1341 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1342 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1343 return SUPPORTED_FIBRE;
1344
1345 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1346 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1347 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1348 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1349 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1350 return SUPPORTED_Backplane;
1351 return 0;
1352 }
1353
1354 static u32 mlxsw_sp_from_ptys_supported_link(u32 ptys_eth_proto)
1355 {
1356 u32 modes = 0;
1357 int i;
1358
1359 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1360 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1361 modes |= mlxsw_sp_port_link_mode[i].supported;
1362 }
1363 return modes;
1364 }
1365
1366 static u32 mlxsw_sp_from_ptys_advert_link(u32 ptys_eth_proto)
1367 {
1368 u32 modes = 0;
1369 int i;
1370
1371 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1372 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1373 modes |= mlxsw_sp_port_link_mode[i].advertised;
1374 }
1375 return modes;
1376 }
1377
1378 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1379 struct ethtool_cmd *cmd)
1380 {
1381 u32 speed = SPEED_UNKNOWN;
1382 u8 duplex = DUPLEX_UNKNOWN;
1383 int i;
1384
1385 if (!carrier_ok)
1386 goto out;
1387
1388 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1389 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1390 speed = mlxsw_sp_port_link_mode[i].speed;
1391 duplex = DUPLEX_FULL;
1392 break;
1393 }
1394 }
1395 out:
1396 ethtool_cmd_speed_set(cmd, speed);
1397 cmd->duplex = duplex;
1398 }
1399
1400 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1401 {
1402 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1403 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1404 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1405 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1406 return PORT_FIBRE;
1407
1408 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1409 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1410 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1411 return PORT_DA;
1412
1413 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1414 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1415 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1416 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1417 return PORT_NONE;
1418
1419 return PORT_OTHER;
1420 }
1421
1422 static int mlxsw_sp_port_get_settings(struct net_device *dev,
1423 struct ethtool_cmd *cmd)
1424 {
1425 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1426 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1427 char ptys_pl[MLXSW_REG_PTYS_LEN];
1428 u32 eth_proto_cap;
1429 u32 eth_proto_admin;
1430 u32 eth_proto_oper;
1431 int err;
1432
1433 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1434 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1435 if (err) {
1436 netdev_err(dev, "Failed to get proto");
1437 return err;
1438 }
1439 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
1440 &eth_proto_admin, &eth_proto_oper);
1441
1442 cmd->supported = mlxsw_sp_from_ptys_supported_port(eth_proto_cap) |
1443 mlxsw_sp_from_ptys_supported_link(eth_proto_cap) |
1444 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1445 cmd->advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_admin);
1446 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev),
1447 eth_proto_oper, cmd);
1448
1449 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1450 cmd->port = mlxsw_sp_port_connector_port(eth_proto_oper);
1451 cmd->lp_advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_oper);
1452
1453 cmd->transceiver = XCVR_INTERNAL;
1454 return 0;
1455 }
1456
1457 static u32 mlxsw_sp_to_ptys_advert_link(u32 advertising)
1458 {
1459 u32 ptys_proto = 0;
1460 int i;
1461
1462 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1463 if (advertising & mlxsw_sp_port_link_mode[i].advertised)
1464 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1465 }
1466 return ptys_proto;
1467 }
1468
1469 static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1470 {
1471 u32 ptys_proto = 0;
1472 int i;
1473
1474 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1475 if (speed == mlxsw_sp_port_link_mode[i].speed)
1476 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1477 }
1478 return ptys_proto;
1479 }
1480
1481 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1482 {
1483 u32 ptys_proto = 0;
1484 int i;
1485
1486 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1487 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1488 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1489 }
1490 return ptys_proto;
1491 }
1492
1493 static int mlxsw_sp_port_set_settings(struct net_device *dev,
1494 struct ethtool_cmd *cmd)
1495 {
1496 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1497 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1498 char ptys_pl[MLXSW_REG_PTYS_LEN];
1499 u32 speed;
1500 u32 eth_proto_new;
1501 u32 eth_proto_cap;
1502 u32 eth_proto_admin;
1503 bool is_up;
1504 int err;
1505
1506 speed = ethtool_cmd_speed(cmd);
1507
1508 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
1509 mlxsw_sp_to_ptys_advert_link(cmd->advertising) :
1510 mlxsw_sp_to_ptys_speed(speed);
1511
1512 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1513 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1514 if (err) {
1515 netdev_err(dev, "Failed to get proto");
1516 return err;
1517 }
1518 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
1519
1520 eth_proto_new = eth_proto_new & eth_proto_cap;
1521 if (!eth_proto_new) {
1522 netdev_err(dev, "Not supported proto admin requested");
1523 return -EINVAL;
1524 }
1525 if (eth_proto_new == eth_proto_admin)
1526 return 0;
1527
1528 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
1529 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1530 if (err) {
1531 netdev_err(dev, "Failed to set proto admin");
1532 return err;
1533 }
1534
1535 err = mlxsw_sp_port_oper_status_get(mlxsw_sp_port, &is_up);
1536 if (err) {
1537 netdev_err(dev, "Failed to get oper status");
1538 return err;
1539 }
1540 if (!is_up)
1541 return 0;
1542
1543 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1544 if (err) {
1545 netdev_err(dev, "Failed to set admin status");
1546 return err;
1547 }
1548
1549 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1550 if (err) {
1551 netdev_err(dev, "Failed to set admin status");
1552 return err;
1553 }
1554
1555 return 0;
1556 }
1557
1558 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1559 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1560 .get_link = ethtool_op_get_link,
1561 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
1562 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
1563 .get_strings = mlxsw_sp_port_get_strings,
1564 .set_phys_id = mlxsw_sp_port_set_phys_id,
1565 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1566 .get_sset_count = mlxsw_sp_port_get_sset_count,
1567 .get_settings = mlxsw_sp_port_get_settings,
1568 .set_settings = mlxsw_sp_port_set_settings,
1569 };
1570
1571 static int
1572 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
1573 {
1574 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1575 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
1576 char ptys_pl[MLXSW_REG_PTYS_LEN];
1577 u32 eth_proto_admin;
1578
1579 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
1580 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
1581 eth_proto_admin);
1582 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1583 }
1584
1585 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1586 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1587 bool dwrr, u8 dwrr_weight)
1588 {
1589 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1590 char qeec_pl[MLXSW_REG_QEEC_LEN];
1591
1592 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1593 next_index);
1594 mlxsw_reg_qeec_de_set(qeec_pl, true);
1595 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1596 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1598 }
1599
1600 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1601 enum mlxsw_reg_qeec_hr hr, u8 index,
1602 u8 next_index, u32 maxrate)
1603 {
1604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1605 char qeec_pl[MLXSW_REG_QEEC_LEN];
1606
1607 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1608 next_index);
1609 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1610 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1611 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1612 }
1613
1614 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1615 u8 switch_prio, u8 tclass)
1616 {
1617 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1618 char qtct_pl[MLXSW_REG_QTCT_LEN];
1619
1620 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1621 tclass);
1622 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1623 }
1624
1625 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1626 {
1627 int err, i;
1628
1629 /* Setup the elements hierarcy, so that each TC is linked to
1630 * one subgroup, which are all member in the same group.
1631 */
1632 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1633 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
1634 0);
1635 if (err)
1636 return err;
1637 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1638 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1639 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
1640 0, false, 0);
1641 if (err)
1642 return err;
1643 }
1644 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1645 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1646 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
1647 false, 0);
1648 if (err)
1649 return err;
1650 }
1651
1652 /* Make sure the max shaper is disabled in all hierarcies that
1653 * support it.
1654 */
1655 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1656 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
1657 MLXSW_REG_QEEC_MAS_DIS);
1658 if (err)
1659 return err;
1660 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1661 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1662 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1663 i, 0,
1664 MLXSW_REG_QEEC_MAS_DIS);
1665 if (err)
1666 return err;
1667 }
1668 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1669 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1670 MLXSW_REG_QEEC_HIERARCY_TC,
1671 i, i,
1672 MLXSW_REG_QEEC_MAS_DIS);
1673 if (err)
1674 return err;
1675 }
1676
1677 /* Map all priorities to traffic class 0. */
1678 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1679 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1680 if (err)
1681 return err;
1682 }
1683
1684 return 0;
1685 }
1686
1687 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
1688 bool split, u8 module, u8 width, u8 lane)
1689 {
1690 struct mlxsw_sp_port *mlxsw_sp_port;
1691 struct net_device *dev;
1692 size_t bytes;
1693 int err;
1694
1695 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1696 if (!dev)
1697 return -ENOMEM;
1698 mlxsw_sp_port = netdev_priv(dev);
1699 mlxsw_sp_port->dev = dev;
1700 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1701 mlxsw_sp_port->local_port = local_port;
1702 mlxsw_sp_port->split = split;
1703 mlxsw_sp_port->mapping.module = module;
1704 mlxsw_sp_port->mapping.width = width;
1705 mlxsw_sp_port->mapping.lane = lane;
1706 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
1707 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
1708 if (!mlxsw_sp_port->active_vlans) {
1709 err = -ENOMEM;
1710 goto err_port_active_vlans_alloc;
1711 }
1712 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
1713 if (!mlxsw_sp_port->untagged_vlans) {
1714 err = -ENOMEM;
1715 goto err_port_untagged_vlans_alloc;
1716 }
1717 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
1718
1719 mlxsw_sp_port->pcpu_stats =
1720 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1721 if (!mlxsw_sp_port->pcpu_stats) {
1722 err = -ENOMEM;
1723 goto err_alloc_stats;
1724 }
1725
1726 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1727 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1728
1729 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1730 if (err) {
1731 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1732 mlxsw_sp_port->local_port);
1733 goto err_dev_addr_init;
1734 }
1735
1736 netif_carrier_off(dev);
1737
1738 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1739 NETIF_F_HW_VLAN_CTAG_FILTER;
1740
1741 /* Each packet needs to have a Tx header (metadata) on top all other
1742 * headers.
1743 */
1744 dev->hard_header_len += MLXSW_TXHDR_LEN;
1745
1746 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1747 if (err) {
1748 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1749 mlxsw_sp_port->local_port);
1750 goto err_port_system_port_mapping_set;
1751 }
1752
1753 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1754 if (err) {
1755 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1756 mlxsw_sp_port->local_port);
1757 goto err_port_swid_set;
1758 }
1759
1760 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
1761 if (err) {
1762 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1763 mlxsw_sp_port->local_port);
1764 goto err_port_speed_by_width_set;
1765 }
1766
1767 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1768 if (err) {
1769 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1770 mlxsw_sp_port->local_port);
1771 goto err_port_mtu_set;
1772 }
1773
1774 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1775 if (err)
1776 goto err_port_admin_status_set;
1777
1778 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1779 if (err) {
1780 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1781 mlxsw_sp_port->local_port);
1782 goto err_port_buffers_init;
1783 }
1784
1785 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1786 if (err) {
1787 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1788 mlxsw_sp_port->local_port);
1789 goto err_port_ets_init;
1790 }
1791
1792 /* ETS and buffers must be initialized before DCB. */
1793 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1794 if (err) {
1795 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1796 mlxsw_sp_port->local_port);
1797 goto err_port_dcb_init;
1798 }
1799
1800 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
1801 err = register_netdev(dev);
1802 if (err) {
1803 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1804 mlxsw_sp_port->local_port);
1805 goto err_register_netdev;
1806 }
1807
1808 err = mlxsw_core_port_init(mlxsw_sp->core, &mlxsw_sp_port->core_port,
1809 mlxsw_sp_port->local_port, dev,
1810 mlxsw_sp_port->split, module);
1811 if (err) {
1812 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1813 mlxsw_sp_port->local_port);
1814 goto err_core_port_init;
1815 }
1816
1817 err = mlxsw_sp_port_vlan_init(mlxsw_sp_port);
1818 if (err)
1819 goto err_port_vlan_init;
1820
1821 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1822 return 0;
1823
1824 err_port_vlan_init:
1825 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
1826 err_core_port_init:
1827 unregister_netdev(dev);
1828 err_register_netdev:
1829 err_port_dcb_init:
1830 err_port_ets_init:
1831 err_port_buffers_init:
1832 err_port_admin_status_set:
1833 err_port_mtu_set:
1834 err_port_speed_by_width_set:
1835 err_port_swid_set:
1836 err_port_system_port_mapping_set:
1837 err_dev_addr_init:
1838 free_percpu(mlxsw_sp_port->pcpu_stats);
1839 err_alloc_stats:
1840 kfree(mlxsw_sp_port->untagged_vlans);
1841 err_port_untagged_vlans_alloc:
1842 kfree(mlxsw_sp_port->active_vlans);
1843 err_port_active_vlans_alloc:
1844 free_netdev(dev);
1845 return err;
1846 }
1847
1848 static void mlxsw_sp_port_vports_fini(struct mlxsw_sp_port *mlxsw_sp_port)
1849 {
1850 struct net_device *dev = mlxsw_sp_port->dev;
1851 struct mlxsw_sp_port *mlxsw_sp_vport, *tmp;
1852
1853 list_for_each_entry_safe(mlxsw_sp_vport, tmp,
1854 &mlxsw_sp_port->vports_list, vport.list) {
1855 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
1856
1857 /* vPorts created for VLAN devices should already be gone
1858 * by now, since we unregistered the port netdev.
1859 */
1860 WARN_ON(is_vlan_dev(mlxsw_sp_vport->dev));
1861 mlxsw_sp_port_kill_vid(dev, 0, vid);
1862 }
1863 }
1864
1865 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1866 {
1867 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1868
1869 if (!mlxsw_sp_port)
1870 return;
1871 mlxsw_sp->ports[local_port] = NULL;
1872 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
1873 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
1874 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
1875 mlxsw_sp_port_vports_fini(mlxsw_sp_port);
1876 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
1877 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1878 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
1879 free_percpu(mlxsw_sp_port->pcpu_stats);
1880 kfree(mlxsw_sp_port->untagged_vlans);
1881 kfree(mlxsw_sp_port->active_vlans);
1882 free_netdev(mlxsw_sp_port->dev);
1883 }
1884
1885 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1886 {
1887 int i;
1888
1889 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1890 mlxsw_sp_port_remove(mlxsw_sp, i);
1891 kfree(mlxsw_sp->ports);
1892 }
1893
1894 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1895 {
1896 u8 module, width, lane;
1897 size_t alloc_size;
1898 int i;
1899 int err;
1900
1901 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
1902 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1903 if (!mlxsw_sp->ports)
1904 return -ENOMEM;
1905
1906 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
1907 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
1908 &width, &lane);
1909 if (err)
1910 goto err_port_module_info_get;
1911 if (!width)
1912 continue;
1913 mlxsw_sp->port_to_module[i] = module;
1914 err = mlxsw_sp_port_create(mlxsw_sp, i, false, module, width,
1915 lane);
1916 if (err)
1917 goto err_port_create;
1918 }
1919 return 0;
1920
1921 err_port_create:
1922 err_port_module_info_get:
1923 for (i--; i >= 1; i--)
1924 mlxsw_sp_port_remove(mlxsw_sp, i);
1925 kfree(mlxsw_sp->ports);
1926 return err;
1927 }
1928
1929 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
1930 {
1931 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
1932
1933 return local_port - offset;
1934 }
1935
1936 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
1937 u8 module, unsigned int count)
1938 {
1939 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
1940 int err, i;
1941
1942 for (i = 0; i < count; i++) {
1943 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
1944 width, i * width);
1945 if (err)
1946 goto err_port_module_map;
1947 }
1948
1949 for (i = 0; i < count; i++) {
1950 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
1951 if (err)
1952 goto err_port_swid_set;
1953 }
1954
1955 for (i = 0; i < count; i++) {
1956 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
1957 module, width, i * width);
1958 if (err)
1959 goto err_port_create;
1960 }
1961
1962 return 0;
1963
1964 err_port_create:
1965 for (i--; i >= 0; i--)
1966 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1967 i = count;
1968 err_port_swid_set:
1969 for (i--; i >= 0; i--)
1970 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
1971 MLXSW_PORT_SWID_DISABLED_PORT);
1972 i = count;
1973 err_port_module_map:
1974 for (i--; i >= 0; i--)
1975 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
1976 return err;
1977 }
1978
1979 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
1980 u8 base_port, unsigned int count)
1981 {
1982 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
1983 int i;
1984
1985 /* Split by four means we need to re-create two ports, otherwise
1986 * only one.
1987 */
1988 count = count / 2;
1989
1990 for (i = 0; i < count; i++) {
1991 local_port = base_port + i * 2;
1992 module = mlxsw_sp->port_to_module[local_port];
1993
1994 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
1995 0);
1996 }
1997
1998 for (i = 0; i < count; i++)
1999 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
2000
2001 for (i = 0; i < count; i++) {
2002 local_port = base_port + i * 2;
2003 module = mlxsw_sp->port_to_module[local_port];
2004
2005 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
2006 width, 0);
2007 }
2008 }
2009
2010 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
2011 unsigned int count)
2012 {
2013 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2014 struct mlxsw_sp_port *mlxsw_sp_port;
2015 u8 module, cur_width, base_port;
2016 int i;
2017 int err;
2018
2019 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2020 if (!mlxsw_sp_port) {
2021 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2022 local_port);
2023 return -EINVAL;
2024 }
2025
2026 module = mlxsw_sp_port->mapping.module;
2027 cur_width = mlxsw_sp_port->mapping.width;
2028
2029 if (count != 2 && count != 4) {
2030 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2031 return -EINVAL;
2032 }
2033
2034 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2035 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2036 return -EINVAL;
2037 }
2038
2039 /* Make sure we have enough slave (even) ports for the split. */
2040 if (count == 2) {
2041 base_port = local_port;
2042 if (mlxsw_sp->ports[base_port + 1]) {
2043 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2044 return -EINVAL;
2045 }
2046 } else {
2047 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2048 if (mlxsw_sp->ports[base_port + 1] ||
2049 mlxsw_sp->ports[base_port + 3]) {
2050 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2051 return -EINVAL;
2052 }
2053 }
2054
2055 for (i = 0; i < count; i++)
2056 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2057
2058 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2059 if (err) {
2060 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2061 goto err_port_split_create;
2062 }
2063
2064 return 0;
2065
2066 err_port_split_create:
2067 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
2068 return err;
2069 }
2070
2071 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
2072 {
2073 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2074 struct mlxsw_sp_port *mlxsw_sp_port;
2075 u8 cur_width, base_port;
2076 unsigned int count;
2077 int i;
2078
2079 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2080 if (!mlxsw_sp_port) {
2081 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2082 local_port);
2083 return -EINVAL;
2084 }
2085
2086 if (!mlxsw_sp_port->split) {
2087 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2088 return -EINVAL;
2089 }
2090
2091 cur_width = mlxsw_sp_port->mapping.width;
2092 count = cur_width == 1 ? 4 : 2;
2093
2094 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2095
2096 /* Determine which ports to remove. */
2097 if (count == 2 && local_port >= base_port + 2)
2098 base_port = base_port + 2;
2099
2100 for (i = 0; i < count; i++)
2101 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2102
2103 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
2104
2105 return 0;
2106 }
2107
2108 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2109 char *pude_pl, void *priv)
2110 {
2111 struct mlxsw_sp *mlxsw_sp = priv;
2112 struct mlxsw_sp_port *mlxsw_sp_port;
2113 enum mlxsw_reg_pude_oper_status status;
2114 u8 local_port;
2115
2116 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2117 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2118 if (!mlxsw_sp_port) {
2119 dev_warn(mlxsw_sp->bus_info->dev, "Port %d: Link event received for non-existent port\n",
2120 local_port);
2121 return;
2122 }
2123
2124 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2125 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2126 netdev_info(mlxsw_sp_port->dev, "link up\n");
2127 netif_carrier_on(mlxsw_sp_port->dev);
2128 } else {
2129 netdev_info(mlxsw_sp_port->dev, "link down\n");
2130 netif_carrier_off(mlxsw_sp_port->dev);
2131 }
2132 }
2133
2134 static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2135 .func = mlxsw_sp_pude_event_func,
2136 .trap_id = MLXSW_TRAP_ID_PUDE,
2137 };
2138
2139 static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2140 enum mlxsw_event_trap_id trap_id)
2141 {
2142 struct mlxsw_event_listener *el;
2143 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2144 int err;
2145
2146 switch (trap_id) {
2147 case MLXSW_TRAP_ID_PUDE:
2148 el = &mlxsw_sp_pude_event;
2149 break;
2150 }
2151 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2152 if (err)
2153 return err;
2154
2155 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2156 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2157 if (err)
2158 goto err_event_trap_set;
2159
2160 return 0;
2161
2162 err_event_trap_set:
2163 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2164 return err;
2165 }
2166
2167 static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2168 enum mlxsw_event_trap_id trap_id)
2169 {
2170 struct mlxsw_event_listener *el;
2171
2172 switch (trap_id) {
2173 case MLXSW_TRAP_ID_PUDE:
2174 el = &mlxsw_sp_pude_event;
2175 break;
2176 }
2177 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2178 }
2179
2180 static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2181 void *priv)
2182 {
2183 struct mlxsw_sp *mlxsw_sp = priv;
2184 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2185 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2186
2187 if (unlikely(!mlxsw_sp_port)) {
2188 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2189 local_port);
2190 return;
2191 }
2192
2193 skb->dev = mlxsw_sp_port->dev;
2194
2195 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2196 u64_stats_update_begin(&pcpu_stats->syncp);
2197 pcpu_stats->rx_packets++;
2198 pcpu_stats->rx_bytes += skb->len;
2199 u64_stats_update_end(&pcpu_stats->syncp);
2200
2201 skb->protocol = eth_type_trans(skb, skb->dev);
2202 netif_receive_skb(skb);
2203 }
2204
2205 static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
2206 {
2207 .func = mlxsw_sp_rx_listener_func,
2208 .local_port = MLXSW_PORT_DONT_CARE,
2209 .trap_id = MLXSW_TRAP_ID_FDB_MC,
2210 },
2211 /* Traps for specific L2 packet types, not trapped as FDB MC */
2212 {
2213 .func = mlxsw_sp_rx_listener_func,
2214 .local_port = MLXSW_PORT_DONT_CARE,
2215 .trap_id = MLXSW_TRAP_ID_STP,
2216 },
2217 {
2218 .func = mlxsw_sp_rx_listener_func,
2219 .local_port = MLXSW_PORT_DONT_CARE,
2220 .trap_id = MLXSW_TRAP_ID_LACP,
2221 },
2222 {
2223 .func = mlxsw_sp_rx_listener_func,
2224 .local_port = MLXSW_PORT_DONT_CARE,
2225 .trap_id = MLXSW_TRAP_ID_EAPOL,
2226 },
2227 {
2228 .func = mlxsw_sp_rx_listener_func,
2229 .local_port = MLXSW_PORT_DONT_CARE,
2230 .trap_id = MLXSW_TRAP_ID_LLDP,
2231 },
2232 {
2233 .func = mlxsw_sp_rx_listener_func,
2234 .local_port = MLXSW_PORT_DONT_CARE,
2235 .trap_id = MLXSW_TRAP_ID_MMRP,
2236 },
2237 {
2238 .func = mlxsw_sp_rx_listener_func,
2239 .local_port = MLXSW_PORT_DONT_CARE,
2240 .trap_id = MLXSW_TRAP_ID_MVRP,
2241 },
2242 {
2243 .func = mlxsw_sp_rx_listener_func,
2244 .local_port = MLXSW_PORT_DONT_CARE,
2245 .trap_id = MLXSW_TRAP_ID_RPVST,
2246 },
2247 {
2248 .func = mlxsw_sp_rx_listener_func,
2249 .local_port = MLXSW_PORT_DONT_CARE,
2250 .trap_id = MLXSW_TRAP_ID_DHCP,
2251 },
2252 {
2253 .func = mlxsw_sp_rx_listener_func,
2254 .local_port = MLXSW_PORT_DONT_CARE,
2255 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
2256 },
2257 {
2258 .func = mlxsw_sp_rx_listener_func,
2259 .local_port = MLXSW_PORT_DONT_CARE,
2260 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
2261 },
2262 {
2263 .func = mlxsw_sp_rx_listener_func,
2264 .local_port = MLXSW_PORT_DONT_CARE,
2265 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
2266 },
2267 {
2268 .func = mlxsw_sp_rx_listener_func,
2269 .local_port = MLXSW_PORT_DONT_CARE,
2270 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
2271 },
2272 {
2273 .func = mlxsw_sp_rx_listener_func,
2274 .local_port = MLXSW_PORT_DONT_CARE,
2275 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
2276 },
2277 };
2278
2279 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2280 {
2281 char htgt_pl[MLXSW_REG_HTGT_LEN];
2282 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2283 int i;
2284 int err;
2285
2286 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2287 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2288 if (err)
2289 return err;
2290
2291 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2292 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2293 if (err)
2294 return err;
2295
2296 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2297 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2298 &mlxsw_sp_rx_listener[i],
2299 mlxsw_sp);
2300 if (err)
2301 goto err_rx_listener_register;
2302
2303 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2304 mlxsw_sp_rx_listener[i].trap_id);
2305 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2306 if (err)
2307 goto err_rx_trap_set;
2308 }
2309 return 0;
2310
2311 err_rx_trap_set:
2312 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2313 &mlxsw_sp_rx_listener[i],
2314 mlxsw_sp);
2315 err_rx_listener_register:
2316 for (i--; i >= 0; i--) {
2317 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2318 mlxsw_sp_rx_listener[i].trap_id);
2319 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2320
2321 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2322 &mlxsw_sp_rx_listener[i],
2323 mlxsw_sp);
2324 }
2325 return err;
2326 }
2327
2328 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2329 {
2330 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2331 int i;
2332
2333 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2334 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2335 mlxsw_sp_rx_listener[i].trap_id);
2336 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2337
2338 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2339 &mlxsw_sp_rx_listener[i],
2340 mlxsw_sp);
2341 }
2342 }
2343
2344 static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2345 enum mlxsw_reg_sfgc_type type,
2346 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2347 {
2348 enum mlxsw_flood_table_type table_type;
2349 enum mlxsw_sp_flood_table flood_table;
2350 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2351
2352 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
2353 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
2354 else
2355 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
2356
2357 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2358 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2359 else
2360 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
2361
2362 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2363 flood_table);
2364 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2365 }
2366
2367 static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2368 {
2369 int type, err;
2370
2371 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2372 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2373 continue;
2374
2375 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2376 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2377 if (err)
2378 return err;
2379
2380 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2381 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2382 if (err)
2383 return err;
2384 }
2385
2386 return 0;
2387 }
2388
2389 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2390 {
2391 char slcr_pl[MLXSW_REG_SLCR_LEN];
2392
2393 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2394 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2395 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2396 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2397 MLXSW_REG_SLCR_LAG_HASH_SIP |
2398 MLXSW_REG_SLCR_LAG_HASH_DIP |
2399 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2400 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2401 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2402 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2403 }
2404
2405 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
2406 const struct mlxsw_bus_info *mlxsw_bus_info)
2407 {
2408 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2409 int err;
2410
2411 mlxsw_sp->core = mlxsw_core;
2412 mlxsw_sp->bus_info = mlxsw_bus_info;
2413 INIT_LIST_HEAD(&mlxsw_sp->fids);
2414 INIT_LIST_HEAD(&mlxsw_sp->port_vfids.list);
2415 INIT_LIST_HEAD(&mlxsw_sp->br_vfids.list);
2416 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
2417
2418 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2419 if (err) {
2420 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2421 return err;
2422 }
2423
2424 err = mlxsw_sp_ports_create(mlxsw_sp);
2425 if (err) {
2426 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
2427 return err;
2428 }
2429
2430 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2431 if (err) {
2432 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
2433 goto err_event_register;
2434 }
2435
2436 err = mlxsw_sp_traps_init(mlxsw_sp);
2437 if (err) {
2438 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2439 goto err_rx_listener_register;
2440 }
2441
2442 err = mlxsw_sp_flood_init(mlxsw_sp);
2443 if (err) {
2444 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2445 goto err_flood_init;
2446 }
2447
2448 err = mlxsw_sp_buffers_init(mlxsw_sp);
2449 if (err) {
2450 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2451 goto err_buffers_init;
2452 }
2453
2454 err = mlxsw_sp_lag_init(mlxsw_sp);
2455 if (err) {
2456 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2457 goto err_lag_init;
2458 }
2459
2460 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2461 if (err) {
2462 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2463 goto err_switchdev_init;
2464 }
2465
2466 return 0;
2467
2468 err_switchdev_init:
2469 err_lag_init:
2470 mlxsw_sp_buffers_fini(mlxsw_sp);
2471 err_buffers_init:
2472 err_flood_init:
2473 mlxsw_sp_traps_fini(mlxsw_sp);
2474 err_rx_listener_register:
2475 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2476 err_event_register:
2477 mlxsw_sp_ports_remove(mlxsw_sp);
2478 return err;
2479 }
2480
2481 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
2482 {
2483 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2484
2485 mlxsw_sp_switchdev_fini(mlxsw_sp);
2486 mlxsw_sp_buffers_fini(mlxsw_sp);
2487 mlxsw_sp_traps_fini(mlxsw_sp);
2488 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2489 mlxsw_sp_ports_remove(mlxsw_sp);
2490 WARN_ON(!list_empty(&mlxsw_sp->fids));
2491 }
2492
2493 static struct mlxsw_config_profile mlxsw_sp_config_profile = {
2494 .used_max_vepa_channels = 1,
2495 .max_vepa_channels = 0,
2496 .used_max_lag = 1,
2497 .max_lag = MLXSW_SP_LAG_MAX,
2498 .used_max_port_per_lag = 1,
2499 .max_port_per_lag = MLXSW_SP_PORT_PER_LAG_MAX,
2500 .used_max_mid = 1,
2501 .max_mid = MLXSW_SP_MID_MAX,
2502 .used_max_pgt = 1,
2503 .max_pgt = 0,
2504 .used_max_system_port = 1,
2505 .max_system_port = 64,
2506 .used_max_vlan_groups = 1,
2507 .max_vlan_groups = 127,
2508 .used_max_regions = 1,
2509 .max_regions = 400,
2510 .used_flood_tables = 1,
2511 .used_flood_mode = 1,
2512 .flood_mode = 3,
2513 .max_fid_offset_flood_tables = 2,
2514 .fid_offset_flood_table_size = VLAN_N_VID - 1,
2515 .max_fid_flood_tables = 2,
2516 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
2517 .used_max_ib_mc = 1,
2518 .max_ib_mc = 0,
2519 .used_max_pkey = 1,
2520 .max_pkey = 0,
2521 .swid_config = {
2522 {
2523 .used_type = 1,
2524 .type = MLXSW_PORT_SWID_TYPE_ETH,
2525 }
2526 },
2527 };
2528
2529 static struct mlxsw_driver mlxsw_sp_driver = {
2530 .kind = MLXSW_DEVICE_KIND_SPECTRUM,
2531 .owner = THIS_MODULE,
2532 .priv_size = sizeof(struct mlxsw_sp),
2533 .init = mlxsw_sp_init,
2534 .fini = mlxsw_sp_fini,
2535 .port_split = mlxsw_sp_port_split,
2536 .port_unsplit = mlxsw_sp_port_unsplit,
2537 .sb_pool_get = mlxsw_sp_sb_pool_get,
2538 .sb_pool_set = mlxsw_sp_sb_pool_set,
2539 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
2540 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
2541 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
2542 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
2543 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
2544 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
2545 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
2546 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
2547 .txhdr_construct = mlxsw_sp_txhdr_construct,
2548 .txhdr_len = MLXSW_TXHDR_LEN,
2549 .profile = &mlxsw_sp_config_profile,
2550 };
2551
2552 static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
2553 u16 fid)
2554 {
2555 if (mlxsw_sp_fid_is_vfid(fid))
2556 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
2557 else
2558 return test_bit(fid, lag_port->active_vlans);
2559 }
2560
2561 static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
2562 u16 fid)
2563 {
2564 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2565 u8 local_port = mlxsw_sp_port->local_port;
2566 u16 lag_id = mlxsw_sp_port->lag_id;
2567 int i, count = 0;
2568
2569 if (!mlxsw_sp_port->lagged)
2570 return true;
2571
2572 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2573 struct mlxsw_sp_port *lag_port;
2574
2575 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
2576 if (!lag_port || lag_port->local_port == local_port)
2577 continue;
2578 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
2579 count++;
2580 }
2581
2582 return !count;
2583 }
2584
2585 static int
2586 mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2587 u16 fid)
2588 {
2589 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2590 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2591
2592 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
2593 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2594 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
2595 mlxsw_sp_port->local_port);
2596
2597 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
2598 mlxsw_sp_port->local_port, fid);
2599
2600 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2601 }
2602
2603 static int
2604 mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2605 u16 fid)
2606 {
2607 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2608 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2609
2610 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
2611 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2612 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2613
2614 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
2615 mlxsw_sp_port->lag_id, fid);
2616
2617 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2618 }
2619
2620 int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
2621 {
2622 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
2623 return 0;
2624
2625 if (mlxsw_sp_port->lagged)
2626 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
2627 fid);
2628 else
2629 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
2630 }
2631
2632 static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
2633 {
2634 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
2635 }
2636
2637 static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
2638 struct net_device *br_dev)
2639 {
2640 return !mlxsw_sp->master_bridge.dev ||
2641 mlxsw_sp->master_bridge.dev == br_dev;
2642 }
2643
2644 static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
2645 struct net_device *br_dev)
2646 {
2647 mlxsw_sp->master_bridge.dev = br_dev;
2648 mlxsw_sp->master_bridge.ref_count++;
2649 }
2650
2651 static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
2652 {
2653 if (--mlxsw_sp->master_bridge.ref_count == 0)
2654 mlxsw_sp->master_bridge.dev = NULL;
2655 }
2656
2657 static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
2658 struct net_device *br_dev)
2659 {
2660 struct net_device *dev = mlxsw_sp_port->dev;
2661 int err;
2662
2663 /* When port is not bridged untagged packets are tagged with
2664 * PVID=VID=1, thereby creating an implicit VLAN interface in
2665 * the device. Remove it and let bridge code take care of its
2666 * own VLANs.
2667 */
2668 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
2669 if (err)
2670 return err;
2671
2672 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
2673
2674 mlxsw_sp_port->learning = 1;
2675 mlxsw_sp_port->learning_sync = 1;
2676 mlxsw_sp_port->uc_flood = 1;
2677 mlxsw_sp_port->bridged = 1;
2678
2679 return 0;
2680 }
2681
2682 static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
2683 {
2684 struct net_device *dev = mlxsw_sp_port->dev;
2685
2686 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
2687
2688 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
2689
2690 mlxsw_sp_port->learning = 0;
2691 mlxsw_sp_port->learning_sync = 0;
2692 mlxsw_sp_port->uc_flood = 0;
2693 mlxsw_sp_port->bridged = 0;
2694
2695 /* Add implicit VLAN interface in the device, so that untagged
2696 * packets will be classified to the default vFID.
2697 */
2698 mlxsw_sp_port_add_vid(dev, 0, 1);
2699 }
2700
2701 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2702 {
2703 char sldr_pl[MLXSW_REG_SLDR_LEN];
2704
2705 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
2706 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2707 }
2708
2709 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2710 {
2711 char sldr_pl[MLXSW_REG_SLDR_LEN];
2712
2713 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
2714 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2715 }
2716
2717 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2718 u16 lag_id, u8 port_index)
2719 {
2720 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2721 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2722
2723 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
2724 lag_id, port_index);
2725 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2726 }
2727
2728 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2729 u16 lag_id)
2730 {
2731 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2732 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2733
2734 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
2735 lag_id);
2736 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2737 }
2738
2739 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
2740 u16 lag_id)
2741 {
2742 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2743 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2744
2745 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
2746 lag_id);
2747 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2748 }
2749
2750 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
2751 u16 lag_id)
2752 {
2753 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2754 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2755
2756 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
2757 lag_id);
2758 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2759 }
2760
2761 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2762 struct net_device *lag_dev,
2763 u16 *p_lag_id)
2764 {
2765 struct mlxsw_sp_upper *lag;
2766 int free_lag_id = -1;
2767 int i;
2768
2769 for (i = 0; i < MLXSW_SP_LAG_MAX; i++) {
2770 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
2771 if (lag->ref_count) {
2772 if (lag->dev == lag_dev) {
2773 *p_lag_id = i;
2774 return 0;
2775 }
2776 } else if (free_lag_id < 0) {
2777 free_lag_id = i;
2778 }
2779 }
2780 if (free_lag_id < 0)
2781 return -EBUSY;
2782 *p_lag_id = free_lag_id;
2783 return 0;
2784 }
2785
2786 static bool
2787 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
2788 struct net_device *lag_dev,
2789 struct netdev_lag_upper_info *lag_upper_info)
2790 {
2791 u16 lag_id;
2792
2793 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
2794 return false;
2795 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2796 return false;
2797 return true;
2798 }
2799
2800 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2801 u16 lag_id, u8 *p_port_index)
2802 {
2803 int i;
2804
2805 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2806 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
2807 *p_port_index = i;
2808 return 0;
2809 }
2810 }
2811 return -EBUSY;
2812 }
2813
2814 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2815 struct net_device *lag_dev)
2816 {
2817 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2818 struct mlxsw_sp_upper *lag;
2819 u16 lag_id;
2820 u8 port_index;
2821 int err;
2822
2823 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
2824 if (err)
2825 return err;
2826 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2827 if (!lag->ref_count) {
2828 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
2829 if (err)
2830 return err;
2831 lag->dev = lag_dev;
2832 }
2833
2834 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
2835 if (err)
2836 return err;
2837 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
2838 if (err)
2839 goto err_col_port_add;
2840 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
2841 if (err)
2842 goto err_col_port_enable;
2843
2844 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
2845 mlxsw_sp_port->local_port);
2846 mlxsw_sp_port->lag_id = lag_id;
2847 mlxsw_sp_port->lagged = 1;
2848 lag->ref_count++;
2849 return 0;
2850
2851 err_col_port_enable:
2852 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
2853 err_col_port_add:
2854 if (!lag->ref_count)
2855 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
2856 return err;
2857 }
2858
2859 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2860 struct net_device *lag_dev)
2861 {
2862 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2863 u16 lag_id = mlxsw_sp_port->lag_id;
2864 struct mlxsw_sp_upper *lag;
2865
2866 if (!mlxsw_sp_port->lagged)
2867 return;
2868 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2869 WARN_ON(lag->ref_count == 0);
2870
2871 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
2872 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
2873
2874 if (mlxsw_sp_port->bridged) {
2875 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
2876 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
2877 }
2878
2879 if (lag->ref_count == 1)
2880 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
2881
2882 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
2883 mlxsw_sp_port->local_port);
2884 mlxsw_sp_port->lagged = 0;
2885 lag->ref_count--;
2886 }
2887
2888 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2889 u16 lag_id)
2890 {
2891 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2892 char sldr_pl[MLXSW_REG_SLDR_LEN];
2893
2894 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
2895 mlxsw_sp_port->local_port);
2896 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2897 }
2898
2899 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2900 u16 lag_id)
2901 {
2902 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2903 char sldr_pl[MLXSW_REG_SLDR_LEN];
2904
2905 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
2906 mlxsw_sp_port->local_port);
2907 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2908 }
2909
2910 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
2911 bool lag_tx_enabled)
2912 {
2913 if (lag_tx_enabled)
2914 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
2915 mlxsw_sp_port->lag_id);
2916 else
2917 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
2918 mlxsw_sp_port->lag_id);
2919 }
2920
2921 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
2922 struct netdev_lag_lower_state_info *info)
2923 {
2924 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
2925 }
2926
2927 static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
2928 struct net_device *vlan_dev)
2929 {
2930 struct mlxsw_sp_port *mlxsw_sp_vport;
2931 u16 vid = vlan_dev_vlan_id(vlan_dev);
2932
2933 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
2934 if (WARN_ON(!mlxsw_sp_vport))
2935 return -EINVAL;
2936
2937 mlxsw_sp_vport->dev = vlan_dev;
2938
2939 return 0;
2940 }
2941
2942 static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
2943 struct net_device *vlan_dev)
2944 {
2945 struct mlxsw_sp_port *mlxsw_sp_vport;
2946 u16 vid = vlan_dev_vlan_id(vlan_dev);
2947
2948 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
2949 if (WARN_ON(!mlxsw_sp_vport))
2950 return;
2951
2952 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
2953 }
2954
2955 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
2956 unsigned long event, void *ptr)
2957 {
2958 struct netdev_notifier_changeupper_info *info;
2959 struct mlxsw_sp_port *mlxsw_sp_port;
2960 struct net_device *upper_dev;
2961 struct mlxsw_sp *mlxsw_sp;
2962 int err = 0;
2963
2964 mlxsw_sp_port = netdev_priv(dev);
2965 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2966 info = ptr;
2967
2968 switch (event) {
2969 case NETDEV_PRECHANGEUPPER:
2970 upper_dev = info->upper_dev;
2971 if (!is_vlan_dev(upper_dev) &&
2972 !netif_is_lag_master(upper_dev) &&
2973 !netif_is_bridge_master(upper_dev))
2974 return -EINVAL;
2975 if (!info->linking)
2976 break;
2977 /* HW limitation forbids to put ports to multiple bridges. */
2978 if (netif_is_bridge_master(upper_dev) &&
2979 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
2980 return -EINVAL;
2981 if (netif_is_lag_master(upper_dev) &&
2982 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
2983 info->upper_info))
2984 return -EINVAL;
2985 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
2986 return -EINVAL;
2987 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
2988 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
2989 return -EINVAL;
2990 break;
2991 case NETDEV_CHANGEUPPER:
2992 upper_dev = info->upper_dev;
2993 if (is_vlan_dev(upper_dev)) {
2994 if (info->linking)
2995 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
2996 upper_dev);
2997 else
2998 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
2999 upper_dev);
3000 } else if (netif_is_bridge_master(upper_dev)) {
3001 if (info->linking)
3002 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
3003 upper_dev);
3004 else
3005 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
3006 } else if (netif_is_lag_master(upper_dev)) {
3007 if (info->linking)
3008 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
3009 upper_dev);
3010 else
3011 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
3012 upper_dev);
3013 } else {
3014 err = -EINVAL;
3015 WARN_ON(1);
3016 }
3017 break;
3018 }
3019
3020 return err;
3021 }
3022
3023 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
3024 unsigned long event, void *ptr)
3025 {
3026 struct netdev_notifier_changelowerstate_info *info;
3027 struct mlxsw_sp_port *mlxsw_sp_port;
3028 int err;
3029
3030 mlxsw_sp_port = netdev_priv(dev);
3031 info = ptr;
3032
3033 switch (event) {
3034 case NETDEV_CHANGELOWERSTATE:
3035 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3036 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3037 info->lower_state_info);
3038 if (err)
3039 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3040 }
3041 break;
3042 }
3043
3044 return 0;
3045 }
3046
3047 static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
3048 unsigned long event, void *ptr)
3049 {
3050 switch (event) {
3051 case NETDEV_PRECHANGEUPPER:
3052 case NETDEV_CHANGEUPPER:
3053 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
3054 case NETDEV_CHANGELOWERSTATE:
3055 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
3056 }
3057
3058 return 0;
3059 }
3060
3061 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3062 unsigned long event, void *ptr)
3063 {
3064 struct net_device *dev;
3065 struct list_head *iter;
3066 int ret;
3067
3068 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3069 if (mlxsw_sp_port_dev_check(dev)) {
3070 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3071 if (ret)
3072 return ret;
3073 }
3074 }
3075
3076 return 0;
3077 }
3078
3079 static struct mlxsw_sp_fid *
3080 mlxsw_sp_br_vfid_find(const struct mlxsw_sp *mlxsw_sp,
3081 const struct net_device *br_dev)
3082 {
3083 struct mlxsw_sp_fid *f;
3084
3085 list_for_each_entry(f, &mlxsw_sp->br_vfids.list, list) {
3086 if (f->dev == br_dev)
3087 return f;
3088 }
3089
3090 return NULL;
3091 }
3092
3093 static u16 mlxsw_sp_vfid_to_br_vfid(u16 vfid)
3094 {
3095 return vfid - MLXSW_SP_VFID_PORT_MAX;
3096 }
3097
3098 static u16 mlxsw_sp_br_vfid_to_vfid(u16 br_vfid)
3099 {
3100 return MLXSW_SP_VFID_PORT_MAX + br_vfid;
3101 }
3102
3103 static u16 mlxsw_sp_avail_br_vfid_get(const struct mlxsw_sp *mlxsw_sp)
3104 {
3105 return find_first_zero_bit(mlxsw_sp->br_vfids.mapped,
3106 MLXSW_SP_VFID_BR_MAX);
3107 }
3108
3109 static void mlxsw_sp_vport_br_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
3110
3111 static struct mlxsw_sp_fid *mlxsw_sp_br_vfid_create(struct mlxsw_sp *mlxsw_sp,
3112 struct net_device *br_dev)
3113 {
3114 struct device *dev = mlxsw_sp->bus_info->dev;
3115 struct mlxsw_sp_fid *f;
3116 u16 vfid, fid;
3117 int err;
3118
3119 vfid = mlxsw_sp_br_vfid_to_vfid(mlxsw_sp_avail_br_vfid_get(mlxsw_sp));
3120 if (vfid == MLXSW_SP_VFID_MAX) {
3121 dev_err(dev, "No available vFIDs\n");
3122 return ERR_PTR(-ERANGE);
3123 }
3124
3125 fid = mlxsw_sp_vfid_to_fid(vfid);
3126 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
3127 if (err) {
3128 dev_err(dev, "Failed to create FID=%d\n", fid);
3129 return ERR_PTR(err);
3130 }
3131
3132 f = kzalloc(sizeof(*f), GFP_KERNEL);
3133 if (!f)
3134 goto err_allocate_vfid;
3135
3136 f->leave = mlxsw_sp_vport_br_vfid_leave;
3137 f->fid = fid;
3138 f->dev = br_dev;
3139
3140 list_add(&f->list, &mlxsw_sp->br_vfids.list);
3141 set_bit(mlxsw_sp_vfid_to_br_vfid(vfid), mlxsw_sp->br_vfids.mapped);
3142
3143 return f;
3144
3145 err_allocate_vfid:
3146 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
3147 return ERR_PTR(-ENOMEM);
3148 }
3149
3150 static void mlxsw_sp_br_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
3151 struct mlxsw_sp_fid *f)
3152 {
3153 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
3154 u16 br_vfid = mlxsw_sp_vfid_to_br_vfid(vfid);
3155
3156 clear_bit(br_vfid, mlxsw_sp->br_vfids.mapped);
3157 list_del(&f->list);
3158
3159 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
3160
3161 kfree(f);
3162 }
3163
3164 static int mlxsw_sp_vport_br_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3165 struct net_device *br_dev)
3166 {
3167 struct mlxsw_sp_fid *f;
3168 int err;
3169
3170 f = mlxsw_sp_br_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
3171 if (!f) {
3172 f = mlxsw_sp_br_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
3173 if (IS_ERR(f))
3174 return PTR_ERR(f);
3175 }
3176
3177 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
3178 if (err)
3179 goto err_vport_flood_set;
3180
3181 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
3182 if (err)
3183 goto err_vport_fid_map;
3184
3185 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
3186 f->ref_count++;
3187
3188 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
3189
3190 return 0;
3191
3192 err_vport_fid_map:
3193 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3194 err_vport_flood_set:
3195 if (!f->ref_count)
3196 mlxsw_sp_br_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
3197 return err;
3198 }
3199
3200 static void mlxsw_sp_vport_br_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
3201 {
3202 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3203
3204 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
3205
3206 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
3207
3208 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3209
3210 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
3211
3212 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
3213 if (--f->ref_count == 0)
3214 mlxsw_sp_br_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
3215 }
3216
3217 static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3218 struct net_device *br_dev)
3219 {
3220 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3221 struct net_device *dev = mlxsw_sp_vport->dev;
3222 int err;
3223
3224 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
3225
3226 err = mlxsw_sp_vport_br_vfid_join(mlxsw_sp_vport, br_dev);
3227 if (err) {
3228 netdev_err(dev, "Failed to join vFID\n");
3229 goto err_vport_br_vfid_join;
3230 }
3231
3232 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
3233 if (err) {
3234 netdev_err(dev, "Failed to enable learning\n");
3235 goto err_port_vid_learning_set;
3236 }
3237
3238 mlxsw_sp_vport->learning = 1;
3239 mlxsw_sp_vport->learning_sync = 1;
3240 mlxsw_sp_vport->uc_flood = 1;
3241 mlxsw_sp_vport->bridged = 1;
3242
3243 return 0;
3244
3245 err_port_vid_learning_set:
3246 mlxsw_sp_vport_br_vfid_leave(mlxsw_sp_vport);
3247 err_vport_br_vfid_join:
3248 mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
3249 return err;
3250 }
3251
3252 static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
3253 {
3254 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3255
3256 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3257
3258 mlxsw_sp_vport_br_vfid_leave(mlxsw_sp_vport);
3259
3260 mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
3261
3262 mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
3263 MLXSW_REG_SPMS_STATE_FORWARDING);
3264
3265 mlxsw_sp_vport->learning = 0;
3266 mlxsw_sp_vport->learning_sync = 0;
3267 mlxsw_sp_vport->uc_flood = 0;
3268 mlxsw_sp_vport->bridged = 0;
3269 }
3270
3271 static bool
3272 mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
3273 const struct net_device *br_dev)
3274 {
3275 struct mlxsw_sp_port *mlxsw_sp_vport;
3276
3277 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
3278 vport.list) {
3279 struct net_device *dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
3280
3281 if (dev && dev == br_dev)
3282 return false;
3283 }
3284
3285 return true;
3286 }
3287
3288 static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
3289 unsigned long event, void *ptr,
3290 u16 vid)
3291 {
3292 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3293 struct netdev_notifier_changeupper_info *info = ptr;
3294 struct mlxsw_sp_port *mlxsw_sp_vport;
3295 struct net_device *upper_dev;
3296 int err = 0;
3297
3298 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3299
3300 switch (event) {
3301 case NETDEV_PRECHANGEUPPER:
3302 upper_dev = info->upper_dev;
3303 if (!netif_is_bridge_master(upper_dev))
3304 return -EINVAL;
3305 if (!info->linking)
3306 break;
3307 /* We can't have multiple VLAN interfaces configured on
3308 * the same port and being members in the same bridge.
3309 */
3310 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
3311 upper_dev))
3312 return -EINVAL;
3313 break;
3314 case NETDEV_CHANGEUPPER:
3315 upper_dev = info->upper_dev;
3316 if (info->linking) {
3317 if (WARN_ON(!mlxsw_sp_vport))
3318 return -EINVAL;
3319 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
3320 upper_dev);
3321 } else {
3322 if (!mlxsw_sp_vport)
3323 return 0;
3324 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
3325 }
3326 }
3327
3328 return err;
3329 }
3330
3331 static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
3332 unsigned long event, void *ptr,
3333 u16 vid)
3334 {
3335 struct net_device *dev;
3336 struct list_head *iter;
3337 int ret;
3338
3339 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3340 if (mlxsw_sp_port_dev_check(dev)) {
3341 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
3342 vid);
3343 if (ret)
3344 return ret;
3345 }
3346 }
3347
3348 return 0;
3349 }
3350
3351 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
3352 unsigned long event, void *ptr)
3353 {
3354 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3355 u16 vid = vlan_dev_vlan_id(vlan_dev);
3356
3357 if (mlxsw_sp_port_dev_check(real_dev))
3358 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
3359 vid);
3360 else if (netif_is_lag_master(real_dev))
3361 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
3362 vid);
3363
3364 return 0;
3365 }
3366
3367 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3368 unsigned long event, void *ptr)
3369 {
3370 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3371 int err = 0;
3372
3373 if (mlxsw_sp_port_dev_check(dev))
3374 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3375 else if (netif_is_lag_master(dev))
3376 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
3377 else if (is_vlan_dev(dev))
3378 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
3379
3380 return notifier_from_errno(err);
3381 }
3382
3383 static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
3384 .notifier_call = mlxsw_sp_netdevice_event,
3385 };
3386
3387 static int __init mlxsw_sp_module_init(void)
3388 {
3389 int err;
3390
3391 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3392 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
3393 if (err)
3394 goto err_core_driver_register;
3395 return 0;
3396
3397 err_core_driver_register:
3398 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3399 return err;
3400 }
3401
3402 static void __exit mlxsw_sp_module_exit(void)
3403 {
3404 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
3405 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3406 }
3407
3408 module_init(mlxsw_sp_module_init);
3409 module_exit(mlxsw_sp_module_exit);
3410
3411 MODULE_LICENSE("Dual BSD/GPL");
3412 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
3413 MODULE_DESCRIPTION("Mellanox Spectrum driver");
3414 MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SPECTRUM);
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