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mlxsw: spectrum_switchdev: Don't batch learning operations
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
1 /*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/pci.h>
41 #include <linux/netdevice.h>
42 #include <linux/etherdevice.h>
43 #include <linux/ethtool.h>
44 #include <linux/slab.h>
45 #include <linux/device.h>
46 #include <linux/skbuff.h>
47 #include <linux/if_vlan.h>
48 #include <linux/if_bridge.h>
49 #include <linux/workqueue.h>
50 #include <linux/jiffies.h>
51 #include <linux/bitops.h>
52 #include <linux/list.h>
53 #include <linux/notifier.h>
54 #include <linux/dcbnl.h>
55 #include <linux/inetdevice.h>
56 #include <net/switchdev.h>
57 #include <net/pkt_cls.h>
58 #include <net/tc_act/tc_mirred.h>
59 #include <net/netevent.h>
60 #include <net/tc_act/tc_sample.h>
61
62 #include "spectrum.h"
63 #include "pci.h"
64 #include "core.h"
65 #include "reg.h"
66 #include "port.h"
67 #include "trap.h"
68 #include "txheader.h"
69 #include "spectrum_cnt.h"
70 #include "spectrum_dpipe.h"
71
72 static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
73 static const char mlxsw_sp_driver_version[] = "1.0";
74
75 /* tx_hdr_version
76 * Tx header version.
77 * Must be set to 1.
78 */
79 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
80
81 /* tx_hdr_ctl
82 * Packet control type.
83 * 0 - Ethernet control (e.g. EMADs, LACP)
84 * 1 - Ethernet data
85 */
86 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
87
88 /* tx_hdr_proto
89 * Packet protocol type. Must be set to 1 (Ethernet).
90 */
91 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
92
93 /* tx_hdr_rx_is_router
94 * Packet is sent from the router. Valid for data packets only.
95 */
96 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
97
98 /* tx_hdr_fid_valid
99 * Indicates if the 'fid' field is valid and should be used for
100 * forwarding lookup. Valid for data packets only.
101 */
102 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
103
104 /* tx_hdr_swid
105 * Switch partition ID. Must be set to 0.
106 */
107 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
108
109 /* tx_hdr_control_tclass
110 * Indicates if the packet should use the control TClass and not one
111 * of the data TClasses.
112 */
113 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
114
115 /* tx_hdr_etclass
116 * Egress TClass to be used on the egress device on the egress port.
117 */
118 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
119
120 /* tx_hdr_port_mid
121 * Destination local port for unicast packets.
122 * Destination multicast ID for multicast packets.
123 *
124 * Control packets are directed to a specific egress port, while data
125 * packets are transmitted through the CPU port (0) into the switch partition,
126 * where forwarding rules are applied.
127 */
128 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
129
130 /* tx_hdr_fid
131 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
132 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
133 * Valid for data packets only.
134 */
135 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
136
137 /* tx_hdr_type
138 * 0 - Data packets
139 * 6 - Control packets
140 */
141 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
142
143 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
144 unsigned int counter_index, u64 *packets,
145 u64 *bytes)
146 {
147 char mgpc_pl[MLXSW_REG_MGPC_LEN];
148 int err;
149
150 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
151 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
152 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
153 if (err)
154 return err;
155 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
156 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
157 return 0;
158 }
159
160 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
161 unsigned int counter_index)
162 {
163 char mgpc_pl[MLXSW_REG_MGPC_LEN];
164
165 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
166 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
167 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
168 }
169
170 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
171 unsigned int *p_counter_index)
172 {
173 int err;
174
175 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
176 p_counter_index);
177 if (err)
178 return err;
179 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
180 if (err)
181 goto err_counter_clear;
182 return 0;
183
184 err_counter_clear:
185 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
186 *p_counter_index);
187 return err;
188 }
189
190 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
191 unsigned int counter_index)
192 {
193 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
194 counter_index);
195 }
196
197 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
198 const struct mlxsw_tx_info *tx_info)
199 {
200 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
201
202 memset(txhdr, 0, MLXSW_TXHDR_LEN);
203
204 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
205 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
206 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
207 mlxsw_tx_hdr_swid_set(txhdr, 0);
208 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
209 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
210 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
211 }
212
213 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
214 u8 state)
215 {
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
217 enum mlxsw_reg_spms_state spms_state;
218 char *spms_pl;
219 int err;
220
221 switch (state) {
222 case BR_STATE_FORWARDING:
223 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
224 break;
225 case BR_STATE_LEARNING:
226 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
227 break;
228 case BR_STATE_LISTENING: /* fall-through */
229 case BR_STATE_DISABLED: /* fall-through */
230 case BR_STATE_BLOCKING:
231 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
232 break;
233 default:
234 BUG();
235 }
236
237 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
238 if (!spms_pl)
239 return -ENOMEM;
240 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
241 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
242
243 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
244 kfree(spms_pl);
245 return err;
246 }
247
248 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
249 {
250 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
251 int err;
252
253 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
254 if (err)
255 return err;
256 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
257 return 0;
258 }
259
260 static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
261 {
262 int i;
263
264 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
265 return -EIO;
266
267 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
268 MAX_SPAN);
269 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
270 sizeof(struct mlxsw_sp_span_entry),
271 GFP_KERNEL);
272 if (!mlxsw_sp->span.entries)
273 return -ENOMEM;
274
275 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
276 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
277
278 return 0;
279 }
280
281 static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
282 {
283 int i;
284
285 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
286 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
287
288 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
289 }
290 kfree(mlxsw_sp->span.entries);
291 }
292
293 static struct mlxsw_sp_span_entry *
294 mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
295 {
296 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
297 struct mlxsw_sp_span_entry *span_entry;
298 char mpat_pl[MLXSW_REG_MPAT_LEN];
299 u8 local_port = port->local_port;
300 int index;
301 int i;
302 int err;
303
304 /* find a free entry to use */
305 index = -1;
306 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
307 if (!mlxsw_sp->span.entries[i].used) {
308 index = i;
309 span_entry = &mlxsw_sp->span.entries[i];
310 break;
311 }
312 }
313 if (index < 0)
314 return NULL;
315
316 /* create a new port analayzer entry for local_port */
317 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
318 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
319 if (err)
320 return NULL;
321
322 span_entry->used = true;
323 span_entry->id = index;
324 span_entry->ref_count = 1;
325 span_entry->local_port = local_port;
326 return span_entry;
327 }
328
329 static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
330 struct mlxsw_sp_span_entry *span_entry)
331 {
332 u8 local_port = span_entry->local_port;
333 char mpat_pl[MLXSW_REG_MPAT_LEN];
334 int pa_id = span_entry->id;
335
336 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
337 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
338 span_entry->used = false;
339 }
340
341 static struct mlxsw_sp_span_entry *
342 mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
343 {
344 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
345 int i;
346
347 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
348 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
349
350 if (curr->used && curr->local_port == port->local_port)
351 return curr;
352 }
353 return NULL;
354 }
355
356 static struct mlxsw_sp_span_entry
357 *mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
358 {
359 struct mlxsw_sp_span_entry *span_entry;
360
361 span_entry = mlxsw_sp_span_entry_find(port);
362 if (span_entry) {
363 /* Already exists, just take a reference */
364 span_entry->ref_count++;
365 return span_entry;
366 }
367
368 return mlxsw_sp_span_entry_create(port);
369 }
370
371 static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
372 struct mlxsw_sp_span_entry *span_entry)
373 {
374 WARN_ON(!span_entry->ref_count);
375 if (--span_entry->ref_count == 0)
376 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
377 return 0;
378 }
379
380 static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
381 {
382 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
383 struct mlxsw_sp_span_inspected_port *p;
384 int i;
385
386 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
387 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
388
389 list_for_each_entry(p, &curr->bound_ports_list, list)
390 if (p->local_port == port->local_port &&
391 p->type == MLXSW_SP_SPAN_EGRESS)
392 return true;
393 }
394
395 return false;
396 }
397
398 static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
399 int mtu)
400 {
401 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
402 }
403
404 static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
405 {
406 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
407 char sbib_pl[MLXSW_REG_SBIB_LEN];
408 int err;
409
410 /* If port is egress mirrored, the shared buffer size should be
411 * updated according to the mtu value
412 */
413 if (mlxsw_sp_span_is_egress_mirror(port)) {
414 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
415
416 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
417 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
418 if (err) {
419 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
420 return err;
421 }
422 }
423
424 return 0;
425 }
426
427 static struct mlxsw_sp_span_inspected_port *
428 mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
429 struct mlxsw_sp_span_entry *span_entry)
430 {
431 struct mlxsw_sp_span_inspected_port *p;
432
433 list_for_each_entry(p, &span_entry->bound_ports_list, list)
434 if (port->local_port == p->local_port)
435 return p;
436 return NULL;
437 }
438
439 static int
440 mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
441 struct mlxsw_sp_span_entry *span_entry,
442 enum mlxsw_sp_span_type type)
443 {
444 struct mlxsw_sp_span_inspected_port *inspected_port;
445 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
446 char mpar_pl[MLXSW_REG_MPAR_LEN];
447 char sbib_pl[MLXSW_REG_SBIB_LEN];
448 int pa_id = span_entry->id;
449 int err;
450
451 /* if it is an egress SPAN, bind a shared buffer to it */
452 if (type == MLXSW_SP_SPAN_EGRESS) {
453 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
454 port->dev->mtu);
455
456 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
457 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
458 if (err) {
459 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
460 return err;
461 }
462 }
463
464 /* bind the port to the SPAN entry */
465 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
466 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
467 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
468 if (err)
469 goto err_mpar_reg_write;
470
471 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
472 if (!inspected_port) {
473 err = -ENOMEM;
474 goto err_inspected_port_alloc;
475 }
476 inspected_port->local_port = port->local_port;
477 inspected_port->type = type;
478 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
479
480 return 0;
481
482 err_mpar_reg_write:
483 err_inspected_port_alloc:
484 if (type == MLXSW_SP_SPAN_EGRESS) {
485 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
486 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
487 }
488 return err;
489 }
490
491 static void
492 mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
493 struct mlxsw_sp_span_entry *span_entry,
494 enum mlxsw_sp_span_type type)
495 {
496 struct mlxsw_sp_span_inspected_port *inspected_port;
497 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
498 char mpar_pl[MLXSW_REG_MPAR_LEN];
499 char sbib_pl[MLXSW_REG_SBIB_LEN];
500 int pa_id = span_entry->id;
501
502 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
503 if (!inspected_port)
504 return;
505
506 /* remove the inspected port */
507 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
508 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
509 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
510
511 /* remove the SBIB buffer if it was egress SPAN */
512 if (type == MLXSW_SP_SPAN_EGRESS) {
513 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
514 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
515 }
516
517 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
518
519 list_del(&inspected_port->list);
520 kfree(inspected_port);
521 }
522
523 static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
524 struct mlxsw_sp_port *to,
525 enum mlxsw_sp_span_type type)
526 {
527 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
528 struct mlxsw_sp_span_entry *span_entry;
529 int err;
530
531 span_entry = mlxsw_sp_span_entry_get(to);
532 if (!span_entry)
533 return -ENOENT;
534
535 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
536 span_entry->id);
537
538 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
539 if (err)
540 goto err_port_bind;
541
542 return 0;
543
544 err_port_bind:
545 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
546 return err;
547 }
548
549 static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
550 struct mlxsw_sp_port *to,
551 enum mlxsw_sp_span_type type)
552 {
553 struct mlxsw_sp_span_entry *span_entry;
554
555 span_entry = mlxsw_sp_span_entry_find(to);
556 if (!span_entry) {
557 netdev_err(from->dev, "no span entry found\n");
558 return;
559 }
560
561 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
562 span_entry->id);
563 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
564 }
565
566 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
567 bool enable, u32 rate)
568 {
569 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
570 char mpsc_pl[MLXSW_REG_MPSC_LEN];
571
572 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
573 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
574 }
575
576 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
577 bool is_up)
578 {
579 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
580 char paos_pl[MLXSW_REG_PAOS_LEN];
581
582 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
583 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
584 MLXSW_PORT_ADMIN_STATUS_DOWN);
585 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
586 }
587
588 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
589 unsigned char *addr)
590 {
591 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
592 char ppad_pl[MLXSW_REG_PPAD_LEN];
593
594 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
595 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
596 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
597 }
598
599 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
600 {
601 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
602 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
603
604 ether_addr_copy(addr, mlxsw_sp->base_mac);
605 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
606 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
607 }
608
609 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
610 {
611 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
612 char pmtu_pl[MLXSW_REG_PMTU_LEN];
613 int max_mtu;
614 int err;
615
616 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
617 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
618 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
619 if (err)
620 return err;
621 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
622
623 if (mtu > max_mtu)
624 return -EINVAL;
625
626 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
627 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
628 }
629
630 static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
631 u8 swid)
632 {
633 char pspa_pl[MLXSW_REG_PSPA_LEN];
634
635 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
636 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
637 }
638
639 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
640 {
641 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
642
643 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
644 swid);
645 }
646
647 static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
648 bool enable)
649 {
650 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
651 char svpe_pl[MLXSW_REG_SVPE_LEN];
652
653 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
654 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
655 }
656
657 int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
658 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
659 u16 vid)
660 {
661 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
662 char svfa_pl[MLXSW_REG_SVFA_LEN];
663
664 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
665 fid, vid);
666 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
667 }
668
669 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
670 bool learn_enable)
671 {
672 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
673 char *spvmlr_pl;
674 int err;
675
676 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
677 if (!spvmlr_pl)
678 return -ENOMEM;
679 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
680 learn_enable);
681 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
682 kfree(spvmlr_pl);
683 return err;
684 }
685
686 static int
687 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
688 {
689 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
690 char sspr_pl[MLXSW_REG_SSPR_LEN];
691
692 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
693 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
694 }
695
696 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
697 u8 local_port, u8 *p_module,
698 u8 *p_width, u8 *p_lane)
699 {
700 char pmlp_pl[MLXSW_REG_PMLP_LEN];
701 int err;
702
703 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
704 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
705 if (err)
706 return err;
707 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
708 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
709 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
710 return 0;
711 }
712
713 static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
714 u8 module, u8 width, u8 lane)
715 {
716 char pmlp_pl[MLXSW_REG_PMLP_LEN];
717 int i;
718
719 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
720 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
721 for (i = 0; i < width; i++) {
722 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
723 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
724 }
725
726 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
727 }
728
729 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
730 {
731 char pmlp_pl[MLXSW_REG_PMLP_LEN];
732
733 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
734 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
735 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
736 }
737
738 static int mlxsw_sp_port_open(struct net_device *dev)
739 {
740 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
741 int err;
742
743 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
744 if (err)
745 return err;
746 netif_start_queue(dev);
747 return 0;
748 }
749
750 static int mlxsw_sp_port_stop(struct net_device *dev)
751 {
752 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
753
754 netif_stop_queue(dev);
755 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
756 }
757
758 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
759 struct net_device *dev)
760 {
761 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
762 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
763 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
764 const struct mlxsw_tx_info tx_info = {
765 .local_port = mlxsw_sp_port->local_port,
766 .is_emad = false,
767 };
768 u64 len;
769 int err;
770
771 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
772 return NETDEV_TX_BUSY;
773
774 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
775 struct sk_buff *skb_orig = skb;
776
777 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
778 if (!skb) {
779 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
780 dev_kfree_skb_any(skb_orig);
781 return NETDEV_TX_OK;
782 }
783 dev_consume_skb_any(skb_orig);
784 }
785
786 if (eth_skb_pad(skb)) {
787 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
788 return NETDEV_TX_OK;
789 }
790
791 mlxsw_sp_txhdr_construct(skb, &tx_info);
792 /* TX header is consumed by HW on the way so we shouldn't count its
793 * bytes as being sent.
794 */
795 len = skb->len - MLXSW_TXHDR_LEN;
796
797 /* Due to a race we might fail here because of a full queue. In that
798 * unlikely case we simply drop the packet.
799 */
800 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
801
802 if (!err) {
803 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
804 u64_stats_update_begin(&pcpu_stats->syncp);
805 pcpu_stats->tx_packets++;
806 pcpu_stats->tx_bytes += len;
807 u64_stats_update_end(&pcpu_stats->syncp);
808 } else {
809 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
810 dev_kfree_skb_any(skb);
811 }
812 return NETDEV_TX_OK;
813 }
814
815 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
816 {
817 }
818
819 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
820 {
821 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
822 struct sockaddr *addr = p;
823 int err;
824
825 if (!is_valid_ether_addr(addr->sa_data))
826 return -EADDRNOTAVAIL;
827
828 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
829 if (err)
830 return err;
831 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
832 return 0;
833 }
834
835 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
836 int mtu)
837 {
838 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
839 }
840
841 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
842
843 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
844 u16 delay)
845 {
846 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
847 BITS_PER_BYTE));
848 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
849 mtu);
850 }
851
852 /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
853 * Assumes 100m cable and maximum MTU.
854 */
855 #define MLXSW_SP_PAUSE_DELAY 58752
856
857 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
858 u16 delay, bool pfc, bool pause)
859 {
860 if (pfc)
861 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
862 else if (pause)
863 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
864 else
865 return 0;
866 }
867
868 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
869 bool lossy)
870 {
871 if (lossy)
872 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
873 else
874 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
875 thres);
876 }
877
878 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
879 u8 *prio_tc, bool pause_en,
880 struct ieee_pfc *my_pfc)
881 {
882 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
883 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
884 u16 delay = !!my_pfc ? my_pfc->delay : 0;
885 char pbmc_pl[MLXSW_REG_PBMC_LEN];
886 int i, j, err;
887
888 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
889 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
890 if (err)
891 return err;
892
893 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
894 bool configure = false;
895 bool pfc = false;
896 bool lossy;
897 u16 thres;
898
899 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
900 if (prio_tc[j] == i) {
901 pfc = pfc_en & BIT(j);
902 configure = true;
903 break;
904 }
905 }
906
907 if (!configure)
908 continue;
909
910 lossy = !(pfc || pause_en);
911 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
912 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
913 pause_en);
914 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
915 }
916
917 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
918 }
919
920 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
921 int mtu, bool pause_en)
922 {
923 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
924 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
925 struct ieee_pfc *my_pfc;
926 u8 *prio_tc;
927
928 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
929 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
930
931 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
932 pause_en, my_pfc);
933 }
934
935 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
936 {
937 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
938 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
939 int err;
940
941 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
942 if (err)
943 return err;
944 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
945 if (err)
946 goto err_span_port_mtu_update;
947 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
948 if (err)
949 goto err_port_mtu_set;
950 dev->mtu = mtu;
951 return 0;
952
953 err_port_mtu_set:
954 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
955 err_span_port_mtu_update:
956 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
957 return err;
958 }
959
960 static int
961 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
962 struct rtnl_link_stats64 *stats)
963 {
964 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
965 struct mlxsw_sp_port_pcpu_stats *p;
966 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
967 u32 tx_dropped = 0;
968 unsigned int start;
969 int i;
970
971 for_each_possible_cpu(i) {
972 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
973 do {
974 start = u64_stats_fetch_begin_irq(&p->syncp);
975 rx_packets = p->rx_packets;
976 rx_bytes = p->rx_bytes;
977 tx_packets = p->tx_packets;
978 tx_bytes = p->tx_bytes;
979 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980
981 stats->rx_packets += rx_packets;
982 stats->rx_bytes += rx_bytes;
983 stats->tx_packets += tx_packets;
984 stats->tx_bytes += tx_bytes;
985 /* tx_dropped is u32, updated without syncp protection. */
986 tx_dropped += p->tx_dropped;
987 }
988 stats->tx_dropped = tx_dropped;
989 return 0;
990 }
991
992 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
993 {
994 switch (attr_id) {
995 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
996 return true;
997 }
998
999 return false;
1000 }
1001
1002 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1003 void *sp)
1004 {
1005 switch (attr_id) {
1006 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1007 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1008 }
1009
1010 return -EINVAL;
1011 }
1012
1013 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1014 int prio, char *ppcnt_pl)
1015 {
1016 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1017 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1018
1019 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1020 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1021 }
1022
1023 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1024 struct rtnl_link_stats64 *stats)
1025 {
1026 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1027 int err;
1028
1029 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1030 0, ppcnt_pl);
1031 if (err)
1032 goto out;
1033
1034 stats->tx_packets =
1035 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1036 stats->rx_packets =
1037 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1038 stats->tx_bytes =
1039 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1040 stats->rx_bytes =
1041 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1042 stats->multicast =
1043 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1044
1045 stats->rx_crc_errors =
1046 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1047 stats->rx_frame_errors =
1048 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1049
1050 stats->rx_length_errors = (
1051 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1052 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1053 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1054
1055 stats->rx_errors = (stats->rx_crc_errors +
1056 stats->rx_frame_errors + stats->rx_length_errors);
1057
1058 out:
1059 return err;
1060 }
1061
1062 static void update_stats_cache(struct work_struct *work)
1063 {
1064 struct mlxsw_sp_port *mlxsw_sp_port =
1065 container_of(work, struct mlxsw_sp_port,
1066 hw_stats.update_dw.work);
1067
1068 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1069 goto out;
1070
1071 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1072 mlxsw_sp_port->hw_stats.cache);
1073
1074 out:
1075 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
1076 MLXSW_HW_STATS_UPDATE_TIME);
1077 }
1078
1079 /* Return the stats from a cache that is updated periodically,
1080 * as this function might get called in an atomic context.
1081 */
1082 static void
1083 mlxsw_sp_port_get_stats64(struct net_device *dev,
1084 struct rtnl_link_stats64 *stats)
1085 {
1086 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1087
1088 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
1089 }
1090
1091 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1092 u16 vid_begin, u16 vid_end,
1093 bool is_member, bool untagged)
1094 {
1095 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1096 char *spvm_pl;
1097 int err;
1098
1099 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1100 if (!spvm_pl)
1101 return -ENOMEM;
1102
1103 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1104 vid_end, is_member, untagged);
1105 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1106 kfree(spvm_pl);
1107 return err;
1108 }
1109
1110 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1111 u16 vid_end, bool is_member, bool untagged)
1112 {
1113 u16 vid, vid_e;
1114 int err;
1115
1116 for (vid = vid_begin; vid <= vid_end;
1117 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1118 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1119 vid_end);
1120
1121 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1122 is_member, untagged);
1123 if (err)
1124 return err;
1125 }
1126
1127 return 0;
1128 }
1129
1130 static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
1131 {
1132 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1133 u16 vid, last_visited_vid;
1134 int err;
1135
1136 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1137 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
1138 vid);
1139 if (err) {
1140 last_visited_vid = vid;
1141 goto err_port_vid_to_fid_set;
1142 }
1143 }
1144
1145 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
1146 if (err) {
1147 last_visited_vid = VLAN_N_VID;
1148 goto err_port_vid_to_fid_set;
1149 }
1150
1151 return 0;
1152
1153 err_port_vid_to_fid_set:
1154 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
1155 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
1156 vid);
1157 return err;
1158 }
1159
1160 static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
1161 {
1162 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1163 u16 vid;
1164 int err;
1165
1166 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
1167 if (err)
1168 return err;
1169
1170 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1171 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
1172 vid, vid);
1173 if (err)
1174 return err;
1175 }
1176
1177 return 0;
1178 }
1179
1180 static struct mlxsw_sp_port *
1181 mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1182 {
1183 struct mlxsw_sp_port *mlxsw_sp_vport;
1184
1185 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
1186 if (!mlxsw_sp_vport)
1187 return NULL;
1188
1189 /* dev will be set correctly after the VLAN device is linked
1190 * with the real device. In case of bridge SELF invocation, dev
1191 * will remain as is.
1192 */
1193 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
1194 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1195 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
1196 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
1197 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
1198 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
1199 mlxsw_sp_vport->vport.vid = vid;
1200
1201 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
1202
1203 return mlxsw_sp_vport;
1204 }
1205
1206 static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
1207 {
1208 list_del(&mlxsw_sp_vport->vport.list);
1209 kfree(mlxsw_sp_vport);
1210 }
1211
1212 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1213 __be16 __always_unused proto, u16 vid)
1214 {
1215 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1216 struct mlxsw_sp_port *mlxsw_sp_vport;
1217 bool untagged = vid == 1;
1218 int err;
1219
1220 /* VLAN 0 is added to HW filter when device goes up, but it is
1221 * reserved in our case, so simply return.
1222 */
1223 if (!vid)
1224 return 0;
1225
1226 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid))
1227 return 0;
1228
1229 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
1230 if (!mlxsw_sp_vport)
1231 return -ENOMEM;
1232
1233 /* When adding the first VLAN interface on a bridged port we need to
1234 * transition all the active 802.1Q bridge VLANs to use explicit
1235 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
1236 */
1237 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
1238 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
1239 if (err)
1240 goto err_port_vp_mode_trans;
1241 }
1242
1243 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
1244 if (err)
1245 goto err_port_add_vid;
1246
1247 return 0;
1248
1249 err_port_add_vid:
1250 if (list_is_singular(&mlxsw_sp_port->vports_list))
1251 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
1252 err_port_vp_mode_trans:
1253 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1254 return err;
1255 }
1256
1257 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1258 __be16 __always_unused proto, u16 vid)
1259 {
1260 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1261 struct mlxsw_sp_port *mlxsw_sp_vport;
1262 struct mlxsw_sp_fid *f;
1263
1264 /* VLAN 0 is removed from HW filter when device goes down, but
1265 * it is reserved in our case, so simply return.
1266 */
1267 if (!vid)
1268 return 0;
1269
1270 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
1271 if (WARN_ON(!mlxsw_sp_vport))
1272 return 0;
1273
1274 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
1275
1276 /* Drop FID reference. If this was the last reference the
1277 * resources will be freed.
1278 */
1279 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
1280 if (f && !WARN_ON(!f->leave))
1281 f->leave(mlxsw_sp_vport);
1282
1283 /* When removing the last VLAN interface on a bridged port we need to
1284 * transition all active 802.1Q bridge VLANs to use VID to FID
1285 * mappings and set port's mode to VLAN mode.
1286 */
1287 if (list_is_singular(&mlxsw_sp_port->vports_list))
1288 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
1289
1290 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1291
1292 return 0;
1293 }
1294
1295 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1296 size_t len)
1297 {
1298 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1299 u8 module = mlxsw_sp_port->mapping.module;
1300 u8 width = mlxsw_sp_port->mapping.width;
1301 u8 lane = mlxsw_sp_port->mapping.lane;
1302 int err;
1303
1304 if (!mlxsw_sp_port->split)
1305 err = snprintf(name, len, "p%d", module + 1);
1306 else
1307 err = snprintf(name, len, "p%ds%d", module + 1,
1308 lane / width);
1309
1310 if (err >= len)
1311 return -EINVAL;
1312
1313 return 0;
1314 }
1315
1316 static struct mlxsw_sp_port_mall_tc_entry *
1317 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1318 unsigned long cookie) {
1319 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1320
1321 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1322 if (mall_tc_entry->cookie == cookie)
1323 return mall_tc_entry;
1324
1325 return NULL;
1326 }
1327
1328 static int
1329 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1330 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1331 const struct tc_action *a,
1332 bool ingress)
1333 {
1334 struct net *net = dev_net(mlxsw_sp_port->dev);
1335 enum mlxsw_sp_span_type span_type;
1336 struct mlxsw_sp_port *to_port;
1337 struct net_device *to_dev;
1338 int ifindex;
1339
1340 ifindex = tcf_mirred_ifindex(a);
1341 to_dev = __dev_get_by_index(net, ifindex);
1342 if (!to_dev) {
1343 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1344 return -EINVAL;
1345 }
1346
1347 if (!mlxsw_sp_port_dev_check(to_dev)) {
1348 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
1349 return -EOPNOTSUPP;
1350 }
1351 to_port = netdev_priv(to_dev);
1352
1353 mirror->to_local_port = to_port->local_port;
1354 mirror->ingress = ingress;
1355 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1356 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1357 }
1358
1359 static void
1360 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1361 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1362 {
1363 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1364 enum mlxsw_sp_span_type span_type;
1365 struct mlxsw_sp_port *to_port;
1366
1367 to_port = mlxsw_sp->ports[mirror->to_local_port];
1368 span_type = mirror->ingress ?
1369 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1370 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
1371 }
1372
1373 static int
1374 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1375 struct tc_cls_matchall_offload *cls,
1376 const struct tc_action *a,
1377 bool ingress)
1378 {
1379 int err;
1380
1381 if (!mlxsw_sp_port->sample)
1382 return -EOPNOTSUPP;
1383 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1384 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1385 return -EEXIST;
1386 }
1387 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1388 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1389 return -EOPNOTSUPP;
1390 }
1391
1392 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1393 tcf_sample_psample_group(a));
1394 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1395 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1396 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1397
1398 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1399 if (err)
1400 goto err_port_sample_set;
1401 return 0;
1402
1403 err_port_sample_set:
1404 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1405 return err;
1406 }
1407
1408 static void
1409 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1410 {
1411 if (!mlxsw_sp_port->sample)
1412 return;
1413
1414 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1415 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1416 }
1417
1418 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1419 __be16 protocol,
1420 struct tc_cls_matchall_offload *cls,
1421 bool ingress)
1422 {
1423 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1424 const struct tc_action *a;
1425 LIST_HEAD(actions);
1426 int err;
1427
1428 if (!tc_single_action(cls->exts)) {
1429 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1430 return -EOPNOTSUPP;
1431 }
1432
1433 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1434 if (!mall_tc_entry)
1435 return -ENOMEM;
1436 mall_tc_entry->cookie = cls->cookie;
1437
1438 tcf_exts_to_list(cls->exts, &actions);
1439 a = list_first_entry(&actions, struct tc_action, list);
1440
1441 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1442 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1443
1444 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1445 mirror = &mall_tc_entry->mirror;
1446 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1447 mirror, a, ingress);
1448 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1449 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1450 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, cls,
1451 a, ingress);
1452 } else {
1453 err = -EOPNOTSUPP;
1454 }
1455
1456 if (err)
1457 goto err_add_action;
1458
1459 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1460 return 0;
1461
1462 err_add_action:
1463 kfree(mall_tc_entry);
1464 return err;
1465 }
1466
1467 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1468 struct tc_cls_matchall_offload *cls)
1469 {
1470 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1471
1472 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1473 cls->cookie);
1474 if (!mall_tc_entry) {
1475 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1476 return;
1477 }
1478 list_del(&mall_tc_entry->list);
1479
1480 switch (mall_tc_entry->type) {
1481 case MLXSW_SP_PORT_MALL_MIRROR:
1482 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1483 &mall_tc_entry->mirror);
1484 break;
1485 case MLXSW_SP_PORT_MALL_SAMPLE:
1486 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1487 break;
1488 default:
1489 WARN_ON(1);
1490 }
1491
1492 kfree(mall_tc_entry);
1493 }
1494
1495 static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
1496 __be16 proto, struct tc_to_netdev *tc)
1497 {
1498 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1499 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1500
1501 switch (tc->type) {
1502 case TC_SETUP_MATCHALL:
1503 switch (tc->cls_mall->command) {
1504 case TC_CLSMATCHALL_REPLACE:
1505 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1506 proto,
1507 tc->cls_mall,
1508 ingress);
1509 case TC_CLSMATCHALL_DESTROY:
1510 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1511 tc->cls_mall);
1512 return 0;
1513 default:
1514 return -EOPNOTSUPP;
1515 }
1516 case TC_SETUP_CLSFLOWER:
1517 switch (tc->cls_flower->command) {
1518 case TC_CLSFLOWER_REPLACE:
1519 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress,
1520 proto, tc->cls_flower);
1521 case TC_CLSFLOWER_DESTROY:
1522 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress,
1523 tc->cls_flower);
1524 return 0;
1525 case TC_CLSFLOWER_STATS:
1526 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress,
1527 tc->cls_flower);
1528 default:
1529 return -EOPNOTSUPP;
1530 }
1531 }
1532
1533 return -EOPNOTSUPP;
1534 }
1535
1536 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1537 .ndo_open = mlxsw_sp_port_open,
1538 .ndo_stop = mlxsw_sp_port_stop,
1539 .ndo_start_xmit = mlxsw_sp_port_xmit,
1540 .ndo_setup_tc = mlxsw_sp_setup_tc,
1541 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
1542 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1543 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1544 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
1545 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1546 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
1547 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1548 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1549 .ndo_fdb_add = switchdev_port_fdb_add,
1550 .ndo_fdb_del = switchdev_port_fdb_del,
1551 .ndo_fdb_dump = switchdev_port_fdb_dump,
1552 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
1553 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
1554 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
1555 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
1556 };
1557
1558 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1559 struct ethtool_drvinfo *drvinfo)
1560 {
1561 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1562 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1563
1564 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1565 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1566 sizeof(drvinfo->version));
1567 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1568 "%d.%d.%d",
1569 mlxsw_sp->bus_info->fw_rev.major,
1570 mlxsw_sp->bus_info->fw_rev.minor,
1571 mlxsw_sp->bus_info->fw_rev.subminor);
1572 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1573 sizeof(drvinfo->bus_info));
1574 }
1575
1576 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1577 struct ethtool_pauseparam *pause)
1578 {
1579 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1580
1581 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1582 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1583 }
1584
1585 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1586 struct ethtool_pauseparam *pause)
1587 {
1588 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1589
1590 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1591 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1592 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1593
1594 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1595 pfcc_pl);
1596 }
1597
1598 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1599 struct ethtool_pauseparam *pause)
1600 {
1601 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1602 bool pause_en = pause->tx_pause || pause->rx_pause;
1603 int err;
1604
1605 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1606 netdev_err(dev, "PFC already enabled on port\n");
1607 return -EINVAL;
1608 }
1609
1610 if (pause->autoneg) {
1611 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1612 return -EINVAL;
1613 }
1614
1615 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1616 if (err) {
1617 netdev_err(dev, "Failed to configure port's headroom\n");
1618 return err;
1619 }
1620
1621 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1622 if (err) {
1623 netdev_err(dev, "Failed to set PAUSE parameters\n");
1624 goto err_port_pause_configure;
1625 }
1626
1627 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1628 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1629
1630 return 0;
1631
1632 err_port_pause_configure:
1633 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1634 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1635 return err;
1636 }
1637
1638 struct mlxsw_sp_port_hw_stats {
1639 char str[ETH_GSTRING_LEN];
1640 u64 (*getter)(const char *payload);
1641 bool cells_bytes;
1642 };
1643
1644 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1645 {
1646 .str = "a_frames_transmitted_ok",
1647 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1648 },
1649 {
1650 .str = "a_frames_received_ok",
1651 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1652 },
1653 {
1654 .str = "a_frame_check_sequence_errors",
1655 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1656 },
1657 {
1658 .str = "a_alignment_errors",
1659 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1660 },
1661 {
1662 .str = "a_octets_transmitted_ok",
1663 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1664 },
1665 {
1666 .str = "a_octets_received_ok",
1667 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1668 },
1669 {
1670 .str = "a_multicast_frames_xmitted_ok",
1671 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1672 },
1673 {
1674 .str = "a_broadcast_frames_xmitted_ok",
1675 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1676 },
1677 {
1678 .str = "a_multicast_frames_received_ok",
1679 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1680 },
1681 {
1682 .str = "a_broadcast_frames_received_ok",
1683 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1684 },
1685 {
1686 .str = "a_in_range_length_errors",
1687 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1688 },
1689 {
1690 .str = "a_out_of_range_length_field",
1691 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1692 },
1693 {
1694 .str = "a_frame_too_long_errors",
1695 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1696 },
1697 {
1698 .str = "a_symbol_error_during_carrier",
1699 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1700 },
1701 {
1702 .str = "a_mac_control_frames_transmitted",
1703 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1704 },
1705 {
1706 .str = "a_mac_control_frames_received",
1707 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1708 },
1709 {
1710 .str = "a_unsupported_opcodes_received",
1711 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1712 },
1713 {
1714 .str = "a_pause_mac_ctrl_frames_received",
1715 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1716 },
1717 {
1718 .str = "a_pause_mac_ctrl_frames_xmitted",
1719 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1720 },
1721 };
1722
1723 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1724
1725 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1726 {
1727 .str = "rx_octets_prio",
1728 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1729 },
1730 {
1731 .str = "rx_frames_prio",
1732 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1733 },
1734 {
1735 .str = "tx_octets_prio",
1736 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1737 },
1738 {
1739 .str = "tx_frames_prio",
1740 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1741 },
1742 {
1743 .str = "rx_pause_prio",
1744 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1745 },
1746 {
1747 .str = "rx_pause_duration_prio",
1748 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1749 },
1750 {
1751 .str = "tx_pause_prio",
1752 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1753 },
1754 {
1755 .str = "tx_pause_duration_prio",
1756 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1757 },
1758 };
1759
1760 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1761
1762 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1763 {
1764 .str = "tc_transmit_queue_tc",
1765 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1766 .cells_bytes = true,
1767 },
1768 {
1769 .str = "tc_no_buffer_discard_uc_tc",
1770 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1771 },
1772 };
1773
1774 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1775
1776 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
1777 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1778 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
1779 IEEE_8021QAZ_MAX_TCS)
1780
1781 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1782 {
1783 int i;
1784
1785 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1786 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1787 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1788 *p += ETH_GSTRING_LEN;
1789 }
1790 }
1791
1792 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1793 {
1794 int i;
1795
1796 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1797 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1798 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1799 *p += ETH_GSTRING_LEN;
1800 }
1801 }
1802
1803 static void mlxsw_sp_port_get_strings(struct net_device *dev,
1804 u32 stringset, u8 *data)
1805 {
1806 u8 *p = data;
1807 int i;
1808
1809 switch (stringset) {
1810 case ETH_SS_STATS:
1811 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1812 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1813 ETH_GSTRING_LEN);
1814 p += ETH_GSTRING_LEN;
1815 }
1816
1817 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1818 mlxsw_sp_port_get_prio_strings(&p, i);
1819
1820 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1821 mlxsw_sp_port_get_tc_strings(&p, i);
1822
1823 break;
1824 }
1825 }
1826
1827 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1828 enum ethtool_phys_id_state state)
1829 {
1830 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1831 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1832 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1833 bool active;
1834
1835 switch (state) {
1836 case ETHTOOL_ID_ACTIVE:
1837 active = true;
1838 break;
1839 case ETHTOOL_ID_INACTIVE:
1840 active = false;
1841 break;
1842 default:
1843 return -EOPNOTSUPP;
1844 }
1845
1846 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1847 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1848 }
1849
1850 static int
1851 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
1852 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
1853 {
1854 switch (grp) {
1855 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
1856 *p_hw_stats = mlxsw_sp_port_hw_stats;
1857 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
1858 break;
1859 case MLXSW_REG_PPCNT_PRIO_CNT:
1860 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
1861 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1862 break;
1863 case MLXSW_REG_PPCNT_TC_CNT:
1864 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
1865 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
1866 break;
1867 default:
1868 WARN_ON(1);
1869 return -EOPNOTSUPP;
1870 }
1871 return 0;
1872 }
1873
1874 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
1875 enum mlxsw_reg_ppcnt_grp grp, int prio,
1876 u64 *data, int data_index)
1877 {
1878 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1879 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1880 struct mlxsw_sp_port_hw_stats *hw_stats;
1881 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1882 int i, len;
1883 int err;
1884
1885 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
1886 if (err)
1887 return;
1888 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
1889 for (i = 0; i < len; i++) {
1890 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
1891 if (!hw_stats[i].cells_bytes)
1892 continue;
1893 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
1894 data[data_index + i]);
1895 }
1896 }
1897
1898 static void mlxsw_sp_port_get_stats(struct net_device *dev,
1899 struct ethtool_stats *stats, u64 *data)
1900 {
1901 int i, data_index = 0;
1902
1903 /* IEEE 802.3 Counters */
1904 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
1905 data, data_index);
1906 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
1907
1908 /* Per-Priority Counters */
1909 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1910 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
1911 data, data_index);
1912 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1913 }
1914
1915 /* Per-TC Counters */
1916 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1917 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
1918 data, data_index);
1919 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
1920 }
1921 }
1922
1923 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1924 {
1925 switch (sset) {
1926 case ETH_SS_STATS:
1927 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
1928 default:
1929 return -EOPNOTSUPP;
1930 }
1931 }
1932
1933 struct mlxsw_sp_port_link_mode {
1934 enum ethtool_link_mode_bit_indices mask_ethtool;
1935 u32 mask;
1936 u32 speed;
1937 };
1938
1939 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1940 {
1941 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1942 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1943 .speed = SPEED_100,
1944 },
1945 {
1946 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1947 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1948 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1949 .speed = SPEED_1000,
1950 },
1951 {
1952 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1953 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1954 .speed = SPEED_10000,
1955 },
1956 {
1957 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1958 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1959 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
1960 .speed = SPEED_10000,
1961 },
1962 {
1963 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1964 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1965 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1966 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1967 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1968 .speed = SPEED_10000,
1969 },
1970 {
1971 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1972 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
1973 .speed = SPEED_20000,
1974 },
1975 {
1976 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1977 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1978 .speed = SPEED_40000,
1979 },
1980 {
1981 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1982 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1983 .speed = SPEED_40000,
1984 },
1985 {
1986 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1987 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1988 .speed = SPEED_40000,
1989 },
1990 {
1991 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1992 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1993 .speed = SPEED_40000,
1994 },
1995 {
1996 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
1997 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1998 .speed = SPEED_25000,
1999 },
2000 {
2001 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2002 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2003 .speed = SPEED_25000,
2004 },
2005 {
2006 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2007 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2008 .speed = SPEED_25000,
2009 },
2010 {
2011 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2012 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2013 .speed = SPEED_25000,
2014 },
2015 {
2016 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2017 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2018 .speed = SPEED_50000,
2019 },
2020 {
2021 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2022 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2023 .speed = SPEED_50000,
2024 },
2025 {
2026 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2027 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2028 .speed = SPEED_50000,
2029 },
2030 {
2031 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2032 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2033 .speed = SPEED_56000,
2034 },
2035 {
2036 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2037 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2038 .speed = SPEED_56000,
2039 },
2040 {
2041 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2042 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2043 .speed = SPEED_56000,
2044 },
2045 {
2046 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2047 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2048 .speed = SPEED_56000,
2049 },
2050 {
2051 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2052 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2053 .speed = SPEED_100000,
2054 },
2055 {
2056 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2057 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2058 .speed = SPEED_100000,
2059 },
2060 {
2061 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2062 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2063 .speed = SPEED_100000,
2064 },
2065 {
2066 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2067 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2068 .speed = SPEED_100000,
2069 },
2070 };
2071
2072 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2073
2074 static void
2075 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2076 struct ethtool_link_ksettings *cmd)
2077 {
2078 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2079 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2080 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2081 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2082 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2083 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2084 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2085
2086 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2087 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2088 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2089 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2090 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2091 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2092 }
2093
2094 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
2095 {
2096 int i;
2097
2098 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2099 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
2100 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2101 mode);
2102 }
2103 }
2104
2105 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
2106 struct ethtool_link_ksettings *cmd)
2107 {
2108 u32 speed = SPEED_UNKNOWN;
2109 u8 duplex = DUPLEX_UNKNOWN;
2110 int i;
2111
2112 if (!carrier_ok)
2113 goto out;
2114
2115 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2116 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2117 speed = mlxsw_sp_port_link_mode[i].speed;
2118 duplex = DUPLEX_FULL;
2119 break;
2120 }
2121 }
2122 out:
2123 cmd->base.speed = speed;
2124 cmd->base.duplex = duplex;
2125 }
2126
2127 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2128 {
2129 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2130 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2131 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2132 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2133 return PORT_FIBRE;
2134
2135 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2136 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2137 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2138 return PORT_DA;
2139
2140 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2141 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2142 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2143 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2144 return PORT_NONE;
2145
2146 return PORT_OTHER;
2147 }
2148
2149 static u32
2150 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
2151 {
2152 u32 ptys_proto = 0;
2153 int i;
2154
2155 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2156 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2157 cmd->link_modes.advertising))
2158 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2159 }
2160 return ptys_proto;
2161 }
2162
2163 static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2164 {
2165 u32 ptys_proto = 0;
2166 int i;
2167
2168 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2169 if (speed == mlxsw_sp_port_link_mode[i].speed)
2170 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2171 }
2172 return ptys_proto;
2173 }
2174
2175 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2176 {
2177 u32 ptys_proto = 0;
2178 int i;
2179
2180 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2181 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2182 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2183 }
2184 return ptys_proto;
2185 }
2186
2187 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2188 struct ethtool_link_ksettings *cmd)
2189 {
2190 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2191 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2192 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2193
2194 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2195 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2196 }
2197
2198 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2199 struct ethtool_link_ksettings *cmd)
2200 {
2201 if (!autoneg)
2202 return;
2203
2204 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2205 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2206 }
2207
2208 static void
2209 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2210 struct ethtool_link_ksettings *cmd)
2211 {
2212 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2213 return;
2214
2215 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2216 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2217 }
2218
2219 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2220 struct ethtool_link_ksettings *cmd)
2221 {
2222 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2223 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2224 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2225 char ptys_pl[MLXSW_REG_PTYS_LEN];
2226 u8 autoneg_status;
2227 bool autoneg;
2228 int err;
2229
2230 autoneg = mlxsw_sp_port->link.autoneg;
2231 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
2232 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2233 if (err)
2234 return err;
2235 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2236 &eth_proto_oper);
2237
2238 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2239
2240 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2241
2242 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2243 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2244 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2245
2246 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2247 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2248 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2249 cmd);
2250
2251 return 0;
2252 }
2253
2254 static int
2255 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2256 const struct ethtool_link_ksettings *cmd)
2257 {
2258 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2259 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2260 char ptys_pl[MLXSW_REG_PTYS_LEN];
2261 u32 eth_proto_cap, eth_proto_new;
2262 bool autoneg;
2263 int err;
2264
2265 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
2266 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2267 if (err)
2268 return err;
2269 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
2270
2271 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2272 eth_proto_new = autoneg ?
2273 mlxsw_sp_to_ptys_advert_link(cmd) :
2274 mlxsw_sp_to_ptys_speed(cmd->base.speed);
2275
2276 eth_proto_new = eth_proto_new & eth_proto_cap;
2277 if (!eth_proto_new) {
2278 netdev_err(dev, "No supported speed requested\n");
2279 return -EINVAL;
2280 }
2281
2282 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2283 eth_proto_new);
2284 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2285 if (err)
2286 return err;
2287
2288 if (!netif_running(dev))
2289 return 0;
2290
2291 mlxsw_sp_port->link.autoneg = autoneg;
2292
2293 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2294 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
2295
2296 return 0;
2297 }
2298
2299 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2300 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2301 .get_link = ethtool_op_get_link,
2302 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2303 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
2304 .get_strings = mlxsw_sp_port_get_strings,
2305 .set_phys_id = mlxsw_sp_port_set_phys_id,
2306 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2307 .get_sset_count = mlxsw_sp_port_get_sset_count,
2308 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2309 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
2310 };
2311
2312 static int
2313 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2314 {
2315 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2316 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2317 char ptys_pl[MLXSW_REG_PTYS_LEN];
2318 u32 eth_proto_admin;
2319
2320 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
2321 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2322 eth_proto_admin);
2323 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2324 }
2325
2326 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2327 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2328 bool dwrr, u8 dwrr_weight)
2329 {
2330 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2331 char qeec_pl[MLXSW_REG_QEEC_LEN];
2332
2333 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2334 next_index);
2335 mlxsw_reg_qeec_de_set(qeec_pl, true);
2336 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2337 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2338 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2339 }
2340
2341 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2342 enum mlxsw_reg_qeec_hr hr, u8 index,
2343 u8 next_index, u32 maxrate)
2344 {
2345 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2346 char qeec_pl[MLXSW_REG_QEEC_LEN];
2347
2348 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2349 next_index);
2350 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2351 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2352 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2353 }
2354
2355 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2356 u8 switch_prio, u8 tclass)
2357 {
2358 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2359 char qtct_pl[MLXSW_REG_QTCT_LEN];
2360
2361 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2362 tclass);
2363 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2364 }
2365
2366 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2367 {
2368 int err, i;
2369
2370 /* Setup the elements hierarcy, so that each TC is linked to
2371 * one subgroup, which are all member in the same group.
2372 */
2373 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2374 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2375 0);
2376 if (err)
2377 return err;
2378 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2379 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2380 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2381 0, false, 0);
2382 if (err)
2383 return err;
2384 }
2385 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2386 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2387 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2388 false, 0);
2389 if (err)
2390 return err;
2391 }
2392
2393 /* Make sure the max shaper is disabled in all hierarcies that
2394 * support it.
2395 */
2396 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2397 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2398 MLXSW_REG_QEEC_MAS_DIS);
2399 if (err)
2400 return err;
2401 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2402 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2403 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2404 i, 0,
2405 MLXSW_REG_QEEC_MAS_DIS);
2406 if (err)
2407 return err;
2408 }
2409 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2410 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2411 MLXSW_REG_QEEC_HIERARCY_TC,
2412 i, i,
2413 MLXSW_REG_QEEC_MAS_DIS);
2414 if (err)
2415 return err;
2416 }
2417
2418 /* Map all priorities to traffic class 0. */
2419 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2420 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2421 if (err)
2422 return err;
2423 }
2424
2425 return 0;
2426 }
2427
2428 static int mlxsw_sp_port_pvid_vport_create(struct mlxsw_sp_port *mlxsw_sp_port)
2429 {
2430 mlxsw_sp_port->pvid = 1;
2431
2432 return mlxsw_sp_port_add_vid(mlxsw_sp_port->dev, 0, 1);
2433 }
2434
2435 static int mlxsw_sp_port_pvid_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_port)
2436 {
2437 return mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
2438 }
2439
2440 static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2441 bool split, u8 module, u8 width, u8 lane)
2442 {
2443 struct mlxsw_sp_port *mlxsw_sp_port;
2444 struct net_device *dev;
2445 size_t bytes;
2446 int err;
2447
2448 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2449 if (!dev)
2450 return -ENOMEM;
2451 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
2452 mlxsw_sp_port = netdev_priv(dev);
2453 mlxsw_sp_port->dev = dev;
2454 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2455 mlxsw_sp_port->local_port = local_port;
2456 mlxsw_sp_port->split = split;
2457 mlxsw_sp_port->mapping.module = module;
2458 mlxsw_sp_port->mapping.width = width;
2459 mlxsw_sp_port->mapping.lane = lane;
2460 mlxsw_sp_port->link.autoneg = 1;
2461 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
2462 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
2463 if (!mlxsw_sp_port->active_vlans) {
2464 err = -ENOMEM;
2465 goto err_port_active_vlans_alloc;
2466 }
2467 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
2468 if (!mlxsw_sp_port->untagged_vlans) {
2469 err = -ENOMEM;
2470 goto err_port_untagged_vlans_alloc;
2471 }
2472 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
2473 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
2474
2475 mlxsw_sp_port->pcpu_stats =
2476 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2477 if (!mlxsw_sp_port->pcpu_stats) {
2478 err = -ENOMEM;
2479 goto err_alloc_stats;
2480 }
2481
2482 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2483 GFP_KERNEL);
2484 if (!mlxsw_sp_port->sample) {
2485 err = -ENOMEM;
2486 goto err_alloc_sample;
2487 }
2488
2489 mlxsw_sp_port->hw_stats.cache =
2490 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2491
2492 if (!mlxsw_sp_port->hw_stats.cache) {
2493 err = -ENOMEM;
2494 goto err_alloc_hw_stats;
2495 }
2496 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2497 &update_stats_cache);
2498
2499 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2500 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2501
2502 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2503 if (err) {
2504 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2505 mlxsw_sp_port->local_port);
2506 goto err_port_swid_set;
2507 }
2508
2509 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2510 if (err) {
2511 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2512 mlxsw_sp_port->local_port);
2513 goto err_dev_addr_init;
2514 }
2515
2516 netif_carrier_off(dev);
2517
2518 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
2519 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2520 dev->hw_features |= NETIF_F_HW_TC;
2521
2522 dev->min_mtu = 0;
2523 dev->max_mtu = ETH_MAX_MTU;
2524
2525 /* Each packet needs to have a Tx header (metadata) on top all other
2526 * headers.
2527 */
2528 dev->needed_headroom = MLXSW_TXHDR_LEN;
2529
2530 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2531 if (err) {
2532 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2533 mlxsw_sp_port->local_port);
2534 goto err_port_system_port_mapping_set;
2535 }
2536
2537 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2538 if (err) {
2539 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2540 mlxsw_sp_port->local_port);
2541 goto err_port_speed_by_width_set;
2542 }
2543
2544 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2545 if (err) {
2546 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2547 mlxsw_sp_port->local_port);
2548 goto err_port_mtu_set;
2549 }
2550
2551 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2552 if (err)
2553 goto err_port_admin_status_set;
2554
2555 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2556 if (err) {
2557 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2558 mlxsw_sp_port->local_port);
2559 goto err_port_buffers_init;
2560 }
2561
2562 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2563 if (err) {
2564 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2565 mlxsw_sp_port->local_port);
2566 goto err_port_ets_init;
2567 }
2568
2569 /* ETS and buffers must be initialized before DCB. */
2570 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2571 if (err) {
2572 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2573 mlxsw_sp_port->local_port);
2574 goto err_port_dcb_init;
2575 }
2576
2577 err = mlxsw_sp_port_pvid_vport_create(mlxsw_sp_port);
2578 if (err) {
2579 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create PVID vPort\n",
2580 mlxsw_sp_port->local_port);
2581 goto err_port_pvid_vport_create;
2582 }
2583
2584 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
2585 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
2586 err = register_netdev(dev);
2587 if (err) {
2588 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2589 mlxsw_sp_port->local_port);
2590 goto err_register_netdev;
2591 }
2592
2593 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2594 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2595 module);
2596 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
2597 return 0;
2598
2599 err_register_netdev:
2600 mlxsw_sp->ports[local_port] = NULL;
2601 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
2602 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2603 err_port_pvid_vport_create:
2604 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
2605 err_port_dcb_init:
2606 err_port_ets_init:
2607 err_port_buffers_init:
2608 err_port_admin_status_set:
2609 err_port_mtu_set:
2610 err_port_speed_by_width_set:
2611 err_port_system_port_mapping_set:
2612 err_dev_addr_init:
2613 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2614 err_port_swid_set:
2615 kfree(mlxsw_sp_port->hw_stats.cache);
2616 err_alloc_hw_stats:
2617 kfree(mlxsw_sp_port->sample);
2618 err_alloc_sample:
2619 free_percpu(mlxsw_sp_port->pcpu_stats);
2620 err_alloc_stats:
2621 kfree(mlxsw_sp_port->untagged_vlans);
2622 err_port_untagged_vlans_alloc:
2623 kfree(mlxsw_sp_port->active_vlans);
2624 err_port_active_vlans_alloc:
2625 free_netdev(dev);
2626 return err;
2627 }
2628
2629 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2630 bool split, u8 module, u8 width, u8 lane)
2631 {
2632 int err;
2633
2634 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2635 if (err) {
2636 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2637 local_port);
2638 return err;
2639 }
2640 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split,
2641 module, width, lane);
2642 if (err)
2643 goto err_port_create;
2644 return 0;
2645
2646 err_port_create:
2647 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2648 return err;
2649 }
2650
2651 static void __mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2652 {
2653 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2654
2655 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
2656 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
2657 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
2658 mlxsw_sp->ports[local_port] = NULL;
2659 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
2660 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2661 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
2662 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2663 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
2664 kfree(mlxsw_sp_port->hw_stats.cache);
2665 kfree(mlxsw_sp_port->sample);
2666 free_percpu(mlxsw_sp_port->pcpu_stats);
2667 kfree(mlxsw_sp_port->untagged_vlans);
2668 kfree(mlxsw_sp_port->active_vlans);
2669 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
2670 free_netdev(mlxsw_sp_port->dev);
2671 }
2672
2673 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2674 {
2675 __mlxsw_sp_port_remove(mlxsw_sp, local_port);
2676 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2677 }
2678
2679 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2680 {
2681 return mlxsw_sp->ports[local_port] != NULL;
2682 }
2683
2684 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2685 {
2686 int i;
2687
2688 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
2689 if (mlxsw_sp_port_created(mlxsw_sp, i))
2690 mlxsw_sp_port_remove(mlxsw_sp, i);
2691 kfree(mlxsw_sp->port_to_module);
2692 kfree(mlxsw_sp->ports);
2693 }
2694
2695 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2696 {
2697 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
2698 u8 module, width, lane;
2699 size_t alloc_size;
2700 int i;
2701 int err;
2702
2703 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
2704 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2705 if (!mlxsw_sp->ports)
2706 return -ENOMEM;
2707
2708 mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
2709 if (!mlxsw_sp->port_to_module) {
2710 err = -ENOMEM;
2711 goto err_port_to_module_alloc;
2712 }
2713
2714 for (i = 1; i < max_ports; i++) {
2715 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
2716 &width, &lane);
2717 if (err)
2718 goto err_port_module_info_get;
2719 if (!width)
2720 continue;
2721 mlxsw_sp->port_to_module[i] = module;
2722 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
2723 module, width, lane);
2724 if (err)
2725 goto err_port_create;
2726 }
2727 return 0;
2728
2729 err_port_create:
2730 err_port_module_info_get:
2731 for (i--; i >= 1; i--)
2732 if (mlxsw_sp_port_created(mlxsw_sp, i))
2733 mlxsw_sp_port_remove(mlxsw_sp, i);
2734 kfree(mlxsw_sp->port_to_module);
2735 err_port_to_module_alloc:
2736 kfree(mlxsw_sp->ports);
2737 return err;
2738 }
2739
2740 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
2741 {
2742 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
2743
2744 return local_port - offset;
2745 }
2746
2747 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
2748 u8 module, unsigned int count)
2749 {
2750 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
2751 int err, i;
2752
2753 for (i = 0; i < count; i++) {
2754 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
2755 width, i * width);
2756 if (err)
2757 goto err_port_module_map;
2758 }
2759
2760 for (i = 0; i < count; i++) {
2761 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
2762 if (err)
2763 goto err_port_swid_set;
2764 }
2765
2766 for (i = 0; i < count; i++) {
2767 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
2768 module, width, i * width);
2769 if (err)
2770 goto err_port_create;
2771 }
2772
2773 return 0;
2774
2775 err_port_create:
2776 for (i--; i >= 0; i--)
2777 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2778 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2779 i = count;
2780 err_port_swid_set:
2781 for (i--; i >= 0; i--)
2782 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
2783 MLXSW_PORT_SWID_DISABLED_PORT);
2784 i = count;
2785 err_port_module_map:
2786 for (i--; i >= 0; i--)
2787 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
2788 return err;
2789 }
2790
2791 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
2792 u8 base_port, unsigned int count)
2793 {
2794 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
2795 int i;
2796
2797 /* Split by four means we need to re-create two ports, otherwise
2798 * only one.
2799 */
2800 count = count / 2;
2801
2802 for (i = 0; i < count; i++) {
2803 local_port = base_port + i * 2;
2804 module = mlxsw_sp->port_to_module[local_port];
2805
2806 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
2807 0);
2808 }
2809
2810 for (i = 0; i < count; i++)
2811 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
2812
2813 for (i = 0; i < count; i++) {
2814 local_port = base_port + i * 2;
2815 module = mlxsw_sp->port_to_module[local_port];
2816
2817 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
2818 width, 0);
2819 }
2820 }
2821
2822 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
2823 unsigned int count)
2824 {
2825 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2826 struct mlxsw_sp_port *mlxsw_sp_port;
2827 u8 module, cur_width, base_port;
2828 int i;
2829 int err;
2830
2831 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2832 if (!mlxsw_sp_port) {
2833 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2834 local_port);
2835 return -EINVAL;
2836 }
2837
2838 module = mlxsw_sp_port->mapping.module;
2839 cur_width = mlxsw_sp_port->mapping.width;
2840
2841 if (count != 2 && count != 4) {
2842 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2843 return -EINVAL;
2844 }
2845
2846 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2847 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2848 return -EINVAL;
2849 }
2850
2851 /* Make sure we have enough slave (even) ports for the split. */
2852 if (count == 2) {
2853 base_port = local_port;
2854 if (mlxsw_sp->ports[base_port + 1]) {
2855 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2856 return -EINVAL;
2857 }
2858 } else {
2859 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2860 if (mlxsw_sp->ports[base_port + 1] ||
2861 mlxsw_sp->ports[base_port + 3]) {
2862 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2863 return -EINVAL;
2864 }
2865 }
2866
2867 for (i = 0; i < count; i++)
2868 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2869 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2870
2871 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2872 if (err) {
2873 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2874 goto err_port_split_create;
2875 }
2876
2877 return 0;
2878
2879 err_port_split_create:
2880 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
2881 return err;
2882 }
2883
2884 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
2885 {
2886 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2887 struct mlxsw_sp_port *mlxsw_sp_port;
2888 u8 cur_width, base_port;
2889 unsigned int count;
2890 int i;
2891
2892 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2893 if (!mlxsw_sp_port) {
2894 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2895 local_port);
2896 return -EINVAL;
2897 }
2898
2899 if (!mlxsw_sp_port->split) {
2900 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2901 return -EINVAL;
2902 }
2903
2904 cur_width = mlxsw_sp_port->mapping.width;
2905 count = cur_width == 1 ? 4 : 2;
2906
2907 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2908
2909 /* Determine which ports to remove. */
2910 if (count == 2 && local_port >= base_port + 2)
2911 base_port = base_port + 2;
2912
2913 for (i = 0; i < count; i++)
2914 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2915 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2916
2917 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
2918
2919 return 0;
2920 }
2921
2922 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2923 char *pude_pl, void *priv)
2924 {
2925 struct mlxsw_sp *mlxsw_sp = priv;
2926 struct mlxsw_sp_port *mlxsw_sp_port;
2927 enum mlxsw_reg_pude_oper_status status;
2928 u8 local_port;
2929
2930 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2931 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2932 if (!mlxsw_sp_port)
2933 return;
2934
2935 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2936 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2937 netdev_info(mlxsw_sp_port->dev, "link up\n");
2938 netif_carrier_on(mlxsw_sp_port->dev);
2939 } else {
2940 netdev_info(mlxsw_sp_port->dev, "link down\n");
2941 netif_carrier_off(mlxsw_sp_port->dev);
2942 }
2943 }
2944
2945 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
2946 u8 local_port, void *priv)
2947 {
2948 struct mlxsw_sp *mlxsw_sp = priv;
2949 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2950 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2951
2952 if (unlikely(!mlxsw_sp_port)) {
2953 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2954 local_port);
2955 return;
2956 }
2957
2958 skb->dev = mlxsw_sp_port->dev;
2959
2960 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2961 u64_stats_update_begin(&pcpu_stats->syncp);
2962 pcpu_stats->rx_packets++;
2963 pcpu_stats->rx_bytes += skb->len;
2964 u64_stats_update_end(&pcpu_stats->syncp);
2965
2966 skb->protocol = eth_type_trans(skb, skb->dev);
2967 netif_receive_skb(skb);
2968 }
2969
2970 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
2971 void *priv)
2972 {
2973 skb->offload_fwd_mark = 1;
2974 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
2975 }
2976
2977 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
2978 void *priv)
2979 {
2980 struct mlxsw_sp *mlxsw_sp = priv;
2981 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2982 struct psample_group *psample_group;
2983 u32 size;
2984
2985 if (unlikely(!mlxsw_sp_port)) {
2986 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
2987 local_port);
2988 goto out;
2989 }
2990 if (unlikely(!mlxsw_sp_port->sample)) {
2991 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
2992 local_port);
2993 goto out;
2994 }
2995
2996 size = mlxsw_sp_port->sample->truncate ?
2997 mlxsw_sp_port->sample->trunc_size : skb->len;
2998
2999 rcu_read_lock();
3000 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3001 if (!psample_group)
3002 goto out_unlock;
3003 psample_sample_packet(psample_group, skb, size,
3004 mlxsw_sp_port->dev->ifindex, 0,
3005 mlxsw_sp_port->sample->rate);
3006 out_unlock:
3007 rcu_read_unlock();
3008 out:
3009 consume_skb(skb);
3010 }
3011
3012 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3013 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
3014 _is_ctrl, SP_##_trap_group, DISCARD)
3015
3016 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3017 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
3018 _is_ctrl, SP_##_trap_group, DISCARD)
3019
3020 #define MLXSW_SP_EVENTL(_func, _trap_id) \
3021 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
3022
3023 static const struct mlxsw_listener mlxsw_sp_listener[] = {
3024 /* Events */
3025 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
3026 /* L2 traps */
3027 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3028 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3029 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3030 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3031 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3032 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3033 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3034 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3035 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3036 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3037 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
3038 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
3039 /* L3 traps */
3040 MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3041 MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3042 MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3043 MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, OSPF, false),
3044 MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3045 MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3046 MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, ARP_MISS, false),
3047 MLXSW_SP_RXL_NO_MARK(BGP_IPV4, TRAP_TO_CPU, BGP_IPV4, false),
3048 /* PKT Sample trap */
3049 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
3050 false, SP_IP2ME, DISCARD)
3051 };
3052
3053 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3054 {
3055 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3056 enum mlxsw_reg_qpcr_ir_units ir_units;
3057 int max_cpu_policers;
3058 bool is_bytes;
3059 u8 burst_size;
3060 u32 rate;
3061 int i, err;
3062
3063 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3064 return -EIO;
3065
3066 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3067
3068 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3069 for (i = 0; i < max_cpu_policers; i++) {
3070 is_bytes = false;
3071 switch (i) {
3072 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3073 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3074 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3075 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3076 rate = 128;
3077 burst_size = 7;
3078 break;
3079 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3080 rate = 16 * 1024;
3081 burst_size = 10;
3082 break;
3083 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3084 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3085 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3086 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3087 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3088 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3089 rate = 1024;
3090 burst_size = 7;
3091 break;
3092 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3093 is_bytes = true;
3094 rate = 4 * 1024;
3095 burst_size = 4;
3096 break;
3097 default:
3098 continue;
3099 }
3100
3101 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3102 burst_size);
3103 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3104 if (err)
3105 return err;
3106 }
3107
3108 return 0;
3109 }
3110
3111 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
3112 {
3113 char htgt_pl[MLXSW_REG_HTGT_LEN];
3114 enum mlxsw_reg_htgt_trap_group i;
3115 int max_cpu_policers;
3116 int max_trap_groups;
3117 u8 priority, tc;
3118 u16 policer_id;
3119 int err;
3120
3121 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3122 return -EIO;
3123
3124 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
3125 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3126
3127 for (i = 0; i < max_trap_groups; i++) {
3128 policer_id = i;
3129 switch (i) {
3130 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3131 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3132 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3133 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3134 priority = 5;
3135 tc = 5;
3136 break;
3137 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3138 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3139 priority = 4;
3140 tc = 4;
3141 break;
3142 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3143 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3144 priority = 3;
3145 tc = 3;
3146 break;
3147 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3148 priority = 2;
3149 tc = 2;
3150 break;
3151 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3152 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3153 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3154 priority = 1;
3155 tc = 1;
3156 break;
3157 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
3158 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3159 tc = MLXSW_REG_HTGT_DEFAULT_TC;
3160 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
3161 break;
3162 default:
3163 continue;
3164 }
3165
3166 if (max_cpu_policers <= policer_id &&
3167 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3168 return -EIO;
3169
3170 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
3171 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3172 if (err)
3173 return err;
3174 }
3175
3176 return 0;
3177 }
3178
3179 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3180 {
3181 int i;
3182 int err;
3183
3184 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3185 if (err)
3186 return err;
3187
3188 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
3189 if (err)
3190 return err;
3191
3192 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3193 err = mlxsw_core_trap_register(mlxsw_sp->core,
3194 &mlxsw_sp_listener[i],
3195 mlxsw_sp);
3196 if (err)
3197 goto err_listener_register;
3198
3199 }
3200 return 0;
3201
3202 err_listener_register:
3203 for (i--; i >= 0; i--) {
3204 mlxsw_core_trap_unregister(mlxsw_sp->core,
3205 &mlxsw_sp_listener[i],
3206 mlxsw_sp);
3207 }
3208 return err;
3209 }
3210
3211 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3212 {
3213 int i;
3214
3215 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3216 mlxsw_core_trap_unregister(mlxsw_sp->core,
3217 &mlxsw_sp_listener[i],
3218 mlxsw_sp);
3219 }
3220 }
3221
3222 static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
3223 enum mlxsw_reg_sfgc_type type,
3224 enum mlxsw_reg_sfgc_bridge_type bridge_type)
3225 {
3226 enum mlxsw_flood_table_type table_type;
3227 enum mlxsw_sp_flood_table flood_table;
3228 char sfgc_pl[MLXSW_REG_SFGC_LEN];
3229
3230 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
3231 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
3232 else
3233 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
3234
3235 switch (type) {
3236 case MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST:
3237 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
3238 break;
3239 case MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4:
3240 flood_table = MLXSW_SP_FLOOD_TABLE_MC;
3241 break;
3242 default:
3243 flood_table = MLXSW_SP_FLOOD_TABLE_BC;
3244 }
3245
3246 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
3247 flood_table);
3248 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
3249 }
3250
3251 static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
3252 {
3253 int type, err;
3254
3255 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
3256 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
3257 continue;
3258
3259 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3260 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
3261 if (err)
3262 return err;
3263
3264 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3265 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
3266 if (err)
3267 return err;
3268 }
3269
3270 return 0;
3271 }
3272
3273 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3274 {
3275 char slcr_pl[MLXSW_REG_SLCR_LEN];
3276 int err;
3277
3278 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3279 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3280 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3281 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3282 MLXSW_REG_SLCR_LAG_HASH_SIP |
3283 MLXSW_REG_SLCR_LAG_HASH_DIP |
3284 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3285 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3286 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
3287 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3288 if (err)
3289 return err;
3290
3291 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3292 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
3293 return -EIO;
3294
3295 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
3296 sizeof(struct mlxsw_sp_upper),
3297 GFP_KERNEL);
3298 if (!mlxsw_sp->lags)
3299 return -ENOMEM;
3300
3301 return 0;
3302 }
3303
3304 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3305 {
3306 kfree(mlxsw_sp->lags);
3307 }
3308
3309 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3310 {
3311 char htgt_pl[MLXSW_REG_HTGT_LEN];
3312
3313 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3314 MLXSW_REG_HTGT_INVALID_POLICER,
3315 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3316 MLXSW_REG_HTGT_DEFAULT_TC);
3317 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3318 }
3319
3320 static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create);
3321
3322 static int mlxsw_sp_dummy_fid_init(struct mlxsw_sp *mlxsw_sp)
3323 {
3324 return mlxsw_sp_vfid_op(mlxsw_sp, MLXSW_SP_DUMMY_FID, true);
3325 }
3326
3327 static void mlxsw_sp_dummy_fid_fini(struct mlxsw_sp *mlxsw_sp)
3328 {
3329 mlxsw_sp_vfid_op(mlxsw_sp, MLXSW_SP_DUMMY_FID, false);
3330 }
3331
3332 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3333 const struct mlxsw_bus_info *mlxsw_bus_info)
3334 {
3335 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3336 int err;
3337
3338 mlxsw_sp->core = mlxsw_core;
3339 mlxsw_sp->bus_info = mlxsw_bus_info;
3340 INIT_LIST_HEAD(&mlxsw_sp->fids);
3341 INIT_LIST_HEAD(&mlxsw_sp->vfids.list);
3342
3343 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3344 if (err) {
3345 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3346 return err;
3347 }
3348
3349 err = mlxsw_sp_traps_init(mlxsw_sp);
3350 if (err) {
3351 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3352 return err;
3353 }
3354
3355 err = mlxsw_sp_flood_init(mlxsw_sp);
3356 if (err) {
3357 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
3358 goto err_flood_init;
3359 }
3360
3361 err = mlxsw_sp_buffers_init(mlxsw_sp);
3362 if (err) {
3363 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3364 goto err_buffers_init;
3365 }
3366
3367 err = mlxsw_sp_lag_init(mlxsw_sp);
3368 if (err) {
3369 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3370 goto err_lag_init;
3371 }
3372
3373 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3374 if (err) {
3375 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3376 goto err_switchdev_init;
3377 }
3378
3379 err = mlxsw_sp_router_init(mlxsw_sp);
3380 if (err) {
3381 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3382 goto err_router_init;
3383 }
3384
3385 err = mlxsw_sp_span_init(mlxsw_sp);
3386 if (err) {
3387 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3388 goto err_span_init;
3389 }
3390
3391 err = mlxsw_sp_acl_init(mlxsw_sp);
3392 if (err) {
3393 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3394 goto err_acl_init;
3395 }
3396
3397 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3398 if (err) {
3399 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3400 goto err_counter_pool_init;
3401 }
3402
3403 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3404 if (err) {
3405 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3406 goto err_dpipe_init;
3407 }
3408
3409 err = mlxsw_sp_dummy_fid_init(mlxsw_sp);
3410 if (err) {
3411 dev_err(mlxsw_sp->bus_info->dev, "Failed to init dummy FID\n");
3412 goto err_dummy_fid_init;
3413 }
3414
3415 err = mlxsw_sp_ports_create(mlxsw_sp);
3416 if (err) {
3417 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3418 goto err_ports_create;
3419 }
3420
3421 return 0;
3422
3423 err_ports_create:
3424 mlxsw_sp_dummy_fid_fini(mlxsw_sp);
3425 err_dummy_fid_init:
3426 mlxsw_sp_dpipe_fini(mlxsw_sp);
3427 err_dpipe_init:
3428 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3429 err_counter_pool_init:
3430 mlxsw_sp_acl_fini(mlxsw_sp);
3431 err_acl_init:
3432 mlxsw_sp_span_fini(mlxsw_sp);
3433 err_span_init:
3434 mlxsw_sp_router_fini(mlxsw_sp);
3435 err_router_init:
3436 mlxsw_sp_switchdev_fini(mlxsw_sp);
3437 err_switchdev_init:
3438 mlxsw_sp_lag_fini(mlxsw_sp);
3439 err_lag_init:
3440 mlxsw_sp_buffers_fini(mlxsw_sp);
3441 err_buffers_init:
3442 err_flood_init:
3443 mlxsw_sp_traps_fini(mlxsw_sp);
3444 return err;
3445 }
3446
3447 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
3448 {
3449 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3450
3451 mlxsw_sp_ports_remove(mlxsw_sp);
3452 mlxsw_sp_dummy_fid_fini(mlxsw_sp);
3453 mlxsw_sp_dpipe_fini(mlxsw_sp);
3454 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3455 mlxsw_sp_acl_fini(mlxsw_sp);
3456 mlxsw_sp_span_fini(mlxsw_sp);
3457 mlxsw_sp_router_fini(mlxsw_sp);
3458 mlxsw_sp_switchdev_fini(mlxsw_sp);
3459 mlxsw_sp_lag_fini(mlxsw_sp);
3460 mlxsw_sp_buffers_fini(mlxsw_sp);
3461 mlxsw_sp_traps_fini(mlxsw_sp);
3462 WARN_ON(!list_empty(&mlxsw_sp->vfids.list));
3463 WARN_ON(!list_empty(&mlxsw_sp->fids));
3464 }
3465
3466 static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3467 .used_max_vepa_channels = 1,
3468 .max_vepa_channels = 0,
3469 .used_max_mid = 1,
3470 .max_mid = MLXSW_SP_MID_MAX,
3471 .used_max_pgt = 1,
3472 .max_pgt = 0,
3473 .used_flood_tables = 1,
3474 .used_flood_mode = 1,
3475 .flood_mode = 3,
3476 .max_fid_offset_flood_tables = 3,
3477 .fid_offset_flood_table_size = VLAN_N_VID - 1,
3478 .max_fid_flood_tables = 3,
3479 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
3480 .used_max_ib_mc = 1,
3481 .max_ib_mc = 0,
3482 .used_max_pkey = 1,
3483 .max_pkey = 0,
3484 .used_kvd_split_data = 1,
3485 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3486 .kvd_hash_single_parts = 2,
3487 .kvd_hash_double_parts = 1,
3488 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
3489 .swid_config = {
3490 {
3491 .used_type = 1,
3492 .type = MLXSW_PORT_SWID_TYPE_ETH,
3493 }
3494 },
3495 .resource_query_enable = 1,
3496 };
3497
3498 static struct mlxsw_driver mlxsw_sp_driver = {
3499 .kind = mlxsw_sp_driver_name,
3500 .priv_size = sizeof(struct mlxsw_sp),
3501 .init = mlxsw_sp_init,
3502 .fini = mlxsw_sp_fini,
3503 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
3504 .port_split = mlxsw_sp_port_split,
3505 .port_unsplit = mlxsw_sp_port_unsplit,
3506 .sb_pool_get = mlxsw_sp_sb_pool_get,
3507 .sb_pool_set = mlxsw_sp_sb_pool_set,
3508 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3509 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3510 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3511 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3512 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3513 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3514 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3515 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3516 .txhdr_construct = mlxsw_sp_txhdr_construct,
3517 .txhdr_len = MLXSW_TXHDR_LEN,
3518 .profile = &mlxsw_sp_config_profile,
3519 };
3520
3521 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
3522 {
3523 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3524 }
3525
3526 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
3527 {
3528 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
3529 int ret = 0;
3530
3531 if (mlxsw_sp_port_dev_check(lower_dev)) {
3532 *p_mlxsw_sp_port = netdev_priv(lower_dev);
3533 ret = 1;
3534 }
3535
3536 return ret;
3537 }
3538
3539 static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
3540 {
3541 struct mlxsw_sp_port *mlxsw_sp_port;
3542
3543 if (mlxsw_sp_port_dev_check(dev))
3544 return netdev_priv(dev);
3545
3546 mlxsw_sp_port = NULL;
3547 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
3548
3549 return mlxsw_sp_port;
3550 }
3551
3552 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
3553 {
3554 struct mlxsw_sp_port *mlxsw_sp_port;
3555
3556 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3557 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3558 }
3559
3560 static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3561 {
3562 struct mlxsw_sp_port *mlxsw_sp_port;
3563
3564 if (mlxsw_sp_port_dev_check(dev))
3565 return netdev_priv(dev);
3566
3567 mlxsw_sp_port = NULL;
3568 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3569 &mlxsw_sp_port);
3570
3571 return mlxsw_sp_port;
3572 }
3573
3574 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3575 {
3576 struct mlxsw_sp_port *mlxsw_sp_port;
3577
3578 rcu_read_lock();
3579 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3580 if (mlxsw_sp_port)
3581 dev_hold(mlxsw_sp_port->dev);
3582 rcu_read_unlock();
3583 return mlxsw_sp_port;
3584 }
3585
3586 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3587 {
3588 dev_put(mlxsw_sp_port->dev);
3589 }
3590
3591 static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
3592 u16 fid)
3593 {
3594 if (mlxsw_sp_fid_is_vfid(fid))
3595 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
3596 else
3597 return test_bit(fid, lag_port->active_vlans);
3598 }
3599
3600 static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
3601 u16 fid)
3602 {
3603 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3604 u8 local_port = mlxsw_sp_port->local_port;
3605 u16 lag_id = mlxsw_sp_port->lag_id;
3606 u64 max_lag_members;
3607 int i, count = 0;
3608
3609 if (!mlxsw_sp_port->lagged)
3610 return true;
3611
3612 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3613 MAX_LAG_MEMBERS);
3614 for (i = 0; i < max_lag_members; i++) {
3615 struct mlxsw_sp_port *lag_port;
3616
3617 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
3618 if (!lag_port || lag_port->local_port == local_port)
3619 continue;
3620 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
3621 count++;
3622 }
3623
3624 return !count;
3625 }
3626
3627 static int
3628 mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3629 u16 fid)
3630 {
3631 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3632 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3633
3634 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
3635 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3636 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
3637 mlxsw_sp_port->local_port);
3638
3639 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
3640 mlxsw_sp_port->local_port, fid);
3641
3642 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3643 }
3644
3645 static int
3646 mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3647 u16 fid)
3648 {
3649 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3650 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3651
3652 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
3653 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3654 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
3655
3656 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
3657 mlxsw_sp_port->lag_id, fid);
3658
3659 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3660 }
3661
3662 int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
3663 {
3664 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
3665 return 0;
3666
3667 if (mlxsw_sp_port->lagged)
3668 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
3669 fid);
3670 else
3671 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
3672 }
3673
3674 static void mlxsw_sp_master_bridge_gone_sync(struct mlxsw_sp *mlxsw_sp)
3675 {
3676 struct mlxsw_sp_fid *f, *tmp;
3677
3678 list_for_each_entry_safe(f, tmp, &mlxsw_sp->fids, list)
3679 if (--f->ref_count == 0)
3680 mlxsw_sp_fid_destroy(mlxsw_sp, f);
3681 else
3682 WARN_ON_ONCE(1);
3683 }
3684
3685 static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
3686 struct net_device *br_dev)
3687 {
3688 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
3689
3690 return !master_bridge->dev || master_bridge->dev == br_dev;
3691 }
3692
3693 static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
3694 struct net_device *br_dev)
3695 {
3696 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
3697
3698 master_bridge->dev = br_dev;
3699 master_bridge->ref_count++;
3700 }
3701
3702 static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
3703 {
3704 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
3705
3706 if (--master_bridge->ref_count == 0) {
3707 master_bridge->dev = NULL;
3708 /* It's possible upper VLAN devices are still holding
3709 * references to underlying FIDs. Drop the reference
3710 * and release the resources if it was the last one.
3711 * If it wasn't, then something bad happened.
3712 */
3713 mlxsw_sp_master_bridge_gone_sync(mlxsw_sp);
3714 }
3715 }
3716
3717 static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
3718 struct net_device *br_dev)
3719 {
3720 struct net_device *dev = mlxsw_sp_port->dev;
3721 int err;
3722
3723 /* When port is not bridged untagged packets are tagged with
3724 * PVID=VID=1, thereby creating an implicit VLAN interface in
3725 * the device. Remove it and let bridge code take care of its
3726 * own VLANs.
3727 */
3728 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
3729 if (err)
3730 return err;
3731
3732 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
3733
3734 mlxsw_sp_port->learning = 1;
3735 mlxsw_sp_port->learning_sync = 1;
3736 mlxsw_sp_port->uc_flood = 1;
3737 mlxsw_sp_port->mc_flood = 1;
3738 mlxsw_sp_port->mc_router = 0;
3739 mlxsw_sp_port->mc_disabled = 1;
3740 mlxsw_sp_port->bridged = 1;
3741
3742 return 0;
3743 }
3744
3745 static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
3746 {
3747 struct net_device *dev = mlxsw_sp_port->dev;
3748
3749 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
3750
3751 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
3752
3753 mlxsw_sp_port->learning = 0;
3754 mlxsw_sp_port->learning_sync = 0;
3755 mlxsw_sp_port->uc_flood = 0;
3756 mlxsw_sp_port->mc_flood = 0;
3757 mlxsw_sp_port->mc_router = 0;
3758 mlxsw_sp_port->bridged = 0;
3759
3760 /* Add implicit VLAN interface in the device, so that untagged
3761 * packets will be classified to the default vFID.
3762 */
3763 mlxsw_sp_port_add_vid(dev, 0, 1);
3764 }
3765
3766 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3767 {
3768 char sldr_pl[MLXSW_REG_SLDR_LEN];
3769
3770 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3771 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3772 }
3773
3774 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3775 {
3776 char sldr_pl[MLXSW_REG_SLDR_LEN];
3777
3778 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3779 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3780 }
3781
3782 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3783 u16 lag_id, u8 port_index)
3784 {
3785 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3786 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3787
3788 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3789 lag_id, port_index);
3790 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3791 }
3792
3793 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3794 u16 lag_id)
3795 {
3796 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3797 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3798
3799 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3800 lag_id);
3801 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3802 }
3803
3804 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3805 u16 lag_id)
3806 {
3807 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3808 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3809
3810 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3811 lag_id);
3812 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3813 }
3814
3815 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
3816 u16 lag_id)
3817 {
3818 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3819 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3820
3821 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
3822 lag_id);
3823 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3824 }
3825
3826 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3827 struct net_device *lag_dev,
3828 u16 *p_lag_id)
3829 {
3830 struct mlxsw_sp_upper *lag;
3831 int free_lag_id = -1;
3832 u64 max_lag;
3833 int i;
3834
3835 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
3836 for (i = 0; i < max_lag; i++) {
3837 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
3838 if (lag->ref_count) {
3839 if (lag->dev == lag_dev) {
3840 *p_lag_id = i;
3841 return 0;
3842 }
3843 } else if (free_lag_id < 0) {
3844 free_lag_id = i;
3845 }
3846 }
3847 if (free_lag_id < 0)
3848 return -EBUSY;
3849 *p_lag_id = free_lag_id;
3850 return 0;
3851 }
3852
3853 static bool
3854 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
3855 struct net_device *lag_dev,
3856 struct netdev_lag_upper_info *lag_upper_info)
3857 {
3858 u16 lag_id;
3859
3860 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
3861 return false;
3862 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
3863 return false;
3864 return true;
3865 }
3866
3867 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3868 u16 lag_id, u8 *p_port_index)
3869 {
3870 u64 max_lag_members;
3871 int i;
3872
3873 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3874 MAX_LAG_MEMBERS);
3875 for (i = 0; i < max_lag_members; i++) {
3876 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
3877 *p_port_index = i;
3878 return 0;
3879 }
3880 }
3881 return -EBUSY;
3882 }
3883
3884 static void
3885 mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
3886 struct net_device *lag_dev, u16 lag_id)
3887 {
3888 struct mlxsw_sp_port *mlxsw_sp_vport;
3889 struct mlxsw_sp_fid *f;
3890
3891 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
3892 if (WARN_ON(!mlxsw_sp_vport))
3893 return;
3894
3895 /* If vPort is assigned a RIF, then leave it since it's no
3896 * longer valid.
3897 */
3898 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3899 if (f)
3900 f->leave(mlxsw_sp_vport);
3901
3902 mlxsw_sp_vport->lag_id = lag_id;
3903 mlxsw_sp_vport->lagged = 1;
3904 mlxsw_sp_vport->dev = lag_dev;
3905 }
3906
3907 static void
3908 mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
3909 {
3910 struct mlxsw_sp_port *mlxsw_sp_vport;
3911 struct mlxsw_sp_fid *f;
3912
3913 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
3914 if (WARN_ON(!mlxsw_sp_vport))
3915 return;
3916
3917 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3918 if (f)
3919 f->leave(mlxsw_sp_vport);
3920
3921 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
3922 mlxsw_sp_vport->lagged = 0;
3923 }
3924
3925 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
3926 struct net_device *lag_dev)
3927 {
3928 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3929 struct mlxsw_sp_upper *lag;
3930 u16 lag_id;
3931 u8 port_index;
3932 int err;
3933
3934 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
3935 if (err)
3936 return err;
3937 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3938 if (!lag->ref_count) {
3939 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
3940 if (err)
3941 return err;
3942 lag->dev = lag_dev;
3943 }
3944
3945 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
3946 if (err)
3947 return err;
3948 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
3949 if (err)
3950 goto err_col_port_add;
3951 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
3952 if (err)
3953 goto err_col_port_enable;
3954
3955 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
3956 mlxsw_sp_port->local_port);
3957 mlxsw_sp_port->lag_id = lag_id;
3958 mlxsw_sp_port->lagged = 1;
3959 lag->ref_count++;
3960
3961 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_dev, lag_id);
3962
3963 return 0;
3964
3965 err_col_port_enable:
3966 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
3967 err_col_port_add:
3968 if (!lag->ref_count)
3969 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
3970 return err;
3971 }
3972
3973 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
3974 struct net_device *lag_dev)
3975 {
3976 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3977 u16 lag_id = mlxsw_sp_port->lag_id;
3978 struct mlxsw_sp_upper *lag;
3979
3980 if (!mlxsw_sp_port->lagged)
3981 return;
3982 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3983 WARN_ON(lag->ref_count == 0);
3984
3985 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
3986 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
3987
3988 if (mlxsw_sp_port->bridged) {
3989 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
3990 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
3991 }
3992
3993 if (lag->ref_count == 1)
3994 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
3995
3996 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
3997 mlxsw_sp_port->local_port);
3998 mlxsw_sp_port->lagged = 0;
3999 lag->ref_count--;
4000
4001 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
4002 }
4003
4004 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4005 u16 lag_id)
4006 {
4007 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4008 char sldr_pl[MLXSW_REG_SLDR_LEN];
4009
4010 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4011 mlxsw_sp_port->local_port);
4012 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4013 }
4014
4015 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4016 u16 lag_id)
4017 {
4018 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4019 char sldr_pl[MLXSW_REG_SLDR_LEN];
4020
4021 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4022 mlxsw_sp_port->local_port);
4023 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4024 }
4025
4026 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4027 bool lag_tx_enabled)
4028 {
4029 if (lag_tx_enabled)
4030 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4031 mlxsw_sp_port->lag_id);
4032 else
4033 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4034 mlxsw_sp_port->lag_id);
4035 }
4036
4037 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4038 struct netdev_lag_lower_state_info *info)
4039 {
4040 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4041 }
4042
4043 static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
4044 struct net_device *vlan_dev)
4045 {
4046 struct mlxsw_sp_port *mlxsw_sp_vport;
4047 u16 vid = vlan_dev_vlan_id(vlan_dev);
4048
4049 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
4050 if (WARN_ON(!mlxsw_sp_vport))
4051 return -EINVAL;
4052
4053 mlxsw_sp_vport->dev = vlan_dev;
4054
4055 return 0;
4056 }
4057
4058 static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
4059 struct net_device *vlan_dev)
4060 {
4061 struct mlxsw_sp_port *mlxsw_sp_vport;
4062 u16 vid = vlan_dev_vlan_id(vlan_dev);
4063
4064 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
4065 if (WARN_ON(!mlxsw_sp_vport))
4066 return;
4067
4068 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
4069 }
4070
4071 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4072 bool enable)
4073 {
4074 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4075 enum mlxsw_reg_spms_state spms_state;
4076 char *spms_pl;
4077 u16 vid;
4078 int err;
4079
4080 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4081 MLXSW_REG_SPMS_STATE_DISCARDING;
4082
4083 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4084 if (!spms_pl)
4085 return -ENOMEM;
4086 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4087
4088 for (vid = 0; vid < VLAN_N_VID; vid++)
4089 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4090
4091 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4092 kfree(spms_pl);
4093 return err;
4094 }
4095
4096 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4097 {
4098 int err;
4099
4100 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4101 if (err)
4102 return err;
4103 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4104 true, false);
4105 if (err)
4106 goto err_port_vlan_set;
4107 return 0;
4108
4109 err_port_vlan_set:
4110 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4111 return err;
4112 }
4113
4114 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4115 {
4116 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4117 false, false);
4118 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4119 }
4120
4121 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
4122 unsigned long event, void *ptr)
4123 {
4124 struct netdev_notifier_changeupper_info *info;
4125 struct mlxsw_sp_port *mlxsw_sp_port;
4126 struct net_device *upper_dev;
4127 struct mlxsw_sp *mlxsw_sp;
4128 int err = 0;
4129
4130 mlxsw_sp_port = netdev_priv(dev);
4131 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4132 info = ptr;
4133
4134 switch (event) {
4135 case NETDEV_PRECHANGEUPPER:
4136 upper_dev = info->upper_dev;
4137 if (!is_vlan_dev(upper_dev) &&
4138 !netif_is_lag_master(upper_dev) &&
4139 !netif_is_bridge_master(upper_dev) &&
4140 !netif_is_ovs_master(upper_dev))
4141 return -EINVAL;
4142 if (!info->linking)
4143 break;
4144 /* HW limitation forbids to put ports to multiple bridges. */
4145 if (netif_is_bridge_master(upper_dev) &&
4146 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
4147 return -EINVAL;
4148 if (netif_is_lag_master(upper_dev) &&
4149 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4150 info->upper_info))
4151 return -EINVAL;
4152 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4153 return -EINVAL;
4154 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4155 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4156 return -EINVAL;
4157 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev))
4158 return -EINVAL;
4159 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev))
4160 return -EINVAL;
4161 break;
4162 case NETDEV_CHANGEUPPER:
4163 upper_dev = info->upper_dev;
4164 if (is_vlan_dev(upper_dev)) {
4165 if (info->linking)
4166 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
4167 upper_dev);
4168 else
4169 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
4170 upper_dev);
4171 } else if (netif_is_bridge_master(upper_dev)) {
4172 if (info->linking)
4173 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4174 upper_dev);
4175 else
4176 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
4177 } else if (netif_is_lag_master(upper_dev)) {
4178 if (info->linking)
4179 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4180 upper_dev);
4181 else
4182 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4183 upper_dev);
4184 } else if (netif_is_ovs_master(upper_dev)) {
4185 if (info->linking)
4186 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4187 else
4188 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
4189 } else {
4190 err = -EINVAL;
4191 WARN_ON(1);
4192 }
4193 break;
4194 }
4195
4196 return err;
4197 }
4198
4199 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4200 unsigned long event, void *ptr)
4201 {
4202 struct netdev_notifier_changelowerstate_info *info;
4203 struct mlxsw_sp_port *mlxsw_sp_port;
4204 int err;
4205
4206 mlxsw_sp_port = netdev_priv(dev);
4207 info = ptr;
4208
4209 switch (event) {
4210 case NETDEV_CHANGELOWERSTATE:
4211 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4212 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4213 info->lower_state_info);
4214 if (err)
4215 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4216 }
4217 break;
4218 }
4219
4220 return 0;
4221 }
4222
4223 static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
4224 unsigned long event, void *ptr)
4225 {
4226 switch (event) {
4227 case NETDEV_PRECHANGEUPPER:
4228 case NETDEV_CHANGEUPPER:
4229 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
4230 case NETDEV_CHANGELOWERSTATE:
4231 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
4232 }
4233
4234 return 0;
4235 }
4236
4237 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4238 unsigned long event, void *ptr)
4239 {
4240 struct net_device *dev;
4241 struct list_head *iter;
4242 int ret;
4243
4244 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4245 if (mlxsw_sp_port_dev_check(dev)) {
4246 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4247 if (ret)
4248 return ret;
4249 }
4250 }
4251
4252 return 0;
4253 }
4254
4255 static int mlxsw_sp_master_bridge_vlan_link(struct mlxsw_sp *mlxsw_sp,
4256 struct net_device *vlan_dev)
4257 {
4258 u16 fid = vlan_dev_vlan_id(vlan_dev);
4259 struct mlxsw_sp_fid *f;
4260
4261 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4262 if (!f) {
4263 f = mlxsw_sp_fid_create(mlxsw_sp, fid);
4264 if (IS_ERR(f))
4265 return PTR_ERR(f);
4266 }
4267
4268 f->ref_count++;
4269
4270 return 0;
4271 }
4272
4273 static void mlxsw_sp_master_bridge_vlan_unlink(struct mlxsw_sp *mlxsw_sp,
4274 struct net_device *vlan_dev)
4275 {
4276 u16 fid = vlan_dev_vlan_id(vlan_dev);
4277 struct mlxsw_sp_fid *f;
4278
4279 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4280 if (f && f->rif)
4281 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->rif);
4282 if (f && --f->ref_count == 0)
4283 mlxsw_sp_fid_destroy(mlxsw_sp, f);
4284 }
4285
4286 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4287 unsigned long event, void *ptr)
4288 {
4289 struct netdev_notifier_changeupper_info *info;
4290 struct net_device *upper_dev;
4291 struct mlxsw_sp *mlxsw_sp;
4292 int err = 0;
4293
4294 mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4295 if (!mlxsw_sp)
4296 return 0;
4297
4298 info = ptr;
4299
4300 switch (event) {
4301 case NETDEV_PRECHANGEUPPER:
4302 upper_dev = info->upper_dev;
4303 if (!is_vlan_dev(upper_dev))
4304 return -EINVAL;
4305 if (is_vlan_dev(upper_dev) &&
4306 br_dev != mlxsw_sp_master_bridge(mlxsw_sp)->dev)
4307 return -EINVAL;
4308 break;
4309 case NETDEV_CHANGEUPPER:
4310 upper_dev = info->upper_dev;
4311 if (is_vlan_dev(upper_dev)) {
4312 if (info->linking)
4313 err = mlxsw_sp_master_bridge_vlan_link(mlxsw_sp,
4314 upper_dev);
4315 else
4316 mlxsw_sp_master_bridge_vlan_unlink(mlxsw_sp,
4317 upper_dev);
4318 } else {
4319 err = -EINVAL;
4320 WARN_ON(1);
4321 }
4322 break;
4323 }
4324
4325 return err;
4326 }
4327
4328 static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
4329 {
4330 return find_first_zero_bit(mlxsw_sp->vfids.mapped,
4331 MLXSW_SP_VFID_MAX);
4332 }
4333
4334 static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
4335 {
4336 char sfmr_pl[MLXSW_REG_SFMR_LEN];
4337
4338 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
4339 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
4340 }
4341
4342 static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
4343
4344 static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
4345 struct net_device *br_dev)
4346 {
4347 struct device *dev = mlxsw_sp->bus_info->dev;
4348 struct mlxsw_sp_fid *f;
4349 u16 vfid, fid;
4350 int err;
4351
4352 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
4353 if (vfid == MLXSW_SP_VFID_MAX) {
4354 dev_err(dev, "No available vFIDs\n");
4355 return ERR_PTR(-ERANGE);
4356 }
4357
4358 fid = mlxsw_sp_vfid_to_fid(vfid);
4359 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
4360 if (err) {
4361 dev_err(dev, "Failed to create FID=%d\n", fid);
4362 return ERR_PTR(err);
4363 }
4364
4365 f = kzalloc(sizeof(*f), GFP_KERNEL);
4366 if (!f)
4367 goto err_allocate_vfid;
4368
4369 f->leave = mlxsw_sp_vport_vfid_leave;
4370 f->fid = fid;
4371 f->dev = br_dev;
4372
4373 list_add(&f->list, &mlxsw_sp->vfids.list);
4374 set_bit(vfid, mlxsw_sp->vfids.mapped);
4375
4376 return f;
4377
4378 err_allocate_vfid:
4379 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
4380 return ERR_PTR(-ENOMEM);
4381 }
4382
4383 static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
4384 struct mlxsw_sp_fid *f)
4385 {
4386 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
4387 u16 fid = f->fid;
4388
4389 clear_bit(vfid, mlxsw_sp->vfids.mapped);
4390 list_del(&f->list);
4391
4392 if (f->rif)
4393 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->rif);
4394
4395 kfree(f);
4396
4397 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
4398 }
4399
4400 static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
4401 bool valid)
4402 {
4403 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
4404 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4405
4406 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
4407 vid);
4408 }
4409
4410 static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4411 struct net_device *br_dev)
4412 {
4413 struct mlxsw_sp_fid *f;
4414 int err;
4415
4416 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
4417 if (!f) {
4418 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
4419 if (IS_ERR(f))
4420 return PTR_ERR(f);
4421 }
4422
4423 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
4424 if (err)
4425 goto err_vport_flood_set;
4426
4427 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
4428 if (err)
4429 goto err_vport_fid_map;
4430
4431 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
4432 f->ref_count++;
4433
4434 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
4435
4436 return 0;
4437
4438 err_vport_fid_map:
4439 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4440 err_vport_flood_set:
4441 if (!f->ref_count)
4442 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
4443 return err;
4444 }
4445
4446 static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
4447 {
4448 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4449
4450 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
4451
4452 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
4453
4454 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4455
4456 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
4457
4458 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
4459 if (--f->ref_count == 0)
4460 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
4461 }
4462
4463 static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4464 struct net_device *br_dev)
4465 {
4466 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4467 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4468 struct net_device *dev = mlxsw_sp_vport->dev;
4469 int err;
4470
4471 if (f && !WARN_ON(!f->leave))
4472 f->leave(mlxsw_sp_vport);
4473
4474 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport, br_dev);
4475 if (err) {
4476 netdev_err(dev, "Failed to join vFID\n");
4477 return err;
4478 }
4479
4480 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
4481 if (err) {
4482 netdev_err(dev, "Failed to enable learning\n");
4483 goto err_port_vid_learning_set;
4484 }
4485
4486 mlxsw_sp_vport->learning = 1;
4487 mlxsw_sp_vport->learning_sync = 1;
4488 mlxsw_sp_vport->uc_flood = 1;
4489 mlxsw_sp_vport->mc_flood = 1;
4490 mlxsw_sp_vport->mc_router = 0;
4491 mlxsw_sp_vport->mc_disabled = 1;
4492 mlxsw_sp_vport->bridged = 1;
4493
4494 return 0;
4495
4496 err_port_vid_learning_set:
4497 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
4498 return err;
4499 }
4500
4501 static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
4502 {
4503 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4504
4505 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
4506
4507 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
4508
4509 mlxsw_sp_vport->learning = 0;
4510 mlxsw_sp_vport->learning_sync = 0;
4511 mlxsw_sp_vport->uc_flood = 0;
4512 mlxsw_sp_vport->mc_flood = 0;
4513 mlxsw_sp_vport->mc_router = 0;
4514 mlxsw_sp_vport->bridged = 0;
4515 }
4516
4517 static bool
4518 mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
4519 const struct net_device *br_dev)
4520 {
4521 struct mlxsw_sp_port *mlxsw_sp_vport;
4522
4523 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
4524 vport.list) {
4525 struct net_device *dev = mlxsw_sp_vport_dev_get(mlxsw_sp_vport);
4526
4527 if (dev && dev == br_dev)
4528 return false;
4529 }
4530
4531 return true;
4532 }
4533
4534 static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
4535 unsigned long event, void *ptr,
4536 u16 vid)
4537 {
4538 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4539 struct netdev_notifier_changeupper_info *info = ptr;
4540 struct mlxsw_sp_port *mlxsw_sp_vport;
4541 struct net_device *upper_dev;
4542 int err = 0;
4543
4544 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
4545 if (!mlxsw_sp_vport)
4546 return 0;
4547
4548 switch (event) {
4549 case NETDEV_PRECHANGEUPPER:
4550 upper_dev = info->upper_dev;
4551 if (!netif_is_bridge_master(upper_dev))
4552 return -EINVAL;
4553 if (!info->linking)
4554 break;
4555 /* We can't have multiple VLAN interfaces configured on
4556 * the same port and being members in the same bridge.
4557 */
4558 if (netif_is_bridge_master(upper_dev) &&
4559 !mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
4560 upper_dev))
4561 return -EINVAL;
4562 break;
4563 case NETDEV_CHANGEUPPER:
4564 upper_dev = info->upper_dev;
4565 if (netif_is_bridge_master(upper_dev)) {
4566 if (info->linking)
4567 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
4568 upper_dev);
4569 else
4570 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
4571 } else {
4572 err = -EINVAL;
4573 WARN_ON(1);
4574 }
4575 break;
4576 }
4577
4578 return err;
4579 }
4580
4581 static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
4582 unsigned long event, void *ptr,
4583 u16 vid)
4584 {
4585 struct net_device *dev;
4586 struct list_head *iter;
4587 int ret;
4588
4589 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4590 if (mlxsw_sp_port_dev_check(dev)) {
4591 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
4592 vid);
4593 if (ret)
4594 return ret;
4595 }
4596 }
4597
4598 return 0;
4599 }
4600
4601 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4602 unsigned long event, void *ptr)
4603 {
4604 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4605 u16 vid = vlan_dev_vlan_id(vlan_dev);
4606
4607 if (mlxsw_sp_port_dev_check(real_dev))
4608 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
4609 vid);
4610 else if (netif_is_lag_master(real_dev))
4611 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
4612 vid);
4613
4614 return 0;
4615 }
4616
4617 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4618 {
4619 struct netdev_notifier_changeupper_info *info = ptr;
4620
4621 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4622 return false;
4623 return netif_is_l3_master(info->upper_dev);
4624 }
4625
4626 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4627 unsigned long event, void *ptr)
4628 {
4629 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4630 int err = 0;
4631
4632 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4633 err = mlxsw_sp_netdevice_router_port_event(dev);
4634 else if (mlxsw_sp_is_vrf_event(event, ptr))
4635 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
4636 else if (mlxsw_sp_port_dev_check(dev))
4637 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4638 else if (netif_is_lag_master(dev))
4639 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4640 else if (netif_is_bridge_master(dev))
4641 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
4642 else if (is_vlan_dev(dev))
4643 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
4644
4645 return notifier_from_errno(err);
4646 }
4647
4648 static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4649 .notifier_call = mlxsw_sp_netdevice_event,
4650 };
4651
4652 static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4653 .notifier_call = mlxsw_sp_inetaddr_event,
4654 .priority = 10, /* Must be called before FIB notifier block */
4655 };
4656
4657 static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4658 .notifier_call = mlxsw_sp_router_netevent_event,
4659 };
4660
4661 static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4662 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4663 {0, },
4664 };
4665
4666 static struct pci_driver mlxsw_sp_pci_driver = {
4667 .name = mlxsw_sp_driver_name,
4668 .id_table = mlxsw_sp_pci_id_table,
4669 };
4670
4671 static int __init mlxsw_sp_module_init(void)
4672 {
4673 int err;
4674
4675 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4676 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4677 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4678
4679 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4680 if (err)
4681 goto err_core_driver_register;
4682
4683 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4684 if (err)
4685 goto err_pci_driver_register;
4686
4687 return 0;
4688
4689 err_pci_driver_register:
4690 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
4691 err_core_driver_register:
4692 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4693 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4694 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4695 return err;
4696 }
4697
4698 static void __exit mlxsw_sp_module_exit(void)
4699 {
4700 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
4701 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
4702 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4703 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4704 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4705 }
4706
4707 module_init(mlxsw_sp_module_init);
4708 module_exit(mlxsw_sp_module_exit);
4709
4710 MODULE_LICENSE("Dual BSD/GPL");
4711 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4712 MODULE_DESCRIPTION("Mellanox Spectrum driver");
4713 MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
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