1 /* MOXA ART Ethernet (RTL8201CP) driver.
3 * Copyright (C) 2013 Jonas Jensen
5 * Jonas Jensen <jonas.jensen@gmail.com>
8 * Moxa Technology Co., Ltd. <www.moxa.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/skbuff.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/ethtool.h>
21 #include <linux/platform_device.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/crc32.h>
27 #include <linux/crc32c.h>
28 #include <linux/circ_buf.h>
30 #include "moxart_ether.h"
32 static inline void moxart_desc_write(u32 data
, u32
*desc
)
34 *desc
= cpu_to_le32(data
);
37 static inline u32
moxart_desc_read(u32
*desc
)
39 return le32_to_cpu(*desc
);
42 static inline void moxart_emac_write(struct net_device
*ndev
,
43 unsigned int reg
, unsigned long value
)
45 struct moxart_mac_priv_t
*priv
= netdev_priv(ndev
);
47 writel(value
, priv
->base
+ reg
);
50 static void moxart_update_mac_address(struct net_device
*ndev
)
52 moxart_emac_write(ndev
, REG_MAC_MS_ADDRESS
,
53 ((ndev
->dev_addr
[0] << 8) | (ndev
->dev_addr
[1])));
54 moxart_emac_write(ndev
, REG_MAC_MS_ADDRESS
+ 4,
55 ((ndev
->dev_addr
[2] << 24) |
56 (ndev
->dev_addr
[3] << 16) |
57 (ndev
->dev_addr
[4] << 8) |
58 (ndev
->dev_addr
[5])));
61 static int moxart_set_mac_address(struct net_device
*ndev
, void *addr
)
63 struct sockaddr
*address
= addr
;
65 if (!is_valid_ether_addr(address
->sa_data
))
66 return -EADDRNOTAVAIL
;
68 memcpy(ndev
->dev_addr
, address
->sa_data
, ndev
->addr_len
);
69 moxart_update_mac_address(ndev
);
74 static void moxart_mac_free_memory(struct net_device
*ndev
)
76 struct moxart_mac_priv_t
*priv
= netdev_priv(ndev
);
79 for (i
= 0; i
< RX_DESC_NUM
; i
++)
80 dma_unmap_single(&ndev
->dev
, priv
->rx_mapping
[i
],
81 priv
->rx_buf_size
, DMA_FROM_DEVICE
);
83 if (priv
->tx_desc_base
)
84 dma_free_coherent(NULL
, TX_REG_DESC_SIZE
* TX_DESC_NUM
,
85 priv
->tx_desc_base
, priv
->tx_base
);
87 if (priv
->rx_desc_base
)
88 dma_free_coherent(NULL
, RX_REG_DESC_SIZE
* RX_DESC_NUM
,
89 priv
->rx_desc_base
, priv
->rx_base
);
91 kfree(priv
->tx_buf_base
);
92 kfree(priv
->rx_buf_base
);
95 static void moxart_mac_reset(struct net_device
*ndev
)
97 struct moxart_mac_priv_t
*priv
= netdev_priv(ndev
);
99 writel(SW_RST
, priv
->base
+ REG_MAC_CTRL
);
100 while (readl(priv
->base
+ REG_MAC_CTRL
) & SW_RST
)
103 writel(0, priv
->base
+ REG_INTERRUPT_MASK
);
105 priv
->reg_maccr
= RX_BROADPKT
| FULLDUP
| CRC_APD
| RX_FTL
;
108 static void moxart_mac_enable(struct net_device
*ndev
)
110 struct moxart_mac_priv_t
*priv
= netdev_priv(ndev
);
112 writel(0x00001010, priv
->base
+ REG_INT_TIMER_CTRL
);
113 writel(0x00000001, priv
->base
+ REG_APOLL_TIMER_CTRL
);
114 writel(0x00000390, priv
->base
+ REG_DMA_BLEN_CTRL
);
116 priv
->reg_imr
|= (RPKT_FINISH_M
| XPKT_FINISH_M
);
117 writel(priv
->reg_imr
, priv
->base
+ REG_INTERRUPT_MASK
);
119 priv
->reg_maccr
|= (RCV_EN
| XMT_EN
| RDMA_EN
| XDMA_EN
);
120 writel(priv
->reg_maccr
, priv
->base
+ REG_MAC_CTRL
);
123 static void moxart_mac_setup_desc_ring(struct net_device
*ndev
)
125 struct moxart_mac_priv_t
*priv
= netdev_priv(ndev
);
129 for (i
= 0; i
< TX_DESC_NUM
; i
++) {
130 desc
= priv
->tx_desc_base
+ i
* TX_REG_DESC_SIZE
;
131 memset(desc
, 0, TX_REG_DESC_SIZE
);
133 priv
->tx_buf
[i
] = priv
->tx_buf_base
+ priv
->tx_buf_size
* i
;
135 moxart_desc_write(TX_DESC1_END
, desc
+ TX_REG_OFFSET_DESC1
);
140 for (i
= 0; i
< RX_DESC_NUM
; i
++) {
141 desc
= priv
->rx_desc_base
+ i
* RX_REG_DESC_SIZE
;
142 memset(desc
, 0, RX_REG_DESC_SIZE
);
143 moxart_desc_write(RX_DESC0_DMA_OWN
, desc
+ RX_REG_OFFSET_DESC0
);
144 moxart_desc_write(RX_BUF_SIZE
& RX_DESC1_BUF_SIZE_MASK
,
145 desc
+ RX_REG_OFFSET_DESC1
);
147 priv
->rx_buf
[i
] = priv
->rx_buf_base
+ priv
->rx_buf_size
* i
;
148 priv
->rx_mapping
[i
] = dma_map_single(&ndev
->dev
,
152 if (dma_mapping_error(&ndev
->dev
, priv
->rx_mapping
[i
]))
153 netdev_err(ndev
, "DMA mapping error\n");
155 moxart_desc_write(priv
->rx_mapping
[i
],
156 desc
+ RX_REG_OFFSET_DESC2
+ RX_DESC2_ADDRESS_PHYS
);
157 moxart_desc_write((uintptr_t)priv
->rx_buf
[i
],
158 desc
+ RX_REG_OFFSET_DESC2
+ RX_DESC2_ADDRESS_VIRT
);
160 moxart_desc_write(RX_DESC1_END
, desc
+ RX_REG_OFFSET_DESC1
);
164 /* reset the MAC controller TX/RX desciptor base address */
165 writel(priv
->tx_base
, priv
->base
+ REG_TXR_BASE_ADDRESS
);
166 writel(priv
->rx_base
, priv
->base
+ REG_RXR_BASE_ADDRESS
);
169 static int moxart_mac_open(struct net_device
*ndev
)
171 struct moxart_mac_priv_t
*priv
= netdev_priv(ndev
);
173 if (!is_valid_ether_addr(ndev
->dev_addr
))
174 return -EADDRNOTAVAIL
;
176 napi_enable(&priv
->napi
);
178 moxart_mac_reset(ndev
);
179 moxart_update_mac_address(ndev
);
180 moxart_mac_setup_desc_ring(ndev
);
181 moxart_mac_enable(ndev
);
182 netif_start_queue(ndev
);
184 netdev_dbg(ndev
, "%s: IMR=0x%x, MACCR=0x%x\n",
185 __func__
, readl(priv
->base
+ REG_INTERRUPT_MASK
),
186 readl(priv
->base
+ REG_MAC_CTRL
));
191 static int moxart_mac_stop(struct net_device
*ndev
)
193 struct moxart_mac_priv_t
*priv
= netdev_priv(ndev
);
195 napi_disable(&priv
->napi
);
197 netif_stop_queue(ndev
);
199 /* disable all interrupts */
200 writel(0, priv
->base
+ REG_INTERRUPT_MASK
);
202 /* disable all functions */
203 writel(0, priv
->base
+ REG_MAC_CTRL
);
208 static int moxart_rx_poll(struct napi_struct
*napi
, int budget
)
210 struct moxart_mac_priv_t
*priv
= container_of(napi
,
211 struct moxart_mac_priv_t
,
213 struct net_device
*ndev
= priv
->ndev
;
216 unsigned int desc0
, len
;
217 int rx_head
= priv
->rx_head
;
220 while (rx
< budget
) {
221 desc
= priv
->rx_desc_base
+ (RX_REG_DESC_SIZE
* rx_head
);
222 desc0
= moxart_desc_read(desc
+ RX_REG_OFFSET_DESC0
);
223 rmb(); /* ensure desc0 is up to date */
225 if (desc0
& RX_DESC0_DMA_OWN
)
228 if (desc0
& (RX_DESC0_ERR
| RX_DESC0_CRC_ERR
| RX_DESC0_FTL
|
229 RX_DESC0_RUNT
| RX_DESC0_ODD_NB
)) {
230 net_dbg_ratelimited("packet error\n");
231 ndev
->stats
.rx_dropped
++;
232 ndev
->stats
.rx_errors
++;
236 len
= desc0
& RX_DESC0_FRAME_LEN_MASK
;
238 if (len
> RX_BUF_SIZE
)
241 dma_sync_single_for_cpu(&ndev
->dev
,
242 priv
->rx_mapping
[rx_head
],
243 priv
->rx_buf_size
, DMA_FROM_DEVICE
);
244 skb
= netdev_alloc_skb_ip_align(ndev
, len
);
246 if (unlikely(!skb
)) {
247 net_dbg_ratelimited("netdev_alloc_skb_ip_align failed\n");
248 ndev
->stats
.rx_dropped
++;
249 ndev
->stats
.rx_errors
++;
253 memcpy(skb
->data
, priv
->rx_buf
[rx_head
], len
);
255 skb
->protocol
= eth_type_trans(skb
, ndev
);
256 napi_gro_receive(&priv
->napi
, skb
);
259 ndev
->stats
.rx_packets
++;
260 ndev
->stats
.rx_bytes
+= len
;
261 if (desc0
& RX_DESC0_MULTICAST
)
262 ndev
->stats
.multicast
++;
265 wmb(); /* prevent setting ownership back too early */
266 moxart_desc_write(RX_DESC0_DMA_OWN
, desc
+ RX_REG_OFFSET_DESC0
);
268 rx_head
= RX_NEXT(rx_head
);
269 priv
->rx_head
= rx_head
;
273 napi_complete_done(napi
, rx
);
276 priv
->reg_imr
|= RPKT_FINISH_M
;
277 writel(priv
->reg_imr
, priv
->base
+ REG_INTERRUPT_MASK
);
282 static int moxart_tx_queue_space(struct net_device
*ndev
)
284 struct moxart_mac_priv_t
*priv
= netdev_priv(ndev
);
286 return CIRC_SPACE(priv
->tx_head
, priv
->tx_tail
, TX_DESC_NUM
);
289 static void moxart_tx_finished(struct net_device
*ndev
)
291 struct moxart_mac_priv_t
*priv
= netdev_priv(ndev
);
292 unsigned tx_head
= priv
->tx_head
;
293 unsigned tx_tail
= priv
->tx_tail
;
295 while (tx_tail
!= tx_head
) {
296 dma_unmap_single(&ndev
->dev
, priv
->tx_mapping
[tx_tail
],
297 priv
->tx_len
[tx_tail
], DMA_TO_DEVICE
);
299 ndev
->stats
.tx_packets
++;
300 ndev
->stats
.tx_bytes
+= priv
->tx_skb
[tx_tail
]->len
;
302 dev_kfree_skb_irq(priv
->tx_skb
[tx_tail
]);
303 priv
->tx_skb
[tx_tail
] = NULL
;
305 tx_tail
= TX_NEXT(tx_tail
);
307 priv
->tx_tail
= tx_tail
;
308 if (netif_queue_stopped(ndev
) &&
309 moxart_tx_queue_space(ndev
) >= TX_WAKE_THRESHOLD
)
310 netif_wake_queue(ndev
);
313 static irqreturn_t
moxart_mac_interrupt(int irq
, void *dev_id
)
315 struct net_device
*ndev
= (struct net_device
*) dev_id
;
316 struct moxart_mac_priv_t
*priv
= netdev_priv(ndev
);
317 unsigned int ists
= readl(priv
->base
+ REG_INTERRUPT_STATUS
);
319 if (ists
& XPKT_OK_INT_STS
)
320 moxart_tx_finished(ndev
);
322 if (ists
& RPKT_FINISH
) {
323 if (napi_schedule_prep(&priv
->napi
)) {
324 priv
->reg_imr
&= ~RPKT_FINISH_M
;
325 writel(priv
->reg_imr
, priv
->base
+ REG_INTERRUPT_MASK
);
326 __napi_schedule(&priv
->napi
);
333 static int moxart_mac_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
335 struct moxart_mac_priv_t
*priv
= netdev_priv(ndev
);
338 unsigned int tx_head
;
340 int ret
= NETDEV_TX_BUSY
;
342 spin_lock_irq(&priv
->txlock
);
344 tx_head
= priv
->tx_head
;
345 desc
= priv
->tx_desc_base
+ (TX_REG_DESC_SIZE
* tx_head
);
347 if (moxart_tx_queue_space(ndev
) == 1)
348 netif_stop_queue(ndev
);
350 if (moxart_desc_read(desc
+ TX_REG_OFFSET_DESC0
) & TX_DESC0_DMA_OWN
) {
351 net_dbg_ratelimited("no TX space for packet\n");
352 ndev
->stats
.tx_dropped
++;
355 rmb(); /* ensure data is only read that had TX_DESC0_DMA_OWN cleared */
357 len
= skb
->len
> TX_BUF_SIZE
? TX_BUF_SIZE
: skb
->len
;
359 priv
->tx_mapping
[tx_head
] = dma_map_single(&ndev
->dev
, skb
->data
,
361 if (dma_mapping_error(&ndev
->dev
, priv
->tx_mapping
[tx_head
])) {
362 netdev_err(ndev
, "DMA mapping error\n");
366 priv
->tx_len
[tx_head
] = len
;
367 priv
->tx_skb
[tx_head
] = skb
;
369 moxart_desc_write(priv
->tx_mapping
[tx_head
],
370 desc
+ TX_REG_OFFSET_DESC2
+ TX_DESC2_ADDRESS_PHYS
);
371 moxart_desc_write((uintptr_t)skb
->data
,
372 desc
+ TX_REG_OFFSET_DESC2
+ TX_DESC2_ADDRESS_VIRT
);
374 if (skb
->len
< ETH_ZLEN
) {
375 memset(&skb
->data
[skb
->len
],
376 0, ETH_ZLEN
- skb
->len
);
380 dma_sync_single_for_device(&ndev
->dev
, priv
->tx_mapping
[tx_head
],
381 priv
->tx_buf_size
, DMA_TO_DEVICE
);
383 txdes1
= TX_DESC1_LTS
| TX_DESC1_FTS
| (len
& TX_DESC1_BUF_SIZE_MASK
);
384 if (tx_head
== TX_DESC_NUM_MASK
)
385 txdes1
|= TX_DESC1_END
;
386 moxart_desc_write(txdes1
, desc
+ TX_REG_OFFSET_DESC1
);
387 wmb(); /* flush descriptor before transferring ownership */
388 moxart_desc_write(TX_DESC0_DMA_OWN
, desc
+ TX_REG_OFFSET_DESC0
);
390 /* start to send packet */
391 writel(0xffffffff, priv
->base
+ REG_TX_POLL_DEMAND
);
393 priv
->tx_head
= TX_NEXT(tx_head
);
395 netif_trans_update(ndev
);
398 spin_unlock_irq(&priv
->txlock
);
403 static void moxart_mac_setmulticast(struct net_device
*ndev
)
405 struct moxart_mac_priv_t
*priv
= netdev_priv(ndev
);
406 struct netdev_hw_addr
*ha
;
409 netdev_for_each_mc_addr(ha
, ndev
) {
410 crc_val
= crc32_le(~0, ha
->addr
, ETH_ALEN
);
411 crc_val
= (crc_val
>> 26) & 0x3f;
413 writel(readl(priv
->base
+ REG_MCAST_HASH_TABLE1
) |
414 (1UL << (crc_val
- 32)),
415 priv
->base
+ REG_MCAST_HASH_TABLE1
);
417 writel(readl(priv
->base
+ REG_MCAST_HASH_TABLE0
) |
419 priv
->base
+ REG_MCAST_HASH_TABLE0
);
424 static void moxart_mac_set_rx_mode(struct net_device
*ndev
)
426 struct moxart_mac_priv_t
*priv
= netdev_priv(ndev
);
428 spin_lock_irq(&priv
->txlock
);
430 (ndev
->flags
& IFF_PROMISC
) ? (priv
->reg_maccr
|= RCV_ALL
) :
431 (priv
->reg_maccr
&= ~RCV_ALL
);
433 (ndev
->flags
& IFF_ALLMULTI
) ? (priv
->reg_maccr
|= RX_MULTIPKT
) :
434 (priv
->reg_maccr
&= ~RX_MULTIPKT
);
436 if ((ndev
->flags
& IFF_MULTICAST
) && netdev_mc_count(ndev
)) {
437 priv
->reg_maccr
|= HT_MULTI_EN
;
438 moxart_mac_setmulticast(ndev
);
440 priv
->reg_maccr
&= ~HT_MULTI_EN
;
443 writel(priv
->reg_maccr
, priv
->base
+ REG_MAC_CTRL
);
445 spin_unlock_irq(&priv
->txlock
);
448 static const struct net_device_ops moxart_netdev_ops
= {
449 .ndo_open
= moxart_mac_open
,
450 .ndo_stop
= moxart_mac_stop
,
451 .ndo_start_xmit
= moxart_mac_start_xmit
,
452 .ndo_set_rx_mode
= moxart_mac_set_rx_mode
,
453 .ndo_set_mac_address
= moxart_set_mac_address
,
454 .ndo_validate_addr
= eth_validate_addr
,
457 static int moxart_mac_probe(struct platform_device
*pdev
)
459 struct device
*p_dev
= &pdev
->dev
;
460 struct device_node
*node
= p_dev
->of_node
;
461 struct net_device
*ndev
;
462 struct moxart_mac_priv_t
*priv
;
463 struct resource
*res
;
467 ndev
= alloc_etherdev(sizeof(struct moxart_mac_priv_t
));
471 irq
= irq_of_parse_and_map(node
, 0);
473 netdev_err(ndev
, "irq_of_parse_and_map failed\n");
478 priv
= netdev_priv(ndev
);
481 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
482 ndev
->base_addr
= res
->start
;
483 priv
->base
= devm_ioremap_resource(p_dev
, res
);
484 if (IS_ERR(priv
->base
)) {
485 dev_err(p_dev
, "devm_ioremap_resource failed\n");
486 ret
= PTR_ERR(priv
->base
);
490 spin_lock_init(&priv
->txlock
);
492 priv
->tx_buf_size
= TX_BUF_SIZE
;
493 priv
->rx_buf_size
= RX_BUF_SIZE
;
495 priv
->tx_desc_base
= dma_alloc_coherent(NULL
, TX_REG_DESC_SIZE
*
496 TX_DESC_NUM
, &priv
->tx_base
,
497 GFP_DMA
| GFP_KERNEL
);
498 if (priv
->tx_desc_base
== NULL
) {
503 priv
->rx_desc_base
= dma_alloc_coherent(NULL
, RX_REG_DESC_SIZE
*
504 RX_DESC_NUM
, &priv
->rx_base
,
505 GFP_DMA
| GFP_KERNEL
);
506 if (priv
->rx_desc_base
== NULL
) {
511 priv
->tx_buf_base
= kmalloc(priv
->tx_buf_size
* TX_DESC_NUM
,
513 if (!priv
->tx_buf_base
) {
518 priv
->rx_buf_base
= kmalloc(priv
->rx_buf_size
* RX_DESC_NUM
,
520 if (!priv
->rx_buf_base
) {
525 platform_set_drvdata(pdev
, ndev
);
527 ret
= devm_request_irq(p_dev
, irq
, moxart_mac_interrupt
, 0,
530 netdev_err(ndev
, "devm_request_irq failed\n");
534 ndev
->netdev_ops
= &moxart_netdev_ops
;
535 netif_napi_add(ndev
, &priv
->napi
, moxart_rx_poll
, RX_DESC_NUM
);
536 ndev
->priv_flags
|= IFF_UNICAST_FLT
;
539 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
541 ret
= register_netdev(ndev
);
547 netdev_dbg(ndev
, "%s: IRQ=%d address=%pM\n",
548 __func__
, ndev
->irq
, ndev
->dev_addr
);
553 netdev_err(ndev
, "init failed\n");
554 moxart_mac_free_memory(ndev
);
560 static int moxart_remove(struct platform_device
*pdev
)
562 struct net_device
*ndev
= platform_get_drvdata(pdev
);
564 unregister_netdev(ndev
);
565 free_irq(ndev
->irq
, ndev
);
566 moxart_mac_free_memory(ndev
);
572 static const struct of_device_id moxart_mac_match
[] = {
573 { .compatible
= "moxa,moxart-mac" },
576 MODULE_DEVICE_TABLE(of
, moxart_mac_match
);
578 static struct platform_driver moxart_mac_driver
= {
579 .probe
= moxart_mac_probe
,
580 .remove
= moxart_remove
,
582 .name
= "moxart-ethernet",
583 .of_match_table
= moxart_mac_match
,
586 module_platform_driver(moxart_mac_driver
);
588 MODULE_DESCRIPTION("MOXART RTL8201CP Ethernet driver");
589 MODULE_LICENSE("GPL v2");
590 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");