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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mscc / ocelot.c
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7 #include <linux/dsa/ocelot.h>
8 #include <linux/if_bridge.h>
9 #include <linux/ptp_classify.h>
10 #include <soc/mscc/ocelot_vcap.h>
11 #include "ocelot.h"
12 #include "ocelot_vcap.h"
13
14 #define TABLE_UPDATE_SLEEP_US 10
15 #define TABLE_UPDATE_TIMEOUT_US 100000
16
17 struct ocelot_mact_entry {
18 u8 mac[ETH_ALEN];
19 u16 vid;
20 enum macaccess_entry_type type;
21 };
22
23 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
24 {
25 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
26 }
27
28 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
29 {
30 u32 val;
31
32 return readx_poll_timeout(ocelot_mact_read_macaccess,
33 ocelot, val,
34 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
35 MACACCESS_CMD_IDLE,
36 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
37 }
38
39 static void ocelot_mact_select(struct ocelot *ocelot,
40 const unsigned char mac[ETH_ALEN],
41 unsigned int vid)
42 {
43 u32 macl = 0, mach = 0;
44
45 /* Set the MAC address to handle and the vlan associated in a format
46 * understood by the hardware.
47 */
48 mach |= vid << 16;
49 mach |= mac[0] << 8;
50 mach |= mac[1] << 0;
51 macl |= mac[2] << 24;
52 macl |= mac[3] << 16;
53 macl |= mac[4] << 8;
54 macl |= mac[5] << 0;
55
56 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
57 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
58
59 }
60
61 int ocelot_mact_learn(struct ocelot *ocelot, int port,
62 const unsigned char mac[ETH_ALEN],
63 unsigned int vid, enum macaccess_entry_type type)
64 {
65 u32 cmd = ANA_TABLES_MACACCESS_VALID |
66 ANA_TABLES_MACACCESS_DEST_IDX(port) |
67 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
68 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
69 unsigned int mc_ports;
70
71 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
72 if (type == ENTRYTYPE_MACv4)
73 mc_ports = (mac[1] << 8) | mac[2];
74 else if (type == ENTRYTYPE_MACv6)
75 mc_ports = (mac[0] << 8) | mac[1];
76 else
77 mc_ports = 0;
78
79 if (mc_ports & BIT(ocelot->num_phys_ports))
80 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
81
82 ocelot_mact_select(ocelot, mac, vid);
83
84 /* Issue a write command */
85 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
86
87 return ocelot_mact_wait_for_completion(ocelot);
88 }
89 EXPORT_SYMBOL(ocelot_mact_learn);
90
91 int ocelot_mact_forget(struct ocelot *ocelot,
92 const unsigned char mac[ETH_ALEN], unsigned int vid)
93 {
94 ocelot_mact_select(ocelot, mac, vid);
95
96 /* Issue a forget command */
97 ocelot_write(ocelot,
98 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
99 ANA_TABLES_MACACCESS);
100
101 return ocelot_mact_wait_for_completion(ocelot);
102 }
103 EXPORT_SYMBOL(ocelot_mact_forget);
104
105 static void ocelot_mact_init(struct ocelot *ocelot)
106 {
107 /* Configure the learning mode entries attributes:
108 * - Do not copy the frame to the CPU extraction queues.
109 * - Use the vlan and mac_cpoy for dmac lookup.
110 */
111 ocelot_rmw(ocelot, 0,
112 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
113 | ANA_AGENCTRL_LEARN_FWD_KILL
114 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
115 ANA_AGENCTRL);
116
117 /* Clear the MAC table */
118 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
119 }
120
121 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
122 {
123 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
124 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
125 ANA_PORT_VCAP_S2_CFG, port);
126
127 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
128 ANA_PORT_VCAP_CFG, port);
129
130 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
131 REW_PORT_CFG_ES0_EN,
132 REW_PORT_CFG, port);
133 }
134
135 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
136 {
137 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
138 }
139
140 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
141 {
142 u32 val;
143
144 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
145 ocelot,
146 val,
147 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
148 ANA_TABLES_VLANACCESS_CMD_IDLE,
149 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
150 }
151
152 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
153 {
154 /* Select the VID to configure */
155 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
156 ANA_TABLES_VLANTIDX);
157 /* Set the vlan port members mask and issue a write command */
158 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
159 ANA_TABLES_VLANACCESS_CMD_WRITE,
160 ANA_TABLES_VLANACCESS);
161
162 return ocelot_vlant_wait_for_completion(ocelot);
163 }
164
165 static void ocelot_port_set_native_vlan(struct ocelot *ocelot, int port,
166 struct ocelot_vlan native_vlan)
167 {
168 struct ocelot_port *ocelot_port = ocelot->ports[port];
169 u32 val = 0;
170
171 ocelot_port->native_vlan = native_vlan;
172
173 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(native_vlan.vid),
174 REW_PORT_VLAN_CFG_PORT_VID_M,
175 REW_PORT_VLAN_CFG, port);
176
177 if (ocelot_port->vlan_aware) {
178 if (native_vlan.valid)
179 /* Tag all frames except when VID == DEFAULT_VLAN */
180 val = REW_TAG_CFG_TAG_CFG(1);
181 else
182 /* Tag all frames */
183 val = REW_TAG_CFG_TAG_CFG(3);
184 } else {
185 /* Port tagging disabled. */
186 val = REW_TAG_CFG_TAG_CFG(0);
187 }
188 ocelot_rmw_gix(ocelot, val,
189 REW_TAG_CFG_TAG_CFG_M,
190 REW_TAG_CFG, port);
191 }
192
193 /* Default vlan to clasify for untagged frames (may be zero) */
194 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port,
195 struct ocelot_vlan pvid_vlan)
196 {
197 struct ocelot_port *ocelot_port = ocelot->ports[port];
198 u32 val = 0;
199
200 ocelot_port->pvid_vlan = pvid_vlan;
201
202 if (!ocelot_port->vlan_aware)
203 pvid_vlan.vid = 0;
204
205 ocelot_rmw_gix(ocelot,
206 ANA_PORT_VLAN_CFG_VLAN_VID(pvid_vlan.vid),
207 ANA_PORT_VLAN_CFG_VLAN_VID_M,
208 ANA_PORT_VLAN_CFG, port);
209
210 /* If there's no pvid, we should drop not only untagged traffic (which
211 * happens automatically), but also 802.1p traffic which gets
212 * classified to VLAN 0, but that is always in our RX filter, so it
213 * would get accepted were it not for this setting.
214 */
215 if (!pvid_vlan.valid && ocelot_port->vlan_aware)
216 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
217 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
218
219 ocelot_rmw_gix(ocelot, val,
220 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
221 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
222 ANA_PORT_DROP_CFG, port);
223 }
224
225 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
226 bool vlan_aware)
227 {
228 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
229 struct ocelot_port *ocelot_port = ocelot->ports[port];
230 struct ocelot_vcap_filter *filter;
231 u32 val;
232
233 list_for_each_entry(filter, &block->rules, list) {
234 if (filter->ingress_port_mask & BIT(port) &&
235 filter->action.vid_replace_ena) {
236 dev_err(ocelot->dev,
237 "Cannot change VLAN state with vlan modify rules active\n");
238 return -EBUSY;
239 }
240 }
241
242 ocelot_port->vlan_aware = vlan_aware;
243
244 if (vlan_aware)
245 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
246 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
247 else
248 val = 0;
249 ocelot_rmw_gix(ocelot, val,
250 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
251 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
252 ANA_PORT_VLAN_CFG, port);
253
254 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan);
255 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->native_vlan);
256
257 return 0;
258 }
259 EXPORT_SYMBOL(ocelot_port_vlan_filtering);
260
261 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
262 bool untagged)
263 {
264 struct ocelot_port *ocelot_port = ocelot->ports[port];
265
266 /* Deny changing the native VLAN, but always permit deleting it */
267 if (untagged && ocelot_port->native_vlan.vid != vid &&
268 ocelot_port->native_vlan.valid) {
269 dev_err(ocelot->dev,
270 "Port already has a native VLAN: %d\n",
271 ocelot_port->native_vlan.vid);
272 return -EBUSY;
273 }
274
275 return 0;
276 }
277 EXPORT_SYMBOL(ocelot_vlan_prepare);
278
279 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
280 bool untagged)
281 {
282 int ret;
283
284 /* Make the port a member of the VLAN */
285 ocelot->vlan_mask[vid] |= BIT(port);
286 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
287 if (ret)
288 return ret;
289
290 /* Default ingress vlan classification */
291 if (pvid) {
292 struct ocelot_vlan pvid_vlan;
293
294 pvid_vlan.vid = vid;
295 pvid_vlan.valid = true;
296 ocelot_port_set_pvid(ocelot, port, pvid_vlan);
297 }
298
299 /* Untagged egress vlan clasification */
300 if (untagged) {
301 struct ocelot_vlan native_vlan;
302
303 native_vlan.vid = vid;
304 native_vlan.valid = true;
305 ocelot_port_set_native_vlan(ocelot, port, native_vlan);
306 }
307
308 return 0;
309 }
310 EXPORT_SYMBOL(ocelot_vlan_add);
311
312 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
313 {
314 struct ocelot_port *ocelot_port = ocelot->ports[port];
315 int ret;
316
317 /* Stop the port from being a member of the vlan */
318 ocelot->vlan_mask[vid] &= ~BIT(port);
319 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
320 if (ret)
321 return ret;
322
323 /* Ingress */
324 if (ocelot_port->pvid_vlan.vid == vid) {
325 struct ocelot_vlan pvid_vlan = {0};
326
327 ocelot_port_set_pvid(ocelot, port, pvid_vlan);
328 }
329
330 /* Egress */
331 if (ocelot_port->native_vlan.vid == vid) {
332 struct ocelot_vlan native_vlan = {0};
333
334 ocelot_port_set_native_vlan(ocelot, port, native_vlan);
335 }
336
337 return 0;
338 }
339 EXPORT_SYMBOL(ocelot_vlan_del);
340
341 static void ocelot_vlan_init(struct ocelot *ocelot)
342 {
343 u16 port, vid;
344
345 /* Clear VLAN table, by default all ports are members of all VLANs */
346 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
347 ANA_TABLES_VLANACCESS);
348 ocelot_vlant_wait_for_completion(ocelot);
349
350 /* Configure the port VLAN memberships */
351 for (vid = 1; vid < VLAN_N_VID; vid++) {
352 ocelot->vlan_mask[vid] = 0;
353 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
354 }
355
356 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
357 * traffic. It is added automatically if 8021q module is loaded, but
358 * we can't rely on it since module may be not loaded.
359 */
360 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
361 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
362
363 /* Set vlan ingress filter mask to all ports but the CPU port by
364 * default.
365 */
366 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
367 ANA_VLANMASK);
368
369 for (port = 0; port < ocelot->num_phys_ports; port++) {
370 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
371 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
372 }
373 }
374
375 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port)
376 {
377 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);
378 }
379
380 int ocelot_port_flush(struct ocelot *ocelot, int port)
381 {
382 unsigned int pause_ena;
383 int err, val;
384
385 /* Disable dequeuing from the egress queues */
386 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS,
387 QSYS_PORT_MODE_DEQUEUE_DIS,
388 QSYS_PORT_MODE, port);
389
390 /* Disable flow control */
391 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena);
392 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
393
394 /* Disable priority flow control */
395 ocelot_fields_write(ocelot, port,
396 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0);
397
398 /* Wait at least the time it takes to receive a frame of maximum length
399 * at the port.
400 * Worst-case delays for 10 kilobyte jumbo frames are:
401 * 8 ms on a 10M port
402 * 800 μs on a 100M port
403 * 80 μs on a 1G port
404 * 32 μs on a 2.5G port
405 */
406 usleep_range(8000, 10000);
407
408 /* Disable half duplex backpressure. */
409 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE,
410 SYS_FRONT_PORT_MODE, port);
411
412 /* Flush the queues associated with the port. */
413 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA,
414 REW_PORT_CFG, port);
415
416 /* Enable dequeuing from the egress queues. */
417 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE,
418 port);
419
420 /* Wait until flushing is complete. */
421 err = read_poll_timeout(ocelot_read_eq_avail, val, !val,
422 100, 2000000, false, ocelot, port);
423
424 /* Clear flushing again. */
425 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port);
426
427 /* Re-enable flow control */
428 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena);
429
430 return err;
431 }
432 EXPORT_SYMBOL(ocelot_port_flush);
433
434 void ocelot_adjust_link(struct ocelot *ocelot, int port,
435 struct phy_device *phydev)
436 {
437 struct ocelot_port *ocelot_port = ocelot->ports[port];
438 int speed, mode = 0;
439
440 switch (phydev->speed) {
441 case SPEED_10:
442 speed = OCELOT_SPEED_10;
443 break;
444 case SPEED_100:
445 speed = OCELOT_SPEED_100;
446 break;
447 case SPEED_1000:
448 speed = OCELOT_SPEED_1000;
449 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
450 break;
451 case SPEED_2500:
452 speed = OCELOT_SPEED_2500;
453 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
454 break;
455 default:
456 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n",
457 port, phydev->speed);
458 return;
459 }
460
461 phy_print_status(phydev);
462
463 if (!phydev->link)
464 return;
465
466 /* Only full duplex supported for now */
467 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |
468 mode, DEV_MAC_MODE_CFG);
469
470 /* Disable HDX fast control */
471 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
472 DEV_PORT_MISC);
473
474 /* SGMII only for now */
475 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
476 PCS1G_MODE_CFG);
477 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
478
479 /* Enable PCS */
480 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
481
482 /* No aneg on SGMII */
483 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
484
485 /* No loopback */
486 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
487
488 /* Enable MAC module */
489 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
490 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
491
492 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
493 * reset
494 */
495 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
496 DEV_CLOCK_CFG);
497
498 /* No PFC */
499 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
500 ANA_PFC_PFC_CFG, port);
501
502 /* Core: Enable port for frame transfer */
503 ocelot_fields_write(ocelot, port,
504 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
505
506 /* Flow control */
507 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
508 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
509 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
510 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
511 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
512 SYS_MAC_FC_CFG, port);
513 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
514 }
515 EXPORT_SYMBOL(ocelot_adjust_link);
516
517 void ocelot_port_enable(struct ocelot *ocelot, int port,
518 struct phy_device *phy)
519 {
520 /* Enable receiving frames on the port, and activate auto-learning of
521 * MAC addresses.
522 */
523 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
524 ANA_PORT_PORT_CFG_RECV_ENA |
525 ANA_PORT_PORT_CFG_PORTID_VAL(port),
526 ANA_PORT_PORT_CFG, port);
527 }
528 EXPORT_SYMBOL(ocelot_port_enable);
529
530 void ocelot_port_disable(struct ocelot *ocelot, int port)
531 {
532 struct ocelot_port *ocelot_port = ocelot->ports[port];
533
534 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG);
535 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
536 }
537 EXPORT_SYMBOL(ocelot_port_disable);
538
539 static void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port,
540 struct sk_buff *clone)
541 {
542 struct ocelot_port *ocelot_port = ocelot->ports[port];
543
544 spin_lock(&ocelot_port->ts_id_lock);
545
546 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS;
547 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */
548 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id;
549 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4;
550 skb_queue_tail(&ocelot_port->tx_skbs, clone);
551
552 spin_unlock(&ocelot_port->ts_id_lock);
553 }
554
555 u32 ocelot_ptp_rew_op(struct sk_buff *skb)
556 {
557 struct sk_buff *clone = OCELOT_SKB_CB(skb)->clone;
558 u8 ptp_cmd = OCELOT_SKB_CB(skb)->ptp_cmd;
559 u32 rew_op = 0;
560
561 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP && clone) {
562 rew_op = ptp_cmd;
563 rew_op |= OCELOT_SKB_CB(clone)->ts_id << 3;
564 } else if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) {
565 rew_op = ptp_cmd;
566 }
567
568 return rew_op;
569 }
570 EXPORT_SYMBOL(ocelot_ptp_rew_op);
571
572 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb)
573 {
574 struct ptp_header *hdr;
575 unsigned int ptp_class;
576 u8 msgtype, twostep;
577
578 ptp_class = ptp_classify_raw(skb);
579 if (ptp_class == PTP_CLASS_NONE)
580 return false;
581
582 hdr = ptp_parse_header(skb, ptp_class);
583 if (!hdr)
584 return false;
585
586 msgtype = ptp_get_msgtype(hdr, ptp_class);
587 twostep = hdr->flag_field[0] & 0x2;
588
589 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0)
590 return true;
591
592 return false;
593 }
594
595 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port,
596 struct sk_buff *skb,
597 struct sk_buff **clone)
598 {
599 struct ocelot_port *ocelot_port = ocelot->ports[port];
600 u8 ptp_cmd = ocelot_port->ptp_cmd;
601
602 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */
603 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) {
604 if (ocelot_ptp_is_onestep_sync(skb)) {
605 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd;
606 return 0;
607 }
608
609 /* Fall back to two-step timestamping */
610 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
611 }
612
613 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) {
614 *clone = skb_clone_sk(skb);
615 if (!(*clone))
616 return -ENOMEM;
617
618 ocelot_port_add_txtstamp_skb(ocelot, port, *clone);
619 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd;
620 }
621
622 return 0;
623 }
624 EXPORT_SYMBOL(ocelot_port_txtstamp_request);
625
626 static void ocelot_get_hwtimestamp(struct ocelot *ocelot,
627 struct timespec64 *ts)
628 {
629 unsigned long flags;
630 u32 val;
631
632 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
633
634 /* Read current PTP time to get seconds */
635 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
636
637 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
638 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
639 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
640 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
641
642 /* Read packet HW timestamp from FIFO */
643 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP);
644 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val);
645
646 /* Sec has incremented since the ts was registered */
647 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC))
648 ts->tv_sec--;
649
650 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
651 }
652
653 void ocelot_get_txtstamp(struct ocelot *ocelot)
654 {
655 int budget = OCELOT_PTP_QUEUE_SZ;
656
657 while (budget--) {
658 struct sk_buff *skb, *skb_tmp, *skb_match = NULL;
659 struct skb_shared_hwtstamps shhwtstamps;
660 struct ocelot_port *port;
661 struct timespec64 ts;
662 unsigned long flags;
663 u32 val, id, txport;
664
665 val = ocelot_read(ocelot, SYS_PTP_STATUS);
666
667 /* Check if a timestamp can be retrieved */
668 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD))
669 break;
670
671 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL);
672
673 /* Retrieve the ts ID and Tx port */
674 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val);
675 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val);
676
677 /* Retrieve its associated skb */
678 port = ocelot->ports[txport];
679
680 spin_lock_irqsave(&port->tx_skbs.lock, flags);
681
682 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) {
683 if (OCELOT_SKB_CB(skb)->ts_id != id)
684 continue;
685 __skb_unlink(skb, &port->tx_skbs);
686 skb_match = skb;
687 break;
688 }
689
690 spin_unlock_irqrestore(&port->tx_skbs.lock, flags);
691
692 /* Get the h/w timestamp */
693 ocelot_get_hwtimestamp(ocelot, &ts);
694
695 if (unlikely(!skb_match))
696 continue;
697
698 /* Set the timestamp into the skb */
699 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
700 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
701 skb_complete_tx_timestamp(skb_match, &shhwtstamps);
702
703 /* Next ts */
704 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT);
705 }
706 }
707 EXPORT_SYMBOL(ocelot_get_txtstamp);
708
709 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
710 u32 *rval)
711 {
712 u32 bytes_valid, val;
713
714 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
715 if (val == XTR_NOT_READY) {
716 if (ifh)
717 return -EIO;
718
719 do {
720 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
721 } while (val == XTR_NOT_READY);
722 }
723
724 switch (val) {
725 case XTR_ABORT:
726 return -EIO;
727 case XTR_EOF_0:
728 case XTR_EOF_1:
729 case XTR_EOF_2:
730 case XTR_EOF_3:
731 case XTR_PRUNED:
732 bytes_valid = XTR_VALID_BYTES(val);
733 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
734 if (val == XTR_ESCAPE)
735 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
736 else
737 *rval = val;
738
739 return bytes_valid;
740 case XTR_ESCAPE:
741 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
742
743 return 4;
744 default:
745 *rval = val;
746
747 return 4;
748 }
749 }
750
751 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh)
752 {
753 int i, err = 0;
754
755 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
756 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
757 if (err != 4)
758 return (err < 0) ? err : -EIO;
759 }
760
761 return 0;
762 }
763
764 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb)
765 {
766 struct skb_shared_hwtstamps *shhwtstamps;
767 u64 tod_in_ns, full_ts_in_ns;
768 u64 timestamp, src_port, len;
769 u32 xfh[OCELOT_TAG_LEN / 4];
770 struct net_device *dev;
771 struct timespec64 ts;
772 struct sk_buff *skb;
773 int sz, buf_len;
774 u32 val, *buf;
775 int err;
776
777 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh);
778 if (err)
779 return err;
780
781 ocelot_xfh_get_src_port(xfh, &src_port);
782 ocelot_xfh_get_len(xfh, &len);
783 ocelot_xfh_get_rew_val(xfh, &timestamp);
784
785 if (WARN_ON(src_port >= ocelot->num_phys_ports))
786 return -EINVAL;
787
788 dev = ocelot->ops->port_to_netdev(ocelot, src_port);
789 if (!dev)
790 return -EINVAL;
791
792 skb = netdev_alloc_skb(dev, len);
793 if (unlikely(!skb)) {
794 netdev_err(dev, "Unable to allocate sk_buff\n");
795 return -ENOMEM;
796 }
797
798 buf_len = len - ETH_FCS_LEN;
799 buf = (u32 *)skb_put(skb, buf_len);
800
801 len = 0;
802 do {
803 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
804 if (sz < 0) {
805 err = sz;
806 goto out_free_skb;
807 }
808 *buf++ = val;
809 len += sz;
810 } while (len < buf_len);
811
812 /* Read the FCS */
813 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
814 if (sz < 0) {
815 err = sz;
816 goto out_free_skb;
817 }
818
819 /* Update the statistics if part of the FCS was read before */
820 len -= ETH_FCS_LEN - sz;
821
822 if (unlikely(dev->features & NETIF_F_RXFCS)) {
823 buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
824 *buf = val;
825 }
826
827 if (ocelot->ptp) {
828 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
829
830 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
831 if ((tod_in_ns & 0xffffffff) < timestamp)
832 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
833 timestamp;
834 else
835 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
836 timestamp;
837
838 shhwtstamps = skb_hwtstamps(skb);
839 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
840 shhwtstamps->hwtstamp = full_ts_in_ns;
841 }
842
843 /* Everything we see on an interface that is in the HW bridge
844 * has already been forwarded.
845 */
846 if (ocelot->ports[src_port]->bridge)
847 skb->offload_fwd_mark = 1;
848
849 skb->protocol = eth_type_trans(skb, dev);
850
851 *nskb = skb;
852
853 return 0;
854
855 out_free_skb:
856 kfree_skb(skb);
857 return err;
858 }
859 EXPORT_SYMBOL(ocelot_xtr_poll_frame);
860
861 bool ocelot_can_inject(struct ocelot *ocelot, int grp)
862 {
863 u32 val = ocelot_read(ocelot, QS_INJ_STATUS);
864
865 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))))
866 return false;
867 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))
868 return false;
869
870 return true;
871 }
872 EXPORT_SYMBOL(ocelot_can_inject);
873
874 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
875 u32 rew_op, struct sk_buff *skb)
876 {
877 u32 ifh[OCELOT_TAG_LEN / 4] = {0};
878 unsigned int i, count, last;
879
880 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
881 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
882
883 ocelot_ifh_set_bypass(ifh, 1);
884 ocelot_ifh_set_dest(ifh, BIT_ULL(port));
885 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C);
886 ocelot_ifh_set_vid(ifh, skb_vlan_tag_get(skb));
887 ocelot_ifh_set_rew_op(ifh, rew_op);
888
889 for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
890 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
891
892 count = DIV_ROUND_UP(skb->len, 4);
893 last = skb->len % 4;
894 for (i = 0; i < count; i++)
895 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
896
897 /* Add padding */
898 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
899 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
900 i++;
901 }
902
903 /* Indicate EOF and valid bytes in last word */
904 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
905 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
906 QS_INJ_CTRL_EOF,
907 QS_INJ_CTRL, grp);
908
909 /* Add dummy CRC */
910 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
911 skb_tx_timestamp(skb);
912
913 skb->dev->stats.tx_packets++;
914 skb->dev->stats.tx_bytes += skb->len;
915 }
916 EXPORT_SYMBOL(ocelot_port_inject_frame);
917
918 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
919 {
920 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
921 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
922 }
923 EXPORT_SYMBOL(ocelot_drain_cpu_queue);
924
925 int ocelot_fdb_add(struct ocelot *ocelot, int port,
926 const unsigned char *addr, u16 vid)
927 {
928 int pgid = port;
929
930 if (port == ocelot->npi)
931 pgid = PGID_CPU;
932
933 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED);
934 }
935 EXPORT_SYMBOL(ocelot_fdb_add);
936
937 int ocelot_fdb_del(struct ocelot *ocelot, int port,
938 const unsigned char *addr, u16 vid)
939 {
940 return ocelot_mact_forget(ocelot, addr, vid);
941 }
942 EXPORT_SYMBOL(ocelot_fdb_del);
943
944 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid,
945 bool is_static, void *data)
946 {
947 struct ocelot_dump_ctx *dump = data;
948 u32 portid = NETLINK_CB(dump->cb->skb).portid;
949 u32 seq = dump->cb->nlh->nlmsg_seq;
950 struct nlmsghdr *nlh;
951 struct ndmsg *ndm;
952
953 if (dump->idx < dump->cb->args[2])
954 goto skip;
955
956 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
957 sizeof(*ndm), NLM_F_MULTI);
958 if (!nlh)
959 return -EMSGSIZE;
960
961 ndm = nlmsg_data(nlh);
962 ndm->ndm_family = AF_BRIDGE;
963 ndm->ndm_pad1 = 0;
964 ndm->ndm_pad2 = 0;
965 ndm->ndm_flags = NTF_SELF;
966 ndm->ndm_type = 0;
967 ndm->ndm_ifindex = dump->dev->ifindex;
968 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
969
970 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr))
971 goto nla_put_failure;
972
973 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid))
974 goto nla_put_failure;
975
976 nlmsg_end(dump->skb, nlh);
977
978 skip:
979 dump->idx++;
980 return 0;
981
982 nla_put_failure:
983 nlmsg_cancel(dump->skb, nlh);
984 return -EMSGSIZE;
985 }
986 EXPORT_SYMBOL(ocelot_port_fdb_do_dump);
987
988 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
989 struct ocelot_mact_entry *entry)
990 {
991 u32 val, dst, macl, mach;
992 char mac[ETH_ALEN];
993
994 /* Set row and column to read from */
995 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
996 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
997
998 /* Issue a read command */
999 ocelot_write(ocelot,
1000 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
1001 ANA_TABLES_MACACCESS);
1002
1003 if (ocelot_mact_wait_for_completion(ocelot))
1004 return -ETIMEDOUT;
1005
1006 /* Read the entry flags */
1007 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
1008 if (!(val & ANA_TABLES_MACACCESS_VALID))
1009 return -EINVAL;
1010
1011 /* If the entry read has another port configured as its destination,
1012 * do not report it.
1013 */
1014 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
1015 if (dst != port)
1016 return -EINVAL;
1017
1018 /* Get the entry's MAC address and VLAN id */
1019 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
1020 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
1021
1022 mac[0] = (mach >> 8) & 0xff;
1023 mac[1] = (mach >> 0) & 0xff;
1024 mac[2] = (macl >> 24) & 0xff;
1025 mac[3] = (macl >> 16) & 0xff;
1026 mac[4] = (macl >> 8) & 0xff;
1027 mac[5] = (macl >> 0) & 0xff;
1028
1029 entry->vid = (mach >> 16) & 0xfff;
1030 ether_addr_copy(entry->mac, mac);
1031
1032 return 0;
1033 }
1034
1035 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1036 dsa_fdb_dump_cb_t *cb, void *data)
1037 {
1038 int i, j;
1039
1040 /* Loop through all the mac tables entries. */
1041 for (i = 0; i < ocelot->num_mact_rows; i++) {
1042 for (j = 0; j < 4; j++) {
1043 struct ocelot_mact_entry entry;
1044 bool is_static;
1045 int ret;
1046
1047 ret = ocelot_mact_read(ocelot, port, i, j, &entry);
1048 /* If the entry is invalid (wrong port, invalid...),
1049 * skip it.
1050 */
1051 if (ret == -EINVAL)
1052 continue;
1053 else if (ret)
1054 return ret;
1055
1056 is_static = (entry.type == ENTRYTYPE_LOCKED);
1057
1058 ret = cb(entry.mac, entry.vid, is_static, data);
1059 if (ret)
1060 return ret;
1061 }
1062 }
1063
1064 return 0;
1065 }
1066 EXPORT_SYMBOL(ocelot_fdb_dump);
1067
1068 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr)
1069 {
1070 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
1071 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
1072 }
1073 EXPORT_SYMBOL(ocelot_hwstamp_get);
1074
1075 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr)
1076 {
1077 struct ocelot_port *ocelot_port = ocelot->ports[port];
1078 struct hwtstamp_config cfg;
1079
1080 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1081 return -EFAULT;
1082
1083 /* reserved for future extensions */
1084 if (cfg.flags)
1085 return -EINVAL;
1086
1087 /* Tx type sanity check */
1088 switch (cfg.tx_type) {
1089 case HWTSTAMP_TX_ON:
1090 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
1091 break;
1092 case HWTSTAMP_TX_ONESTEP_SYNC:
1093 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
1094 * need to update the origin time.
1095 */
1096 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
1097 break;
1098 case HWTSTAMP_TX_OFF:
1099 ocelot_port->ptp_cmd = 0;
1100 break;
1101 default:
1102 return -ERANGE;
1103 }
1104
1105 mutex_lock(&ocelot->ptp_lock);
1106
1107 switch (cfg.rx_filter) {
1108 case HWTSTAMP_FILTER_NONE:
1109 break;
1110 case HWTSTAMP_FILTER_ALL:
1111 case HWTSTAMP_FILTER_SOME:
1112 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1113 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1114 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1115 case HWTSTAMP_FILTER_NTP_ALL:
1116 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1117 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1118 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1119 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1120 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1121 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1122 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1123 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1124 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1125 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1126 break;
1127 default:
1128 mutex_unlock(&ocelot->ptp_lock);
1129 return -ERANGE;
1130 }
1131
1132 /* Commit back the result & save it */
1133 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
1134 mutex_unlock(&ocelot->ptp_lock);
1135
1136 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1137 }
1138 EXPORT_SYMBOL(ocelot_hwstamp_set);
1139
1140 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data)
1141 {
1142 int i;
1143
1144 if (sset != ETH_SS_STATS)
1145 return;
1146
1147 for (i = 0; i < ocelot->num_stats; i++)
1148 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
1149 ETH_GSTRING_LEN);
1150 }
1151 EXPORT_SYMBOL(ocelot_get_strings);
1152
1153 static void ocelot_update_stats(struct ocelot *ocelot)
1154 {
1155 int i, j;
1156
1157 mutex_lock(&ocelot->stats_lock);
1158
1159 for (i = 0; i < ocelot->num_phys_ports; i++) {
1160 /* Configure the port to read the stats from */
1161 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
1162
1163 for (j = 0; j < ocelot->num_stats; j++) {
1164 u32 val;
1165 unsigned int idx = i * ocelot->num_stats + j;
1166
1167 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
1168 ocelot->stats_layout[j].offset);
1169
1170 if (val < (ocelot->stats[idx] & U32_MAX))
1171 ocelot->stats[idx] += (u64)1 << 32;
1172
1173 ocelot->stats[idx] = (ocelot->stats[idx] &
1174 ~(u64)U32_MAX) + val;
1175 }
1176 }
1177
1178 mutex_unlock(&ocelot->stats_lock);
1179 }
1180
1181 static void ocelot_check_stats_work(struct work_struct *work)
1182 {
1183 struct delayed_work *del_work = to_delayed_work(work);
1184 struct ocelot *ocelot = container_of(del_work, struct ocelot,
1185 stats_work);
1186
1187 ocelot_update_stats(ocelot);
1188
1189 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1190 OCELOT_STATS_CHECK_DELAY);
1191 }
1192
1193 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
1194 {
1195 int i;
1196
1197 /* check and update now */
1198 ocelot_update_stats(ocelot);
1199
1200 /* Copy all counters */
1201 for (i = 0; i < ocelot->num_stats; i++)
1202 *data++ = ocelot->stats[port * ocelot->num_stats + i];
1203 }
1204 EXPORT_SYMBOL(ocelot_get_ethtool_stats);
1205
1206 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
1207 {
1208 if (sset != ETH_SS_STATS)
1209 return -EOPNOTSUPP;
1210
1211 return ocelot->num_stats;
1212 }
1213 EXPORT_SYMBOL(ocelot_get_sset_count);
1214
1215 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
1216 struct ethtool_ts_info *info)
1217 {
1218 info->phc_index = ocelot->ptp_clock ?
1219 ptp_clock_index(ocelot->ptp_clock) : -1;
1220 if (info->phc_index == -1) {
1221 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1222 SOF_TIMESTAMPING_RX_SOFTWARE |
1223 SOF_TIMESTAMPING_SOFTWARE;
1224 return 0;
1225 }
1226 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1227 SOF_TIMESTAMPING_RX_SOFTWARE |
1228 SOF_TIMESTAMPING_SOFTWARE |
1229 SOF_TIMESTAMPING_TX_HARDWARE |
1230 SOF_TIMESTAMPING_RX_HARDWARE |
1231 SOF_TIMESTAMPING_RAW_HARDWARE;
1232 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
1233 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
1234 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
1235
1236 return 0;
1237 }
1238 EXPORT_SYMBOL(ocelot_get_ts_info);
1239
1240 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond,
1241 bool only_active_ports)
1242 {
1243 u32 mask = 0;
1244 int port;
1245
1246 for (port = 0; port < ocelot->num_phys_ports; port++) {
1247 struct ocelot_port *ocelot_port = ocelot->ports[port];
1248
1249 if (!ocelot_port)
1250 continue;
1251
1252 if (ocelot_port->bond == bond) {
1253 if (only_active_ports && !ocelot_port->lag_tx_active)
1254 continue;
1255
1256 mask |= BIT(port);
1257 }
1258 }
1259
1260 return mask;
1261 }
1262
1263 static u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot,
1264 struct net_device *bridge)
1265 {
1266 u32 mask = 0;
1267 int port;
1268
1269 for (port = 0; port < ocelot->num_phys_ports; port++) {
1270 struct ocelot_port *ocelot_port = ocelot->ports[port];
1271
1272 if (!ocelot_port)
1273 continue;
1274
1275 if (ocelot_port->stp_state == BR_STATE_FORWARDING &&
1276 ocelot_port->bridge == bridge)
1277 mask |= BIT(port);
1278 }
1279
1280 return mask;
1281 }
1282
1283 static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot)
1284 {
1285 u32 mask = 0;
1286 int port;
1287
1288 for (port = 0; port < ocelot->num_phys_ports; port++) {
1289 struct ocelot_port *ocelot_port = ocelot->ports[port];
1290
1291 if (!ocelot_port)
1292 continue;
1293
1294 if (ocelot_port->is_dsa_8021q_cpu)
1295 mask |= BIT(port);
1296 }
1297
1298 return mask;
1299 }
1300
1301 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot)
1302 {
1303 unsigned long cpu_fwd_mask;
1304 int port;
1305
1306 /* If a DSA tag_8021q CPU exists, it needs to be included in the
1307 * regular forwarding path of the front ports regardless of whether
1308 * those are bridged or standalone.
1309 * If DSA tag_8021q is not used, this returns 0, which is fine because
1310 * the hardware-based CPU port module can be a destination for packets
1311 * even if it isn't part of PGID_SRC.
1312 */
1313 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot);
1314
1315 /* Apply FWD mask. The loop is needed to add/remove the current port as
1316 * a source for the other ports.
1317 */
1318 for (port = 0; port < ocelot->num_phys_ports; port++) {
1319 struct ocelot_port *ocelot_port = ocelot->ports[port];
1320 unsigned long mask;
1321
1322 if (!ocelot_port) {
1323 /* Unused ports can't send anywhere */
1324 mask = 0;
1325 } else if (ocelot_port->is_dsa_8021q_cpu) {
1326 /* The DSA tag_8021q CPU ports need to be able to
1327 * forward packets to all other ports except for
1328 * themselves
1329 */
1330 mask = GENMASK(ocelot->num_phys_ports - 1, 0);
1331 mask &= ~cpu_fwd_mask;
1332 } else if (ocelot_port->bridge) {
1333 struct net_device *bridge = ocelot_port->bridge;
1334 struct net_device *bond = ocelot_port->bond;
1335
1336 mask = ocelot_get_bridge_fwd_mask(ocelot, bridge);
1337 mask &= ~BIT(port);
1338 if (bond) {
1339 mask &= ~ocelot_get_bond_mask(ocelot, bond,
1340 false);
1341 }
1342 } else {
1343 /* Standalone ports forward only to DSA tag_8021q CPU
1344 * ports (if those exist), or to the hardware CPU port
1345 * module otherwise.
1346 */
1347 mask = cpu_fwd_mask;
1348 }
1349
1350 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1351 }
1352 }
1353 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask);
1354
1355 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1356 {
1357 struct ocelot_port *ocelot_port = ocelot->ports[port];
1358 u32 learn_ena = 0;
1359
1360 ocelot_port->stp_state = state;
1361
1362 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) &&
1363 ocelot_port->learn_ena)
1364 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA;
1365
1366 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA,
1367 ANA_PORT_PORT_CFG, port);
1368
1369 ocelot_apply_bridge_fwd_mask(ocelot);
1370 }
1371 EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
1372
1373 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
1374 {
1375 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
1376
1377 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
1378 * which is clearly not what our intention is. So avoid that.
1379 */
1380 if (!age_period)
1381 age_period = 1;
1382
1383 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
1384 }
1385 EXPORT_SYMBOL(ocelot_set_ageing_time);
1386
1387 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1388 const unsigned char *addr,
1389 u16 vid)
1390 {
1391 struct ocelot_multicast *mc;
1392
1393 list_for_each_entry(mc, &ocelot->multicast, list) {
1394 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1395 return mc;
1396 }
1397
1398 return NULL;
1399 }
1400
1401 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
1402 {
1403 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
1404 return ENTRYTYPE_MACv4;
1405 if (addr[0] == 0x33 && addr[1] == 0x33)
1406 return ENTRYTYPE_MACv6;
1407 return ENTRYTYPE_LOCKED;
1408 }
1409
1410 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index,
1411 unsigned long ports)
1412 {
1413 struct ocelot_pgid *pgid;
1414
1415 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL);
1416 if (!pgid)
1417 return ERR_PTR(-ENOMEM);
1418
1419 pgid->ports = ports;
1420 pgid->index = index;
1421 refcount_set(&pgid->refcount, 1);
1422 list_add_tail(&pgid->list, &ocelot->pgids);
1423
1424 return pgid;
1425 }
1426
1427 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid)
1428 {
1429 if (!refcount_dec_and_test(&pgid->refcount))
1430 return;
1431
1432 list_del(&pgid->list);
1433 kfree(pgid);
1434 }
1435
1436 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot,
1437 const struct ocelot_multicast *mc)
1438 {
1439 struct ocelot_pgid *pgid;
1440 int index;
1441
1442 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
1443 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
1444 * destination mask table (PGID), the destination set is programmed as
1445 * part of the entry MAC address.", and the DEST_IDX is set to 0.
1446 */
1447 if (mc->entry_type == ENTRYTYPE_MACv4 ||
1448 mc->entry_type == ENTRYTYPE_MACv6)
1449 return ocelot_pgid_alloc(ocelot, 0, mc->ports);
1450
1451 list_for_each_entry(pgid, &ocelot->pgids, list) {
1452 /* When searching for a nonreserved multicast PGID, ignore the
1453 * dummy PGID of zero that we have for MACv4/MACv6 entries
1454 */
1455 if (pgid->index && pgid->ports == mc->ports) {
1456 refcount_inc(&pgid->refcount);
1457 return pgid;
1458 }
1459 }
1460
1461 /* Search for a free index in the nonreserved multicast PGID area */
1462 for_each_nonreserved_multicast_dest_pgid(ocelot, index) {
1463 bool used = false;
1464
1465 list_for_each_entry(pgid, &ocelot->pgids, list) {
1466 if (pgid->index == index) {
1467 used = true;
1468 break;
1469 }
1470 }
1471
1472 if (!used)
1473 return ocelot_pgid_alloc(ocelot, index, mc->ports);
1474 }
1475
1476 return ERR_PTR(-ENOSPC);
1477 }
1478
1479 static void ocelot_encode_ports_to_mdb(unsigned char *addr,
1480 struct ocelot_multicast *mc)
1481 {
1482 ether_addr_copy(addr, mc->addr);
1483
1484 if (mc->entry_type == ENTRYTYPE_MACv4) {
1485 addr[0] = 0;
1486 addr[1] = mc->ports >> 8;
1487 addr[2] = mc->ports & 0xff;
1488 } else if (mc->entry_type == ENTRYTYPE_MACv6) {
1489 addr[0] = mc->ports >> 8;
1490 addr[1] = mc->ports & 0xff;
1491 }
1492 }
1493
1494 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1495 const struct switchdev_obj_port_mdb *mdb)
1496 {
1497 unsigned char addr[ETH_ALEN];
1498 struct ocelot_multicast *mc;
1499 struct ocelot_pgid *pgid;
1500 u16 vid = mdb->vid;
1501
1502 if (port == ocelot->npi)
1503 port = ocelot->num_phys_ports;
1504
1505 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1506 if (!mc) {
1507 /* New entry */
1508 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1509 if (!mc)
1510 return -ENOMEM;
1511
1512 mc->entry_type = ocelot_classify_mdb(mdb->addr);
1513 ether_addr_copy(mc->addr, mdb->addr);
1514 mc->vid = vid;
1515
1516 list_add_tail(&mc->list, &ocelot->multicast);
1517 } else {
1518 /* Existing entry. Clean up the current port mask from
1519 * hardware now, because we'll be modifying it.
1520 */
1521 ocelot_pgid_free(ocelot, mc->pgid);
1522 ocelot_encode_ports_to_mdb(addr, mc);
1523 ocelot_mact_forget(ocelot, addr, vid);
1524 }
1525
1526 mc->ports |= BIT(port);
1527
1528 pgid = ocelot_mdb_get_pgid(ocelot, mc);
1529 if (IS_ERR(pgid)) {
1530 dev_err(ocelot->dev,
1531 "Cannot allocate PGID for mdb %pM vid %d\n",
1532 mc->addr, mc->vid);
1533 devm_kfree(ocelot->dev, mc);
1534 return PTR_ERR(pgid);
1535 }
1536 mc->pgid = pgid;
1537
1538 ocelot_encode_ports_to_mdb(addr, mc);
1539
1540 if (mc->entry_type != ENTRYTYPE_MACv4 &&
1541 mc->entry_type != ENTRYTYPE_MACv6)
1542 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1543 pgid->index);
1544
1545 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1546 mc->entry_type);
1547 }
1548 EXPORT_SYMBOL(ocelot_port_mdb_add);
1549
1550 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
1551 const struct switchdev_obj_port_mdb *mdb)
1552 {
1553 unsigned char addr[ETH_ALEN];
1554 struct ocelot_multicast *mc;
1555 struct ocelot_pgid *pgid;
1556 u16 vid = mdb->vid;
1557
1558 if (port == ocelot->npi)
1559 port = ocelot->num_phys_ports;
1560
1561 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1562 if (!mc)
1563 return -ENOENT;
1564
1565 ocelot_encode_ports_to_mdb(addr, mc);
1566 ocelot_mact_forget(ocelot, addr, vid);
1567
1568 ocelot_pgid_free(ocelot, mc->pgid);
1569 mc->ports &= ~BIT(port);
1570 if (!mc->ports) {
1571 list_del(&mc->list);
1572 devm_kfree(ocelot->dev, mc);
1573 return 0;
1574 }
1575
1576 /* We have a PGID with fewer ports now */
1577 pgid = ocelot_mdb_get_pgid(ocelot, mc);
1578 if (IS_ERR(pgid))
1579 return PTR_ERR(pgid);
1580 mc->pgid = pgid;
1581
1582 ocelot_encode_ports_to_mdb(addr, mc);
1583
1584 if (mc->entry_type != ENTRYTYPE_MACv4 &&
1585 mc->entry_type != ENTRYTYPE_MACv6)
1586 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1587 pgid->index);
1588
1589 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1590 mc->entry_type);
1591 }
1592 EXPORT_SYMBOL(ocelot_port_mdb_del);
1593
1594 void ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1595 struct net_device *bridge)
1596 {
1597 struct ocelot_port *ocelot_port = ocelot->ports[port];
1598
1599 ocelot_port->bridge = bridge;
1600
1601 ocelot_apply_bridge_fwd_mask(ocelot);
1602 }
1603 EXPORT_SYMBOL(ocelot_port_bridge_join);
1604
1605 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1606 struct net_device *bridge)
1607 {
1608 struct ocelot_port *ocelot_port = ocelot->ports[port];
1609 struct ocelot_vlan pvid = {0}, native_vlan = {0};
1610
1611 ocelot_port->bridge = NULL;
1612
1613 ocelot_port_set_pvid(ocelot, port, pvid);
1614 ocelot_port_set_native_vlan(ocelot, port, native_vlan);
1615 ocelot_apply_bridge_fwd_mask(ocelot);
1616 }
1617 EXPORT_SYMBOL(ocelot_port_bridge_leave);
1618
1619 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1620 {
1621 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);
1622 int i, port, lag;
1623
1624 /* Reset destination and aggregation PGIDS */
1625 for_each_unicast_dest_pgid(ocelot, port)
1626 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1627
1628 for_each_aggr_pgid(ocelot, i)
1629 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1630 ANA_PGID_PGID, i);
1631
1632 /* The visited ports bitmask holds the list of ports offloading any
1633 * bonding interface. Initially we mark all these ports as unvisited,
1634 * then every time we visit a port in this bitmask, we know that it is
1635 * the lowest numbered port, i.e. the one whose logical ID == physical
1636 * port ID == LAG ID. So we mark as visited all further ports in the
1637 * bitmask that are offloading the same bonding interface. This way,
1638 * we set up the aggregation PGIDs only once per bonding interface.
1639 */
1640 for (port = 0; port < ocelot->num_phys_ports; port++) {
1641 struct ocelot_port *ocelot_port = ocelot->ports[port];
1642
1643 if (!ocelot_port || !ocelot_port->bond)
1644 continue;
1645
1646 visited &= ~BIT(port);
1647 }
1648
1649 /* Now, set PGIDs for each active LAG */
1650 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1651 struct net_device *bond = ocelot->ports[lag]->bond;
1652 int num_active_ports = 0;
1653 unsigned long bond_mask;
1654 u8 aggr_idx[16];
1655
1656 if (!bond || (visited & BIT(lag)))
1657 continue;
1658
1659 bond_mask = ocelot_get_bond_mask(ocelot, bond, true);
1660
1661 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1662 // Destination mask
1663 ocelot_write_rix(ocelot, bond_mask,
1664 ANA_PGID_PGID, port);
1665 aggr_idx[num_active_ports++] = port;
1666 }
1667
1668 for_each_aggr_pgid(ocelot, i) {
1669 u32 ac;
1670
1671 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1672 ac &= ~bond_mask;
1673 /* Don't do division by zero if there was no active
1674 * port. Just make all aggregation codes zero.
1675 */
1676 if (num_active_ports)
1677 ac |= BIT(aggr_idx[i % num_active_ports]);
1678 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1679 }
1680
1681 /* Mark all ports in the same LAG as visited to avoid applying
1682 * the same config again.
1683 */
1684 for (port = lag; port < ocelot->num_phys_ports; port++) {
1685 struct ocelot_port *ocelot_port = ocelot->ports[port];
1686
1687 if (!ocelot_port)
1688 continue;
1689
1690 if (ocelot_port->bond == bond)
1691 visited |= BIT(port);
1692 }
1693 }
1694 }
1695
1696 /* When offloading a bonding interface, the switch ports configured under the
1697 * same bond must have the same logical port ID, equal to the physical port ID
1698 * of the lowest numbered physical port in that bond. Otherwise, in standalone/
1699 * bridged mode, each port has a logical port ID equal to its physical port ID.
1700 */
1701 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot)
1702 {
1703 int port;
1704
1705 for (port = 0; port < ocelot->num_phys_ports; port++) {
1706 struct ocelot_port *ocelot_port = ocelot->ports[port];
1707 struct net_device *bond;
1708
1709 if (!ocelot_port)
1710 continue;
1711
1712 bond = ocelot_port->bond;
1713 if (bond) {
1714 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond,
1715 false));
1716
1717 ocelot_rmw_gix(ocelot,
1718 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1719 ANA_PORT_PORT_CFG_PORTID_VAL_M,
1720 ANA_PORT_PORT_CFG, port);
1721 } else {
1722 ocelot_rmw_gix(ocelot,
1723 ANA_PORT_PORT_CFG_PORTID_VAL(port),
1724 ANA_PORT_PORT_CFG_PORTID_VAL_M,
1725 ANA_PORT_PORT_CFG, port);
1726 }
1727 }
1728 }
1729
1730 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1731 struct net_device *bond,
1732 struct netdev_lag_upper_info *info)
1733 {
1734 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
1735 return -EOPNOTSUPP;
1736
1737 ocelot->ports[port]->bond = bond;
1738
1739 ocelot_setup_logical_port_ids(ocelot);
1740 ocelot_apply_bridge_fwd_mask(ocelot);
1741 ocelot_set_aggr_pgids(ocelot);
1742
1743 return 0;
1744 }
1745 EXPORT_SYMBOL(ocelot_port_lag_join);
1746
1747 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1748 struct net_device *bond)
1749 {
1750 ocelot->ports[port]->bond = NULL;
1751
1752 ocelot_setup_logical_port_ids(ocelot);
1753 ocelot_apply_bridge_fwd_mask(ocelot);
1754 ocelot_set_aggr_pgids(ocelot);
1755 }
1756 EXPORT_SYMBOL(ocelot_port_lag_leave);
1757
1758 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active)
1759 {
1760 struct ocelot_port *ocelot_port = ocelot->ports[port];
1761
1762 ocelot_port->lag_tx_active = lag_tx_active;
1763
1764 /* Rebalance the LAGs */
1765 ocelot_set_aggr_pgids(ocelot);
1766 }
1767 EXPORT_SYMBOL(ocelot_port_lag_change);
1768
1769 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
1770 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
1771 * In the special case that it's the NPI port that we're configuring, the
1772 * length of the tag and optional prefix needs to be accounted for privately,
1773 * in order to be able to sustain communication at the requested @sdu.
1774 */
1775 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
1776 {
1777 struct ocelot_port *ocelot_port = ocelot->ports[port];
1778 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
1779 int pause_start, pause_stop;
1780 int atop, atop_tot;
1781
1782 if (port == ocelot->npi) {
1783 maxlen += OCELOT_TAG_LEN;
1784
1785 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
1786 maxlen += OCELOT_SHORT_PREFIX_LEN;
1787 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
1788 maxlen += OCELOT_LONG_PREFIX_LEN;
1789 }
1790
1791 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
1792
1793 /* Set Pause watermark hysteresis */
1794 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
1795 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
1796 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
1797 pause_start);
1798 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
1799 pause_stop);
1800
1801 /* Tail dropping watermarks */
1802 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
1803 OCELOT_BUFFER_CELL_SZ;
1804 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
1805 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
1806 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
1807 }
1808 EXPORT_SYMBOL(ocelot_port_set_maxlen);
1809
1810 int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
1811 {
1812 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
1813
1814 if (port == ocelot->npi) {
1815 max_mtu -= OCELOT_TAG_LEN;
1816
1817 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
1818 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
1819 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
1820 max_mtu -= OCELOT_LONG_PREFIX_LEN;
1821 }
1822
1823 return max_mtu;
1824 }
1825 EXPORT_SYMBOL(ocelot_get_max_mtu);
1826
1827 static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
1828 bool enabled)
1829 {
1830 struct ocelot_port *ocelot_port = ocelot->ports[port];
1831 u32 val = 0;
1832
1833 if (enabled)
1834 val = ANA_PORT_PORT_CFG_LEARN_ENA;
1835
1836 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
1837 ANA_PORT_PORT_CFG, port);
1838
1839 ocelot_port->learn_ena = enabled;
1840 }
1841
1842 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
1843 bool enabled)
1844 {
1845 u32 val = 0;
1846
1847 if (enabled)
1848 val = BIT(port);
1849
1850 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
1851 }
1852
1853 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
1854 bool enabled)
1855 {
1856 u32 val = 0;
1857
1858 if (enabled)
1859 val = BIT(port);
1860
1861 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
1862 }
1863
1864 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
1865 bool enabled)
1866 {
1867 u32 val = 0;
1868
1869 if (enabled)
1870 val = BIT(port);
1871
1872 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
1873 }
1874
1875 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
1876 struct switchdev_brport_flags flags)
1877 {
1878 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1879 BR_BCAST_FLOOD))
1880 return -EINVAL;
1881
1882 return 0;
1883 }
1884 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags);
1885
1886 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
1887 struct switchdev_brport_flags flags)
1888 {
1889 if (flags.mask & BR_LEARNING)
1890 ocelot_port_set_learning(ocelot, port,
1891 !!(flags.val & BR_LEARNING));
1892
1893 if (flags.mask & BR_FLOOD)
1894 ocelot_port_set_ucast_flood(ocelot, port,
1895 !!(flags.val & BR_FLOOD));
1896
1897 if (flags.mask & BR_MCAST_FLOOD)
1898 ocelot_port_set_mcast_flood(ocelot, port,
1899 !!(flags.val & BR_MCAST_FLOOD));
1900
1901 if (flags.mask & BR_BCAST_FLOOD)
1902 ocelot_port_set_bcast_flood(ocelot, port,
1903 !!(flags.val & BR_BCAST_FLOOD));
1904 }
1905 EXPORT_SYMBOL(ocelot_port_bridge_flags);
1906
1907 void ocelot_init_port(struct ocelot *ocelot, int port)
1908 {
1909 struct ocelot_port *ocelot_port = ocelot->ports[port];
1910
1911 skb_queue_head_init(&ocelot_port->tx_skbs);
1912 spin_lock_init(&ocelot_port->ts_id_lock);
1913
1914 /* Basic L2 initialization */
1915
1916 /* Set MAC IFG Gaps
1917 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
1918 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
1919 */
1920 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
1921 DEV_MAC_IFG_CFG);
1922
1923 /* Load seed (0) and set MAC HDX late collision */
1924 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
1925 DEV_MAC_HDX_CFG_SEED_LOAD,
1926 DEV_MAC_HDX_CFG);
1927 mdelay(1);
1928 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
1929 DEV_MAC_HDX_CFG);
1930
1931 /* Set Max Length and maximum tags allowed */
1932 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
1933 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
1934 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
1935 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
1936 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
1937 DEV_MAC_TAGS_CFG);
1938
1939 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
1940 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
1941 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
1942
1943 /* Enable transmission of pause frames */
1944 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
1945
1946 /* Drop frames with multicast source address */
1947 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
1948 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
1949 ANA_PORT_DROP_CFG, port);
1950
1951 /* Set default VLAN and tag type to 8021Q. */
1952 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
1953 REW_PORT_VLAN_CFG_PORT_TPID_M,
1954 REW_PORT_VLAN_CFG, port);
1955
1956 /* Disable source address learning for standalone mode */
1957 ocelot_port_set_learning(ocelot, port, false);
1958
1959 /* Enable vcap lookups */
1960 ocelot_vcap_enable(ocelot, port);
1961 }
1962 EXPORT_SYMBOL(ocelot_init_port);
1963
1964 /* Configure and enable the CPU port module, which is a set of queues
1965 * accessible through register MMIO, frame DMA or Ethernet (in case
1966 * NPI mode is used).
1967 */
1968 static void ocelot_cpu_port_init(struct ocelot *ocelot)
1969 {
1970 int cpu = ocelot->num_phys_ports;
1971
1972 /* The unicast destination PGID for the CPU port module is unused */
1973 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
1974 /* Instead set up a multicast destination PGID for traffic copied to
1975 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
1976 * addresses will be copied to the CPU via this PGID.
1977 */
1978 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
1979 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
1980 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
1981 ANA_PORT_PORT_CFG, cpu);
1982
1983 /* Enable CPU port module */
1984 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
1985 /* CPU port Injection/Extraction configuration */
1986 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
1987 OCELOT_TAG_PREFIX_NONE);
1988 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
1989 OCELOT_TAG_PREFIX_NONE);
1990
1991 /* Configure the CPU port to be VLAN aware */
1992 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
1993 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
1994 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
1995 ANA_PORT_VLAN_CFG, cpu);
1996 }
1997
1998 static void ocelot_detect_features(struct ocelot *ocelot)
1999 {
2000 int mmgt, eq_ctrl;
2001
2002 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
2003 * the number of 240-byte free memory words (aka 4-cell chunks) and not
2004 * 192 bytes as the documentation incorrectly says.
2005 */
2006 mmgt = ocelot_read(ocelot, SYS_MMGT);
2007 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
2008
2009 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
2010 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
2011 }
2012
2013 int ocelot_init(struct ocelot *ocelot)
2014 {
2015 char queue_name[32];
2016 int i, ret;
2017 u32 port;
2018
2019 if (ocelot->ops->reset) {
2020 ret = ocelot->ops->reset(ocelot);
2021 if (ret) {
2022 dev_err(ocelot->dev, "Switch reset failed\n");
2023 return ret;
2024 }
2025 }
2026
2027 ocelot->stats = devm_kcalloc(ocelot->dev,
2028 ocelot->num_phys_ports * ocelot->num_stats,
2029 sizeof(u64), GFP_KERNEL);
2030 if (!ocelot->stats)
2031 return -ENOMEM;
2032
2033 mutex_init(&ocelot->stats_lock);
2034 mutex_init(&ocelot->ptp_lock);
2035 spin_lock_init(&ocelot->ptp_clock_lock);
2036 snprintf(queue_name, sizeof(queue_name), "%s-stats",
2037 dev_name(ocelot->dev));
2038 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
2039 if (!ocelot->stats_queue)
2040 return -ENOMEM;
2041
2042 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
2043 if (!ocelot->owq) {
2044 destroy_workqueue(ocelot->stats_queue);
2045 return -ENOMEM;
2046 }
2047
2048 INIT_LIST_HEAD(&ocelot->multicast);
2049 INIT_LIST_HEAD(&ocelot->pgids);
2050 ocelot_detect_features(ocelot);
2051 ocelot_mact_init(ocelot);
2052 ocelot_vlan_init(ocelot);
2053 ocelot_vcap_init(ocelot);
2054 ocelot_cpu_port_init(ocelot);
2055
2056 for (port = 0; port < ocelot->num_phys_ports; port++) {
2057 /* Clear all counters (5 groups) */
2058 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
2059 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
2060 SYS_STAT_CFG);
2061 }
2062
2063 /* Only use S-Tag */
2064 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
2065
2066 /* Aggregation mode */
2067 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
2068 ANA_AGGR_CFG_AC_DMAC_ENA |
2069 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
2070 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA |
2071 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA |
2072 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA,
2073 ANA_AGGR_CFG);
2074
2075 /* Set MAC age time to default value. The entry is aged after
2076 * 2*AGE_PERIOD
2077 */
2078 ocelot_write(ocelot,
2079 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
2080 ANA_AUTOAGE);
2081
2082 /* Disable learning for frames discarded by VLAN ingress filtering */
2083 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
2084
2085 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
2086 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
2087 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
2088
2089 /* Setup flooding PGIDs */
2090 for (i = 0; i < ocelot->num_flooding_pgids; i++)
2091 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
2092 ANA_FLOODING_FLD_BROADCAST(PGID_BC) |
2093 ANA_FLOODING_FLD_UNICAST(PGID_UC),
2094 ANA_FLOODING, i);
2095 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
2096 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
2097 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
2098 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
2099 ANA_FLOODING_IPMC);
2100
2101 for (port = 0; port < ocelot->num_phys_ports; port++) {
2102 /* Transmit the frame to the local port. */
2103 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2104 /* Do not forward BPDU frames to the front ports. */
2105 ocelot_write_gix(ocelot,
2106 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2107 ANA_PORT_CPU_FWD_BPDU_CFG,
2108 port);
2109 /* Ensure bridging is disabled */
2110 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
2111 }
2112
2113 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
2114 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
2115
2116 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
2117 }
2118
2119 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE);
2120
2121 /* Allow broadcast and unknown L2 multicast to the CPU. */
2122 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2123 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2124 ANA_PGID_PGID, PGID_MC);
2125 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2126 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2127 ANA_PGID_PGID, PGID_BC);
2128 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
2129 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
2130
2131 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
2132 * registers endianness.
2133 */
2134 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
2135 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
2136 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
2137 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
2138 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
2139 ANA_CPUQ_CFG_CPUQ_LRN(2) |
2140 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
2141 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
2142 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
2143 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
2144 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
2145 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
2146 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
2147 for (i = 0; i < 16; i++)
2148 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
2149 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
2150 ANA_CPUQ_8021_CFG, i);
2151
2152 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work);
2153 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
2154 OCELOT_STATS_CHECK_DELAY);
2155
2156 return 0;
2157 }
2158 EXPORT_SYMBOL(ocelot_init);
2159
2160 void ocelot_deinit(struct ocelot *ocelot)
2161 {
2162 cancel_delayed_work(&ocelot->stats_work);
2163 destroy_workqueue(ocelot->stats_queue);
2164 destroy_workqueue(ocelot->owq);
2165 mutex_destroy(&ocelot->stats_lock);
2166 }
2167 EXPORT_SYMBOL(ocelot_deinit);
2168
2169 void ocelot_deinit_port(struct ocelot *ocelot, int port)
2170 {
2171 struct ocelot_port *ocelot_port = ocelot->ports[port];
2172
2173 skb_queue_purge(&ocelot_port->tx_skbs);
2174 }
2175 EXPORT_SYMBOL(ocelot_deinit_port);
2176
2177 MODULE_LICENSE("Dual MIT/GPL");
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