1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
7 #include <linux/if_bridge.h>
9 #include "ocelot_vcap.h"
11 #define TABLE_UPDATE_SLEEP_US 10
12 #define TABLE_UPDATE_TIMEOUT_US 100000
14 struct ocelot_mact_entry
{
17 enum macaccess_entry_type type
;
20 static inline u32
ocelot_mact_read_macaccess(struct ocelot
*ocelot
)
22 return ocelot_read(ocelot
, ANA_TABLES_MACACCESS
);
25 static inline int ocelot_mact_wait_for_completion(struct ocelot
*ocelot
)
29 return readx_poll_timeout(ocelot_mact_read_macaccess
,
31 (val
& ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M
) ==
33 TABLE_UPDATE_SLEEP_US
, TABLE_UPDATE_TIMEOUT_US
);
36 static void ocelot_mact_select(struct ocelot
*ocelot
,
37 const unsigned char mac
[ETH_ALEN
],
40 u32 macl
= 0, mach
= 0;
42 /* Set the MAC address to handle and the vlan associated in a format
43 * understood by the hardware.
53 ocelot_write(ocelot
, macl
, ANA_TABLES_MACLDATA
);
54 ocelot_write(ocelot
, mach
, ANA_TABLES_MACHDATA
);
58 int ocelot_mact_learn(struct ocelot
*ocelot
, int port
,
59 const unsigned char mac
[ETH_ALEN
],
60 unsigned int vid
, enum macaccess_entry_type type
)
62 ocelot_mact_select(ocelot
, mac
, vid
);
64 /* Issue a write command */
65 ocelot_write(ocelot
, ANA_TABLES_MACACCESS_VALID
|
66 ANA_TABLES_MACACCESS_DEST_IDX(port
) |
67 ANA_TABLES_MACACCESS_ENTRYTYPE(type
) |
68 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN
),
69 ANA_TABLES_MACACCESS
);
71 return ocelot_mact_wait_for_completion(ocelot
);
73 EXPORT_SYMBOL(ocelot_mact_learn
);
75 int ocelot_mact_forget(struct ocelot
*ocelot
,
76 const unsigned char mac
[ETH_ALEN
], unsigned int vid
)
78 ocelot_mact_select(ocelot
, mac
, vid
);
80 /* Issue a forget command */
82 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET
),
83 ANA_TABLES_MACACCESS
);
85 return ocelot_mact_wait_for_completion(ocelot
);
87 EXPORT_SYMBOL(ocelot_mact_forget
);
89 static void ocelot_mact_init(struct ocelot
*ocelot
)
91 /* Configure the learning mode entries attributes:
92 * - Do not copy the frame to the CPU extraction queues.
93 * - Use the vlan and mac_cpoy for dmac lookup.
96 ANA_AGENCTRL_LEARN_CPU_COPY
| ANA_AGENCTRL_IGNORE_DMAC_FLAGS
97 | ANA_AGENCTRL_LEARN_FWD_KILL
98 | ANA_AGENCTRL_LEARN_IGNORE_VLAN
,
101 /* Clear the MAC table */
102 ocelot_write(ocelot
, MACACCESS_CMD_INIT
, ANA_TABLES_MACACCESS
);
105 static void ocelot_vcap_enable(struct ocelot
*ocelot
, int port
)
107 ocelot_write_gix(ocelot
, ANA_PORT_VCAP_S2_CFG_S2_ENA
|
108 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
109 ANA_PORT_VCAP_S2_CFG
, port
);
112 static inline u32
ocelot_vlant_read_vlanaccess(struct ocelot
*ocelot
)
114 return ocelot_read(ocelot
, ANA_TABLES_VLANACCESS
);
117 static inline int ocelot_vlant_wait_for_completion(struct ocelot
*ocelot
)
121 return readx_poll_timeout(ocelot_vlant_read_vlanaccess
,
124 (val
& ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M
) ==
125 ANA_TABLES_VLANACCESS_CMD_IDLE
,
126 TABLE_UPDATE_SLEEP_US
, TABLE_UPDATE_TIMEOUT_US
);
129 static int ocelot_vlant_set_mask(struct ocelot
*ocelot
, u16 vid
, u32 mask
)
131 /* Select the VID to configure */
132 ocelot_write(ocelot
, ANA_TABLES_VLANTIDX_V_INDEX(vid
),
133 ANA_TABLES_VLANTIDX
);
134 /* Set the vlan port members mask and issue a write command */
135 ocelot_write(ocelot
, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask
) |
136 ANA_TABLES_VLANACCESS_CMD_WRITE
,
137 ANA_TABLES_VLANACCESS
);
139 return ocelot_vlant_wait_for_completion(ocelot
);
142 static int ocelot_port_set_native_vlan(struct ocelot
*ocelot
, int port
,
145 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
148 if (ocelot_port
->vid
!= vid
) {
149 /* Always permit deleting the native VLAN (vid = 0) */
150 if (ocelot_port
->vid
&& vid
) {
152 "Port already has a native VLAN: %d\n",
156 ocelot_port
->vid
= vid
;
159 ocelot_rmw_gix(ocelot
, REW_PORT_VLAN_CFG_PORT_VID(vid
),
160 REW_PORT_VLAN_CFG_PORT_VID_M
,
161 REW_PORT_VLAN_CFG
, port
);
163 if (ocelot_port
->vlan_aware
&& !ocelot_port
->vid
)
164 /* If port is vlan-aware and tagged, drop untagged and priority
167 val
= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA
|
168 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA
|
169 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA
;
170 ocelot_rmw_gix(ocelot
, val
,
171 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA
|
172 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA
|
173 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA
,
174 ANA_PORT_DROP_CFG
, port
);
176 if (ocelot_port
->vlan_aware
) {
177 if (ocelot_port
->vid
)
178 /* Tag all frames except when VID == DEFAULT_VLAN */
179 val
= REW_TAG_CFG_TAG_CFG(1);
182 val
= REW_TAG_CFG_TAG_CFG(3);
184 /* Port tagging disabled. */
185 val
= REW_TAG_CFG_TAG_CFG(0);
187 ocelot_rmw_gix(ocelot
, val
,
188 REW_TAG_CFG_TAG_CFG_M
,
194 void ocelot_port_vlan_filtering(struct ocelot
*ocelot
, int port
,
197 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
200 ocelot_port
->vlan_aware
= vlan_aware
;
203 val
= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA
|
204 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
207 ocelot_rmw_gix(ocelot
, val
,
208 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA
|
209 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M
,
210 ANA_PORT_VLAN_CFG
, port
);
212 ocelot_port_set_native_vlan(ocelot
, port
, ocelot_port
->vid
);
214 EXPORT_SYMBOL(ocelot_port_vlan_filtering
);
216 /* Default vlan to clasify for untagged frames (may be zero) */
217 static void ocelot_port_set_pvid(struct ocelot
*ocelot
, int port
, u16 pvid
)
219 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
221 ocelot_rmw_gix(ocelot
,
222 ANA_PORT_VLAN_CFG_VLAN_VID(pvid
),
223 ANA_PORT_VLAN_CFG_VLAN_VID_M
,
224 ANA_PORT_VLAN_CFG
, port
);
226 ocelot_port
->pvid
= pvid
;
229 int ocelot_vlan_add(struct ocelot
*ocelot
, int port
, u16 vid
, bool pvid
,
234 /* Make the port a member of the VLAN */
235 ocelot
->vlan_mask
[vid
] |= BIT(port
);
236 ret
= ocelot_vlant_set_mask(ocelot
, vid
, ocelot
->vlan_mask
[vid
]);
240 /* Default ingress vlan classification */
242 ocelot_port_set_pvid(ocelot
, port
, vid
);
244 /* Untagged egress vlan clasification */
246 ret
= ocelot_port_set_native_vlan(ocelot
, port
, vid
);
253 EXPORT_SYMBOL(ocelot_vlan_add
);
255 int ocelot_vlan_del(struct ocelot
*ocelot
, int port
, u16 vid
)
257 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
260 /* Stop the port from being a member of the vlan */
261 ocelot
->vlan_mask
[vid
] &= ~BIT(port
);
262 ret
= ocelot_vlant_set_mask(ocelot
, vid
, ocelot
->vlan_mask
[vid
]);
267 if (ocelot_port
->pvid
== vid
)
268 ocelot_port_set_pvid(ocelot
, port
, 0);
271 if (ocelot_port
->vid
== vid
)
272 ocelot_port_set_native_vlan(ocelot
, port
, 0);
276 EXPORT_SYMBOL(ocelot_vlan_del
);
278 static void ocelot_vlan_init(struct ocelot
*ocelot
)
282 /* Clear VLAN table, by default all ports are members of all VLANs */
283 ocelot_write(ocelot
, ANA_TABLES_VLANACCESS_CMD_INIT
,
284 ANA_TABLES_VLANACCESS
);
285 ocelot_vlant_wait_for_completion(ocelot
);
287 /* Configure the port VLAN memberships */
288 for (vid
= 1; vid
< VLAN_N_VID
; vid
++) {
289 ocelot
->vlan_mask
[vid
] = 0;
290 ocelot_vlant_set_mask(ocelot
, vid
, ocelot
->vlan_mask
[vid
]);
293 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
294 * traffic. It is added automatically if 8021q module is loaded, but
295 * we can't rely on it since module may be not loaded.
297 ocelot
->vlan_mask
[0] = GENMASK(ocelot
->num_phys_ports
- 1, 0);
298 ocelot_vlant_set_mask(ocelot
, 0, ocelot
->vlan_mask
[0]);
300 /* Set vlan ingress filter mask to all ports but the CPU port by
303 ocelot_write(ocelot
, GENMASK(ocelot
->num_phys_ports
- 1, 0),
306 for (port
= 0; port
< ocelot
->num_phys_ports
; port
++) {
307 ocelot_write_gix(ocelot
, 0, REW_PORT_VLAN_CFG
, port
);
308 ocelot_write_gix(ocelot
, 0, REW_TAG_CFG
, port
);
312 void ocelot_adjust_link(struct ocelot
*ocelot
, int port
,
313 struct phy_device
*phydev
)
315 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
318 switch (phydev
->speed
) {
320 speed
= OCELOT_SPEED_10
;
323 speed
= OCELOT_SPEED_100
;
326 speed
= OCELOT_SPEED_1000
;
327 mode
= DEV_MAC_MODE_CFG_GIGA_MODE_ENA
;
330 speed
= OCELOT_SPEED_2500
;
331 mode
= DEV_MAC_MODE_CFG_GIGA_MODE_ENA
;
334 dev_err(ocelot
->dev
, "Unsupported PHY speed on port %d: %d\n",
335 port
, phydev
->speed
);
339 phy_print_status(phydev
);
344 /* Only full duplex supported for now */
345 ocelot_port_writel(ocelot_port
, DEV_MAC_MODE_CFG_FDX_ENA
|
346 mode
, DEV_MAC_MODE_CFG
);
348 /* Disable HDX fast control */
349 ocelot_port_writel(ocelot_port
, DEV_PORT_MISC_HDX_FAST_DIS
,
352 /* SGMII only for now */
353 ocelot_port_writel(ocelot_port
, PCS1G_MODE_CFG_SGMII_MODE_ENA
,
355 ocelot_port_writel(ocelot_port
, PCS1G_SD_CFG_SD_SEL
, PCS1G_SD_CFG
);
358 ocelot_port_writel(ocelot_port
, PCS1G_CFG_PCS_ENA
, PCS1G_CFG
);
360 /* No aneg on SGMII */
361 ocelot_port_writel(ocelot_port
, 0, PCS1G_ANEG_CFG
);
364 ocelot_port_writel(ocelot_port
, 0, PCS1G_LB_CFG
);
366 /* Enable MAC module */
367 ocelot_port_writel(ocelot_port
, DEV_MAC_ENA_CFG_RX_ENA
|
368 DEV_MAC_ENA_CFG_TX_ENA
, DEV_MAC_ENA_CFG
);
370 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
372 ocelot_port_writel(ocelot_port
, DEV_CLOCK_CFG_LINK_SPEED(speed
),
376 ocelot_write_gix(ocelot
, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed
),
377 ANA_PFC_PFC_CFG
, port
);
379 /* Core: Enable port for frame transfer */
380 ocelot_fields_write(ocelot
, port
,
381 QSYS_SWITCH_PORT_MODE_PORT_ENA
, 1);
384 ocelot_write_rix(ocelot
, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
385 SYS_MAC_FC_CFG_RX_FC_ENA
| SYS_MAC_FC_CFG_TX_FC_ENA
|
386 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA
|
387 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
388 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed
),
389 SYS_MAC_FC_CFG
, port
);
390 ocelot_write_rix(ocelot
, 0, ANA_POL_FLOWC
, port
);
392 EXPORT_SYMBOL(ocelot_adjust_link
);
394 void ocelot_port_enable(struct ocelot
*ocelot
, int port
,
395 struct phy_device
*phy
)
397 /* Enable receiving frames on the port, and activate auto-learning of
400 ocelot_write_gix(ocelot
, ANA_PORT_PORT_CFG_LEARNAUTO
|
401 ANA_PORT_PORT_CFG_RECV_ENA
|
402 ANA_PORT_PORT_CFG_PORTID_VAL(port
),
403 ANA_PORT_PORT_CFG
, port
);
405 EXPORT_SYMBOL(ocelot_port_enable
);
407 void ocelot_port_disable(struct ocelot
*ocelot
, int port
)
409 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
411 ocelot_port_writel(ocelot_port
, 0, DEV_MAC_ENA_CFG
);
412 ocelot_fields_write(ocelot
, port
, QSYS_SWITCH_PORT_MODE_PORT_ENA
, 0);
414 EXPORT_SYMBOL(ocelot_port_disable
);
416 int ocelot_port_add_txtstamp_skb(struct ocelot_port
*ocelot_port
,
419 struct skb_shared_info
*shinfo
= skb_shinfo(skb
);
420 struct ocelot
*ocelot
= ocelot_port
->ocelot
;
422 if (ocelot
->ptp
&& shinfo
->tx_flags
& SKBTX_HW_TSTAMP
&&
423 ocelot_port
->ptp_cmd
== IFH_REW_OP_TWO_STEP_PTP
) {
424 shinfo
->tx_flags
|= SKBTX_IN_PROGRESS
;
425 /* Store timestamp ID in cb[0] of sk_buff */
426 skb
->cb
[0] = ocelot_port
->ts_id
% 4;
427 skb_queue_tail(&ocelot_port
->tx_skbs
, skb
);
432 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb
);
434 static void ocelot_get_hwtimestamp(struct ocelot
*ocelot
,
435 struct timespec64
*ts
)
440 spin_lock_irqsave(&ocelot
->ptp_clock_lock
, flags
);
442 /* Read current PTP time to get seconds */
443 val
= ocelot_read_rix(ocelot
, PTP_PIN_CFG
, TOD_ACC_PIN
);
445 val
&= ~(PTP_PIN_CFG_SYNC
| PTP_PIN_CFG_ACTION_MASK
| PTP_PIN_CFG_DOM
);
446 val
|= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE
);
447 ocelot_write_rix(ocelot
, val
, PTP_PIN_CFG
, TOD_ACC_PIN
);
448 ts
->tv_sec
= ocelot_read_rix(ocelot
, PTP_PIN_TOD_SEC_LSB
, TOD_ACC_PIN
);
450 /* Read packet HW timestamp from FIFO */
451 val
= ocelot_read(ocelot
, SYS_PTP_TXSTAMP
);
452 ts
->tv_nsec
= SYS_PTP_TXSTAMP_PTP_TXSTAMP(val
);
454 /* Sec has incremented since the ts was registered */
455 if ((ts
->tv_sec
& 0x1) != !!(val
& SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC
))
458 spin_unlock_irqrestore(&ocelot
->ptp_clock_lock
, flags
);
461 void ocelot_get_txtstamp(struct ocelot
*ocelot
)
463 int budget
= OCELOT_PTP_QUEUE_SZ
;
466 struct sk_buff
*skb
, *skb_tmp
, *skb_match
= NULL
;
467 struct skb_shared_hwtstamps shhwtstamps
;
468 struct ocelot_port
*port
;
469 struct timespec64 ts
;
473 val
= ocelot_read(ocelot
, SYS_PTP_STATUS
);
475 /* Check if a timestamp can be retrieved */
476 if (!(val
& SYS_PTP_STATUS_PTP_MESS_VLD
))
479 WARN_ON(val
& SYS_PTP_STATUS_PTP_OVFL
);
481 /* Retrieve the ts ID and Tx port */
482 id
= SYS_PTP_STATUS_PTP_MESS_ID_X(val
);
483 txport
= SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val
);
485 /* Retrieve its associated skb */
486 port
= ocelot
->ports
[txport
];
488 spin_lock_irqsave(&port
->tx_skbs
.lock
, flags
);
490 skb_queue_walk_safe(&port
->tx_skbs
, skb
, skb_tmp
) {
491 if (skb
->cb
[0] != id
)
493 __skb_unlink(skb
, &port
->tx_skbs
);
498 spin_unlock_irqrestore(&port
->tx_skbs
.lock
, flags
);
500 /* Get the h/w timestamp */
501 ocelot_get_hwtimestamp(ocelot
, &ts
);
503 if (unlikely(!skb_match
))
506 /* Set the timestamp into the skb */
507 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
508 shhwtstamps
.hwtstamp
= ktime_set(ts
.tv_sec
, ts
.tv_nsec
);
509 skb_tstamp_tx(skb_match
, &shhwtstamps
);
511 dev_kfree_skb_any(skb_match
);
514 ocelot_write(ocelot
, SYS_PTP_NXT_PTP_NXT
, SYS_PTP_NXT
);
517 EXPORT_SYMBOL(ocelot_get_txtstamp
);
519 int ocelot_fdb_add(struct ocelot
*ocelot
, int port
,
520 const unsigned char *addr
, u16 vid
)
522 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
525 if (port
== ocelot
->npi
)
529 if (!ocelot_port
->vlan_aware
)
530 /* If the bridge is not VLAN aware and no VID was
531 * provided, set it to pvid to ensure the MAC entry
532 * matches incoming untagged packets
534 vid
= ocelot_port
->pvid
;
536 /* If the bridge is VLAN aware a VID must be provided as
537 * otherwise the learnt entry wouldn't match any frame.
542 return ocelot_mact_learn(ocelot
, pgid
, addr
, vid
, ENTRYTYPE_LOCKED
);
544 EXPORT_SYMBOL(ocelot_fdb_add
);
546 int ocelot_fdb_del(struct ocelot
*ocelot
, int port
,
547 const unsigned char *addr
, u16 vid
)
549 return ocelot_mact_forget(ocelot
, addr
, vid
);
551 EXPORT_SYMBOL(ocelot_fdb_del
);
553 int ocelot_port_fdb_do_dump(const unsigned char *addr
, u16 vid
,
554 bool is_static
, void *data
)
556 struct ocelot_dump_ctx
*dump
= data
;
557 u32 portid
= NETLINK_CB(dump
->cb
->skb
).portid
;
558 u32 seq
= dump
->cb
->nlh
->nlmsg_seq
;
559 struct nlmsghdr
*nlh
;
562 if (dump
->idx
< dump
->cb
->args
[2])
565 nlh
= nlmsg_put(dump
->skb
, portid
, seq
, RTM_NEWNEIGH
,
566 sizeof(*ndm
), NLM_F_MULTI
);
570 ndm
= nlmsg_data(nlh
);
571 ndm
->ndm_family
= AF_BRIDGE
;
574 ndm
->ndm_flags
= NTF_SELF
;
576 ndm
->ndm_ifindex
= dump
->dev
->ifindex
;
577 ndm
->ndm_state
= is_static
? NUD_NOARP
: NUD_REACHABLE
;
579 if (nla_put(dump
->skb
, NDA_LLADDR
, ETH_ALEN
, addr
))
580 goto nla_put_failure
;
582 if (vid
&& nla_put_u16(dump
->skb
, NDA_VLAN
, vid
))
583 goto nla_put_failure
;
585 nlmsg_end(dump
->skb
, nlh
);
592 nlmsg_cancel(dump
->skb
, nlh
);
595 EXPORT_SYMBOL(ocelot_port_fdb_do_dump
);
597 static int ocelot_mact_read(struct ocelot
*ocelot
, int port
, int row
, int col
,
598 struct ocelot_mact_entry
*entry
)
600 u32 val
, dst
, macl
, mach
;
603 /* Set row and column to read from */
604 ocelot_field_write(ocelot
, ANA_TABLES_MACTINDX_M_INDEX
, row
);
605 ocelot_field_write(ocelot
, ANA_TABLES_MACTINDX_BUCKET
, col
);
607 /* Issue a read command */
609 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ
),
610 ANA_TABLES_MACACCESS
);
612 if (ocelot_mact_wait_for_completion(ocelot
))
615 /* Read the entry flags */
616 val
= ocelot_read(ocelot
, ANA_TABLES_MACACCESS
);
617 if (!(val
& ANA_TABLES_MACACCESS_VALID
))
620 /* If the entry read has another port configured as its destination,
623 dst
= (val
& ANA_TABLES_MACACCESS_DEST_IDX_M
) >> 3;
627 /* Get the entry's MAC address and VLAN id */
628 macl
= ocelot_read(ocelot
, ANA_TABLES_MACLDATA
);
629 mach
= ocelot_read(ocelot
, ANA_TABLES_MACHDATA
);
631 mac
[0] = (mach
>> 8) & 0xff;
632 mac
[1] = (mach
>> 0) & 0xff;
633 mac
[2] = (macl
>> 24) & 0xff;
634 mac
[3] = (macl
>> 16) & 0xff;
635 mac
[4] = (macl
>> 8) & 0xff;
636 mac
[5] = (macl
>> 0) & 0xff;
638 entry
->vid
= (mach
>> 16) & 0xfff;
639 ether_addr_copy(entry
->mac
, mac
);
644 int ocelot_fdb_dump(struct ocelot
*ocelot
, int port
,
645 dsa_fdb_dump_cb_t
*cb
, void *data
)
649 /* Loop through all the mac tables entries. */
650 for (i
= 0; i
< ocelot
->num_mact_rows
; i
++) {
651 for (j
= 0; j
< 4; j
++) {
652 struct ocelot_mact_entry entry
;
656 ret
= ocelot_mact_read(ocelot
, port
, i
, j
, &entry
);
657 /* If the entry is invalid (wrong port, invalid...),
665 is_static
= (entry
.type
== ENTRYTYPE_LOCKED
);
667 ret
= cb(entry
.mac
, entry
.vid
, is_static
, data
);
675 EXPORT_SYMBOL(ocelot_fdb_dump
);
677 int ocelot_hwstamp_get(struct ocelot
*ocelot
, int port
, struct ifreq
*ifr
)
679 return copy_to_user(ifr
->ifr_data
, &ocelot
->hwtstamp_config
,
680 sizeof(ocelot
->hwtstamp_config
)) ? -EFAULT
: 0;
682 EXPORT_SYMBOL(ocelot_hwstamp_get
);
684 int ocelot_hwstamp_set(struct ocelot
*ocelot
, int port
, struct ifreq
*ifr
)
686 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
687 struct hwtstamp_config cfg
;
689 if (copy_from_user(&cfg
, ifr
->ifr_data
, sizeof(cfg
)))
692 /* reserved for future extensions */
696 /* Tx type sanity check */
697 switch (cfg
.tx_type
) {
699 ocelot_port
->ptp_cmd
= IFH_REW_OP_TWO_STEP_PTP
;
701 case HWTSTAMP_TX_ONESTEP_SYNC
:
702 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
703 * need to update the origin time.
705 ocelot_port
->ptp_cmd
= IFH_REW_OP_ORIGIN_PTP
;
707 case HWTSTAMP_TX_OFF
:
708 ocelot_port
->ptp_cmd
= 0;
714 mutex_lock(&ocelot
->ptp_lock
);
716 switch (cfg
.rx_filter
) {
717 case HWTSTAMP_FILTER_NONE
:
719 case HWTSTAMP_FILTER_ALL
:
720 case HWTSTAMP_FILTER_SOME
:
721 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
722 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
723 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
724 case HWTSTAMP_FILTER_NTP_ALL
:
725 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
726 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
727 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
728 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
729 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
730 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
731 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
732 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
733 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
734 cfg
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
737 mutex_unlock(&ocelot
->ptp_lock
);
741 /* Commit back the result & save it */
742 memcpy(&ocelot
->hwtstamp_config
, &cfg
, sizeof(cfg
));
743 mutex_unlock(&ocelot
->ptp_lock
);
745 return copy_to_user(ifr
->ifr_data
, &cfg
, sizeof(cfg
)) ? -EFAULT
: 0;
747 EXPORT_SYMBOL(ocelot_hwstamp_set
);
749 void ocelot_get_strings(struct ocelot
*ocelot
, int port
, u32 sset
, u8
*data
)
753 if (sset
!= ETH_SS_STATS
)
756 for (i
= 0; i
< ocelot
->num_stats
; i
++)
757 memcpy(data
+ i
* ETH_GSTRING_LEN
, ocelot
->stats_layout
[i
].name
,
760 EXPORT_SYMBOL(ocelot_get_strings
);
762 static void ocelot_update_stats(struct ocelot
*ocelot
)
766 mutex_lock(&ocelot
->stats_lock
);
768 for (i
= 0; i
< ocelot
->num_phys_ports
; i
++) {
769 /* Configure the port to read the stats from */
770 ocelot_write(ocelot
, SYS_STAT_CFG_STAT_VIEW(i
), SYS_STAT_CFG
);
772 for (j
= 0; j
< ocelot
->num_stats
; j
++) {
774 unsigned int idx
= i
* ocelot
->num_stats
+ j
;
776 val
= ocelot_read_rix(ocelot
, SYS_COUNT_RX_OCTETS
,
777 ocelot
->stats_layout
[j
].offset
);
779 if (val
< (ocelot
->stats
[idx
] & U32_MAX
))
780 ocelot
->stats
[idx
] += (u64
)1 << 32;
782 ocelot
->stats
[idx
] = (ocelot
->stats
[idx
] &
783 ~(u64
)U32_MAX
) + val
;
787 mutex_unlock(&ocelot
->stats_lock
);
790 static void ocelot_check_stats_work(struct work_struct
*work
)
792 struct delayed_work
*del_work
= to_delayed_work(work
);
793 struct ocelot
*ocelot
= container_of(del_work
, struct ocelot
,
796 ocelot_update_stats(ocelot
);
798 queue_delayed_work(ocelot
->stats_queue
, &ocelot
->stats_work
,
799 OCELOT_STATS_CHECK_DELAY
);
802 void ocelot_get_ethtool_stats(struct ocelot
*ocelot
, int port
, u64
*data
)
806 /* check and update now */
807 ocelot_update_stats(ocelot
);
809 /* Copy all counters */
810 for (i
= 0; i
< ocelot
->num_stats
; i
++)
811 *data
++ = ocelot
->stats
[port
* ocelot
->num_stats
+ i
];
813 EXPORT_SYMBOL(ocelot_get_ethtool_stats
);
815 int ocelot_get_sset_count(struct ocelot
*ocelot
, int port
, int sset
)
817 if (sset
!= ETH_SS_STATS
)
820 return ocelot
->num_stats
;
822 EXPORT_SYMBOL(ocelot_get_sset_count
);
824 int ocelot_get_ts_info(struct ocelot
*ocelot
, int port
,
825 struct ethtool_ts_info
*info
)
827 info
->phc_index
= ocelot
->ptp_clock
?
828 ptp_clock_index(ocelot
->ptp_clock
) : -1;
829 if (info
->phc_index
== -1) {
830 info
->so_timestamping
|= SOF_TIMESTAMPING_TX_SOFTWARE
|
831 SOF_TIMESTAMPING_RX_SOFTWARE
|
832 SOF_TIMESTAMPING_SOFTWARE
;
835 info
->so_timestamping
|= SOF_TIMESTAMPING_TX_SOFTWARE
|
836 SOF_TIMESTAMPING_RX_SOFTWARE
|
837 SOF_TIMESTAMPING_SOFTWARE
|
838 SOF_TIMESTAMPING_TX_HARDWARE
|
839 SOF_TIMESTAMPING_RX_HARDWARE
|
840 SOF_TIMESTAMPING_RAW_HARDWARE
;
841 info
->tx_types
= BIT(HWTSTAMP_TX_OFF
) | BIT(HWTSTAMP_TX_ON
) |
842 BIT(HWTSTAMP_TX_ONESTEP_SYNC
);
843 info
->rx_filters
= BIT(HWTSTAMP_FILTER_NONE
) | BIT(HWTSTAMP_FILTER_ALL
);
847 EXPORT_SYMBOL(ocelot_get_ts_info
);
849 void ocelot_bridge_stp_state_set(struct ocelot
*ocelot
, int port
, u8 state
)
854 if (!(BIT(port
) & ocelot
->bridge_mask
))
857 port_cfg
= ocelot_read_gix(ocelot
, ANA_PORT_PORT_CFG
, port
);
860 case BR_STATE_FORWARDING
:
861 ocelot
->bridge_fwd_mask
|= BIT(port
);
863 case BR_STATE_LEARNING
:
864 port_cfg
|= ANA_PORT_PORT_CFG_LEARN_ENA
;
868 port_cfg
&= ~ANA_PORT_PORT_CFG_LEARN_ENA
;
869 ocelot
->bridge_fwd_mask
&= ~BIT(port
);
873 ocelot_write_gix(ocelot
, port_cfg
, ANA_PORT_PORT_CFG
, port
);
875 /* Apply FWD mask. The loop is needed to add/remove the current port as
876 * a source for the other ports.
878 for (p
= 0; p
< ocelot
->num_phys_ports
; p
++) {
879 if (ocelot
->bridge_fwd_mask
& BIT(p
)) {
880 unsigned long mask
= ocelot
->bridge_fwd_mask
& ~BIT(p
);
882 for (i
= 0; i
< ocelot
->num_phys_ports
; i
++) {
883 unsigned long bond_mask
= ocelot
->lags
[i
];
888 if (bond_mask
& BIT(p
)) {
894 ocelot_write_rix(ocelot
, mask
,
895 ANA_PGID_PGID
, PGID_SRC
+ p
);
897 ocelot_write_rix(ocelot
, 0,
898 ANA_PGID_PGID
, PGID_SRC
+ p
);
902 EXPORT_SYMBOL(ocelot_bridge_stp_state_set
);
904 void ocelot_set_ageing_time(struct ocelot
*ocelot
, unsigned int msecs
)
906 unsigned int age_period
= ANA_AUTOAGE_AGE_PERIOD(msecs
/ 2000);
908 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
909 * which is clearly not what our intention is. So avoid that.
914 ocelot_rmw(ocelot
, age_period
, ANA_AUTOAGE_AGE_PERIOD_M
, ANA_AUTOAGE
);
916 EXPORT_SYMBOL(ocelot_set_ageing_time
);
918 static struct ocelot_multicast
*ocelot_multicast_get(struct ocelot
*ocelot
,
919 const unsigned char *addr
,
922 struct ocelot_multicast
*mc
;
924 list_for_each_entry(mc
, &ocelot
->multicast
, list
) {
925 if (ether_addr_equal(mc
->addr
, addr
) && mc
->vid
== vid
)
932 static enum macaccess_entry_type
ocelot_classify_mdb(const unsigned char *addr
)
934 if (addr
[0] == 0x01 && addr
[1] == 0x00 && addr
[2] == 0x5e)
935 return ENTRYTYPE_MACv4
;
936 if (addr
[0] == 0x33 && addr
[1] == 0x33)
937 return ENTRYTYPE_MACv6
;
938 return ENTRYTYPE_NORMAL
;
941 static int ocelot_mdb_get_pgid(struct ocelot
*ocelot
,
942 enum macaccess_entry_type entry_type
)
946 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
947 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
948 * destination mask table (PGID), the destination set is programmed as
949 * part of the entry MAC address.", and the DEST_IDX is set to 0.
951 if (entry_type
== ENTRYTYPE_MACv4
||
952 entry_type
== ENTRYTYPE_MACv6
)
955 for_each_nonreserved_multicast_dest_pgid(ocelot
, pgid
) {
956 struct ocelot_multicast
*mc
;
959 list_for_each_entry(mc
, &ocelot
->multicast
, list
) {
960 if (mc
->pgid
== pgid
) {
973 static void ocelot_encode_ports_to_mdb(unsigned char *addr
,
974 struct ocelot_multicast
*mc
,
975 enum macaccess_entry_type entry_type
)
977 memcpy(addr
, mc
->addr
, ETH_ALEN
);
979 if (entry_type
== ENTRYTYPE_MACv4
) {
981 addr
[1] = mc
->ports
>> 8;
982 addr
[2] = mc
->ports
& 0xff;
983 } else if (entry_type
== ENTRYTYPE_MACv6
) {
984 addr
[0] = mc
->ports
>> 8;
985 addr
[1] = mc
->ports
& 0xff;
989 int ocelot_port_mdb_add(struct ocelot
*ocelot
, int port
,
990 const struct switchdev_obj_port_mdb
*mdb
)
992 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
993 enum macaccess_entry_type entry_type
;
994 unsigned char addr
[ETH_ALEN
];
995 struct ocelot_multicast
*mc
;
999 if (port
== ocelot
->npi
)
1000 port
= ocelot
->num_phys_ports
;
1003 vid
= ocelot_port
->pvid
;
1005 entry_type
= ocelot_classify_mdb(mdb
->addr
);
1007 mc
= ocelot_multicast_get(ocelot
, mdb
->addr
, vid
);
1009 int pgid
= ocelot_mdb_get_pgid(ocelot
, entry_type
);
1012 dev_err(ocelot
->dev
,
1013 "No more PGIDs available for mdb %pM vid %d\n",
1018 mc
= devm_kzalloc(ocelot
->dev
, sizeof(*mc
), GFP_KERNEL
);
1022 memcpy(mc
->addr
, mdb
->addr
, ETH_ALEN
);
1026 list_add_tail(&mc
->list
, &ocelot
->multicast
);
1031 ocelot_encode_ports_to_mdb(addr
, mc
, entry_type
);
1032 ocelot_mact_forget(ocelot
, addr
, vid
);
1035 mc
->ports
|= BIT(port
);
1036 ocelot_encode_ports_to_mdb(addr
, mc
, entry_type
);
1038 return ocelot_mact_learn(ocelot
, mc
->pgid
, addr
, vid
, entry_type
);
1040 EXPORT_SYMBOL(ocelot_port_mdb_add
);
1042 int ocelot_port_mdb_del(struct ocelot
*ocelot
, int port
,
1043 const struct switchdev_obj_port_mdb
*mdb
)
1045 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
1046 enum macaccess_entry_type entry_type
;
1047 unsigned char addr
[ETH_ALEN
];
1048 struct ocelot_multicast
*mc
;
1051 if (port
== ocelot
->npi
)
1052 port
= ocelot
->num_phys_ports
;
1055 vid
= ocelot_port
->pvid
;
1057 mc
= ocelot_multicast_get(ocelot
, mdb
->addr
, vid
);
1061 entry_type
= ocelot_classify_mdb(mdb
->addr
);
1063 ocelot_encode_ports_to_mdb(addr
, mc
, entry_type
);
1064 ocelot_mact_forget(ocelot
, addr
, vid
);
1066 mc
->ports
&= ~BIT(port
);
1068 list_del(&mc
->list
);
1069 devm_kfree(ocelot
->dev
, mc
);
1073 ocelot_encode_ports_to_mdb(addr
, mc
, entry_type
);
1075 return ocelot_mact_learn(ocelot
, mc
->pgid
, addr
, vid
, entry_type
);
1077 EXPORT_SYMBOL(ocelot_port_mdb_del
);
1079 int ocelot_port_bridge_join(struct ocelot
*ocelot
, int port
,
1080 struct net_device
*bridge
)
1082 if (!ocelot
->bridge_mask
) {
1083 ocelot
->hw_bridge_dev
= bridge
;
1085 if (ocelot
->hw_bridge_dev
!= bridge
)
1086 /* This is adding the port to a second bridge, this is
1091 ocelot
->bridge_mask
|= BIT(port
);
1095 EXPORT_SYMBOL(ocelot_port_bridge_join
);
1097 int ocelot_port_bridge_leave(struct ocelot
*ocelot
, int port
,
1098 struct net_device
*bridge
)
1100 ocelot
->bridge_mask
&= ~BIT(port
);
1102 if (!ocelot
->bridge_mask
)
1103 ocelot
->hw_bridge_dev
= NULL
;
1105 ocelot_port_vlan_filtering(ocelot
, port
, 0);
1106 ocelot_port_set_pvid(ocelot
, port
, 0);
1107 return ocelot_port_set_native_vlan(ocelot
, port
, 0);
1109 EXPORT_SYMBOL(ocelot_port_bridge_leave
);
1111 static void ocelot_set_aggr_pgids(struct ocelot
*ocelot
)
1115 /* Reset destination and aggregation PGIDS */
1116 for_each_unicast_dest_pgid(ocelot
, port
)
1117 ocelot_write_rix(ocelot
, BIT(port
), ANA_PGID_PGID
, port
);
1119 for_each_aggr_pgid(ocelot
, i
)
1120 ocelot_write_rix(ocelot
, GENMASK(ocelot
->num_phys_ports
- 1, 0),
1123 /* Now, set PGIDs for each LAG */
1124 for (lag
= 0; lag
< ocelot
->num_phys_ports
; lag
++) {
1125 unsigned long bond_mask
;
1129 bond_mask
= ocelot
->lags
[lag
];
1133 for_each_set_bit(port
, &bond_mask
, ocelot
->num_phys_ports
) {
1135 ocelot_write_rix(ocelot
, bond_mask
,
1136 ANA_PGID_PGID
, port
);
1137 aggr_idx
[aggr_count
] = port
;
1141 for_each_aggr_pgid(ocelot
, i
) {
1144 ac
= ocelot_read_rix(ocelot
, ANA_PGID_PGID
, i
);
1146 ac
|= BIT(aggr_idx
[i
% aggr_count
]);
1147 ocelot_write_rix(ocelot
, ac
, ANA_PGID_PGID
, i
);
1152 static void ocelot_setup_lag(struct ocelot
*ocelot
, int lag
)
1154 unsigned long bond_mask
= ocelot
->lags
[lag
];
1157 for_each_set_bit(p
, &bond_mask
, ocelot
->num_phys_ports
) {
1158 u32 port_cfg
= ocelot_read_gix(ocelot
, ANA_PORT_PORT_CFG
, p
);
1160 port_cfg
&= ~ANA_PORT_PORT_CFG_PORTID_VAL_M
;
1162 /* Use lag port as logical port for port i */
1163 ocelot_write_gix(ocelot
, port_cfg
|
1164 ANA_PORT_PORT_CFG_PORTID_VAL(lag
),
1165 ANA_PORT_PORT_CFG
, p
);
1169 int ocelot_port_lag_join(struct ocelot
*ocelot
, int port
,
1170 struct net_device
*bond
)
1172 struct net_device
*ndev
;
1177 for_each_netdev_in_bond_rcu(bond
, ndev
) {
1178 struct ocelot_port_private
*priv
= netdev_priv(ndev
);
1180 bond_mask
|= BIT(priv
->chip_port
);
1184 lp
= __ffs(bond_mask
);
1186 /* If the new port is the lowest one, use it as the logical port from
1191 ocelot
->lags
[port
] = bond_mask
;
1192 bond_mask
&= ~BIT(port
);
1194 lp
= __ffs(bond_mask
);
1195 ocelot
->lags
[lp
] = 0;
1199 ocelot
->lags
[lp
] |= BIT(port
);
1202 ocelot_setup_lag(ocelot
, lag
);
1203 ocelot_set_aggr_pgids(ocelot
);
1207 EXPORT_SYMBOL(ocelot_port_lag_join
);
1209 void ocelot_port_lag_leave(struct ocelot
*ocelot
, int port
,
1210 struct net_device
*bond
)
1215 /* Remove port from any lag */
1216 for (i
= 0; i
< ocelot
->num_phys_ports
; i
++)
1217 ocelot
->lags
[i
] &= ~BIT(port
);
1219 /* if it was the logical port of the lag, move the lag config to the
1222 if (ocelot
->lags
[port
]) {
1223 int n
= __ffs(ocelot
->lags
[port
]);
1225 ocelot
->lags
[n
] = ocelot
->lags
[port
];
1226 ocelot
->lags
[port
] = 0;
1228 ocelot_setup_lag(ocelot
, n
);
1231 port_cfg
= ocelot_read_gix(ocelot
, ANA_PORT_PORT_CFG
, port
);
1232 port_cfg
&= ~ANA_PORT_PORT_CFG_PORTID_VAL_M
;
1233 ocelot_write_gix(ocelot
, port_cfg
| ANA_PORT_PORT_CFG_PORTID_VAL(port
),
1234 ANA_PORT_PORT_CFG
, port
);
1236 ocelot_set_aggr_pgids(ocelot
);
1238 EXPORT_SYMBOL(ocelot_port_lag_leave
);
1240 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
1241 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
1242 * In the special case that it's the NPI port that we're configuring, the
1243 * length of the tag and optional prefix needs to be accounted for privately,
1244 * in order to be able to sustain communication at the requested @sdu.
1246 void ocelot_port_set_maxlen(struct ocelot
*ocelot
, int port
, size_t sdu
)
1248 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
1249 int maxlen
= sdu
+ ETH_HLEN
+ ETH_FCS_LEN
;
1250 int pause_start
, pause_stop
;
1253 if (port
== ocelot
->npi
) {
1254 maxlen
+= OCELOT_TAG_LEN
;
1256 if (ocelot
->inj_prefix
== OCELOT_TAG_PREFIX_SHORT
)
1257 maxlen
+= OCELOT_SHORT_PREFIX_LEN
;
1258 else if (ocelot
->inj_prefix
== OCELOT_TAG_PREFIX_LONG
)
1259 maxlen
+= OCELOT_LONG_PREFIX_LEN
;
1262 ocelot_port_writel(ocelot_port
, maxlen
, DEV_MAC_MAXLEN_CFG
);
1264 /* Set Pause watermark hysteresis */
1265 pause_start
= 6 * maxlen
/ OCELOT_BUFFER_CELL_SZ
;
1266 pause_stop
= 4 * maxlen
/ OCELOT_BUFFER_CELL_SZ
;
1267 ocelot_fields_write(ocelot
, port
, SYS_PAUSE_CFG_PAUSE_START
,
1269 ocelot_fields_write(ocelot
, port
, SYS_PAUSE_CFG_PAUSE_STOP
,
1272 /* Tail dropping watermark */
1273 atop_wm
= (ocelot
->shared_queue_sz
- 9 * maxlen
) /
1274 OCELOT_BUFFER_CELL_SZ
;
1275 ocelot_write_rix(ocelot
, ocelot
->ops
->wm_enc(9 * maxlen
),
1277 ocelot_write(ocelot
, ocelot
->ops
->wm_enc(atop_wm
), SYS_ATOP_TOT_CFG
);
1279 EXPORT_SYMBOL(ocelot_port_set_maxlen
);
1281 int ocelot_get_max_mtu(struct ocelot
*ocelot
, int port
)
1283 int max_mtu
= 65535 - ETH_HLEN
- ETH_FCS_LEN
;
1285 if (port
== ocelot
->npi
) {
1286 max_mtu
-= OCELOT_TAG_LEN
;
1288 if (ocelot
->inj_prefix
== OCELOT_TAG_PREFIX_SHORT
)
1289 max_mtu
-= OCELOT_SHORT_PREFIX_LEN
;
1290 else if (ocelot
->inj_prefix
== OCELOT_TAG_PREFIX_LONG
)
1291 max_mtu
-= OCELOT_LONG_PREFIX_LEN
;
1296 EXPORT_SYMBOL(ocelot_get_max_mtu
);
1298 void ocelot_init_port(struct ocelot
*ocelot
, int port
)
1300 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
1302 skb_queue_head_init(&ocelot_port
->tx_skbs
);
1304 /* Basic L2 initialization */
1307 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
1308 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
1310 ocelot_port_writel(ocelot_port
, DEV_MAC_IFG_CFG_TX_IFG(5),
1313 /* Load seed (0) and set MAC HDX late collision */
1314 ocelot_port_writel(ocelot_port
, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
1315 DEV_MAC_HDX_CFG_SEED_LOAD
,
1318 ocelot_port_writel(ocelot_port
, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
1321 /* Set Max Length and maximum tags allowed */
1322 ocelot_port_set_maxlen(ocelot
, port
, ETH_DATA_LEN
);
1323 ocelot_port_writel(ocelot_port
, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD
) |
1324 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA
|
1325 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA
|
1326 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA
,
1329 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
1330 ocelot_port_writel(ocelot_port
, 0, DEV_MAC_FC_MAC_HIGH_CFG
);
1331 ocelot_port_writel(ocelot_port
, 0, DEV_MAC_FC_MAC_LOW_CFG
);
1333 /* Enable transmission of pause frames */
1334 ocelot_fields_write(ocelot
, port
, SYS_PAUSE_CFG_PAUSE_ENA
, 1);
1336 /* Drop frames with multicast source address */
1337 ocelot_rmw_gix(ocelot
, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA
,
1338 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA
,
1339 ANA_PORT_DROP_CFG
, port
);
1341 /* Set default VLAN and tag type to 8021Q. */
1342 ocelot_rmw_gix(ocelot
, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q
),
1343 REW_PORT_VLAN_CFG_PORT_TPID_M
,
1344 REW_PORT_VLAN_CFG
, port
);
1346 /* Enable vcap lookups */
1347 ocelot_vcap_enable(ocelot
, port
);
1349 EXPORT_SYMBOL(ocelot_init_port
);
1351 /* Configure and enable the CPU port module, which is a set of queues.
1352 * If @npi contains a valid port index, the CPU port module is connected
1353 * to the Node Processor Interface (NPI). This is the mode through which
1354 * frames can be injected from and extracted to an external CPU,
1357 void ocelot_configure_cpu(struct ocelot
*ocelot
, int npi
,
1358 enum ocelot_tag_prefix injection
,
1359 enum ocelot_tag_prefix extraction
)
1361 int cpu
= ocelot
->num_phys_ports
;
1364 ocelot
->inj_prefix
= injection
;
1365 ocelot
->xtr_prefix
= extraction
;
1367 /* The unicast destination PGID for the CPU port module is unused */
1368 ocelot_write_rix(ocelot
, 0, ANA_PGID_PGID
, cpu
);
1369 /* Instead set up a multicast destination PGID for traffic copied to
1370 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
1371 * addresses will be copied to the CPU via this PGID.
1373 ocelot_write_rix(ocelot
, BIT(cpu
), ANA_PGID_PGID
, PGID_CPU
);
1374 ocelot_write_gix(ocelot
, ANA_PORT_PORT_CFG_RECV_ENA
|
1375 ANA_PORT_PORT_CFG_PORTID_VAL(cpu
),
1376 ANA_PORT_PORT_CFG
, cpu
);
1378 if (npi
>= 0 && npi
< ocelot
->num_phys_ports
) {
1379 ocelot_write(ocelot
, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M
|
1380 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(npi
),
1383 /* Enable NPI port */
1384 ocelot_fields_write(ocelot
, npi
,
1385 QSYS_SWITCH_PORT_MODE_PORT_ENA
, 1);
1386 /* NPI port Injection/Extraction configuration */
1387 ocelot_fields_write(ocelot
, npi
, SYS_PORT_MODE_INCL_XTR_HDR
,
1389 ocelot_fields_write(ocelot
, npi
, SYS_PORT_MODE_INCL_INJ_HDR
,
1392 /* Disable transmission of pause frames */
1393 ocelot_fields_write(ocelot
, npi
, SYS_PAUSE_CFG_PAUSE_ENA
, 0);
1396 /* Enable CPU port module */
1397 ocelot_fields_write(ocelot
, cpu
, QSYS_SWITCH_PORT_MODE_PORT_ENA
, 1);
1398 /* CPU port Injection/Extraction configuration */
1399 ocelot_fields_write(ocelot
, cpu
, SYS_PORT_MODE_INCL_XTR_HDR
,
1401 ocelot_fields_write(ocelot
, cpu
, SYS_PORT_MODE_INCL_INJ_HDR
,
1404 /* Configure the CPU port to be VLAN aware */
1405 ocelot_write_gix(ocelot
, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
1406 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA
|
1407 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
1408 ANA_PORT_VLAN_CFG
, cpu
);
1410 EXPORT_SYMBOL(ocelot_configure_cpu
);
1412 int ocelot_init(struct ocelot
*ocelot
)
1414 char queue_name
[32];
1418 if (ocelot
->ops
->reset
) {
1419 ret
= ocelot
->ops
->reset(ocelot
);
1421 dev_err(ocelot
->dev
, "Switch reset failed\n");
1426 ocelot
->lags
= devm_kcalloc(ocelot
->dev
, ocelot
->num_phys_ports
,
1427 sizeof(u32
), GFP_KERNEL
);
1431 ocelot
->stats
= devm_kcalloc(ocelot
->dev
,
1432 ocelot
->num_phys_ports
* ocelot
->num_stats
,
1433 sizeof(u64
), GFP_KERNEL
);
1437 mutex_init(&ocelot
->stats_lock
);
1438 mutex_init(&ocelot
->ptp_lock
);
1439 spin_lock_init(&ocelot
->ptp_clock_lock
);
1440 snprintf(queue_name
, sizeof(queue_name
), "%s-stats",
1441 dev_name(ocelot
->dev
));
1442 ocelot
->stats_queue
= create_singlethread_workqueue(queue_name
);
1443 if (!ocelot
->stats_queue
)
1446 INIT_LIST_HEAD(&ocelot
->multicast
);
1447 ocelot_mact_init(ocelot
);
1448 ocelot_vlan_init(ocelot
);
1449 ocelot_vcap_init(ocelot
);
1451 for (port
= 0; port
< ocelot
->num_phys_ports
; port
++) {
1452 /* Clear all counters (5 groups) */
1453 ocelot_write(ocelot
, SYS_STAT_CFG_STAT_VIEW(port
) |
1454 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
1458 /* Only use S-Tag */
1459 ocelot_write(ocelot
, ETH_P_8021AD
, SYS_VLAN_ETYPE_CFG
);
1461 /* Aggregation mode */
1462 ocelot_write(ocelot
, ANA_AGGR_CFG_AC_SMAC_ENA
|
1463 ANA_AGGR_CFG_AC_DMAC_ENA
|
1464 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA
|
1465 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA
, ANA_AGGR_CFG
);
1467 /* Set MAC age time to default value. The entry is aged after
1470 ocelot_write(ocelot
,
1471 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME
/ 2 / HZ
),
1474 /* Disable learning for frames discarded by VLAN ingress filtering */
1475 regmap_field_write(ocelot
->regfields
[ANA_ADVLEARN_VLAN_CHK
], 1);
1477 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
1478 ocelot_write(ocelot
, SYS_FRM_AGING_AGE_TX_ENA
|
1479 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING
);
1481 /* Setup flooding PGIDs */
1482 ocelot_write_rix(ocelot
, ANA_FLOODING_FLD_MULTICAST(PGID_MC
) |
1483 ANA_FLOODING_FLD_BROADCAST(PGID_MC
) |
1484 ANA_FLOODING_FLD_UNICAST(PGID_UC
),
1486 ocelot_write(ocelot
, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6
) |
1487 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC
) |
1488 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4
) |
1489 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC
),
1492 for (port
= 0; port
< ocelot
->num_phys_ports
; port
++) {
1493 /* Transmit the frame to the local port. */
1494 ocelot_write_rix(ocelot
, BIT(port
), ANA_PGID_PGID
, port
);
1495 /* Do not forward BPDU frames to the front ports. */
1496 ocelot_write_gix(ocelot
,
1497 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
1498 ANA_PORT_CPU_FWD_BPDU_CFG
,
1500 /* Ensure bridging is disabled */
1501 ocelot_write_rix(ocelot
, 0, ANA_PGID_PGID
, PGID_SRC
+ port
);
1504 /* Allow broadcast MAC frames. */
1505 for_each_nonreserved_multicast_dest_pgid(ocelot
, i
) {
1506 u32 val
= ANA_PGID_PGID_PGID(GENMASK(ocelot
->num_phys_ports
- 1, 0));
1508 ocelot_write_rix(ocelot
, val
, ANA_PGID_PGID
, i
);
1510 ocelot_write_rix(ocelot
,
1511 ANA_PGID_PGID_PGID(GENMASK(ocelot
->num_phys_ports
, 0)),
1512 ANA_PGID_PGID
, PGID_MC
);
1513 ocelot_write_rix(ocelot
, 0, ANA_PGID_PGID
, PGID_MCIPV4
);
1514 ocelot_write_rix(ocelot
, 0, ANA_PGID_PGID
, PGID_MCIPV6
);
1516 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
1517 * registers endianness.
1519 ocelot_write_rix(ocelot
, QS_INJ_GRP_CFG_BYTE_SWAP
|
1520 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG
, 0);
1521 ocelot_write_rix(ocelot
, QS_XTR_GRP_CFG_BYTE_SWAP
|
1522 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG
, 0);
1523 ocelot_write(ocelot
, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
1524 ANA_CPUQ_CFG_CPUQ_LRN(2) |
1525 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
1526 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
1527 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
1528 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
1529 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
1530 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
1531 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG
);
1532 for (i
= 0; i
< 16; i
++)
1533 ocelot_write_rix(ocelot
, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
1534 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
1535 ANA_CPUQ_8021_CFG
, i
);
1537 INIT_DELAYED_WORK(&ocelot
->stats_work
, ocelot_check_stats_work
);
1538 queue_delayed_work(ocelot
->stats_queue
, &ocelot
->stats_work
,
1539 OCELOT_STATS_CHECK_DELAY
);
1543 EXPORT_SYMBOL(ocelot_init
);
1545 void ocelot_deinit(struct ocelot
*ocelot
)
1547 struct ocelot_port
*port
;
1550 cancel_delayed_work(&ocelot
->stats_work
);
1551 destroy_workqueue(ocelot
->stats_queue
);
1552 mutex_destroy(&ocelot
->stats_lock
);
1554 for (i
= 0; i
< ocelot
->num_phys_ports
; i
++) {
1555 port
= ocelot
->ports
[i
];
1556 skb_queue_purge(&port
->tx_skbs
);
1559 EXPORT_SYMBOL(ocelot_deinit
);
1561 MODULE_LICENSE("Dual MIT/GPL");