1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
7 #include <linux/interrupt.h>
8 #include <linux/module.h>
9 #include <linux/of_net.h>
10 #include <linux/netdevice.h>
11 #include <linux/of_mdio.h>
12 #include <linux/of_platform.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/skbuff.h>
15 #include <net/switchdev.h>
19 #define IFH_EXTRACT_BITFIELD64(x, o, w) (((x) >> (o)) & GENMASK_ULL((w) - 1, 0))
21 static int ocelot_parse_ifh(u32
*_ifh
, struct frame_info
*info
)
26 ifh
[0] = be64_to_cpu(((__force __be64
*)_ifh
)[0]);
27 ifh
[1] = be64_to_cpu(((__force __be64
*)_ifh
)[1]);
29 wlen
= IFH_EXTRACT_BITFIELD64(ifh
[0], 7, 8);
30 llen
= IFH_EXTRACT_BITFIELD64(ifh
[0], 15, 6);
32 info
->len
= OCELOT_BUFFER_CELL_SZ
* wlen
+ llen
- 80;
34 info
->timestamp
= IFH_EXTRACT_BITFIELD64(ifh
[0], 21, 32);
36 info
->port
= IFH_EXTRACT_BITFIELD64(ifh
[1], 43, 4);
38 info
->tag_type
= IFH_EXTRACT_BITFIELD64(ifh
[1], 16, 1);
39 info
->vid
= IFH_EXTRACT_BITFIELD64(ifh
[1], 0, 12);
44 static int ocelot_rx_frame_word(struct ocelot
*ocelot
, u8 grp
, bool ifh
,
50 val
= ocelot_read_rix(ocelot
, QS_XTR_RD
, grp
);
51 if (val
== XTR_NOT_READY
) {
56 val
= ocelot_read_rix(ocelot
, QS_XTR_RD
, grp
);
57 } while (val
== XTR_NOT_READY
);
68 bytes_valid
= XTR_VALID_BYTES(val
);
69 val
= ocelot_read_rix(ocelot
, QS_XTR_RD
, grp
);
70 if (val
== XTR_ESCAPE
)
71 *rval
= ocelot_read_rix(ocelot
, QS_XTR_RD
, grp
);
77 *rval
= ocelot_read_rix(ocelot
, QS_XTR_RD
, grp
);
87 static irqreturn_t
ocelot_xtr_irq_handler(int irq
, void *arg
)
89 struct ocelot
*ocelot
= arg
;
93 if (!(ocelot_read(ocelot
, QS_XTR_DATA_PRESENT
) & BIT(grp
)))
97 struct skb_shared_hwtstamps
*shhwtstamps
;
98 struct ocelot_port_private
*priv
;
99 struct ocelot_port
*ocelot_port
;
100 u64 tod_in_ns
, full_ts_in_ns
;
101 struct frame_info info
= {};
102 struct net_device
*dev
;
103 u32 ifh
[4], val
, *buf
;
104 struct timespec64 ts
;
105 int sz
, len
, buf_len
;
108 for (i
= 0; i
< OCELOT_TAG_LEN
/ 4; i
++) {
109 err
= ocelot_rx_frame_word(ocelot
, grp
, true, &ifh
[i
]);
117 ocelot_parse_ifh(ifh
, &info
);
119 ocelot_port
= ocelot
->ports
[info
.port
];
120 priv
= container_of(ocelot_port
, struct ocelot_port_private
,
124 skb
= netdev_alloc_skb(dev
, info
.len
);
126 if (unlikely(!skb
)) {
127 netdev_err(dev
, "Unable to allocate sk_buff\n");
131 buf_len
= info
.len
- ETH_FCS_LEN
;
132 buf
= (u32
*)skb_put(skb
, buf_len
);
136 sz
= ocelot_rx_frame_word(ocelot
, grp
, false, &val
);
139 } while (len
< buf_len
);
142 sz
= ocelot_rx_frame_word(ocelot
, grp
, false, &val
);
143 /* Update the statistics if part of the FCS was read before */
144 len
-= ETH_FCS_LEN
- sz
;
146 if (unlikely(dev
->features
& NETIF_F_RXFCS
)) {
147 buf
= (u32
*)skb_put(skb
, ETH_FCS_LEN
);
157 ocelot_ptp_gettime64(&ocelot
->ptp_info
, &ts
);
159 tod_in_ns
= ktime_set(ts
.tv_sec
, ts
.tv_nsec
);
160 if ((tod_in_ns
& 0xffffffff) < info
.timestamp
)
161 full_ts_in_ns
= (((tod_in_ns
>> 32) - 1) << 32) |
164 full_ts_in_ns
= (tod_in_ns
& GENMASK_ULL(63, 32)) |
167 shhwtstamps
= skb_hwtstamps(skb
);
168 memset(shhwtstamps
, 0, sizeof(struct skb_shared_hwtstamps
));
169 shhwtstamps
->hwtstamp
= full_ts_in_ns
;
172 /* Everything we see on an interface that is in the HW bridge
173 * has already been forwarded.
175 if (ocelot
->bridge_mask
& BIT(info
.port
))
176 skb
->offload_fwd_mark
= 1;
178 skb
->protocol
= eth_type_trans(skb
, dev
);
180 dev
->stats
.rx_bytes
+= len
;
181 dev
->stats
.rx_packets
++;
182 } while (ocelot_read(ocelot
, QS_XTR_DATA_PRESENT
) & BIT(grp
));
185 while (ocelot_read(ocelot
, QS_XTR_DATA_PRESENT
) & BIT(grp
))
186 ocelot_read_rix(ocelot
, QS_XTR_RD
, grp
);
191 static irqreturn_t
ocelot_ptp_rdy_irq_handler(int irq
, void *arg
)
193 struct ocelot
*ocelot
= arg
;
195 ocelot_get_txtstamp(ocelot
);
200 static const struct of_device_id mscc_ocelot_match
[] = {
201 { .compatible
= "mscc,vsc7514-switch" },
204 MODULE_DEVICE_TABLE(of
, mscc_ocelot_match
);
206 static void ocelot_port_pcs_init(struct ocelot
*ocelot
, int port
)
208 struct ocelot_port
*ocelot_port
= ocelot
->ports
[port
];
210 /* Disable HDX fast control */
211 ocelot_port_writel(ocelot_port
, DEV_PORT_MISC_HDX_FAST_DIS
,
214 /* SGMII only for now */
215 ocelot_port_writel(ocelot_port
, PCS1G_MODE_CFG_SGMII_MODE_ENA
,
217 ocelot_port_writel(ocelot_port
, PCS1G_SD_CFG_SD_SEL
, PCS1G_SD_CFG
);
220 ocelot_port_writel(ocelot_port
, PCS1G_CFG_PCS_ENA
, PCS1G_CFG
);
222 /* No aneg on SGMII */
223 ocelot_port_writel(ocelot_port
, 0, PCS1G_ANEG_CFG
);
226 ocelot_port_writel(ocelot_port
, 0, PCS1G_LB_CFG
);
229 static int ocelot_reset(struct ocelot
*ocelot
)
234 regmap_field_write(ocelot
->regfields
[SYS_RESET_CFG_MEM_INIT
], 1);
235 regmap_field_write(ocelot
->regfields
[SYS_RESET_CFG_MEM_ENA
], 1);
239 regmap_field_read(ocelot
->regfields
[SYS_RESET_CFG_MEM_INIT
],
241 } while (val
&& --retries
);
246 regmap_field_write(ocelot
->regfields
[SYS_RESET_CFG_MEM_ENA
], 1);
247 regmap_field_write(ocelot
->regfields
[SYS_RESET_CFG_CORE_ENA
], 1);
252 static const struct ocelot_ops ocelot_ops
= {
253 .pcs_init
= ocelot_port_pcs_init
,
254 .reset
= ocelot_reset
,
257 static int mscc_ocelot_probe(struct platform_device
*pdev
)
259 struct device_node
*np
= pdev
->dev
.of_node
;
260 struct device_node
*ports
, *portnp
;
261 int err
, irq_xtr
, irq_ptp_rdy
;
262 struct ocelot
*ocelot
;
267 enum ocelot_target id
;
280 if (!np
&& !pdev
->dev
.platform_data
)
283 ocelot
= devm_kzalloc(&pdev
->dev
, sizeof(*ocelot
), GFP_KERNEL
);
287 platform_set_drvdata(pdev
, ocelot
);
288 ocelot
->dev
= &pdev
->dev
;
290 for (i
= 0; i
< ARRAY_SIZE(io_target
); i
++) {
291 struct regmap
*target
;
292 struct resource
*res
;
294 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
297 target
= ocelot_regmap_init(ocelot
, res
);
298 if (IS_ERR(target
)) {
299 if (io_target
[i
].optional
) {
300 ocelot
->targets
[io_target
[i
].id
] = NULL
;
303 return PTR_ERR(target
);
306 ocelot
->targets
[io_target
[i
].id
] = target
;
309 hsio
= syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio");
311 dev_err(&pdev
->dev
, "missing hsio syscon\n");
312 return PTR_ERR(hsio
);
315 ocelot
->targets
[HSIO
] = hsio
;
317 err
= ocelot_chip_init(ocelot
, &ocelot_ops
);
321 irq_xtr
= platform_get_irq_byname(pdev
, "xtr");
325 err
= devm_request_threaded_irq(&pdev
->dev
, irq_xtr
, NULL
,
326 ocelot_xtr_irq_handler
, IRQF_ONESHOT
,
327 "frame extraction", ocelot
);
331 irq_ptp_rdy
= platform_get_irq_byname(pdev
, "ptp_rdy");
332 if (irq_ptp_rdy
> 0 && ocelot
->targets
[PTP
]) {
333 err
= devm_request_threaded_irq(&pdev
->dev
, irq_ptp_rdy
, NULL
,
334 ocelot_ptp_rdy_irq_handler
,
335 IRQF_ONESHOT
, "ptp ready",
340 /* Both the PTP interrupt and the PTP bank are available */
344 ocelot
->num_cpu_ports
= 1; /* 1 port on the switch, two groups */
346 ports
= of_get_child_by_name(np
, "ethernet-ports");
348 dev_err(&pdev
->dev
, "no ethernet-ports child node found\n");
352 ocelot
->num_phys_ports
= of_get_child_count(ports
);
354 ocelot
->ports
= devm_kcalloc(&pdev
->dev
, ocelot
->num_phys_ports
,
355 sizeof(struct ocelot_port
*), GFP_KERNEL
);
358 ocelot_set_cpu_port(ocelot
, ocelot
->num_phys_ports
,
359 OCELOT_TAG_PREFIX_NONE
, OCELOT_TAG_PREFIX_NONE
);
361 for_each_available_child_of_node(ports
, portnp
) {
362 struct ocelot_port_private
*priv
;
363 struct ocelot_port
*ocelot_port
;
364 struct device_node
*phy_node
;
365 phy_interface_t phy_mode
;
366 struct phy_device
*phy
;
367 struct resource
*res
;
373 if (of_property_read_u32(portnp
, "reg", &port
))
376 snprintf(res_name
, sizeof(res_name
), "port%d", port
);
378 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
380 regs
= devm_ioremap_resource(&pdev
->dev
, res
);
384 phy_node
= of_parse_phandle(portnp
, "phy-handle", 0);
388 phy
= of_phy_find_device(phy_node
);
389 of_node_put(phy_node
);
393 err
= ocelot_probe_port(ocelot
, port
, regs
, phy
);
399 ocelot_port
= ocelot
->ports
[port
];
400 priv
= container_of(ocelot_port
, struct ocelot_port_private
,
403 of_get_phy_mode(portnp
, &phy_mode
);
405 priv
->phy_mode
= phy_mode
;
407 switch (priv
->phy_mode
) {
408 case PHY_INTERFACE_MODE_NA
:
410 case PHY_INTERFACE_MODE_SGMII
:
412 case PHY_INTERFACE_MODE_QSGMII
:
413 /* Ensure clock signals and speed is set on all
416 ocelot_port_writel(ocelot_port
,
417 DEV_CLOCK_CFG_LINK_SPEED
423 "invalid phy mode for port%d, (Q)SGMII only\n",
430 serdes
= devm_of_phy_get(ocelot
->dev
, portnp
, NULL
);
431 if (IS_ERR(serdes
)) {
432 err
= PTR_ERR(serdes
);
433 if (err
== -EPROBE_DEFER
)
434 dev_dbg(ocelot
->dev
, "deferring probe\n");
437 "missing SerDes phys for port%d\n",
444 priv
->serdes
= serdes
;
447 register_netdevice_notifier(&ocelot_netdevice_nb
);
448 register_switchdev_notifier(&ocelot_switchdev_nb
);
449 register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb
);
451 dev_info(&pdev
->dev
, "Ocelot switch probed\n");
458 static int mscc_ocelot_remove(struct platform_device
*pdev
)
460 struct ocelot
*ocelot
= platform_get_drvdata(pdev
);
462 ocelot_deinit(ocelot
);
463 unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb
);
464 unregister_switchdev_notifier(&ocelot_switchdev_nb
);
465 unregister_netdevice_notifier(&ocelot_netdevice_nb
);
470 static struct platform_driver mscc_ocelot_driver
= {
471 .probe
= mscc_ocelot_probe
,
472 .remove
= mscc_ocelot_remove
,
474 .name
= "ocelot-switch",
475 .of_match_table
= mscc_ocelot_match
,
479 module_platform_driver(mscc_ocelot_driver
);
481 MODULE_DESCRIPTION("Microsemi Ocelot switch driver");
482 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
483 MODULE_LICENSE("Dual MIT/GPL");