drivers/net/ethernet/netronome/nfp/nfp_asm.h

   1 /*
   2  * Copyright (C) 2016 Netronome Systems, Inc.
   3  *
   4  * This software is dual licensed under the GNU General License Version 2,
   5  * June 1991 as shown in the file COPYING in the top-level directory of this
   6  * source tree or the BSD 2-Clause License provided below.  You have the
   7  * option to license this software under the complete terms of either license.
   8  *
   9  * The BSD 2-Clause License:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      1. Redistributions of source code must retain the above
  16  *         copyright notice, this list of conditions and the following
  17  *         disclaimer.
  18  *
  19  *      2. Redistributions in binary form must reproduce the above
  20  *         copyright notice, this list of conditions and the following
  21  *         disclaimer in the documentation and/or other materials
  22  *         provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #ifndef __NFP_ASM_H__
  35 #define __NFP_ASM_H__ 1
  36
  37 #include <linux/bitfield.h>
  38 #include <linux/types.h>
  39
  40 #define REG_NONE        0
  41
  42 #define RE_REG_NO_DST   0x020
  43 #define RE_REG_IMM      0x020
  44 #define RE_REG_IMM_encode(x)                                    \
  45         (RE_REG_IMM | ((x) & 0x1f) | (((x) & 0x60) << 1))
  46 #define RE_REG_IMM_MAX   0x07fULL
  47 #define RE_REG_LM       0x050
  48 #define RE_REG_LM_IDX   0x008
  49 #define RE_REG_LM_IDX_MAX       0x7
  50 #define RE_REG_XFR      0x080
  51
  52 #define UR_REG_XFR      0x180
  53 #define UR_REG_LM       0x200
  54 #define UR_REG_LM_IDX   0x020
  55 #define UR_REG_LM_POST_MOD      0x010
  56 #define UR_REG_LM_POST_MOD_DEC  0x001
  57 #define UR_REG_LM_IDX_MAX       0xf
  58 #define UR_REG_NN       0x280
  59 #define UR_REG_NO_DST   0x300
  60 #define UR_REG_IMM      UR_REG_NO_DST
  61 #define UR_REG_IMM_encode(x) (UR_REG_IMM | (x))
  62 #define UR_REG_IMM_MAX   0x0ffULL
  63
  64 #define OP_BR_BASE              0x0d800000020ULL
  65 #define OP_BR_BASE_MASK         0x0f8000c3ce0ULL
  66 #define OP_BR_MASK              0x0000000001fULL
  67 #define OP_BR_EV_PIP            0x00000000300ULL
  68 #define OP_BR_CSS               0x0000003c000ULL
  69 #define OP_BR_DEFBR             0x00000300000ULL
  70 #define OP_BR_ADDR_LO           0x007ffc00000ULL
  71 #define OP_BR_ADDR_HI           0x10000000000ULL
  72
  73 #define nfp_is_br(_insn)                                \
  74         (((_insn) & OP_BR_BASE_MASK) == OP_BR_BASE)
  75
  76 enum br_mask {
  77         BR_BEQ = 0x00,
  78         BR_BNE = 0x01,
  79         BR_BHS = 0x04,
  80         BR_BLO = 0x05,
  81         BR_BGE = 0x08,
  82         BR_UNC = 0x18,
  83 };
  84
  85 enum br_ev_pip {
  86         BR_EV_PIP_UNCOND = 0,
  87         BR_EV_PIP_COND = 1,
  88 };
  89
  90 enum br_ctx_signal_state {
  91         BR_CSS_NONE = 2,
  92 };
  93
  94 #define OP_BBYTE_BASE           0x0c800000000ULL
  95 #define OP_BB_A_SRC             0x000000000ffULL
  96 #define OP_BB_BYTE              0x00000000300ULL
  97 #define OP_BB_B_SRC             0x0000003fc00ULL
  98 #define OP_BB_I8                0x00000040000ULL
  99 #define OP_BB_EQ                0x00000080000ULL
 100 #define OP_BB_DEFBR             0x00000300000ULL
 101 #define OP_BB_ADDR_LO           0x007ffc00000ULL
 102 #define OP_BB_ADDR_HI           0x10000000000ULL
 103 #define OP_BB_SRC_LMEXTN        0x40000000000ULL
 104
 105 #define OP_BALU_BASE            0x0e800000000ULL
 106 #define OP_BA_A_SRC             0x000000003ffULL
 107 #define OP_BA_B_SRC             0x000000ffc00ULL
 108 #define OP_BA_DEFBR             0x00000300000ULL
 109 #define OP_BA_ADDR_HI           0x0007fc00000ULL
 110
 111 #define OP_IMMED_A_SRC          0x000000003ffULL
 112 #define OP_IMMED_B_SRC          0x000000ffc00ULL
 113 #define OP_IMMED_IMM            0x0000ff00000ULL
 114 #define OP_IMMED_WIDTH          0x00060000000ULL
 115 #define OP_IMMED_INV            0x00080000000ULL
 116 #define OP_IMMED_SHIFT          0x00600000000ULL
 117 #define OP_IMMED_BASE           0x0f000000000ULL
 118 #define OP_IMMED_WR_AB          0x20000000000ULL
 119 #define OP_IMMED_SRC_LMEXTN     0x40000000000ULL
 120 #define OP_IMMED_DST_LMEXTN     0x80000000000ULL
 121
 122 enum immed_width {
 123         IMMED_WIDTH_ALL = 0,
 124         IMMED_WIDTH_BYTE = 1,
 125         IMMED_WIDTH_WORD = 2,
 126 };
 127
 128 enum immed_shift {
 129         IMMED_SHIFT_0B = 0,
 130         IMMED_SHIFT_1B = 1,
 131         IMMED_SHIFT_2B = 2,
 132 };
 133
 134 #define OP_SHF_BASE             0x08000000000ULL
 135 #define OP_SHF_A_SRC            0x000000000ffULL
 136 #define OP_SHF_SC               0x00000000300ULL
 137 #define OP_SHF_B_SRC            0x0000003fc00ULL
 138 #define OP_SHF_I8               0x00000040000ULL
 139 #define OP_SHF_SW               0x00000080000ULL
 140 #define OP_SHF_DST              0x0000ff00000ULL
 141 #define OP_SHF_SHIFT            0x001f0000000ULL
 142 #define OP_SHF_OP               0x00e00000000ULL
 143 #define OP_SHF_DST_AB           0x01000000000ULL
 144 #define OP_SHF_WR_AB            0x20000000000ULL
 145 #define OP_SHF_SRC_LMEXTN       0x40000000000ULL
 146 #define OP_SHF_DST_LMEXTN       0x80000000000ULL
 147
 148 enum shf_op {
 149         SHF_OP_NONE = 0,
 150         SHF_OP_AND = 2,
 151         SHF_OP_OR = 5,
 152 };
 153
 154 enum shf_sc {
 155         SHF_SC_R_ROT = 0,
 156         SHF_SC_R_SHF = 1,
 157         SHF_SC_L_SHF = 2,
 158         SHF_SC_R_DSHF = 3,
 159 };
 160
 161 #define OP_ALU_A_SRC            0x000000003ffULL
 162 #define OP_ALU_B_SRC            0x000000ffc00ULL
 163 #define OP_ALU_DST              0x0003ff00000ULL
 164 #define OP_ALU_SW               0x00040000000ULL
 165 #define OP_ALU_OP               0x00f80000000ULL
 166 #define OP_ALU_DST_AB           0x01000000000ULL
 167 #define OP_ALU_BASE             0x0a000000000ULL
 168 #define OP_ALU_WR_AB            0x20000000000ULL
 169 #define OP_ALU_SRC_LMEXTN       0x40000000000ULL
 170 #define OP_ALU_DST_LMEXTN       0x80000000000ULL
 171
 172 enum alu_op {
 173         ALU_OP_NONE     = 0x00,
 174         ALU_OP_ADD      = 0x01,
 175         ALU_OP_NEG      = 0x04,
 176         ALU_OP_AND      = 0x08,
 177         ALU_OP_SUB_C    = 0x0d,
 178         ALU_OP_ADD_C    = 0x11,
 179         ALU_OP_OR       = 0x14,
 180         ALU_OP_SUB      = 0x15,
 181         ALU_OP_XOR      = 0x18,
 182 };
 183
 184 enum alu_dst_ab {
 185         ALU_DST_A = 0,
 186         ALU_DST_B = 1,
 187 };
 188
 189 #define OP_LDF_BASE             0x0c000000000ULL
 190 #define OP_LDF_A_SRC            0x000000000ffULL
 191 #define OP_LDF_SC               0x00000000300ULL
 192 #define OP_LDF_B_SRC            0x0000003fc00ULL
 193 #define OP_LDF_I8               0x00000040000ULL
 194 #define OP_LDF_SW               0x00000080000ULL
 195 #define OP_LDF_ZF               0x00000100000ULL
 196 #define OP_LDF_BMASK            0x0000f000000ULL
 197 #define OP_LDF_SHF              0x001f0000000ULL
 198 #define OP_LDF_WR_AB            0x20000000000ULL
 199 #define OP_LDF_SRC_LMEXTN       0x40000000000ULL
 200 #define OP_LDF_DST_LMEXTN       0x80000000000ULL
 201
 202 #define OP_CMD_A_SRC            0x000000000ffULL
 203 #define OP_CMD_CTX              0x00000000300ULL
 204 #define OP_CMD_B_SRC            0x0000003fc00ULL
 205 #define OP_CMD_TOKEN            0x000000c0000ULL
 206 #define OP_CMD_XFER             0x00001f00000ULL
 207 #define OP_CMD_CNT              0x0000e000000ULL
 208 #define OP_CMD_SIG              0x000f0000000ULL
 209 #define OP_CMD_TGT_CMD          0x07f00000000ULL
 210 #define OP_CMD_MODE            0x1c0000000000ULL
 211
 212 struct cmd_tgt_act {
 213         u8 token;
 214         u8 tgt_cmd;
 215 };
 216
 217 enum cmd_tgt_map {
 218         CMD_TGT_READ8,
 219         CMD_TGT_WRITE8,
 220         CMD_TGT_READ_LE,
 221         CMD_TGT_READ_SWAP_LE,
 222         __CMD_TGT_MAP_SIZE,
 223 };
 224
 225 extern const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE];
 226
 227 enum cmd_mode {
 228         CMD_MODE_40b_AB = 0,
 229         CMD_MODE_40b_BA = 1,
 230         CMD_MODE_32b    = 4,
 231 };
 232
 233 enum cmd_ctx_swap {
 234         CMD_CTX_SWAP = 0,
 235         CMD_CTX_NO_SWAP = 3,
 236 };
 237
 238 #define OP_LCSR_BASE            0x0fc00000000ULL
 239 #define OP_LCSR_A_SRC           0x000000003ffULL
 240 #define OP_LCSR_B_SRC           0x000000ffc00ULL
 241 #define OP_LCSR_WRITE           0x00000200000ULL
 242 #define OP_LCSR_ADDR            0x001ffc00000ULL
 243 #define OP_LCSR_SRC_LMEXTN      0x40000000000ULL
 244 #define OP_LCSR_DST_LMEXTN      0x80000000000ULL
 245
 246 enum lcsr_wr_src {
 247         LCSR_WR_AREG,
 248         LCSR_WR_BREG,
 249         LCSR_WR_IMM,
 250 };
 251
 252 #define OP_CARB_BASE            0x0e000000000ULL
 253 #define OP_CARB_OR              0x00000010000ULL
 254
 255 /* Software register representation, independent of operand type */
 256 #define NN_REG_TYPE     GENMASK(31, 24)
 257 #define NN_REG_LM_IDX   GENMASK(23, 22)
 258 #define NN_REG_LM_IDX_HI        BIT(23)
 259 #define NN_REG_LM_IDX_LO        BIT(22)
 260 #define NN_REG_LM_MOD   GENMASK(21, 20)
 261 #define NN_REG_VAL      GENMASK(7, 0)
 262
 263 enum nfp_bpf_reg_type {
 264         NN_REG_GPR_A =  BIT(0),
 265         NN_REG_GPR_B =  BIT(1),
 266         NN_REG_GPR_BOTH = NN_REG_GPR_A | NN_REG_GPR_B,
 267         NN_REG_NNR =    BIT(2),
 268         NN_REG_XFER =   BIT(3),
 269         NN_REG_IMM =    BIT(4),
 270         NN_REG_NONE =   BIT(5),
 271         NN_REG_LMEM =   BIT(6),
 272 };
 273
 274 enum nfp_bpf_lm_mode {
 275         NN_LM_MOD_NONE = 0,
 276         NN_LM_MOD_INC,
 277         NN_LM_MOD_DEC,
 278 };
 279
 280 #define reg_both(x)     __enc_swreg((x), NN_REG_GPR_BOTH)
 281 #define reg_a(x)        __enc_swreg((x), NN_REG_GPR_A)
 282 #define reg_b(x)        __enc_swreg((x), NN_REG_GPR_B)
 283 #define reg_nnr(x)      __enc_swreg((x), NN_REG_NNR)
 284 #define reg_xfer(x)     __enc_swreg((x), NN_REG_XFER)
 285 #define reg_imm(x)      __enc_swreg((x), NN_REG_IMM)
 286 #define reg_none()      __enc_swreg(0, NN_REG_NONE)
 287 #define reg_lm(x, off)  __enc_swreg_lm((x), NN_LM_MOD_NONE, (off))
 288 #define reg_lm_inc(x)   __enc_swreg_lm((x), NN_LM_MOD_INC, 0)
 289 #define reg_lm_dec(x)   __enc_swreg_lm((x), NN_LM_MOD_DEC, 0)
 290 #define __reg_lm(x, mod, off)   __enc_swreg_lm((x), (mod), (off))
 291
 292 typedef __u32 __bitwise swreg;
 293
 294 static inline swreg __enc_swreg(u16 id, u8 type)
 295 {
 296         return (__force swreg)(id | FIELD_PREP(NN_REG_TYPE, type));
 297 }
 298
 299 static inline swreg __enc_swreg_lm(u8 id, enum nfp_bpf_lm_mode mode, u8 off)
 300 {
 301         WARN_ON(id > 3 || (off && mode != NN_LM_MOD_NONE));
 302
 303         return (__force swreg)(FIELD_PREP(NN_REG_TYPE, NN_REG_LMEM) |
 304                                FIELD_PREP(NN_REG_LM_IDX, id) |
 305                                FIELD_PREP(NN_REG_LM_MOD, mode) |
 306                                off);
 307 }
 308
 309 static inline u32 swreg_raw(swreg reg)
 310 {
 311         return (__force u32)reg;
 312 }
 313
 314 static inline enum nfp_bpf_reg_type swreg_type(swreg reg)
 315 {
 316         return FIELD_GET(NN_REG_TYPE, swreg_raw(reg));
 317 }
 318
 319 static inline u16 swreg_value(swreg reg)
 320 {
 321         return FIELD_GET(NN_REG_VAL, swreg_raw(reg));
 322 }
 323
 324 static inline bool swreg_lm_idx(swreg reg)
 325 {
 326         return FIELD_GET(NN_REG_LM_IDX_LO, swreg_raw(reg));
 327 }
 328
 329 static inline bool swreg_lmextn(swreg reg)
 330 {
 331         return FIELD_GET(NN_REG_LM_IDX_HI, swreg_raw(reg));
 332 }
 333
 334 static inline enum nfp_bpf_lm_mode swreg_lm_mode(swreg reg)
 335 {
 336         return FIELD_GET(NN_REG_LM_MOD, swreg_raw(reg));
 337 }
 338
 339 struct nfp_insn_ur_regs {
 340         enum alu_dst_ab dst_ab;
 341         u16 dst;
 342         u16 areg, breg;
 343         bool swap;
 344         bool wr_both;
 345         bool dst_lmextn;
 346         bool src_lmextn;
 347 };
 348
 349 struct nfp_insn_re_regs {
 350         enum alu_dst_ab dst_ab;
 351         u8 dst;
 352         u8 areg, breg;
 353         bool swap;
 354         bool wr_both;
 355         bool i8;
 356         bool dst_lmextn;
 357         bool src_lmextn;
 358 };
 359
 360 int swreg_to_unrestricted(swreg dst, swreg lreg, swreg rreg,
 361                           struct nfp_insn_ur_regs *reg);
 362 int swreg_to_restricted(swreg dst, swreg lreg, swreg rreg,
 363                         struct nfp_insn_re_regs *reg, bool has_imm8);
 364
 365 #endif