drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h

   1 /*
   2  * Copyright (C) 2015-2017 Netronome Systems, Inc.
   3  *
   4  * This software is dual licensed under the GNU General License Version 2,
   5  * June 1991 as shown in the file COPYING in the top-level directory of this
   6  * source tree or the BSD 2-Clause License provided below.  You have the
   7  * option to license this software under the complete terms of either license.
   8  *
   9  * The BSD 2-Clause License:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      1. Redistributions of source code must retain the above
  16  *         copyright notice, this list of conditions and the following
  17  *         disclaimer.
  18  *
  19  *      2. Redistributions in binary form must reproduce the above
  20  *         copyright notice, this list of conditions and the following
  21  *         disclaimer in the documentation and/or other materials
  22  *         provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 /*
  35  * nfp_net_ctrl.h
  36  * Netronome network device driver: Control BAR layout
  37  * Authors: Jakub Kicinski <jakub.kicinski@netronome.com>
  38  *          Jason McMullan <jason.mcmullan@netronome.com>
  39  *          Rolf Neugebauer <rolf.neugebauer@netronome.com>
  40  *          Brad Petrus <brad.petrus@netronome.com>
  41  */
  42
  43 #ifndef _NFP_NET_CTRL_H_
  44 #define _NFP_NET_CTRL_H_
  45
  46 /* IMPORTANT: This header file is shared with the FW,
  47  *            no OS specific constructs, please!
  48  */
  49
  50 /**
  51  * Configuration BAR size.
  52  *
  53  * The configuration BAR is 8K in size, but due to
  54  * THB-350, 32k needs to be reserved.
  55  */
  56 #define NFP_NET_CFG_BAR_SZ              (32 * 1024)
  57
  58 /**
  59  * Offset in Freelist buffer where packet starts on RX
  60  */
  61 #define NFP_NET_RX_OFFSET               32
  62
  63 /**
  64  * Maximum header size supported for LSO frames
  65  */
  66 #define NFP_NET_LSO_MAX_HDR_SZ          255
  67
  68 /**
  69  * Prepend field types
  70  */
  71 #define NFP_NET_META_FIELD_SIZE         4
  72 #define NFP_NET_META_HASH               1 /* next field carries hash type */
  73 #define NFP_NET_META_MARK               2
  74
  75 /**
  76  * Hash type pre-pended when a RSS hash was computed
  77  */
  78 #define NFP_NET_RSS_NONE                0
  79 #define NFP_NET_RSS_IPV4                1
  80 #define NFP_NET_RSS_IPV6                2
  81 #define NFP_NET_RSS_IPV6_EX             3
  82 #define NFP_NET_RSS_IPV4_TCP            4
  83 #define NFP_NET_RSS_IPV6_TCP            5
  84 #define NFP_NET_RSS_IPV6_EX_TCP         6
  85 #define NFP_NET_RSS_IPV4_UDP            7
  86 #define NFP_NET_RSS_IPV6_UDP            8
  87 #define NFP_NET_RSS_IPV6_EX_UDP         9
  88
  89 /**
  90  * @NFP_NET_TXR_MAX:         Maximum number of TX rings
  91  * @NFP_NET_RXR_MAX:         Maximum number of RX rings
  92  */
  93 #define NFP_NET_TXR_MAX                 64
  94 #define NFP_NET_RXR_MAX                 64
  95
  96 /**
  97  * Read/Write config words (0x0000 - 0x002c)
  98  * @NFP_NET_CFG_CTRL:        Global control
  99  * @NFP_NET_CFG_UPDATE:      Indicate which fields are updated
 100  * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings
 101  * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings
 102  * @NFP_NET_CFG_MTU:         Set MTU size
 103  * @NFP_NET_CFG_FLBUFSZ:     Set freelist buffer size (must be larger than MTU)
 104  * @NFP_NET_CFG_EXN:         MSI-X table entry for exceptions
 105  * @NFP_NET_CFG_LSC:         MSI-X table entry for link state changes
 106  * @NFP_NET_CFG_MACADDR:     MAC address
 107  *
 108  * TODO:
 109  * - define Error details in UPDATE
 110  */
 111 #define NFP_NET_CFG_CTRL                0x0000
 112 #define   NFP_NET_CFG_CTRL_ENABLE         (0x1 <<  0) /* Global enable */
 113 #define   NFP_NET_CFG_CTRL_PROMISC        (0x1 <<  1) /* Enable Promisc mode */
 114 #define   NFP_NET_CFG_CTRL_L2BC           (0x1 <<  2) /* Allow L2 Broadcast */
 115 #define   NFP_NET_CFG_CTRL_L2MC           (0x1 <<  3) /* Allow L2 Multicast */
 116 #define   NFP_NET_CFG_CTRL_RXCSUM         (0x1 <<  4) /* Enable RX Checksum */
 117 #define   NFP_NET_CFG_CTRL_TXCSUM         (0x1 <<  5) /* Enable TX Checksum */
 118 #define   NFP_NET_CFG_CTRL_RXVLAN         (0x1 <<  6) /* Enable VLAN strip */
 119 #define   NFP_NET_CFG_CTRL_TXVLAN         (0x1 <<  7) /* Enable VLAN insert */
 120 #define   NFP_NET_CFG_CTRL_SCATTER        (0x1 <<  8) /* Scatter DMA */
 121 #define   NFP_NET_CFG_CTRL_GATHER         (0x1 <<  9) /* Gather DMA */
 122 #define   NFP_NET_CFG_CTRL_LSO            (0x1 << 10) /* LSO/TSO */
 123 #define   NFP_NET_CFG_CTRL_RINGCFG        (0x1 << 16) /* Ring runtime changes */
 124 #define   NFP_NET_CFG_CTRL_RSS            (0x1 << 17) /* RSS */
 125 #define   NFP_NET_CFG_CTRL_IRQMOD         (0x1 << 18) /* Interrupt moderation */
 126 #define   NFP_NET_CFG_CTRL_RINGPRIO       (0x1 << 19) /* Ring priorities */
 127 #define   NFP_NET_CFG_CTRL_MSIXAUTO       (0x1 << 20) /* MSI-X auto-masking */
 128 #define   NFP_NET_CFG_CTRL_TXRWB          (0x1 << 21) /* Write-back of TX ring*/
 129 #define   NFP_NET_CFG_CTRL_L2SWITCH       (0x1 << 22) /* L2 Switch */
 130 #define   NFP_NET_CFG_CTRL_L2SWITCH_LOCAL (0x1 << 23) /* Switch to local */
 131 #define   NFP_NET_CFG_CTRL_VXLAN          (0x1 << 24) /* VXLAN tunnel support */
 132 #define   NFP_NET_CFG_CTRL_NVGRE          (0x1 << 25) /* NVGRE tunnel support */
 133 #define   NFP_NET_CFG_CTRL_BPF            (0x1 << 27) /* BPF offload capable */
 134 #define NFP_NET_CFG_UPDATE              0x0004
 135 #define   NFP_NET_CFG_UPDATE_GEN          (0x1 <<  0) /* General update */
 136 #define   NFP_NET_CFG_UPDATE_RING         (0x1 <<  1) /* Ring config change */
 137 #define   NFP_NET_CFG_UPDATE_RSS          (0x1 <<  2) /* RSS config change */
 138 #define   NFP_NET_CFG_UPDATE_TXRPRIO      (0x1 <<  3) /* TX Ring prio change */
 139 #define   NFP_NET_CFG_UPDATE_RXRPRIO      (0x1 <<  4) /* RX Ring prio change */
 140 #define   NFP_NET_CFG_UPDATE_MSIX         (0x1 <<  5) /* MSI-X change */
 141 #define   NFP_NET_CFG_UPDATE_L2SWITCH     (0x1 <<  6) /* Switch changes */
 142 #define   NFP_NET_CFG_UPDATE_RESET        (0x1 <<  7) /* Update due to FLR */
 143 #define   NFP_NET_CFG_UPDATE_IRQMOD       (0x1 <<  8) /* IRQ mod change */
 144 #define   NFP_NET_CFG_UPDATE_VXLAN        (0x1 <<  9) /* VXLAN port change */
 145 #define   NFP_NET_CFG_UPDATE_BPF          (0x1 << 10) /* BPF program load */
 146 #define   NFP_NET_CFG_UPDATE_ERR          (0x1 << 31) /* A error occurred */
 147 #define NFP_NET_CFG_TXRS_ENABLE         0x0008
 148 #define NFP_NET_CFG_RXRS_ENABLE         0x0010
 149 #define NFP_NET_CFG_MTU                 0x0018
 150 #define NFP_NET_CFG_FLBUFSZ             0x001c
 151 #define NFP_NET_CFG_EXN                 0x001f
 152 #define NFP_NET_CFG_LSC                 0x0020
 153 #define NFP_NET_CFG_MACADDR             0x0024
 154
 155 /**
 156  * Read-only words (0x0030 - 0x0050):
 157  * @NFP_NET_CFG_VERSION:     Firmware version number
 158  * @NFP_NET_CFG_STS:         Status
 159  * @NFP_NET_CFG_CAP:         Capabilities (same bits as @NFP_NET_CFG_CTRL)
 160  * @NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings
 161  * @NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings
 162  * @NFP_NET_CFG_MAX_MTU:     Maximum support MTU
 163  * @NFP_NET_CFG_START_TXQ:   Start Queue Control Queue to use for TX (PF only)
 164  * @NFP_NET_CFG_START_RXQ:   Start Queue Control Queue to use for RX (PF only)
 165  *
 166  * TODO:
 167  * - define more STS bits
 168  */
 169 #define NFP_NET_CFG_VERSION             0x0030
 170 #define   NFP_NET_CFG_VERSION_RESERVED_MASK     (0xff << 24)
 171 #define   NFP_NET_CFG_VERSION_CLASS_MASK  (0xff << 16)
 172 #define   NFP_NET_CFG_VERSION_CLASS(x)    (((x) & 0xff) << 16)
 173 #define   NFP_NET_CFG_VERSION_CLASS_GENERIC     0
 174 #define   NFP_NET_CFG_VERSION_MAJOR_MASK  (0xff <<  8)
 175 #define   NFP_NET_CFG_VERSION_MAJOR(x)    (((x) & 0xff) <<  8)
 176 #define   NFP_NET_CFG_VERSION_MINOR_MASK  (0xff <<  0)
 177 #define   NFP_NET_CFG_VERSION_MINOR(x)    (((x) & 0xff) <<  0)
 178 #define NFP_NET_CFG_STS                 0x0034
 179 #define   NFP_NET_CFG_STS_LINK            (0x1 << 0) /* Link up or down */
 180 /* Link rate */
 181 #define   NFP_NET_CFG_STS_LINK_RATE_SHIFT 1
 182 #define   NFP_NET_CFG_STS_LINK_RATE_MASK  0xF
 183 #define   NFP_NET_CFG_STS_LINK_RATE       \
 184         (NFP_NET_CFG_STS_LINK_RATE_MASK << NFP_NET_CFG_STS_LINK_RATE_SHIFT)
 185 #define   NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED   0
 186 #define   NFP_NET_CFG_STS_LINK_RATE_UNKNOWN       1
 187 #define   NFP_NET_CFG_STS_LINK_RATE_1G            2
 188 #define   NFP_NET_CFG_STS_LINK_RATE_10G           3
 189 #define   NFP_NET_CFG_STS_LINK_RATE_25G           4
 190 #define   NFP_NET_CFG_STS_LINK_RATE_40G           5
 191 #define   NFP_NET_CFG_STS_LINK_RATE_50G           6
 192 #define   NFP_NET_CFG_STS_LINK_RATE_100G          7
 193 #define NFP_NET_CFG_CAP                 0x0038
 194 #define NFP_NET_CFG_MAX_TXRINGS         0x003c
 195 #define NFP_NET_CFG_MAX_RXRINGS         0x0040
 196 #define NFP_NET_CFG_MAX_MTU             0x0044
 197 /* Next two words are being used by VFs for solving THB350 issue */
 198 #define NFP_NET_CFG_START_TXQ           0x0048
 199 #define NFP_NET_CFG_START_RXQ           0x004c
 200
 201 /**
 202  * Prepend configuration
 203  */
 204 #define NFP_NET_CFG_RX_OFFSET           0x0050
 205 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC           0       /* Prepend mode */
 206
 207 /**
 208  * RSS capabilities
 209  * @NFP_NET_CFG_RSS_CAP_HFUNC:  supported hash functions (same bits as
 210  *                              @NFP_NET_CFG_RSS_HFUNC)
 211  */
 212 #define NFP_NET_CFG_RSS_CAP             0x0054
 213 #define   NFP_NET_CFG_RSS_CAP_HFUNC       0xff000000
 214
 215 /**
 216  * VXLAN/UDP encap configuration
 217  * @NFP_NET_CFG_VXLAN_PORT:     Base address of table of tunnels' UDP dst ports
 218  * @NFP_NET_CFG_VXLAN_SZ:       Size of the UDP port table in bytes
 219  */
 220 #define NFP_NET_CFG_VXLAN_PORT          0x0060
 221 #define NFP_NET_CFG_VXLAN_SZ              0x0008
 222
 223 /**
 224  * BPF section
 225  * @NFP_NET_CFG_BPF_ABI:        BPF ABI version
 226  * @NFP_NET_CFG_BPF_CAP:        BPF capabilities
 227  * @NFP_NET_CFG_BPF_MAX_LEN:    Maximum size of JITed BPF code in bytes
 228  * @NFP_NET_CFG_BPF_START:      Offset at which BPF will be loaded
 229  * @NFP_NET_CFG_BPF_DONE:       Offset to jump to on exit
 230  * @NFP_NET_CFG_BPF_STACK_SZ:   Total size of stack area in 64B chunks
 231  * @NFP_NET_CFG_BPF_INL_MTU:    Packet data split offset in 64B chunks
 232  * @NFP_NET_CFG_BPF_SIZE:       Size of the JITed BPF code in instructions
 233  * @NFP_NET_CFG_BPF_ADDR:       DMA address of the buffer with JITed BPF code
 234  */
 235 #define NFP_NET_CFG_BPF_ABI             0x0080
 236 #define   NFP_NET_BPF_ABI               1
 237 #define NFP_NET_CFG_BPF_CAP             0x0081
 238 #define   NFP_NET_BPF_CAP_RELO          (1 << 0) /* seamless reload */
 239 #define NFP_NET_CFG_BPF_MAX_LEN         0x0082
 240 #define NFP_NET_CFG_BPF_START           0x0084
 241 #define NFP_NET_CFG_BPF_DONE            0x0086
 242 #define NFP_NET_CFG_BPF_STACK_SZ        0x0088
 243 #define NFP_NET_CFG_BPF_INL_MTU         0x0089
 244 #define NFP_NET_CFG_BPF_SIZE            0x008e
 245 #define NFP_NET_CFG_BPF_ADDR            0x0090
 246 #define   NFP_NET_CFG_BPF_CFG_8CTX      (1 << 0) /* 8ctx mode */
 247 #define   NFP_NET_CFG_BPF_CFG_MASK      7ULL
 248 #define   NFP_NET_CFG_BPF_ADDR_MASK     (~NFP_NET_CFG_BPF_CFG_MASK)
 249
 250 /**
 251  * 40B reserved for future use (0x0098 - 0x00c0)
 252  */
 253 #define NFP_NET_CFG_RESERVED            0x0098
 254 #define NFP_NET_CFG_RESERVED_SZ         0x0028
 255
 256 /**
 257  * RSS configuration (0x0100 - 0x01ac):
 258  * Used only when NFP_NET_CFG_CTRL_RSS is enabled
 259  * @NFP_NET_CFG_RSS_CFG:     RSS configuration word
 260  * @NFP_NET_CFG_RSS_KEY:     RSS "secret" key
 261  * @NFP_NET_CFG_RSS_ITBL:    RSS indirection table
 262  */
 263 #define NFP_NET_CFG_RSS_BASE            0x0100
 264 #define NFP_NET_CFG_RSS_CTRL            NFP_NET_CFG_RSS_BASE
 265 #define   NFP_NET_CFG_RSS_MASK            (0x7f)
 266 #define   NFP_NET_CFG_RSS_MASK_of(_x)     ((_x) & 0x7f)
 267 #define   NFP_NET_CFG_RSS_IPV4            (1 <<  8) /* RSS for IPv4 */
 268 #define   NFP_NET_CFG_RSS_IPV6            (1 <<  9) /* RSS for IPv6 */
 269 #define   NFP_NET_CFG_RSS_IPV4_TCP        (1 << 10) /* RSS for IPv4/TCP */
 270 #define   NFP_NET_CFG_RSS_IPV4_UDP        (1 << 11) /* RSS for IPv4/UDP */
 271 #define   NFP_NET_CFG_RSS_IPV6_TCP        (1 << 12) /* RSS for IPv6/TCP */
 272 #define   NFP_NET_CFG_RSS_IPV6_UDP        (1 << 13) /* RSS for IPv6/UDP */
 273 #define   NFP_NET_CFG_RSS_HFUNC           0xff000000
 274 #define   NFP_NET_CFG_RSS_TOEPLITZ        (1 << 24) /* Use Toeplitz hash */
 275 #define   NFP_NET_CFG_RSS_XOR             (1 << 25) /* Use XOR as hash */
 276 #define   NFP_NET_CFG_RSS_CRC32           (1 << 26) /* Use CRC32 as hash */
 277 #define   NFP_NET_CFG_RSS_HFUNCS          3
 278 #define NFP_NET_CFG_RSS_KEY             (NFP_NET_CFG_RSS_BASE + 0x4)
 279 #define NFP_NET_CFG_RSS_KEY_SZ          0x28
 280 #define NFP_NET_CFG_RSS_ITBL            (NFP_NET_CFG_RSS_BASE + 0x4 + \
 281                                          NFP_NET_CFG_RSS_KEY_SZ)
 282 #define NFP_NET_CFG_RSS_ITBL_SZ         0x80
 283
 284 /**
 285  * TX ring configuration (0x200 - 0x800)
 286  * @NFP_NET_CFG_TXR_BASE:    Base offset for TX ring configuration
 287  * @NFP_NET_CFG_TXR_ADDR:    Per TX ring DMA address (8B entries)
 288  * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries)
 289  * @NFP_NET_CFG_TXR_SZ:      Per TX ring ring size (1B entries)
 290  * @NFP_NET_CFG_TXR_VEC:     Per TX ring MSI-X table entry (1B entries)
 291  * @NFP_NET_CFG_TXR_PRIO:    Per TX ring priority (1B entries)
 292  * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet
 293  */
 294 #define NFP_NET_CFG_TXR_BASE            0x0200
 295 #define NFP_NET_CFG_TXR_ADDR(_x)        (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))
 296 #define NFP_NET_CFG_TXR_WB_ADDR(_x)     (NFP_NET_CFG_TXR_BASE + 0x200 + \
 297                                          ((_x) * 0x8))
 298 #define NFP_NET_CFG_TXR_SZ(_x)          (NFP_NET_CFG_TXR_BASE + 0x400 + (_x))
 299 #define NFP_NET_CFG_TXR_VEC(_x)         (NFP_NET_CFG_TXR_BASE + 0x440 + (_x))
 300 #define NFP_NET_CFG_TXR_PRIO(_x)        (NFP_NET_CFG_TXR_BASE + 0x480 + (_x))
 301 #define NFP_NET_CFG_TXR_IRQ_MOD(_x)     (NFP_NET_CFG_TXR_BASE + 0x500 + \
 302                                          ((_x) * 0x4))
 303
 304 /**
 305  * RX ring configuration (0x0800 - 0x0c00)
 306  * @NFP_NET_CFG_RXR_BASE:    Base offset for RX ring configuration
 307  * @NFP_NET_CFG_RXR_ADDR:    Per RX ring DMA address (8B entries)
 308  * @NFP_NET_CFG_RXR_SZ:      Per RX ring ring size (1B entries)
 309  * @NFP_NET_CFG_RXR_VEC:     Per RX ring MSI-X table entry (1B entries)
 310  * @NFP_NET_CFG_RXR_PRIO:    Per RX ring priority (1B entries)
 311  * @NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries)
 312  */
 313 #define NFP_NET_CFG_RXR_BASE            0x0800
 314 #define NFP_NET_CFG_RXR_ADDR(_x)        (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))
 315 #define NFP_NET_CFG_RXR_SZ(_x)          (NFP_NET_CFG_RXR_BASE + 0x200 + (_x))
 316 #define NFP_NET_CFG_RXR_VEC(_x)         (NFP_NET_CFG_RXR_BASE + 0x240 + (_x))
 317 #define NFP_NET_CFG_RXR_PRIO(_x)        (NFP_NET_CFG_RXR_BASE + 0x280 + (_x))
 318 #define NFP_NET_CFG_RXR_IRQ_MOD(_x)     (NFP_NET_CFG_RXR_BASE + 0x300 + \
 319                                          ((_x) * 0x4))
 320
 321 /**
 322  * Interrupt Control/Cause registers (0x0c00 - 0x0d00)
 323  * These registers are only used when MSI-X auto-masking is not
 324  * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set).  The array is index
 325  * by MSI-X entry and are 1B in size.  If an entry is zero, the
 326  * corresponding entry is enabled.  If the FW generates an interrupt,
 327  * it writes a cause into the corresponding field.  This also masks
 328  * the MSI-X entry and the host driver must clear the register to
 329  * re-enable the interrupt.
 330  */
 331 #define NFP_NET_CFG_ICR_BASE            0x0c00
 332 #define NFP_NET_CFG_ICR(_x)             (NFP_NET_CFG_ICR_BASE + (_x))
 333 #define   NFP_NET_CFG_ICR_UNMASKED      0x0
 334 #define   NFP_NET_CFG_ICR_RXTX          0x1
 335 #define   NFP_NET_CFG_ICR_LSC           0x2
 336
 337 /**
 338  * General device stats (0x0d00 - 0x0d90)
 339  * all counters are 64bit.
 340  */
 341 #define NFP_NET_CFG_STATS_BASE          0x0d00
 342 #define NFP_NET_CFG_STATS_RX_DISCARDS   (NFP_NET_CFG_STATS_BASE + 0x00)
 343 #define NFP_NET_CFG_STATS_RX_ERRORS     (NFP_NET_CFG_STATS_BASE + 0x08)
 344 #define NFP_NET_CFG_STATS_RX_OCTETS     (NFP_NET_CFG_STATS_BASE + 0x10)
 345 #define NFP_NET_CFG_STATS_RX_UC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x18)
 346 #define NFP_NET_CFG_STATS_RX_MC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x20)
 347 #define NFP_NET_CFG_STATS_RX_BC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x28)
 348 #define NFP_NET_CFG_STATS_RX_FRAMES     (NFP_NET_CFG_STATS_BASE + 0x30)
 349 #define NFP_NET_CFG_STATS_RX_MC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x38)
 350 #define NFP_NET_CFG_STATS_RX_BC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x40)
 351
 352 #define NFP_NET_CFG_STATS_TX_DISCARDS   (NFP_NET_CFG_STATS_BASE + 0x48)
 353 #define NFP_NET_CFG_STATS_TX_ERRORS     (NFP_NET_CFG_STATS_BASE + 0x50)
 354 #define NFP_NET_CFG_STATS_TX_OCTETS     (NFP_NET_CFG_STATS_BASE + 0x58)
 355 #define NFP_NET_CFG_STATS_TX_UC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x60)
 356 #define NFP_NET_CFG_STATS_TX_MC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x68)
 357 #define NFP_NET_CFG_STATS_TX_BC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x70)
 358 #define NFP_NET_CFG_STATS_TX_FRAMES     (NFP_NET_CFG_STATS_BASE + 0x78)
 359 #define NFP_NET_CFG_STATS_TX_MC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x80)
 360 #define NFP_NET_CFG_STATS_TX_BC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x88)
 361
 362 #define NFP_NET_CFG_STATS_APP0_FRAMES   (NFP_NET_CFG_STATS_BASE + 0x90)
 363 #define NFP_NET_CFG_STATS_APP0_BYTES    (NFP_NET_CFG_STATS_BASE + 0x98)
 364 #define NFP_NET_CFG_STATS_APP1_FRAMES   (NFP_NET_CFG_STATS_BASE + 0xa0)
 365 #define NFP_NET_CFG_STATS_APP1_BYTES    (NFP_NET_CFG_STATS_BASE + 0xa8)
 366 #define NFP_NET_CFG_STATS_APP2_FRAMES   (NFP_NET_CFG_STATS_BASE + 0xb0)
 367 #define NFP_NET_CFG_STATS_APP2_BYTES    (NFP_NET_CFG_STATS_BASE + 0xb8)
 368 #define NFP_NET_CFG_STATS_APP3_FRAMES   (NFP_NET_CFG_STATS_BASE + 0xc0)
 369 #define NFP_NET_CFG_STATS_APP3_BYTES    (NFP_NET_CFG_STATS_BASE + 0xc8)
 370
 371 /**
 372  * Per ring stats (0x1000 - 0x1800)
 373  * options, 64bit per entry
 374  * @NFP_NET_CFG_TXR_STATS:   TX ring statistics (Packet and Byte count)
 375  * @NFP_NET_CFG_RXR_STATS:   RX ring statistics (Packet and Byte count)
 376  */
 377 #define NFP_NET_CFG_TXR_STATS_BASE      0x1000
 378 #define NFP_NET_CFG_TXR_STATS(_x)       (NFP_NET_CFG_TXR_STATS_BASE + \
 379                                          ((_x) * 0x10))
 380 #define NFP_NET_CFG_RXR_STATS_BASE      0x1400
 381 #define NFP_NET_CFG_RXR_STATS(_x)       (NFP_NET_CFG_RXR_STATS_BASE + \
 382                                          ((_x) * 0x10))
 383
 384 #endif /* _NFP_NET_CTRL_H_ */