1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
5 * Note: This driver is a cleanroom reimplementation based on reverse
6 * engineered documentation written by Carl-Daniel Hailfinger
7 * and Andrew de Quincey.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4,5 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
20 * We suspect that on some hardware no TX done interrupts are generated.
21 * This means recovery from netif_stop_queue only happens if the hw timer
22 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
23 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
24 * If your hardware reliably generates tx done interrupts, then you can remove
25 * DEV_NEED_TIMERIRQ from the driver_data flags.
26 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
27 * superfluous timer interrupts from the nic.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #define FORCEDETH_VERSION "0.64"
33 #define DRV_NAME "forcedeth"
35 #include <linux/module.h>
36 #include <linux/types.h>
37 #include <linux/pci.h>
38 #include <linux/interrupt.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/delay.h>
42 #include <linux/sched.h>
43 #include <linux/spinlock.h>
44 #include <linux/ethtool.h>
45 #include <linux/timer.h>
46 #include <linux/skbuff.h>
47 #include <linux/mii.h>
48 #include <linux/random.h>
49 #include <linux/if_vlan.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/slab.h>
52 #include <linux/uaccess.h>
53 #include <linux/prefetch.h>
54 #include <linux/u64_stats_sync.h>
59 #define TX_WORK_PER_LOOP 64
60 #define RX_WORK_PER_LOOP 64
66 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
67 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
68 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
69 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
70 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
71 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
72 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
73 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
74 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
75 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
76 #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
77 #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
78 #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
79 #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
80 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
81 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
82 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
83 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
84 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
85 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
86 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
87 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
88 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
89 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
90 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
91 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
92 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
95 NvRegIrqStatus
= 0x000,
96 #define NVREG_IRQSTAT_MIIEVENT 0x040
97 #define NVREG_IRQSTAT_MASK 0x83ff
99 #define NVREG_IRQ_RX_ERROR 0x0001
100 #define NVREG_IRQ_RX 0x0002
101 #define NVREG_IRQ_RX_NOBUF 0x0004
102 #define NVREG_IRQ_TX_ERR 0x0008
103 #define NVREG_IRQ_TX_OK 0x0010
104 #define NVREG_IRQ_TIMER 0x0020
105 #define NVREG_IRQ_LINK 0x0040
106 #define NVREG_IRQ_RX_FORCED 0x0080
107 #define NVREG_IRQ_TX_FORCED 0x0100
108 #define NVREG_IRQ_RECOVER_ERROR 0x8200
109 #define NVREG_IRQMASK_THROUGHPUT 0x00df
110 #define NVREG_IRQMASK_CPU 0x0060
111 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
112 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
113 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
115 NvRegUnknownSetupReg6
= 0x008,
116 #define NVREG_UNKSETUP6_VAL 3
119 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
120 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
122 NvRegPollingInterval
= 0x00c,
123 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
124 #define NVREG_POLL_DEFAULT_CPU 13
125 NvRegMSIMap0
= 0x020,
126 NvRegMSIMap1
= 0x024,
127 NvRegMSIIrqMask
= 0x030,
128 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
130 #define NVREG_MISC1_PAUSE_TX 0x01
131 #define NVREG_MISC1_HD 0x02
132 #define NVREG_MISC1_FORCE 0x3b0f3c
134 NvRegMacReset
= 0x34,
135 #define NVREG_MAC_RESET_ASSERT 0x0F3
136 NvRegTransmitterControl
= 0x084,
137 #define NVREG_XMITCTL_START 0x01
138 #define NVREG_XMITCTL_MGMT_ST 0x40000000
139 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
140 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
141 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
142 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
143 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
144 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
145 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
146 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
147 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
148 #define NVREG_XMITCTL_DATA_START 0x00100000
149 #define NVREG_XMITCTL_DATA_READY 0x00010000
150 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
151 NvRegTransmitterStatus
= 0x088,
152 #define NVREG_XMITSTAT_BUSY 0x01
154 NvRegPacketFilterFlags
= 0x8c,
155 #define NVREG_PFF_PAUSE_RX 0x08
156 #define NVREG_PFF_ALWAYS 0x7F0000
157 #define NVREG_PFF_PROMISC 0x80
158 #define NVREG_PFF_MYADDR 0x20
159 #define NVREG_PFF_LOOPBACK 0x10
161 NvRegOffloadConfig
= 0x90,
162 #define NVREG_OFFLOAD_HOMEPHY 0x601
163 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
164 NvRegReceiverControl
= 0x094,
165 #define NVREG_RCVCTL_START 0x01
166 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
167 NvRegReceiverStatus
= 0x98,
168 #define NVREG_RCVSTAT_BUSY 0x01
170 NvRegSlotTime
= 0x9c,
171 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
172 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
173 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
174 #define NVREG_SLOTTIME_HALF 0x0000ff00
175 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
176 #define NVREG_SLOTTIME_MASK 0x000000ff
178 NvRegTxDeferral
= 0xA0,
179 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
180 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
181 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
182 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
183 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
184 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
185 NvRegRxDeferral
= 0xA4,
186 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
187 NvRegMacAddrA
= 0xA8,
188 NvRegMacAddrB
= 0xAC,
189 NvRegMulticastAddrA
= 0xB0,
190 #define NVREG_MCASTADDRA_FORCE 0x01
191 NvRegMulticastAddrB
= 0xB4,
192 NvRegMulticastMaskA
= 0xB8,
193 #define NVREG_MCASTMASKA_NONE 0xffffffff
194 NvRegMulticastMaskB
= 0xBC,
195 #define NVREG_MCASTMASKB_NONE 0xffff
197 NvRegPhyInterface
= 0xC0,
198 #define PHY_RGMII 0x10000000
199 NvRegBackOffControl
= 0xC4,
200 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
201 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
202 #define NVREG_BKOFFCTRL_SELECT 24
203 #define NVREG_BKOFFCTRL_GEAR 12
205 NvRegTxRingPhysAddr
= 0x100,
206 NvRegRxRingPhysAddr
= 0x104,
207 NvRegRingSizes
= 0x108,
208 #define NVREG_RINGSZ_TXSHIFT 0
209 #define NVREG_RINGSZ_RXSHIFT 16
210 NvRegTransmitPoll
= 0x10c,
211 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
212 NvRegLinkSpeed
= 0x110,
213 #define NVREG_LINKSPEED_FORCE 0x10000
214 #define NVREG_LINKSPEED_10 1000
215 #define NVREG_LINKSPEED_100 100
216 #define NVREG_LINKSPEED_1000 50
217 #define NVREG_LINKSPEED_MASK (0xFFF)
218 NvRegUnknownSetupReg5
= 0x130,
219 #define NVREG_UNKSETUP5_BIT31 (1<<31)
220 NvRegTxWatermark
= 0x13c,
221 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
222 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
223 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
224 NvRegTxRxControl
= 0x144,
225 #define NVREG_TXRXCTL_KICK 0x0001
226 #define NVREG_TXRXCTL_BIT1 0x0002
227 #define NVREG_TXRXCTL_BIT2 0x0004
228 #define NVREG_TXRXCTL_IDLE 0x0008
229 #define NVREG_TXRXCTL_RESET 0x0010
230 #define NVREG_TXRXCTL_RXCHECK 0x0400
231 #define NVREG_TXRXCTL_DESC_1 0
232 #define NVREG_TXRXCTL_DESC_2 0x002100
233 #define NVREG_TXRXCTL_DESC_3 0xc02200
234 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
235 #define NVREG_TXRXCTL_VLANINS 0x00080
236 NvRegTxRingPhysAddrHigh
= 0x148,
237 NvRegRxRingPhysAddrHigh
= 0x14C,
238 NvRegTxPauseFrame
= 0x170,
239 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
240 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
241 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
242 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
243 NvRegTxPauseFrameLimit
= 0x174,
244 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
245 NvRegMIIStatus
= 0x180,
246 #define NVREG_MIISTAT_ERROR 0x0001
247 #define NVREG_MIISTAT_LINKCHANGE 0x0008
248 #define NVREG_MIISTAT_MASK_RW 0x0007
249 #define NVREG_MIISTAT_MASK_ALL 0x000f
250 NvRegMIIMask
= 0x184,
251 #define NVREG_MII_LINKCHANGE 0x0008
253 NvRegAdapterControl
= 0x188,
254 #define NVREG_ADAPTCTL_START 0x02
255 #define NVREG_ADAPTCTL_LINKUP 0x04
256 #define NVREG_ADAPTCTL_PHYVALID 0x40000
257 #define NVREG_ADAPTCTL_RUNNING 0x100000
258 #define NVREG_ADAPTCTL_PHYSHIFT 24
259 NvRegMIISpeed
= 0x18c,
260 #define NVREG_MIISPEED_BIT8 (1<<8)
261 #define NVREG_MIIDELAY 5
262 NvRegMIIControl
= 0x190,
263 #define NVREG_MIICTL_INUSE 0x08000
264 #define NVREG_MIICTL_WRITE 0x00400
265 #define NVREG_MIICTL_ADDRSHIFT 5
266 NvRegMIIData
= 0x194,
267 NvRegTxUnicast
= 0x1a0,
268 NvRegTxMulticast
= 0x1a4,
269 NvRegTxBroadcast
= 0x1a8,
270 NvRegWakeUpFlags
= 0x200,
271 #define NVREG_WAKEUPFLAGS_VAL 0x7770
272 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
273 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
274 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
275 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
276 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
277 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
278 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
279 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
280 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
281 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
283 NvRegMgmtUnitGetVersion
= 0x204,
284 #define NVREG_MGMTUNITGETVERSION 0x01
285 NvRegMgmtUnitVersion
= 0x208,
286 #define NVREG_MGMTUNITVERSION 0x08
287 NvRegPowerCap
= 0x268,
288 #define NVREG_POWERCAP_D3SUPP (1<<30)
289 #define NVREG_POWERCAP_D2SUPP (1<<26)
290 #define NVREG_POWERCAP_D1SUPP (1<<25)
291 NvRegPowerState
= 0x26c,
292 #define NVREG_POWERSTATE_POWEREDUP 0x8000
293 #define NVREG_POWERSTATE_VALID 0x0100
294 #define NVREG_POWERSTATE_MASK 0x0003
295 #define NVREG_POWERSTATE_D0 0x0000
296 #define NVREG_POWERSTATE_D1 0x0001
297 #define NVREG_POWERSTATE_D2 0x0002
298 #define NVREG_POWERSTATE_D3 0x0003
299 NvRegMgmtUnitControl
= 0x278,
300 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
302 NvRegTxZeroReXmt
= 0x284,
303 NvRegTxOneReXmt
= 0x288,
304 NvRegTxManyReXmt
= 0x28c,
305 NvRegTxLateCol
= 0x290,
306 NvRegTxUnderflow
= 0x294,
307 NvRegTxLossCarrier
= 0x298,
308 NvRegTxExcessDef
= 0x29c,
309 NvRegTxRetryErr
= 0x2a0,
310 NvRegRxFrameErr
= 0x2a4,
311 NvRegRxExtraByte
= 0x2a8,
312 NvRegRxLateCol
= 0x2ac,
314 NvRegRxFrameTooLong
= 0x2b4,
315 NvRegRxOverflow
= 0x2b8,
316 NvRegRxFCSErr
= 0x2bc,
317 NvRegRxFrameAlignErr
= 0x2c0,
318 NvRegRxLenErr
= 0x2c4,
319 NvRegRxUnicast
= 0x2c8,
320 NvRegRxMulticast
= 0x2cc,
321 NvRegRxBroadcast
= 0x2d0,
323 NvRegTxFrame
= 0x2d8,
325 NvRegTxPause
= 0x2e0,
326 NvRegRxPause
= 0x2e4,
327 NvRegRxDropFrame
= 0x2e8,
328 NvRegVlanControl
= 0x300,
329 #define NVREG_VLANCONTROL_ENABLE 0x2000
330 NvRegMSIXMap0
= 0x3e0,
331 NvRegMSIXMap1
= 0x3e4,
332 NvRegMSIXIrqStatus
= 0x3f0,
334 NvRegPowerState2
= 0x600,
335 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
336 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
337 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
338 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
341 /* Big endian: should work, but is untested */
347 struct ring_desc_ex
{
355 struct ring_desc
*orig
;
356 struct ring_desc_ex
*ex
;
359 #define FLAG_MASK_V1 0xffff0000
360 #define FLAG_MASK_V2 0xffffc000
361 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
362 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
364 #define NV_TX_LASTPACKET (1<<16)
365 #define NV_TX_RETRYERROR (1<<19)
366 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
367 #define NV_TX_FORCED_INTERRUPT (1<<24)
368 #define NV_TX_DEFERRED (1<<26)
369 #define NV_TX_CARRIERLOST (1<<27)
370 #define NV_TX_LATECOLLISION (1<<28)
371 #define NV_TX_UNDERFLOW (1<<29)
372 #define NV_TX_ERROR (1<<30)
373 #define NV_TX_VALID (1<<31)
375 #define NV_TX2_LASTPACKET (1<<29)
376 #define NV_TX2_RETRYERROR (1<<18)
377 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
378 #define NV_TX2_FORCED_INTERRUPT (1<<30)
379 #define NV_TX2_DEFERRED (1<<25)
380 #define NV_TX2_CARRIERLOST (1<<26)
381 #define NV_TX2_LATECOLLISION (1<<27)
382 #define NV_TX2_UNDERFLOW (1<<28)
383 /* error and valid are the same for both */
384 #define NV_TX2_ERROR (1<<30)
385 #define NV_TX2_VALID (1<<31)
386 #define NV_TX2_TSO (1<<28)
387 #define NV_TX2_TSO_SHIFT 14
388 #define NV_TX2_TSO_MAX_SHIFT 14
389 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
390 #define NV_TX2_CHECKSUM_L3 (1<<27)
391 #define NV_TX2_CHECKSUM_L4 (1<<26)
393 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
395 #define NV_RX_DESCRIPTORVALID (1<<16)
396 #define NV_RX_MISSEDFRAME (1<<17)
397 #define NV_RX_SUBTRACT1 (1<<18)
398 #define NV_RX_ERROR1 (1<<23)
399 #define NV_RX_ERROR2 (1<<24)
400 #define NV_RX_ERROR3 (1<<25)
401 #define NV_RX_ERROR4 (1<<26)
402 #define NV_RX_CRCERR (1<<27)
403 #define NV_RX_OVERFLOW (1<<28)
404 #define NV_RX_FRAMINGERR (1<<29)
405 #define NV_RX_ERROR (1<<30)
406 #define NV_RX_AVAIL (1<<31)
407 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
409 #define NV_RX2_CHECKSUMMASK (0x1C000000)
410 #define NV_RX2_CHECKSUM_IP (0x10000000)
411 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
412 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
413 #define NV_RX2_DESCRIPTORVALID (1<<29)
414 #define NV_RX2_SUBTRACT1 (1<<25)
415 #define NV_RX2_ERROR1 (1<<18)
416 #define NV_RX2_ERROR2 (1<<19)
417 #define NV_RX2_ERROR3 (1<<20)
418 #define NV_RX2_ERROR4 (1<<21)
419 #define NV_RX2_CRCERR (1<<22)
420 #define NV_RX2_OVERFLOW (1<<23)
421 #define NV_RX2_FRAMINGERR (1<<24)
422 /* error and avail are the same for both */
423 #define NV_RX2_ERROR (1<<30)
424 #define NV_RX2_AVAIL (1<<31)
425 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
427 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
428 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
430 /* Miscellaneous hardware related defines: */
431 #define NV_PCI_REGSZ_VER1 0x270
432 #define NV_PCI_REGSZ_VER2 0x2d4
433 #define NV_PCI_REGSZ_VER3 0x604
434 #define NV_PCI_REGSZ_MAX 0x604
436 /* various timeout delays: all in usec */
437 #define NV_TXRX_RESET_DELAY 4
438 #define NV_TXSTOP_DELAY1 10
439 #define NV_TXSTOP_DELAY1MAX 500000
440 #define NV_TXSTOP_DELAY2 100
441 #define NV_RXSTOP_DELAY1 10
442 #define NV_RXSTOP_DELAY1MAX 500000
443 #define NV_RXSTOP_DELAY2 100
444 #define NV_SETUP5_DELAY 5
445 #define NV_SETUP5_DELAYMAX 50000
446 #define NV_POWERUP_DELAY 5
447 #define NV_POWERUP_DELAYMAX 5000
448 #define NV_MIIBUSY_DELAY 50
449 #define NV_MIIPHY_DELAY 10
450 #define NV_MIIPHY_DELAYMAX 10000
451 #define NV_MAC_RESET_DELAY 64
453 #define NV_WAKEUPPATTERNS 5
454 #define NV_WAKEUPMASKENTRIES 4
456 /* General driver defaults */
457 #define NV_WATCHDOG_TIMEO (5*HZ)
459 #define RX_RING_DEFAULT 512
460 #define TX_RING_DEFAULT 256
461 #define RX_RING_MIN 128
462 #define TX_RING_MIN 64
463 #define RING_MAX_DESC_VER_1 1024
464 #define RING_MAX_DESC_VER_2_3 16384
466 /* rx/tx mac addr + type + vlan + align + slack*/
467 #define NV_RX_HEADERS (64)
468 /* even more slack. */
469 #define NV_RX_ALLOC_PAD (64)
471 /* maximum mtu size */
472 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
473 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
475 #define OOM_REFILL (1+HZ/20)
476 #define POLL_WAIT (1+HZ/100)
477 #define LINK_TIMEOUT (3*HZ)
478 #define STATS_INTERVAL (10*HZ)
482 * The nic supports three different descriptor types:
483 * - DESC_VER_1: Original
484 * - DESC_VER_2: support for jumbo frames.
485 * - DESC_VER_3: 64-bit format.
492 #define PHY_OUI_MARVELL 0x5043
493 #define PHY_OUI_CICADA 0x03f1
494 #define PHY_OUI_VITESSE 0x01c1
495 #define PHY_OUI_REALTEK 0x0732
496 #define PHY_OUI_REALTEK2 0x0020
497 #define PHYID1_OUI_MASK 0x03ff
498 #define PHYID1_OUI_SHFT 6
499 #define PHYID2_OUI_MASK 0xfc00
500 #define PHYID2_OUI_SHFT 10
501 #define PHYID2_MODEL_MASK 0x03f0
502 #define PHY_MODEL_REALTEK_8211 0x0110
503 #define PHY_REV_MASK 0x0001
504 #define PHY_REV_REALTEK_8211B 0x0000
505 #define PHY_REV_REALTEK_8211C 0x0001
506 #define PHY_MODEL_REALTEK_8201 0x0200
507 #define PHY_MODEL_MARVELL_E3016 0x0220
508 #define PHY_MARVELL_E3016_INITMASK 0x0300
509 #define PHY_CICADA_INIT1 0x0f000
510 #define PHY_CICADA_INIT2 0x0e00
511 #define PHY_CICADA_INIT3 0x01000
512 #define PHY_CICADA_INIT4 0x0200
513 #define PHY_CICADA_INIT5 0x0004
514 #define PHY_CICADA_INIT6 0x02000
515 #define PHY_VITESSE_INIT_REG1 0x1f
516 #define PHY_VITESSE_INIT_REG2 0x10
517 #define PHY_VITESSE_INIT_REG3 0x11
518 #define PHY_VITESSE_INIT_REG4 0x12
519 #define PHY_VITESSE_INIT_MSK1 0xc
520 #define PHY_VITESSE_INIT_MSK2 0x0180
521 #define PHY_VITESSE_INIT1 0x52b5
522 #define PHY_VITESSE_INIT2 0xaf8a
523 #define PHY_VITESSE_INIT3 0x8
524 #define PHY_VITESSE_INIT4 0x8f8a
525 #define PHY_VITESSE_INIT5 0xaf86
526 #define PHY_VITESSE_INIT6 0x8f86
527 #define PHY_VITESSE_INIT7 0xaf82
528 #define PHY_VITESSE_INIT8 0x0100
529 #define PHY_VITESSE_INIT9 0x8f82
530 #define PHY_VITESSE_INIT10 0x0
531 #define PHY_REALTEK_INIT_REG1 0x1f
532 #define PHY_REALTEK_INIT_REG2 0x19
533 #define PHY_REALTEK_INIT_REG3 0x13
534 #define PHY_REALTEK_INIT_REG4 0x14
535 #define PHY_REALTEK_INIT_REG5 0x18
536 #define PHY_REALTEK_INIT_REG6 0x11
537 #define PHY_REALTEK_INIT_REG7 0x01
538 #define PHY_REALTEK_INIT1 0x0000
539 #define PHY_REALTEK_INIT2 0x8e00
540 #define PHY_REALTEK_INIT3 0x0001
541 #define PHY_REALTEK_INIT4 0xad17
542 #define PHY_REALTEK_INIT5 0xfb54
543 #define PHY_REALTEK_INIT6 0xf5c7
544 #define PHY_REALTEK_INIT7 0x1000
545 #define PHY_REALTEK_INIT8 0x0003
546 #define PHY_REALTEK_INIT9 0x0008
547 #define PHY_REALTEK_INIT10 0x0005
548 #define PHY_REALTEK_INIT11 0x0200
549 #define PHY_REALTEK_INIT_MSK1 0x0003
551 #define PHY_GIGABIT 0x0100
553 #define PHY_TIMEOUT 0x1
554 #define PHY_ERROR 0x2
558 #define PHY_HALF 0x100
560 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
561 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
562 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
563 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
564 #define NV_PAUSEFRAME_RX_REQ 0x0010
565 #define NV_PAUSEFRAME_TX_REQ 0x0020
566 #define NV_PAUSEFRAME_AUTONEG 0x0040
568 /* MSI/MSI-X defines */
569 #define NV_MSI_X_MAX_VECTORS 8
570 #define NV_MSI_X_VECTORS_MASK 0x000f
571 #define NV_MSI_CAPABLE 0x0010
572 #define NV_MSI_X_CAPABLE 0x0020
573 #define NV_MSI_ENABLED 0x0040
574 #define NV_MSI_X_ENABLED 0x0080
576 #define NV_MSI_X_VECTOR_ALL 0x0
577 #define NV_MSI_X_VECTOR_RX 0x0
578 #define NV_MSI_X_VECTOR_TX 0x1
579 #define NV_MSI_X_VECTOR_OTHER 0x2
581 #define NV_MSI_PRIV_OFFSET 0x68
582 #define NV_MSI_PRIV_VALUE 0xffffffff
584 #define NV_RESTART_TX 0x1
585 #define NV_RESTART_RX 0x2
587 #define NV_TX_LIMIT_COUNT 16
589 #define NV_DYNAMIC_THRESHOLD 4
590 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
593 struct nv_ethtool_str
{
594 char name
[ETH_GSTRING_LEN
];
597 static const struct nv_ethtool_str nv_estats_str
[] = {
598 { "tx_bytes" }, /* includes Ethernet FCS CRC */
602 { "tx_late_collision" },
603 { "tx_fifo_errors" },
604 { "tx_carrier_errors" },
605 { "tx_excess_deferral" },
606 { "tx_retry_error" },
607 { "rx_frame_error" },
609 { "rx_late_collision" },
611 { "rx_frame_too_long" },
612 { "rx_over_errors" },
614 { "rx_frame_align_error" },
615 { "rx_length_error" },
620 { "rx_errors_total" },
621 { "tx_errors_total" },
623 /* version 2 stats */
626 { "rx_bytes" }, /* includes Ethernet FCS CRC */
631 /* version 3 stats */
637 struct nv_ethtool_stats
{
638 u64 tx_bytes
; /* should be ifconfig->tx_bytes + 4*tx_packets */
642 u64 tx_late_collision
;
644 u64 tx_carrier_errors
;
645 u64 tx_excess_deferral
;
649 u64 rx_late_collision
;
651 u64 rx_frame_too_long
;
654 u64 rx_frame_align_error
;
659 u64 rx_packets
; /* should be ifconfig->rx_packets */
663 /* version 2 stats */
665 u64 tx_packets
; /* should be ifconfig->tx_packets */
666 u64 rx_bytes
; /* should be ifconfig->rx_bytes + 4*rx_packets */
671 /* version 3 stats */
677 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
678 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
679 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
682 #define NV_TEST_COUNT_BASE 3
683 #define NV_TEST_COUNT_EXTENDED 4
685 static const struct nv_ethtool_str nv_etests_str
[] = {
686 { "link (online/offline)" },
687 { "register (offline) " },
688 { "interrupt (offline) " },
689 { "loopback (offline) " }
692 struct register_test
{
697 static const struct register_test nv_registers_test
[] = {
698 { NvRegUnknownSetupReg6
, 0x01 },
699 { NvRegMisc1
, 0x03c },
700 { NvRegOffloadConfig
, 0x03ff },
701 { NvRegMulticastAddrA
, 0xffffffff },
702 { NvRegTxWatermark
, 0x0ff },
703 { NvRegWakeUpFlags
, 0x07777 },
710 unsigned int dma_len
:31;
711 unsigned int dma_single
:1;
712 struct ring_desc_ex
*first_tx_desc
;
713 struct nv_skb_map
*next_tx_ctx
;
716 struct nv_txrx_stats
{
718 u64 stat_rx_bytes
; /* not always available in HW */
719 u64 stat_rx_missed_errors
;
721 u64 stat_tx_packets
; /* not always available in HW */
726 #define nv_txrx_stats_inc(member) \
727 __this_cpu_inc(np->txrx_stats->member)
728 #define nv_txrx_stats_add(member, count) \
729 __this_cpu_add(np->txrx_stats->member, (count))
733 * All hardware access under netdev_priv(dev)->lock, except the performance
735 * - rx is (pseudo-) lockless: it relies on the single-threading provided
736 * by the arch code for interrupts.
737 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
738 * needs netdev_priv(dev)->lock :-(
739 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
741 * Hardware stats updates are protected by hwstats_lock:
742 * - updated by nv_do_stats_poll (timer). This is meant to avoid
743 * integer wraparound in the NIC stats registers, at low frequency
745 * - updated by nv_get_ethtool_stats + nv_get_stats64
747 * Software stats are accessed only through 64b synchronization points
748 * and are not subject to other synchronization techniques (single
749 * update thread on the TX or RX paths).
752 /* in dev: base, irq */
756 struct net_device
*dev
;
757 struct napi_struct napi
;
759 /* hardware stats are updated in syscall and timer */
760 spinlock_t hwstats_lock
;
761 struct nv_ethtool_stats estats
;
770 unsigned int phy_oui
;
771 unsigned int phy_model
;
772 unsigned int phy_rev
;
778 /* General data: RO fields */
779 dma_addr_t ring_addr
;
780 struct pci_dev
*pci_dev
;
796 /* rx specific fields.
797 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
799 union ring_type get_rx
, put_rx
, last_rx
;
800 struct nv_skb_map
*get_rx_ctx
, *put_rx_ctx
;
801 struct nv_skb_map
*last_rx_ctx
;
802 struct nv_skb_map
*rx_skb
;
804 union ring_type rx_ring
;
805 unsigned int rx_buf_sz
;
806 unsigned int pkt_limit
;
807 struct timer_list oom_kick
;
808 struct timer_list nic_poll
;
809 struct timer_list stats_poll
;
813 /* RX software stats */
814 struct u64_stats_sync swstats_rx_syncp
;
815 struct nv_txrx_stats __percpu
*txrx_stats
;
817 /* media detection workaround.
818 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
821 unsigned long link_timeout
;
823 * tx specific fields.
825 union ring_type get_tx
, put_tx
, last_tx
;
826 struct nv_skb_map
*get_tx_ctx
, *put_tx_ctx
;
827 struct nv_skb_map
*last_tx_ctx
;
828 struct nv_skb_map
*tx_skb
;
830 union ring_type tx_ring
;
834 u32 tx_pkts_in_progress
;
835 struct nv_skb_map
*tx_change_owner
;
836 struct nv_skb_map
*tx_end_flip
;
839 /* TX software stats */
840 struct u64_stats_sync swstats_tx_syncp
;
842 /* msi/msi-x fields */
844 struct msix_entry msi_x_entry
[NV_MSI_X_MAX_VECTORS
];
849 /* power saved state */
850 u32 saved_config_space
[NV_PCI_REGSZ_MAX
/4];
852 /* for different msi-x irq type */
853 char name_rx
[IFNAMSIZ
+ 3]; /* -rx */
854 char name_tx
[IFNAMSIZ
+ 3]; /* -tx */
855 char name_other
[IFNAMSIZ
+ 6]; /* -other */
859 * Maximum number of loops until we assume that a bit in the irq mask
860 * is stuck. Overridable with module param.
862 static int max_interrupt_work
= 4;
865 * Optimization can be either throuput mode or cpu mode
867 * Throughput Mode: Every tx and rx packet will generate an interrupt.
868 * CPU Mode: Interrupts are controlled by a timer.
871 NV_OPTIMIZATION_MODE_THROUGHPUT
,
872 NV_OPTIMIZATION_MODE_CPU
,
873 NV_OPTIMIZATION_MODE_DYNAMIC
875 static int optimization_mode
= NV_OPTIMIZATION_MODE_DYNAMIC
;
878 * Poll interval for timer irq
880 * This interval determines how frequent an interrupt is generated.
881 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
882 * Min = 0, and Max = 65535
884 static int poll_interval
= -1;
893 static int msi
= NV_MSI_INT_ENABLED
;
899 NV_MSIX_INT_DISABLED
,
902 static int msix
= NV_MSIX_INT_ENABLED
;
908 NV_DMA_64BIT_DISABLED
,
911 static int dma_64bit
= NV_DMA_64BIT_ENABLED
;
914 * Debug output control for tx_timeout
916 static bool debug_tx_timeout
= false;
919 * Crossover Detection
920 * Realtek 8201 phy + some OEM boards do not work properly.
923 NV_CROSSOVER_DETECTION_DISABLED
,
924 NV_CROSSOVER_DETECTION_ENABLED
926 static int phy_cross
= NV_CROSSOVER_DETECTION_DISABLED
;
929 * Power down phy when interface is down (persists through reboot;
930 * older Linux and other OSes may not power it up again)
932 static int phy_power_down
;
934 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
936 return netdev_priv(dev
);
939 static inline u8 __iomem
*get_hwbase(struct net_device
*dev
)
941 return ((struct fe_priv
*)netdev_priv(dev
))->base
;
944 static inline void pci_push(u8 __iomem
*base
)
946 /* force out pending posted writes */
950 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
952 return le32_to_cpu(prd
->flaglen
)
953 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
956 static inline u32
nv_descr_getlength_ex(struct ring_desc_ex
*prd
, u32 v
)
958 return le32_to_cpu(prd
->flaglen
) & LEN_MASK_V2
;
961 static bool nv_optimized(struct fe_priv
*np
)
963 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
968 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
969 int delay
, int delaymax
)
971 u8 __iomem
*base
= get_hwbase(dev
);
979 } while ((readl(base
+ offset
) & mask
) != target
);
983 #define NV_SETUP_RX_RING 0x01
984 #define NV_SETUP_TX_RING 0x02
986 static inline u32
dma_low(dma_addr_t addr
)
991 static inline u32
dma_high(dma_addr_t addr
)
993 return addr
>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
996 static void setup_hw_rings(struct net_device
*dev
, int rxtx_flags
)
998 struct fe_priv
*np
= get_nvpriv(dev
);
999 u8 __iomem
*base
= get_hwbase(dev
);
1001 if (!nv_optimized(np
)) {
1002 if (rxtx_flags
& NV_SETUP_RX_RING
)
1003 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
1004 if (rxtx_flags
& NV_SETUP_TX_RING
)
1005 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
1007 if (rxtx_flags
& NV_SETUP_RX_RING
) {
1008 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
1009 writel(dma_high(np
->ring_addr
), base
+ NvRegRxRingPhysAddrHigh
);
1011 if (rxtx_flags
& NV_SETUP_TX_RING
) {
1012 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
1013 writel(dma_high(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddrHigh
);
1018 static void free_rings(struct net_device
*dev
)
1020 struct fe_priv
*np
= get_nvpriv(dev
);
1022 if (!nv_optimized(np
)) {
1023 if (np
->rx_ring
.orig
)
1024 dma_free_coherent(&np
->pci_dev
->dev
,
1025 sizeof(struct ring_desc
) *
1028 np
->rx_ring
.orig
, np
->ring_addr
);
1031 dma_free_coherent(&np
->pci_dev
->dev
,
1032 sizeof(struct ring_desc_ex
) *
1035 np
->rx_ring
.ex
, np
->ring_addr
);
1041 static int using_multi_irqs(struct net_device
*dev
)
1043 struct fe_priv
*np
= get_nvpriv(dev
);
1045 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
1046 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
1047 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1)))
1053 static void nv_txrx_gate(struct net_device
*dev
, bool gate
)
1055 struct fe_priv
*np
= get_nvpriv(dev
);
1056 u8 __iomem
*base
= get_hwbase(dev
);
1059 if (!np
->mac_in_use
&&
1060 (np
->driver_data
& DEV_HAS_POWER_CNTRL
)) {
1061 powerstate
= readl(base
+ NvRegPowerState2
);
1063 powerstate
|= NVREG_POWERSTATE2_GATE_CLOCKS
;
1065 powerstate
&= ~NVREG_POWERSTATE2_GATE_CLOCKS
;
1066 writel(powerstate
, base
+ NvRegPowerState2
);
1070 static void nv_enable_irq(struct net_device
*dev
)
1072 struct fe_priv
*np
= get_nvpriv(dev
);
1074 if (!using_multi_irqs(dev
)) {
1075 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1076 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1078 enable_irq(np
->pci_dev
->irq
);
1080 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1081 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1082 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1086 static void nv_disable_irq(struct net_device
*dev
)
1088 struct fe_priv
*np
= get_nvpriv(dev
);
1090 if (!using_multi_irqs(dev
)) {
1091 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1092 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1094 disable_irq(np
->pci_dev
->irq
);
1096 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1097 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1098 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1102 /* In MSIX mode, a write to irqmask behaves as XOR */
1103 static void nv_enable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1105 u8 __iomem
*base
= get_hwbase(dev
);
1107 writel(mask
, base
+ NvRegIrqMask
);
1110 static void nv_disable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1112 struct fe_priv
*np
= get_nvpriv(dev
);
1113 u8 __iomem
*base
= get_hwbase(dev
);
1115 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
1116 writel(mask
, base
+ NvRegIrqMask
);
1118 if (np
->msi_flags
& NV_MSI_ENABLED
)
1119 writel(0, base
+ NvRegMSIIrqMask
);
1120 writel(0, base
+ NvRegIrqMask
);
1124 static void nv_napi_enable(struct net_device
*dev
)
1126 struct fe_priv
*np
= get_nvpriv(dev
);
1128 napi_enable(&np
->napi
);
1131 static void nv_napi_disable(struct net_device
*dev
)
1133 struct fe_priv
*np
= get_nvpriv(dev
);
1135 napi_disable(&np
->napi
);
1138 #define MII_READ (-1)
1139 /* mii_rw: read/write a register on the PHY.
1141 * Caller must guarantee serialization
1143 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
1145 u8 __iomem
*base
= get_hwbase(dev
);
1149 writel(NVREG_MIISTAT_MASK_RW
, base
+ NvRegMIIStatus
);
1151 reg
= readl(base
+ NvRegMIIControl
);
1152 if (reg
& NVREG_MIICTL_INUSE
) {
1153 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
1154 udelay(NV_MIIBUSY_DELAY
);
1157 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
1158 if (value
!= MII_READ
) {
1159 writel(value
, base
+ NvRegMIIData
);
1160 reg
|= NVREG_MIICTL_WRITE
;
1162 writel(reg
, base
+ NvRegMIIControl
);
1164 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
1165 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
)) {
1167 } else if (value
!= MII_READ
) {
1168 /* it was a write operation - fewer failures are detectable */
1170 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
1173 retval
= readl(base
+ NvRegMIIData
);
1179 static int phy_reset(struct net_device
*dev
, u32 bmcr_setup
)
1181 struct fe_priv
*np
= netdev_priv(dev
);
1183 unsigned int tries
= 0;
1185 miicontrol
= BMCR_RESET
| bmcr_setup
;
1186 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
))
1189 /* wait for 500ms */
1192 /* must wait till reset is deasserted */
1193 while (miicontrol
& BMCR_RESET
) {
1194 usleep_range(10000, 20000);
1195 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1196 /* FIXME: 100 tries seem excessive */
1203 static int init_realtek_8211b(struct net_device
*dev
, struct fe_priv
*np
)
1205 static const struct {
1209 { PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
},
1210 { PHY_REALTEK_INIT_REG2
, PHY_REALTEK_INIT2
},
1211 { PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
},
1212 { PHY_REALTEK_INIT_REG3
, PHY_REALTEK_INIT4
},
1213 { PHY_REALTEK_INIT_REG4
, PHY_REALTEK_INIT5
},
1214 { PHY_REALTEK_INIT_REG5
, PHY_REALTEK_INIT6
},
1215 { PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
},
1219 for (i
= 0; i
< ARRAY_SIZE(ri
); i
++) {
1220 if (mii_rw(dev
, np
->phyaddr
, ri
[i
].reg
, ri
[i
].init
))
1227 static int init_realtek_8211c(struct net_device
*dev
, struct fe_priv
*np
)
1230 u8 __iomem
*base
= get_hwbase(dev
);
1231 u32 powerstate
= readl(base
+ NvRegPowerState2
);
1233 /* need to perform hw phy reset */
1234 powerstate
|= NVREG_POWERSTATE2_PHY_RESET
;
1235 writel(powerstate
, base
+ NvRegPowerState2
);
1238 powerstate
&= ~NVREG_POWERSTATE2_PHY_RESET
;
1239 writel(powerstate
, base
+ NvRegPowerState2
);
1242 reg
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1243 reg
|= PHY_REALTEK_INIT9
;
1244 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, reg
))
1246 if (mii_rw(dev
, np
->phyaddr
,
1247 PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT10
))
1249 reg
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG7
, MII_READ
);
1250 if (!(reg
& PHY_REALTEK_INIT11
)) {
1251 reg
|= PHY_REALTEK_INIT11
;
1252 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG7
, reg
))
1255 if (mii_rw(dev
, np
->phyaddr
,
1256 PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
))
1262 static int init_realtek_8201(struct net_device
*dev
, struct fe_priv
*np
)
1266 if (np
->driver_data
& DEV_NEED_PHY_INIT_FIX
) {
1267 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1268 PHY_REALTEK_INIT_REG6
, MII_READ
);
1269 phy_reserved
|= PHY_REALTEK_INIT7
;
1270 if (mii_rw(dev
, np
->phyaddr
,
1271 PHY_REALTEK_INIT_REG6
, phy_reserved
))
1278 static int init_realtek_8201_cross(struct net_device
*dev
, struct fe_priv
*np
)
1282 if (phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
1283 if (mii_rw(dev
, np
->phyaddr
,
1284 PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
))
1286 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1287 PHY_REALTEK_INIT_REG2
, MII_READ
);
1288 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
1289 phy_reserved
|= PHY_REALTEK_INIT3
;
1290 if (mii_rw(dev
, np
->phyaddr
,
1291 PHY_REALTEK_INIT_REG2
, phy_reserved
))
1293 if (mii_rw(dev
, np
->phyaddr
,
1294 PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
))
1301 static int init_cicada(struct net_device
*dev
, struct fe_priv
*np
,
1306 if (phyinterface
& PHY_RGMII
) {
1307 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
1308 phy_reserved
&= ~(PHY_CICADA_INIT1
| PHY_CICADA_INIT2
);
1309 phy_reserved
|= (PHY_CICADA_INIT3
| PHY_CICADA_INIT4
);
1310 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
))
1312 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1313 phy_reserved
|= PHY_CICADA_INIT5
;
1314 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
))
1317 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
1318 phy_reserved
|= PHY_CICADA_INIT6
;
1319 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
))
1325 static int init_vitesse(struct net_device
*dev
, struct fe_priv
*np
)
1329 if (mii_rw(dev
, np
->phyaddr
,
1330 PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT1
))
1332 if (mii_rw(dev
, np
->phyaddr
,
1333 PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT2
))
1335 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1336 PHY_VITESSE_INIT_REG4
, MII_READ
);
1337 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
))
1339 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1340 PHY_VITESSE_INIT_REG3
, MII_READ
);
1341 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1342 phy_reserved
|= PHY_VITESSE_INIT3
;
1343 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
))
1345 if (mii_rw(dev
, np
->phyaddr
,
1346 PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT4
))
1348 if (mii_rw(dev
, np
->phyaddr
,
1349 PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT5
))
1351 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1352 PHY_VITESSE_INIT_REG4
, MII_READ
);
1353 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1354 phy_reserved
|= PHY_VITESSE_INIT3
;
1355 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
))
1357 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1358 PHY_VITESSE_INIT_REG3
, MII_READ
);
1359 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
))
1361 if (mii_rw(dev
, np
->phyaddr
,
1362 PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT6
))
1364 if (mii_rw(dev
, np
->phyaddr
,
1365 PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT7
))
1367 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1368 PHY_VITESSE_INIT_REG4
, MII_READ
);
1369 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
))
1371 phy_reserved
= mii_rw(dev
, np
->phyaddr
,
1372 PHY_VITESSE_INIT_REG3
, MII_READ
);
1373 phy_reserved
&= ~PHY_VITESSE_INIT_MSK2
;
1374 phy_reserved
|= PHY_VITESSE_INIT8
;
1375 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
))
1377 if (mii_rw(dev
, np
->phyaddr
,
1378 PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT9
))
1380 if (mii_rw(dev
, np
->phyaddr
,
1381 PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT10
))
1387 static int phy_init(struct net_device
*dev
)
1389 struct fe_priv
*np
= get_nvpriv(dev
);
1390 u8 __iomem
*base
= get_hwbase(dev
);
1392 u32 mii_status
, mii_control
, mii_control_1000
, reg
;
1394 /* phy errata for E3016 phy */
1395 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
1396 reg
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1397 reg
&= ~PHY_MARVELL_E3016_INITMASK
;
1398 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, reg
)) {
1399 netdev_info(dev
, "%s: phy write to errata reg failed\n",
1400 pci_name(np
->pci_dev
));
1404 if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1405 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1406 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1407 if (init_realtek_8211b(dev
, np
)) {
1408 netdev_info(dev
, "%s: phy init failed\n",
1409 pci_name(np
->pci_dev
));
1412 } else if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1413 np
->phy_rev
== PHY_REV_REALTEK_8211C
) {
1414 if (init_realtek_8211c(dev
, np
)) {
1415 netdev_info(dev
, "%s: phy init failed\n",
1416 pci_name(np
->pci_dev
));
1419 } else if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1420 if (init_realtek_8201(dev
, np
)) {
1421 netdev_info(dev
, "%s: phy init failed\n",
1422 pci_name(np
->pci_dev
));
1428 /* set advertise register */
1429 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1430 reg
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1431 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
1432 ADVERTISE_PAUSE_ASYM
| ADVERTISE_PAUSE_CAP
);
1433 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
1434 netdev_info(dev
, "%s: phy write to advertise failed\n",
1435 pci_name(np
->pci_dev
));
1439 /* get phy interface type */
1440 phyinterface
= readl(base
+ NvRegPhyInterface
);
1442 /* see if gigabit phy */
1443 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1444 if (mii_status
& PHY_GIGABIT
) {
1445 np
->gigabit
= PHY_GIGABIT
;
1446 mii_control_1000
= mii_rw(dev
, np
->phyaddr
,
1447 MII_CTRL1000
, MII_READ
);
1448 mii_control_1000
&= ~ADVERTISE_1000HALF
;
1449 if (phyinterface
& PHY_RGMII
)
1450 mii_control_1000
|= ADVERTISE_1000FULL
;
1452 mii_control_1000
&= ~ADVERTISE_1000FULL
;
1454 if (mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, mii_control_1000
)) {
1455 netdev_info(dev
, "%s: phy init failed\n",
1456 pci_name(np
->pci_dev
));
1462 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1463 mii_control
|= BMCR_ANENABLE
;
1465 if (np
->phy_oui
== PHY_OUI_REALTEK
&&
1466 np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1467 np
->phy_rev
== PHY_REV_REALTEK_8211C
) {
1468 /* start autoneg since we already performed hw reset above */
1469 mii_control
|= BMCR_ANRESTART
;
1470 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
1471 netdev_info(dev
, "%s: phy init failed\n",
1472 pci_name(np
->pci_dev
));
1477 * (certain phys need bmcr to be setup with reset)
1479 if (phy_reset(dev
, mii_control
)) {
1480 netdev_info(dev
, "%s: phy reset failed\n",
1481 pci_name(np
->pci_dev
));
1486 /* phy vendor specific configuration */
1487 if (np
->phy_oui
== PHY_OUI_CICADA
) {
1488 if (init_cicada(dev
, np
, phyinterface
)) {
1489 netdev_info(dev
, "%s: phy init failed\n",
1490 pci_name(np
->pci_dev
));
1493 } else if (np
->phy_oui
== PHY_OUI_VITESSE
) {
1494 if (init_vitesse(dev
, np
)) {
1495 netdev_info(dev
, "%s: phy init failed\n",
1496 pci_name(np
->pci_dev
));
1499 } else if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1500 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1501 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1502 /* reset could have cleared these out, set them back */
1503 if (init_realtek_8211b(dev
, np
)) {
1504 netdev_info(dev
, "%s: phy init failed\n",
1505 pci_name(np
->pci_dev
));
1508 } else if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1509 if (init_realtek_8201(dev
, np
) ||
1510 init_realtek_8201_cross(dev
, np
)) {
1511 netdev_info(dev
, "%s: phy init failed\n",
1512 pci_name(np
->pci_dev
));
1518 /* some phys clear out pause advertisement on reset, set it back */
1519 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
);
1521 /* restart auto negotiation, power down phy */
1522 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1523 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
1525 mii_control
|= BMCR_PDOWN
;
1526 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
))
1532 static void nv_start_rx(struct net_device
*dev
)
1534 struct fe_priv
*np
= netdev_priv(dev
);
1535 u8 __iomem
*base
= get_hwbase(dev
);
1536 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1538 /* Already running? Stop it. */
1539 if ((readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) && !np
->mac_in_use
) {
1540 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1541 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1544 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1546 rx_ctrl
|= NVREG_RCVCTL_START
;
1548 rx_ctrl
&= ~NVREG_RCVCTL_RX_PATH_EN
;
1549 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1553 static void nv_stop_rx(struct net_device
*dev
)
1555 struct fe_priv
*np
= netdev_priv(dev
);
1556 u8 __iomem
*base
= get_hwbase(dev
);
1557 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1559 if (!np
->mac_in_use
)
1560 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1562 rx_ctrl
|= NVREG_RCVCTL_RX_PATH_EN
;
1563 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1564 if (reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
1565 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
))
1566 netdev_info(dev
, "%s: ReceiverStatus remained busy\n",
1569 udelay(NV_RXSTOP_DELAY2
);
1570 if (!np
->mac_in_use
)
1571 writel(0, base
+ NvRegLinkSpeed
);
1574 static void nv_start_tx(struct net_device
*dev
)
1576 struct fe_priv
*np
= netdev_priv(dev
);
1577 u8 __iomem
*base
= get_hwbase(dev
);
1578 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1580 tx_ctrl
|= NVREG_XMITCTL_START
;
1582 tx_ctrl
&= ~NVREG_XMITCTL_TX_PATH_EN
;
1583 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1587 static void nv_stop_tx(struct net_device
*dev
)
1589 struct fe_priv
*np
= netdev_priv(dev
);
1590 u8 __iomem
*base
= get_hwbase(dev
);
1591 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1593 if (!np
->mac_in_use
)
1594 tx_ctrl
&= ~NVREG_XMITCTL_START
;
1596 tx_ctrl
|= NVREG_XMITCTL_TX_PATH_EN
;
1597 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1598 if (reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
1599 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
))
1600 netdev_info(dev
, "%s: TransmitterStatus remained busy\n",
1603 udelay(NV_TXSTOP_DELAY2
);
1604 if (!np
->mac_in_use
)
1605 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
1606 base
+ NvRegTransmitPoll
);
1609 static void nv_start_rxtx(struct net_device
*dev
)
1615 static void nv_stop_rxtx(struct net_device
*dev
)
1621 static void nv_txrx_reset(struct net_device
*dev
)
1623 struct fe_priv
*np
= netdev_priv(dev
);
1624 u8 __iomem
*base
= get_hwbase(dev
);
1626 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1628 udelay(NV_TXRX_RESET_DELAY
);
1629 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1633 static void nv_mac_reset(struct net_device
*dev
)
1635 struct fe_priv
*np
= netdev_priv(dev
);
1636 u8 __iomem
*base
= get_hwbase(dev
);
1637 u32 temp1
, temp2
, temp3
;
1639 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1642 /* save registers since they will be cleared on reset */
1643 temp1
= readl(base
+ NvRegMacAddrA
);
1644 temp2
= readl(base
+ NvRegMacAddrB
);
1645 temp3
= readl(base
+ NvRegTransmitPoll
);
1647 writel(NVREG_MAC_RESET_ASSERT
, base
+ NvRegMacReset
);
1649 udelay(NV_MAC_RESET_DELAY
);
1650 writel(0, base
+ NvRegMacReset
);
1652 udelay(NV_MAC_RESET_DELAY
);
1654 /* restore saved registers */
1655 writel(temp1
, base
+ NvRegMacAddrA
);
1656 writel(temp2
, base
+ NvRegMacAddrB
);
1657 writel(temp3
, base
+ NvRegTransmitPoll
);
1659 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1663 /* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1664 static void nv_update_stats(struct net_device
*dev
)
1666 struct fe_priv
*np
= netdev_priv(dev
);
1667 u8 __iomem
*base
= get_hwbase(dev
);
1669 /* If it happens that this is run in top-half context, then
1670 * replace the spin_lock of hwstats_lock with
1671 * spin_lock_irqsave() in calling functions. */
1672 WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half");
1673 assert_spin_locked(&np
->hwstats_lock
);
1675 /* query hardware */
1676 np
->estats
.tx_bytes
+= readl(base
+ NvRegTxCnt
);
1677 np
->estats
.tx_zero_rexmt
+= readl(base
+ NvRegTxZeroReXmt
);
1678 np
->estats
.tx_one_rexmt
+= readl(base
+ NvRegTxOneReXmt
);
1679 np
->estats
.tx_many_rexmt
+= readl(base
+ NvRegTxManyReXmt
);
1680 np
->estats
.tx_late_collision
+= readl(base
+ NvRegTxLateCol
);
1681 np
->estats
.tx_fifo_errors
+= readl(base
+ NvRegTxUnderflow
);
1682 np
->estats
.tx_carrier_errors
+= readl(base
+ NvRegTxLossCarrier
);
1683 np
->estats
.tx_excess_deferral
+= readl(base
+ NvRegTxExcessDef
);
1684 np
->estats
.tx_retry_error
+= readl(base
+ NvRegTxRetryErr
);
1685 np
->estats
.rx_frame_error
+= readl(base
+ NvRegRxFrameErr
);
1686 np
->estats
.rx_extra_byte
+= readl(base
+ NvRegRxExtraByte
);
1687 np
->estats
.rx_late_collision
+= readl(base
+ NvRegRxLateCol
);
1688 np
->estats
.rx_runt
+= readl(base
+ NvRegRxRunt
);
1689 np
->estats
.rx_frame_too_long
+= readl(base
+ NvRegRxFrameTooLong
);
1690 np
->estats
.rx_over_errors
+= readl(base
+ NvRegRxOverflow
);
1691 np
->estats
.rx_crc_errors
+= readl(base
+ NvRegRxFCSErr
);
1692 np
->estats
.rx_frame_align_error
+= readl(base
+ NvRegRxFrameAlignErr
);
1693 np
->estats
.rx_length_error
+= readl(base
+ NvRegRxLenErr
);
1694 np
->estats
.rx_unicast
+= readl(base
+ NvRegRxUnicast
);
1695 np
->estats
.rx_multicast
+= readl(base
+ NvRegRxMulticast
);
1696 np
->estats
.rx_broadcast
+= readl(base
+ NvRegRxBroadcast
);
1697 np
->estats
.rx_packets
=
1698 np
->estats
.rx_unicast
+
1699 np
->estats
.rx_multicast
+
1700 np
->estats
.rx_broadcast
;
1701 np
->estats
.rx_errors_total
=
1702 np
->estats
.rx_crc_errors
+
1703 np
->estats
.rx_over_errors
+
1704 np
->estats
.rx_frame_error
+
1705 (np
->estats
.rx_frame_align_error
- np
->estats
.rx_extra_byte
) +
1706 np
->estats
.rx_late_collision
+
1707 np
->estats
.rx_runt
+
1708 np
->estats
.rx_frame_too_long
;
1709 np
->estats
.tx_errors_total
=
1710 np
->estats
.tx_late_collision
+
1711 np
->estats
.tx_fifo_errors
+
1712 np
->estats
.tx_carrier_errors
+
1713 np
->estats
.tx_excess_deferral
+
1714 np
->estats
.tx_retry_error
;
1716 if (np
->driver_data
& DEV_HAS_STATISTICS_V2
) {
1717 np
->estats
.tx_deferral
+= readl(base
+ NvRegTxDef
);
1718 np
->estats
.tx_packets
+= readl(base
+ NvRegTxFrame
);
1719 np
->estats
.rx_bytes
+= readl(base
+ NvRegRxCnt
);
1720 np
->estats
.tx_pause
+= readl(base
+ NvRegTxPause
);
1721 np
->estats
.rx_pause
+= readl(base
+ NvRegRxPause
);
1722 np
->estats
.rx_drop_frame
+= readl(base
+ NvRegRxDropFrame
);
1723 np
->estats
.rx_errors_total
+= np
->estats
.rx_drop_frame
;
1726 if (np
->driver_data
& DEV_HAS_STATISTICS_V3
) {
1727 np
->estats
.tx_unicast
+= readl(base
+ NvRegTxUnicast
);
1728 np
->estats
.tx_multicast
+= readl(base
+ NvRegTxMulticast
);
1729 np
->estats
.tx_broadcast
+= readl(base
+ NvRegTxBroadcast
);
1733 static void nv_get_stats(int cpu
, struct fe_priv
*np
,
1734 struct rtnl_link_stats64
*storage
)
1736 struct nv_txrx_stats
*src
= per_cpu_ptr(np
->txrx_stats
, cpu
);
1737 unsigned int syncp_start
;
1738 u64 rx_packets
, rx_bytes
, rx_dropped
, rx_missed_errors
;
1739 u64 tx_packets
, tx_bytes
, tx_dropped
;
1742 syncp_start
= u64_stats_fetch_begin_irq(&np
->swstats_rx_syncp
);
1743 rx_packets
= src
->stat_rx_packets
;
1744 rx_bytes
= src
->stat_rx_bytes
;
1745 rx_dropped
= src
->stat_rx_dropped
;
1746 rx_missed_errors
= src
->stat_rx_missed_errors
;
1747 } while (u64_stats_fetch_retry_irq(&np
->swstats_rx_syncp
, syncp_start
));
1749 storage
->rx_packets
+= rx_packets
;
1750 storage
->rx_bytes
+= rx_bytes
;
1751 storage
->rx_dropped
+= rx_dropped
;
1752 storage
->rx_missed_errors
+= rx_missed_errors
;
1755 syncp_start
= u64_stats_fetch_begin_irq(&np
->swstats_tx_syncp
);
1756 tx_packets
= src
->stat_tx_packets
;
1757 tx_bytes
= src
->stat_tx_bytes
;
1758 tx_dropped
= src
->stat_tx_dropped
;
1759 } while (u64_stats_fetch_retry_irq(&np
->swstats_tx_syncp
, syncp_start
));
1761 storage
->tx_packets
+= tx_packets
;
1762 storage
->tx_bytes
+= tx_bytes
;
1763 storage
->tx_dropped
+= tx_dropped
;
1767 * nv_get_stats64: dev->ndo_get_stats64 function
1768 * Get latest stats value from the nic.
1769 * Called with read_lock(&dev_base_lock) held for read -
1770 * only synchronized against unregister_netdevice.
1773 nv_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*storage
)
1774 __acquires(&netdev_priv(dev
)->hwstats_lock
)
1775 __releases(&netdev_priv(dev
)->hwstats_lock
)
1777 struct fe_priv
*np
= netdev_priv(dev
);
1781 * Note: because HW stats are not always available and for
1782 * consistency reasons, the following ifconfig stats are
1783 * managed by software: rx_bytes, tx_bytes, rx_packets and
1784 * tx_packets. The related hardware stats reported by ethtool
1785 * should be equivalent to these ifconfig stats, with 4
1786 * additional bytes per packet (Ethernet FCS CRC), except for
1787 * tx_packets when TSO kicks in.
1790 /* software stats */
1791 for_each_online_cpu(cpu
)
1792 nv_get_stats(cpu
, np
, storage
);
1794 /* If the nic supports hw counters then retrieve latest values */
1795 if (np
->driver_data
& DEV_HAS_STATISTICS_V123
) {
1796 spin_lock_bh(&np
->hwstats_lock
);
1798 nv_update_stats(dev
);
1801 storage
->rx_errors
= np
->estats
.rx_errors_total
;
1802 storage
->tx_errors
= np
->estats
.tx_errors_total
;
1804 /* meaningful only when NIC supports stats v3 */
1805 storage
->multicast
= np
->estats
.rx_multicast
;
1807 /* detailed rx_errors */
1808 storage
->rx_length_errors
= np
->estats
.rx_length_error
;
1809 storage
->rx_over_errors
= np
->estats
.rx_over_errors
;
1810 storage
->rx_crc_errors
= np
->estats
.rx_crc_errors
;
1811 storage
->rx_frame_errors
= np
->estats
.rx_frame_align_error
;
1812 storage
->rx_fifo_errors
= np
->estats
.rx_drop_frame
;
1814 /* detailed tx_errors */
1815 storage
->tx_carrier_errors
= np
->estats
.tx_carrier_errors
;
1816 storage
->tx_fifo_errors
= np
->estats
.tx_fifo_errors
;
1818 spin_unlock_bh(&np
->hwstats_lock
);
1823 * nv_alloc_rx: fill rx ring entries.
1824 * Return 1 if the allocations for the skbs failed and the
1825 * rx engine is without Available descriptors
1827 static int nv_alloc_rx(struct net_device
*dev
)
1829 struct fe_priv
*np
= netdev_priv(dev
);
1830 struct ring_desc
*less_rx
;
1832 less_rx
= np
->get_rx
.orig
;
1833 if (less_rx
-- == np
->rx_ring
.orig
)
1834 less_rx
= np
->last_rx
.orig
;
1836 while (np
->put_rx
.orig
!= less_rx
) {
1837 struct sk_buff
*skb
= netdev_alloc_skb(dev
, np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1839 np
->put_rx_ctx
->skb
= skb
;
1840 np
->put_rx_ctx
->dma
= dma_map_single(&np
->pci_dev
->dev
,
1844 if (unlikely(dma_mapping_error(&np
->pci_dev
->dev
,
1845 np
->put_rx_ctx
->dma
))) {
1847 goto packet_dropped
;
1849 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1850 np
->put_rx
.orig
->buf
= cpu_to_le32(np
->put_rx_ctx
->dma
);
1852 np
->put_rx
.orig
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX_AVAIL
);
1853 if (unlikely(np
->put_rx
.orig
++ == np
->last_rx
.orig
))
1854 np
->put_rx
.orig
= np
->rx_ring
.orig
;
1855 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1856 np
->put_rx_ctx
= np
->rx_skb
;
1859 u64_stats_update_begin(&np
->swstats_rx_syncp
);
1860 nv_txrx_stats_inc(stat_rx_dropped
);
1861 u64_stats_update_end(&np
->swstats_rx_syncp
);
1868 static int nv_alloc_rx_optimized(struct net_device
*dev
)
1870 struct fe_priv
*np
= netdev_priv(dev
);
1871 struct ring_desc_ex
*less_rx
;
1873 less_rx
= np
->get_rx
.ex
;
1874 if (less_rx
-- == np
->rx_ring
.ex
)
1875 less_rx
= np
->last_rx
.ex
;
1877 while (np
->put_rx
.ex
!= less_rx
) {
1878 struct sk_buff
*skb
= netdev_alloc_skb(dev
, np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1880 np
->put_rx_ctx
->skb
= skb
;
1881 np
->put_rx_ctx
->dma
= dma_map_single(&np
->pci_dev
->dev
,
1885 if (unlikely(dma_mapping_error(&np
->pci_dev
->dev
,
1886 np
->put_rx_ctx
->dma
))) {
1888 goto packet_dropped
;
1890 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1891 np
->put_rx
.ex
->bufhigh
= cpu_to_le32(dma_high(np
->put_rx_ctx
->dma
));
1892 np
->put_rx
.ex
->buflow
= cpu_to_le32(dma_low(np
->put_rx_ctx
->dma
));
1894 np
->put_rx
.ex
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX2_AVAIL
);
1895 if (unlikely(np
->put_rx
.ex
++ == np
->last_rx
.ex
))
1896 np
->put_rx
.ex
= np
->rx_ring
.ex
;
1897 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1898 np
->put_rx_ctx
= np
->rx_skb
;
1901 u64_stats_update_begin(&np
->swstats_rx_syncp
);
1902 nv_txrx_stats_inc(stat_rx_dropped
);
1903 u64_stats_update_end(&np
->swstats_rx_syncp
);
1910 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1911 static void nv_do_rx_refill(struct timer_list
*t
)
1913 struct fe_priv
*np
= from_timer(np
, t
, oom_kick
);
1915 /* Just reschedule NAPI rx processing */
1916 napi_schedule(&np
->napi
);
1919 static void nv_init_rx(struct net_device
*dev
)
1921 struct fe_priv
*np
= netdev_priv(dev
);
1924 np
->get_rx
= np
->rx_ring
;
1925 np
->put_rx
= np
->rx_ring
;
1927 if (!nv_optimized(np
))
1928 np
->last_rx
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
-1];
1930 np
->last_rx
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
-1];
1931 np
->get_rx_ctx
= np
->rx_skb
;
1932 np
->put_rx_ctx
= np
->rx_skb
;
1933 np
->last_rx_ctx
= &np
->rx_skb
[np
->rx_ring_size
-1];
1935 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1936 if (!nv_optimized(np
)) {
1937 np
->rx_ring
.orig
[i
].flaglen
= 0;
1938 np
->rx_ring
.orig
[i
].buf
= 0;
1940 np
->rx_ring
.ex
[i
].flaglen
= 0;
1941 np
->rx_ring
.ex
[i
].txvlan
= 0;
1942 np
->rx_ring
.ex
[i
].bufhigh
= 0;
1943 np
->rx_ring
.ex
[i
].buflow
= 0;
1945 np
->rx_skb
[i
].skb
= NULL
;
1946 np
->rx_skb
[i
].dma
= 0;
1950 static void nv_init_tx(struct net_device
*dev
)
1952 struct fe_priv
*np
= netdev_priv(dev
);
1955 np
->get_tx
= np
->tx_ring
;
1956 np
->put_tx
= np
->tx_ring
;
1958 if (!nv_optimized(np
))
1959 np
->last_tx
.orig
= &np
->tx_ring
.orig
[np
->tx_ring_size
-1];
1961 np
->last_tx
.ex
= &np
->tx_ring
.ex
[np
->tx_ring_size
-1];
1962 np
->get_tx_ctx
= np
->tx_skb
;
1963 np
->put_tx_ctx
= np
->tx_skb
;
1964 np
->last_tx_ctx
= &np
->tx_skb
[np
->tx_ring_size
-1];
1965 netdev_reset_queue(np
->dev
);
1966 np
->tx_pkts_in_progress
= 0;
1967 np
->tx_change_owner
= NULL
;
1968 np
->tx_end_flip
= NULL
;
1971 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1972 if (!nv_optimized(np
)) {
1973 np
->tx_ring
.orig
[i
].flaglen
= 0;
1974 np
->tx_ring
.orig
[i
].buf
= 0;
1976 np
->tx_ring
.ex
[i
].flaglen
= 0;
1977 np
->tx_ring
.ex
[i
].txvlan
= 0;
1978 np
->tx_ring
.ex
[i
].bufhigh
= 0;
1979 np
->tx_ring
.ex
[i
].buflow
= 0;
1981 np
->tx_skb
[i
].skb
= NULL
;
1982 np
->tx_skb
[i
].dma
= 0;
1983 np
->tx_skb
[i
].dma_len
= 0;
1984 np
->tx_skb
[i
].dma_single
= 0;
1985 np
->tx_skb
[i
].first_tx_desc
= NULL
;
1986 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
1990 static int nv_init_ring(struct net_device
*dev
)
1992 struct fe_priv
*np
= netdev_priv(dev
);
1997 if (!nv_optimized(np
))
1998 return nv_alloc_rx(dev
);
2000 return nv_alloc_rx_optimized(dev
);
2003 static void nv_unmap_txskb(struct fe_priv
*np
, struct nv_skb_map
*tx_skb
)
2006 if (tx_skb
->dma_single
)
2007 dma_unmap_single(&np
->pci_dev
->dev
, tx_skb
->dma
,
2011 dma_unmap_page(&np
->pci_dev
->dev
, tx_skb
->dma
,
2018 static int nv_release_txskb(struct fe_priv
*np
, struct nv_skb_map
*tx_skb
)
2020 nv_unmap_txskb(np
, tx_skb
);
2022 dev_kfree_skb_any(tx_skb
->skb
);
2029 static void nv_drain_tx(struct net_device
*dev
)
2031 struct fe_priv
*np
= netdev_priv(dev
);
2034 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
2035 if (!nv_optimized(np
)) {
2036 np
->tx_ring
.orig
[i
].flaglen
= 0;
2037 np
->tx_ring
.orig
[i
].buf
= 0;
2039 np
->tx_ring
.ex
[i
].flaglen
= 0;
2040 np
->tx_ring
.ex
[i
].txvlan
= 0;
2041 np
->tx_ring
.ex
[i
].bufhigh
= 0;
2042 np
->tx_ring
.ex
[i
].buflow
= 0;
2044 if (nv_release_txskb(np
, &np
->tx_skb
[i
])) {
2045 u64_stats_update_begin(&np
->swstats_tx_syncp
);
2046 nv_txrx_stats_inc(stat_tx_dropped
);
2047 u64_stats_update_end(&np
->swstats_tx_syncp
);
2049 np
->tx_skb
[i
].dma
= 0;
2050 np
->tx_skb
[i
].dma_len
= 0;
2051 np
->tx_skb
[i
].dma_single
= 0;
2052 np
->tx_skb
[i
].first_tx_desc
= NULL
;
2053 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
2055 np
->tx_pkts_in_progress
= 0;
2056 np
->tx_change_owner
= NULL
;
2057 np
->tx_end_flip
= NULL
;
2060 static void nv_drain_rx(struct net_device
*dev
)
2062 struct fe_priv
*np
= netdev_priv(dev
);
2065 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
2066 if (!nv_optimized(np
)) {
2067 np
->rx_ring
.orig
[i
].flaglen
= 0;
2068 np
->rx_ring
.orig
[i
].buf
= 0;
2070 np
->rx_ring
.ex
[i
].flaglen
= 0;
2071 np
->rx_ring
.ex
[i
].txvlan
= 0;
2072 np
->rx_ring
.ex
[i
].bufhigh
= 0;
2073 np
->rx_ring
.ex
[i
].buflow
= 0;
2076 if (np
->rx_skb
[i
].skb
) {
2077 dma_unmap_single(&np
->pci_dev
->dev
, np
->rx_skb
[i
].dma
,
2078 (skb_end_pointer(np
->rx_skb
[i
].skb
) -
2079 np
->rx_skb
[i
].skb
->data
),
2081 dev_kfree_skb(np
->rx_skb
[i
].skb
);
2082 np
->rx_skb
[i
].skb
= NULL
;
2087 static void nv_drain_rxtx(struct net_device
*dev
)
2093 static inline u32
nv_get_empty_tx_slots(struct fe_priv
*np
)
2095 return (u32
)(np
->tx_ring_size
- ((np
->tx_ring_size
+ (np
->put_tx_ctx
- np
->get_tx_ctx
)) % np
->tx_ring_size
));
2098 static void nv_legacybackoff_reseed(struct net_device
*dev
)
2100 u8 __iomem
*base
= get_hwbase(dev
);
2105 reg
= readl(base
+ NvRegSlotTime
) & ~NVREG_SLOTTIME_MASK
;
2106 get_random_bytes(&low
, sizeof(low
));
2107 reg
|= low
& NVREG_SLOTTIME_MASK
;
2109 /* Need to stop tx before change takes effect.
2110 * Caller has already gained np->lock.
2112 tx_status
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
;
2116 writel(reg
, base
+ NvRegSlotTime
);
2122 /* Gear Backoff Seeds */
2123 #define BACKOFF_SEEDSET_ROWS 8
2124 #define BACKOFF_SEEDSET_LFSRS 15
2126 /* Known Good seed sets */
2127 static const u32 main_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
2128 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2129 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2130 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2131 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2132 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2133 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2134 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2135 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2137 static const u32 gear_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
2138 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2139 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2140 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2141 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2142 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2143 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2144 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2145 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2147 static void nv_gear_backoff_reseed(struct net_device
*dev
)
2149 u8 __iomem
*base
= get_hwbase(dev
);
2150 u32 miniseed1
, miniseed2
, miniseed2_reversed
, miniseed3
, miniseed3_reversed
;
2151 u32 temp
, seedset
, combinedSeed
;
2154 /* Setup seed for free running LFSR */
2155 /* We are going to read the time stamp counter 3 times
2156 and swizzle bits around to increase randomness */
2157 get_random_bytes(&miniseed1
, sizeof(miniseed1
));
2158 miniseed1
&= 0x0fff;
2162 get_random_bytes(&miniseed2
, sizeof(miniseed2
));
2163 miniseed2
&= 0x0fff;
2166 miniseed2_reversed
=
2167 ((miniseed2
& 0xF00) >> 8) |
2168 (miniseed2
& 0x0F0) |
2169 ((miniseed2
& 0x00F) << 8);
2171 get_random_bytes(&miniseed3
, sizeof(miniseed3
));
2172 miniseed3
&= 0x0fff;
2175 miniseed3_reversed
=
2176 ((miniseed3
& 0xF00) >> 8) |
2177 (miniseed3
& 0x0F0) |
2178 ((miniseed3
& 0x00F) << 8);
2180 combinedSeed
= ((miniseed1
^ miniseed2_reversed
) << 12) |
2181 (miniseed2
^ miniseed3_reversed
);
2183 /* Seeds can not be zero */
2184 if ((combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
) == 0)
2185 combinedSeed
|= 0x08;
2186 if ((combinedSeed
& (NVREG_BKOFFCTRL_SEED_MASK
<< NVREG_BKOFFCTRL_GEAR
)) == 0)
2187 combinedSeed
|= 0x8000;
2189 /* No need to disable tx here */
2190 temp
= NVREG_BKOFFCTRL_DEFAULT
| (0 << NVREG_BKOFFCTRL_SELECT
);
2191 temp
|= combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
;
2192 temp
|= combinedSeed
>> NVREG_BKOFFCTRL_GEAR
;
2193 writel(temp
, base
+ NvRegBackOffControl
);
2195 /* Setup seeds for all gear LFSRs. */
2196 get_random_bytes(&seedset
, sizeof(seedset
));
2197 seedset
= seedset
% BACKOFF_SEEDSET_ROWS
;
2198 for (i
= 1; i
<= BACKOFF_SEEDSET_LFSRS
; i
++) {
2199 temp
= NVREG_BKOFFCTRL_DEFAULT
| (i
<< NVREG_BKOFFCTRL_SELECT
);
2200 temp
|= main_seedset
[seedset
][i
-1] & 0x3ff;
2201 temp
|= ((gear_seedset
[seedset
][i
-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR
);
2202 writel(temp
, base
+ NvRegBackOffControl
);
2207 * nv_start_xmit: dev->hard_start_xmit function
2208 * Called with netif_tx_lock held.
2210 static netdev_tx_t
nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2212 struct fe_priv
*np
= netdev_priv(dev
);
2214 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
2215 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2219 u32 size
= skb_headlen(skb
);
2220 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2222 struct ring_desc
*put_tx
;
2223 struct ring_desc
*start_tx
;
2224 struct ring_desc
*prev_tx
;
2225 struct nv_skb_map
*prev_tx_ctx
;
2226 struct nv_skb_map
*tmp_tx_ctx
= NULL
, *start_tx_ctx
= NULL
;
2227 unsigned long flags
;
2229 /* add fragments to entries count */
2230 for (i
= 0; i
< fragments
; i
++) {
2231 u32 frag_size
= skb_frag_size(&skb_shinfo(skb
)->frags
[i
]);
2233 entries
+= (frag_size
>> NV_TX2_TSO_MAX_SHIFT
) +
2234 ((frag_size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2237 spin_lock_irqsave(&np
->lock
, flags
);
2238 empty_slots
= nv_get_empty_tx_slots(np
);
2239 if (unlikely(empty_slots
<= entries
)) {
2240 netif_stop_queue(dev
);
2242 spin_unlock_irqrestore(&np
->lock
, flags
);
2243 return NETDEV_TX_BUSY
;
2245 spin_unlock_irqrestore(&np
->lock
, flags
);
2247 start_tx
= put_tx
= np
->put_tx
.orig
;
2249 /* setup the header buffer */
2251 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2252 np
->put_tx_ctx
->dma
= dma_map_single(&np
->pci_dev
->dev
,
2253 skb
->data
+ offset
, bcnt
,
2255 if (unlikely(dma_mapping_error(&np
->pci_dev
->dev
,
2256 np
->put_tx_ctx
->dma
))) {
2257 /* on DMA mapping error - drop the packet */
2258 dev_kfree_skb_any(skb
);
2259 u64_stats_update_begin(&np
->swstats_tx_syncp
);
2260 nv_txrx_stats_inc(stat_tx_dropped
);
2261 u64_stats_update_end(&np
->swstats_tx_syncp
);
2262 return NETDEV_TX_OK
;
2264 np
->put_tx_ctx
->dma_len
= bcnt
;
2265 np
->put_tx_ctx
->dma_single
= 1;
2266 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2267 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2269 tx_flags
= np
->tx_flags
;
2272 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2273 put_tx
= np
->tx_ring
.orig
;
2274 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2275 np
->put_tx_ctx
= np
->tx_skb
;
2278 /* setup the fragments */
2279 for (i
= 0; i
< fragments
; i
++) {
2280 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2281 u32 frag_size
= skb_frag_size(frag
);
2286 start_tx_ctx
= tmp_tx_ctx
= np
->put_tx_ctx
;
2288 bcnt
= (frag_size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: frag_size
;
2289 np
->put_tx_ctx
->dma
= skb_frag_dma_map(
2294 if (unlikely(dma_mapping_error(&np
->pci_dev
->dev
,
2295 np
->put_tx_ctx
->dma
))) {
2297 /* Unwind the mapped fragments */
2299 nv_unmap_txskb(np
, start_tx_ctx
);
2300 if (unlikely(tmp_tx_ctx
++ == np
->last_tx_ctx
))
2301 tmp_tx_ctx
= np
->tx_skb
;
2302 } while (tmp_tx_ctx
!= np
->put_tx_ctx
);
2303 dev_kfree_skb_any(skb
);
2304 np
->put_tx_ctx
= start_tx_ctx
;
2305 u64_stats_update_begin(&np
->swstats_tx_syncp
);
2306 nv_txrx_stats_inc(stat_tx_dropped
);
2307 u64_stats_update_end(&np
->swstats_tx_syncp
);
2308 return NETDEV_TX_OK
;
2311 np
->put_tx_ctx
->dma_len
= bcnt
;
2312 np
->put_tx_ctx
->dma_single
= 0;
2313 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2314 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2318 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2319 put_tx
= np
->tx_ring
.orig
;
2320 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2321 np
->put_tx_ctx
= np
->tx_skb
;
2322 } while (frag_size
);
2325 if (unlikely(put_tx
== np
->tx_ring
.orig
))
2326 prev_tx
= np
->last_tx
.orig
;
2328 prev_tx
= put_tx
- 1;
2330 if (unlikely(np
->put_tx_ctx
== np
->tx_skb
))
2331 prev_tx_ctx
= np
->last_tx_ctx
;
2333 prev_tx_ctx
= np
->put_tx_ctx
- 1;
2335 /* set last fragment flag */
2336 prev_tx
->flaglen
|= cpu_to_le32(tx_flags_extra
);
2338 /* save skb in this slot's context area */
2339 prev_tx_ctx
->skb
= skb
;
2341 if (skb_is_gso(skb
))
2342 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2344 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2345 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2347 spin_lock_irqsave(&np
->lock
, flags
);
2350 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2352 netdev_sent_queue(np
->dev
, skb
->len
);
2354 skb_tx_timestamp(skb
);
2356 np
->put_tx
.orig
= put_tx
;
2358 spin_unlock_irqrestore(&np
->lock
, flags
);
2360 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2361 return NETDEV_TX_OK
;
2364 static netdev_tx_t
nv_start_xmit_optimized(struct sk_buff
*skb
,
2365 struct net_device
*dev
)
2367 struct fe_priv
*np
= netdev_priv(dev
);
2370 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2374 u32 size
= skb_headlen(skb
);
2375 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2377 struct ring_desc_ex
*put_tx
;
2378 struct ring_desc_ex
*start_tx
;
2379 struct ring_desc_ex
*prev_tx
;
2380 struct nv_skb_map
*prev_tx_ctx
;
2381 struct nv_skb_map
*start_tx_ctx
= NULL
;
2382 struct nv_skb_map
*tmp_tx_ctx
= NULL
;
2383 unsigned long flags
;
2385 /* add fragments to entries count */
2386 for (i
= 0; i
< fragments
; i
++) {
2387 u32 frag_size
= skb_frag_size(&skb_shinfo(skb
)->frags
[i
]);
2389 entries
+= (frag_size
>> NV_TX2_TSO_MAX_SHIFT
) +
2390 ((frag_size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2393 spin_lock_irqsave(&np
->lock
, flags
);
2394 empty_slots
= nv_get_empty_tx_slots(np
);
2395 if (unlikely(empty_slots
<= entries
)) {
2396 netif_stop_queue(dev
);
2398 spin_unlock_irqrestore(&np
->lock
, flags
);
2399 return NETDEV_TX_BUSY
;
2401 spin_unlock_irqrestore(&np
->lock
, flags
);
2403 start_tx
= put_tx
= np
->put_tx
.ex
;
2404 start_tx_ctx
= np
->put_tx_ctx
;
2406 /* setup the header buffer */
2408 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2409 np
->put_tx_ctx
->dma
= dma_map_single(&np
->pci_dev
->dev
,
2410 skb
->data
+ offset
, bcnt
,
2412 if (unlikely(dma_mapping_error(&np
->pci_dev
->dev
,
2413 np
->put_tx_ctx
->dma
))) {
2414 /* on DMA mapping error - drop the packet */
2415 dev_kfree_skb_any(skb
);
2416 u64_stats_update_begin(&np
->swstats_tx_syncp
);
2417 nv_txrx_stats_inc(stat_tx_dropped
);
2418 u64_stats_update_end(&np
->swstats_tx_syncp
);
2419 return NETDEV_TX_OK
;
2421 np
->put_tx_ctx
->dma_len
= bcnt
;
2422 np
->put_tx_ctx
->dma_single
= 1;
2423 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2424 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2425 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2427 tx_flags
= NV_TX2_VALID
;
2430 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2431 put_tx
= np
->tx_ring
.ex
;
2432 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2433 np
->put_tx_ctx
= np
->tx_skb
;
2436 /* setup the fragments */
2437 for (i
= 0; i
< fragments
; i
++) {
2438 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2439 u32 frag_size
= skb_frag_size(frag
);
2443 bcnt
= (frag_size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: frag_size
;
2445 start_tx_ctx
= tmp_tx_ctx
= np
->put_tx_ctx
;
2446 np
->put_tx_ctx
->dma
= skb_frag_dma_map(
2452 if (unlikely(dma_mapping_error(&np
->pci_dev
->dev
,
2453 np
->put_tx_ctx
->dma
))) {
2455 /* Unwind the mapped fragments */
2457 nv_unmap_txskb(np
, start_tx_ctx
);
2458 if (unlikely(tmp_tx_ctx
++ == np
->last_tx_ctx
))
2459 tmp_tx_ctx
= np
->tx_skb
;
2460 } while (tmp_tx_ctx
!= np
->put_tx_ctx
);
2461 dev_kfree_skb_any(skb
);
2462 np
->put_tx_ctx
= start_tx_ctx
;
2463 u64_stats_update_begin(&np
->swstats_tx_syncp
);
2464 nv_txrx_stats_inc(stat_tx_dropped
);
2465 u64_stats_update_end(&np
->swstats_tx_syncp
);
2466 return NETDEV_TX_OK
;
2468 np
->put_tx_ctx
->dma_len
= bcnt
;
2469 np
->put_tx_ctx
->dma_single
= 0;
2470 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2471 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2472 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2476 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2477 put_tx
= np
->tx_ring
.ex
;
2478 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2479 np
->put_tx_ctx
= np
->tx_skb
;
2480 } while (frag_size
);
2483 if (unlikely(put_tx
== np
->tx_ring
.ex
))
2484 prev_tx
= np
->last_tx
.ex
;
2486 prev_tx
= put_tx
- 1;
2488 if (unlikely(np
->put_tx_ctx
== np
->tx_skb
))
2489 prev_tx_ctx
= np
->last_tx_ctx
;
2491 prev_tx_ctx
= np
->put_tx_ctx
- 1;
2493 /* set last fragment flag */
2494 prev_tx
->flaglen
|= cpu_to_le32(NV_TX2_LASTPACKET
);
2496 /* save skb in this slot's context area */
2497 prev_tx_ctx
->skb
= skb
;
2499 if (skb_is_gso(skb
))
2500 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2502 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2503 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2506 if (skb_vlan_tag_present(skb
))
2507 start_tx
->txvlan
= cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT
|
2508 skb_vlan_tag_get(skb
));
2510 start_tx
->txvlan
= 0;
2512 spin_lock_irqsave(&np
->lock
, flags
);
2515 /* Limit the number of outstanding tx. Setup all fragments, but
2516 * do not set the VALID bit on the first descriptor. Save a pointer
2517 * to that descriptor and also for next skb_map element.
2520 if (np
->tx_pkts_in_progress
== NV_TX_LIMIT_COUNT
) {
2521 if (!np
->tx_change_owner
)
2522 np
->tx_change_owner
= start_tx_ctx
;
2524 /* remove VALID bit */
2525 tx_flags
&= ~NV_TX2_VALID
;
2526 start_tx_ctx
->first_tx_desc
= start_tx
;
2527 start_tx_ctx
->next_tx_ctx
= np
->put_tx_ctx
;
2528 np
->tx_end_flip
= np
->put_tx_ctx
;
2530 np
->tx_pkts_in_progress
++;
2535 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2537 netdev_sent_queue(np
->dev
, skb
->len
);
2539 skb_tx_timestamp(skb
);
2541 np
->put_tx
.ex
= put_tx
;
2543 spin_unlock_irqrestore(&np
->lock
, flags
);
2545 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2546 return NETDEV_TX_OK
;
2549 static inline void nv_tx_flip_ownership(struct net_device
*dev
)
2551 struct fe_priv
*np
= netdev_priv(dev
);
2553 np
->tx_pkts_in_progress
--;
2554 if (np
->tx_change_owner
) {
2555 np
->tx_change_owner
->first_tx_desc
->flaglen
|=
2556 cpu_to_le32(NV_TX2_VALID
);
2557 np
->tx_pkts_in_progress
++;
2559 np
->tx_change_owner
= np
->tx_change_owner
->next_tx_ctx
;
2560 if (np
->tx_change_owner
== np
->tx_end_flip
)
2561 np
->tx_change_owner
= NULL
;
2563 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2568 * nv_tx_done: check for completed packets, release the skbs.
2570 * Caller must own np->lock.
2572 static int nv_tx_done(struct net_device
*dev
, int limit
)
2574 struct fe_priv
*np
= netdev_priv(dev
);
2577 struct ring_desc
*orig_get_tx
= np
->get_tx
.orig
;
2578 unsigned int bytes_compl
= 0;
2580 while ((np
->get_tx
.orig
!= np
->put_tx
.orig
) &&
2581 !((flags
= le32_to_cpu(np
->get_tx
.orig
->flaglen
)) & NV_TX_VALID
) &&
2582 (tx_work
< limit
)) {
2584 nv_unmap_txskb(np
, np
->get_tx_ctx
);
2586 if (np
->desc_ver
== DESC_VER_1
) {
2587 if (flags
& NV_TX_LASTPACKET
) {
2588 if (unlikely(flags
& NV_TX_ERROR
)) {
2589 if ((flags
& NV_TX_RETRYERROR
)
2590 && !(flags
& NV_TX_RETRYCOUNT_MASK
))
2591 nv_legacybackoff_reseed(dev
);
2595 u64_stats_update_begin(&np
->swstats_tx_syncp
);
2596 nv_txrx_stats_inc(stat_tx_packets
);
2597 len
= np
->get_tx_ctx
->skb
->len
;
2598 nv_txrx_stats_add(stat_tx_bytes
, len
);
2599 u64_stats_update_end(&np
->swstats_tx_syncp
);
2601 bytes_compl
+= np
->get_tx_ctx
->skb
->len
;
2602 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2603 np
->get_tx_ctx
->skb
= NULL
;
2607 if (flags
& NV_TX2_LASTPACKET
) {
2608 if (unlikely(flags
& NV_TX2_ERROR
)) {
2609 if ((flags
& NV_TX2_RETRYERROR
)
2610 && !(flags
& NV_TX2_RETRYCOUNT_MASK
))
2611 nv_legacybackoff_reseed(dev
);
2615 u64_stats_update_begin(&np
->swstats_tx_syncp
);
2616 nv_txrx_stats_inc(stat_tx_packets
);
2617 len
= np
->get_tx_ctx
->skb
->len
;
2618 nv_txrx_stats_add(stat_tx_bytes
, len
);
2619 u64_stats_update_end(&np
->swstats_tx_syncp
);
2621 bytes_compl
+= np
->get_tx_ctx
->skb
->len
;
2622 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2623 np
->get_tx_ctx
->skb
= NULL
;
2627 if (unlikely(np
->get_tx
.orig
++ == np
->last_tx
.orig
))
2628 np
->get_tx
.orig
= np
->tx_ring
.orig
;
2629 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2630 np
->get_tx_ctx
= np
->tx_skb
;
2633 netdev_completed_queue(np
->dev
, tx_work
, bytes_compl
);
2635 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.orig
!= orig_get_tx
))) {
2637 netif_wake_queue(dev
);
2642 static int nv_tx_done_optimized(struct net_device
*dev
, int limit
)
2644 struct fe_priv
*np
= netdev_priv(dev
);
2647 struct ring_desc_ex
*orig_get_tx
= np
->get_tx
.ex
;
2648 unsigned long bytes_cleaned
= 0;
2650 while ((np
->get_tx
.ex
!= np
->put_tx
.ex
) &&
2651 !((flags
= le32_to_cpu(np
->get_tx
.ex
->flaglen
)) & NV_TX2_VALID
) &&
2652 (tx_work
< limit
)) {
2654 nv_unmap_txskb(np
, np
->get_tx_ctx
);
2656 if (flags
& NV_TX2_LASTPACKET
) {
2657 if (unlikely(flags
& NV_TX2_ERROR
)) {
2658 if ((flags
& NV_TX2_RETRYERROR
)
2659 && !(flags
& NV_TX2_RETRYCOUNT_MASK
)) {
2660 if (np
->driver_data
& DEV_HAS_GEAR_MODE
)
2661 nv_gear_backoff_reseed(dev
);
2663 nv_legacybackoff_reseed(dev
);
2668 u64_stats_update_begin(&np
->swstats_tx_syncp
);
2669 nv_txrx_stats_inc(stat_tx_packets
);
2670 len
= np
->get_tx_ctx
->skb
->len
;
2671 nv_txrx_stats_add(stat_tx_bytes
, len
);
2672 u64_stats_update_end(&np
->swstats_tx_syncp
);
2675 bytes_cleaned
+= np
->get_tx_ctx
->skb
->len
;
2676 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2677 np
->get_tx_ctx
->skb
= NULL
;
2681 nv_tx_flip_ownership(dev
);
2684 if (unlikely(np
->get_tx
.ex
++ == np
->last_tx
.ex
))
2685 np
->get_tx
.ex
= np
->tx_ring
.ex
;
2686 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2687 np
->get_tx_ctx
= np
->tx_skb
;
2690 netdev_completed_queue(np
->dev
, tx_work
, bytes_cleaned
);
2692 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.ex
!= orig_get_tx
))) {
2694 netif_wake_queue(dev
);
2700 * nv_tx_timeout: dev->tx_timeout function
2701 * Called with netif_tx_lock held.
2703 static void nv_tx_timeout(struct net_device
*dev
)
2705 struct fe_priv
*np
= netdev_priv(dev
);
2706 u8 __iomem
*base
= get_hwbase(dev
);
2708 union ring_type put_tx
;
2711 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
2712 status
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
2714 status
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
2716 netdev_warn(dev
, "Got tx_timeout. irq status: %08x\n", status
);
2718 if (unlikely(debug_tx_timeout
)) {
2721 netdev_info(dev
, "Ring at %lx\n", (unsigned long)np
->ring_addr
);
2722 netdev_info(dev
, "Dumping tx registers\n");
2723 for (i
= 0; i
<= np
->register_size
; i
+= 32) {
2725 "%3x: %08x %08x %08x %08x "
2726 "%08x %08x %08x %08x\n",
2728 readl(base
+ i
+ 0), readl(base
+ i
+ 4),
2729 readl(base
+ i
+ 8), readl(base
+ i
+ 12),
2730 readl(base
+ i
+ 16), readl(base
+ i
+ 20),
2731 readl(base
+ i
+ 24), readl(base
+ i
+ 28));
2733 netdev_info(dev
, "Dumping tx ring\n");
2734 for (i
= 0; i
< np
->tx_ring_size
; i
+= 4) {
2735 if (!nv_optimized(np
)) {
2737 "%03x: %08x %08x // %08x %08x "
2738 "// %08x %08x // %08x %08x\n",
2740 le32_to_cpu(np
->tx_ring
.orig
[i
].buf
),
2741 le32_to_cpu(np
->tx_ring
.orig
[i
].flaglen
),
2742 le32_to_cpu(np
->tx_ring
.orig
[i
+1].buf
),
2743 le32_to_cpu(np
->tx_ring
.orig
[i
+1].flaglen
),
2744 le32_to_cpu(np
->tx_ring
.orig
[i
+2].buf
),
2745 le32_to_cpu(np
->tx_ring
.orig
[i
+2].flaglen
),
2746 le32_to_cpu(np
->tx_ring
.orig
[i
+3].buf
),
2747 le32_to_cpu(np
->tx_ring
.orig
[i
+3].flaglen
));
2750 "%03x: %08x %08x %08x "
2751 "// %08x %08x %08x "
2752 "// %08x %08x %08x "
2753 "// %08x %08x %08x\n",
2755 le32_to_cpu(np
->tx_ring
.ex
[i
].bufhigh
),
2756 le32_to_cpu(np
->tx_ring
.ex
[i
].buflow
),
2757 le32_to_cpu(np
->tx_ring
.ex
[i
].flaglen
),
2758 le32_to_cpu(np
->tx_ring
.ex
[i
+1].bufhigh
),
2759 le32_to_cpu(np
->tx_ring
.ex
[i
+1].buflow
),
2760 le32_to_cpu(np
->tx_ring
.ex
[i
+1].flaglen
),
2761 le32_to_cpu(np
->tx_ring
.ex
[i
+2].bufhigh
),
2762 le32_to_cpu(np
->tx_ring
.ex
[i
+2].buflow
),
2763 le32_to_cpu(np
->tx_ring
.ex
[i
+2].flaglen
),
2764 le32_to_cpu(np
->tx_ring
.ex
[i
+3].bufhigh
),
2765 le32_to_cpu(np
->tx_ring
.ex
[i
+3].buflow
),
2766 le32_to_cpu(np
->tx_ring
.ex
[i
+3].flaglen
));
2771 spin_lock_irq(&np
->lock
);
2773 /* 1) stop tx engine */
2776 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2777 saved_tx_limit
= np
->tx_limit
;
2778 np
->tx_limit
= 0; /* prevent giving HW any limited pkts */
2779 np
->tx_stop
= 0; /* prevent waking tx queue */
2780 if (!nv_optimized(np
))
2781 nv_tx_done(dev
, np
->tx_ring_size
);
2783 nv_tx_done_optimized(dev
, np
->tx_ring_size
);
2785 /* save current HW position */
2786 if (np
->tx_change_owner
)
2787 put_tx
.ex
= np
->tx_change_owner
->first_tx_desc
;
2789 put_tx
= np
->put_tx
;
2791 /* 3) clear all tx state */
2795 /* 4) restore state to current HW position */
2796 np
->get_tx
= np
->put_tx
= put_tx
;
2797 np
->tx_limit
= saved_tx_limit
;
2799 /* 5) restart tx engine */
2801 netif_wake_queue(dev
);
2802 spin_unlock_irq(&np
->lock
);
2806 * Called when the nic notices a mismatch between the actual data len on the
2807 * wire and the len indicated in the 802 header
2809 static int nv_getlen(struct net_device
*dev
, void *packet
, int datalen
)
2811 int hdrlen
; /* length of the 802 header */
2812 int protolen
; /* length as stored in the proto field */
2814 /* 1) calculate len according to header */
2815 if (((struct vlan_ethhdr
*)packet
)->h_vlan_proto
== htons(ETH_P_8021Q
)) {
2816 protolen
= ntohs(((struct vlan_ethhdr
*)packet
)->h_vlan_encapsulated_proto
);
2819 protolen
= ntohs(((struct ethhdr
*)packet
)->h_proto
);
2822 if (protolen
> ETH_DATA_LEN
)
2823 return datalen
; /* Value in proto field not a len, no checks possible */
2826 /* consistency checks: */
2827 if (datalen
> ETH_ZLEN
) {
2828 if (datalen
>= protolen
) {
2829 /* more data on wire than in 802 header, trim of
2834 /* less data on wire than mentioned in header.
2835 * Discard the packet.
2840 /* short packet. Accept only if 802 values are also short */
2841 if (protolen
> ETH_ZLEN
) {
2848 static void rx_missing_handler(u32 flags
, struct fe_priv
*np
)
2850 if (flags
& NV_RX_MISSEDFRAME
) {
2851 u64_stats_update_begin(&np
->swstats_rx_syncp
);
2852 nv_txrx_stats_inc(stat_rx_missed_errors
);
2853 u64_stats_update_end(&np
->swstats_rx_syncp
);
2857 static int nv_rx_process(struct net_device
*dev
, int limit
)
2859 struct fe_priv
*np
= netdev_priv(dev
);
2862 struct sk_buff
*skb
;
2865 while ((np
->get_rx
.orig
!= np
->put_rx
.orig
) &&
2866 !((flags
= le32_to_cpu(np
->get_rx
.orig
->flaglen
)) & NV_RX_AVAIL
) &&
2867 (rx_work
< limit
)) {
2870 * the packet is for us - immediately tear down the pci mapping.
2871 * TODO: check if a prefetch of the first cacheline improves
2874 dma_unmap_single(&np
->pci_dev
->dev
, np
->get_rx_ctx
->dma
,
2875 np
->get_rx_ctx
->dma_len
,
2877 skb
= np
->get_rx_ctx
->skb
;
2878 np
->get_rx_ctx
->skb
= NULL
;
2880 /* look at what we actually got: */
2881 if (np
->desc_ver
== DESC_VER_1
) {
2882 if (likely(flags
& NV_RX_DESCRIPTORVALID
)) {
2883 len
= flags
& LEN_MASK_V1
;
2884 if (unlikely(flags
& NV_RX_ERROR
)) {
2885 if ((flags
& NV_RX_ERROR_MASK
) == NV_RX_ERROR4
) {
2886 len
= nv_getlen(dev
, skb
->data
, len
);
2892 /* framing errors are soft errors */
2893 else if ((flags
& NV_RX_ERROR_MASK
) == NV_RX_FRAMINGERR
) {
2894 if (flags
& NV_RX_SUBTRACT1
)
2897 /* the rest are hard errors */
2899 rx_missing_handler(flags
, np
);
2909 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2910 len
= flags
& LEN_MASK_V2
;
2911 if (unlikely(flags
& NV_RX2_ERROR
)) {
2912 if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_ERROR4
) {
2913 len
= nv_getlen(dev
, skb
->data
, len
);
2919 /* framing errors are soft errors */
2920 else if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_FRAMINGERR
) {
2921 if (flags
& NV_RX2_SUBTRACT1
)
2924 /* the rest are hard errors */
2930 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
2931 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
2932 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2938 /* got a valid packet - forward it to the network core */
2940 skb
->protocol
= eth_type_trans(skb
, dev
);
2941 napi_gro_receive(&np
->napi
, skb
);
2942 u64_stats_update_begin(&np
->swstats_rx_syncp
);
2943 nv_txrx_stats_inc(stat_rx_packets
);
2944 nv_txrx_stats_add(stat_rx_bytes
, len
);
2945 u64_stats_update_end(&np
->swstats_rx_syncp
);
2947 if (unlikely(np
->get_rx
.orig
++ == np
->last_rx
.orig
))
2948 np
->get_rx
.orig
= np
->rx_ring
.orig
;
2949 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
2950 np
->get_rx_ctx
= np
->rx_skb
;
2958 static int nv_rx_process_optimized(struct net_device
*dev
, int limit
)
2960 struct fe_priv
*np
= netdev_priv(dev
);
2964 struct sk_buff
*skb
;
2967 while ((np
->get_rx
.ex
!= np
->put_rx
.ex
) &&
2968 !((flags
= le32_to_cpu(np
->get_rx
.ex
->flaglen
)) & NV_RX2_AVAIL
) &&
2969 (rx_work
< limit
)) {
2972 * the packet is for us - immediately tear down the pci mapping.
2973 * TODO: check if a prefetch of the first cacheline improves
2976 dma_unmap_single(&np
->pci_dev
->dev
, np
->get_rx_ctx
->dma
,
2977 np
->get_rx_ctx
->dma_len
,
2979 skb
= np
->get_rx_ctx
->skb
;
2980 np
->get_rx_ctx
->skb
= NULL
;
2982 /* look at what we actually got: */
2983 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2984 len
= flags
& LEN_MASK_V2
;
2985 if (unlikely(flags
& NV_RX2_ERROR
)) {
2986 if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_ERROR4
) {
2987 len
= nv_getlen(dev
, skb
->data
, len
);
2993 /* framing errors are soft errors */
2994 else if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_FRAMINGERR
) {
2995 if (flags
& NV_RX2_SUBTRACT1
)
2998 /* the rest are hard errors */
3005 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
3006 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
3007 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3009 /* got a valid packet - forward it to the network core */
3011 skb
->protocol
= eth_type_trans(skb
, dev
);
3012 prefetch(skb
->data
);
3014 vlanflags
= le32_to_cpu(np
->get_rx
.ex
->buflow
);
3017 * There's need to check for NETIF_F_HW_VLAN_CTAG_RX
3018 * here. Even if vlan rx accel is disabled,
3019 * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
3021 if (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
&&
3022 vlanflags
& NV_RX3_VLAN_TAG_PRESENT
) {
3023 u16 vid
= vlanflags
& NV_RX3_VLAN_TAG_MASK
;
3025 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vid
);
3027 napi_gro_receive(&np
->napi
, skb
);
3028 u64_stats_update_begin(&np
->swstats_rx_syncp
);
3029 nv_txrx_stats_inc(stat_rx_packets
);
3030 nv_txrx_stats_add(stat_rx_bytes
, len
);
3031 u64_stats_update_end(&np
->swstats_rx_syncp
);
3036 if (unlikely(np
->get_rx
.ex
++ == np
->last_rx
.ex
))
3037 np
->get_rx
.ex
= np
->rx_ring
.ex
;
3038 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
3039 np
->get_rx_ctx
= np
->rx_skb
;
3047 static void set_bufsize(struct net_device
*dev
)
3049 struct fe_priv
*np
= netdev_priv(dev
);
3051 if (dev
->mtu
<= ETH_DATA_LEN
)
3052 np
->rx_buf_sz
= ETH_DATA_LEN
+ NV_RX_HEADERS
;
3054 np
->rx_buf_sz
= dev
->mtu
+ NV_RX_HEADERS
;
3058 * nv_change_mtu: dev->change_mtu function
3059 * Called with dev_base_lock held for read.
3061 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
3063 struct fe_priv
*np
= netdev_priv(dev
);
3069 /* return early if the buffer sizes will not change */
3070 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
3073 /* synchronized against open : rtnl_lock() held by caller */
3074 if (netif_running(dev
)) {
3075 u8 __iomem
*base
= get_hwbase(dev
);
3077 * It seems that the nic preloads valid ring entries into an
3078 * internal buffer. The procedure for flushing everything is
3079 * guessed, there is probably a simpler approach.
3080 * Changing the MTU is a rare event, it shouldn't matter.
3082 nv_disable_irq(dev
);
3083 nv_napi_disable(dev
);
3084 netif_tx_lock_bh(dev
);
3085 netif_addr_lock(dev
);
3086 spin_lock(&np
->lock
);
3090 /* drain rx queue */
3092 /* reinit driver view of the rx queue */
3094 if (nv_init_ring(dev
)) {
3095 if (!np
->in_shutdown
)
3096 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3098 /* reinit nic view of the rx queue */
3099 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
3100 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
3101 writel(((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
3102 base
+ NvRegRingSizes
);
3104 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
3107 /* restart rx engine */
3109 spin_unlock(&np
->lock
);
3110 netif_addr_unlock(dev
);
3111 netif_tx_unlock_bh(dev
);
3112 nv_napi_enable(dev
);
3118 static void nv_copy_mac_to_hw(struct net_device
*dev
)
3120 u8 __iomem
*base
= get_hwbase(dev
);
3123 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
3124 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
3125 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
3127 writel(mac
[0], base
+ NvRegMacAddrA
);
3128 writel(mac
[1], base
+ NvRegMacAddrB
);
3132 * nv_set_mac_address: dev->set_mac_address function
3133 * Called with rtnl_lock() held.
3135 static int nv_set_mac_address(struct net_device
*dev
, void *addr
)
3137 struct fe_priv
*np
= netdev_priv(dev
);
3138 struct sockaddr
*macaddr
= (struct sockaddr
*)addr
;
3140 if (!is_valid_ether_addr(macaddr
->sa_data
))
3141 return -EADDRNOTAVAIL
;
3143 /* synchronized against open : rtnl_lock() held by caller */
3144 memcpy(dev
->dev_addr
, macaddr
->sa_data
, ETH_ALEN
);
3146 if (netif_running(dev
)) {
3147 netif_tx_lock_bh(dev
);
3148 netif_addr_lock(dev
);
3149 spin_lock_irq(&np
->lock
);
3151 /* stop rx engine */
3154 /* set mac address */
3155 nv_copy_mac_to_hw(dev
);
3157 /* restart rx engine */
3159 spin_unlock_irq(&np
->lock
);
3160 netif_addr_unlock(dev
);
3161 netif_tx_unlock_bh(dev
);
3163 nv_copy_mac_to_hw(dev
);
3169 * nv_set_multicast: dev->set_multicast function
3170 * Called with netif_tx_lock held.
3172 static void nv_set_multicast(struct net_device
*dev
)
3174 struct fe_priv
*np
= netdev_priv(dev
);
3175 u8 __iomem
*base
= get_hwbase(dev
);
3178 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & NVREG_PFF_PAUSE_RX
;
3180 memset(addr
, 0, sizeof(addr
));
3181 memset(mask
, 0, sizeof(mask
));
3183 if (dev
->flags
& IFF_PROMISC
) {
3184 pff
|= NVREG_PFF_PROMISC
;
3186 pff
|= NVREG_PFF_MYADDR
;
3188 if (dev
->flags
& IFF_ALLMULTI
|| !netdev_mc_empty(dev
)) {
3192 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
3193 if (dev
->flags
& IFF_ALLMULTI
) {
3194 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
3196 struct netdev_hw_addr
*ha
;
3198 netdev_for_each_mc_addr(ha
, dev
) {
3199 unsigned char *hw_addr
= ha
->addr
;
3202 a
= le32_to_cpu(*(__le32
*) hw_addr
);
3203 b
= le16_to_cpu(*(__le16
*) (&hw_addr
[4]));
3210 addr
[0] = alwaysOn
[0];
3211 addr
[1] = alwaysOn
[1];
3212 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
3213 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
3215 mask
[0] = NVREG_MCASTMASKA_NONE
;
3216 mask
[1] = NVREG_MCASTMASKB_NONE
;
3219 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
3220 pff
|= NVREG_PFF_ALWAYS
;
3221 spin_lock_irq(&np
->lock
);
3223 writel(addr
[0], base
+ NvRegMulticastAddrA
);
3224 writel(addr
[1], base
+ NvRegMulticastAddrB
);
3225 writel(mask
[0], base
+ NvRegMulticastMaskA
);
3226 writel(mask
[1], base
+ NvRegMulticastMaskB
);
3227 writel(pff
, base
+ NvRegPacketFilterFlags
);
3229 spin_unlock_irq(&np
->lock
);
3232 static void nv_update_pause(struct net_device
*dev
, u32 pause_flags
)
3234 struct fe_priv
*np
= netdev_priv(dev
);
3235 u8 __iomem
*base
= get_hwbase(dev
);
3237 np
->pause_flags
&= ~(NV_PAUSEFRAME_TX_ENABLE
| NV_PAUSEFRAME_RX_ENABLE
);
3239 if (np
->pause_flags
& NV_PAUSEFRAME_RX_CAPABLE
) {
3240 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & ~NVREG_PFF_PAUSE_RX
;
3241 if (pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) {
3242 writel(pff
|NVREG_PFF_PAUSE_RX
, base
+ NvRegPacketFilterFlags
);
3243 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3245 writel(pff
, base
+ NvRegPacketFilterFlags
);
3248 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
) {
3249 u32 regmisc
= readl(base
+ NvRegMisc1
) & ~NVREG_MISC1_PAUSE_TX
;
3250 if (pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) {
3251 u32 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V1
;
3252 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
)
3253 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V2
;
3254 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
) {
3255 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V3
;
3256 /* limit the number of tx pause frames to a default of 8 */
3257 writel(readl(base
+ NvRegTxPauseFrameLimit
)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE
, base
+ NvRegTxPauseFrameLimit
);
3259 writel(pause_enable
, base
+ NvRegTxPauseFrame
);
3260 writel(regmisc
|NVREG_MISC1_PAUSE_TX
, base
+ NvRegMisc1
);
3261 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3263 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
3264 writel(regmisc
, base
+ NvRegMisc1
);
3269 static void nv_force_linkspeed(struct net_device
*dev
, int speed
, int duplex
)
3271 struct fe_priv
*np
= netdev_priv(dev
);
3272 u8 __iomem
*base
= get_hwbase(dev
);
3276 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|speed
;
3277 np
->duplex
= duplex
;
3279 /* see if gigabit phy */
3280 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3281 if (mii_status
& PHY_GIGABIT
) {
3282 np
->gigabit
= PHY_GIGABIT
;
3283 phyreg
= readl(base
+ NvRegSlotTime
);
3284 phyreg
&= ~(0x3FF00);
3285 if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
)
3286 phyreg
|= NVREG_SLOTTIME_10_100_FULL
;
3287 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
)
3288 phyreg
|= NVREG_SLOTTIME_10_100_FULL
;
3289 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
3290 phyreg
|= NVREG_SLOTTIME_1000_FULL
;
3291 writel(phyreg
, base
+ NvRegSlotTime
);
3294 phyreg
= readl(base
+ NvRegPhyInterface
);
3295 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
3296 if (np
->duplex
== 0)
3298 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
3300 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) ==
3301 NVREG_LINKSPEED_1000
)
3303 writel(phyreg
, base
+ NvRegPhyInterface
);
3305 if (phyreg
& PHY_RGMII
) {
3306 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) ==
3307 NVREG_LINKSPEED_1000
)
3308 txreg
= NVREG_TX_DEFERRAL_RGMII_1000
;
3310 txreg
= NVREG_TX_DEFERRAL_RGMII_10_100
;
3312 txreg
= NVREG_TX_DEFERRAL_DEFAULT
;
3314 writel(txreg
, base
+ NvRegTxDeferral
);
3316 if (np
->desc_ver
== DESC_VER_1
) {
3317 txreg
= NVREG_TX_WM_DESC1_DEFAULT
;
3319 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) ==
3320 NVREG_LINKSPEED_1000
)
3321 txreg
= NVREG_TX_WM_DESC2_3_1000
;
3323 txreg
= NVREG_TX_WM_DESC2_3_DEFAULT
;
3325 writel(txreg
, base
+ NvRegTxWatermark
);
3327 writel(NVREG_MISC1_FORCE
| (np
->duplex
? 0 : NVREG_MISC1_HD
),
3330 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
3335 * nv_update_linkspeed - Setup the MAC according to the link partner
3336 * @dev: Network device to be configured
3338 * The function queries the PHY and checks if there is a link partner.
3339 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3340 * set to 10 MBit HD.
3342 * The function returns 0 if there is no link partner and 1 if there is
3343 * a good link partner.
3345 static int nv_update_linkspeed(struct net_device
*dev
)
3347 struct fe_priv
*np
= netdev_priv(dev
);
3348 u8 __iomem
*base
= get_hwbase(dev
);
3351 int adv_lpa
, adv_pause
, lpa_pause
;
3352 int newls
= np
->linkspeed
;
3353 int newdup
= np
->duplex
;
3357 u32 control_1000
, status_1000
, phyreg
, pause_flags
, txreg
;
3361 /* If device loopback is enabled, set carrier on and enable max link
3364 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
3365 if (bmcr
& BMCR_LOOPBACK
) {
3366 if (netif_running(dev
)) {
3367 nv_force_linkspeed(dev
, NVREG_LINKSPEED_1000
, 1);
3368 if (!netif_carrier_ok(dev
))
3369 netif_carrier_on(dev
);
3374 /* BMSR_LSTATUS is latched, read it twice:
3375 * we want the current value.
3377 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3378 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3380 if (!(mii_status
& BMSR_LSTATUS
)) {
3381 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3387 if (np
->autoneg
== 0) {
3388 if (np
->fixed_mode
& LPA_100FULL
) {
3389 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3391 } else if (np
->fixed_mode
& LPA_100HALF
) {
3392 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3394 } else if (np
->fixed_mode
& LPA_10FULL
) {
3395 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3398 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3404 /* check auto negotiation is complete */
3405 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
3406 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3407 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3413 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3414 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
3417 if (np
->gigabit
== PHY_GIGABIT
) {
3418 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
3419 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_STAT1000
, MII_READ
);
3421 if ((control_1000
& ADVERTISE_1000FULL
) &&
3422 (status_1000
& LPA_1000FULL
)) {
3423 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
3429 /* FIXME: handle parallel detection properly */
3430 adv_lpa
= lpa
& adv
;
3431 if (adv_lpa
& LPA_100FULL
) {
3432 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3434 } else if (adv_lpa
& LPA_100HALF
) {
3435 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3437 } else if (adv_lpa
& LPA_10FULL
) {
3438 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3440 } else if (adv_lpa
& LPA_10HALF
) {
3441 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3444 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3449 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
3452 np
->duplex
= newdup
;
3453 np
->linkspeed
= newls
;
3455 /* The transmitter and receiver must be restarted for safe update */
3456 if (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
) {
3457 txrxFlags
|= NV_RESTART_TX
;
3460 if (readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) {
3461 txrxFlags
|= NV_RESTART_RX
;
3465 if (np
->gigabit
== PHY_GIGABIT
) {
3466 phyreg
= readl(base
+ NvRegSlotTime
);
3467 phyreg
&= ~(0x3FF00);
3468 if (((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
) ||
3469 ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
))
3470 phyreg
|= NVREG_SLOTTIME_10_100_FULL
;
3471 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
3472 phyreg
|= NVREG_SLOTTIME_1000_FULL
;
3473 writel(phyreg
, base
+ NvRegSlotTime
);
3476 phyreg
= readl(base
+ NvRegPhyInterface
);
3477 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
3478 if (np
->duplex
== 0)
3480 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
3482 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3484 writel(phyreg
, base
+ NvRegPhyInterface
);
3486 phy_exp
= mii_rw(dev
, np
->phyaddr
, MII_EXPANSION
, MII_READ
) & EXPANSION_NWAY
; /* autoneg capable */
3487 if (phyreg
& PHY_RGMII
) {
3488 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
) {
3489 txreg
= NVREG_TX_DEFERRAL_RGMII_1000
;
3491 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
)) {
3492 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_10
)
3493 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_10
;
3495 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_100
;
3497 txreg
= NVREG_TX_DEFERRAL_RGMII_10_100
;
3501 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
))
3502 txreg
= NVREG_TX_DEFERRAL_MII_STRETCH
;
3504 txreg
= NVREG_TX_DEFERRAL_DEFAULT
;
3506 writel(txreg
, base
+ NvRegTxDeferral
);
3508 if (np
->desc_ver
== DESC_VER_1
) {
3509 txreg
= NVREG_TX_WM_DESC1_DEFAULT
;
3511 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3512 txreg
= NVREG_TX_WM_DESC2_3_1000
;
3514 txreg
= NVREG_TX_WM_DESC2_3_DEFAULT
;
3516 writel(txreg
, base
+ NvRegTxWatermark
);
3518 writel(NVREG_MISC1_FORCE
| (np
->duplex
? 0 : NVREG_MISC1_HD
),
3521 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
3525 /* setup pause frame */
3526 if (netif_running(dev
) && (np
->duplex
!= 0)) {
3527 if (np
->autoneg
&& np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) {
3528 adv_pause
= adv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3529 lpa_pause
= lpa
& (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
);
3531 switch (adv_pause
) {
3532 case ADVERTISE_PAUSE_CAP
:
3533 if (lpa_pause
& LPA_PAUSE_CAP
) {
3534 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3535 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3536 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3539 case ADVERTISE_PAUSE_ASYM
:
3540 if (lpa_pause
== (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
))
3541 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3543 case ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
:
3544 if (lpa_pause
& LPA_PAUSE_CAP
) {
3545 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3546 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3547 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3549 if (lpa_pause
== LPA_PAUSE_ASYM
)
3550 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3554 pause_flags
= np
->pause_flags
;
3557 nv_update_pause(dev
, pause_flags
);
3559 if (txrxFlags
& NV_RESTART_TX
)
3561 if (txrxFlags
& NV_RESTART_RX
)
3567 static void nv_linkchange(struct net_device
*dev
)
3569 if (nv_update_linkspeed(dev
)) {
3570 if (!netif_carrier_ok(dev
)) {
3571 netif_carrier_on(dev
);
3572 netdev_info(dev
, "link up\n");
3573 nv_txrx_gate(dev
, false);
3577 if (netif_carrier_ok(dev
)) {
3578 netif_carrier_off(dev
);
3579 netdev_info(dev
, "link down\n");
3580 nv_txrx_gate(dev
, true);
3586 static void nv_link_irq(struct net_device
*dev
)
3588 u8 __iomem
*base
= get_hwbase(dev
);
3591 miistat
= readl(base
+ NvRegMIIStatus
);
3592 writel(NVREG_MIISTAT_LINKCHANGE
, base
+ NvRegMIIStatus
);
3594 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
3598 static void nv_msi_workaround(struct fe_priv
*np
)
3601 /* Need to toggle the msi irq mask within the ethernet device,
3602 * otherwise, future interrupts will not be detected.
3604 if (np
->msi_flags
& NV_MSI_ENABLED
) {
3605 u8 __iomem
*base
= np
->base
;
3607 writel(0, base
+ NvRegMSIIrqMask
);
3608 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
3612 static inline int nv_change_interrupt_mode(struct net_device
*dev
, int total_work
)
3614 struct fe_priv
*np
= netdev_priv(dev
);
3616 if (optimization_mode
== NV_OPTIMIZATION_MODE_DYNAMIC
) {
3617 if (total_work
> NV_DYNAMIC_THRESHOLD
) {
3618 /* transition to poll based interrupts */
3619 np
->quiet_count
= 0;
3620 if (np
->irqmask
!= NVREG_IRQMASK_CPU
) {
3621 np
->irqmask
= NVREG_IRQMASK_CPU
;
3625 if (np
->quiet_count
< NV_DYNAMIC_MAX_QUIET_COUNT
) {
3628 /* reached a period of low activity, switch
3629 to per tx/rx packet interrupts */
3630 if (np
->irqmask
!= NVREG_IRQMASK_THROUGHPUT
) {
3631 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
3640 static irqreturn_t
nv_nic_irq(int foo
, void *data
)
3642 struct net_device
*dev
= (struct net_device
*) data
;
3643 struct fe_priv
*np
= netdev_priv(dev
);
3644 u8 __iomem
*base
= get_hwbase(dev
);
3646 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3647 np
->events
= readl(base
+ NvRegIrqStatus
);
3648 writel(np
->events
, base
+ NvRegIrqStatus
);
3650 np
->events
= readl(base
+ NvRegMSIXIrqStatus
);
3651 writel(np
->events
, base
+ NvRegMSIXIrqStatus
);
3653 if (!(np
->events
& np
->irqmask
))
3656 nv_msi_workaround(np
);
3658 if (napi_schedule_prep(&np
->napi
)) {
3660 * Disable further irq's (msix not enabled with napi)
3662 writel(0, base
+ NvRegIrqMask
);
3663 __napi_schedule(&np
->napi
);
3669 /* All _optimized functions are used to help increase performance
3670 * (reduce CPU and increase throughput). They use descripter version 3,
3671 * compiler directives, and reduce memory accesses.
3673 static irqreturn_t
nv_nic_irq_optimized(int foo
, void *data
)
3675 struct net_device
*dev
= (struct net_device
*) data
;
3676 struct fe_priv
*np
= netdev_priv(dev
);
3677 u8 __iomem
*base
= get_hwbase(dev
);
3679 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3680 np
->events
= readl(base
+ NvRegIrqStatus
);
3681 writel(np
->events
, base
+ NvRegIrqStatus
);
3683 np
->events
= readl(base
+ NvRegMSIXIrqStatus
);
3684 writel(np
->events
, base
+ NvRegMSIXIrqStatus
);
3686 if (!(np
->events
& np
->irqmask
))
3689 nv_msi_workaround(np
);
3691 if (napi_schedule_prep(&np
->napi
)) {
3693 * Disable further irq's (msix not enabled with napi)
3695 writel(0, base
+ NvRegIrqMask
);
3696 __napi_schedule(&np
->napi
);
3702 static irqreturn_t
nv_nic_irq_tx(int foo
, void *data
)
3704 struct net_device
*dev
= (struct net_device
*) data
;
3705 struct fe_priv
*np
= netdev_priv(dev
);
3706 u8 __iomem
*base
= get_hwbase(dev
);
3709 unsigned long flags
;
3712 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_TX_ALL
;
3713 writel(events
, base
+ NvRegMSIXIrqStatus
);
3714 netdev_dbg(dev
, "tx irq events: %08x\n", events
);
3715 if (!(events
& np
->irqmask
))
3718 spin_lock_irqsave(&np
->lock
, flags
);
3719 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3720 spin_unlock_irqrestore(&np
->lock
, flags
);
3722 if (unlikely(i
> max_interrupt_work
)) {
3723 spin_lock_irqsave(&np
->lock
, flags
);
3724 /* disable interrupts on the nic */
3725 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegIrqMask
);
3728 if (!np
->in_shutdown
) {
3729 np
->nic_poll_irq
|= NVREG_IRQ_TX_ALL
;
3730 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3732 spin_unlock_irqrestore(&np
->lock
, flags
);
3733 netdev_dbg(dev
, "%s: too many iterations (%d)\n",
3740 return IRQ_RETVAL(i
);
3743 static int nv_napi_poll(struct napi_struct
*napi
, int budget
)
3745 struct fe_priv
*np
= container_of(napi
, struct fe_priv
, napi
);
3746 struct net_device
*dev
= np
->dev
;
3747 u8 __iomem
*base
= get_hwbase(dev
);
3748 unsigned long flags
;
3750 int rx_count
, tx_work
= 0, rx_work
= 0;
3753 if (!nv_optimized(np
)) {
3754 spin_lock_irqsave(&np
->lock
, flags
);
3755 tx_work
+= nv_tx_done(dev
, np
->tx_ring_size
);
3756 spin_unlock_irqrestore(&np
->lock
, flags
);
3758 rx_count
= nv_rx_process(dev
, budget
- rx_work
);
3759 retcode
= nv_alloc_rx(dev
);
3761 spin_lock_irqsave(&np
->lock
, flags
);
3762 tx_work
+= nv_tx_done_optimized(dev
, np
->tx_ring_size
);
3763 spin_unlock_irqrestore(&np
->lock
, flags
);
3765 rx_count
= nv_rx_process_optimized(dev
,
3767 retcode
= nv_alloc_rx_optimized(dev
);
3769 } while (retcode
== 0 &&
3770 rx_count
> 0 && (rx_work
+= rx_count
) < budget
);
3773 spin_lock_irqsave(&np
->lock
, flags
);
3774 if (!np
->in_shutdown
)
3775 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3776 spin_unlock_irqrestore(&np
->lock
, flags
);
3779 nv_change_interrupt_mode(dev
, tx_work
+ rx_work
);
3781 if (unlikely(np
->events
& NVREG_IRQ_LINK
)) {
3782 spin_lock_irqsave(&np
->lock
, flags
);
3784 spin_unlock_irqrestore(&np
->lock
, flags
);
3786 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3787 spin_lock_irqsave(&np
->lock
, flags
);
3789 spin_unlock_irqrestore(&np
->lock
, flags
);
3790 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3792 if (unlikely(np
->events
& NVREG_IRQ_RECOVER_ERROR
)) {
3793 spin_lock_irqsave(&np
->lock
, flags
);
3794 if (!np
->in_shutdown
) {
3795 np
->nic_poll_irq
= np
->irqmask
;
3796 np
->recover_error
= 1;
3797 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3799 spin_unlock_irqrestore(&np
->lock
, flags
);
3800 napi_complete(napi
);
3804 if (rx_work
< budget
) {
3805 /* re-enable interrupts
3806 (msix not enabled in napi) */
3807 napi_complete_done(napi
, rx_work
);
3809 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3814 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
)
3816 struct net_device
*dev
= (struct net_device
*) data
;
3817 struct fe_priv
*np
= netdev_priv(dev
);
3818 u8 __iomem
*base
= get_hwbase(dev
);
3821 unsigned long flags
;
3824 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
3825 writel(events
, base
+ NvRegMSIXIrqStatus
);
3826 netdev_dbg(dev
, "rx irq events: %08x\n", events
);
3827 if (!(events
& np
->irqmask
))
3830 if (nv_rx_process_optimized(dev
, RX_WORK_PER_LOOP
)) {
3831 if (unlikely(nv_alloc_rx_optimized(dev
))) {
3832 spin_lock_irqsave(&np
->lock
, flags
);
3833 if (!np
->in_shutdown
)
3834 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3835 spin_unlock_irqrestore(&np
->lock
, flags
);
3839 if (unlikely(i
> max_interrupt_work
)) {
3840 spin_lock_irqsave(&np
->lock
, flags
);
3841 /* disable interrupts on the nic */
3842 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3845 if (!np
->in_shutdown
) {
3846 np
->nic_poll_irq
|= NVREG_IRQ_RX_ALL
;
3847 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3849 spin_unlock_irqrestore(&np
->lock
, flags
);
3850 netdev_dbg(dev
, "%s: too many iterations (%d)\n",
3856 return IRQ_RETVAL(i
);
3859 static irqreturn_t
nv_nic_irq_other(int foo
, void *data
)
3861 struct net_device
*dev
= (struct net_device
*) data
;
3862 struct fe_priv
*np
= netdev_priv(dev
);
3863 u8 __iomem
*base
= get_hwbase(dev
);
3866 unsigned long flags
;
3869 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_OTHER
;
3870 writel(events
, base
+ NvRegMSIXIrqStatus
);
3871 netdev_dbg(dev
, "irq events: %08x\n", events
);
3872 if (!(events
& np
->irqmask
))
3875 /* check tx in case we reached max loop limit in tx isr */
3876 spin_lock_irqsave(&np
->lock
, flags
);
3877 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3878 spin_unlock_irqrestore(&np
->lock
, flags
);
3880 if (events
& NVREG_IRQ_LINK
) {
3881 spin_lock_irqsave(&np
->lock
, flags
);
3883 spin_unlock_irqrestore(&np
->lock
, flags
);
3885 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
3886 spin_lock_irqsave(&np
->lock
, flags
);
3888 spin_unlock_irqrestore(&np
->lock
, flags
);
3889 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3891 if (events
& NVREG_IRQ_RECOVER_ERROR
) {
3892 spin_lock_irqsave(&np
->lock
, flags
);
3893 /* disable interrupts on the nic */
3894 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3897 if (!np
->in_shutdown
) {
3898 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3899 np
->recover_error
= 1;
3900 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3902 spin_unlock_irqrestore(&np
->lock
, flags
);
3905 if (unlikely(i
> max_interrupt_work
)) {
3906 spin_lock_irqsave(&np
->lock
, flags
);
3907 /* disable interrupts on the nic */
3908 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3911 if (!np
->in_shutdown
) {
3912 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3913 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3915 spin_unlock_irqrestore(&np
->lock
, flags
);
3916 netdev_dbg(dev
, "%s: too many iterations (%d)\n",
3923 return IRQ_RETVAL(i
);
3926 static irqreturn_t
nv_nic_irq_test(int foo
, void *data
)
3928 struct net_device
*dev
= (struct net_device
*) data
;
3929 struct fe_priv
*np
= netdev_priv(dev
);
3930 u8 __iomem
*base
= get_hwbase(dev
);
3933 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3934 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
3935 writel(events
& NVREG_IRQ_TIMER
, base
+ NvRegIrqStatus
);
3937 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
3938 writel(events
& NVREG_IRQ_TIMER
, base
+ NvRegMSIXIrqStatus
);
3941 if (!(events
& NVREG_IRQ_TIMER
))
3942 return IRQ_RETVAL(0);
3944 nv_msi_workaround(np
);
3946 spin_lock(&np
->lock
);
3948 spin_unlock(&np
->lock
);
3950 return IRQ_RETVAL(1);
3953 static void set_msix_vector_map(struct net_device
*dev
, u32 vector
, u32 irqmask
)
3955 u8 __iomem
*base
= get_hwbase(dev
);
3959 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3960 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3961 * the remaining 8 interrupts.
3963 for (i
= 0; i
< 8; i
++) {
3964 if ((irqmask
>> i
) & 0x1)
3965 msixmap
|= vector
<< (i
<< 2);
3967 writel(readl(base
+ NvRegMSIXMap0
) | msixmap
, base
+ NvRegMSIXMap0
);
3970 for (i
= 0; i
< 8; i
++) {
3971 if ((irqmask
>> (i
+ 8)) & 0x1)
3972 msixmap
|= vector
<< (i
<< 2);
3974 writel(readl(base
+ NvRegMSIXMap1
) | msixmap
, base
+ NvRegMSIXMap1
);
3977 static int nv_request_irq(struct net_device
*dev
, int intr_test
)
3979 struct fe_priv
*np
= get_nvpriv(dev
);
3980 u8 __iomem
*base
= get_hwbase(dev
);
3983 irqreturn_t (*handler
)(int foo
, void *data
);
3986 handler
= nv_nic_irq_test
;
3988 if (nv_optimized(np
))
3989 handler
= nv_nic_irq_optimized
;
3991 handler
= nv_nic_irq
;
3994 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) {
3995 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++)
3996 np
->msi_x_entry
[i
].entry
= i
;
3997 ret
= pci_enable_msix_range(np
->pci_dev
,
3999 np
->msi_flags
& NV_MSI_X_VECTORS_MASK
,
4000 np
->msi_flags
& NV_MSI_X_VECTORS_MASK
);
4002 np
->msi_flags
|= NV_MSI_X_ENABLED
;
4003 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
&& !intr_test
) {
4004 /* Request irq for rx handling */
4005 sprintf(np
->name_rx
, "%s-rx", dev
->name
);
4006 ret
= request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
,
4007 nv_nic_irq_rx
, IRQF_SHARED
, np
->name_rx
, dev
);
4010 "request_irq failed for rx %d\n",
4012 pci_disable_msix(np
->pci_dev
);
4013 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4016 /* Request irq for tx handling */
4017 sprintf(np
->name_tx
, "%s-tx", dev
->name
);
4018 ret
= request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
,
4019 nv_nic_irq_tx
, IRQF_SHARED
, np
->name_tx
, dev
);
4022 "request_irq failed for tx %d\n",
4024 pci_disable_msix(np
->pci_dev
);
4025 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4028 /* Request irq for link and timer handling */
4029 sprintf(np
->name_other
, "%s-other", dev
->name
);
4030 ret
= request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
,
4031 nv_nic_irq_other
, IRQF_SHARED
, np
->name_other
, dev
);
4034 "request_irq failed for link %d\n",
4036 pci_disable_msix(np
->pci_dev
);
4037 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4040 /* map interrupts to their respective vector */
4041 writel(0, base
+ NvRegMSIXMap0
);
4042 writel(0, base
+ NvRegMSIXMap1
);
4043 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_RX
, NVREG_IRQ_RX_ALL
);
4044 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_TX
, NVREG_IRQ_TX_ALL
);
4045 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_OTHER
, NVREG_IRQ_OTHER
);
4047 /* Request irq for all interrupts */
4048 ret
= request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
,
4049 handler
, IRQF_SHARED
, dev
->name
, dev
);
4052 "request_irq failed %d\n",
4054 pci_disable_msix(np
->pci_dev
);
4055 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4059 /* map interrupts to vector 0 */
4060 writel(0, base
+ NvRegMSIXMap0
);
4061 writel(0, base
+ NvRegMSIXMap1
);
4063 netdev_info(dev
, "MSI-X enabled\n");
4067 if (np
->msi_flags
& NV_MSI_CAPABLE
) {
4068 ret
= pci_enable_msi(np
->pci_dev
);
4070 np
->msi_flags
|= NV_MSI_ENABLED
;
4071 ret
= request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
);
4073 netdev_info(dev
, "request_irq failed %d\n",
4075 pci_disable_msi(np
->pci_dev
);
4076 np
->msi_flags
&= ~NV_MSI_ENABLED
;
4080 /* map interrupts to vector 0 */
4081 writel(0, base
+ NvRegMSIMap0
);
4082 writel(0, base
+ NvRegMSIMap1
);
4083 /* enable msi vector 0 */
4084 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
4085 netdev_info(dev
, "MSI enabled\n");
4090 if (request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0)
4095 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, dev
);
4097 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, dev
);
4102 static void nv_free_irq(struct net_device
*dev
)
4104 struct fe_priv
*np
= get_nvpriv(dev
);
4107 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
4108 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++)
4109 free_irq(np
->msi_x_entry
[i
].vector
, dev
);
4110 pci_disable_msix(np
->pci_dev
);
4111 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4113 free_irq(np
->pci_dev
->irq
, dev
);
4114 if (np
->msi_flags
& NV_MSI_ENABLED
) {
4115 pci_disable_msi(np
->pci_dev
);
4116 np
->msi_flags
&= ~NV_MSI_ENABLED
;
4121 static void nv_do_nic_poll(struct timer_list
*t
)
4123 struct fe_priv
*np
= from_timer(np
, t
, nic_poll
);
4124 struct net_device
*dev
= np
->dev
;
4125 u8 __iomem
*base
= get_hwbase(dev
);
4127 unsigned long flags
;
4128 unsigned int irq
= 0;
4131 * First disable irq(s) and then
4132 * reenable interrupts on the nic, we have to do this before calling
4133 * nv_nic_irq because that may decide to do otherwise
4136 if (!using_multi_irqs(dev
)) {
4137 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
4138 irq
= np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
;
4140 irq
= np
->pci_dev
->irq
;
4143 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
4144 irq
= np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
;
4145 mask
|= NVREG_IRQ_RX_ALL
;
4147 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
4148 irq
= np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
;
4149 mask
|= NVREG_IRQ_TX_ALL
;
4151 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
4152 irq
= np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
;
4153 mask
|= NVREG_IRQ_OTHER
;
4157 disable_irq_nosync_lockdep_irqsave(irq
, &flags
);
4158 synchronize_irq(irq
);
4160 if (np
->recover_error
) {
4161 np
->recover_error
= 0;
4162 netdev_info(dev
, "MAC in recoverable error state\n");
4163 if (netif_running(dev
)) {
4164 netif_tx_lock_bh(dev
);
4165 netif_addr_lock(dev
);
4166 spin_lock(&np
->lock
);
4169 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
4172 /* drain rx queue */
4174 /* reinit driver view of the rx queue */
4176 if (nv_init_ring(dev
)) {
4177 if (!np
->in_shutdown
)
4178 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4180 /* reinit nic view of the rx queue */
4181 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4182 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4183 writel(((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4184 base
+ NvRegRingSizes
);
4186 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4188 /* clear interrupts */
4189 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
4190 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4192 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
4194 /* restart rx engine */
4196 spin_unlock(&np
->lock
);
4197 netif_addr_unlock(dev
);
4198 netif_tx_unlock_bh(dev
);
4202 writel(mask
, base
+ NvRegIrqMask
);
4205 if (!using_multi_irqs(dev
)) {
4206 np
->nic_poll_irq
= 0;
4207 if (nv_optimized(np
))
4208 nv_nic_irq_optimized(0, dev
);
4212 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
4213 np
->nic_poll_irq
&= ~NVREG_IRQ_RX_ALL
;
4214 nv_nic_irq_rx(0, dev
);
4216 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
4217 np
->nic_poll_irq
&= ~NVREG_IRQ_TX_ALL
;
4218 nv_nic_irq_tx(0, dev
);
4220 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
4221 np
->nic_poll_irq
&= ~NVREG_IRQ_OTHER
;
4222 nv_nic_irq_other(0, dev
);
4226 enable_irq_lockdep_irqrestore(irq
, &flags
);
4229 #ifdef CONFIG_NET_POLL_CONTROLLER
4230 static void nv_poll_controller(struct net_device
*dev
)
4232 struct fe_priv
*np
= netdev_priv(dev
);
4234 nv_do_nic_poll(&np
->nic_poll
);
4238 static void nv_do_stats_poll(struct timer_list
*t
)
4239 __acquires(&netdev_priv(dev
)->hwstats_lock
)
4240 __releases(&netdev_priv(dev
)->hwstats_lock
)
4242 struct fe_priv
*np
= from_timer(np
, t
, stats_poll
);
4243 struct net_device
*dev
= np
->dev
;
4245 /* If lock is currently taken, the stats are being refreshed
4246 * and hence fresh enough */
4247 if (spin_trylock(&np
->hwstats_lock
)) {
4248 nv_update_stats(dev
);
4249 spin_unlock(&np
->hwstats_lock
);
4252 if (!np
->in_shutdown
)
4253 mod_timer(&np
->stats_poll
,
4254 round_jiffies(jiffies
+ STATS_INTERVAL
));
4257 static void nv_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
4259 struct fe_priv
*np
= netdev_priv(dev
);
4260 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
4261 strlcpy(info
->version
, FORCEDETH_VERSION
, sizeof(info
->version
));
4262 strlcpy(info
->bus_info
, pci_name(np
->pci_dev
), sizeof(info
->bus_info
));
4265 static void nv_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4267 struct fe_priv
*np
= netdev_priv(dev
);
4268 wolinfo
->supported
= WAKE_MAGIC
;
4270 spin_lock_irq(&np
->lock
);
4272 wolinfo
->wolopts
= WAKE_MAGIC
;
4273 spin_unlock_irq(&np
->lock
);
4276 static int nv_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4278 struct fe_priv
*np
= netdev_priv(dev
);
4279 u8 __iomem
*base
= get_hwbase(dev
);
4282 if (wolinfo
->wolopts
== 0) {
4284 } else if (wolinfo
->wolopts
& WAKE_MAGIC
) {
4286 flags
= NVREG_WAKEUPFLAGS_ENABLE
;
4288 if (netif_running(dev
)) {
4289 spin_lock_irq(&np
->lock
);
4290 writel(flags
, base
+ NvRegWakeUpFlags
);
4291 spin_unlock_irq(&np
->lock
);
4293 device_set_wakeup_enable(&np
->pci_dev
->dev
, np
->wolenabled
);
4297 static int nv_get_link_ksettings(struct net_device
*dev
,
4298 struct ethtool_link_ksettings
*cmd
)
4300 struct fe_priv
*np
= netdev_priv(dev
);
4301 u32 speed
, supported
, advertising
;
4304 spin_lock_irq(&np
->lock
);
4305 cmd
->base
.port
= PORT_MII
;
4306 if (!netif_running(dev
)) {
4307 /* We do not track link speed / duplex setting if the
4308 * interface is disabled. Force a link check */
4309 if (nv_update_linkspeed(dev
)) {
4310 netif_carrier_on(dev
);
4312 netif_carrier_off(dev
);
4316 if (netif_carrier_ok(dev
)) {
4317 switch (np
->linkspeed
& (NVREG_LINKSPEED_MASK
)) {
4318 case NVREG_LINKSPEED_10
:
4321 case NVREG_LINKSPEED_100
:
4324 case NVREG_LINKSPEED_1000
:
4331 cmd
->base
.duplex
= DUPLEX_HALF
;
4333 cmd
->base
.duplex
= DUPLEX_FULL
;
4335 speed
= SPEED_UNKNOWN
;
4336 cmd
->base
.duplex
= DUPLEX_UNKNOWN
;
4338 cmd
->base
.speed
= speed
;
4339 cmd
->base
.autoneg
= np
->autoneg
;
4341 advertising
= ADVERTISED_MII
;
4343 advertising
|= ADVERTISED_Autoneg
;
4344 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4345 if (adv
& ADVERTISE_10HALF
)
4346 advertising
|= ADVERTISED_10baseT_Half
;
4347 if (adv
& ADVERTISE_10FULL
)
4348 advertising
|= ADVERTISED_10baseT_Full
;
4349 if (adv
& ADVERTISE_100HALF
)
4350 advertising
|= ADVERTISED_100baseT_Half
;
4351 if (adv
& ADVERTISE_100FULL
)
4352 advertising
|= ADVERTISED_100baseT_Full
;
4353 if (np
->gigabit
== PHY_GIGABIT
) {
4354 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4355 if (adv
& ADVERTISE_1000FULL
)
4356 advertising
|= ADVERTISED_1000baseT_Full
;
4359 supported
= (SUPPORTED_Autoneg
|
4360 SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
4361 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
4363 if (np
->gigabit
== PHY_GIGABIT
)
4364 supported
|= SUPPORTED_1000baseT_Full
;
4366 cmd
->base
.phy_address
= np
->phyaddr
;
4368 ethtool_convert_legacy_u32_to_link_mode(cmd
->link_modes
.supported
,
4370 ethtool_convert_legacy_u32_to_link_mode(cmd
->link_modes
.advertising
,
4373 /* ignore maxtxpkt, maxrxpkt for now */
4374 spin_unlock_irq(&np
->lock
);
4378 static int nv_set_link_ksettings(struct net_device
*dev
,
4379 const struct ethtool_link_ksettings
*cmd
)
4381 struct fe_priv
*np
= netdev_priv(dev
);
4382 u32 speed
= cmd
->base
.speed
;
4385 ethtool_convert_link_mode_to_legacy_u32(&advertising
,
4386 cmd
->link_modes
.advertising
);
4388 if (cmd
->base
.port
!= PORT_MII
)
4390 if (cmd
->base
.phy_address
!= np
->phyaddr
) {
4391 /* TODO: support switching between multiple phys. Should be
4392 * trivial, but not enabled due to lack of test hardware. */
4395 if (cmd
->base
.autoneg
== AUTONEG_ENABLE
) {
4398 mask
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4399 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
4400 if (np
->gigabit
== PHY_GIGABIT
)
4401 mask
|= ADVERTISED_1000baseT_Full
;
4403 if ((advertising
& mask
) == 0)
4406 } else if (cmd
->base
.autoneg
== AUTONEG_DISABLE
) {
4407 /* Note: autonegotiation disable, speed 1000 intentionally
4408 * forbidden - no one should need that. */
4410 if (speed
!= SPEED_10
&& speed
!= SPEED_100
)
4412 if (cmd
->base
.duplex
!= DUPLEX_HALF
&&
4413 cmd
->base
.duplex
!= DUPLEX_FULL
)
4419 netif_carrier_off(dev
);
4420 if (netif_running(dev
)) {
4421 unsigned long flags
;
4423 nv_disable_irq(dev
);
4424 netif_tx_lock_bh(dev
);
4425 netif_addr_lock(dev
);
4426 /* with plain spinlock lockdep complains */
4427 spin_lock_irqsave(&np
->lock
, flags
);
4430 * this can take some time, and interrupts are disabled
4431 * due to spin_lock_irqsave, but let's hope no daemon
4432 * is going to change the settings very often...
4434 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4435 * + some minor delays, which is up to a second approximately
4438 spin_unlock_irqrestore(&np
->lock
, flags
);
4439 netif_addr_unlock(dev
);
4440 netif_tx_unlock_bh(dev
);
4443 if (cmd
->base
.autoneg
== AUTONEG_ENABLE
) {
4448 /* advertise only what has been requested */
4449 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4450 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4451 if (advertising
& ADVERTISED_10baseT_Half
)
4452 adv
|= ADVERTISE_10HALF
;
4453 if (advertising
& ADVERTISED_10baseT_Full
)
4454 adv
|= ADVERTISE_10FULL
;
4455 if (advertising
& ADVERTISED_100baseT_Half
)
4456 adv
|= ADVERTISE_100HALF
;
4457 if (advertising
& ADVERTISED_100baseT_Full
)
4458 adv
|= ADVERTISE_100FULL
;
4459 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisements but disable tx pause */
4460 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4461 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4462 adv
|= ADVERTISE_PAUSE_ASYM
;
4463 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4465 if (np
->gigabit
== PHY_GIGABIT
) {
4466 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4467 adv
&= ~ADVERTISE_1000FULL
;
4468 if (advertising
& ADVERTISED_1000baseT_Full
)
4469 adv
|= ADVERTISE_1000FULL
;
4470 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4473 if (netif_running(dev
))
4474 netdev_info(dev
, "link down\n");
4475 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4476 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4477 bmcr
|= BMCR_ANENABLE
;
4478 /* reset the phy in order for settings to stick,
4479 * and cause autoneg to start */
4480 if (phy_reset(dev
, bmcr
)) {
4481 netdev_info(dev
, "phy reset failed\n");
4485 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4486 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4493 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4494 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4495 if (speed
== SPEED_10
&& cmd
->base
.duplex
== DUPLEX_HALF
)
4496 adv
|= ADVERTISE_10HALF
;
4497 if (speed
== SPEED_10
&& cmd
->base
.duplex
== DUPLEX_FULL
)
4498 adv
|= ADVERTISE_10FULL
;
4499 if (speed
== SPEED_100
&& cmd
->base
.duplex
== DUPLEX_HALF
)
4500 adv
|= ADVERTISE_100HALF
;
4501 if (speed
== SPEED_100
&& cmd
->base
.duplex
== DUPLEX_FULL
)
4502 adv
|= ADVERTISE_100FULL
;
4503 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4504 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) {/* for rx we set both advertisements but disable tx pause */
4505 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4506 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4508 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
) {
4509 adv
|= ADVERTISE_PAUSE_ASYM
;
4510 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4512 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4513 np
->fixed_mode
= adv
;
4515 if (np
->gigabit
== PHY_GIGABIT
) {
4516 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4517 adv
&= ~ADVERTISE_1000FULL
;
4518 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4521 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4522 bmcr
&= ~(BMCR_ANENABLE
|BMCR_SPEED100
|BMCR_SPEED1000
|BMCR_FULLDPLX
);
4523 if (np
->fixed_mode
& (ADVERTISE_10FULL
|ADVERTISE_100FULL
))
4524 bmcr
|= BMCR_FULLDPLX
;
4525 if (np
->fixed_mode
& (ADVERTISE_100HALF
|ADVERTISE_100FULL
))
4526 bmcr
|= BMCR_SPEED100
;
4527 if (np
->phy_oui
== PHY_OUI_MARVELL
) {
4528 /* reset the phy in order for forced mode settings to stick */
4529 if (phy_reset(dev
, bmcr
)) {
4530 netdev_info(dev
, "phy reset failed\n");
4534 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4535 if (netif_running(dev
)) {
4536 /* Wait a bit and then reconfigure the nic. */
4543 if (netif_running(dev
)) {
4551 #define FORCEDETH_REGS_VER 1
4553 static int nv_get_regs_len(struct net_device
*dev
)
4555 struct fe_priv
*np
= netdev_priv(dev
);
4556 return np
->register_size
;
4559 static void nv_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *buf
)
4561 struct fe_priv
*np
= netdev_priv(dev
);
4562 u8 __iomem
*base
= get_hwbase(dev
);
4566 regs
->version
= FORCEDETH_REGS_VER
;
4567 spin_lock_irq(&np
->lock
);
4568 for (i
= 0; i
< np
->register_size
/sizeof(u32
); i
++)
4569 rbuf
[i
] = readl(base
+ i
*sizeof(u32
));
4570 spin_unlock_irq(&np
->lock
);
4573 static int nv_nway_reset(struct net_device
*dev
)
4575 struct fe_priv
*np
= netdev_priv(dev
);
4581 netif_carrier_off(dev
);
4582 if (netif_running(dev
)) {
4583 nv_disable_irq(dev
);
4584 netif_tx_lock_bh(dev
);
4585 netif_addr_lock(dev
);
4586 spin_lock(&np
->lock
);
4589 spin_unlock(&np
->lock
);
4590 netif_addr_unlock(dev
);
4591 netif_tx_unlock_bh(dev
);
4592 netdev_info(dev
, "link down\n");
4595 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4596 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4597 bmcr
|= BMCR_ANENABLE
;
4598 /* reset the phy in order for settings to stick*/
4599 if (phy_reset(dev
, bmcr
)) {
4600 netdev_info(dev
, "phy reset failed\n");
4604 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4605 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4608 if (netif_running(dev
)) {
4620 static void nv_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4622 struct fe_priv
*np
= netdev_priv(dev
);
4624 ring
->rx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4625 ring
->tx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4627 ring
->rx_pending
= np
->rx_ring_size
;
4628 ring
->tx_pending
= np
->tx_ring_size
;
4631 static int nv_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4633 struct fe_priv
*np
= netdev_priv(dev
);
4634 u8 __iomem
*base
= get_hwbase(dev
);
4635 u8
*rxtx_ring
, *rx_skbuff
, *tx_skbuff
;
4636 dma_addr_t ring_addr
;
4638 if (ring
->rx_pending
< RX_RING_MIN
||
4639 ring
->tx_pending
< TX_RING_MIN
||
4640 ring
->rx_mini_pending
!= 0 ||
4641 ring
->rx_jumbo_pending
!= 0 ||
4642 (np
->desc_ver
== DESC_VER_1
&&
4643 (ring
->rx_pending
> RING_MAX_DESC_VER_1
||
4644 ring
->tx_pending
> RING_MAX_DESC_VER_1
)) ||
4645 (np
->desc_ver
!= DESC_VER_1
&&
4646 (ring
->rx_pending
> RING_MAX_DESC_VER_2_3
||
4647 ring
->tx_pending
> RING_MAX_DESC_VER_2_3
))) {
4651 /* allocate new rings */
4652 if (!nv_optimized(np
)) {
4653 rxtx_ring
= dma_alloc_coherent(&np
->pci_dev
->dev
,
4654 sizeof(struct ring_desc
) *
4657 &ring_addr
, GFP_ATOMIC
);
4659 rxtx_ring
= dma_alloc_coherent(&np
->pci_dev
->dev
,
4660 sizeof(struct ring_desc_ex
) *
4663 &ring_addr
, GFP_ATOMIC
);
4665 rx_skbuff
= kmalloc_array(ring
->rx_pending
, sizeof(struct nv_skb_map
),
4667 tx_skbuff
= kmalloc_array(ring
->tx_pending
, sizeof(struct nv_skb_map
),
4669 if (!rxtx_ring
|| !rx_skbuff
|| !tx_skbuff
) {
4670 /* fall back to old rings */
4671 if (!nv_optimized(np
)) {
4673 dma_free_coherent(&np
->pci_dev
->dev
,
4674 sizeof(struct ring_desc
) *
4677 rxtx_ring
, ring_addr
);
4680 dma_free_coherent(&np
->pci_dev
->dev
,
4681 sizeof(struct ring_desc_ex
) *
4684 rxtx_ring
, ring_addr
);
4692 if (netif_running(dev
)) {
4693 nv_disable_irq(dev
);
4694 nv_napi_disable(dev
);
4695 netif_tx_lock_bh(dev
);
4696 netif_addr_lock(dev
);
4697 spin_lock(&np
->lock
);
4707 /* set new values */
4708 np
->rx_ring_size
= ring
->rx_pending
;
4709 np
->tx_ring_size
= ring
->tx_pending
;
4711 if (!nv_optimized(np
)) {
4712 np
->rx_ring
.orig
= (struct ring_desc
*)rxtx_ring
;
4713 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
4715 np
->rx_ring
.ex
= (struct ring_desc_ex
*)rxtx_ring
;
4716 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
4718 np
->rx_skb
= (struct nv_skb_map
*)rx_skbuff
;
4719 np
->tx_skb
= (struct nv_skb_map
*)tx_skbuff
;
4720 np
->ring_addr
= ring_addr
;
4722 memset(np
->rx_skb
, 0, sizeof(struct nv_skb_map
) * np
->rx_ring_size
);
4723 memset(np
->tx_skb
, 0, sizeof(struct nv_skb_map
) * np
->tx_ring_size
);
4725 if (netif_running(dev
)) {
4726 /* reinit driver view of the queues */
4728 if (nv_init_ring(dev
)) {
4729 if (!np
->in_shutdown
)
4730 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4733 /* reinit nic view of the queues */
4734 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4735 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4736 writel(((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4737 base
+ NvRegRingSizes
);
4739 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4742 /* restart engines */
4744 spin_unlock(&np
->lock
);
4745 netif_addr_unlock(dev
);
4746 netif_tx_unlock_bh(dev
);
4747 nv_napi_enable(dev
);
4755 static void nv_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4757 struct fe_priv
*np
= netdev_priv(dev
);
4759 pause
->autoneg
= (np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) != 0;
4760 pause
->rx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) != 0;
4761 pause
->tx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) != 0;
4764 static int nv_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4766 struct fe_priv
*np
= netdev_priv(dev
);
4769 if ((!np
->autoneg
&& np
->duplex
== 0) ||
4770 (np
->autoneg
&& !pause
->autoneg
&& np
->duplex
== 0)) {
4771 netdev_info(dev
, "can not set pause settings when forced link is in half duplex\n");
4774 if (pause
->tx_pause
&& !(np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)) {
4775 netdev_info(dev
, "hardware does not support tx pause frames\n");
4779 netif_carrier_off(dev
);
4780 if (netif_running(dev
)) {
4781 nv_disable_irq(dev
);
4782 netif_tx_lock_bh(dev
);
4783 netif_addr_lock(dev
);
4784 spin_lock(&np
->lock
);
4787 spin_unlock(&np
->lock
);
4788 netif_addr_unlock(dev
);
4789 netif_tx_unlock_bh(dev
);
4792 np
->pause_flags
&= ~(NV_PAUSEFRAME_RX_REQ
|NV_PAUSEFRAME_TX_REQ
);
4793 if (pause
->rx_pause
)
4794 np
->pause_flags
|= NV_PAUSEFRAME_RX_REQ
;
4795 if (pause
->tx_pause
)
4796 np
->pause_flags
|= NV_PAUSEFRAME_TX_REQ
;
4798 if (np
->autoneg
&& pause
->autoneg
) {
4799 np
->pause_flags
|= NV_PAUSEFRAME_AUTONEG
;
4801 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4802 adv
&= ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4803 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisements but disable tx pause */
4804 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4805 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4806 adv
|= ADVERTISE_PAUSE_ASYM
;
4807 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4809 if (netif_running(dev
))
4810 netdev_info(dev
, "link down\n");
4811 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4812 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4813 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4815 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4816 if (pause
->rx_pause
)
4817 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4818 if (pause
->tx_pause
)
4819 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4821 if (!netif_running(dev
))
4822 nv_update_linkspeed(dev
);
4824 nv_update_pause(dev
, np
->pause_flags
);
4827 if (netif_running(dev
)) {
4834 static int nv_set_loopback(struct net_device
*dev
, netdev_features_t features
)
4836 struct fe_priv
*np
= netdev_priv(dev
);
4837 unsigned long flags
;
4839 int err
, retval
= 0;
4841 spin_lock_irqsave(&np
->lock
, flags
);
4842 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4843 if (features
& NETIF_F_LOOPBACK
) {
4844 if (miicontrol
& BMCR_LOOPBACK
) {
4845 spin_unlock_irqrestore(&np
->lock
, flags
);
4846 netdev_info(dev
, "Loopback already enabled\n");
4849 nv_disable_irq(dev
);
4850 /* Turn on loopback mode */
4851 miicontrol
|= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
4852 err
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
);
4855 spin_unlock_irqrestore(&np
->lock
, flags
);
4858 if (netif_running(dev
)) {
4859 /* Force 1000 Mbps full-duplex */
4860 nv_force_linkspeed(dev
, NVREG_LINKSPEED_1000
,
4863 netif_carrier_on(dev
);
4865 spin_unlock_irqrestore(&np
->lock
, flags
);
4867 "Internal PHY loopback mode enabled.\n");
4870 if (!(miicontrol
& BMCR_LOOPBACK
)) {
4871 spin_unlock_irqrestore(&np
->lock
, flags
);
4872 netdev_info(dev
, "Loopback already disabled\n");
4875 nv_disable_irq(dev
);
4876 /* Turn off loopback */
4877 spin_unlock_irqrestore(&np
->lock
, flags
);
4878 netdev_info(dev
, "Internal PHY loopback mode disabled.\n");
4882 spin_lock_irqsave(&np
->lock
, flags
);
4884 spin_unlock_irqrestore(&np
->lock
, flags
);
4889 static netdev_features_t
nv_fix_features(struct net_device
*dev
,
4890 netdev_features_t features
)
4892 /* vlan is dependent on rx checksum offload */
4893 if (features
& (NETIF_F_HW_VLAN_CTAG_TX
|NETIF_F_HW_VLAN_CTAG_RX
))
4894 features
|= NETIF_F_RXCSUM
;
4899 static void nv_vlan_mode(struct net_device
*dev
, netdev_features_t features
)
4901 struct fe_priv
*np
= get_nvpriv(dev
);
4903 spin_lock_irq(&np
->lock
);
4905 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
4906 np
->txrxctl_bits
|= NVREG_TXRXCTL_VLANSTRIP
;
4908 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANSTRIP
;
4910 if (features
& NETIF_F_HW_VLAN_CTAG_TX
)
4911 np
->txrxctl_bits
|= NVREG_TXRXCTL_VLANINS
;
4913 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANINS
;
4915 writel(np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4917 spin_unlock_irq(&np
->lock
);
4920 static int nv_set_features(struct net_device
*dev
, netdev_features_t features
)
4922 struct fe_priv
*np
= netdev_priv(dev
);
4923 u8 __iomem
*base
= get_hwbase(dev
);
4924 netdev_features_t changed
= dev
->features
^ features
;
4927 if ((changed
& NETIF_F_LOOPBACK
) && netif_running(dev
)) {
4928 retval
= nv_set_loopback(dev
, features
);
4933 if (changed
& NETIF_F_RXCSUM
) {
4934 spin_lock_irq(&np
->lock
);
4936 if (features
& NETIF_F_RXCSUM
)
4937 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
4939 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_RXCHECK
;
4941 if (netif_running(dev
))
4942 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
4944 spin_unlock_irq(&np
->lock
);
4947 if (changed
& (NETIF_F_HW_VLAN_CTAG_TX
| NETIF_F_HW_VLAN_CTAG_RX
))
4948 nv_vlan_mode(dev
, features
);
4953 static int nv_get_sset_count(struct net_device
*dev
, int sset
)
4955 struct fe_priv
*np
= netdev_priv(dev
);
4959 if (np
->driver_data
& DEV_HAS_TEST_EXTENDED
)
4960 return NV_TEST_COUNT_EXTENDED
;
4962 return NV_TEST_COUNT_BASE
;
4964 if (np
->driver_data
& DEV_HAS_STATISTICS_V3
)
4965 return NV_DEV_STATISTICS_V3_COUNT
;
4966 else if (np
->driver_data
& DEV_HAS_STATISTICS_V2
)
4967 return NV_DEV_STATISTICS_V2_COUNT
;
4968 else if (np
->driver_data
& DEV_HAS_STATISTICS_V1
)
4969 return NV_DEV_STATISTICS_V1_COUNT
;
4977 static void nv_get_ethtool_stats(struct net_device
*dev
,
4978 struct ethtool_stats
*estats
, u64
*buffer
)
4979 __acquires(&netdev_priv(dev
)->hwstats_lock
)
4980 __releases(&netdev_priv(dev
)->hwstats_lock
)
4982 struct fe_priv
*np
= netdev_priv(dev
);
4984 spin_lock_bh(&np
->hwstats_lock
);
4985 nv_update_stats(dev
);
4986 memcpy(buffer
, &np
->estats
,
4987 nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(u64
));
4988 spin_unlock_bh(&np
->hwstats_lock
);
4991 static int nv_link_test(struct net_device
*dev
)
4993 struct fe_priv
*np
= netdev_priv(dev
);
4996 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4997 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4999 /* check phy link status */
5000 if (!(mii_status
& BMSR_LSTATUS
))
5006 static int nv_register_test(struct net_device
*dev
)
5008 u8 __iomem
*base
= get_hwbase(dev
);
5010 u32 orig_read
, new_read
;
5013 orig_read
= readl(base
+ nv_registers_test
[i
].reg
);
5015 /* xor with mask to toggle bits */
5016 orig_read
^= nv_registers_test
[i
].mask
;
5018 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
5020 new_read
= readl(base
+ nv_registers_test
[i
].reg
);
5022 if ((new_read
& nv_registers_test
[i
].mask
) != (orig_read
& nv_registers_test
[i
].mask
))
5025 /* restore original value */
5026 orig_read
^= nv_registers_test
[i
].mask
;
5027 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
5029 } while (nv_registers_test
[++i
].reg
!= 0);
5034 static int nv_interrupt_test(struct net_device
*dev
)
5036 struct fe_priv
*np
= netdev_priv(dev
);
5037 u8 __iomem
*base
= get_hwbase(dev
);
5040 u32 save_msi_flags
, save_poll_interval
= 0;
5042 if (netif_running(dev
)) {
5043 /* free current irq */
5045 save_poll_interval
= readl(base
+NvRegPollingInterval
);
5048 /* flag to test interrupt handler */
5051 /* setup test irq */
5052 save_msi_flags
= np
->msi_flags
;
5053 np
->msi_flags
&= ~NV_MSI_X_VECTORS_MASK
;
5054 np
->msi_flags
|= 0x001; /* setup 1 vector */
5055 if (nv_request_irq(dev
, 1))
5058 /* setup timer interrupt */
5059 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
5060 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
5062 nv_enable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
5064 /* wait for at least one interrupt */
5067 spin_lock_irq(&np
->lock
);
5069 /* flag should be set within ISR */
5070 testcnt
= np
->intr_test
;
5074 nv_disable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
5075 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
5076 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5078 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
5080 spin_unlock_irq(&np
->lock
);
5084 np
->msi_flags
= save_msi_flags
;
5086 if (netif_running(dev
)) {
5087 writel(save_poll_interval
, base
+ NvRegPollingInterval
);
5088 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
5089 /* restore original irq */
5090 if (nv_request_irq(dev
, 0))
5097 static int nv_loopback_test(struct net_device
*dev
)
5099 struct fe_priv
*np
= netdev_priv(dev
);
5100 u8 __iomem
*base
= get_hwbase(dev
);
5101 struct sk_buff
*tx_skb
, *rx_skb
;
5102 dma_addr_t test_dma_addr
;
5103 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
5105 int len
, i
, pkt_len
;
5107 u32 filter_flags
= 0;
5108 u32 misc1_flags
= 0;
5111 if (netif_running(dev
)) {
5112 nv_disable_irq(dev
);
5113 filter_flags
= readl(base
+ NvRegPacketFilterFlags
);
5114 misc1_flags
= readl(base
+ NvRegMisc1
);
5119 /* reinit driver view of the rx queue */
5123 /* setup hardware for loopback */
5124 writel(NVREG_MISC1_FORCE
, base
+ NvRegMisc1
);
5125 writel(NVREG_PFF_ALWAYS
| NVREG_PFF_LOOPBACK
, base
+ NvRegPacketFilterFlags
);
5127 /* reinit nic view of the rx queue */
5128 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5129 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5130 writel(((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5131 base
+ NvRegRingSizes
);
5134 /* restart rx engine */
5137 /* setup packet for tx */
5138 pkt_len
= ETH_DATA_LEN
;
5139 tx_skb
= netdev_alloc_skb(dev
, pkt_len
);
5144 test_dma_addr
= dma_map_single(&np
->pci_dev
->dev
, tx_skb
->data
,
5145 skb_tailroom(tx_skb
),
5147 if (unlikely(dma_mapping_error(&np
->pci_dev
->dev
,
5149 dev_kfree_skb_any(tx_skb
);
5152 pkt_data
= skb_put(tx_skb
, pkt_len
);
5153 for (i
= 0; i
< pkt_len
; i
++)
5154 pkt_data
[i
] = (u8
)(i
& 0xff);
5156 if (!nv_optimized(np
)) {
5157 np
->tx_ring
.orig
[0].buf
= cpu_to_le32(test_dma_addr
);
5158 np
->tx_ring
.orig
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
5160 np
->tx_ring
.ex
[0].bufhigh
= cpu_to_le32(dma_high(test_dma_addr
));
5161 np
->tx_ring
.ex
[0].buflow
= cpu_to_le32(dma_low(test_dma_addr
));
5162 np
->tx_ring
.ex
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
5164 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5165 pci_push(get_hwbase(dev
));
5169 /* check for rx of the packet */
5170 if (!nv_optimized(np
)) {
5171 flags
= le32_to_cpu(np
->rx_ring
.orig
[0].flaglen
);
5172 len
= nv_descr_getlength(&np
->rx_ring
.orig
[0], np
->desc_ver
);
5175 flags
= le32_to_cpu(np
->rx_ring
.ex
[0].flaglen
);
5176 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[0], np
->desc_ver
);
5179 if (flags
& NV_RX_AVAIL
) {
5181 } else if (np
->desc_ver
== DESC_VER_1
) {
5182 if (flags
& NV_RX_ERROR
)
5185 if (flags
& NV_RX2_ERROR
)
5190 if (len
!= pkt_len
) {
5193 rx_skb
= np
->rx_skb
[0].skb
;
5194 for (i
= 0; i
< pkt_len
; i
++) {
5195 if (rx_skb
->data
[i
] != (u8
)(i
& 0xff)) {
5203 dma_unmap_single(&np
->pci_dev
->dev
, test_dma_addr
,
5204 (skb_end_pointer(tx_skb
) - tx_skb
->data
),
5206 dev_kfree_skb_any(tx_skb
);
5211 /* drain rx queue */
5214 if (netif_running(dev
)) {
5215 writel(misc1_flags
, base
+ NvRegMisc1
);
5216 writel(filter_flags
, base
+ NvRegPacketFilterFlags
);
5223 static void nv_self_test(struct net_device
*dev
, struct ethtool_test
*test
, u64
*buffer
)
5225 struct fe_priv
*np
= netdev_priv(dev
);
5226 u8 __iomem
*base
= get_hwbase(dev
);
5229 count
= nv_get_sset_count(dev
, ETH_SS_TEST
);
5230 memset(buffer
, 0, count
* sizeof(u64
));
5232 if (!nv_link_test(dev
)) {
5233 test
->flags
|= ETH_TEST_FL_FAILED
;
5237 if (test
->flags
& ETH_TEST_FL_OFFLINE
) {
5238 if (netif_running(dev
)) {
5239 netif_stop_queue(dev
);
5240 nv_napi_disable(dev
);
5241 netif_tx_lock_bh(dev
);
5242 netif_addr_lock(dev
);
5243 spin_lock_irq(&np
->lock
);
5244 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5245 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
5246 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5248 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
5252 /* drain rx queue */
5254 spin_unlock_irq(&np
->lock
);
5255 netif_addr_unlock(dev
);
5256 netif_tx_unlock_bh(dev
);
5259 if (!nv_register_test(dev
)) {
5260 test
->flags
|= ETH_TEST_FL_FAILED
;
5264 result
= nv_interrupt_test(dev
);
5266 test
->flags
|= ETH_TEST_FL_FAILED
;
5274 if (count
> NV_TEST_COUNT_BASE
&& !nv_loopback_test(dev
)) {
5275 test
->flags
|= ETH_TEST_FL_FAILED
;
5279 if (netif_running(dev
)) {
5280 /* reinit driver view of the rx queue */
5282 if (nv_init_ring(dev
)) {
5283 if (!np
->in_shutdown
)
5284 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
5286 /* reinit nic view of the rx queue */
5287 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5288 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5289 writel(((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5290 base
+ NvRegRingSizes
);
5292 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5294 /* restart rx engine */
5296 netif_start_queue(dev
);
5297 nv_napi_enable(dev
);
5298 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5303 static void nv_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buffer
)
5305 switch (stringset
) {
5307 memcpy(buffer
, &nv_estats_str
, nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(struct nv_ethtool_str
));
5310 memcpy(buffer
, &nv_etests_str
, nv_get_sset_count(dev
, ETH_SS_TEST
)*sizeof(struct nv_ethtool_str
));
5315 static const struct ethtool_ops ops
= {
5316 .get_drvinfo
= nv_get_drvinfo
,
5317 .get_link
= ethtool_op_get_link
,
5318 .get_wol
= nv_get_wol
,
5319 .set_wol
= nv_set_wol
,
5320 .get_regs_len
= nv_get_regs_len
,
5321 .get_regs
= nv_get_regs
,
5322 .nway_reset
= nv_nway_reset
,
5323 .get_ringparam
= nv_get_ringparam
,
5324 .set_ringparam
= nv_set_ringparam
,
5325 .get_pauseparam
= nv_get_pauseparam
,
5326 .set_pauseparam
= nv_set_pauseparam
,
5327 .get_strings
= nv_get_strings
,
5328 .get_ethtool_stats
= nv_get_ethtool_stats
,
5329 .get_sset_count
= nv_get_sset_count
,
5330 .self_test
= nv_self_test
,
5331 .get_ts_info
= ethtool_op_get_ts_info
,
5332 .get_link_ksettings
= nv_get_link_ksettings
,
5333 .set_link_ksettings
= nv_set_link_ksettings
,
5336 /* The mgmt unit and driver use a semaphore to access the phy during init */
5337 static int nv_mgmt_acquire_sema(struct net_device
*dev
)
5339 struct fe_priv
*np
= netdev_priv(dev
);
5340 u8 __iomem
*base
= get_hwbase(dev
);
5342 u32 tx_ctrl
, mgmt_sema
;
5344 for (i
= 0; i
< 10; i
++) {
5345 mgmt_sema
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_SEMA_MASK
;
5346 if (mgmt_sema
== NVREG_XMITCTL_MGMT_SEMA_FREE
)
5351 if (mgmt_sema
!= NVREG_XMITCTL_MGMT_SEMA_FREE
)
5354 for (i
= 0; i
< 2; i
++) {
5355 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5356 tx_ctrl
|= NVREG_XMITCTL_HOST_SEMA_ACQ
;
5357 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
5359 /* verify that semaphore was acquired */
5360 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5361 if (((tx_ctrl
& NVREG_XMITCTL_HOST_SEMA_MASK
) == NVREG_XMITCTL_HOST_SEMA_ACQ
) &&
5362 ((tx_ctrl
& NVREG_XMITCTL_MGMT_SEMA_MASK
) == NVREG_XMITCTL_MGMT_SEMA_FREE
)) {
5372 static void nv_mgmt_release_sema(struct net_device
*dev
)
5374 struct fe_priv
*np
= netdev_priv(dev
);
5375 u8 __iomem
*base
= get_hwbase(dev
);
5378 if (np
->driver_data
& DEV_HAS_MGMT_UNIT
) {
5379 if (np
->mgmt_sema
) {
5380 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5381 tx_ctrl
&= ~NVREG_XMITCTL_HOST_SEMA_ACQ
;
5382 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
5388 static int nv_mgmt_get_version(struct net_device
*dev
)
5390 struct fe_priv
*np
= netdev_priv(dev
);
5391 u8 __iomem
*base
= get_hwbase(dev
);
5392 u32 data_ready
= readl(base
+ NvRegTransmitterControl
);
5393 u32 data_ready2
= 0;
5394 unsigned long start
;
5397 writel(NVREG_MGMTUNITGETVERSION
, base
+ NvRegMgmtUnitGetVersion
);
5398 writel(data_ready
^ NVREG_XMITCTL_DATA_START
, base
+ NvRegTransmitterControl
);
5400 while (time_before(jiffies
, start
+ 5*HZ
)) {
5401 data_ready2
= readl(base
+ NvRegTransmitterControl
);
5402 if ((data_ready
& NVREG_XMITCTL_DATA_READY
) != (data_ready2
& NVREG_XMITCTL_DATA_READY
)) {
5406 schedule_timeout_uninterruptible(1);
5409 if (!ready
|| (data_ready2
& NVREG_XMITCTL_DATA_ERROR
))
5412 np
->mgmt_version
= readl(base
+ NvRegMgmtUnitVersion
) & NVREG_MGMTUNITVERSION
;
5417 static int nv_open(struct net_device
*dev
)
5419 struct fe_priv
*np
= netdev_priv(dev
);
5420 u8 __iomem
*base
= get_hwbase(dev
);
5426 mii_rw(dev
, np
->phyaddr
, MII_BMCR
,
5427 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
) & ~BMCR_PDOWN
);
5429 nv_txrx_gate(dev
, false);
5430 /* erase previous misconfiguration */
5431 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
5433 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5434 writel(0, base
+ NvRegMulticastAddrB
);
5435 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5436 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5437 writel(0, base
+ NvRegPacketFilterFlags
);
5439 writel(0, base
+ NvRegTransmitterControl
);
5440 writel(0, base
+ NvRegReceiverControl
);
5442 writel(0, base
+ NvRegAdapterControl
);
5444 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)
5445 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
5447 /* initialize descriptor rings */
5449 oom
= nv_init_ring(dev
);
5451 writel(0, base
+ NvRegLinkSpeed
);
5452 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5454 writel(0, base
+ NvRegUnknownSetupReg6
);
5456 np
->in_shutdown
= 0;
5459 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5460 writel(((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5461 base
+ NvRegRingSizes
);
5463 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
5464 if (np
->desc_ver
== DESC_VER_1
)
5465 writel(NVREG_TX_WM_DESC1_DEFAULT
, base
+ NvRegTxWatermark
);
5467 writel(NVREG_TX_WM_DESC2_3_DEFAULT
, base
+ NvRegTxWatermark
);
5468 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5469 writel(np
->vlanctl_bits
, base
+ NvRegVlanControl
);
5471 writel(NVREG_TXRXCTL_BIT1
|np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5472 if (reg_delay(dev
, NvRegUnknownSetupReg5
,
5473 NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
5474 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
))
5476 "%s: SetupReg5, Bit 31 remained off\n", __func__
);
5478 writel(0, base
+ NvRegMIIMask
);
5479 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5480 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5482 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
5483 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
5484 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
5485 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5487 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
5489 get_random_bytes(&low
, sizeof(low
));
5490 low
&= NVREG_SLOTTIME_MASK
;
5491 if (np
->desc_ver
== DESC_VER_1
) {
5492 writel(low
|NVREG_SLOTTIME_DEFAULT
, base
+ NvRegSlotTime
);
5494 if (!(np
->driver_data
& DEV_HAS_GEAR_MODE
)) {
5495 /* setup legacy backoff */
5496 writel(NVREG_SLOTTIME_LEGBF_ENABLED
|NVREG_SLOTTIME_10_100_FULL
|low
, base
+ NvRegSlotTime
);
5498 writel(NVREG_SLOTTIME_10_100_FULL
, base
+ NvRegSlotTime
);
5499 nv_gear_backoff_reseed(dev
);
5502 writel(NVREG_TX_DEFERRAL_DEFAULT
, base
+ NvRegTxDeferral
);
5503 writel(NVREG_RX_DEFERRAL_DEFAULT
, base
+ NvRegRxDeferral
);
5504 if (poll_interval
== -1) {
5505 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
)
5506 writel(NVREG_POLL_DEFAULT_THROUGHPUT
, base
+ NvRegPollingInterval
);
5508 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
5510 writel(poll_interval
& 0xFFFF, base
+ NvRegPollingInterval
);
5511 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
5512 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
5513 base
+ NvRegAdapterControl
);
5514 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
5515 writel(NVREG_MII_LINKCHANGE
, base
+ NvRegMIIMask
);
5517 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
5519 i
= readl(base
+ NvRegPowerState
);
5520 if ((i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
5521 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
5525 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
5527 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5529 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5530 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5533 if (nv_request_irq(dev
, 0))
5536 /* ask for interrupts */
5537 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5539 spin_lock_irq(&np
->lock
);
5540 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5541 writel(0, base
+ NvRegMulticastAddrB
);
5542 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5543 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5544 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5545 /* One manual link speed update: Interrupts are enabled, future link
5546 * speed changes cause interrupts and are handled by nv_link_irq().
5548 readl(base
+ NvRegMIIStatus
);
5549 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5551 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5554 ret
= nv_update_linkspeed(dev
);
5556 netif_start_queue(dev
);
5557 nv_napi_enable(dev
);
5560 netif_carrier_on(dev
);
5562 netdev_info(dev
, "no link during initialization\n");
5563 netif_carrier_off(dev
);
5566 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
5568 /* start statistics timer */
5569 if (np
->driver_data
& (DEV_HAS_STATISTICS_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_STATISTICS_V3
))
5570 mod_timer(&np
->stats_poll
,
5571 round_jiffies(jiffies
+ STATS_INTERVAL
));
5573 spin_unlock_irq(&np
->lock
);
5575 /* If the loopback feature was set while the device was down, make sure
5576 * that it's set correctly now.
5578 if (dev
->features
& NETIF_F_LOOPBACK
)
5579 nv_set_loopback(dev
, dev
->features
);
5587 static int nv_close(struct net_device
*dev
)
5589 struct fe_priv
*np
= netdev_priv(dev
);
5592 spin_lock_irq(&np
->lock
);
5593 np
->in_shutdown
= 1;
5594 spin_unlock_irq(&np
->lock
);
5595 nv_napi_disable(dev
);
5596 synchronize_irq(np
->pci_dev
->irq
);
5598 del_timer_sync(&np
->oom_kick
);
5599 del_timer_sync(&np
->nic_poll
);
5600 del_timer_sync(&np
->stats_poll
);
5602 netif_stop_queue(dev
);
5603 spin_lock_irq(&np
->lock
);
5604 nv_update_pause(dev
, 0); /* otherwise stop_tx bricks NIC */
5608 /* disable interrupts on the nic or we will lock up */
5609 base
= get_hwbase(dev
);
5610 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5613 spin_unlock_irq(&np
->lock
);
5619 if (np
->wolenabled
|| !phy_power_down
) {
5620 nv_txrx_gate(dev
, false);
5621 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5624 /* power down phy */
5625 mii_rw(dev
, np
->phyaddr
, MII_BMCR
,
5626 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
)|BMCR_PDOWN
);
5627 nv_txrx_gate(dev
, true);
5630 /* FIXME: power down nic */
5635 static const struct net_device_ops nv_netdev_ops
= {
5636 .ndo_open
= nv_open
,
5637 .ndo_stop
= nv_close
,
5638 .ndo_get_stats64
= nv_get_stats64
,
5639 .ndo_start_xmit
= nv_start_xmit
,
5640 .ndo_tx_timeout
= nv_tx_timeout
,
5641 .ndo_change_mtu
= nv_change_mtu
,
5642 .ndo_fix_features
= nv_fix_features
,
5643 .ndo_set_features
= nv_set_features
,
5644 .ndo_validate_addr
= eth_validate_addr
,
5645 .ndo_set_mac_address
= nv_set_mac_address
,
5646 .ndo_set_rx_mode
= nv_set_multicast
,
5647 #ifdef CONFIG_NET_POLL_CONTROLLER
5648 .ndo_poll_controller
= nv_poll_controller
,
5652 static const struct net_device_ops nv_netdev_ops_optimized
= {
5653 .ndo_open
= nv_open
,
5654 .ndo_stop
= nv_close
,
5655 .ndo_get_stats64
= nv_get_stats64
,
5656 .ndo_start_xmit
= nv_start_xmit_optimized
,
5657 .ndo_tx_timeout
= nv_tx_timeout
,
5658 .ndo_change_mtu
= nv_change_mtu
,
5659 .ndo_fix_features
= nv_fix_features
,
5660 .ndo_set_features
= nv_set_features
,
5661 .ndo_validate_addr
= eth_validate_addr
,
5662 .ndo_set_mac_address
= nv_set_mac_address
,
5663 .ndo_set_rx_mode
= nv_set_multicast
,
5664 #ifdef CONFIG_NET_POLL_CONTROLLER
5665 .ndo_poll_controller
= nv_poll_controller
,
5669 static int nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
5671 struct net_device
*dev
;
5676 u32 powerstate
, txreg
;
5677 u32 phystate_orig
= 0, phystate
;
5678 int phyinitialized
= 0;
5679 static int printed_version
;
5681 if (!printed_version
++)
5682 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5685 dev
= alloc_etherdev(sizeof(struct fe_priv
));
5690 np
= netdev_priv(dev
);
5692 np
->pci_dev
= pci_dev
;
5693 spin_lock_init(&np
->lock
);
5694 spin_lock_init(&np
->hwstats_lock
);
5695 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
5696 u64_stats_init(&np
->swstats_rx_syncp
);
5697 u64_stats_init(&np
->swstats_tx_syncp
);
5698 np
->txrx_stats
= alloc_percpu(struct nv_txrx_stats
);
5699 if (!np
->txrx_stats
) {
5700 pr_err("np->txrx_stats, alloc memory error.\n");
5702 goto out_alloc_percpu
;
5705 timer_setup(&np
->oom_kick
, nv_do_rx_refill
, 0);
5706 timer_setup(&np
->nic_poll
, nv_do_nic_poll
, 0);
5707 timer_setup(&np
->stats_poll
, nv_do_stats_poll
, TIMER_DEFERRABLE
);
5709 err
= pci_enable_device(pci_dev
);
5713 pci_set_master(pci_dev
);
5715 err
= pci_request_regions(pci_dev
, DRV_NAME
);
5719 if (id
->driver_data
& (DEV_HAS_VLAN
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V2
|DEV_HAS_STATISTICS_V3
))
5720 np
->register_size
= NV_PCI_REGSZ_VER3
;
5721 else if (id
->driver_data
& DEV_HAS_STATISTICS_V1
)
5722 np
->register_size
= NV_PCI_REGSZ_VER2
;
5724 np
->register_size
= NV_PCI_REGSZ_VER1
;
5728 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
5729 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
5730 pci_resource_len(pci_dev
, i
) >= np
->register_size
) {
5731 addr
= pci_resource_start(pci_dev
, i
);
5735 if (i
== DEVICE_COUNT_RESOURCE
) {
5736 dev_info(&pci_dev
->dev
, "Couldn't find register window\n");
5740 /* copy of driver data */
5741 np
->driver_data
= id
->driver_data
;
5742 /* copy of device id */
5743 np
->device_id
= id
->device
;
5745 /* handle different descriptor versions */
5746 if (id
->driver_data
& DEV_HAS_HIGH_DMA
) {
5747 /* packet format 3: supports 40-bit addressing */
5748 np
->desc_ver
= DESC_VER_3
;
5749 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_3
;
5751 if (pci_set_dma_mask(pci_dev
, DMA_BIT_MASK(39)))
5752 dev_info(&pci_dev
->dev
,
5753 "64-bit DMA failed, using 32-bit addressing\n");
5755 dev
->features
|= NETIF_F_HIGHDMA
;
5756 if (pci_set_consistent_dma_mask(pci_dev
, DMA_BIT_MASK(39))) {
5757 dev_info(&pci_dev
->dev
,
5758 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5761 } else if (id
->driver_data
& DEV_HAS_LARGEDESC
) {
5762 /* packet format 2: supports jumbo frames */
5763 np
->desc_ver
= DESC_VER_2
;
5764 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_2
;
5766 /* original packet format */
5767 np
->desc_ver
= DESC_VER_1
;
5768 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_1
;
5771 np
->pkt_limit
= NV_PKTLIMIT_1
;
5772 if (id
->driver_data
& DEV_HAS_LARGEDESC
)
5773 np
->pkt_limit
= NV_PKTLIMIT_2
;
5775 if (id
->driver_data
& DEV_HAS_CHECKSUM
) {
5776 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
5777 dev
->hw_features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
|
5778 NETIF_F_TSO
| NETIF_F_RXCSUM
;
5781 np
->vlanctl_bits
= 0;
5782 if (id
->driver_data
& DEV_HAS_VLAN
) {
5783 np
->vlanctl_bits
= NVREG_VLANCONTROL_ENABLE
;
5784 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
|
5785 NETIF_F_HW_VLAN_CTAG_TX
;
5788 dev
->features
|= dev
->hw_features
;
5790 /* Add loopback capability to the device. */
5791 dev
->hw_features
|= NETIF_F_LOOPBACK
;
5793 /* MTU range: 64 - 1500 or 9100 */
5794 dev
->min_mtu
= ETH_ZLEN
+ ETH_FCS_LEN
;
5795 dev
->max_mtu
= np
->pkt_limit
;
5797 np
->pause_flags
= NV_PAUSEFRAME_RX_CAPABLE
| NV_PAUSEFRAME_RX_REQ
| NV_PAUSEFRAME_AUTONEG
;
5798 if ((id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V1
) ||
5799 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
) ||
5800 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
)) {
5801 np
->pause_flags
|= NV_PAUSEFRAME_TX_CAPABLE
| NV_PAUSEFRAME_TX_REQ
;
5805 np
->base
= ioremap(addr
, np
->register_size
);
5809 np
->rx_ring_size
= RX_RING_DEFAULT
;
5810 np
->tx_ring_size
= TX_RING_DEFAULT
;
5812 if (!nv_optimized(np
)) {
5813 np
->rx_ring
.orig
= dma_alloc_coherent(&pci_dev
->dev
,
5814 sizeof(struct ring_desc
) *
5819 if (!np
->rx_ring
.orig
)
5821 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
5823 np
->rx_ring
.ex
= dma_alloc_coherent(&pci_dev
->dev
,
5824 sizeof(struct ring_desc_ex
) *
5827 &np
->ring_addr
, GFP_KERNEL
);
5828 if (!np
->rx_ring
.ex
)
5830 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
5832 np
->rx_skb
= kcalloc(np
->rx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5833 np
->tx_skb
= kcalloc(np
->tx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5834 if (!np
->rx_skb
|| !np
->tx_skb
)
5837 if (!nv_optimized(np
))
5838 dev
->netdev_ops
= &nv_netdev_ops
;
5840 dev
->netdev_ops
= &nv_netdev_ops_optimized
;
5842 netif_napi_add(dev
, &np
->napi
, nv_napi_poll
, RX_WORK_PER_LOOP
);
5843 dev
->ethtool_ops
= &ops
;
5844 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
5846 pci_set_drvdata(pci_dev
, dev
);
5848 /* read the mac address */
5849 base
= get_hwbase(dev
);
5850 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
5851 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
5853 /* check the workaround bit for correct mac address order */
5854 txreg
= readl(base
+ NvRegTransmitPoll
);
5855 if (id
->driver_data
& DEV_HAS_CORRECT_MACADDR
) {
5856 /* mac address is already in correct order */
5857 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5858 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5859 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5860 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5861 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5862 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5863 } else if (txreg
& NVREG_TRANSMITPOLL_MAC_ADDR_REV
) {
5864 /* mac address is already in correct order */
5865 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5866 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5867 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5868 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5869 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5870 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5872 * Set orig mac address back to the reversed version.
5873 * This flag will be cleared during low power transition.
5874 * Therefore, we should always put back the reversed address.
5876 np
->orig_mac
[0] = (dev
->dev_addr
[5] << 0) + (dev
->dev_addr
[4] << 8) +
5877 (dev
->dev_addr
[3] << 16) + (dev
->dev_addr
[2] << 24);
5878 np
->orig_mac
[1] = (dev
->dev_addr
[1] << 0) + (dev
->dev_addr
[0] << 8);
5880 /* need to reverse mac address to correct order */
5881 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
5882 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
5883 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
5884 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
5885 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
5886 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
5887 writel(txreg
|NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5888 dev_dbg(&pci_dev
->dev
,
5889 "%s: set workaround bit for reversed mac addr\n",
5893 if (!is_valid_ether_addr(dev
->dev_addr
)) {
5895 * Bad mac address. At least one bios sets the mac address
5896 * to 01:23:45:67:89:ab
5898 dev_err(&pci_dev
->dev
,
5899 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5901 eth_hw_addr_random(dev
);
5902 dev_err(&pci_dev
->dev
,
5903 "Using random MAC address: %pM\n", dev
->dev_addr
);
5906 /* set mac address */
5907 nv_copy_mac_to_hw(dev
);
5910 writel(0, base
+ NvRegWakeUpFlags
);
5912 device_set_wakeup_enable(&pci_dev
->dev
, false);
5914 if (id
->driver_data
& DEV_HAS_POWER_CNTRL
) {
5916 /* take phy and nic out of low power mode */
5917 powerstate
= readl(base
+ NvRegPowerState2
);
5918 powerstate
&= ~NVREG_POWERSTATE2_POWERUP_MASK
;
5919 if ((id
->driver_data
& DEV_NEED_LOW_POWER_FIX
) &&
5920 pci_dev
->revision
>= 0xA3)
5921 powerstate
|= NVREG_POWERSTATE2_POWERUP_REV_A3
;
5922 writel(powerstate
, base
+ NvRegPowerState2
);
5925 if (np
->desc_ver
== DESC_VER_1
)
5926 np
->tx_flags
= NV_TX_VALID
;
5928 np
->tx_flags
= NV_TX2_VALID
;
5931 if ((id
->driver_data
& DEV_HAS_MSI
) && msi
)
5932 np
->msi_flags
|= NV_MSI_CAPABLE
;
5934 if ((id
->driver_data
& DEV_HAS_MSI_X
) && msix
) {
5935 /* msix has had reported issues when modifying irqmask
5936 as in the case of napi, therefore, disable for now
5939 np
->msi_flags
|= NV_MSI_X_CAPABLE
;
5943 if (optimization_mode
== NV_OPTIMIZATION_MODE_CPU
) {
5944 np
->irqmask
= NVREG_IRQMASK_CPU
;
5945 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5946 np
->msi_flags
|= 0x0001;
5947 } else if (optimization_mode
== NV_OPTIMIZATION_MODE_DYNAMIC
&&
5948 !(id
->driver_data
& DEV_NEED_TIMERIRQ
)) {
5949 /* start off in throughput mode */
5950 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
5951 /* remove support for msix mode */
5952 np
->msi_flags
&= ~NV_MSI_X_CAPABLE
;
5954 optimization_mode
= NV_OPTIMIZATION_MODE_THROUGHPUT
;
5955 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
5956 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5957 np
->msi_flags
|= 0x0003;
5960 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
5961 np
->irqmask
|= NVREG_IRQ_TIMER
;
5962 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
5963 np
->need_linktimer
= 1;
5964 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
5966 np
->need_linktimer
= 0;
5969 /* Limit the number of tx's outstanding for hw bug */
5970 if (id
->driver_data
& DEV_NEED_TX_LIMIT
) {
5972 if (((id
->driver_data
& DEV_NEED_TX_LIMIT2
) == DEV_NEED_TX_LIMIT2
) &&
5973 pci_dev
->revision
>= 0xA2)
5977 /* clear phy state and temporarily halt phy interrupts */
5978 writel(0, base
+ NvRegMIIMask
);
5979 phystate
= readl(base
+ NvRegAdapterControl
);
5980 if (phystate
& NVREG_ADAPTCTL_RUNNING
) {
5982 phystate
&= ~NVREG_ADAPTCTL_RUNNING
;
5983 writel(phystate
, base
+ NvRegAdapterControl
);
5985 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5987 if (id
->driver_data
& DEV_HAS_MGMT_UNIT
) {
5988 /* management unit running on the mac? */
5989 if ((readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_ST
) &&
5990 (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_PHY_INIT
) &&
5991 nv_mgmt_acquire_sema(dev
) &&
5992 nv_mgmt_get_version(dev
)) {
5994 if (np
->mgmt_version
> 0)
5995 np
->mac_in_use
= readl(base
+ NvRegMgmtUnitControl
) & NVREG_MGMTUNITCONTROL_INUSE
;
5996 /* management unit setup the phy already? */
5997 if (np
->mac_in_use
&&
5998 ((readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_MASK
) ==
5999 NVREG_XMITCTL_SYNC_PHY_INIT
)) {
6000 /* phy is inited by mgmt unit */
6003 /* we need to init the phy */
6008 /* find a suitable phy */
6009 for (i
= 1; i
<= 32; i
++) {
6011 int phyaddr
= i
& 0x1F;
6013 spin_lock_irq(&np
->lock
);
6014 id1
= mii_rw(dev
, phyaddr
, MII_PHYSID1
, MII_READ
);
6015 spin_unlock_irq(&np
->lock
);
6016 if (id1
< 0 || id1
== 0xffff)
6018 spin_lock_irq(&np
->lock
);
6019 id2
= mii_rw(dev
, phyaddr
, MII_PHYSID2
, MII_READ
);
6020 spin_unlock_irq(&np
->lock
);
6021 if (id2
< 0 || id2
== 0xffff)
6024 np
->phy_model
= id2
& PHYID2_MODEL_MASK
;
6025 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
6026 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
6027 np
->phyaddr
= phyaddr
;
6028 np
->phy_oui
= id1
| id2
;
6030 /* Realtek hardcoded phy id1 to all zero's on certain phys */
6031 if (np
->phy_oui
== PHY_OUI_REALTEK2
)
6032 np
->phy_oui
= PHY_OUI_REALTEK
;
6033 /* Setup phy revision for Realtek */
6034 if (np
->phy_oui
== PHY_OUI_REALTEK
&& np
->phy_model
== PHY_MODEL_REALTEK_8211
)
6035 np
->phy_rev
= mii_rw(dev
, phyaddr
, MII_RESV1
, MII_READ
) & PHY_REV_MASK
;
6040 dev_info(&pci_dev
->dev
, "open: Could not find a valid PHY\n");
6044 if (!phyinitialized
) {
6048 /* see if it is a gigabit phy */
6049 u32 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
6050 if (mii_status
& PHY_GIGABIT
)
6051 np
->gigabit
= PHY_GIGABIT
;
6054 /* set default link speed settings */
6055 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
6059 err
= register_netdev(dev
);
6061 dev_info(&pci_dev
->dev
, "unable to register netdev: %d\n", err
);
6065 netif_carrier_off(dev
);
6067 /* Some NICs freeze when TX pause is enabled while NIC is
6068 * down, and this stays across warm reboots. The sequence
6069 * below should be enough to recover from that state.
6071 nv_update_pause(dev
, 0);
6075 if (id
->driver_data
& DEV_HAS_VLAN
)
6076 nv_vlan_mode(dev
, dev
->features
);
6078 dev_info(&pci_dev
->dev
, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
6079 dev
->name
, np
->phy_oui
, np
->phyaddr
, dev
->dev_addr
);
6081 dev_info(&pci_dev
->dev
, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
6082 dev
->features
& NETIF_F_HIGHDMA
? "highdma " : "",
6083 dev
->features
& (NETIF_F_IP_CSUM
| NETIF_F_SG
) ?
6085 dev
->features
& (NETIF_F_HW_VLAN_CTAG_RX
|
6086 NETIF_F_HW_VLAN_CTAG_TX
) ?
6088 dev
->features
& (NETIF_F_LOOPBACK
) ?
6090 id
->driver_data
& DEV_HAS_POWER_CNTRL
? "pwrctl " : "",
6091 id
->driver_data
& DEV_HAS_MGMT_UNIT
? "mgmt " : "",
6092 id
->driver_data
& DEV_NEED_TIMERIRQ
? "timirq " : "",
6093 np
->gigabit
== PHY_GIGABIT
? "gbit " : "",
6094 np
->need_linktimer
? "lnktim " : "",
6095 np
->msi_flags
& NV_MSI_CAPABLE
? "msi " : "",
6096 np
->msi_flags
& NV_MSI_X_CAPABLE
? "msi-x " : "",
6103 writel(phystate
|NVREG_ADAPTCTL_RUNNING
, base
+ NvRegAdapterControl
);
6107 iounmap(get_hwbase(dev
));
6109 pci_release_regions(pci_dev
);
6111 pci_disable_device(pci_dev
);
6113 free_percpu(np
->txrx_stats
);
6120 static void nv_restore_phy(struct net_device
*dev
)
6122 struct fe_priv
*np
= netdev_priv(dev
);
6123 u16 phy_reserved
, mii_control
;
6125 if (np
->phy_oui
== PHY_OUI_REALTEK
&&
6126 np
->phy_model
== PHY_MODEL_REALTEK_8201
&&
6127 phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
6128 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
);
6129 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, MII_READ
);
6130 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
6131 phy_reserved
|= PHY_REALTEK_INIT8
;
6132 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, phy_reserved
);
6133 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
);
6135 /* restart auto negotiation */
6136 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
6137 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
6138 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
);
6142 static void nv_restore_mac_addr(struct pci_dev
*pci_dev
)
6144 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
6145 struct fe_priv
*np
= netdev_priv(dev
);
6146 u8 __iomem
*base
= get_hwbase(dev
);
6148 /* special op: write back the misordered MAC address - otherwise
6149 * the next nv_probe would see a wrong address.
6151 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
6152 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
6153 writel(readl(base
+ NvRegTransmitPoll
) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
6154 base
+ NvRegTransmitPoll
);
6157 static void nv_remove(struct pci_dev
*pci_dev
)
6159 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
6160 struct fe_priv
*np
= netdev_priv(dev
);
6162 free_percpu(np
->txrx_stats
);
6164 unregister_netdev(dev
);
6166 nv_restore_mac_addr(pci_dev
);
6168 /* restore any phy related changes */
6169 nv_restore_phy(dev
);
6171 nv_mgmt_release_sema(dev
);
6173 /* free all structures */
6175 iounmap(get_hwbase(dev
));
6176 pci_release_regions(pci_dev
);
6177 pci_disable_device(pci_dev
);
6181 #ifdef CONFIG_PM_SLEEP
6182 static int nv_suspend(struct device
*device
)
6184 struct net_device
*dev
= dev_get_drvdata(device
);
6185 struct fe_priv
*np
= netdev_priv(dev
);
6186 u8 __iomem
*base
= get_hwbase(dev
);
6189 if (netif_running(dev
)) {
6193 netif_device_detach(dev
);
6195 /* save non-pci configuration space */
6196 for (i
= 0; i
<= np
->register_size
/sizeof(u32
); i
++)
6197 np
->saved_config_space
[i
] = readl(base
+ i
*sizeof(u32
));
6202 static int nv_resume(struct device
*device
)
6204 struct pci_dev
*pdev
= to_pci_dev(device
);
6205 struct net_device
*dev
= pci_get_drvdata(pdev
);
6206 struct fe_priv
*np
= netdev_priv(dev
);
6207 u8 __iomem
*base
= get_hwbase(dev
);
6210 /* restore non-pci configuration space */
6211 for (i
= 0; i
<= np
->register_size
/sizeof(u32
); i
++)
6212 writel(np
->saved_config_space
[i
], base
+i
*sizeof(u32
));
6214 if (np
->driver_data
& DEV_NEED_MSI_FIX
)
6215 pci_write_config_dword(pdev
, NV_MSI_PRIV_OFFSET
, NV_MSI_PRIV_VALUE
);
6217 /* restore phy state, including autoneg */
6220 netif_device_attach(dev
);
6221 if (netif_running(dev
)) {
6223 nv_set_multicast(dev
);
6228 static SIMPLE_DEV_PM_OPS(nv_pm_ops
, nv_suspend
, nv_resume
);
6229 #define NV_PM_OPS (&nv_pm_ops)
6232 #define NV_PM_OPS NULL
6233 #endif /* CONFIG_PM_SLEEP */
6236 static void nv_shutdown(struct pci_dev
*pdev
)
6238 struct net_device
*dev
= pci_get_drvdata(pdev
);
6239 struct fe_priv
*np
= netdev_priv(dev
);
6241 if (netif_running(dev
))
6245 * Restore the MAC so a kernel started by kexec won't get confused.
6246 * If we really go for poweroff, we must not restore the MAC,
6247 * otherwise the MAC for WOL will be reversed at least on some boards.
6249 if (system_state
!= SYSTEM_POWER_OFF
)
6250 nv_restore_mac_addr(pdev
);
6252 pci_disable_device(pdev
);
6254 * Apparently it is not possible to reinitialise from D3 hot,
6255 * only put the device into D3 if we really go for poweroff.
6257 if (system_state
== SYSTEM_POWER_OFF
) {
6258 pci_wake_from_d3(pdev
, np
->wolenabled
);
6259 pci_set_power_state(pdev
, PCI_D3hot
);
6263 #define nv_shutdown NULL
6264 #endif /* CONFIG_PM */
6266 static const struct pci_device_id pci_tbl
[] = {
6267 { /* nForce Ethernet Controller */
6268 PCI_DEVICE(0x10DE, 0x01C3),
6269 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
6271 { /* nForce2 Ethernet Controller */
6272 PCI_DEVICE(0x10DE, 0x0066),
6273 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
6275 { /* nForce3 Ethernet Controller */
6276 PCI_DEVICE(0x10DE, 0x00D6),
6277 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
6279 { /* nForce3 Ethernet Controller */
6280 PCI_DEVICE(0x10DE, 0x0086),
6281 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6283 { /* nForce3 Ethernet Controller */
6284 PCI_DEVICE(0x10DE, 0x008C),
6285 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6287 { /* nForce3 Ethernet Controller */
6288 PCI_DEVICE(0x10DE, 0x00E6),
6289 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6291 { /* nForce3 Ethernet Controller */
6292 PCI_DEVICE(0x10DE, 0x00DF),
6293 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6295 { /* CK804 Ethernet Controller */
6296 PCI_DEVICE(0x10DE, 0x0056),
6297 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6299 { /* CK804 Ethernet Controller */
6300 PCI_DEVICE(0x10DE, 0x0057),
6301 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6303 { /* MCP04 Ethernet Controller */
6304 PCI_DEVICE(0x10DE, 0x0037),
6305 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6307 { /* MCP04 Ethernet Controller */
6308 PCI_DEVICE(0x10DE, 0x0038),
6309 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6311 { /* MCP51 Ethernet Controller */
6312 PCI_DEVICE(0x10DE, 0x0268),
6313 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
|DEV_NEED_LOW_POWER_FIX
,
6315 { /* MCP51 Ethernet Controller */
6316 PCI_DEVICE(0x10DE, 0x0269),
6317 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
|DEV_NEED_LOW_POWER_FIX
,
6319 { /* MCP55 Ethernet Controller */
6320 PCI_DEVICE(0x10DE, 0x0372),
6321 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
|DEV_NEED_MSI_FIX
,
6323 { /* MCP55 Ethernet Controller */
6324 PCI_DEVICE(0x10DE, 0x0373),
6325 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
|DEV_NEED_MSI_FIX
,
6327 { /* MCP61 Ethernet Controller */
6328 PCI_DEVICE(0x10DE, 0x03E5),
6329 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_MSI_FIX
,
6331 { /* MCP61 Ethernet Controller */
6332 PCI_DEVICE(0x10DE, 0x03E6),
6333 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_MSI_FIX
,
6335 { /* MCP61 Ethernet Controller */
6336 PCI_DEVICE(0x10DE, 0x03EE),
6337 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_MSI_FIX
,
6339 { /* MCP61 Ethernet Controller */
6340 PCI_DEVICE(0x10DE, 0x03EF),
6341 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_MSI_FIX
,
6343 { /* MCP65 Ethernet Controller */
6344 PCI_DEVICE(0x10DE, 0x0450),
6345 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6347 { /* MCP65 Ethernet Controller */
6348 PCI_DEVICE(0x10DE, 0x0451),
6349 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6351 { /* MCP65 Ethernet Controller */
6352 PCI_DEVICE(0x10DE, 0x0452),
6353 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6355 { /* MCP65 Ethernet Controller */
6356 PCI_DEVICE(0x10DE, 0x0453),
6357 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6359 { /* MCP67 Ethernet Controller */
6360 PCI_DEVICE(0x10DE, 0x054C),
6361 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6363 { /* MCP67 Ethernet Controller */
6364 PCI_DEVICE(0x10DE, 0x054D),
6365 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6367 { /* MCP67 Ethernet Controller */
6368 PCI_DEVICE(0x10DE, 0x054E),
6369 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6371 { /* MCP67 Ethernet Controller */
6372 PCI_DEVICE(0x10DE, 0x054F),
6373 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6375 { /* MCP73 Ethernet Controller */
6376 PCI_DEVICE(0x10DE, 0x07DC),
6377 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6379 { /* MCP73 Ethernet Controller */
6380 PCI_DEVICE(0x10DE, 0x07DD),
6381 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6383 { /* MCP73 Ethernet Controller */
6384 PCI_DEVICE(0x10DE, 0x07DE),
6385 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6387 { /* MCP73 Ethernet Controller */
6388 PCI_DEVICE(0x10DE, 0x07DF),
6389 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V12
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_MSI_FIX
,
6391 { /* MCP77 Ethernet Controller */
6392 PCI_DEVICE(0x10DE, 0x0760),
6393 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6395 { /* MCP77 Ethernet Controller */
6396 PCI_DEVICE(0x10DE, 0x0761),
6397 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6399 { /* MCP77 Ethernet Controller */
6400 PCI_DEVICE(0x10DE, 0x0762),
6401 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6403 { /* MCP77 Ethernet Controller */
6404 PCI_DEVICE(0x10DE, 0x0763),
6405 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6407 { /* MCP79 Ethernet Controller */
6408 PCI_DEVICE(0x10DE, 0x0AB0),
6409 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6411 { /* MCP79 Ethernet Controller */
6412 PCI_DEVICE(0x10DE, 0x0AB1),
6413 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6415 { /* MCP79 Ethernet Controller */
6416 PCI_DEVICE(0x10DE, 0x0AB2),
6417 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6419 { /* MCP79 Ethernet Controller */
6420 PCI_DEVICE(0x10DE, 0x0AB3),
6421 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT2
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
|DEV_NEED_MSI_FIX
,
6423 { /* MCP89 Ethernet Controller */
6424 PCI_DEVICE(0x10DE, 0x0D7D),
6425 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V123
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
|DEV_NEED_PHY_INIT_FIX
,
6430 static struct pci_driver forcedeth_pci_driver
= {
6432 .id_table
= pci_tbl
,
6434 .remove
= nv_remove
,
6435 .shutdown
= nv_shutdown
,
6436 .driver
.pm
= NV_PM_OPS
,
6439 module_param(max_interrupt_work
, int, 0);
6440 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
6441 module_param(optimization_mode
, int, 0);
6442 MODULE_PARM_DESC(optimization_mode
, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6443 module_param(poll_interval
, int, 0);
6444 MODULE_PARM_DESC(poll_interval
, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6445 module_param(msi
, int, 0);
6446 MODULE_PARM_DESC(msi
, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6447 module_param(msix
, int, 0);
6448 MODULE_PARM_DESC(msix
, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6449 module_param(dma_64bit
, int, 0);
6450 MODULE_PARM_DESC(dma_64bit
, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6451 module_param(phy_cross
, int, 0);
6452 MODULE_PARM_DESC(phy_cross
, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6453 module_param(phy_power_down
, int, 0);
6454 MODULE_PARM_DESC(phy_power_down
, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6455 module_param(debug_tx_timeout
, bool, 0);
6456 MODULE_PARM_DESC(debug_tx_timeout
,
6457 "Dump tx related registers and ring when tx_timeout happens");
6459 module_pci_driver(forcedeth_pci_driver
);
6460 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6461 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6462 MODULE_LICENSE("GPL");
6463 MODULE_DEVICE_TABLE(pci
, pci_tbl
);