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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / oki-semi / pch_gbe / pch_gbe_main.c
1 /*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "pch_gbe.h"
21 #include "pch_gbe_api.h"
22 #include <linux/module.h>
23 #include <linux/net_tstamp.h>
24 #include <linux/ptp_classify.h>
25 #include <linux/gpio.h>
26
27 #define DRV_VERSION "1.01"
28 const char pch_driver_version[] = DRV_VERSION;
29
30 #define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
31 #define PCH_GBE_MAR_ENTRIES 16
32 #define PCH_GBE_SHORT_PKT 64
33 #define DSC_INIT16 0xC000
34 #define PCH_GBE_DMA_ALIGN 0
35 #define PCH_GBE_DMA_PADDING 2
36 #define PCH_GBE_WATCHDOG_PERIOD (5 * HZ) /* watchdog time */
37 #define PCH_GBE_COPYBREAK_DEFAULT 256
38 #define PCH_GBE_PCI_BAR 1
39 #define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
40
41 /* Macros for ML7223 */
42 #define PCI_VENDOR_ID_ROHM 0x10db
43 #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
44
45 /* Macros for ML7831 */
46 #define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802
47
48 #define PCH_GBE_TX_WEIGHT 64
49 #define PCH_GBE_RX_WEIGHT 64
50 #define PCH_GBE_RX_BUFFER_WRITE 16
51
52 /* Initialize the wake-on-LAN settings */
53 #define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
54
55 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
56 PCH_GBE_CHIP_TYPE_INTERNAL | \
57 PCH_GBE_RGMII_MODE_RGMII \
58 )
59
60 /* Ethertype field values */
61 #define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880
62 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
63 #define PCH_GBE_FRAME_SIZE_2048 2048
64 #define PCH_GBE_FRAME_SIZE_4096 4096
65 #define PCH_GBE_FRAME_SIZE_8192 8192
66
67 #define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
68 #define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
69 #define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
70 #define PCH_GBE_DESC_UNUSED(R) \
71 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
72 (R)->next_to_clean - (R)->next_to_use - 1)
73
74 /* Pause packet value */
75 #define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
76 #define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
77 #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
78 #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
79
80
81 /* This defines the bits that are set in the Interrupt Mask
82 * Set/Read Register. Each bit is documented below:
83 * o RXT0 = Receiver Timer Interrupt (ring 0)
84 * o TXDW = Transmit Descriptor Written Back
85 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
86 * o RXSEQ = Receive Sequence Error
87 * o LSC = Link Status Change
88 */
89 #define PCH_GBE_INT_ENABLE_MASK ( \
90 PCH_GBE_INT_RX_DMA_CMPLT | \
91 PCH_GBE_INT_RX_DSC_EMP | \
92 PCH_GBE_INT_RX_FIFO_ERR | \
93 PCH_GBE_INT_WOL_DET | \
94 PCH_GBE_INT_TX_CMPLT \
95 )
96
97 #define PCH_GBE_INT_DISABLE_ALL 0
98
99 /* Macros for ieee1588 */
100 /* 0x40 Time Synchronization Channel Control Register Bits */
101 #define MASTER_MODE (1<<0)
102 #define SLAVE_MODE (0)
103 #define V2_MODE (1<<31)
104 #define CAP_MODE0 (0)
105 #define CAP_MODE2 (1<<17)
106
107 /* 0x44 Time Synchronization Channel Event Register Bits */
108 #define TX_SNAPSHOT_LOCKED (1<<0)
109 #define RX_SNAPSHOT_LOCKED (1<<1)
110
111 #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
112 #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
113
114 #define MINNOW_PHY_RESET_GPIO 13
115
116 static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
117
118 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
119 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
120 int data);
121 static void pch_gbe_set_multi(struct net_device *netdev);
122
123 static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
124 {
125 u8 *data = skb->data;
126 unsigned int offset;
127 u16 *hi, *id;
128 u32 lo;
129
130 if (ptp_classify_raw(skb) == PTP_CLASS_NONE)
131 return 0;
132
133 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
134
135 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
136 return 0;
137
138 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
139 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
140
141 memcpy(&lo, &hi[1], sizeof(lo));
142
143 return (uid_hi == *hi &&
144 uid_lo == lo &&
145 seqid == *id);
146 }
147
148 static void
149 pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
150 {
151 struct skb_shared_hwtstamps *shhwtstamps;
152 struct pci_dev *pdev;
153 u64 ns;
154 u32 hi, lo, val;
155 u16 uid, seq;
156
157 if (!adapter->hwts_rx_en)
158 return;
159
160 /* Get ieee1588's dev information */
161 pdev = adapter->ptp_pdev;
162
163 val = pch_ch_event_read(pdev);
164
165 if (!(val & RX_SNAPSHOT_LOCKED))
166 return;
167
168 lo = pch_src_uuid_lo_read(pdev);
169 hi = pch_src_uuid_hi_read(pdev);
170
171 uid = hi & 0xffff;
172 seq = (hi >> 16) & 0xffff;
173
174 if (!pch_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
175 goto out;
176
177 ns = pch_rx_snap_read(pdev);
178
179 shhwtstamps = skb_hwtstamps(skb);
180 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
181 shhwtstamps->hwtstamp = ns_to_ktime(ns);
182 out:
183 pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
184 }
185
186 static void
187 pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
188 {
189 struct skb_shared_hwtstamps shhwtstamps;
190 struct pci_dev *pdev;
191 struct skb_shared_info *shtx;
192 u64 ns;
193 u32 cnt, val;
194
195 shtx = skb_shinfo(skb);
196 if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
197 return;
198
199 shtx->tx_flags |= SKBTX_IN_PROGRESS;
200
201 /* Get ieee1588's dev information */
202 pdev = adapter->ptp_pdev;
203
204 /*
205 * This really stinks, but we have to poll for the Tx time stamp.
206 */
207 for (cnt = 0; cnt < 100; cnt++) {
208 val = pch_ch_event_read(pdev);
209 if (val & TX_SNAPSHOT_LOCKED)
210 break;
211 udelay(1);
212 }
213 if (!(val & TX_SNAPSHOT_LOCKED)) {
214 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
215 return;
216 }
217
218 ns = pch_tx_snap_read(pdev);
219
220 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
221 shhwtstamps.hwtstamp = ns_to_ktime(ns);
222 skb_tstamp_tx(skb, &shhwtstamps);
223
224 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
225 }
226
227 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
228 {
229 struct hwtstamp_config cfg;
230 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
231 struct pci_dev *pdev;
232 u8 station[20];
233
234 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
235 return -EFAULT;
236
237 if (cfg.flags) /* reserved for future extensions */
238 return -EINVAL;
239
240 /* Get ieee1588's dev information */
241 pdev = adapter->ptp_pdev;
242
243 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
244 return -ERANGE;
245
246 switch (cfg.rx_filter) {
247 case HWTSTAMP_FILTER_NONE:
248 adapter->hwts_rx_en = 0;
249 break;
250 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
251 adapter->hwts_rx_en = 0;
252 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
253 break;
254 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
255 adapter->hwts_rx_en = 1;
256 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
257 break;
258 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
259 adapter->hwts_rx_en = 1;
260 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
261 strcpy(station, PTP_L4_MULTICAST_SA);
262 pch_set_station_address(station, pdev);
263 break;
264 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
265 adapter->hwts_rx_en = 1;
266 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
267 strcpy(station, PTP_L2_MULTICAST_SA);
268 pch_set_station_address(station, pdev);
269 break;
270 default:
271 return -ERANGE;
272 }
273
274 adapter->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
275
276 /* Clear out any old time stamps. */
277 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
278
279 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
280 }
281
282 static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
283 {
284 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
285 }
286
287 /**
288 * pch_gbe_mac_read_mac_addr - Read MAC address
289 * @hw: Pointer to the HW structure
290 * Returns:
291 * 0: Successful.
292 */
293 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
294 {
295 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
296 u32 adr1a, adr1b;
297
298 adr1a = ioread32(&hw->reg->mac_adr[0].high);
299 adr1b = ioread32(&hw->reg->mac_adr[0].low);
300
301 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
302 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
303 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
304 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
305 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
306 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
307
308 netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr);
309 return 0;
310 }
311
312 /**
313 * pch_gbe_wait_clr_bit - Wait to clear a bit
314 * @reg: Pointer of register
315 * @busy: Busy bit
316 */
317 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
318 {
319 u32 tmp;
320
321 /* wait busy */
322 tmp = 1000;
323 while ((ioread32(reg) & bit) && --tmp)
324 cpu_relax();
325 if (!tmp)
326 pr_err("Error: busy bit is not cleared\n");
327 }
328
329 /**
330 * pch_gbe_mac_mar_set - Set MAC address register
331 * @hw: Pointer to the HW structure
332 * @addr: Pointer to the MAC address
333 * @index: MAC address array register
334 */
335 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
336 {
337 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
338 u32 mar_low, mar_high, adrmask;
339
340 netdev_dbg(adapter->netdev, "index : 0x%x\n", index);
341
342 /*
343 * HW expects these in little endian so we reverse the byte order
344 * from network order (big endian) to little endian
345 */
346 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
347 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
348 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
349 /* Stop the MAC Address of index. */
350 adrmask = ioread32(&hw->reg->ADDR_MASK);
351 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
352 /* wait busy */
353 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
354 /* Set the MAC address to the MAC address 1A/1B register */
355 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
356 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
357 /* Start the MAC address of index */
358 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
359 /* wait busy */
360 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
361 }
362
363 /**
364 * pch_gbe_mac_reset_hw - Reset hardware
365 * @hw: Pointer to the HW structure
366 */
367 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
368 {
369 /* Read the MAC address. and store to the private data */
370 pch_gbe_mac_read_mac_addr(hw);
371 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
372 #ifdef PCH_GBE_MAC_IFOP_RGMII
373 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
374 #endif
375 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
376 /* Setup the receive addresses */
377 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
378 return;
379 }
380
381 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
382 {
383 u32 rctl;
384 /* Disables Receive MAC */
385 rctl = ioread32(&hw->reg->MAC_RX_EN);
386 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
387 }
388
389 static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
390 {
391 u32 rctl;
392 /* Enables Receive MAC */
393 rctl = ioread32(&hw->reg->MAC_RX_EN);
394 iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
395 }
396
397 /**
398 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
399 * @hw: Pointer to the HW structure
400 * @mar_count: Receive address registers
401 */
402 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
403 {
404 u32 i;
405
406 /* Setup the receive address */
407 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
408
409 /* Zero out the other receive addresses */
410 for (i = 1; i < mar_count; i++) {
411 iowrite32(0, &hw->reg->mac_adr[i].high);
412 iowrite32(0, &hw->reg->mac_adr[i].low);
413 }
414 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
415 /* wait busy */
416 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
417 }
418
419
420 /**
421 * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
422 * @hw: Pointer to the HW structure
423 * @mc_addr_list: Array of multicast addresses to program
424 * @mc_addr_count: Number of multicast addresses to program
425 * @mar_used_count: The first MAC Address register free to program
426 * @mar_total_num: Total number of supported MAC Address Registers
427 */
428 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
429 u8 *mc_addr_list, u32 mc_addr_count,
430 u32 mar_used_count, u32 mar_total_num)
431 {
432 u32 i, adrmask;
433
434 /* Load the first set of multicast addresses into the exact
435 * filters (RAR). If there are not enough to fill the RAR
436 * array, clear the filters.
437 */
438 for (i = mar_used_count; i < mar_total_num; i++) {
439 if (mc_addr_count) {
440 pch_gbe_mac_mar_set(hw, mc_addr_list, i);
441 mc_addr_count--;
442 mc_addr_list += ETH_ALEN;
443 } else {
444 /* Clear MAC address mask */
445 adrmask = ioread32(&hw->reg->ADDR_MASK);
446 iowrite32((adrmask | (0x0001 << i)),
447 &hw->reg->ADDR_MASK);
448 /* wait busy */
449 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
450 /* Clear MAC address */
451 iowrite32(0, &hw->reg->mac_adr[i].high);
452 iowrite32(0, &hw->reg->mac_adr[i].low);
453 }
454 }
455 }
456
457 /**
458 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
459 * @hw: Pointer to the HW structure
460 * Returns:
461 * 0: Successful.
462 * Negative value: Failed.
463 */
464 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
465 {
466 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
467 struct pch_gbe_mac_info *mac = &hw->mac;
468 u32 rx_fctrl;
469
470 netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc);
471
472 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
473
474 switch (mac->fc) {
475 case PCH_GBE_FC_NONE:
476 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
477 mac->tx_fc_enable = false;
478 break;
479 case PCH_GBE_FC_RX_PAUSE:
480 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
481 mac->tx_fc_enable = false;
482 break;
483 case PCH_GBE_FC_TX_PAUSE:
484 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
485 mac->tx_fc_enable = true;
486 break;
487 case PCH_GBE_FC_FULL:
488 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
489 mac->tx_fc_enable = true;
490 break;
491 default:
492 netdev_err(adapter->netdev,
493 "Flow control param set incorrectly\n");
494 return -EINVAL;
495 }
496 if (mac->link_duplex == DUPLEX_HALF)
497 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
498 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
499 netdev_dbg(adapter->netdev,
500 "RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
501 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
502 return 0;
503 }
504
505 /**
506 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
507 * @hw: Pointer to the HW structure
508 * @wu_evt: Wake up event
509 */
510 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
511 {
512 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
513 u32 addr_mask;
514
515 netdev_dbg(adapter->netdev, "wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
516 wu_evt, ioread32(&hw->reg->ADDR_MASK));
517
518 if (wu_evt) {
519 /* Set Wake-On-Lan address mask */
520 addr_mask = ioread32(&hw->reg->ADDR_MASK);
521 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
522 /* wait busy */
523 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
524 iowrite32(0, &hw->reg->WOL_ST);
525 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
526 iowrite32(0x02, &hw->reg->TCPIP_ACC);
527 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
528 } else {
529 iowrite32(0, &hw->reg->WOL_CTRL);
530 iowrite32(0, &hw->reg->WOL_ST);
531 }
532 return;
533 }
534
535 /**
536 * pch_gbe_mac_ctrl_miim - Control MIIM interface
537 * @hw: Pointer to the HW structure
538 * @addr: Address of PHY
539 * @dir: Operetion. (Write or Read)
540 * @reg: Access register of PHY
541 * @data: Write data.
542 *
543 * Returns: Read date.
544 */
545 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
546 u16 data)
547 {
548 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
549 u32 data_out = 0;
550 unsigned int i;
551 unsigned long flags;
552
553 spin_lock_irqsave(&hw->miim_lock, flags);
554
555 for (i = 100; i; --i) {
556 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
557 break;
558 udelay(20);
559 }
560 if (i == 0) {
561 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n");
562 spin_unlock_irqrestore(&hw->miim_lock, flags);
563 return 0; /* No way to indicate timeout error */
564 }
565 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
566 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
567 dir | data), &hw->reg->MIIM);
568 for (i = 0; i < 100; i++) {
569 udelay(20);
570 data_out = ioread32(&hw->reg->MIIM);
571 if ((data_out & PCH_GBE_MIIM_OPER_READY))
572 break;
573 }
574 spin_unlock_irqrestore(&hw->miim_lock, flags);
575
576 netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n",
577 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
578 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
579 return (u16) data_out;
580 }
581
582 /**
583 * pch_gbe_mac_set_pause_packet - Set pause packet
584 * @hw: Pointer to the HW structure
585 */
586 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
587 {
588 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
589 unsigned long tmp2, tmp3;
590
591 /* Set Pause packet */
592 tmp2 = hw->mac.addr[1];
593 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
594 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
595
596 tmp3 = hw->mac.addr[5];
597 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
598 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
599 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
600
601 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
602 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
603 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
604 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
605 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
606
607 /* Transmit Pause Packet */
608 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
609
610 netdev_dbg(adapter->netdev,
611 "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
612 ioread32(&hw->reg->PAUSE_PKT1),
613 ioread32(&hw->reg->PAUSE_PKT2),
614 ioread32(&hw->reg->PAUSE_PKT3),
615 ioread32(&hw->reg->PAUSE_PKT4),
616 ioread32(&hw->reg->PAUSE_PKT5));
617
618 return;
619 }
620
621
622 /**
623 * pch_gbe_alloc_queues - Allocate memory for all rings
624 * @adapter: Board private structure to initialize
625 * Returns:
626 * 0: Successfully
627 * Negative value: Failed
628 */
629 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
630 {
631 adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev,
632 sizeof(*adapter->tx_ring), GFP_KERNEL);
633 if (!adapter->tx_ring)
634 return -ENOMEM;
635
636 adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev,
637 sizeof(*adapter->rx_ring), GFP_KERNEL);
638 if (!adapter->rx_ring)
639 return -ENOMEM;
640 return 0;
641 }
642
643 /**
644 * pch_gbe_init_stats - Initialize status
645 * @adapter: Board private structure to initialize
646 */
647 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
648 {
649 memset(&adapter->stats, 0, sizeof(adapter->stats));
650 return;
651 }
652
653 /**
654 * pch_gbe_init_phy - Initialize PHY
655 * @adapter: Board private structure to initialize
656 * Returns:
657 * 0: Successfully
658 * Negative value: Failed
659 */
660 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
661 {
662 struct net_device *netdev = adapter->netdev;
663 u32 addr;
664 u16 bmcr, stat;
665
666 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
667 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
668 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
669 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
670 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
671 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
672 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
673 break;
674 }
675 adapter->hw.phy.addr = adapter->mii.phy_id;
676 netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id);
677 if (addr == PCH_GBE_PHY_REGS_LEN)
678 return -EAGAIN;
679 /* Selected the phy and isolate the rest */
680 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
681 if (addr != adapter->mii.phy_id) {
682 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
683 BMCR_ISOLATE);
684 } else {
685 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
686 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
687 bmcr & ~BMCR_ISOLATE);
688 }
689 }
690
691 /* MII setup */
692 adapter->mii.phy_id_mask = 0x1F;
693 adapter->mii.reg_num_mask = 0x1F;
694 adapter->mii.dev = adapter->netdev;
695 adapter->mii.mdio_read = pch_gbe_mdio_read;
696 adapter->mii.mdio_write = pch_gbe_mdio_write;
697 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
698 return 0;
699 }
700
701 /**
702 * pch_gbe_mdio_read - The read function for mii
703 * @netdev: Network interface device structure
704 * @addr: Phy ID
705 * @reg: Access location
706 * Returns:
707 * 0: Successfully
708 * Negative value: Failed
709 */
710 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
711 {
712 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
713 struct pch_gbe_hw *hw = &adapter->hw;
714
715 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
716 (u16) 0);
717 }
718
719 /**
720 * pch_gbe_mdio_write - The write function for mii
721 * @netdev: Network interface device structure
722 * @addr: Phy ID (not used)
723 * @reg: Access location
724 * @data: Write data
725 */
726 static void pch_gbe_mdio_write(struct net_device *netdev,
727 int addr, int reg, int data)
728 {
729 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
730 struct pch_gbe_hw *hw = &adapter->hw;
731
732 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
733 }
734
735 /**
736 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
737 * @work: Pointer of board private structure
738 */
739 static void pch_gbe_reset_task(struct work_struct *work)
740 {
741 struct pch_gbe_adapter *adapter;
742 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
743
744 rtnl_lock();
745 pch_gbe_reinit_locked(adapter);
746 rtnl_unlock();
747 }
748
749 /**
750 * pch_gbe_reinit_locked- Re-initialization
751 * @adapter: Board private structure
752 */
753 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
754 {
755 pch_gbe_down(adapter);
756 pch_gbe_up(adapter);
757 }
758
759 /**
760 * pch_gbe_reset - Reset GbE
761 * @adapter: Board private structure
762 */
763 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
764 {
765 struct net_device *netdev = adapter->netdev;
766
767 pch_gbe_mac_reset_hw(&adapter->hw);
768 /* reprogram multicast address register after reset */
769 pch_gbe_set_multi(netdev);
770 /* Setup the receive address. */
771 pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
772 if (pch_gbe_hal_init_hw(&adapter->hw))
773 netdev_err(netdev, "Hardware Error\n");
774 }
775
776 /**
777 * pch_gbe_free_irq - Free an interrupt
778 * @adapter: Board private structure
779 */
780 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
781 {
782 struct net_device *netdev = adapter->netdev;
783
784 free_irq(adapter->irq, netdev);
785 pci_free_irq_vectors(adapter->pdev);
786 }
787
788 /**
789 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
790 * @adapter: Board private structure
791 */
792 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
793 {
794 struct pch_gbe_hw *hw = &adapter->hw;
795
796 atomic_inc(&adapter->irq_sem);
797 iowrite32(0, &hw->reg->INT_EN);
798 ioread32(&hw->reg->INT_ST);
799 synchronize_irq(adapter->irq);
800
801 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
802 ioread32(&hw->reg->INT_EN));
803 }
804
805 /**
806 * pch_gbe_irq_enable - Enable default interrupt generation settings
807 * @adapter: Board private structure
808 */
809 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
810 {
811 struct pch_gbe_hw *hw = &adapter->hw;
812
813 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
814 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
815 ioread32(&hw->reg->INT_ST);
816 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
817 ioread32(&hw->reg->INT_EN));
818 }
819
820
821
822 /**
823 * pch_gbe_setup_tctl - configure the Transmit control registers
824 * @adapter: Board private structure
825 */
826 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
827 {
828 struct pch_gbe_hw *hw = &adapter->hw;
829 u32 tx_mode, tcpip;
830
831 tx_mode = PCH_GBE_TM_LONG_PKT |
832 PCH_GBE_TM_ST_AND_FD |
833 PCH_GBE_TM_SHORT_PKT |
834 PCH_GBE_TM_TH_TX_STRT_8 |
835 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
836
837 iowrite32(tx_mode, &hw->reg->TX_MODE);
838
839 tcpip = ioread32(&hw->reg->TCPIP_ACC);
840 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
841 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
842 return;
843 }
844
845 /**
846 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
847 * @adapter: Board private structure
848 */
849 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
850 {
851 struct pch_gbe_hw *hw = &adapter->hw;
852 u32 tdba, tdlen, dctrl;
853
854 netdev_dbg(adapter->netdev, "dma addr = 0x%08llx size = 0x%08x\n",
855 (unsigned long long)adapter->tx_ring->dma,
856 adapter->tx_ring->size);
857
858 /* Setup the HW Tx Head and Tail descriptor pointers */
859 tdba = adapter->tx_ring->dma;
860 tdlen = adapter->tx_ring->size - 0x10;
861 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
862 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
863 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
864
865 /* Enables Transmission DMA */
866 dctrl = ioread32(&hw->reg->DMA_CTRL);
867 dctrl |= PCH_GBE_TX_DMA_EN;
868 iowrite32(dctrl, &hw->reg->DMA_CTRL);
869 }
870
871 /**
872 * pch_gbe_setup_rctl - Configure the receive control registers
873 * @adapter: Board private structure
874 */
875 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
876 {
877 struct pch_gbe_hw *hw = &adapter->hw;
878 u32 rx_mode, tcpip;
879
880 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
881 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
882
883 iowrite32(rx_mode, &hw->reg->RX_MODE);
884
885 tcpip = ioread32(&hw->reg->TCPIP_ACC);
886
887 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
888 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
889 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
890 return;
891 }
892
893 /**
894 * pch_gbe_configure_rx - Configure Receive Unit after Reset
895 * @adapter: Board private structure
896 */
897 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
898 {
899 struct pch_gbe_hw *hw = &adapter->hw;
900 u32 rdba, rdlen, rxdma;
901
902 netdev_dbg(adapter->netdev, "dma adr = 0x%08llx size = 0x%08x\n",
903 (unsigned long long)adapter->rx_ring->dma,
904 adapter->rx_ring->size);
905
906 pch_gbe_mac_force_mac_fc(hw);
907
908 pch_gbe_disable_mac_rx(hw);
909
910 /* Disables Receive DMA */
911 rxdma = ioread32(&hw->reg->DMA_CTRL);
912 rxdma &= ~PCH_GBE_RX_DMA_EN;
913 iowrite32(rxdma, &hw->reg->DMA_CTRL);
914
915 netdev_dbg(adapter->netdev,
916 "MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
917 ioread32(&hw->reg->MAC_RX_EN),
918 ioread32(&hw->reg->DMA_CTRL));
919
920 /* Setup the HW Rx Head and Tail Descriptor Pointers and
921 * the Base and Length of the Rx Descriptor Ring */
922 rdba = adapter->rx_ring->dma;
923 rdlen = adapter->rx_ring->size - 0x10;
924 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
925 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
926 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
927 }
928
929 /**
930 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
931 * @adapter: Board private structure
932 * @buffer_info: Buffer information structure
933 */
934 static void pch_gbe_unmap_and_free_tx_resource(
935 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
936 {
937 if (buffer_info->mapped) {
938 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
939 buffer_info->length, DMA_TO_DEVICE);
940 buffer_info->mapped = false;
941 }
942 if (buffer_info->skb) {
943 dev_kfree_skb_any(buffer_info->skb);
944 buffer_info->skb = NULL;
945 }
946 }
947
948 /**
949 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
950 * @adapter: Board private structure
951 * @buffer_info: Buffer information structure
952 */
953 static void pch_gbe_unmap_and_free_rx_resource(
954 struct pch_gbe_adapter *adapter,
955 struct pch_gbe_buffer *buffer_info)
956 {
957 if (buffer_info->mapped) {
958 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
959 buffer_info->length, DMA_FROM_DEVICE);
960 buffer_info->mapped = false;
961 }
962 if (buffer_info->skb) {
963 dev_kfree_skb_any(buffer_info->skb);
964 buffer_info->skb = NULL;
965 }
966 }
967
968 /**
969 * pch_gbe_clean_tx_ring - Free Tx Buffers
970 * @adapter: Board private structure
971 * @tx_ring: Ring to be cleaned
972 */
973 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
974 struct pch_gbe_tx_ring *tx_ring)
975 {
976 struct pch_gbe_hw *hw = &adapter->hw;
977 struct pch_gbe_buffer *buffer_info;
978 unsigned long size;
979 unsigned int i;
980
981 /* Free all the Tx ring sk_buffs */
982 for (i = 0; i < tx_ring->count; i++) {
983 buffer_info = &tx_ring->buffer_info[i];
984 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
985 }
986 netdev_dbg(adapter->netdev,
987 "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
988
989 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
990 memset(tx_ring->buffer_info, 0, size);
991
992 /* Zero out the descriptor ring */
993 memset(tx_ring->desc, 0, tx_ring->size);
994 tx_ring->next_to_use = 0;
995 tx_ring->next_to_clean = 0;
996 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
997 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
998 }
999
1000 /**
1001 * pch_gbe_clean_rx_ring - Free Rx Buffers
1002 * @adapter: Board private structure
1003 * @rx_ring: Ring to free buffers from
1004 */
1005 static void
1006 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
1007 struct pch_gbe_rx_ring *rx_ring)
1008 {
1009 struct pch_gbe_hw *hw = &adapter->hw;
1010 struct pch_gbe_buffer *buffer_info;
1011 unsigned long size;
1012 unsigned int i;
1013
1014 /* Free all the Rx ring sk_buffs */
1015 for (i = 0; i < rx_ring->count; i++) {
1016 buffer_info = &rx_ring->buffer_info[i];
1017 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
1018 }
1019 netdev_dbg(adapter->netdev,
1020 "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
1021 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1022 memset(rx_ring->buffer_info, 0, size);
1023
1024 /* Zero out the descriptor ring */
1025 memset(rx_ring->desc, 0, rx_ring->size);
1026 rx_ring->next_to_clean = 0;
1027 rx_ring->next_to_use = 0;
1028 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
1029 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
1030 }
1031
1032 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
1033 u16 duplex)
1034 {
1035 struct pch_gbe_hw *hw = &adapter->hw;
1036 unsigned long rgmii = 0;
1037
1038 /* Set the RGMII control. */
1039 #ifdef PCH_GBE_MAC_IFOP_RGMII
1040 switch (speed) {
1041 case SPEED_10:
1042 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
1043 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1044 break;
1045 case SPEED_100:
1046 rgmii = (PCH_GBE_RGMII_RATE_25M |
1047 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1048 break;
1049 case SPEED_1000:
1050 rgmii = (PCH_GBE_RGMII_RATE_125M |
1051 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1052 break;
1053 }
1054 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1055 #else /* GMII */
1056 rgmii = 0;
1057 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1058 #endif
1059 }
1060 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1061 u16 duplex)
1062 {
1063 struct net_device *netdev = adapter->netdev;
1064 struct pch_gbe_hw *hw = &adapter->hw;
1065 unsigned long mode = 0;
1066
1067 /* Set the communication mode */
1068 switch (speed) {
1069 case SPEED_10:
1070 mode = PCH_GBE_MODE_MII_ETHER;
1071 netdev->tx_queue_len = 10;
1072 break;
1073 case SPEED_100:
1074 mode = PCH_GBE_MODE_MII_ETHER;
1075 netdev->tx_queue_len = 100;
1076 break;
1077 case SPEED_1000:
1078 mode = PCH_GBE_MODE_GMII_ETHER;
1079 break;
1080 }
1081 if (duplex == DUPLEX_FULL)
1082 mode |= PCH_GBE_MODE_FULL_DUPLEX;
1083 else
1084 mode |= PCH_GBE_MODE_HALF_DUPLEX;
1085 iowrite32(mode, &hw->reg->MODE);
1086 }
1087
1088 /**
1089 * pch_gbe_watchdog - Watchdog process
1090 * @data: Board private structure
1091 */
1092 static void pch_gbe_watchdog(unsigned long data)
1093 {
1094 struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
1095 struct net_device *netdev = adapter->netdev;
1096 struct pch_gbe_hw *hw = &adapter->hw;
1097
1098 netdev_dbg(netdev, "right now = %ld\n", jiffies);
1099
1100 pch_gbe_update_stats(adapter);
1101 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
1102 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1103 netdev->tx_queue_len = adapter->tx_queue_len;
1104 /* mii library handles link maintenance tasks */
1105 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
1106 netdev_err(netdev, "ethtool get setting Error\n");
1107 mod_timer(&adapter->watchdog_timer,
1108 round_jiffies(jiffies +
1109 PCH_GBE_WATCHDOG_PERIOD));
1110 return;
1111 }
1112 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
1113 hw->mac.link_duplex = cmd.duplex;
1114 /* Set the RGMII control. */
1115 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1116 hw->mac.link_duplex);
1117 /* Set the communication mode */
1118 pch_gbe_set_mode(adapter, hw->mac.link_speed,
1119 hw->mac.link_duplex);
1120 netdev_dbg(netdev,
1121 "Link is Up %d Mbps %s-Duplex\n",
1122 hw->mac.link_speed,
1123 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1124 netif_carrier_on(netdev);
1125 netif_wake_queue(netdev);
1126 } else if ((!mii_link_ok(&adapter->mii)) &&
1127 (netif_carrier_ok(netdev))) {
1128 netdev_dbg(netdev, "NIC Link is Down\n");
1129 hw->mac.link_speed = SPEED_10;
1130 hw->mac.link_duplex = DUPLEX_HALF;
1131 netif_carrier_off(netdev);
1132 netif_stop_queue(netdev);
1133 }
1134 mod_timer(&adapter->watchdog_timer,
1135 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1136 }
1137
1138 /**
1139 * pch_gbe_tx_queue - Carry out queuing of the transmission data
1140 * @adapter: Board private structure
1141 * @tx_ring: Tx descriptor ring structure
1142 * @skb: Sockt buffer structure
1143 */
1144 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1145 struct pch_gbe_tx_ring *tx_ring,
1146 struct sk_buff *skb)
1147 {
1148 struct pch_gbe_hw *hw = &adapter->hw;
1149 struct pch_gbe_tx_desc *tx_desc;
1150 struct pch_gbe_buffer *buffer_info;
1151 struct sk_buff *tmp_skb;
1152 unsigned int frame_ctrl;
1153 unsigned int ring_num;
1154
1155 /*-- Set frame control --*/
1156 frame_ctrl = 0;
1157 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1158 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
1159 if (skb->ip_summed == CHECKSUM_NONE)
1160 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1161
1162 /* Performs checksum processing */
1163 /*
1164 * It is because the hardware accelerator does not support a checksum,
1165 * when the received data size is less than 64 bytes.
1166 */
1167 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
1168 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1169 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1170 if (skb->protocol == htons(ETH_P_IP)) {
1171 struct iphdr *iph = ip_hdr(skb);
1172 unsigned int offset;
1173 offset = skb_transport_offset(skb);
1174 if (iph->protocol == IPPROTO_TCP) {
1175 skb->csum = 0;
1176 tcp_hdr(skb)->check = 0;
1177 skb->csum = skb_checksum(skb, offset,
1178 skb->len - offset, 0);
1179 tcp_hdr(skb)->check =
1180 csum_tcpudp_magic(iph->saddr,
1181 iph->daddr,
1182 skb->len - offset,
1183 IPPROTO_TCP,
1184 skb->csum);
1185 } else if (iph->protocol == IPPROTO_UDP) {
1186 skb->csum = 0;
1187 udp_hdr(skb)->check = 0;
1188 skb->csum =
1189 skb_checksum(skb, offset,
1190 skb->len - offset, 0);
1191 udp_hdr(skb)->check =
1192 csum_tcpudp_magic(iph->saddr,
1193 iph->daddr,
1194 skb->len - offset,
1195 IPPROTO_UDP,
1196 skb->csum);
1197 }
1198 }
1199 }
1200
1201 ring_num = tx_ring->next_to_use;
1202 if (unlikely((ring_num + 1) == tx_ring->count))
1203 tx_ring->next_to_use = 0;
1204 else
1205 tx_ring->next_to_use = ring_num + 1;
1206
1207
1208 buffer_info = &tx_ring->buffer_info[ring_num];
1209 tmp_skb = buffer_info->skb;
1210
1211 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1212 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1213 tmp_skb->data[ETH_HLEN] = 0x00;
1214 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1215 tmp_skb->len = skb->len;
1216 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1217 (skb->len - ETH_HLEN));
1218 /*-- Set Buffer information --*/
1219 buffer_info->length = tmp_skb->len;
1220 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1221 buffer_info->length,
1222 DMA_TO_DEVICE);
1223 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1224 netdev_err(adapter->netdev, "TX DMA map failed\n");
1225 buffer_info->dma = 0;
1226 buffer_info->time_stamp = 0;
1227 tx_ring->next_to_use = ring_num;
1228 return;
1229 }
1230 buffer_info->mapped = true;
1231 buffer_info->time_stamp = jiffies;
1232
1233 /*-- Set Tx descriptor --*/
1234 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1235 tx_desc->buffer_addr = (buffer_info->dma);
1236 tx_desc->length = (tmp_skb->len);
1237 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1238 tx_desc->tx_frame_ctrl = (frame_ctrl);
1239 tx_desc->gbec_status = (DSC_INIT16);
1240
1241 if (unlikely(++ring_num == tx_ring->count))
1242 ring_num = 0;
1243
1244 /* Update software pointer of TX descriptor */
1245 iowrite32(tx_ring->dma +
1246 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1247 &hw->reg->TX_DSC_SW_P);
1248
1249 pch_tx_timestamp(adapter, skb);
1250
1251 dev_kfree_skb_any(skb);
1252 }
1253
1254 /**
1255 * pch_gbe_update_stats - Update the board statistics counters
1256 * @adapter: Board private structure
1257 */
1258 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1259 {
1260 struct net_device *netdev = adapter->netdev;
1261 struct pci_dev *pdev = adapter->pdev;
1262 struct pch_gbe_hw_stats *stats = &adapter->stats;
1263 unsigned long flags;
1264
1265 /*
1266 * Prevent stats update while adapter is being reset, or if the pci
1267 * connection is down.
1268 */
1269 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1270 return;
1271
1272 spin_lock_irqsave(&adapter->stats_lock, flags);
1273
1274 /* Update device status "adapter->stats" */
1275 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1276 stats->tx_errors = stats->tx_length_errors +
1277 stats->tx_aborted_errors +
1278 stats->tx_carrier_errors + stats->tx_timeout_count;
1279
1280 /* Update network device status "adapter->net_stats" */
1281 netdev->stats.rx_packets = stats->rx_packets;
1282 netdev->stats.rx_bytes = stats->rx_bytes;
1283 netdev->stats.rx_dropped = stats->rx_dropped;
1284 netdev->stats.tx_packets = stats->tx_packets;
1285 netdev->stats.tx_bytes = stats->tx_bytes;
1286 netdev->stats.tx_dropped = stats->tx_dropped;
1287 /* Fill out the OS statistics structure */
1288 netdev->stats.multicast = stats->multicast;
1289 netdev->stats.collisions = stats->collisions;
1290 /* Rx Errors */
1291 netdev->stats.rx_errors = stats->rx_errors;
1292 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1293 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1294 /* Tx Errors */
1295 netdev->stats.tx_errors = stats->tx_errors;
1296 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1297 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1298
1299 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1300 }
1301
1302 static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
1303 {
1304 u32 rxdma;
1305
1306 /* Disable Receive DMA */
1307 rxdma = ioread32(&hw->reg->DMA_CTRL);
1308 rxdma &= ~PCH_GBE_RX_DMA_EN;
1309 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1310 }
1311
1312 static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
1313 {
1314 u32 rxdma;
1315
1316 /* Enables Receive DMA */
1317 rxdma = ioread32(&hw->reg->DMA_CTRL);
1318 rxdma |= PCH_GBE_RX_DMA_EN;
1319 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1320 }
1321
1322 /**
1323 * pch_gbe_intr - Interrupt Handler
1324 * @irq: Interrupt number
1325 * @data: Pointer to a network interface device structure
1326 * Returns:
1327 * - IRQ_HANDLED: Our interrupt
1328 * - IRQ_NONE: Not our interrupt
1329 */
1330 static irqreturn_t pch_gbe_intr(int irq, void *data)
1331 {
1332 struct net_device *netdev = data;
1333 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1334 struct pch_gbe_hw *hw = &adapter->hw;
1335 u32 int_st;
1336 u32 int_en;
1337
1338 /* Check request status */
1339 int_st = ioread32(&hw->reg->INT_ST);
1340 int_st = int_st & ioread32(&hw->reg->INT_EN);
1341 /* When request status is no interruption factor */
1342 if (unlikely(!int_st))
1343 return IRQ_NONE; /* Not our interrupt. End processing. */
1344 netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st);
1345 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1346 adapter->stats.intr_rx_frame_err_count++;
1347 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1348 if (!adapter->rx_stop_flag) {
1349 adapter->stats.intr_rx_fifo_err_count++;
1350 netdev_dbg(netdev, "Rx fifo over run\n");
1351 adapter->rx_stop_flag = true;
1352 int_en = ioread32(&hw->reg->INT_EN);
1353 iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1354 &hw->reg->INT_EN);
1355 pch_gbe_disable_dma_rx(&adapter->hw);
1356 int_st |= ioread32(&hw->reg->INT_ST);
1357 int_st = int_st & ioread32(&hw->reg->INT_EN);
1358 }
1359 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1360 adapter->stats.intr_rx_dma_err_count++;
1361 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1362 adapter->stats.intr_tx_fifo_err_count++;
1363 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1364 adapter->stats.intr_tx_dma_err_count++;
1365 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1366 adapter->stats.intr_tcpip_err_count++;
1367 /* When Rx descriptor is empty */
1368 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1369 adapter->stats.intr_rx_dsc_empty_count++;
1370 netdev_dbg(netdev, "Rx descriptor is empty\n");
1371 int_en = ioread32(&hw->reg->INT_EN);
1372 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1373 if (hw->mac.tx_fc_enable) {
1374 /* Set Pause packet */
1375 pch_gbe_mac_set_pause_packet(hw);
1376 }
1377 }
1378
1379 /* When request status is Receive interruption */
1380 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
1381 (adapter->rx_stop_flag)) {
1382 if (likely(napi_schedule_prep(&adapter->napi))) {
1383 /* Enable only Rx Descriptor empty */
1384 atomic_inc(&adapter->irq_sem);
1385 int_en = ioread32(&hw->reg->INT_EN);
1386 int_en &=
1387 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1388 iowrite32(int_en, &hw->reg->INT_EN);
1389 /* Start polling for NAPI */
1390 __napi_schedule(&adapter->napi);
1391 }
1392 }
1393 netdev_dbg(netdev, "return = 0x%08x INT_EN reg = 0x%08x\n",
1394 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1395 return IRQ_HANDLED;
1396 }
1397
1398 /**
1399 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1400 * @adapter: Board private structure
1401 * @rx_ring: Rx descriptor ring
1402 * @cleaned_count: Cleaned count
1403 */
1404 static void
1405 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1406 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1407 {
1408 struct net_device *netdev = adapter->netdev;
1409 struct pci_dev *pdev = adapter->pdev;
1410 struct pch_gbe_hw *hw = &adapter->hw;
1411 struct pch_gbe_rx_desc *rx_desc;
1412 struct pch_gbe_buffer *buffer_info;
1413 struct sk_buff *skb;
1414 unsigned int i;
1415 unsigned int bufsz;
1416
1417 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1418 i = rx_ring->next_to_use;
1419
1420 while ((cleaned_count--)) {
1421 buffer_info = &rx_ring->buffer_info[i];
1422 skb = netdev_alloc_skb(netdev, bufsz);
1423 if (unlikely(!skb)) {
1424 /* Better luck next round */
1425 adapter->stats.rx_alloc_buff_failed++;
1426 break;
1427 }
1428 /* align */
1429 skb_reserve(skb, NET_IP_ALIGN);
1430 buffer_info->skb = skb;
1431
1432 buffer_info->dma = dma_map_single(&pdev->dev,
1433 buffer_info->rx_buffer,
1434 buffer_info->length,
1435 DMA_FROM_DEVICE);
1436 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1437 dev_kfree_skb(skb);
1438 buffer_info->skb = NULL;
1439 buffer_info->dma = 0;
1440 adapter->stats.rx_alloc_buff_failed++;
1441 break; /* while !buffer_info->skb */
1442 }
1443 buffer_info->mapped = true;
1444 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1445 rx_desc->buffer_addr = (buffer_info->dma);
1446 rx_desc->gbec_status = DSC_INIT16;
1447
1448 netdev_dbg(netdev,
1449 "i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1450 i, (unsigned long long)buffer_info->dma,
1451 buffer_info->length);
1452
1453 if (unlikely(++i == rx_ring->count))
1454 i = 0;
1455 }
1456 if (likely(rx_ring->next_to_use != i)) {
1457 rx_ring->next_to_use = i;
1458 if (unlikely(i-- == 0))
1459 i = (rx_ring->count - 1);
1460 iowrite32(rx_ring->dma +
1461 (int)sizeof(struct pch_gbe_rx_desc) * i,
1462 &hw->reg->RX_DSC_SW_P);
1463 }
1464 return;
1465 }
1466
1467 static int
1468 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1469 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1470 {
1471 struct pci_dev *pdev = adapter->pdev;
1472 struct pch_gbe_buffer *buffer_info;
1473 unsigned int i;
1474 unsigned int bufsz;
1475 unsigned int size;
1476
1477 bufsz = adapter->rx_buffer_len;
1478
1479 size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1480 rx_ring->rx_buff_pool =
1481 dma_zalloc_coherent(&pdev->dev, size,
1482 &rx_ring->rx_buff_pool_logic, GFP_KERNEL);
1483 if (!rx_ring->rx_buff_pool)
1484 return -ENOMEM;
1485
1486 rx_ring->rx_buff_pool_size = size;
1487 for (i = 0; i < rx_ring->count; i++) {
1488 buffer_info = &rx_ring->buffer_info[i];
1489 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1490 buffer_info->length = bufsz;
1491 }
1492 return 0;
1493 }
1494
1495 /**
1496 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1497 * @adapter: Board private structure
1498 * @tx_ring: Tx descriptor ring
1499 */
1500 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1501 struct pch_gbe_tx_ring *tx_ring)
1502 {
1503 struct pch_gbe_buffer *buffer_info;
1504 struct sk_buff *skb;
1505 unsigned int i;
1506 unsigned int bufsz;
1507 struct pch_gbe_tx_desc *tx_desc;
1508
1509 bufsz =
1510 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1511
1512 for (i = 0; i < tx_ring->count; i++) {
1513 buffer_info = &tx_ring->buffer_info[i];
1514 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1515 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1516 buffer_info->skb = skb;
1517 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1518 tx_desc->gbec_status = (DSC_INIT16);
1519 }
1520 return;
1521 }
1522
1523 /**
1524 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1525 * @adapter: Board private structure
1526 * @tx_ring: Tx descriptor ring
1527 * Returns:
1528 * true: Cleaned the descriptor
1529 * false: Not cleaned the descriptor
1530 */
1531 static bool
1532 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1533 struct pch_gbe_tx_ring *tx_ring)
1534 {
1535 struct pch_gbe_tx_desc *tx_desc;
1536 struct pch_gbe_buffer *buffer_info;
1537 struct sk_buff *skb;
1538 unsigned int i;
1539 unsigned int cleaned_count = 0;
1540 bool cleaned = false;
1541 int unused, thresh;
1542
1543 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1544 tx_ring->next_to_clean);
1545
1546 i = tx_ring->next_to_clean;
1547 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1548 netdev_dbg(adapter->netdev, "gbec_status:0x%04x dma_status:0x%04x\n",
1549 tx_desc->gbec_status, tx_desc->dma_status);
1550
1551 unused = PCH_GBE_DESC_UNUSED(tx_ring);
1552 thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
1553 if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh))
1554 { /* current marked clean, tx queue filling up, do extra clean */
1555 int j, k;
1556 if (unused < 8) { /* tx queue nearly full */
1557 netdev_dbg(adapter->netdev,
1558 "clean_tx: transmit queue warning (%x,%x) unused=%d\n",
1559 tx_ring->next_to_clean, tx_ring->next_to_use,
1560 unused);
1561 }
1562
1563 /* current marked clean, scan for more that need cleaning. */
1564 k = i;
1565 for (j = 0; j < PCH_GBE_TX_WEIGHT; j++)
1566 {
1567 tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
1568 if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/
1569 if (++k >= tx_ring->count) k = 0; /*increment, wrap*/
1570 }
1571 if (j < PCH_GBE_TX_WEIGHT) {
1572 netdev_dbg(adapter->netdev,
1573 "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n",
1574 unused, j, i, k, tx_ring->next_to_use,
1575 tx_desc->gbec_status);
1576 i = k; /*found one to clean, usu gbec_status==2000.*/
1577 }
1578 }
1579
1580 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1581 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n",
1582 tx_desc->gbec_status);
1583 buffer_info = &tx_ring->buffer_info[i];
1584 skb = buffer_info->skb;
1585 cleaned = true;
1586
1587 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1588 adapter->stats.tx_aborted_errors++;
1589 netdev_err(adapter->netdev, "Transfer Abort Error\n");
1590 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1591 ) {
1592 adapter->stats.tx_carrier_errors++;
1593 netdev_err(adapter->netdev,
1594 "Transfer Carrier Sense Error\n");
1595 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1596 ) {
1597 adapter->stats.tx_aborted_errors++;
1598 netdev_err(adapter->netdev,
1599 "Transfer Collision Abort Error\n");
1600 } else if ((tx_desc->gbec_status &
1601 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1602 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1603 adapter->stats.collisions++;
1604 adapter->stats.tx_packets++;
1605 adapter->stats.tx_bytes += skb->len;
1606 netdev_dbg(adapter->netdev, "Transfer Collision\n");
1607 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1608 ) {
1609 adapter->stats.tx_packets++;
1610 adapter->stats.tx_bytes += skb->len;
1611 }
1612 if (buffer_info->mapped) {
1613 netdev_dbg(adapter->netdev,
1614 "unmap buffer_info->dma : %d\n", i);
1615 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1616 buffer_info->length, DMA_TO_DEVICE);
1617 buffer_info->mapped = false;
1618 }
1619 if (buffer_info->skb) {
1620 netdev_dbg(adapter->netdev,
1621 "trim buffer_info->skb : %d\n", i);
1622 skb_trim(buffer_info->skb, 0);
1623 }
1624 tx_desc->gbec_status = DSC_INIT16;
1625 if (unlikely(++i == tx_ring->count))
1626 i = 0;
1627 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1628
1629 /* weight of a sort for tx, to avoid endless transmit cleanup */
1630 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1631 cleaned = false;
1632 break;
1633 }
1634 }
1635 netdev_dbg(adapter->netdev,
1636 "called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1637 cleaned_count);
1638 if (cleaned_count > 0) { /*skip this if nothing cleaned*/
1639 /* Recover from running out of Tx resources in xmit_frame */
1640 netif_tx_lock(adapter->netdev);
1641 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev))))
1642 {
1643 netif_wake_queue(adapter->netdev);
1644 adapter->stats.tx_restart_count++;
1645 netdev_dbg(adapter->netdev, "Tx wake queue\n");
1646 }
1647
1648 tx_ring->next_to_clean = i;
1649
1650 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1651 tx_ring->next_to_clean);
1652 netif_tx_unlock(adapter->netdev);
1653 }
1654 return cleaned;
1655 }
1656
1657 /**
1658 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1659 * @adapter: Board private structure
1660 * @rx_ring: Rx descriptor ring
1661 * @work_done: Completed count
1662 * @work_to_do: Request count
1663 * Returns:
1664 * true: Cleaned the descriptor
1665 * false: Not cleaned the descriptor
1666 */
1667 static bool
1668 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1669 struct pch_gbe_rx_ring *rx_ring,
1670 int *work_done, int work_to_do)
1671 {
1672 struct net_device *netdev = adapter->netdev;
1673 struct pci_dev *pdev = adapter->pdev;
1674 struct pch_gbe_buffer *buffer_info;
1675 struct pch_gbe_rx_desc *rx_desc;
1676 u32 length;
1677 unsigned int i;
1678 unsigned int cleaned_count = 0;
1679 bool cleaned = false;
1680 struct sk_buff *skb;
1681 u8 dma_status;
1682 u16 gbec_status;
1683 u32 tcp_ip_status;
1684
1685 i = rx_ring->next_to_clean;
1686
1687 while (*work_done < work_to_do) {
1688 /* Check Rx descriptor status */
1689 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1690 if (rx_desc->gbec_status == DSC_INIT16)
1691 break;
1692 cleaned = true;
1693 cleaned_count++;
1694
1695 dma_status = rx_desc->dma_status;
1696 gbec_status = rx_desc->gbec_status;
1697 tcp_ip_status = rx_desc->tcp_ip_status;
1698 rx_desc->gbec_status = DSC_INIT16;
1699 buffer_info = &rx_ring->buffer_info[i];
1700 skb = buffer_info->skb;
1701 buffer_info->skb = NULL;
1702
1703 /* unmap dma */
1704 dma_unmap_single(&pdev->dev, buffer_info->dma,
1705 buffer_info->length, DMA_FROM_DEVICE);
1706 buffer_info->mapped = false;
1707
1708 netdev_dbg(netdev,
1709 "RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x] BufInf = 0x%p\n",
1710 i, dma_status, gbec_status, tcp_ip_status,
1711 buffer_info);
1712 /* Error check */
1713 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1714 adapter->stats.rx_frame_errors++;
1715 netdev_err(netdev, "Receive Not Octal Error\n");
1716 } else if (unlikely(gbec_status &
1717 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1718 adapter->stats.rx_frame_errors++;
1719 netdev_err(netdev, "Receive Nibble Error\n");
1720 } else if (unlikely(gbec_status &
1721 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1722 adapter->stats.rx_crc_errors++;
1723 netdev_err(netdev, "Receive CRC Error\n");
1724 } else {
1725 /* get receive length */
1726 /* length convert[-3], length includes FCS length */
1727 length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1728 if (rx_desc->rx_words_eob & 0x02)
1729 length = length - 4;
1730 /*
1731 * buffer_info->rx_buffer: [Header:14][payload]
1732 * skb->data: [Reserve:2][Header:14][payload]
1733 */
1734 memcpy(skb->data, buffer_info->rx_buffer, length);
1735
1736 /* update status of driver */
1737 adapter->stats.rx_bytes += length;
1738 adapter->stats.rx_packets++;
1739 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1740 adapter->stats.multicast++;
1741 /* Write meta date of skb */
1742 skb_put(skb, length);
1743
1744 pch_rx_timestamp(adapter, skb);
1745
1746 skb->protocol = eth_type_trans(skb, netdev);
1747 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1748 skb->ip_summed = CHECKSUM_UNNECESSARY;
1749 else
1750 skb->ip_summed = CHECKSUM_NONE;
1751
1752 napi_gro_receive(&adapter->napi, skb);
1753 (*work_done)++;
1754 netdev_dbg(netdev,
1755 "Receive skb->ip_summed: %d length: %d\n",
1756 skb->ip_summed, length);
1757 }
1758 /* return some buffers to hardware, one at a time is too slow */
1759 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1760 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1761 cleaned_count);
1762 cleaned_count = 0;
1763 }
1764 if (++i == rx_ring->count)
1765 i = 0;
1766 }
1767 rx_ring->next_to_clean = i;
1768 if (cleaned_count)
1769 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1770 return cleaned;
1771 }
1772
1773 /**
1774 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1775 * @adapter: Board private structure
1776 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
1777 * Returns:
1778 * 0: Successfully
1779 * Negative value: Failed
1780 */
1781 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1782 struct pch_gbe_tx_ring *tx_ring)
1783 {
1784 struct pci_dev *pdev = adapter->pdev;
1785 struct pch_gbe_tx_desc *tx_desc;
1786 int size;
1787 int desNo;
1788
1789 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1790 tx_ring->buffer_info = vzalloc(size);
1791 if (!tx_ring->buffer_info)
1792 return -ENOMEM;
1793
1794 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1795
1796 tx_ring->desc = dma_zalloc_coherent(&pdev->dev, tx_ring->size,
1797 &tx_ring->dma, GFP_KERNEL);
1798 if (!tx_ring->desc) {
1799 vfree(tx_ring->buffer_info);
1800 return -ENOMEM;
1801 }
1802
1803 tx_ring->next_to_use = 0;
1804 tx_ring->next_to_clean = 0;
1805
1806 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1807 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1808 tx_desc->gbec_status = DSC_INIT16;
1809 }
1810 netdev_dbg(adapter->netdev,
1811 "tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1812 tx_ring->desc, (unsigned long long)tx_ring->dma,
1813 tx_ring->next_to_clean, tx_ring->next_to_use);
1814 return 0;
1815 }
1816
1817 /**
1818 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1819 * @adapter: Board private structure
1820 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1821 * Returns:
1822 * 0: Successfully
1823 * Negative value: Failed
1824 */
1825 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1826 struct pch_gbe_rx_ring *rx_ring)
1827 {
1828 struct pci_dev *pdev = adapter->pdev;
1829 struct pch_gbe_rx_desc *rx_desc;
1830 int size;
1831 int desNo;
1832
1833 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1834 rx_ring->buffer_info = vzalloc(size);
1835 if (!rx_ring->buffer_info)
1836 return -ENOMEM;
1837
1838 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1839 rx_ring->desc = dma_zalloc_coherent(&pdev->dev, rx_ring->size,
1840 &rx_ring->dma, GFP_KERNEL);
1841 if (!rx_ring->desc) {
1842 vfree(rx_ring->buffer_info);
1843 return -ENOMEM;
1844 }
1845 rx_ring->next_to_clean = 0;
1846 rx_ring->next_to_use = 0;
1847 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1848 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1849 rx_desc->gbec_status = DSC_INIT16;
1850 }
1851 netdev_dbg(adapter->netdev,
1852 "rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1853 rx_ring->desc, (unsigned long long)rx_ring->dma,
1854 rx_ring->next_to_clean, rx_ring->next_to_use);
1855 return 0;
1856 }
1857
1858 /**
1859 * pch_gbe_free_tx_resources - Free Tx Resources
1860 * @adapter: Board private structure
1861 * @tx_ring: Tx descriptor ring for a specific queue
1862 */
1863 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1864 struct pch_gbe_tx_ring *tx_ring)
1865 {
1866 struct pci_dev *pdev = adapter->pdev;
1867
1868 pch_gbe_clean_tx_ring(adapter, tx_ring);
1869 vfree(tx_ring->buffer_info);
1870 tx_ring->buffer_info = NULL;
1871 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1872 tx_ring->desc = NULL;
1873 }
1874
1875 /**
1876 * pch_gbe_free_rx_resources - Free Rx Resources
1877 * @adapter: Board private structure
1878 * @rx_ring: Ring to clean the resources from
1879 */
1880 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1881 struct pch_gbe_rx_ring *rx_ring)
1882 {
1883 struct pci_dev *pdev = adapter->pdev;
1884
1885 pch_gbe_clean_rx_ring(adapter, rx_ring);
1886 vfree(rx_ring->buffer_info);
1887 rx_ring->buffer_info = NULL;
1888 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1889 rx_ring->desc = NULL;
1890 }
1891
1892 /**
1893 * pch_gbe_request_irq - Allocate an interrupt line
1894 * @adapter: Board private structure
1895 * Returns:
1896 * 0: Successfully
1897 * Negative value: Failed
1898 */
1899 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1900 {
1901 struct net_device *netdev = adapter->netdev;
1902 int err;
1903
1904 err = pci_alloc_irq_vectors(adapter->pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1905 if (err < 0)
1906 return err;
1907
1908 adapter->irq = pci_irq_vector(adapter->pdev, 0);
1909
1910 err = request_irq(adapter->irq, &pch_gbe_intr, IRQF_SHARED,
1911 netdev->name, netdev);
1912 if (err)
1913 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n",
1914 err);
1915 netdev_dbg(netdev, "have_msi : %d return : 0x%04x\n",
1916 pci_dev_msi_enabled(adapter->pdev), err);
1917 return err;
1918 }
1919
1920 /**
1921 * pch_gbe_up - Up GbE network device
1922 * @adapter: Board private structure
1923 * Returns:
1924 * 0: Successfully
1925 * Negative value: Failed
1926 */
1927 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1928 {
1929 struct net_device *netdev = adapter->netdev;
1930 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1931 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1932 int err = -EINVAL;
1933
1934 /* Ensure we have a valid MAC */
1935 if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
1936 netdev_err(netdev, "Error: Invalid MAC address\n");
1937 goto out;
1938 }
1939
1940 /* hardware has been reset, we need to reload some things */
1941 pch_gbe_set_multi(netdev);
1942
1943 pch_gbe_setup_tctl(adapter);
1944 pch_gbe_configure_tx(adapter);
1945 pch_gbe_setup_rctl(adapter);
1946 pch_gbe_configure_rx(adapter);
1947
1948 err = pch_gbe_request_irq(adapter);
1949 if (err) {
1950 netdev_err(netdev,
1951 "Error: can't bring device up - irq request failed\n");
1952 goto out;
1953 }
1954 err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1955 if (err) {
1956 netdev_err(netdev,
1957 "Error: can't bring device up - alloc rx buffers pool failed\n");
1958 goto freeirq;
1959 }
1960 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1961 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1962 adapter->tx_queue_len = netdev->tx_queue_len;
1963 pch_gbe_enable_dma_rx(&adapter->hw);
1964 pch_gbe_enable_mac_rx(&adapter->hw);
1965
1966 mod_timer(&adapter->watchdog_timer, jiffies);
1967
1968 napi_enable(&adapter->napi);
1969 pch_gbe_irq_enable(adapter);
1970 netif_start_queue(adapter->netdev);
1971
1972 return 0;
1973
1974 freeirq:
1975 pch_gbe_free_irq(adapter);
1976 out:
1977 return err;
1978 }
1979
1980 /**
1981 * pch_gbe_down - Down GbE network device
1982 * @adapter: Board private structure
1983 */
1984 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1985 {
1986 struct net_device *netdev = adapter->netdev;
1987 struct pci_dev *pdev = adapter->pdev;
1988 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1989
1990 /* signal that we're down so the interrupt handler does not
1991 * reschedule our watchdog timer */
1992 napi_disable(&adapter->napi);
1993 atomic_set(&adapter->irq_sem, 0);
1994
1995 pch_gbe_irq_disable(adapter);
1996 pch_gbe_free_irq(adapter);
1997
1998 del_timer_sync(&adapter->watchdog_timer);
1999
2000 netdev->tx_queue_len = adapter->tx_queue_len;
2001 netif_carrier_off(netdev);
2002 netif_stop_queue(netdev);
2003
2004 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
2005 pch_gbe_reset(adapter);
2006 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
2007 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
2008
2009 pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
2010 rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
2011 rx_ring->rx_buff_pool_logic = 0;
2012 rx_ring->rx_buff_pool_size = 0;
2013 rx_ring->rx_buff_pool = NULL;
2014 }
2015
2016 /**
2017 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
2018 * @adapter: Board private structure to initialize
2019 * Returns:
2020 * 0: Successfully
2021 * Negative value: Failed
2022 */
2023 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
2024 {
2025 struct pch_gbe_hw *hw = &adapter->hw;
2026 struct net_device *netdev = adapter->netdev;
2027
2028 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2029 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2030 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2031
2032 /* Initialize the hardware-specific values */
2033 if (pch_gbe_hal_setup_init_funcs(hw)) {
2034 netdev_err(netdev, "Hardware Initialization Failure\n");
2035 return -EIO;
2036 }
2037 if (pch_gbe_alloc_queues(adapter)) {
2038 netdev_err(netdev, "Unable to allocate memory for queues\n");
2039 return -ENOMEM;
2040 }
2041 spin_lock_init(&adapter->hw.miim_lock);
2042 spin_lock_init(&adapter->stats_lock);
2043 spin_lock_init(&adapter->ethtool_lock);
2044 atomic_set(&adapter->irq_sem, 0);
2045 pch_gbe_irq_disable(adapter);
2046
2047 pch_gbe_init_stats(adapter);
2048
2049 netdev_dbg(netdev,
2050 "rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
2051 (u32) adapter->rx_buffer_len,
2052 hw->mac.min_frame_size, hw->mac.max_frame_size);
2053 return 0;
2054 }
2055
2056 /**
2057 * pch_gbe_open - Called when a network interface is made active
2058 * @netdev: Network interface device structure
2059 * Returns:
2060 * 0: Successfully
2061 * Negative value: Failed
2062 */
2063 static int pch_gbe_open(struct net_device *netdev)
2064 {
2065 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2066 struct pch_gbe_hw *hw = &adapter->hw;
2067 int err;
2068
2069 /* allocate transmit descriptors */
2070 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2071 if (err)
2072 goto err_setup_tx;
2073 /* allocate receive descriptors */
2074 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2075 if (err)
2076 goto err_setup_rx;
2077 pch_gbe_hal_power_up_phy(hw);
2078 err = pch_gbe_up(adapter);
2079 if (err)
2080 goto err_up;
2081 netdev_dbg(netdev, "Success End\n");
2082 return 0;
2083
2084 err_up:
2085 if (!adapter->wake_up_evt)
2086 pch_gbe_hal_power_down_phy(hw);
2087 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2088 err_setup_rx:
2089 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2090 err_setup_tx:
2091 pch_gbe_reset(adapter);
2092 netdev_err(netdev, "Error End\n");
2093 return err;
2094 }
2095
2096 /**
2097 * pch_gbe_stop - Disables a network interface
2098 * @netdev: Network interface device structure
2099 * Returns:
2100 * 0: Successfully
2101 */
2102 static int pch_gbe_stop(struct net_device *netdev)
2103 {
2104 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2105 struct pch_gbe_hw *hw = &adapter->hw;
2106
2107 pch_gbe_down(adapter);
2108 if (!adapter->wake_up_evt)
2109 pch_gbe_hal_power_down_phy(hw);
2110 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2111 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2112 return 0;
2113 }
2114
2115 /**
2116 * pch_gbe_xmit_frame - Packet transmitting start
2117 * @skb: Socket buffer structure
2118 * @netdev: Network interface device structure
2119 * Returns:
2120 * - NETDEV_TX_OK: Normal end
2121 * - NETDEV_TX_BUSY: Error end
2122 */
2123 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2124 {
2125 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2126 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
2127
2128 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2129 netif_stop_queue(netdev);
2130 netdev_dbg(netdev,
2131 "Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
2132 tx_ring->next_to_use, tx_ring->next_to_clean);
2133 return NETDEV_TX_BUSY;
2134 }
2135
2136 /* CRC,ITAG no support */
2137 pch_gbe_tx_queue(adapter, tx_ring, skb);
2138 return NETDEV_TX_OK;
2139 }
2140
2141 /**
2142 * pch_gbe_set_multi - Multicast and Promiscuous mode set
2143 * @netdev: Network interface device structure
2144 */
2145 static void pch_gbe_set_multi(struct net_device *netdev)
2146 {
2147 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2148 struct pch_gbe_hw *hw = &adapter->hw;
2149 struct netdev_hw_addr *ha;
2150 u8 *mta_list;
2151 u32 rctl;
2152 int i;
2153 int mc_count;
2154
2155 netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
2156
2157 /* Check for Promiscuous and All Multicast modes */
2158 rctl = ioread32(&hw->reg->RX_MODE);
2159 mc_count = netdev_mc_count(netdev);
2160 if ((netdev->flags & IFF_PROMISC)) {
2161 rctl &= ~PCH_GBE_ADD_FIL_EN;
2162 rctl &= ~PCH_GBE_MLT_FIL_EN;
2163 } else if ((netdev->flags & IFF_ALLMULTI)) {
2164 /* all the multicasting receive permissions */
2165 rctl |= PCH_GBE_ADD_FIL_EN;
2166 rctl &= ~PCH_GBE_MLT_FIL_EN;
2167 } else {
2168 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
2169 /* all the multicasting receive permissions */
2170 rctl |= PCH_GBE_ADD_FIL_EN;
2171 rctl &= ~PCH_GBE_MLT_FIL_EN;
2172 } else {
2173 rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2174 }
2175 }
2176 iowrite32(rctl, &hw->reg->RX_MODE);
2177
2178 if (mc_count >= PCH_GBE_MAR_ENTRIES)
2179 return;
2180 mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
2181 if (!mta_list)
2182 return;
2183
2184 /* The shared function expects a packed array of only addresses. */
2185 i = 0;
2186 netdev_for_each_mc_addr(ha, netdev) {
2187 if (i == mc_count)
2188 break;
2189 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
2190 }
2191 pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
2192 PCH_GBE_MAR_ENTRIES);
2193 kfree(mta_list);
2194
2195 netdev_dbg(netdev,
2196 "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
2197 ioread32(&hw->reg->RX_MODE), mc_count);
2198 }
2199
2200 /**
2201 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2202 * @netdev: Network interface device structure
2203 * @addr: Pointer to an address structure
2204 * Returns:
2205 * 0: Successfully
2206 * -EADDRNOTAVAIL: Failed
2207 */
2208 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2209 {
2210 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2211 struct sockaddr *skaddr = addr;
2212 int ret_val;
2213
2214 if (!is_valid_ether_addr(skaddr->sa_data)) {
2215 ret_val = -EADDRNOTAVAIL;
2216 } else {
2217 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2218 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2219 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2220 ret_val = 0;
2221 }
2222 netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val);
2223 netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr);
2224 netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr);
2225 netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2226 ioread32(&adapter->hw.reg->mac_adr[0].high),
2227 ioread32(&adapter->hw.reg->mac_adr[0].low));
2228 return ret_val;
2229 }
2230
2231 /**
2232 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2233 * @netdev: Network interface device structure
2234 * @new_mtu: New value for maximum frame size
2235 * Returns:
2236 * 0: Successfully
2237 * -EINVAL: Failed
2238 */
2239 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2240 {
2241 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2242 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2243 unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2244 int err;
2245
2246 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2247 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2248 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2249 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2250 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2251 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2252 else
2253 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2254
2255 if (netif_running(netdev)) {
2256 pch_gbe_down(adapter);
2257 err = pch_gbe_up(adapter);
2258 if (err) {
2259 adapter->rx_buffer_len = old_rx_buffer_len;
2260 pch_gbe_up(adapter);
2261 return err;
2262 } else {
2263 netdev->mtu = new_mtu;
2264 adapter->hw.mac.max_frame_size = max_frame;
2265 }
2266 } else {
2267 pch_gbe_reset(adapter);
2268 netdev->mtu = new_mtu;
2269 adapter->hw.mac.max_frame_size = max_frame;
2270 }
2271
2272 netdev_dbg(netdev,
2273 "max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2274 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2275 adapter->hw.mac.max_frame_size);
2276 return 0;
2277 }
2278
2279 /**
2280 * pch_gbe_set_features - Reset device after features changed
2281 * @netdev: Network interface device structure
2282 * @features: New features
2283 * Returns:
2284 * 0: HW state updated successfully
2285 */
2286 static int pch_gbe_set_features(struct net_device *netdev,
2287 netdev_features_t features)
2288 {
2289 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2290 netdev_features_t changed = features ^ netdev->features;
2291
2292 if (!(changed & NETIF_F_RXCSUM))
2293 return 0;
2294
2295 if (netif_running(netdev))
2296 pch_gbe_reinit_locked(adapter);
2297 else
2298 pch_gbe_reset(adapter);
2299
2300 return 0;
2301 }
2302
2303 /**
2304 * pch_gbe_ioctl - Controls register through a MII interface
2305 * @netdev: Network interface device structure
2306 * @ifr: Pointer to ifr structure
2307 * @cmd: Control command
2308 * Returns:
2309 * 0: Successfully
2310 * Negative value: Failed
2311 */
2312 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2313 {
2314 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2315
2316 netdev_dbg(netdev, "cmd : 0x%04x\n", cmd);
2317
2318 if (cmd == SIOCSHWTSTAMP)
2319 return hwtstamp_ioctl(netdev, ifr, cmd);
2320
2321 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2322 }
2323
2324 /**
2325 * pch_gbe_tx_timeout - Respond to a Tx Hang
2326 * @netdev: Network interface device structure
2327 */
2328 static void pch_gbe_tx_timeout(struct net_device *netdev)
2329 {
2330 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2331
2332 /* Do the reset outside of interrupt context */
2333 adapter->stats.tx_timeout_count++;
2334 schedule_work(&adapter->reset_task);
2335 }
2336
2337 /**
2338 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2339 * @napi: Pointer of polling device struct
2340 * @budget: The maximum number of a packet
2341 * Returns:
2342 * false: Exit the polling mode
2343 * true: Continue the polling mode
2344 */
2345 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2346 {
2347 struct pch_gbe_adapter *adapter =
2348 container_of(napi, struct pch_gbe_adapter, napi);
2349 int work_done = 0;
2350 bool poll_end_flag = false;
2351 bool cleaned = false;
2352
2353 netdev_dbg(adapter->netdev, "budget : %d\n", budget);
2354
2355 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2356 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2357
2358 if (cleaned)
2359 work_done = budget;
2360 /* If no Tx and not enough Rx work done,
2361 * exit the polling mode
2362 */
2363 if (work_done < budget)
2364 poll_end_flag = true;
2365
2366 if (poll_end_flag) {
2367 napi_complete_done(napi, work_done);
2368 pch_gbe_irq_enable(adapter);
2369 }
2370
2371 if (adapter->rx_stop_flag) {
2372 adapter->rx_stop_flag = false;
2373 pch_gbe_enable_dma_rx(&adapter->hw);
2374 }
2375
2376 netdev_dbg(adapter->netdev,
2377 "poll_end_flag : %d work_done : %d budget : %d\n",
2378 poll_end_flag, work_done, budget);
2379
2380 return work_done;
2381 }
2382
2383 #ifdef CONFIG_NET_POLL_CONTROLLER
2384 /**
2385 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2386 * @netdev: Network interface device structure
2387 */
2388 static void pch_gbe_netpoll(struct net_device *netdev)
2389 {
2390 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2391
2392 disable_irq(adapter->irq);
2393 pch_gbe_intr(adapter->irq, netdev);
2394 enable_irq(adapter->irq);
2395 }
2396 #endif
2397
2398 static const struct net_device_ops pch_gbe_netdev_ops = {
2399 .ndo_open = pch_gbe_open,
2400 .ndo_stop = pch_gbe_stop,
2401 .ndo_start_xmit = pch_gbe_xmit_frame,
2402 .ndo_set_mac_address = pch_gbe_set_mac,
2403 .ndo_tx_timeout = pch_gbe_tx_timeout,
2404 .ndo_change_mtu = pch_gbe_change_mtu,
2405 .ndo_set_features = pch_gbe_set_features,
2406 .ndo_do_ioctl = pch_gbe_ioctl,
2407 .ndo_set_rx_mode = pch_gbe_set_multi,
2408 #ifdef CONFIG_NET_POLL_CONTROLLER
2409 .ndo_poll_controller = pch_gbe_netpoll,
2410 #endif
2411 };
2412
2413 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2414 pci_channel_state_t state)
2415 {
2416 struct net_device *netdev = pci_get_drvdata(pdev);
2417 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2418
2419 netif_device_detach(netdev);
2420 if (netif_running(netdev))
2421 pch_gbe_down(adapter);
2422 pci_disable_device(pdev);
2423 /* Request a slot slot reset. */
2424 return PCI_ERS_RESULT_NEED_RESET;
2425 }
2426
2427 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2428 {
2429 struct net_device *netdev = pci_get_drvdata(pdev);
2430 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2431 struct pch_gbe_hw *hw = &adapter->hw;
2432
2433 if (pci_enable_device(pdev)) {
2434 netdev_err(netdev, "Cannot re-enable PCI device after reset\n");
2435 return PCI_ERS_RESULT_DISCONNECT;
2436 }
2437 pci_set_master(pdev);
2438 pci_enable_wake(pdev, PCI_D0, 0);
2439 pch_gbe_hal_power_up_phy(hw);
2440 pch_gbe_reset(adapter);
2441 /* Clear wake up status */
2442 pch_gbe_mac_set_wol_event(hw, 0);
2443
2444 return PCI_ERS_RESULT_RECOVERED;
2445 }
2446
2447 static void pch_gbe_io_resume(struct pci_dev *pdev)
2448 {
2449 struct net_device *netdev = pci_get_drvdata(pdev);
2450 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2451
2452 if (netif_running(netdev)) {
2453 if (pch_gbe_up(adapter)) {
2454 netdev_dbg(netdev,
2455 "can't bring device back up after reset\n");
2456 return;
2457 }
2458 }
2459 netif_device_attach(netdev);
2460 }
2461
2462 static int __pch_gbe_suspend(struct pci_dev *pdev)
2463 {
2464 struct net_device *netdev = pci_get_drvdata(pdev);
2465 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2466 struct pch_gbe_hw *hw = &adapter->hw;
2467 u32 wufc = adapter->wake_up_evt;
2468 int retval = 0;
2469
2470 netif_device_detach(netdev);
2471 if (netif_running(netdev))
2472 pch_gbe_down(adapter);
2473 if (wufc) {
2474 pch_gbe_set_multi(netdev);
2475 pch_gbe_setup_rctl(adapter);
2476 pch_gbe_configure_rx(adapter);
2477 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2478 hw->mac.link_duplex);
2479 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2480 hw->mac.link_duplex);
2481 pch_gbe_mac_set_wol_event(hw, wufc);
2482 pci_disable_device(pdev);
2483 } else {
2484 pch_gbe_hal_power_down_phy(hw);
2485 pch_gbe_mac_set_wol_event(hw, wufc);
2486 pci_disable_device(pdev);
2487 }
2488 return retval;
2489 }
2490
2491 #ifdef CONFIG_PM
2492 static int pch_gbe_suspend(struct device *device)
2493 {
2494 struct pci_dev *pdev = to_pci_dev(device);
2495
2496 return __pch_gbe_suspend(pdev);
2497 }
2498
2499 static int pch_gbe_resume(struct device *device)
2500 {
2501 struct pci_dev *pdev = to_pci_dev(device);
2502 struct net_device *netdev = pci_get_drvdata(pdev);
2503 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2504 struct pch_gbe_hw *hw = &adapter->hw;
2505 u32 err;
2506
2507 err = pci_enable_device(pdev);
2508 if (err) {
2509 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
2510 return err;
2511 }
2512 pci_set_master(pdev);
2513 pch_gbe_hal_power_up_phy(hw);
2514 pch_gbe_reset(adapter);
2515 /* Clear wake on lan control and status */
2516 pch_gbe_mac_set_wol_event(hw, 0);
2517
2518 if (netif_running(netdev))
2519 pch_gbe_up(adapter);
2520 netif_device_attach(netdev);
2521
2522 return 0;
2523 }
2524 #endif /* CONFIG_PM */
2525
2526 static void pch_gbe_shutdown(struct pci_dev *pdev)
2527 {
2528 __pch_gbe_suspend(pdev);
2529 if (system_state == SYSTEM_POWER_OFF) {
2530 pci_wake_from_d3(pdev, true);
2531 pci_set_power_state(pdev, PCI_D3hot);
2532 }
2533 }
2534
2535 static void pch_gbe_remove(struct pci_dev *pdev)
2536 {
2537 struct net_device *netdev = pci_get_drvdata(pdev);
2538 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2539
2540 cancel_work_sync(&adapter->reset_task);
2541 unregister_netdev(netdev);
2542
2543 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2544
2545 free_netdev(netdev);
2546 }
2547
2548 static int pch_gbe_probe(struct pci_dev *pdev,
2549 const struct pci_device_id *pci_id)
2550 {
2551 struct net_device *netdev;
2552 struct pch_gbe_adapter *adapter;
2553 int ret;
2554
2555 ret = pcim_enable_device(pdev);
2556 if (ret)
2557 return ret;
2558
2559 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2560 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2561 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2562 if (ret) {
2563 ret = pci_set_consistent_dma_mask(pdev,
2564 DMA_BIT_MASK(32));
2565 if (ret) {
2566 dev_err(&pdev->dev, "ERR: No usable DMA "
2567 "configuration, aborting\n");
2568 return ret;
2569 }
2570 }
2571 }
2572
2573 ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev));
2574 if (ret) {
2575 dev_err(&pdev->dev,
2576 "ERR: Can't reserve PCI I/O and memory resources\n");
2577 return ret;
2578 }
2579 pci_set_master(pdev);
2580
2581 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2582 if (!netdev)
2583 return -ENOMEM;
2584 SET_NETDEV_DEV(netdev, &pdev->dev);
2585
2586 pci_set_drvdata(pdev, netdev);
2587 adapter = netdev_priv(netdev);
2588 adapter->netdev = netdev;
2589 adapter->pdev = pdev;
2590 adapter->hw.back = adapter;
2591 adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
2592 adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
2593 if (adapter->pdata && adapter->pdata->platform_init)
2594 adapter->pdata->platform_init(pdev);
2595
2596 adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
2597 PCI_DEVFN(12, 4));
2598
2599 netdev->netdev_ops = &pch_gbe_netdev_ops;
2600 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2601 netif_napi_add(netdev, &adapter->napi,
2602 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2603 netdev->hw_features = NETIF_F_RXCSUM |
2604 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2605 netdev->features = netdev->hw_features;
2606 pch_gbe_set_ethtool_ops(netdev);
2607
2608 /* MTU range: 46 - 10300 */
2609 netdev->min_mtu = ETH_ZLEN - ETH_HLEN;
2610 netdev->max_mtu = PCH_GBE_MAX_JUMBO_FRAME_SIZE -
2611 (ETH_HLEN + ETH_FCS_LEN);
2612
2613 pch_gbe_mac_load_mac_addr(&adapter->hw);
2614 pch_gbe_mac_reset_hw(&adapter->hw);
2615
2616 /* setup the private structure */
2617 ret = pch_gbe_sw_init(adapter);
2618 if (ret)
2619 goto err_free_netdev;
2620
2621 /* Initialize PHY */
2622 ret = pch_gbe_init_phy(adapter);
2623 if (ret) {
2624 dev_err(&pdev->dev, "PHY initialize error\n");
2625 goto err_free_adapter;
2626 }
2627 pch_gbe_hal_get_bus_info(&adapter->hw);
2628
2629 /* Read the MAC address. and store to the private data */
2630 ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2631 if (ret) {
2632 dev_err(&pdev->dev, "MAC address Read Error\n");
2633 goto err_free_adapter;
2634 }
2635
2636 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2637 if (!is_valid_ether_addr(netdev->dev_addr)) {
2638 /*
2639 * If the MAC is invalid (or just missing), display a warning
2640 * but do not abort setting up the device. pch_gbe_up will
2641 * prevent the interface from being brought up until a valid MAC
2642 * is set.
2643 */
2644 dev_err(&pdev->dev, "Invalid MAC address, "
2645 "interface disabled.\n");
2646 }
2647 setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2648 (unsigned long)adapter);
2649
2650 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2651
2652 pch_gbe_check_options(adapter);
2653
2654 /* initialize the wol settings based on the eeprom settings */
2655 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2656 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2657
2658 /* reset the hardware with the new settings */
2659 pch_gbe_reset(adapter);
2660
2661 ret = register_netdev(netdev);
2662 if (ret)
2663 goto err_free_adapter;
2664 /* tell the stack to leave us alone until pch_gbe_open() is called */
2665 netif_carrier_off(netdev);
2666 netif_stop_queue(netdev);
2667
2668 dev_dbg(&pdev->dev, "PCH Network Connection\n");
2669
2670 /* Disable hibernation on certain platforms */
2671 if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
2672 pch_gbe_phy_disable_hibernate(&adapter->hw);
2673
2674 device_set_wakeup_enable(&pdev->dev, 1);
2675 return 0;
2676
2677 err_free_adapter:
2678 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2679 err_free_netdev:
2680 free_netdev(netdev);
2681 return ret;
2682 }
2683
2684 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
2685 * ensure it is awake for probe and init. Request the line and reset the PHY.
2686 */
2687 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
2688 {
2689 unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
2690 unsigned gpio = MINNOW_PHY_RESET_GPIO;
2691 int ret;
2692
2693 ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
2694 "minnow_phy_reset");
2695 if (ret) {
2696 dev_err(&pdev->dev,
2697 "ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
2698 return ret;
2699 }
2700
2701 gpio_set_value(gpio, 0);
2702 usleep_range(1250, 1500);
2703 gpio_set_value(gpio, 1);
2704 usleep_range(1250, 1500);
2705
2706 return ret;
2707 }
2708
2709 static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
2710 .phy_tx_clk_delay = true,
2711 .phy_disable_hibernate = true,
2712 .platform_init = pch_gbe_minnow_platform_init,
2713 };
2714
2715 static const struct pci_device_id pch_gbe_pcidev_id[] = {
2716 {.vendor = PCI_VENDOR_ID_INTEL,
2717 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2718 .subvendor = PCI_VENDOR_ID_CIRCUITCO,
2719 .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD,
2720 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2721 .class_mask = (0xFFFF00),
2722 .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata
2723 },
2724 {.vendor = PCI_VENDOR_ID_INTEL,
2725 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2726 .subvendor = PCI_ANY_ID,
2727 .subdevice = PCI_ANY_ID,
2728 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2729 .class_mask = (0xFFFF00)
2730 },
2731 {.vendor = PCI_VENDOR_ID_ROHM,
2732 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2733 .subvendor = PCI_ANY_ID,
2734 .subdevice = PCI_ANY_ID,
2735 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2736 .class_mask = (0xFFFF00)
2737 },
2738 {.vendor = PCI_VENDOR_ID_ROHM,
2739 .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2740 .subvendor = PCI_ANY_ID,
2741 .subdevice = PCI_ANY_ID,
2742 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2743 .class_mask = (0xFFFF00)
2744 },
2745 /* required last entry */
2746 {0}
2747 };
2748
2749 #ifdef CONFIG_PM
2750 static const struct dev_pm_ops pch_gbe_pm_ops = {
2751 .suspend = pch_gbe_suspend,
2752 .resume = pch_gbe_resume,
2753 .freeze = pch_gbe_suspend,
2754 .thaw = pch_gbe_resume,
2755 .poweroff = pch_gbe_suspend,
2756 .restore = pch_gbe_resume,
2757 };
2758 #endif
2759
2760 static const struct pci_error_handlers pch_gbe_err_handler = {
2761 .error_detected = pch_gbe_io_error_detected,
2762 .slot_reset = pch_gbe_io_slot_reset,
2763 .resume = pch_gbe_io_resume
2764 };
2765
2766 static struct pci_driver pch_gbe_driver = {
2767 .name = KBUILD_MODNAME,
2768 .id_table = pch_gbe_pcidev_id,
2769 .probe = pch_gbe_probe,
2770 .remove = pch_gbe_remove,
2771 #ifdef CONFIG_PM
2772 .driver.pm = &pch_gbe_pm_ops,
2773 #endif
2774 .shutdown = pch_gbe_shutdown,
2775 .err_handler = &pch_gbe_err_handler
2776 };
2777
2778
2779 static int __init pch_gbe_init_module(void)
2780 {
2781 int ret;
2782
2783 pr_info("EG20T PCH Gigabit Ethernet Driver - version %s\n",DRV_VERSION);
2784 ret = pci_register_driver(&pch_gbe_driver);
2785 if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2786 if (copybreak == 0) {
2787 pr_info("copybreak disabled\n");
2788 } else {
2789 pr_info("copybreak enabled for packets <= %u bytes\n",
2790 copybreak);
2791 }
2792 }
2793 return ret;
2794 }
2795
2796 static void __exit pch_gbe_exit_module(void)
2797 {
2798 pci_unregister_driver(&pch_gbe_driver);
2799 }
2800
2801 module_init(pch_gbe_init_module);
2802 module_exit(pch_gbe_exit_module);
2803
2804 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2805 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
2806 MODULE_LICENSE("GPL");
2807 MODULE_VERSION(DRV_VERSION);
2808 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2809
2810 module_param(copybreak, uint, 0644);
2811 MODULE_PARM_DESC(copybreak,
2812 "Maximum size of packet that is copied to a new buffer on receive");
2813
2814 /* pch_gbe_main.c */
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