1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
38 #include <linux/delay.h>
39 #include <linux/firmware.h>
40 #include <linux/interrupt.h>
41 #include <linux/list.h>
42 #include <linux/mutex.h>
43 #include <linux/pci.h>
44 #include <linux/slab.h>
45 #include <linux/string.h>
46 #include <linux/workqueue.h>
47 #include <linux/zlib.h>
48 #include <linux/hashtable.h>
49 #include <linux/qed/qed_if.h>
50 #include "qed_debug.h"
53 extern const struct qed_common_ops qed_common_ops_pass
;
55 #define QED_MAJOR_VERSION 8
56 #define QED_MINOR_VERSION 33
57 #define QED_REVISION_VERSION 0
58 #define QED_ENGINEERING_VERSION 20
61 ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
62 (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION)
64 #define STORM_FW_VERSION \
65 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
66 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
68 #define MAX_HWFNS_PER_DEVICE (4)
72 #define QED_WFQ_UNIT 100
74 #define QED_WID_SIZE (1024)
75 #define QED_MIN_WIDS (4)
76 #define QED_PF_DEMS_SIZE (4)
79 enum qed_coalescing_mode
{
80 QED_COAL_MODE_DISABLE
,
85 QED_PUT_FILE_BEGIN
= DRV_MSG_CODE_NVM_PUT_FILE_BEGIN
,
86 QED_PUT_FILE_DATA
= DRV_MSG_CODE_NVM_PUT_FILE_DATA
,
87 QED_NVM_WRITE_NVRAM
= DRV_MSG_CODE_NVM_WRITE_NVRAM
,
88 QED_GET_MCP_NVM_RESP
= 0xFFFFFF00
91 struct qed_eth_cb_ops
;
93 union qed_mcp_protocol_stats
;
94 enum qed_mcp_protocol_type
;
95 enum qed_mfw_tlv_type
;
96 union qed_mfw_tlv_data
;
99 #define QED_MFW_GET_FIELD(name, field) \
100 (((name) & (field ## _MASK)) >> (field ## _SHIFT))
102 #define QED_MFW_SET_FIELD(name, field, value) \
104 (name) &= ~(field ## _MASK); \
105 (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
108 static inline u32
qed_db_addr(u32 cid
, u32 DEMS
)
110 u32 db_addr
= FIELD_VALUE(DB_LEGACY_ADDR_DEMS
, DEMS
) |
111 (cid
* QED_PF_DEMS_SIZE
);
116 static inline u32
qed_db_addr_vf(u32 cid
, u32 DEMS
)
118 u32 db_addr
= FIELD_VALUE(DB_LEGACY_ADDR_DEMS
, DEMS
) |
119 FIELD_VALUE(DB_LEGACY_ADDR_ICID
, cid
);
124 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
125 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
126 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
128 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
130 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
131 (val == (cond1) ? true1 : \
132 (val == (cond2) ? true2 : def))
138 struct qed_sb_attn_info
;
140 struct qed_sb_sp_info
;
150 QED_MODE_L2GENEVE_TUNN
,
151 QED_MODE_IPGENEVE_TUNN
,
158 QED_TUNN_CLSS_MAC_VLAN
,
159 QED_TUNN_CLSS_MAC_VNI
,
160 QED_TUNN_CLSS_INNER_MAC_VLAN
,
161 QED_TUNN_CLSS_INNER_MAC_VNI
,
162 QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE
,
166 struct qed_tunn_update_type
{
169 enum qed_tunn_clss tun_cls
;
172 struct qed_tunn_update_udp_port
{
177 struct qed_tunnel_info
{
178 struct qed_tunn_update_type vxlan
;
179 struct qed_tunn_update_type l2_geneve
;
180 struct qed_tunn_update_type ip_geneve
;
181 struct qed_tunn_update_type l2_gre
;
182 struct qed_tunn_update_type ip_gre
;
184 struct qed_tunn_update_udp_port vxlan_port
;
185 struct qed_tunn_update_udp_port geneve_port
;
187 bool b_update_rx_cls
;
188 bool b_update_tx_cls
;
191 struct qed_tunn_start_params
{
192 unsigned long tunn_mode
;
195 u8 update_vxlan_udp_port
;
196 u8 update_geneve_udp_port
;
198 u8 tunn_clss_l2geneve
;
199 u8 tunn_clss_ipgeneve
;
204 struct qed_tunn_update_params
{
205 unsigned long tunn_mode_update_mask
;
206 unsigned long tunn_mode
;
209 u8 update_rx_pf_clss
;
210 u8 update_tx_pf_clss
;
211 u8 update_vxlan_udp_port
;
212 u8 update_geneve_udp_port
;
214 u8 tunn_clss_l2geneve
;
215 u8 tunn_clss_ipgeneve
;
220 /* The PCI personality is not quite synonymous to protocol ID:
221 * 1. All personalities need CORE connections
222 * 2. The Ethernet personality may support also the RoCE/iWARP protocol
224 enum qed_pci_personality
{
231 QED_PCI_DEFAULT
, /* default in shmem */
234 /* All VFs are symmetric, all counters are PF + all VFs */
241 /* HW / FW resources, output of features supported below, most information
242 * is received from MFW.
257 QED_RDMA_STATS_QUEUE
,
273 QED_PORT_MODE_DE_2X40G
,
274 QED_PORT_MODE_DE_2X50G
,
275 QED_PORT_MODE_DE_1X100G
,
276 QED_PORT_MODE_DE_4X10G_F
,
277 QED_PORT_MODE_DE_4X10G_E
,
278 QED_PORT_MODE_DE_4X20G
,
279 QED_PORT_MODE_DE_1X40G
,
280 QED_PORT_MODE_DE_2X25G
,
281 QED_PORT_MODE_DE_1X25G
,
282 QED_PORT_MODE_DE_4X25G
,
283 QED_PORT_MODE_DE_2X10G
,
294 enum qed_wol_support
{
295 QED_WOL_SUPPORT_NONE
,
299 enum qed_db_rec_exec
{
306 /* PCI personality */
307 enum qed_pci_personality personality
;
308 #define QED_IS_RDMA_PERSONALITY(dev) \
309 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
310 (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
311 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
312 #define QED_IS_ROCE_PERSONALITY(dev) \
313 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
314 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
315 #define QED_IS_IWARP_PERSONALITY(dev) \
316 ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
317 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
318 #define QED_IS_L2_PERSONALITY(dev) \
319 ((dev)->hw_info.personality == QED_PCI_ETH || \
320 QED_IS_RDMA_PERSONALITY(dev))
321 #define QED_IS_FCOE_PERSONALITY(dev) \
322 ((dev)->hw_info.personality == QED_PCI_FCOE)
323 #define QED_IS_ISCSI_PERSONALITY(dev) \
324 ((dev)->hw_info.personality == QED_PCI_ISCSI)
326 /* Resource Allocation scheme results */
327 u32 resc_start
[QED_MAX_RESC
];
328 u32 resc_num
[QED_MAX_RESC
];
329 u32 feat_num
[QED_MAX_FEATURES
];
331 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
332 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
333 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
334 RESC_NUM(_p_hwfn, resc))
335 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
337 /* Amount of traffic classes HW supports */
340 /* Amount of TCs which should be active according to DCBx or upper
341 * layer driver configuration.
347 bool multi_tc_roce_en
;
348 #define IS_QED_MULTI_TC_ROCE(p_hwfn) (((p_hwfn)->hw_info.multi_tc_roce_en))
355 unsigned char hw_mac_addr
[ETH_ALEN
];
361 struct qed_igu_info
*p_igu_info
;
365 unsigned long device_capabilities
;
368 enum qed_wol_support b_wol_support
;
371 /* maximun size of read/write commands (HW limit) */
372 #define DMAE_MAX_RW_SIZE 0x2000
374 struct qed_dmae_info
{
375 /* Mutex for synchronizing access to functions */
380 dma_addr_t completion_word_phys_addr
;
382 /* The memory location where the DMAE writes the completion
383 * value when an operation is finished on this context.
385 u32
*p_completion_word
;
387 dma_addr_t intermediate_buffer_phys_addr
;
389 /* An intermediate buffer for DMAE operations that use virtual
390 * addresses - data is DMA'd to/from this buffer and then
391 * memcpy'd to/from the virtual address
393 u32
*p_intermediate_buffer
;
395 dma_addr_t dmae_cmd_phys_addr
;
396 struct dmae_cmd
*p_dmae_cmd
;
399 struct qed_wfq_data
{
400 /* when feature is configured for at least 1 vport */
406 struct init_qm_pq_params
*qm_pq_params
;
407 struct init_qm_vport_params
*qm_vport_params
;
408 struct init_qm_port_params
*qm_port_params
;
422 u8 max_phys_tcs_per_port
;
430 struct qed_wfq_data
*wfq_data
;
434 struct qed_db_recovery_info
{
435 struct list_head list
;
437 /* Lock to protect the doorbell recovery mechanism list */
439 u32 db_recovery_counter
;
447 struct qed_storm_stats
{
448 struct storm_stats mstats
;
449 struct storm_stats pstats
;
450 struct storm_stats tstats
;
451 struct storm_stats ustats
;
455 struct fw_ver_info
*fw_ver_info
;
456 const u8
*modes_tree_buf
;
457 union init_op
*init_ops
;
462 enum qed_mf_mode_bit
{
463 /* Supports PF-classification based on tag */
466 /* Supports PF-classification based on MAC */
469 /* Supports PF-classification based on protocol type */
470 QED_MF_LLH_PROTO_CLSS
,
472 /* Requires a default PF to be set */
475 /* Allow LL2 to multicast/broadcast */
476 QED_MF_LL2_NON_UNICAST
,
478 /* Allow Cross-PF [& child VFs] Tx-switching */
479 QED_MF_INTER_PF_SWITCH
,
481 /* Unified Fabtic Port support enabled */
484 /* Disable Accelerated Receive Flow Steering (aRFS) */
487 /* Use vlan for steering */
488 QED_MF_8021Q_TAGGING
,
490 /* Use stag for steering */
491 QED_MF_8021AD_TAGGING
,
493 /* Allow DSCP to TC mapping */
494 QED_MF_DSCP_TO_TC_MAP
,
499 QED_UFP_MODE_VNIC_BW
,
503 enum qed_ufp_pri_type
{
509 struct qed_ufp_info
{
510 enum qed_ufp_pri_type pri_type
;
511 enum qed_ufp_mode mode
;
516 BAR_ID_0
, /* used for GRC */
517 BAR_ID_1
/* Used for doorbells */
520 struct qed_nvm_image_info
{
522 struct bist_nvm_image_att
*image_att
;
526 #define DRV_MODULE_VERSION \
527 __stringify(QED_MAJOR_VERSION) "." \
528 __stringify(QED_MINOR_VERSION) "." \
529 __stringify(QED_REVISION_VERSION) "." \
530 __stringify(QED_ENGINEERING_VERSION)
532 struct qed_simd_fp_handler
{
534 void (*func
)(void *);
537 enum qed_slowpath_wq_flag
{
538 QED_SLOWPATH_MFW_TLV_REQ
,
539 QED_SLOWPATH_PERIODIC_DB_REC
,
543 struct qed_dev
*cdev
;
544 u8 my_id
; /* ID inside the PF */
545 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
546 u8 rel_pf_id
; /* Relative to engine*/
548 #define QED_PATH_ID(_p_hwfn) \
549 (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
555 char name
[NAME_SIZE
];
557 bool first_on_engine
;
560 u8 num_funcs_on_engine
;
564 void __iomem
*regview
;
565 void __iomem
*doorbells
;
567 unsigned long db_size
;
570 struct qed_ptt_pool
*p_ptt_pool
;
573 struct qed_hw_info hw_info
;
575 /* rt_array (for init-tool) */
576 struct qed_rt_data rt_data
;
579 struct qed_spq
*p_spq
;
585 struct qed_consq
*p_consq
;
587 /* Slow-Path definitions */
588 struct tasklet_struct
*sp_dpc
;
589 bool b_sp_dpc_enabled
;
591 struct qed_ptt
*p_main_ptt
;
592 struct qed_ptt
*p_dpc_ptt
;
594 /* PTP will be used only by the leading function.
595 * Usage of all PTP-apis should be synchronized as result.
597 struct qed_ptt
*p_ptp_ptt
;
599 struct qed_sb_sp_info
*p_sp_sb
;
600 struct qed_sb_attn_info
*p_sb_attn
;
602 /* Protocol related */
604 struct qed_ll2_info
*p_ll2_info
;
605 struct qed_ooo_info
*p_ooo_info
;
606 struct qed_rdma_info
*p_rdma_info
;
607 struct qed_iscsi_info
*p_iscsi_info
;
608 struct qed_fcoe_info
*p_fcoe_info
;
609 struct qed_pf_params pf_params
;
611 bool b_rdma_enabled_in_prs
;
612 u32 rdma_prs_search_reg
;
614 struct qed_cxt_mngr
*p_cxt_mngr
;
616 /* Flag indicating whether interrupts are enabled or not*/
618 bool b_int_requested
;
620 /* True if the driver requests for the link */
621 bool b_drv_link_init
;
623 struct qed_vf_iov
*vf_iov_info
;
624 struct qed_pf_iov
*pf_iov_info
;
625 struct qed_mcp_info
*mcp_info
;
627 struct qed_dcbx_info
*p_dcbx_info
;
629 struct qed_ufp_info ufp_info
;
631 struct qed_dmae_info dmae_info
;
634 struct qed_qm_info qm_info
;
635 struct qed_storm_stats storm_stats
;
637 /* Buffer for unzipping firmware data */
640 struct dbg_tools_data dbg_info
;
643 /* PWM region specific data */
648 /* This is used to calculate the doorbell address */
649 u32 dpi_start_offset
;
651 /* If one of the following is set then EDPM shouldn't be used */
656 struct qed_l2_info
*p_l2_info
;
658 /* Mechanism for recovering from doorbell drop */
659 struct qed_db_recovery_info db_recovery_info
;
661 /* Nvm images number and attributes */
662 struct qed_nvm_image_info nvm_info
;
664 struct qed_ptt
*p_arfs_ptt
;
666 struct qed_simd_fp_handler simd_proto_handler
[64];
668 #ifdef CONFIG_QED_SRIOV
669 struct workqueue_struct
*iov_wq
;
670 struct delayed_work iov_task
;
671 unsigned long iov_task_flags
;
673 struct z_stream_s
*stream
;
674 bool slowpath_wq_active
;
675 struct workqueue_struct
*slowpath_wq
;
676 struct delayed_work slowpath_task
;
677 unsigned long slowpath_task_flags
;
678 u32 periodic_db_rec_count
;
684 unsigned long mem_start
;
685 unsigned long mem_end
;
690 struct qed_int_param
{
693 u8 min_msix_cnt
; /* for minimal functionality */
696 struct qed_int_params
{
697 struct qed_int_param in
;
698 struct qed_int_param out
;
699 struct msix_entry
*msix_table
;
707 struct qed_dbg_feature
{
708 struct dentry
*dentry
;
714 struct qed_dbg_params
{
715 struct qed_dbg_feature features
[DBG_FEATURE_NUM
];
723 char name
[NAME_SIZE
];
725 enum qed_dev_type type
;
726 /* Translate type/revision combo into the proper conditions */
727 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
728 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
730 #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
731 #define QED_IS_K2(dev) QED_IS_AH(dev)
735 #define QED_DEV_ID_MASK 0xff00
736 #define QED_DEV_ID_MASK_BB 0x1600
737 #define QED_DEV_ID_MASK_AH 0x8000
740 #define CHIP_NUM_MASK 0xffff
741 #define CHIP_NUM_SHIFT 16
744 #define CHIP_REV_MASK 0xf
745 #define CHIP_REV_SHIFT 12
746 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
749 #define CHIP_METAL_MASK 0xff
750 #define CHIP_METAL_SHIFT 4
753 #define CHIP_BOND_ID_MASK 0xf
754 #define CHIP_BOND_ID_SHIFT 0
757 u8 num_ports_in_engine
;
758 u8 num_funcs_in_port
;
762 unsigned long mf_bits
;
767 /* Add MF related configuration */
771 /* WoL related configurations */
773 u8 wol_mac
[ETH_ALEN
];
776 enum qed_coalescing_mode int_coalescing_mode
;
777 u16 rx_coalesce_usecs
;
778 u16 tx_coalesce_usecs
;
780 /* Start Bar offset of first hwfn */
781 void __iomem
*regview
;
782 void __iomem
*doorbells
;
784 unsigned long db_size
;
790 const struct iro
*iro_arr
;
791 #define IRO (p_hwfn->cdev->iro_arr)
795 struct qed_hwfn hwfns
[MAX_HWFNS_PER_DEVICE
];
798 struct qed_hw_sriov_info
*p_iov_info
;
799 #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info)
800 struct qed_tunnel_info tunnel
;
803 struct qed_eth_stats
*reset_stats
;
804 struct qed_fw_data
*fw_data
;
808 /* Linux specific here */
809 struct qede_dev
*edev
;
810 struct pci_dev
*pdev
;
812 #define QED_FLAG_STORAGE_STARTED (BIT(0))
815 struct pci_params pci_params
;
817 struct qed_int_params int_params
;
820 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
821 #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE)
823 /* Callbacks to protocol driver */
825 struct qed_common_cb_ops
*common
;
826 struct qed_eth_cb_ops
*eth
;
827 struct qed_fcoe_cb_ops
*fcoe
;
828 struct qed_iscsi_cb_ops
*iscsi
;
832 struct qed_dbg_params dbg_params
;
834 #ifdef CONFIG_QED_LL2
835 struct qed_cb_ll2_info
*ll2
;
836 u8 ll2_mac_address
[ETH_ALEN
];
838 DECLARE_HASHTABLE(connections
, 10);
839 const struct firmware
*firmware
;
843 u32 rdma_max_srq_sge
;
844 u16 tunn_feature_mask
;
847 #define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \
849 #define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
850 : MAX_NUM_L2_QUEUES_K2)
851 #define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \
853 #define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
854 : MAX_SB_PER_PATH_K2)
855 #define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \
859 * @brief qed_concrete_to_sw_fid - get the sw function id from
860 * the concrete value.
862 * @param concrete_fid
866 static inline u8
qed_concrete_to_sw_fid(struct qed_dev
*cdev
,
869 u8 vfid
= GET_FIELD(concrete_fid
, PXP_CONCRETE_FID_VFID
);
870 u8 pfid
= GET_FIELD(concrete_fid
, PXP_CONCRETE_FID_PFID
);
871 u8 vf_valid
= GET_FIELD(concrete_fid
,
872 PXP_CONCRETE_FID_VFVALID
);
876 sw_fid
= vfid
+ MAX_NUM_PFS
;
884 #define MAX_NUM_VOQS_E4 20
886 int qed_configure_vport_wfq(struct qed_dev
*cdev
, u16 vp_id
, u32 rate
);
887 void qed_configure_vp_wfq_on_link_change(struct qed_dev
*cdev
,
888 struct qed_ptt
*p_ptt
,
891 void qed_clean_wfq_db(struct qed_hwfn
*p_hwfn
, struct qed_ptt
*p_ptt
);
892 int qed_device_num_engines(struct qed_dev
*cdev
);
893 int qed_device_get_port_id(struct qed_dev
*cdev
);
894 void qed_set_fw_mac_addr(__le16
*fw_msb
,
895 __le16
*fw_mid
, __le16
*fw_lsb
, u8
*mac
);
897 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
899 /* Flags for indication of required queues */
900 #define PQ_FLAGS_RLS (BIT(0))
901 #define PQ_FLAGS_MCOS (BIT(1))
902 #define PQ_FLAGS_LB (BIT(2))
903 #define PQ_FLAGS_OOO (BIT(3))
904 #define PQ_FLAGS_ACK (BIT(4))
905 #define PQ_FLAGS_OFLD (BIT(5))
906 #define PQ_FLAGS_VFS (BIT(6))
907 #define PQ_FLAGS_LLT (BIT(7))
908 #define PQ_FLAGS_MTC (BIT(8))
910 /* physical queue index for cm context intialization */
911 u16
qed_get_cm_pq_idx(struct qed_hwfn
*p_hwfn
, u32 pq_flags
);
912 u16
qed_get_cm_pq_idx_mcos(struct qed_hwfn
*p_hwfn
, u8 tc
);
913 u16
qed_get_cm_pq_idx_vf(struct qed_hwfn
*p_hwfn
, u16 vf
);
914 u16
qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn
*p_hwfn
, u8 tc
);
915 u16
qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn
*p_hwfn
, u8 tc
);
917 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
919 /* doorbell recovery mechanism */
920 void qed_db_recovery_dp(struct qed_hwfn
*p_hwfn
);
921 void qed_db_recovery_execute(struct qed_hwfn
*p_hwfn
,
922 enum qed_db_rec_exec db_exec
);
923 bool qed_edpm_enabled(struct qed_hwfn
*p_hwfn
);
925 /* Other Linux specific common definitions */
926 #define DP_NAME(cdev) ((cdev)->name)
928 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
932 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
933 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
934 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
936 #define DOORBELL(cdev, db_addr, val) \
937 writel((u32)val, (void __iomem *)((u8 __iomem *)\
938 (cdev->doorbells) + (db_addr)))
941 int qed_fill_dev_info(struct qed_dev
*cdev
,
942 struct qed_dev_info
*dev_info
);
943 void qed_link_update(struct qed_hwfn
*hwfn
, struct qed_ptt
*ptt
);
944 u32
qed_unzip_data(struct qed_hwfn
*p_hwfn
,
945 u32 input_len
, u8
*input_buf
,
946 u32 max_size
, u8
*unzip_buf
);
947 void qed_get_protocol_stats(struct qed_dev
*cdev
,
948 enum qed_mcp_protocol_type type
,
949 union qed_mcp_protocol_stats
*stats
);
950 int qed_slowpath_irq_req(struct qed_hwfn
*hwfn
);
951 void qed_slowpath_irq_sync(struct qed_hwfn
*p_hwfn
);
952 int qed_mfw_tlv_req(struct qed_hwfn
*hwfn
);
954 int qed_mfw_fill_tlv_data(struct qed_hwfn
*hwfn
,
955 enum qed_mfw_tlv_type type
,
956 union qed_mfw_tlv_data
*tlv_data
);
958 void qed_hw_info_set_offload_tc(struct qed_hw_info
*p_info
, u8 tc
);
960 void qed_periodic_db_rec_start(struct qed_hwfn
*p_hwfn
);