1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
38 #include <linux/delay.h>
39 #include <linux/firmware.h>
40 #include <linux/interrupt.h>
41 #include <linux/list.h>
42 #include <linux/mutex.h>
43 #include <linux/pci.h>
44 #include <linux/slab.h>
45 #include <linux/string.h>
46 #include <linux/workqueue.h>
47 #include <linux/zlib.h>
48 #include <linux/hashtable.h>
49 #include <linux/qed/qed_if.h>
50 #include "qed_debug.h"
53 extern const struct qed_common_ops qed_common_ops_pass
;
55 #define QED_MAJOR_VERSION 8
56 #define QED_MINOR_VERSION 10
57 #define QED_REVISION_VERSION 10
58 #define QED_ENGINEERING_VERSION 21
61 ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
62 (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION)
64 #define STORM_FW_VERSION \
65 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
66 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
68 #define MAX_HWFNS_PER_DEVICE (4)
72 #define QED_WFQ_UNIT 100
74 #define QED_WID_SIZE (1024)
75 #define QED_PF_DEMS_SIZE (4)
78 enum qed_coalescing_mode
{
79 QED_COAL_MODE_DISABLE
,
83 struct qed_eth_cb_ops
;
85 union qed_mcp_protocol_stats
;
86 enum qed_mcp_protocol_type
;
89 #define QED_MFW_GET_FIELD(name, field) \
90 (((name) & (field ## _MASK)) >> (field ## _SHIFT))
92 #define QED_MFW_SET_FIELD(name, field, value) \
94 (name) &= ~((field ## _MASK) << (field ## _SHIFT)); \
95 (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
98 static inline u32
qed_db_addr(u32 cid
, u32 DEMS
)
100 u32 db_addr
= FIELD_VALUE(DB_LEGACY_ADDR_DEMS
, DEMS
) |
101 (cid
* QED_PF_DEMS_SIZE
);
106 static inline u32
qed_db_addr_vf(u32 cid
, u32 DEMS
)
108 u32 db_addr
= FIELD_VALUE(DB_LEGACY_ADDR_DEMS
, DEMS
) |
109 FIELD_VALUE(DB_LEGACY_ADDR_ICID
, cid
);
114 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
115 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
116 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
118 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
120 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
121 (val == (cond1) ? true1 : \
122 (val == (cond2) ? true2 : def))
128 struct qed_sb_attn_info
;
130 struct qed_sb_sp_info
;
140 QED_MODE_L2GENEVE_TUNN
,
141 QED_MODE_IPGENEVE_TUNN
,
148 QED_TUNN_CLSS_MAC_VLAN
,
149 QED_TUNN_CLSS_MAC_VNI
,
150 QED_TUNN_CLSS_INNER_MAC_VLAN
,
151 QED_TUNN_CLSS_INNER_MAC_VNI
,
152 QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE
,
156 struct qed_tunn_update_type
{
159 enum qed_tunn_clss tun_cls
;
162 struct qed_tunn_update_udp_port
{
167 struct qed_tunnel_info
{
168 struct qed_tunn_update_type vxlan
;
169 struct qed_tunn_update_type l2_geneve
;
170 struct qed_tunn_update_type ip_geneve
;
171 struct qed_tunn_update_type l2_gre
;
172 struct qed_tunn_update_type ip_gre
;
174 struct qed_tunn_update_udp_port vxlan_port
;
175 struct qed_tunn_update_udp_port geneve_port
;
177 bool b_update_rx_cls
;
178 bool b_update_tx_cls
;
181 struct qed_tunn_start_params
{
182 unsigned long tunn_mode
;
185 u8 update_vxlan_udp_port
;
186 u8 update_geneve_udp_port
;
188 u8 tunn_clss_l2geneve
;
189 u8 tunn_clss_ipgeneve
;
194 struct qed_tunn_update_params
{
195 unsigned long tunn_mode_update_mask
;
196 unsigned long tunn_mode
;
199 u8 update_rx_pf_clss
;
200 u8 update_tx_pf_clss
;
201 u8 update_vxlan_udp_port
;
202 u8 update_geneve_udp_port
;
204 u8 tunn_clss_l2geneve
;
205 u8 tunn_clss_ipgeneve
;
210 /* The PCI personality is not quite synonymous to protocol ID:
211 * 1. All personalities need CORE connections
212 * 2. The Ethernet personality may support also the RoCE protocol
214 enum qed_pci_personality
{
219 QED_PCI_DEFAULT
/* default in shmem */
222 /* All VFs are symmetric, all counters are PF + all VFs */
229 /* HW / FW resources, output of features supported below, most information
230 * is received from MFW.
245 QED_RDMA_STATS_QUEUE
,
261 QED_PORT_MODE_DE_2X40G
,
262 QED_PORT_MODE_DE_2X50G
,
263 QED_PORT_MODE_DE_1X100G
,
264 QED_PORT_MODE_DE_4X10G_F
,
265 QED_PORT_MODE_DE_4X10G_E
,
266 QED_PORT_MODE_DE_4X20G
,
267 QED_PORT_MODE_DE_1X40G
,
268 QED_PORT_MODE_DE_2X25G
,
269 QED_PORT_MODE_DE_1X25G
,
270 QED_PORT_MODE_DE_4X25G
,
271 QED_PORT_MODE_DE_2X10G
,
281 enum qed_wol_support
{
282 QED_WOL_SUPPORT_NONE
,
287 /* PCI personality */
288 enum qed_pci_personality personality
;
290 /* Resource Allocation scheme results */
291 u32 resc_start
[QED_MAX_RESC
];
292 u32 resc_num
[QED_MAX_RESC
];
293 u32 feat_num
[QED_MAX_FEATURES
];
295 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
296 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
297 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
298 RESC_NUM(_p_hwfn, resc))
299 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
301 /* Amount of traffic classes HW supports */
304 /* Amount of TCs which should be active according to DCBx or upper
305 * layer driver configuration.
315 unsigned char hw_mac_addr
[ETH_ALEN
];
321 struct qed_igu_info
*p_igu_info
;
325 unsigned long device_capabilities
;
328 enum qed_wol_support b_wol_support
;
331 /* maximun size of read/write commands (HW limit) */
332 #define DMAE_MAX_RW_SIZE 0x2000
334 struct qed_dmae_info
{
335 /* Mutex for synchronizing access to functions */
340 dma_addr_t completion_word_phys_addr
;
342 /* The memory location where the DMAE writes the completion
343 * value when an operation is finished on this context.
345 u32
*p_completion_word
;
347 dma_addr_t intermediate_buffer_phys_addr
;
349 /* An intermediate buffer for DMAE operations that use virtual
350 * addresses - data is DMA'd to/from this buffer and then
351 * memcpy'd to/from the virtual address
353 u32
*p_intermediate_buffer
;
355 dma_addr_t dmae_cmd_phys_addr
;
356 struct dmae_cmd
*p_dmae_cmd
;
359 struct qed_wfq_data
{
360 /* when feature is configured for at least 1 vport */
366 struct init_qm_pq_params
*qm_pq_params
;
367 struct init_qm_vport_params
*qm_vport_params
;
368 struct init_qm_port_params
*qm_port_params
;
382 u8 max_phys_tcs_per_port
;
390 struct qed_wfq_data
*wfq_data
;
399 struct qed_storm_stats
{
400 struct storm_stats mstats
;
401 struct storm_stats pstats
;
402 struct storm_stats tstats
;
403 struct storm_stats ustats
;
407 struct fw_ver_info
*fw_ver_info
;
408 const u8
*modes_tree_buf
;
409 union init_op
*init_ops
;
414 #define DRV_MODULE_VERSION \
415 __stringify(QED_MAJOR_VERSION) "." \
416 __stringify(QED_MINOR_VERSION) "." \
417 __stringify(QED_REVISION_VERSION) "." \
418 __stringify(QED_ENGINEERING_VERSION)
420 struct qed_simd_fp_handler
{
422 void (*func
)(void *);
426 struct qed_dev
*cdev
;
427 u8 my_id
; /* ID inside the PF */
428 #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
429 u8 rel_pf_id
; /* Relative to engine*/
431 #define QED_PATH_ID(_p_hwfn) \
432 (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
438 char name
[NAME_SIZE
];
440 bool first_on_engine
;
443 u8 num_funcs_on_engine
;
447 void __iomem
*regview
;
448 void __iomem
*doorbells
;
450 unsigned long db_size
;
453 struct qed_ptt_pool
*p_ptt_pool
;
456 struct qed_hw_info hw_info
;
458 /* rt_array (for init-tool) */
459 struct qed_rt_data rt_data
;
462 struct qed_spq
*p_spq
;
468 struct qed_consq
*p_consq
;
470 /* Slow-Path definitions */
471 struct tasklet_struct
*sp_dpc
;
472 bool b_sp_dpc_enabled
;
474 struct qed_ptt
*p_main_ptt
;
475 struct qed_ptt
*p_dpc_ptt
;
477 struct qed_sb_sp_info
*p_sp_sb
;
478 struct qed_sb_attn_info
*p_sb_attn
;
480 /* Protocol related */
482 struct qed_ll2_info
*p_ll2_info
;
483 struct qed_ooo_info
*p_ooo_info
;
484 struct qed_rdma_info
*p_rdma_info
;
485 struct qed_iscsi_info
*p_iscsi_info
;
486 struct qed_fcoe_info
*p_fcoe_info
;
487 struct qed_pf_params pf_params
;
489 bool b_rdma_enabled_in_prs
;
490 u32 rdma_prs_search_reg
;
492 /* Array of sb_info of all status blocks */
493 struct qed_sb_info
*sbs_info
[MAX_SB_PER_PF_MIMD
];
496 struct qed_cxt_mngr
*p_cxt_mngr
;
498 /* Flag indicating whether interrupts are enabled or not*/
500 bool b_int_requested
;
502 /* True if the driver requests for the link */
503 bool b_drv_link_init
;
505 struct qed_vf_iov
*vf_iov_info
;
506 struct qed_pf_iov
*pf_iov_info
;
507 struct qed_mcp_info
*mcp_info
;
509 struct qed_dcbx_info
*p_dcbx_info
;
511 struct qed_dmae_info dmae_info
;
514 struct qed_qm_info qm_info
;
515 struct qed_storm_stats storm_stats
;
517 /* Buffer for unzipping firmware data */
520 struct dbg_tools_data dbg_info
;
522 /* PWM region specific data */
526 /* This is used to calculate the doorbell address */
527 u32 dpi_start_offset
;
529 /* If one of the following is set then EDPM shouldn't be used */
533 struct qed_ptt
*p_arfs_ptt
;
535 /* p_ptp_ptt is valid for leading HWFN only */
536 struct qed_ptt
*p_ptp_ptt
;
537 struct qed_simd_fp_handler simd_proto_handler
[64];
539 #ifdef CONFIG_QED_SRIOV
540 struct workqueue_struct
*iov_wq
;
541 struct delayed_work iov_task
;
542 unsigned long iov_task_flags
;
545 struct z_stream_s
*stream
;
546 struct qed_roce_ll2_info
*ll2
;
552 unsigned long mem_start
;
553 unsigned long mem_end
;
558 struct qed_int_param
{
561 u8 min_msix_cnt
; /* for minimal functionality */
564 struct qed_int_params
{
565 struct qed_int_param in
;
566 struct qed_int_param out
;
567 struct msix_entry
*msix_table
;
575 struct qed_dbg_feature
{
576 struct dentry
*dentry
;
582 struct qed_dbg_params
{
583 struct qed_dbg_feature features
[DBG_FEATURE_NUM
];
591 char name
[NAME_SIZE
];
593 enum qed_dev_type type
;
594 /* Translate type/revision combo into the proper conditions */
595 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
596 #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \
598 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
600 #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
601 #define QED_IS_K2(dev) QED_IS_AH(dev)
603 #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
604 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
608 #define QED_DEV_ID_MASK 0xff00
609 #define QED_DEV_ID_MASK_BB 0x1600
610 #define QED_DEV_ID_MASK_AH 0x8000
613 #define CHIP_NUM_MASK 0xffff
614 #define CHIP_NUM_SHIFT 16
617 #define CHIP_REV_MASK 0xf
618 #define CHIP_REV_SHIFT 12
619 #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev)
620 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
623 #define CHIP_METAL_MASK 0xff
624 #define CHIP_METAL_SHIFT 4
627 #define CHIP_BOND_ID_MASK 0xf
628 #define CHIP_BOND_ID_SHIFT 0
631 u8 num_ports_in_engines
;
632 u8 num_funcs_in_port
;
635 enum qed_mf_mode mf_mode
;
636 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
637 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
638 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
642 u8 ver_str
[VER_SIZE
];
644 /* Add MF related configuration */
648 /* WoL related configurations */
650 u8 wol_mac
[ETH_ALEN
];
653 enum qed_coalescing_mode int_coalescing_mode
;
654 u16 rx_coalesce_usecs
;
655 u16 tx_coalesce_usecs
;
657 /* Start Bar offset of first hwfn */
658 void __iomem
*regview
;
659 void __iomem
*doorbells
;
661 unsigned long db_size
;
667 const struct iro
*iro_arr
;
668 #define IRO (p_hwfn->cdev->iro_arr)
672 struct qed_hwfn hwfns
[MAX_HWFNS_PER_DEVICE
];
675 struct qed_hw_sriov_info
*p_iov_info
;
676 #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info)
677 struct qed_tunnel_info tunnel
;
680 struct qed_eth_stats
*reset_stats
;
681 struct qed_fw_data
*fw_data
;
685 /* Linux specific here */
686 struct qede_dev
*edev
;
687 struct pci_dev
*pdev
;
689 #define QED_FLAG_STORAGE_STARTED (BIT(0))
692 struct pci_params pci_params
;
694 struct qed_int_params int_params
;
697 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
698 #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE)
700 /* Callbacks to protocol driver */
702 struct qed_common_cb_ops
*common
;
703 struct qed_eth_cb_ops
*eth
;
704 struct qed_fcoe_cb_ops
*fcoe
;
705 struct qed_iscsi_cb_ops
*iscsi
;
709 struct qed_dbg_params dbg_params
;
711 #ifdef CONFIG_QED_LL2
712 struct qed_cb_ll2_info
*ll2
;
713 u8 ll2_mac_address
[ETH_ALEN
];
715 DECLARE_HASHTABLE(connections
, 10);
716 const struct firmware
*firmware
;
720 u32 rdma_max_srq_sge
;
721 u16 tunn_feature_mask
;
724 #define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \
726 #define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
727 : MAX_NUM_L2_QUEUES_K2)
728 #define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \
730 #define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
731 : MAX_SB_PER_PATH_K2)
732 #define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \
736 * @brief qed_concrete_to_sw_fid - get the sw function id from
737 * the concrete value.
739 * @param concrete_fid
743 static inline u8
qed_concrete_to_sw_fid(struct qed_dev
*cdev
,
746 u8 vfid
= GET_FIELD(concrete_fid
, PXP_CONCRETE_FID_VFID
);
747 u8 pfid
= GET_FIELD(concrete_fid
, PXP_CONCRETE_FID_PFID
);
748 u8 vf_valid
= GET_FIELD(concrete_fid
,
749 PXP_CONCRETE_FID_VFVALID
);
753 sw_fid
= vfid
+ MAX_NUM_PFS
;
763 int qed_configure_vport_wfq(struct qed_dev
*cdev
, u16 vp_id
, u32 rate
);
764 void qed_configure_vp_wfq_on_link_change(struct qed_dev
*cdev
,
765 struct qed_ptt
*p_ptt
,
768 void qed_clean_wfq_db(struct qed_hwfn
*p_hwfn
, struct qed_ptt
*p_ptt
);
769 int qed_device_num_engines(struct qed_dev
*cdev
);
770 int qed_device_get_port_id(struct qed_dev
*cdev
);
772 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
774 /* Flags for indication of required queues */
775 #define PQ_FLAGS_RLS (BIT(0))
776 #define PQ_FLAGS_MCOS (BIT(1))
777 #define PQ_FLAGS_LB (BIT(2))
778 #define PQ_FLAGS_OOO (BIT(3))
779 #define PQ_FLAGS_ACK (BIT(4))
780 #define PQ_FLAGS_OFLD (BIT(5))
781 #define PQ_FLAGS_VFS (BIT(6))
782 #define PQ_FLAGS_LLT (BIT(7))
784 /* physical queue index for cm context intialization */
785 u16
qed_get_cm_pq_idx(struct qed_hwfn
*p_hwfn
, u32 pq_flags
);
786 u16
qed_get_cm_pq_idx_mcos(struct qed_hwfn
*p_hwfn
, u8 tc
);
787 u16
qed_get_cm_pq_idx_vf(struct qed_hwfn
*p_hwfn
, u16 vf
);
789 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
791 /* Other Linux specific common definitions */
792 #define DP_NAME(cdev) ((cdev)->name)
794 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
798 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
799 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
800 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
802 #define DOORBELL(cdev, db_addr, val) \
803 writel((u32)val, (void __iomem *)((u8 __iomem *)\
804 (cdev->doorbells) + (db_addr)))
807 int qed_fill_dev_info(struct qed_dev
*cdev
,
808 struct qed_dev_info
*dev_info
);
809 void qed_link_update(struct qed_hwfn
*hwfn
);
810 u32
qed_unzip_data(struct qed_hwfn
*p_hwfn
,
811 u32 input_len
, u8
*input_buf
,
812 u32 max_size
, u8
*unzip_buf
);
813 void qed_get_protocol_stats(struct qed_dev
*cdev
,
814 enum qed_mcp_protocol_type type
,
815 union qed_mcp_protocol_stats
*stats
);
816 int qed_slowpath_irq_req(struct qed_hwfn
*hwfn
);
817 void qed_slowpath_irq_sync(struct qed_hwfn
*p_hwfn
);