drivers/net/ethernet/qlogic/qed/qed.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _QED_H
  34 #define _QED_H
  35
  36 #include <linux/types.h>
  37 #include <linux/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/firmware.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/list.h>
  42 #include <linux/mutex.h>
  43 #include <linux/pci.h>
  44 #include <linux/slab.h>
  45 #include <linux/string.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/zlib.h>
  48 #include <linux/hashtable.h>
  49 #include <linux/qed/qed_if.h>
  50 #include "qed_debug.h"
  51 #include "qed_hsi.h"
  52
  53 extern const struct qed_common_ops qed_common_ops_pass;
  54
  55 #define QED_MAJOR_VERSION               8
  56 #define QED_MINOR_VERSION               10
  57 #define QED_REVISION_VERSION            10
  58 #define QED_ENGINEERING_VERSION 21
  59
  60 #define QED_VERSION                                              \
  61         ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
  62          (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION)
  63
  64 #define STORM_FW_VERSION                                       \
  65         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
  66          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  67
  68 #define MAX_HWFNS_PER_DEVICE    (4)
  69 #define NAME_SIZE 16
  70 #define VER_SIZE 16
  71
  72 #define QED_WFQ_UNIT    100
  73
  74 #define QED_WID_SIZE            (1024)
  75 #define QED_PF_DEMS_SIZE        (4)
  76
  77 /* cau states */
  78 enum qed_coalescing_mode {
  79         QED_COAL_MODE_DISABLE,
  80         QED_COAL_MODE_ENABLE
  81 };
  82
  83 struct qed_eth_cb_ops;
  84 struct qed_dev_info;
  85 union qed_mcp_protocol_stats;
  86 enum qed_mcp_protocol_type;
  87
  88 /* helpers */
  89 #define QED_MFW_GET_FIELD(name, field) \
  90         (((name) & (field ## _MASK)) >> (field ## _SHIFT))
  91
  92 #define QED_MFW_SET_FIELD(name, field, value)                                  \
  93         do {                                                                   \
  94                 (name)  &= ~((field ## _MASK) << (field ## _SHIFT));           \
  95                 (name)  |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
  96         } while (0)
  97
  98 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
  99 {
 100         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 101                       (cid * QED_PF_DEMS_SIZE);
 102
 103         return db_addr;
 104 }
 105
 106 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
 107 {
 108         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 109                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 110
 111         return db_addr;
 112 }
 113
 114 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                                 \
 115         ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
 116          ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
 117
 118 #define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)
 119
 120 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 121         (val == (cond1) ? true1 :                     \
 122          (val == (cond2) ? true2 : def))
 123
 124 /* forward */
 125 struct qed_ptt_pool;
 126 struct qed_spq;
 127 struct qed_sb_info;
 128 struct qed_sb_attn_info;
 129 struct qed_cxt_mngr;
 130 struct qed_sb_sp_info;
 131 struct qed_ll2_info;
 132 struct qed_mcp_info;
 133
 134 struct qed_rt_data {
 135         u32     *init_val;
 136         bool    *b_valid;
 137 };
 138
 139 enum qed_tunn_mode {
 140         QED_MODE_L2GENEVE_TUNN,
 141         QED_MODE_IPGENEVE_TUNN,
 142         QED_MODE_L2GRE_TUNN,
 143         QED_MODE_IPGRE_TUNN,
 144         QED_MODE_VXLAN_TUNN,
 145 };
 146
 147 enum qed_tunn_clss {
 148         QED_TUNN_CLSS_MAC_VLAN,
 149         QED_TUNN_CLSS_MAC_VNI,
 150         QED_TUNN_CLSS_INNER_MAC_VLAN,
 151         QED_TUNN_CLSS_INNER_MAC_VNI,
 152         MAX_QED_TUNN_CLSS,
 153 };
 154
 155 struct qed_tunn_start_params {
 156         unsigned long   tunn_mode;
 157         u16             vxlan_udp_port;
 158         u16             geneve_udp_port;
 159         u8              update_vxlan_udp_port;
 160         u8              update_geneve_udp_port;
 161         u8              tunn_clss_vxlan;
 162         u8              tunn_clss_l2geneve;
 163         u8              tunn_clss_ipgeneve;
 164         u8              tunn_clss_l2gre;
 165         u8              tunn_clss_ipgre;
 166 };
 167
 168 struct qed_tunn_update_params {
 169         unsigned long   tunn_mode_update_mask;
 170         unsigned long   tunn_mode;
 171         u16             vxlan_udp_port;
 172         u16             geneve_udp_port;
 173         u8              update_rx_pf_clss;
 174         u8              update_tx_pf_clss;
 175         u8              update_vxlan_udp_port;
 176         u8              update_geneve_udp_port;
 177         u8              tunn_clss_vxlan;
 178         u8              tunn_clss_l2geneve;
 179         u8              tunn_clss_ipgeneve;
 180         u8              tunn_clss_l2gre;
 181         u8              tunn_clss_ipgre;
 182 };
 183
 184 /* The PCI personality is not quite synonymous to protocol ID:
 185  * 1. All personalities need CORE connections
 186  * 2. The Ethernet personality may support also the RoCE protocol
 187  */
 188 enum qed_pci_personality {
 189         QED_PCI_ETH,
 190         QED_PCI_FCOE,
 191         QED_PCI_ISCSI,
 192         QED_PCI_ETH_ROCE,
 193         QED_PCI_DEFAULT /* default in shmem */
 194 };
 195
 196 /* All VFs are symmetric, all counters are PF + all VFs */
 197 struct qed_qm_iids {
 198         u32 cids;
 199         u32 vf_cids;
 200         u32 tids;
 201 };
 202
 203 /* HW / FW resources, output of features supported below, most information
 204  * is received from MFW.
 205  */
 206 enum qed_resources {
 207         QED_SB,
 208         QED_L2_QUEUE,
 209         QED_VPORT,
 210         QED_RSS_ENG,
 211         QED_PQ,
 212         QED_RL,
 213         QED_MAC,
 214         QED_VLAN,
 215         QED_RDMA_CNQ_RAM,
 216         QED_ILT,
 217         QED_LL2_QUEUE,
 218         QED_CMDQS_CQS,
 219         QED_RDMA_STATS_QUEUE,
 220         QED_BDQ,
 221         QED_MAX_RESC,
 222 };
 223
 224 enum QED_FEATURE {
 225         QED_PF_L2_QUE,
 226         QED_VF,
 227         QED_RDMA_CNQ,
 228         QED_VF_L2_QUE,
 229         QED_FCOE_CQ,
 230         QED_MAX_FEATURES,
 231 };
 232
 233 enum QED_PORT_MODE {
 234         QED_PORT_MODE_DE_2X40G,
 235         QED_PORT_MODE_DE_2X50G,
 236         QED_PORT_MODE_DE_1X100G,
 237         QED_PORT_MODE_DE_4X10G_F,
 238         QED_PORT_MODE_DE_4X10G_E,
 239         QED_PORT_MODE_DE_4X20G,
 240         QED_PORT_MODE_DE_1X40G,
 241         QED_PORT_MODE_DE_2X25G,
 242         QED_PORT_MODE_DE_1X25G,
 243         QED_PORT_MODE_DE_4X25G,
 244         QED_PORT_MODE_DE_2X10G,
 245 };
 246
 247 enum qed_dev_cap {
 248         QED_DEV_CAP_ETH,
 249         QED_DEV_CAP_FCOE,
 250         QED_DEV_CAP_ISCSI,
 251         QED_DEV_CAP_ROCE,
 252 };
 253
 254 enum qed_wol_support {
 255         QED_WOL_SUPPORT_NONE,
 256         QED_WOL_SUPPORT_PME,
 257 };
 258
 259 struct qed_hw_info {
 260         /* PCI personality */
 261         enum qed_pci_personality        personality;
 262
 263         /* Resource Allocation scheme results */
 264         u32                             resc_start[QED_MAX_RESC];
 265         u32                             resc_num[QED_MAX_RESC];
 266         u32                             feat_num[QED_MAX_FEATURES];
 267
 268 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 269 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 270 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 271                                  RESC_NUM(_p_hwfn, resc))
 272 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 273
 274         /* Amount of traffic classes HW supports */
 275         u8 num_hw_tc;
 276
 277         /* Amount of TCs which should be active according to DCBx or upper
 278          * layer driver configuration.
 279          */
 280         u8 num_active_tc;
 281         u8                              offload_tc;
 282
 283         u32                             concrete_fid;
 284         u16                             opaque_fid;
 285         u16                             ovlan;
 286         u32                             part_num[4];
 287
 288         unsigned char                   hw_mac_addr[ETH_ALEN];
 289         u64                             node_wwn;
 290         u64                             port_wwn;
 291
 292         u16                             num_fcoe_conns;
 293
 294         struct qed_igu_info             *p_igu_info;
 295
 296         u32                             port_mode;
 297         u32                             hw_mode;
 298         unsigned long           device_capabilities;
 299         u16                             mtu;
 300
 301         enum qed_wol_support b_wol_support;
 302 };
 303
 304 /* maximun size of read/write commands (HW limit) */
 305 #define DMAE_MAX_RW_SIZE        0x2000
 306
 307 struct qed_dmae_info {
 308         /* Mutex for synchronizing access to functions */
 309         struct mutex    mutex;
 310
 311         u8              channel;
 312
 313         dma_addr_t      completion_word_phys_addr;
 314
 315         /* The memory location where the DMAE writes the completion
 316          * value when an operation is finished on this context.
 317          */
 318         u32             *p_completion_word;
 319
 320         dma_addr_t      intermediate_buffer_phys_addr;
 321
 322         /* An intermediate buffer for DMAE operations that use virtual
 323          * addresses - data is DMA'd to/from this buffer and then
 324          * memcpy'd to/from the virtual address
 325          */
 326         u32             *p_intermediate_buffer;
 327
 328         dma_addr_t      dmae_cmd_phys_addr;
 329         struct dmae_cmd *p_dmae_cmd;
 330 };
 331
 332 struct qed_wfq_data {
 333         /* when feature is configured for at least 1 vport */
 334         u32     min_speed;
 335         bool    configured;
 336 };
 337
 338 struct qed_qm_info {
 339         struct init_qm_pq_params        *qm_pq_params;
 340         struct init_qm_vport_params     *qm_vport_params;
 341         struct init_qm_port_params      *qm_port_params;
 342         u16                             start_pq;
 343         u8                              start_vport;
 344         u16                              pure_lb_pq;
 345         u16                             offload_pq;
 346         u16                             low_latency_pq;
 347         u16                             pure_ack_pq;
 348         u16                             ooo_pq;
 349         u16                             first_vf_pq;
 350         u16                             first_mcos_pq;
 351         u16                             first_rl_pq;
 352         u16                             num_pqs;
 353         u16                             num_vf_pqs;
 354         u8                              num_vports;
 355         u8                              max_phys_tcs_per_port;
 356         u8                              ooo_tc;
 357         bool                            pf_rl_en;
 358         bool                            pf_wfq_en;
 359         bool                            vport_rl_en;
 360         bool                            vport_wfq_en;
 361         u8                              pf_wfq;
 362         u32                             pf_rl;
 363         struct qed_wfq_data             *wfq_data;
 364         u8 num_pf_rls;
 365 };
 366
 367 struct storm_stats {
 368         u32     address;
 369         u32     len;
 370 };
 371
 372 struct qed_storm_stats {
 373         struct storm_stats mstats;
 374         struct storm_stats pstats;
 375         struct storm_stats tstats;
 376         struct storm_stats ustats;
 377 };
 378
 379 struct qed_fw_data {
 380         struct fw_ver_info      *fw_ver_info;
 381         const u8                *modes_tree_buf;
 382         union init_op           *init_ops;
 383         const u32               *arr_data;
 384         u32                     init_ops_size;
 385 };
 386
 387 #define DRV_MODULE_VERSION                    \
 388         __stringify(QED_MAJOR_VERSION) "."    \
 389         __stringify(QED_MINOR_VERSION) "."    \
 390         __stringify(QED_REVISION_VERSION) "." \
 391         __stringify(QED_ENGINEERING_VERSION)
 392
 393 struct qed_simd_fp_handler {
 394         void    *token;
 395         void    (*func)(void *);
 396 };
 397
 398 struct qed_hwfn {
 399         struct qed_dev                  *cdev;
 400         u8                              my_id;          /* ID inside the PF */
 401 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 402         u8                              rel_pf_id;      /* Relative to engine*/
 403         u8                              abs_pf_id;
 404 #define QED_PATH_ID(_p_hwfn) \
 405         (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 406         u8                              port_id;
 407         bool                            b_active;
 408
 409         u32                             dp_module;
 410         u8                              dp_level;
 411         char                            name[NAME_SIZE];
 412
 413         bool                            first_on_engine;
 414         bool                            hw_init_done;
 415
 416         u8                              num_funcs_on_engine;
 417         u8 enabled_func_idx;
 418
 419         /* BAR access */
 420         void __iomem                    *regview;
 421         void __iomem                    *doorbells;
 422         u64                             db_phys_addr;
 423         unsigned long                   db_size;
 424
 425         /* PTT pool */
 426         struct qed_ptt_pool             *p_ptt_pool;
 427
 428         /* HW info */
 429         struct qed_hw_info              hw_info;
 430
 431         /* rt_array (for init-tool) */
 432         struct qed_rt_data              rt_data;
 433
 434         /* SPQ */
 435         struct qed_spq                  *p_spq;
 436
 437         /* EQ */
 438         struct qed_eq                   *p_eq;
 439
 440         /* Consolidate Q*/
 441         struct qed_consq                *p_consq;
 442
 443         /* Slow-Path definitions */
 444         struct tasklet_struct           *sp_dpc;
 445         bool                            b_sp_dpc_enabled;
 446
 447         struct qed_ptt                  *p_main_ptt;
 448         struct qed_ptt                  *p_dpc_ptt;
 449
 450         struct qed_sb_sp_info           *p_sp_sb;
 451         struct qed_sb_attn_info         *p_sb_attn;
 452
 453         /* Protocol related */
 454         bool                            using_ll2;
 455         struct qed_ll2_info             *p_ll2_info;
 456         struct qed_ooo_info             *p_ooo_info;
 457         struct qed_rdma_info            *p_rdma_info;
 458         struct qed_iscsi_info           *p_iscsi_info;
 459         struct qed_fcoe_info            *p_fcoe_info;
 460         struct qed_pf_params            pf_params;
 461
 462         bool b_rdma_enabled_in_prs;
 463         u32 rdma_prs_search_reg;
 464
 465         /* Array of sb_info of all status blocks */
 466         struct qed_sb_info              *sbs_info[MAX_SB_PER_PF_MIMD];
 467         u16                             num_sbs;
 468
 469         struct qed_cxt_mngr             *p_cxt_mngr;
 470
 471         /* Flag indicating whether interrupts are enabled or not*/
 472         bool                            b_int_enabled;
 473         bool                            b_int_requested;
 474
 475         /* True if the driver requests for the link */
 476         bool                            b_drv_link_init;
 477
 478         struct qed_vf_iov               *vf_iov_info;
 479         struct qed_pf_iov               *pf_iov_info;
 480         struct qed_mcp_info             *mcp_info;
 481
 482         struct qed_dcbx_info            *p_dcbx_info;
 483
 484         struct qed_dmae_info            dmae_info;
 485
 486         /* QM init */
 487         struct qed_qm_info              qm_info;
 488         struct qed_storm_stats          storm_stats;
 489
 490         /* Buffer for unzipping firmware data */
 491         void                            *unzip_buf;
 492
 493         struct dbg_tools_data           dbg_info;
 494
 495         /* PWM region specific data */
 496         u32                             dpi_size;
 497         u32                             dpi_count;
 498
 499         /* This is used to calculate the doorbell address */
 500         u32 dpi_start_offset;
 501
 502         /* If one of the following is set then EDPM shouldn't be used */
 503         u8 dcbx_no_edpm;
 504         u8 db_bar_no_edpm;
 505
 506         /* p_ptp_ptt is valid for leading HWFN only */
 507         struct qed_ptt *p_ptp_ptt;
 508         struct qed_simd_fp_handler      simd_proto_handler[64];
 509
 510 #ifdef CONFIG_QED_SRIOV
 511         struct workqueue_struct *iov_wq;
 512         struct delayed_work iov_task;
 513         unsigned long iov_task_flags;
 514 #endif
 515
 516         struct z_stream_s               *stream;
 517         struct qed_roce_ll2_info        *ll2;
 518 };
 519
 520 struct pci_params {
 521         int             pm_cap;
 522
 523         unsigned long   mem_start;
 524         unsigned long   mem_end;
 525         unsigned int    irq;
 526         u8              pf_num;
 527 };
 528
 529 struct qed_int_param {
 530         u32     int_mode;
 531         u8      num_vectors;
 532         u8      min_msix_cnt; /* for minimal functionality */
 533 };
 534
 535 struct qed_int_params {
 536         struct qed_int_param    in;
 537         struct qed_int_param    out;
 538         struct msix_entry       *msix_table;
 539         bool                    fp_initialized;
 540         u8                      fp_msix_base;
 541         u8                      fp_msix_cnt;
 542         u8                      rdma_msix_base;
 543         u8                      rdma_msix_cnt;
 544 };
 545
 546 struct qed_dbg_feature {
 547         struct dentry *dentry;
 548         u8 *dump_buf;
 549         u32 buf_size;
 550         u32 dumped_dwords;
 551 };
 552
 553 struct qed_dbg_params {
 554         struct qed_dbg_feature features[DBG_FEATURE_NUM];
 555         u8 engine_for_debug;
 556         bool print_data;
 557 };
 558
 559 struct qed_dev {
 560         u32     dp_module;
 561         u8      dp_level;
 562         char    name[NAME_SIZE];
 563
 564         enum    qed_dev_type type;
 565 /* Translate type/revision combo into the proper conditions */
 566 #define QED_IS_BB(dev)  ((dev)->type == QED_DEV_TYPE_BB)
 567 #define QED_IS_BB_A0(dev)       (QED_IS_BB(dev) && \
 568                                  CHIP_REV_IS_A0(dev))
 569 #define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \
 570                                  CHIP_REV_IS_B0(dev))
 571 #define QED_IS_AH(dev)  ((dev)->type == QED_DEV_TYPE_AH)
 572 #define QED_IS_K2(dev)  QED_IS_AH(dev)
 573
 574 #define QED_GET_TYPE(dev)       (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
 575                                  QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
 576
 577         u16     vendor_id;
 578         u16     device_id;
 579 #define QED_DEV_ID_MASK         0xff00
 580 #define QED_DEV_ID_MASK_BB      0x1600
 581 #define QED_DEV_ID_MASK_AH      0x8000
 582
 583         u16     chip_num;
 584 #define CHIP_NUM_MASK                   0xffff
 585 #define CHIP_NUM_SHIFT                  16
 586
 587         u16     chip_rev;
 588 #define CHIP_REV_MASK                   0xf
 589 #define CHIP_REV_SHIFT                  12
 590 #define CHIP_REV_IS_A0(_cdev)   (!(_cdev)->chip_rev)
 591 #define CHIP_REV_IS_B0(_cdev)   ((_cdev)->chip_rev == 1)
 592
 593         u16                             chip_metal;
 594 #define CHIP_METAL_MASK                 0xff
 595 #define CHIP_METAL_SHIFT                4
 596
 597         u16                             chip_bond_id;
 598 #define CHIP_BOND_ID_MASK               0xf
 599 #define CHIP_BOND_ID_SHIFT              0
 600
 601         u8                              num_engines;
 602         u8                              num_ports_in_engines;
 603         u8                              num_funcs_in_port;
 604
 605         u8                              path_id;
 606         enum qed_mf_mode                mf_mode;
 607 #define IS_MF_DEFAULT(_p_hwfn)  (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
 608 #define IS_MF_SI(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
 609 #define IS_MF_SD(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
 610
 611         int                             pcie_width;
 612         int                             pcie_speed;
 613         u8                              ver_str[VER_SIZE];
 614
 615         /* Add MF related configuration */
 616         u8                              mcp_rev;
 617         u8                              boot_mode;
 618
 619         /* WoL related configurations */
 620         u8 wol_config;
 621         u8 wol_mac[ETH_ALEN];
 622
 623         u32                             int_mode;
 624         enum qed_coalescing_mode        int_coalescing_mode;
 625         u16                             rx_coalesce_usecs;
 626         u16                             tx_coalesce_usecs;
 627
 628         /* Start Bar offset of first hwfn */
 629         void __iomem                    *regview;
 630         void __iomem                    *doorbells;
 631         u64                             db_phys_addr;
 632         unsigned long                   db_size;
 633
 634         /* PCI */
 635         u8                              cache_shift;
 636
 637         /* Init */
 638         const struct iro                *iro_arr;
 639 #define IRO (p_hwfn->cdev->iro_arr)
 640
 641         /* HW functions */
 642         u8                              num_hwfns;
 643         struct qed_hwfn                 hwfns[MAX_HWFNS_PER_DEVICE];
 644
 645         /* SRIOV */
 646         struct qed_hw_sriov_info *p_iov_info;
 647 #define IS_QED_SRIOV(cdev)              (!!(cdev)->p_iov_info)
 648
 649         unsigned long                   tunn_mode;
 650
 651         bool                            b_is_vf;
 652         u32                             drv_type;
 653         struct qed_eth_stats            *reset_stats;
 654         struct qed_fw_data              *fw_data;
 655
 656         u32                             mcp_nvm_resp;
 657
 658         /* Linux specific here */
 659         struct  qede_dev                *edev;
 660         struct  pci_dev                 *pdev;
 661         u32 flags;
 662 #define QED_FLAG_STORAGE_STARTED        (BIT(0))
 663         int                             msg_enable;
 664
 665         struct pci_params               pci_params;
 666
 667         struct qed_int_params           int_params;
 668
 669         u8                              protocol;
 670 #define IS_QED_ETH_IF(cdev)     ((cdev)->protocol == QED_PROTOCOL_ETH)
 671 #define IS_QED_FCOE_IF(cdev)    ((cdev)->protocol == QED_PROTOCOL_FCOE)
 672
 673         /* Callbacks to protocol driver */
 674         union {
 675                 struct qed_common_cb_ops        *common;
 676                 struct qed_eth_cb_ops           *eth;
 677                 struct qed_fcoe_cb_ops          *fcoe;
 678                 struct qed_iscsi_cb_ops         *iscsi;
 679         } protocol_ops;
 680         void                            *ops_cookie;
 681
 682         struct qed_dbg_params           dbg_params;
 683
 684 #ifdef CONFIG_QED_LL2
 685         struct qed_cb_ll2_info          *ll2;
 686         u8                              ll2_mac_address[ETH_ALEN];
 687 #endif
 688         DECLARE_HASHTABLE(connections, 10);
 689         const struct firmware           *firmware;
 690
 691         u32 rdma_max_sge;
 692         u32 rdma_max_inline;
 693         u32 rdma_max_srq_sge;
 694 };
 695
 696 #define NUM_OF_VFS(dev)         (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \
 697                                                 : MAX_NUM_VFS_K2)
 698 #define NUM_OF_L2_QUEUES(dev)   (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 699                                                 : MAX_NUM_L2_QUEUES_K2)
 700 #define NUM_OF_PORTS(dev)       (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 701                                                 : MAX_NUM_PORTS_K2)
 702 #define NUM_OF_SBS(dev)         (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 703                                                 : MAX_SB_PER_PATH_K2)
 704 #define NUM_OF_ENG_PFS(dev)     (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \
 705                                                 : MAX_NUM_PFS_K2)
 706
 707 /**
 708  * @brief qed_concrete_to_sw_fid - get the sw function id from
 709  *        the concrete value.
 710  *
 711  * @param concrete_fid
 712  *
 713  * @return inline u8
 714  */
 715 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
 716                                         u32 concrete_fid)
 717 {
 718         u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 719         u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 720         u8 vf_valid = GET_FIELD(concrete_fid,
 721                                 PXP_CONCRETE_FID_VFVALID);
 722         u8 sw_fid;
 723
 724         if (vf_valid)
 725                 sw_fid = vfid + MAX_NUM_PFS;
 726         else
 727                 sw_fid = pfid;
 728
 729         return sw_fid;
 730 }
 731
 732 #define PURE_LB_TC 8
 733 #define OOO_LB_TC 9
 734
 735 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
 736 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
 737                                          struct qed_ptt *p_ptt,
 738                                          u32 min_pf_rate);
 739
 740 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
 741 int qed_device_num_engines(struct qed_dev *cdev);
 742
 743 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 744
 745 /* Flags for indication of required queues */
 746 #define PQ_FLAGS_RLS    (BIT(0))
 747 #define PQ_FLAGS_MCOS   (BIT(1))
 748 #define PQ_FLAGS_LB     (BIT(2))
 749 #define PQ_FLAGS_OOO    (BIT(3))
 750 #define PQ_FLAGS_ACK    (BIT(4))
 751 #define PQ_FLAGS_OFLD   (BIT(5))
 752 #define PQ_FLAGS_VFS    (BIT(6))
 753 #define PQ_FLAGS_LLT    (BIT(7))
 754
 755 /* physical queue index for cm context intialization */
 756 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags);
 757 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc);
 758 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf);
 759
 760 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 761
 762 /* Other Linux specific common definitions */
 763 #define DP_NAME(cdev) ((cdev)->name)
 764
 765 #define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\
 766                                                 (cdev->regview) + \
 767                                                          (offset))
 768
 769 #define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))
 770 #define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
 771 #define REG_WR16(cdev, offset, val)     writew((u16)val, REG_ADDR(cdev, offset))
 772
 773 #define DOORBELL(cdev, db_addr, val)                     \
 774         writel((u32)val, (void __iomem *)((u8 __iomem *)\
 775                                           (cdev->doorbells) + (db_addr)))
 776
 777 /* Prototypes */
 778 int qed_fill_dev_info(struct qed_dev *cdev,
 779                       struct qed_dev_info *dev_info);
 780 void qed_link_update(struct qed_hwfn *hwfn);
 781 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
 782                    u32 input_len, u8 *input_buf,
 783                    u32 max_size, u8 *unzip_buf);
 784 void qed_get_protocol_stats(struct qed_dev *cdev,
 785                             enum qed_mcp_protocol_type type,
 786                             union qed_mcp_protocol_stats *stats);
 787 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
 788 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn);
 789
 790 #endif /* _QED_H */