1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/types.h>
34 #include <linux/bitops.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/errno.h>
37 #include <linux/kernel.h>
38 #include <linux/list.h>
39 #include <linux/log2.h>
40 #include <linux/pci.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/bitops.h>
46 #include "qed_dev_api.h"
49 #include "qed_init_ops.h"
50 #include "qed_reg_addr.h"
51 #include "qed_sriov.h"
53 /* Max number of connection types in HW (DQ/CDU etc.) */
54 #define MAX_CONN_TYPES PROTOCOLID_COMMON
55 #define NUM_TASK_TYPES 2
56 #define NUM_TASK_PF_SEGMENTS 4
57 #define NUM_TASK_VF_SEGMENTS 1
60 #define QM_PQ_ELEMENT_SIZE 4 /* in bytes */
62 /* Doorbell-Queue constants */
63 #define DQ_RANGE_SHIFT 4
64 #define DQ_RANGE_ALIGN BIT(DQ_RANGE_SHIFT)
66 /* Searcher constants */
67 #define SRC_MIN_NUM_ELEMS 256
69 /* Timers constants */
71 #define TM_ALIGN BIT(TM_SHIFT)
72 #define TM_ELEM_SIZE 4
74 /* For RoCE we configure to 64K to cover for RoCE max tasks 256K purpose. */
75 #define ILT_DEFAULT_HW_P_SIZE (IS_ENABLED(CONFIG_QED_RDMA) ? 4 : 3)
77 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
78 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET
80 /* ILT entry structure */
81 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL
82 #define ILT_ENTRY_PHY_ADDR_SHIFT 0
83 #define ILT_ENTRY_VALID_MASK 0x1ULL
84 #define ILT_ENTRY_VALID_SHIFT 52
85 #define ILT_ENTRY_IN_REGS 2
86 #define ILT_REG_SIZE_IN_BYTES 4
88 /* connection context union */
90 struct core_conn_context core_ctx
;
91 struct eth_conn_context eth_ctx
;
92 struct iscsi_conn_context iscsi_ctx
;
93 struct roce_conn_context roce_ctx
;
96 /* TYPE-0 task context - iSCSI */
97 union type0_task_context
{
98 struct iscsi_task_context iscsi_ctx
;
101 /* TYPE-1 task context - ROCE */
102 union type1_task_context
{
103 struct rdma_task_context roce_ctx
;
111 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
112 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
114 #define CONN_CXT_SIZE(p_hwfn) \
115 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
117 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
119 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
120 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
122 /* Alignment is inherent to the type1_task_context structure */
123 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
125 /* PF per protocl configuration object */
126 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
127 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
135 struct qed_conn_type_cfg
{
139 struct qed_tid_seg tid_seg
[TASK_SEGMENTS
];
142 /* ILT Client configuration, Per connection type (protocol) resources. */
143 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
144 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
147 #define CDUT_SEG_BLK(n) (1 + (u8)(n))
148 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_ ## X ## _SEGMENTS)
160 struct ilt_cfg_pair
{
165 struct qed_ilt_cli_blk
{
166 u32 total_size
; /* 0 means not active */
167 u32 real_size_in_page
;
169 u32 dynamic_line_cnt
;
172 struct qed_ilt_client_cfg
{
176 struct ilt_cfg_pair first
;
177 struct ilt_cfg_pair last
;
178 struct ilt_cfg_pair p_size
;
180 /* ILT client blocks for PF */
181 struct qed_ilt_cli_blk pf_blks
[ILT_CLI_PF_BLOCKS
];
184 /* ILT client blocks for VFs */
185 struct qed_ilt_cli_blk vf_blks
[ILT_CLI_VF_BLOCKS
];
191 * Protocol acquired CID lists
192 * PF start line in ILT
200 struct qed_cid_acquired_map
{
203 unsigned long *cid_map
;
206 struct qed_cxt_mngr
{
207 /* Per protocl configuration */
208 struct qed_conn_type_cfg conn_cfg
[MAX_CONN_TYPES
];
210 /* computed ILT structure */
211 struct qed_ilt_client_cfg clients
[ILT_CLI_MAX
];
213 /* Task type sizes */
214 u32 task_type_size
[NUM_TASK_TYPES
];
216 /* total number of VFs for this hwfn -
217 * ALL VFs are symmetric in terms of HW resources
221 /* total number of SRQ's for this hwfn */
225 struct qed_cid_acquired_map acquired
[MAX_CONN_TYPES
];
227 /* ILT shadow table */
228 struct qed_dma_mem
*ilt_shadow
;
231 /* Mutex for a dynamic ILT allocation */
235 struct qed_dma_mem
*t2
;
240 static bool src_proto(enum protocol_type type
)
242 return type
== PROTOCOLID_ISCSI
||
243 type
== PROTOCOLID_ROCE
;
246 static bool tm_cid_proto(enum protocol_type type
)
248 return type
== PROTOCOLID_ISCSI
||
249 type
== PROTOCOLID_ROCE
;
252 /* counts the iids for the CDU/CDUC ILT client configuration */
253 struct qed_cdu_iids
{
258 static void qed_cxt_cdu_iids(struct qed_cxt_mngr
*p_mngr
,
259 struct qed_cdu_iids
*iids
)
263 for (type
= 0; type
< MAX_CONN_TYPES
; type
++) {
264 iids
->pf_cids
+= p_mngr
->conn_cfg
[type
].cid_count
;
265 iids
->per_vf_cids
+= p_mngr
->conn_cfg
[type
].cids_per_vf
;
269 /* counts the iids for the Searcher block configuration */
270 struct qed_src_iids
{
275 static void qed_cxt_src_iids(struct qed_cxt_mngr
*p_mngr
,
276 struct qed_src_iids
*iids
)
280 for (i
= 0; i
< MAX_CONN_TYPES
; i
++) {
284 iids
->pf_cids
+= p_mngr
->conn_cfg
[i
].cid_count
;
285 iids
->per_vf_cids
+= p_mngr
->conn_cfg
[i
].cids_per_vf
;
289 /* counts the iids for the Timers block configuration */
292 u32 pf_tids
[NUM_TASK_PF_SEGMENTS
]; /* per segment */
298 static void qed_cxt_tm_iids(struct qed_cxt_mngr
*p_mngr
,
299 struct qed_tm_iids
*iids
)
303 for (i
= 0; i
< MAX_CONN_TYPES
; i
++) {
304 struct qed_conn_type_cfg
*p_cfg
= &p_mngr
->conn_cfg
[i
];
306 if (tm_cid_proto(i
)) {
307 iids
->pf_cids
+= p_cfg
->cid_count
;
308 iids
->per_vf_cids
+= p_cfg
->cids_per_vf
;
312 iids
->pf_cids
= roundup(iids
->pf_cids
, TM_ALIGN
);
313 iids
->per_vf_cids
= roundup(iids
->per_vf_cids
, TM_ALIGN
);
314 iids
->per_vf_tids
= roundup(iids
->per_vf_tids
, TM_ALIGN
);
316 for (iids
->pf_tids_total
= 0, j
= 0; j
< NUM_TASK_PF_SEGMENTS
; j
++) {
317 iids
->pf_tids
[j
] = roundup(iids
->pf_tids
[j
], TM_ALIGN
);
318 iids
->pf_tids_total
+= iids
->pf_tids
[j
];
322 static void qed_cxt_qm_iids(struct qed_hwfn
*p_hwfn
,
323 struct qed_qm_iids
*iids
)
325 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
326 struct qed_tid_seg
*segs
;
327 u32 vf_cids
= 0, type
, j
;
330 for (type
= 0; type
< MAX_CONN_TYPES
; type
++) {
331 iids
->cids
+= p_mngr
->conn_cfg
[type
].cid_count
;
332 vf_cids
+= p_mngr
->conn_cfg
[type
].cids_per_vf
;
334 segs
= p_mngr
->conn_cfg
[type
].tid_seg
;
335 /* for each segment there is at most one
336 * protocol for which count is not 0.
338 for (j
= 0; j
< NUM_TASK_PF_SEGMENTS
; j
++)
339 iids
->tids
+= segs
[j
].count
;
341 /* The last array elelment is for the VFs. As for PF
342 * segments there can be only one protocol for
343 * which this value is not 0.
345 vf_tids
+= segs
[NUM_TASK_PF_SEGMENTS
].count
;
348 iids
->vf_cids
+= vf_cids
* p_mngr
->vf_count
;
349 iids
->tids
+= vf_tids
* p_mngr
->vf_count
;
351 DP_VERBOSE(p_hwfn
, QED_MSG_ILT
,
352 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
353 iids
->cids
, iids
->vf_cids
, iids
->tids
, vf_tids
);
356 static struct qed_tid_seg
*qed_cxt_tid_seg_info(struct qed_hwfn
*p_hwfn
,
359 struct qed_cxt_mngr
*p_cfg
= p_hwfn
->p_cxt_mngr
;
362 /* Find the protocol with tid count > 0 for this segment.
363 * Note: there can only be one and this is already validated.
365 for (i
= 0; i
< MAX_CONN_TYPES
; i
++)
366 if (p_cfg
->conn_cfg
[i
].tid_seg
[seg
].count
)
367 return &p_cfg
->conn_cfg
[i
].tid_seg
[seg
];
371 static void qed_cxt_set_srq_count(struct qed_hwfn
*p_hwfn
, u32 num_srqs
)
373 struct qed_cxt_mngr
*p_mgr
= p_hwfn
->p_cxt_mngr
;
375 p_mgr
->srq_count
= num_srqs
;
378 static u32
qed_cxt_get_srq_count(struct qed_hwfn
*p_hwfn
)
380 struct qed_cxt_mngr
*p_mgr
= p_hwfn
->p_cxt_mngr
;
382 return p_mgr
->srq_count
;
385 /* set the iids count per protocol */
386 static void qed_cxt_set_proto_cid_count(struct qed_hwfn
*p_hwfn
,
387 enum protocol_type type
,
388 u32 cid_count
, u32 vf_cid_cnt
)
390 struct qed_cxt_mngr
*p_mgr
= p_hwfn
->p_cxt_mngr
;
391 struct qed_conn_type_cfg
*p_conn
= &p_mgr
->conn_cfg
[type
];
393 p_conn
->cid_count
= roundup(cid_count
, DQ_RANGE_ALIGN
);
394 p_conn
->cids_per_vf
= roundup(vf_cid_cnt
, DQ_RANGE_ALIGN
);
396 if (type
== PROTOCOLID_ROCE
) {
397 u32 page_sz
= p_mgr
->clients
[ILT_CLI_CDUC
].p_size
.val
;
398 u32 cxt_size
= CONN_CXT_SIZE(p_hwfn
);
399 u32 elems_per_page
= ILT_PAGE_IN_BYTES(page_sz
) / cxt_size
;
401 p_conn
->cid_count
= roundup(p_conn
->cid_count
, elems_per_page
);
405 u32
qed_cxt_get_proto_cid_count(struct qed_hwfn
*p_hwfn
,
406 enum protocol_type type
, u32
*vf_cid
)
409 *vf_cid
= p_hwfn
->p_cxt_mngr
->conn_cfg
[type
].cids_per_vf
;
411 return p_hwfn
->p_cxt_mngr
->conn_cfg
[type
].cid_count
;
414 u32
qed_cxt_get_proto_cid_start(struct qed_hwfn
*p_hwfn
,
415 enum protocol_type type
)
417 return p_hwfn
->p_cxt_mngr
->acquired
[type
].start_cid
;
420 u32
qed_cxt_get_proto_tid_count(struct qed_hwfn
*p_hwfn
,
421 enum protocol_type type
)
426 for (i
= 0; i
< TASK_SEGMENTS
; i
++)
427 cnt
+= p_hwfn
->p_cxt_mngr
->conn_cfg
[type
].tid_seg
[i
].count
;
432 static void qed_cxt_set_proto_tid_count(struct qed_hwfn
*p_hwfn
,
433 enum protocol_type proto
,
435 u8 seg_type
, u32 count
, bool has_fl
)
437 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
438 struct qed_tid_seg
*p_seg
= &p_mngr
->conn_cfg
[proto
].tid_seg
[seg
];
440 p_seg
->count
= count
;
441 p_seg
->has_fl_mem
= has_fl
;
442 p_seg
->type
= seg_type
;
445 static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg
*p_cli
,
446 struct qed_ilt_cli_blk
*p_blk
,
447 u32 start_line
, u32 total_size
, u32 elem_size
)
449 u32 ilt_size
= ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
);
451 /* verify thatits called only once for each block */
452 if (p_blk
->total_size
)
455 p_blk
->total_size
= total_size
;
456 p_blk
->real_size_in_page
= 0;
458 p_blk
->real_size_in_page
= (ilt_size
/ elem_size
) * elem_size
;
459 p_blk
->start_line
= start_line
;
462 static void qed_ilt_cli_adv_line(struct qed_hwfn
*p_hwfn
,
463 struct qed_ilt_client_cfg
*p_cli
,
464 struct qed_ilt_cli_blk
*p_blk
,
465 u32
*p_line
, enum ilt_clients client_id
)
467 if (!p_blk
->total_size
)
471 p_cli
->first
.val
= *p_line
;
473 p_cli
->active
= true;
474 *p_line
+= DIV_ROUND_UP(p_blk
->total_size
, p_blk
->real_size_in_page
);
475 p_cli
->last
.val
= *p_line
- 1;
477 DP_VERBOSE(p_hwfn
, QED_MSG_ILT
,
478 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n",
479 client_id
, p_cli
->first
.val
,
480 p_cli
->last
.val
, p_blk
->total_size
,
481 p_blk
->real_size_in_page
, p_blk
->start_line
);
484 static u32
qed_ilt_get_dynamic_line_cnt(struct qed_hwfn
*p_hwfn
,
485 enum ilt_clients ilt_client
)
487 u32 cid_count
= p_hwfn
->p_cxt_mngr
->conn_cfg
[PROTOCOLID_ROCE
].cid_count
;
488 struct qed_ilt_client_cfg
*p_cli
;
489 u32 lines_to_skip
= 0;
492 if (ilt_client
== ILT_CLI_CDUC
) {
493 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUC
];
495 cxts_per_p
= ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) /
496 (u32
) CONN_CXT_SIZE(p_hwfn
);
498 lines_to_skip
= cid_count
/ cxts_per_p
;
501 return lines_to_skip
;
504 int qed_cxt_cfg_ilt_compute(struct qed_hwfn
*p_hwfn
)
506 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
507 u32 curr_line
, total
, i
, task_size
, line
;
508 struct qed_ilt_client_cfg
*p_cli
;
509 struct qed_ilt_cli_blk
*p_blk
;
510 struct qed_cdu_iids cdu_iids
;
511 struct qed_src_iids src_iids
;
512 struct qed_qm_iids qm_iids
;
513 struct qed_tm_iids tm_iids
;
514 struct qed_tid_seg
*p_seg
;
516 memset(&qm_iids
, 0, sizeof(qm_iids
));
517 memset(&cdu_iids
, 0, sizeof(cdu_iids
));
518 memset(&src_iids
, 0, sizeof(src_iids
));
519 memset(&tm_iids
, 0, sizeof(tm_iids
));
521 p_mngr
->pf_start_line
= RESC_START(p_hwfn
, QED_ILT
);
523 DP_VERBOSE(p_hwfn
, QED_MSG_ILT
,
524 "hwfn [%d] - Set context manager starting line to be 0x%08x\n",
525 p_hwfn
->my_id
, p_hwfn
->p_cxt_mngr
->pf_start_line
);
528 p_cli
= &p_mngr
->clients
[ILT_CLI_CDUC
];
529 curr_line
= p_mngr
->pf_start_line
;
532 p_cli
->pf_total_lines
= 0;
534 /* get the counters for the CDUC and QM clients */
535 qed_cxt_cdu_iids(p_mngr
, &cdu_iids
);
537 p_blk
= &p_cli
->pf_blks
[CDUC_BLK
];
539 total
= cdu_iids
.pf_cids
* CONN_CXT_SIZE(p_hwfn
);
541 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
,
542 total
, CONN_CXT_SIZE(p_hwfn
));
544 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
, ILT_CLI_CDUC
);
545 p_cli
->pf_total_lines
= curr_line
- p_blk
->start_line
;
547 p_blk
->dynamic_line_cnt
= qed_ilt_get_dynamic_line_cnt(p_hwfn
,
551 p_blk
= &p_cli
->vf_blks
[CDUC_BLK
];
552 total
= cdu_iids
.per_vf_cids
* CONN_CXT_SIZE(p_hwfn
);
554 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
,
555 total
, CONN_CXT_SIZE(p_hwfn
));
557 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
, ILT_CLI_CDUC
);
558 p_cli
->vf_total_lines
= curr_line
- p_blk
->start_line
;
560 for (i
= 1; i
< p_mngr
->vf_count
; i
++)
561 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
565 p_cli
= &p_mngr
->clients
[ILT_CLI_CDUT
];
566 p_cli
->first
.val
= curr_line
;
568 /* first the 'working' task memory */
569 for (i
= 0; i
< NUM_TASK_PF_SEGMENTS
; i
++) {
570 p_seg
= qed_cxt_tid_seg_info(p_hwfn
, i
);
571 if (!p_seg
|| p_seg
->count
== 0)
574 p_blk
= &p_cli
->pf_blks
[CDUT_SEG_BLK(i
)];
575 total
= p_seg
->count
* p_mngr
->task_type_size
[p_seg
->type
];
576 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
, total
,
577 p_mngr
->task_type_size
[p_seg
->type
]);
579 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
583 /* next the 'init' task memory (forced load memory) */
584 for (i
= 0; i
< NUM_TASK_PF_SEGMENTS
; i
++) {
585 p_seg
= qed_cxt_tid_seg_info(p_hwfn
, i
);
586 if (!p_seg
|| p_seg
->count
== 0)
589 p_blk
= &p_cli
->pf_blks
[CDUT_FL_SEG_BLK(i
, PF
)];
591 if (!p_seg
->has_fl_mem
) {
592 /* The segment is active (total size pf 'working'
593 * memory is > 0) but has no FL (forced-load, Init)
596 * 1. The total-size in the corrsponding FL block of
597 * the ILT client is set to 0 - No ILT line are
598 * provisioned and no ILT memory allocated.
600 * 2. The start-line of said block is set to the
601 * start line of the matching working memory
602 * block in the ILT client. This is later used to
603 * configure the CDU segment offset registers and
604 * results in an FL command for TIDs of this
605 * segement behaves as regular load commands
606 * (loading TIDs from the working memory).
608 line
= p_cli
->pf_blks
[CDUT_SEG_BLK(i
)].start_line
;
610 qed_ilt_cli_blk_fill(p_cli
, p_blk
, line
, 0, 0);
613 total
= p_seg
->count
* p_mngr
->task_type_size
[p_seg
->type
];
615 qed_ilt_cli_blk_fill(p_cli
, p_blk
,
617 p_mngr
->task_type_size
[p_seg
->type
]);
619 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
622 p_cli
->pf_total_lines
= curr_line
- p_cli
->pf_blks
[0].start_line
;
625 p_seg
= qed_cxt_tid_seg_info(p_hwfn
, TASK_SEGMENT_VF
);
626 if (p_seg
&& p_seg
->count
) {
627 /* Stricly speaking we need to iterate over all VF
628 * task segment types, but a VF has only 1 segment
631 /* 'working' memory */
632 total
= p_seg
->count
* p_mngr
->task_type_size
[p_seg
->type
];
634 p_blk
= &p_cli
->vf_blks
[CDUT_SEG_BLK(0)];
635 qed_ilt_cli_blk_fill(p_cli
, p_blk
,
637 p_mngr
->task_type_size
[p_seg
->type
]);
639 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
643 p_blk
= &p_cli
->vf_blks
[CDUT_FL_SEG_BLK(0, VF
)];
644 if (!p_seg
->has_fl_mem
) {
645 /* see comment above */
646 line
= p_cli
->vf_blks
[CDUT_SEG_BLK(0)].start_line
;
647 qed_ilt_cli_blk_fill(p_cli
, p_blk
, line
, 0, 0);
649 task_size
= p_mngr
->task_type_size
[p_seg
->type
];
650 qed_ilt_cli_blk_fill(p_cli
, p_blk
,
651 curr_line
, total
, task_size
);
652 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
655 p_cli
->vf_total_lines
= curr_line
-
656 p_cli
->vf_blks
[0].start_line
;
658 /* Now for the rest of the VFs */
659 for (i
= 1; i
< p_mngr
->vf_count
; i
++) {
660 p_blk
= &p_cli
->vf_blks
[CDUT_SEG_BLK(0)];
661 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
664 p_blk
= &p_cli
->vf_blks
[CDUT_FL_SEG_BLK(0, VF
)];
665 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
671 p_cli
= &p_mngr
->clients
[ILT_CLI_QM
];
672 p_blk
= &p_cli
->pf_blks
[0];
674 qed_cxt_qm_iids(p_hwfn
, &qm_iids
);
675 total
= qed_qm_pf_mem_size(p_hwfn
->rel_pf_id
, qm_iids
.cids
,
676 qm_iids
.vf_cids
, qm_iids
.tids
,
677 p_hwfn
->qm_info
.num_pqs
,
678 p_hwfn
->qm_info
.num_vf_pqs
);
682 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",
686 p_hwfn
->qm_info
.num_pqs
, p_hwfn
->qm_info
.num_vf_pqs
, total
);
688 qed_ilt_cli_blk_fill(p_cli
, p_blk
,
689 curr_line
, total
* 0x1000,
692 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
, ILT_CLI_QM
);
693 p_cli
->pf_total_lines
= curr_line
- p_blk
->start_line
;
696 p_cli
= &p_mngr
->clients
[ILT_CLI_SRC
];
697 qed_cxt_src_iids(p_mngr
, &src_iids
);
699 /* Both the PF and VFs searcher connections are stored in the per PF
700 * database. Thus sum the PF searcher cids and all the VFs searcher
703 total
= src_iids
.pf_cids
+ src_iids
.per_vf_cids
* p_mngr
->vf_count
;
705 u32 local_max
= max_t(u32
, total
,
708 total
= roundup_pow_of_two(local_max
);
710 p_blk
= &p_cli
->pf_blks
[0];
711 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
,
712 total
* sizeof(struct src_ent
),
713 sizeof(struct src_ent
));
715 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
717 p_cli
->pf_total_lines
= curr_line
- p_blk
->start_line
;
721 p_cli
= &p_mngr
->clients
[ILT_CLI_TM
];
722 qed_cxt_tm_iids(p_mngr
, &tm_iids
);
723 total
= tm_iids
.pf_cids
+ tm_iids
.pf_tids_total
;
725 p_blk
= &p_cli
->pf_blks
[0];
726 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
,
727 total
* TM_ELEM_SIZE
, TM_ELEM_SIZE
);
729 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
731 p_cli
->pf_total_lines
= curr_line
- p_blk
->start_line
;
735 total
= tm_iids
.per_vf_cids
+ tm_iids
.per_vf_tids
;
737 p_blk
= &p_cli
->vf_blks
[0];
738 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
,
739 total
* TM_ELEM_SIZE
, TM_ELEM_SIZE
);
741 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
743 p_cli
->pf_total_lines
= curr_line
- p_blk
->start_line
;
745 for (i
= 1; i
< p_mngr
->vf_count
; i
++)
746 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
750 /* TSDM (SRQ CONTEXT) */
751 total
= qed_cxt_get_srq_count(p_hwfn
);
754 p_cli
= &p_mngr
->clients
[ILT_CLI_TSDM
];
755 p_blk
= &p_cli
->pf_blks
[SRQ_BLK
];
756 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
,
757 total
* SRQ_CXT_SIZE
, SRQ_CXT_SIZE
);
759 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
761 p_cli
->pf_total_lines
= curr_line
- p_blk
->start_line
;
764 if (curr_line
- p_hwfn
->p_cxt_mngr
->pf_start_line
>
765 RESC_NUM(p_hwfn
, QED_ILT
)) {
766 DP_ERR(p_hwfn
, "too many ilt lines...#lines=%d\n",
767 curr_line
- p_hwfn
->p_cxt_mngr
->pf_start_line
);
774 static void qed_cxt_src_t2_free(struct qed_hwfn
*p_hwfn
)
776 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
782 for (i
= 0; i
< p_mngr
->t2_num_pages
; i
++)
783 if (p_mngr
->t2
[i
].p_virt
)
784 dma_free_coherent(&p_hwfn
->cdev
->pdev
->dev
,
786 p_mngr
->t2
[i
].p_virt
,
787 p_mngr
->t2
[i
].p_phys
);
793 static int qed_cxt_src_t2_alloc(struct qed_hwfn
*p_hwfn
)
795 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
796 u32 conn_num
, total_size
, ent_per_page
, psz
, i
;
797 struct qed_ilt_client_cfg
*p_src
;
798 struct qed_src_iids src_iids
;
799 struct qed_dma_mem
*p_t2
;
802 memset(&src_iids
, 0, sizeof(src_iids
));
804 /* if the SRC ILT client is inactive - there are no connection
805 * requiring the searcer, leave.
807 p_src
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_SRC
];
811 qed_cxt_src_iids(p_mngr
, &src_iids
);
812 conn_num
= src_iids
.pf_cids
+ src_iids
.per_vf_cids
* p_mngr
->vf_count
;
813 total_size
= conn_num
* sizeof(struct src_ent
);
815 /* use the same page size as the SRC ILT client */
816 psz
= ILT_PAGE_IN_BYTES(p_src
->p_size
.val
);
817 p_mngr
->t2_num_pages
= DIV_ROUND_UP(total_size
, psz
);
820 p_mngr
->t2
= kcalloc(p_mngr
->t2_num_pages
, sizeof(struct qed_dma_mem
),
827 /* allocate t2 pages */
828 for (i
= 0; i
< p_mngr
->t2_num_pages
; i
++) {
829 u32 size
= min_t(u32
, total_size
, psz
);
830 void **p_virt
= &p_mngr
->t2
[i
].p_virt
;
832 *p_virt
= dma_alloc_coherent(&p_hwfn
->cdev
->pdev
->dev
,
834 &p_mngr
->t2
[i
].p_phys
, GFP_KERNEL
);
835 if (!p_mngr
->t2
[i
].p_virt
) {
839 memset(*p_virt
, 0, size
);
840 p_mngr
->t2
[i
].size
= size
;
844 /* Set the t2 pointers */
846 /* entries per page - must be a power of two */
847 ent_per_page
= psz
/ sizeof(struct src_ent
);
849 p_mngr
->first_free
= (u64
) p_mngr
->t2
[0].p_phys
;
851 p_t2
= &p_mngr
->t2
[(conn_num
- 1) / ent_per_page
];
852 p_mngr
->last_free
= (u64
) p_t2
->p_phys
+
853 ((conn_num
- 1) & (ent_per_page
- 1)) * sizeof(struct src_ent
);
855 for (i
= 0; i
< p_mngr
->t2_num_pages
; i
++) {
856 u32 ent_num
= min_t(u32
,
859 struct src_ent
*entries
= p_mngr
->t2
[i
].p_virt
;
860 u64 p_ent_phys
= (u64
) p_mngr
->t2
[i
].p_phys
, val
;
863 for (j
= 0; j
< ent_num
- 1; j
++) {
864 val
= p_ent_phys
+ (j
+ 1) * sizeof(struct src_ent
);
865 entries
[j
].next
= cpu_to_be64(val
);
868 if (i
< p_mngr
->t2_num_pages
- 1)
869 val
= (u64
) p_mngr
->t2
[i
+ 1].p_phys
;
872 entries
[j
].next
= cpu_to_be64(val
);
880 qed_cxt_src_t2_free(p_hwfn
);
884 #define for_each_ilt_valid_client(pos, clients) \
885 for (pos = 0; pos < ILT_CLI_MAX; pos++) \
886 if (!clients[pos].active) { \
890 /* Total number of ILT lines used by this PF */
891 static u32
qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg
*ilt_clients
)
896 for_each_ilt_valid_client(i
, ilt_clients
)
897 size
+= (ilt_clients
[i
].last
.val
- ilt_clients
[i
].first
.val
+ 1);
902 static void qed_ilt_shadow_free(struct qed_hwfn
*p_hwfn
)
904 struct qed_ilt_client_cfg
*p_cli
= p_hwfn
->p_cxt_mngr
->clients
;
905 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
908 ilt_size
= qed_cxt_ilt_shadow_size(p_cli
);
910 for (i
= 0; p_mngr
->ilt_shadow
&& i
< ilt_size
; i
++) {
911 struct qed_dma_mem
*p_dma
= &p_mngr
->ilt_shadow
[i
];
914 dma_free_coherent(&p_hwfn
->cdev
->pdev
->dev
,
915 p_dma
->size
, p_dma
->p_virt
,
917 p_dma
->p_virt
= NULL
;
919 kfree(p_mngr
->ilt_shadow
);
922 static int qed_ilt_blk_alloc(struct qed_hwfn
*p_hwfn
,
923 struct qed_ilt_cli_blk
*p_blk
,
924 enum ilt_clients ilt_client
,
925 u32 start_line_offset
)
927 struct qed_dma_mem
*ilt_shadow
= p_hwfn
->p_cxt_mngr
->ilt_shadow
;
928 u32 lines
, line
, sz_left
, lines_to_skip
= 0;
930 /* Special handling for RoCE that supports dynamic allocation */
931 if ((p_hwfn
->hw_info
.personality
== QED_PCI_ETH_ROCE
) &&
932 ((ilt_client
== ILT_CLI_CDUT
) || ilt_client
== ILT_CLI_TSDM
))
935 lines_to_skip
= p_blk
->dynamic_line_cnt
;
937 if (!p_blk
->total_size
)
940 sz_left
= p_blk
->total_size
;
941 lines
= DIV_ROUND_UP(sz_left
, p_blk
->real_size_in_page
) - lines_to_skip
;
942 line
= p_blk
->start_line
+ start_line_offset
-
943 p_hwfn
->p_cxt_mngr
->pf_start_line
+ lines_to_skip
;
945 for (; lines
; lines
--) {
950 size
= min_t(u32
, sz_left
, p_blk
->real_size_in_page
);
951 p_virt
= dma_alloc_coherent(&p_hwfn
->cdev
->pdev
->dev
,
952 size
, &p_phys
, GFP_KERNEL
);
955 memset(p_virt
, 0, size
);
957 ilt_shadow
[line
].p_phys
= p_phys
;
958 ilt_shadow
[line
].p_virt
= p_virt
;
959 ilt_shadow
[line
].size
= size
;
961 DP_VERBOSE(p_hwfn
, QED_MSG_ILT
,
962 "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n",
963 line
, (u64
)p_phys
, p_virt
, size
);
972 static int qed_ilt_shadow_alloc(struct qed_hwfn
*p_hwfn
)
974 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
975 struct qed_ilt_client_cfg
*clients
= p_mngr
->clients
;
976 struct qed_ilt_cli_blk
*p_blk
;
980 size
= qed_cxt_ilt_shadow_size(clients
);
981 p_mngr
->ilt_shadow
= kcalloc(size
, sizeof(struct qed_dma_mem
),
983 if (!p_mngr
->ilt_shadow
) {
985 goto ilt_shadow_fail
;
988 DP_VERBOSE(p_hwfn
, QED_MSG_ILT
,
989 "Allocated 0x%x bytes for ilt shadow\n",
990 (u32
)(size
* sizeof(struct qed_dma_mem
)));
992 for_each_ilt_valid_client(i
, clients
) {
993 for (j
= 0; j
< ILT_CLI_PF_BLOCKS
; j
++) {
994 p_blk
= &clients
[i
].pf_blks
[j
];
995 rc
= qed_ilt_blk_alloc(p_hwfn
, p_blk
, i
, 0);
997 goto ilt_shadow_fail
;
999 for (k
= 0; k
< p_mngr
->vf_count
; k
++) {
1000 for (j
= 0; j
< ILT_CLI_VF_BLOCKS
; j
++) {
1001 u32 lines
= clients
[i
].vf_total_lines
* k
;
1003 p_blk
= &clients
[i
].vf_blks
[j
];
1004 rc
= qed_ilt_blk_alloc(p_hwfn
, p_blk
, i
, lines
);
1006 goto ilt_shadow_fail
;
1014 qed_ilt_shadow_free(p_hwfn
);
1018 static void qed_cid_map_free(struct qed_hwfn
*p_hwfn
)
1020 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1023 for (type
= 0; type
< MAX_CONN_TYPES
; type
++) {
1024 kfree(p_mngr
->acquired
[type
].cid_map
);
1025 p_mngr
->acquired
[type
].max_count
= 0;
1026 p_mngr
->acquired
[type
].start_cid
= 0;
1030 static int qed_cid_map_alloc(struct qed_hwfn
*p_hwfn
)
1032 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1036 for (type
= 0; type
< MAX_CONN_TYPES
; type
++) {
1037 u32 cid_cnt
= p_hwfn
->p_cxt_mngr
->conn_cfg
[type
].cid_count
;
1043 size
= DIV_ROUND_UP(cid_cnt
,
1044 sizeof(unsigned long) * BITS_PER_BYTE
) *
1045 sizeof(unsigned long);
1046 p_mngr
->acquired
[type
].cid_map
= kzalloc(size
, GFP_KERNEL
);
1047 if (!p_mngr
->acquired
[type
].cid_map
)
1050 p_mngr
->acquired
[type
].max_count
= cid_cnt
;
1051 p_mngr
->acquired
[type
].start_cid
= start_cid
;
1053 p_hwfn
->p_cxt_mngr
->conn_cfg
[type
].cid_start
= start_cid
;
1055 DP_VERBOSE(p_hwfn
, QED_MSG_CXT
,
1056 "Type %08x start: %08x count %08x\n",
1057 type
, p_mngr
->acquired
[type
].start_cid
,
1058 p_mngr
->acquired
[type
].max_count
);
1059 start_cid
+= cid_cnt
;
1065 qed_cid_map_free(p_hwfn
);
1069 int qed_cxt_mngr_alloc(struct qed_hwfn
*p_hwfn
)
1071 struct qed_ilt_client_cfg
*clients
;
1072 struct qed_cxt_mngr
*p_mngr
;
1075 p_mngr
= kzalloc(sizeof(*p_mngr
), GFP_KERNEL
);
1079 /* Initialize ILT client registers */
1080 clients
= p_mngr
->clients
;
1081 clients
[ILT_CLI_CDUC
].first
.reg
= ILT_CFG_REG(CDUC
, FIRST_ILT
);
1082 clients
[ILT_CLI_CDUC
].last
.reg
= ILT_CFG_REG(CDUC
, LAST_ILT
);
1083 clients
[ILT_CLI_CDUC
].p_size
.reg
= ILT_CFG_REG(CDUC
, P_SIZE
);
1085 clients
[ILT_CLI_QM
].first
.reg
= ILT_CFG_REG(QM
, FIRST_ILT
);
1086 clients
[ILT_CLI_QM
].last
.reg
= ILT_CFG_REG(QM
, LAST_ILT
);
1087 clients
[ILT_CLI_QM
].p_size
.reg
= ILT_CFG_REG(QM
, P_SIZE
);
1089 clients
[ILT_CLI_TM
].first
.reg
= ILT_CFG_REG(TM
, FIRST_ILT
);
1090 clients
[ILT_CLI_TM
].last
.reg
= ILT_CFG_REG(TM
, LAST_ILT
);
1091 clients
[ILT_CLI_TM
].p_size
.reg
= ILT_CFG_REG(TM
, P_SIZE
);
1093 clients
[ILT_CLI_SRC
].first
.reg
= ILT_CFG_REG(SRC
, FIRST_ILT
);
1094 clients
[ILT_CLI_SRC
].last
.reg
= ILT_CFG_REG(SRC
, LAST_ILT
);
1095 clients
[ILT_CLI_SRC
].p_size
.reg
= ILT_CFG_REG(SRC
, P_SIZE
);
1097 clients
[ILT_CLI_CDUT
].first
.reg
= ILT_CFG_REG(CDUT
, FIRST_ILT
);
1098 clients
[ILT_CLI_CDUT
].last
.reg
= ILT_CFG_REG(CDUT
, LAST_ILT
);
1099 clients
[ILT_CLI_CDUT
].p_size
.reg
= ILT_CFG_REG(CDUT
, P_SIZE
);
1101 clients
[ILT_CLI_TSDM
].first
.reg
= ILT_CFG_REG(TSDM
, FIRST_ILT
);
1102 clients
[ILT_CLI_TSDM
].last
.reg
= ILT_CFG_REG(TSDM
, LAST_ILT
);
1103 clients
[ILT_CLI_TSDM
].p_size
.reg
= ILT_CFG_REG(TSDM
, P_SIZE
);
1104 /* default ILT page size for all clients is 32K */
1105 for (i
= 0; i
< ILT_CLI_MAX
; i
++)
1106 p_mngr
->clients
[i
].p_size
.val
= ILT_DEFAULT_HW_P_SIZE
;
1108 /* Initialize task sizes */
1109 p_mngr
->task_type_size
[0] = TYPE0_TASK_CXT_SIZE(p_hwfn
);
1110 p_mngr
->task_type_size
[1] = TYPE1_TASK_CXT_SIZE(p_hwfn
);
1112 if (p_hwfn
->cdev
->p_iov_info
)
1113 p_mngr
->vf_count
= p_hwfn
->cdev
->p_iov_info
->total_vfs
;
1114 /* Initialize the dynamic ILT allocation mutex */
1115 mutex_init(&p_mngr
->mutex
);
1117 /* Set the cxt mangr pointer priori to further allocations */
1118 p_hwfn
->p_cxt_mngr
= p_mngr
;
1123 int qed_cxt_tables_alloc(struct qed_hwfn
*p_hwfn
)
1127 /* Allocate the ILT shadow table */
1128 rc
= qed_ilt_shadow_alloc(p_hwfn
);
1130 goto tables_alloc_fail
;
1132 /* Allocate the T2 table */
1133 rc
= qed_cxt_src_t2_alloc(p_hwfn
);
1135 goto tables_alloc_fail
;
1137 /* Allocate and initialize the acquired cids bitmaps */
1138 rc
= qed_cid_map_alloc(p_hwfn
);
1140 goto tables_alloc_fail
;
1145 qed_cxt_mngr_free(p_hwfn
);
1149 void qed_cxt_mngr_free(struct qed_hwfn
*p_hwfn
)
1151 if (!p_hwfn
->p_cxt_mngr
)
1154 qed_cid_map_free(p_hwfn
);
1155 qed_cxt_src_t2_free(p_hwfn
);
1156 qed_ilt_shadow_free(p_hwfn
);
1157 kfree(p_hwfn
->p_cxt_mngr
);
1159 p_hwfn
->p_cxt_mngr
= NULL
;
1162 void qed_cxt_mngr_setup(struct qed_hwfn
*p_hwfn
)
1164 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1167 /* Reset acquired cids */
1168 for (type
= 0; type
< MAX_CONN_TYPES
; type
++) {
1169 u32 cid_cnt
= p_hwfn
->p_cxt_mngr
->conn_cfg
[type
].cid_count
;
1174 memset(p_mngr
->acquired
[type
].cid_map
, 0,
1175 DIV_ROUND_UP(cid_cnt
,
1176 sizeof(unsigned long) * BITS_PER_BYTE
) *
1177 sizeof(unsigned long));
1182 #define CDUC_CXT_SIZE_SHIFT \
1183 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1185 #define CDUC_CXT_SIZE_MASK \
1186 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1188 #define CDUC_BLOCK_WASTE_SHIFT \
1189 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1191 #define CDUC_BLOCK_WASTE_MASK \
1192 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1194 #define CDUC_NCIB_SHIFT \
1195 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1197 #define CDUC_NCIB_MASK \
1198 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1200 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1201 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1203 #define CDUT_TYPE0_CXT_SIZE_MASK \
1204 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1205 CDUT_TYPE0_CXT_SIZE_SHIFT)
1207 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1208 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1210 #define CDUT_TYPE0_BLOCK_WASTE_MASK \
1211 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1212 CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1214 #define CDUT_TYPE0_NCIB_SHIFT \
1215 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1217 #define CDUT_TYPE0_NCIB_MASK \
1218 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1219 CDUT_TYPE0_NCIB_SHIFT)
1221 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1222 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1224 #define CDUT_TYPE1_CXT_SIZE_MASK \
1225 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1226 CDUT_TYPE1_CXT_SIZE_SHIFT)
1228 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1229 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1231 #define CDUT_TYPE1_BLOCK_WASTE_MASK \
1232 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1233 CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1235 #define CDUT_TYPE1_NCIB_SHIFT \
1236 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1238 #define CDUT_TYPE1_NCIB_MASK \
1239 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1240 CDUT_TYPE1_NCIB_SHIFT)
1242 static void qed_cdu_init_common(struct qed_hwfn
*p_hwfn
)
1244 u32 page_sz
, elems_per_page
, block_waste
, cxt_size
, cdu_params
= 0;
1246 /* CDUC - connection configuration */
1247 page_sz
= p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUC
].p_size
.val
;
1248 cxt_size
= CONN_CXT_SIZE(p_hwfn
);
1249 elems_per_page
= ILT_PAGE_IN_BYTES(page_sz
) / cxt_size
;
1250 block_waste
= ILT_PAGE_IN_BYTES(page_sz
) - elems_per_page
* cxt_size
;
1252 SET_FIELD(cdu_params
, CDUC_CXT_SIZE
, cxt_size
);
1253 SET_FIELD(cdu_params
, CDUC_BLOCK_WASTE
, block_waste
);
1254 SET_FIELD(cdu_params
, CDUC_NCIB
, elems_per_page
);
1255 STORE_RT_REG(p_hwfn
, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET
, cdu_params
);
1257 /* CDUT - type-0 tasks configuration */
1258 page_sz
= p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUT
].p_size
.val
;
1259 cxt_size
= p_hwfn
->p_cxt_mngr
->task_type_size
[0];
1260 elems_per_page
= ILT_PAGE_IN_BYTES(page_sz
) / cxt_size
;
1261 block_waste
= ILT_PAGE_IN_BYTES(page_sz
) - elems_per_page
* cxt_size
;
1263 /* cxt size and block-waste are multipes of 8 */
1265 SET_FIELD(cdu_params
, CDUT_TYPE0_CXT_SIZE
, (cxt_size
>> 3));
1266 SET_FIELD(cdu_params
, CDUT_TYPE0_BLOCK_WASTE
, (block_waste
>> 3));
1267 SET_FIELD(cdu_params
, CDUT_TYPE0_NCIB
, elems_per_page
);
1268 STORE_RT_REG(p_hwfn
, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET
, cdu_params
);
1270 /* CDUT - type-1 tasks configuration */
1271 cxt_size
= p_hwfn
->p_cxt_mngr
->task_type_size
[1];
1272 elems_per_page
= ILT_PAGE_IN_BYTES(page_sz
) / cxt_size
;
1273 block_waste
= ILT_PAGE_IN_BYTES(page_sz
) - elems_per_page
* cxt_size
;
1275 /* cxt size and block-waste are multipes of 8 */
1277 SET_FIELD(cdu_params
, CDUT_TYPE1_CXT_SIZE
, (cxt_size
>> 3));
1278 SET_FIELD(cdu_params
, CDUT_TYPE1_BLOCK_WASTE
, (block_waste
>> 3));
1279 SET_FIELD(cdu_params
, CDUT_TYPE1_NCIB
, elems_per_page
);
1280 STORE_RT_REG(p_hwfn
, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET
, cdu_params
);
1284 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1285 #define CDU_SEG_REG_TYPE_MASK 0x1
1286 #define CDU_SEG_REG_OFFSET_SHIFT 0
1287 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1289 static void qed_cdu_init_pf(struct qed_hwfn
*p_hwfn
)
1291 struct qed_ilt_client_cfg
*p_cli
;
1292 struct qed_tid_seg
*p_seg
;
1293 u32 cdu_seg_params
, offset
;
1296 static const u32 rt_type_offset_arr
[] = {
1297 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET
,
1298 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET
,
1299 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET
,
1300 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1303 static const u32 rt_type_offset_fl_arr
[] = {
1304 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET
,
1305 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET
,
1306 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET
,
1307 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1310 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUT
];
1312 /* There are initializations only for CDUT during pf Phase */
1313 for (i
= 0; i
< NUM_TASK_PF_SEGMENTS
; i
++) {
1315 p_seg
= qed_cxt_tid_seg_info(p_hwfn
, i
);
1319 /* Note: start_line is already adjusted for the CDU
1320 * segment register granularity, so we just need to
1321 * divide. Adjustment is implicit as we assume ILT
1322 * Page size is larger than 32K!
1324 offset
= (ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) *
1325 (p_cli
->pf_blks
[CDUT_SEG_BLK(i
)].start_line
-
1326 p_cli
->first
.val
)) / CDUT_SEG_ALIGNMET_IN_BYTES
;
1329 SET_FIELD(cdu_seg_params
, CDU_SEG_REG_TYPE
, p_seg
->type
);
1330 SET_FIELD(cdu_seg_params
, CDU_SEG_REG_OFFSET
, offset
);
1331 STORE_RT_REG(p_hwfn
, rt_type_offset_arr
[i
], cdu_seg_params
);
1333 offset
= (ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) *
1334 (p_cli
->pf_blks
[CDUT_FL_SEG_BLK(i
, PF
)].start_line
-
1335 p_cli
->first
.val
)) / CDUT_SEG_ALIGNMET_IN_BYTES
;
1338 SET_FIELD(cdu_seg_params
, CDU_SEG_REG_TYPE
, p_seg
->type
);
1339 SET_FIELD(cdu_seg_params
, CDU_SEG_REG_OFFSET
, offset
);
1340 STORE_RT_REG(p_hwfn
, rt_type_offset_fl_arr
[i
], cdu_seg_params
);
1344 void qed_qm_init_pf(struct qed_hwfn
*p_hwfn
)
1346 struct qed_qm_pf_rt_init_params params
;
1347 struct qed_qm_info
*qm_info
= &p_hwfn
->qm_info
;
1348 struct qed_qm_iids iids
;
1350 memset(&iids
, 0, sizeof(iids
));
1351 qed_cxt_qm_iids(p_hwfn
, &iids
);
1353 memset(¶ms
, 0, sizeof(params
));
1354 params
.port_id
= p_hwfn
->port_id
;
1355 params
.pf_id
= p_hwfn
->rel_pf_id
;
1356 params
.max_phys_tcs_per_port
= qm_info
->max_phys_tcs_per_port
;
1357 params
.is_first_pf
= p_hwfn
->first_on_engine
;
1358 params
.num_pf_cids
= iids
.cids
;
1359 params
.num_vf_cids
= iids
.vf_cids
;
1360 params
.start_pq
= qm_info
->start_pq
;
1361 params
.num_pf_pqs
= qm_info
->num_pqs
- qm_info
->num_vf_pqs
;
1362 params
.num_vf_pqs
= qm_info
->num_vf_pqs
;
1363 params
.start_vport
= qm_info
->start_vport
;
1364 params
.num_vports
= qm_info
->num_vports
;
1365 params
.pf_wfq
= qm_info
->pf_wfq
;
1366 params
.pf_rl
= qm_info
->pf_rl
;
1367 params
.pq_params
= qm_info
->qm_pq_params
;
1368 params
.vport_params
= qm_info
->qm_vport_params
;
1370 qed_qm_pf_rt_init(p_hwfn
, p_hwfn
->p_main_ptt
, ¶ms
);
1374 static int qed_cm_init_pf(struct qed_hwfn
*p_hwfn
)
1376 union qed_qm_pq_params pq_params
;
1379 /* XCM pure-LB queue */
1380 memset(&pq_params
, 0, sizeof(pq_params
));
1381 pq_params
.core
.tc
= LB_TC
;
1382 pq
= qed_get_qm_pq(p_hwfn
, PROTOCOLID_CORE
, &pq_params
);
1383 STORE_RT_REG(p_hwfn
, XCM_REG_CON_PHY_Q3_RT_OFFSET
, pq
);
1389 static void qed_dq_init_pf(struct qed_hwfn
*p_hwfn
)
1391 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1392 u32 dq_pf_max_cid
= 0, dq_vf_max_cid
= 0;
1394 dq_pf_max_cid
+= (p_mngr
->conn_cfg
[0].cid_count
>> DQ_RANGE_SHIFT
);
1395 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET
, dq_pf_max_cid
);
1397 dq_vf_max_cid
+= (p_mngr
->conn_cfg
[0].cids_per_vf
>> DQ_RANGE_SHIFT
);
1398 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET
, dq_vf_max_cid
);
1400 dq_pf_max_cid
+= (p_mngr
->conn_cfg
[1].cid_count
>> DQ_RANGE_SHIFT
);
1401 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET
, dq_pf_max_cid
);
1403 dq_vf_max_cid
+= (p_mngr
->conn_cfg
[1].cids_per_vf
>> DQ_RANGE_SHIFT
);
1404 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET
, dq_vf_max_cid
);
1406 dq_pf_max_cid
+= (p_mngr
->conn_cfg
[2].cid_count
>> DQ_RANGE_SHIFT
);
1407 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET
, dq_pf_max_cid
);
1409 dq_vf_max_cid
+= (p_mngr
->conn_cfg
[2].cids_per_vf
>> DQ_RANGE_SHIFT
);
1410 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET
, dq_vf_max_cid
);
1412 dq_pf_max_cid
+= (p_mngr
->conn_cfg
[3].cid_count
>> DQ_RANGE_SHIFT
);
1413 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET
, dq_pf_max_cid
);
1415 dq_vf_max_cid
+= (p_mngr
->conn_cfg
[3].cids_per_vf
>> DQ_RANGE_SHIFT
);
1416 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET
, dq_vf_max_cid
);
1418 dq_pf_max_cid
+= (p_mngr
->conn_cfg
[4].cid_count
>> DQ_RANGE_SHIFT
);
1419 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET
, dq_pf_max_cid
);
1421 dq_vf_max_cid
+= (p_mngr
->conn_cfg
[4].cids_per_vf
>> DQ_RANGE_SHIFT
);
1422 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET
, dq_vf_max_cid
);
1424 dq_pf_max_cid
+= (p_mngr
->conn_cfg
[5].cid_count
>> DQ_RANGE_SHIFT
);
1425 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET
, dq_pf_max_cid
);
1427 dq_vf_max_cid
+= (p_mngr
->conn_cfg
[5].cids_per_vf
>> DQ_RANGE_SHIFT
);
1428 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET
, dq_vf_max_cid
);
1430 /* Connection types 6 & 7 are not in use, yet they must be configured
1431 * as the highest possible connection. Not configuring them means the
1432 * defaults will be used, and with a large number of cids a bug may
1433 * occur, if the defaults will be smaller than dq_pf_max_cid /
1436 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET
, dq_pf_max_cid
);
1437 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET
, dq_vf_max_cid
);
1439 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET
, dq_pf_max_cid
);
1440 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET
, dq_vf_max_cid
);
1443 static void qed_ilt_bounds_init(struct qed_hwfn
*p_hwfn
)
1445 struct qed_ilt_client_cfg
*ilt_clients
;
1448 ilt_clients
= p_hwfn
->p_cxt_mngr
->clients
;
1449 for_each_ilt_valid_client(i
, ilt_clients
) {
1450 STORE_RT_REG(p_hwfn
,
1451 ilt_clients
[i
].first
.reg
,
1452 ilt_clients
[i
].first
.val
);
1453 STORE_RT_REG(p_hwfn
,
1454 ilt_clients
[i
].last
.reg
, ilt_clients
[i
].last
.val
);
1455 STORE_RT_REG(p_hwfn
,
1456 ilt_clients
[i
].p_size
.reg
,
1457 ilt_clients
[i
].p_size
.val
);
1461 static void qed_ilt_vf_bounds_init(struct qed_hwfn
*p_hwfn
)
1463 struct qed_ilt_client_cfg
*p_cli
;
1466 /* For simplicty we set the 'block' to be an ILT page */
1467 if (p_hwfn
->cdev
->p_iov_info
) {
1468 struct qed_hw_sriov_info
*p_iov
= p_hwfn
->cdev
->p_iov_info
;
1470 STORE_RT_REG(p_hwfn
,
1471 PSWRQ2_REG_VF_BASE_RT_OFFSET
,
1472 p_iov
->first_vf_in_pf
);
1473 STORE_RT_REG(p_hwfn
,
1474 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET
,
1475 p_iov
->first_vf_in_pf
+ p_iov
->total_vfs
);
1478 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUC
];
1479 blk_factor
= ilog2(ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) >> 10);
1480 if (p_cli
->active
) {
1481 STORE_RT_REG(p_hwfn
,
1482 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET
,
1484 STORE_RT_REG(p_hwfn
,
1485 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET
,
1486 p_cli
->pf_total_lines
);
1487 STORE_RT_REG(p_hwfn
,
1488 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET
,
1489 p_cli
->vf_total_lines
);
1492 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUT
];
1493 blk_factor
= ilog2(ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) >> 10);
1494 if (p_cli
->active
) {
1495 STORE_RT_REG(p_hwfn
,
1496 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET
,
1498 STORE_RT_REG(p_hwfn
,
1499 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET
,
1500 p_cli
->pf_total_lines
);
1501 STORE_RT_REG(p_hwfn
,
1502 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET
,
1503 p_cli
->vf_total_lines
);
1506 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_TM
];
1507 blk_factor
= ilog2(ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) >> 10);
1508 if (p_cli
->active
) {
1509 STORE_RT_REG(p_hwfn
,
1510 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET
, blk_factor
);
1511 STORE_RT_REG(p_hwfn
,
1512 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET
,
1513 p_cli
->pf_total_lines
);
1514 STORE_RT_REG(p_hwfn
,
1515 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET
,
1516 p_cli
->vf_total_lines
);
1520 /* ILT (PSWRQ2) PF */
1521 static void qed_ilt_init_pf(struct qed_hwfn
*p_hwfn
)
1523 struct qed_ilt_client_cfg
*clients
;
1524 struct qed_cxt_mngr
*p_mngr
;
1525 struct qed_dma_mem
*p_shdw
;
1526 u32 line
, rt_offst
, i
;
1528 qed_ilt_bounds_init(p_hwfn
);
1529 qed_ilt_vf_bounds_init(p_hwfn
);
1531 p_mngr
= p_hwfn
->p_cxt_mngr
;
1532 p_shdw
= p_mngr
->ilt_shadow
;
1533 clients
= p_hwfn
->p_cxt_mngr
->clients
;
1535 for_each_ilt_valid_client(i
, clients
) {
1536 /** Client's 1st val and RT array are absolute, ILT shadows'
1537 * lines are relative.
1539 line
= clients
[i
].first
.val
- p_mngr
->pf_start_line
;
1540 rt_offst
= PSWRQ2_REG_ILT_MEMORY_RT_OFFSET
+
1541 clients
[i
].first
.val
* ILT_ENTRY_IN_REGS
;
1543 for (; line
<= clients
[i
].last
.val
- p_mngr
->pf_start_line
;
1544 line
++, rt_offst
+= ILT_ENTRY_IN_REGS
) {
1545 u64 ilt_hw_entry
= 0;
1547 /** p_virt could be NULL incase of dynamic
1550 if (p_shdw
[line
].p_virt
) {
1551 SET_FIELD(ilt_hw_entry
, ILT_ENTRY_VALID
, 1ULL);
1552 SET_FIELD(ilt_hw_entry
, ILT_ENTRY_PHY_ADDR
,
1553 (p_shdw
[line
].p_phys
>> 12));
1555 DP_VERBOSE(p_hwfn
, QED_MSG_ILT
,
1556 "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n",
1558 (u64
)(p_shdw
[line
].p_phys
>> 12));
1561 STORE_RT_REG_AGG(p_hwfn
, rt_offst
, ilt_hw_entry
);
1566 /* SRC (Searcher) PF */
1567 static void qed_src_init_pf(struct qed_hwfn
*p_hwfn
)
1569 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1570 u32 rounded_conn_num
, conn_num
, conn_max
;
1571 struct qed_src_iids src_iids
;
1573 memset(&src_iids
, 0, sizeof(src_iids
));
1574 qed_cxt_src_iids(p_mngr
, &src_iids
);
1575 conn_num
= src_iids
.pf_cids
+ src_iids
.per_vf_cids
* p_mngr
->vf_count
;
1579 conn_max
= max_t(u32
, conn_num
, SRC_MIN_NUM_ELEMS
);
1580 rounded_conn_num
= roundup_pow_of_two(conn_max
);
1582 STORE_RT_REG(p_hwfn
, SRC_REG_COUNTFREE_RT_OFFSET
, conn_num
);
1583 STORE_RT_REG(p_hwfn
, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET
,
1584 ilog2(rounded_conn_num
));
1586 STORE_RT_REG_AGG(p_hwfn
, SRC_REG_FIRSTFREE_RT_OFFSET
,
1587 p_hwfn
->p_cxt_mngr
->first_free
);
1588 STORE_RT_REG_AGG(p_hwfn
, SRC_REG_LASTFREE_RT_OFFSET
,
1589 p_hwfn
->p_cxt_mngr
->last_free
);
1593 #define TM_CFG_NUM_IDS_SHIFT 0
1594 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL
1595 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
1596 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
1597 #define TM_CFG_PARENT_PF_SHIFT 25
1598 #define TM_CFG_PARENT_PF_MASK 0x7ULL
1600 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
1601 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
1603 #define TM_CFG_TID_OFFSET_SHIFT 30
1604 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
1605 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
1606 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
1608 static void qed_tm_init_pf(struct qed_hwfn
*p_hwfn
)
1610 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1611 u32 active_seg_mask
= 0, tm_offset
, rt_reg
;
1612 struct qed_tm_iids tm_iids
;
1616 memset(&tm_iids
, 0, sizeof(tm_iids
));
1617 qed_cxt_tm_iids(p_mngr
, &tm_iids
);
1619 /* @@@TBD No pre-scan for now */
1621 /* Note: We assume consecutive VFs for a PF */
1622 for (i
= 0; i
< p_mngr
->vf_count
; i
++) {
1624 SET_FIELD(cfg_word
, TM_CFG_NUM_IDS
, tm_iids
.per_vf_cids
);
1625 SET_FIELD(cfg_word
, TM_CFG_PRE_SCAN_OFFSET
, 0);
1626 SET_FIELD(cfg_word
, TM_CFG_PARENT_PF
, p_hwfn
->rel_pf_id
);
1627 SET_FIELD(cfg_word
, TM_CFG_CID_PRE_SCAN_ROWS
, 0);
1628 rt_reg
= TM_REG_CONFIG_CONN_MEM_RT_OFFSET
+
1629 (sizeof(cfg_word
) / sizeof(u32
)) *
1630 (p_hwfn
->cdev
->p_iov_info
->first_vf_in_pf
+ i
);
1631 STORE_RT_REG_AGG(p_hwfn
, rt_reg
, cfg_word
);
1635 SET_FIELD(cfg_word
, TM_CFG_NUM_IDS
, tm_iids
.pf_cids
);
1636 SET_FIELD(cfg_word
, TM_CFG_PRE_SCAN_OFFSET
, 0);
1637 SET_FIELD(cfg_word
, TM_CFG_PARENT_PF
, 0); /* n/a for PF */
1638 SET_FIELD(cfg_word
, TM_CFG_CID_PRE_SCAN_ROWS
, 0); /* scan all */
1640 rt_reg
= TM_REG_CONFIG_CONN_MEM_RT_OFFSET
+
1641 (sizeof(cfg_word
) / sizeof(u32
)) *
1642 (NUM_OF_VFS(p_hwfn
->cdev
) + p_hwfn
->rel_pf_id
);
1643 STORE_RT_REG_AGG(p_hwfn
, rt_reg
, cfg_word
);
1646 STORE_RT_REG(p_hwfn
, TM_REG_PF_ENABLE_CONN_RT_OFFSET
,
1647 tm_iids
.pf_cids
? 0x1 : 0x0);
1649 /* @@@TBD how to enable the scan for the VFs */
1651 tm_offset
= tm_iids
.per_vf_cids
;
1653 /* Note: We assume consecutive VFs for a PF */
1654 for (i
= 0; i
< p_mngr
->vf_count
; i
++) {
1656 SET_FIELD(cfg_word
, TM_CFG_NUM_IDS
, tm_iids
.per_vf_tids
);
1657 SET_FIELD(cfg_word
, TM_CFG_PRE_SCAN_OFFSET
, 0);
1658 SET_FIELD(cfg_word
, TM_CFG_PARENT_PF
, p_hwfn
->rel_pf_id
);
1659 SET_FIELD(cfg_word
, TM_CFG_TID_OFFSET
, tm_offset
);
1660 SET_FIELD(cfg_word
, TM_CFG_TID_PRE_SCAN_ROWS
, (u64
) 0);
1662 rt_reg
= TM_REG_CONFIG_TASK_MEM_RT_OFFSET
+
1663 (sizeof(cfg_word
) / sizeof(u32
)) *
1664 (p_hwfn
->cdev
->p_iov_info
->first_vf_in_pf
+ i
);
1666 STORE_RT_REG_AGG(p_hwfn
, rt_reg
, cfg_word
);
1669 tm_offset
= tm_iids
.pf_cids
;
1670 for (i
= 0; i
< NUM_TASK_PF_SEGMENTS
; i
++) {
1672 SET_FIELD(cfg_word
, TM_CFG_NUM_IDS
, tm_iids
.pf_tids
[i
]);
1673 SET_FIELD(cfg_word
, TM_CFG_PRE_SCAN_OFFSET
, 0);
1674 SET_FIELD(cfg_word
, TM_CFG_PARENT_PF
, 0);
1675 SET_FIELD(cfg_word
, TM_CFG_TID_OFFSET
, tm_offset
);
1676 SET_FIELD(cfg_word
, TM_CFG_TID_PRE_SCAN_ROWS
, (u64
) 0);
1678 rt_reg
= TM_REG_CONFIG_TASK_MEM_RT_OFFSET
+
1679 (sizeof(cfg_word
) / sizeof(u32
)) *
1680 (NUM_OF_VFS(p_hwfn
->cdev
) +
1681 p_hwfn
->rel_pf_id
* NUM_TASK_PF_SEGMENTS
+ i
);
1683 STORE_RT_REG_AGG(p_hwfn
, rt_reg
, cfg_word
);
1684 active_seg_mask
|= (tm_iids
.pf_tids
[i
] ? BIT(i
) : 0);
1686 tm_offset
+= tm_iids
.pf_tids
[i
];
1689 if (p_hwfn
->hw_info
.personality
== QED_PCI_ETH_ROCE
)
1690 active_seg_mask
= 0;
1692 STORE_RT_REG(p_hwfn
, TM_REG_PF_ENABLE_TASK_RT_OFFSET
, active_seg_mask
);
1694 /* @@@TBD how to enable the scan for the VFs */
1697 void qed_cxt_hw_init_common(struct qed_hwfn
*p_hwfn
)
1699 qed_cdu_init_common(p_hwfn
);
1702 void qed_cxt_hw_init_pf(struct qed_hwfn
*p_hwfn
)
1704 qed_qm_init_pf(p_hwfn
);
1705 qed_cm_init_pf(p_hwfn
);
1706 qed_dq_init_pf(p_hwfn
);
1707 qed_cdu_init_pf(p_hwfn
);
1708 qed_ilt_init_pf(p_hwfn
);
1709 qed_src_init_pf(p_hwfn
);
1710 qed_tm_init_pf(p_hwfn
);
1713 int qed_cxt_acquire_cid(struct qed_hwfn
*p_hwfn
,
1714 enum protocol_type type
, u32
*p_cid
)
1716 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1719 if (type
>= MAX_CONN_TYPES
|| !p_mngr
->acquired
[type
].cid_map
) {
1720 DP_NOTICE(p_hwfn
, "Invalid protocol type %d", type
);
1724 rel_cid
= find_first_zero_bit(p_mngr
->acquired
[type
].cid_map
,
1725 p_mngr
->acquired
[type
].max_count
);
1727 if (rel_cid
>= p_mngr
->acquired
[type
].max_count
) {
1728 DP_NOTICE(p_hwfn
, "no CID available for protocol %d\n", type
);
1732 __set_bit(rel_cid
, p_mngr
->acquired
[type
].cid_map
);
1734 *p_cid
= rel_cid
+ p_mngr
->acquired
[type
].start_cid
;
1739 static bool qed_cxt_test_cid_acquired(struct qed_hwfn
*p_hwfn
,
1740 u32 cid
, enum protocol_type
*p_type
)
1742 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1743 struct qed_cid_acquired_map
*p_map
;
1744 enum protocol_type p
;
1747 /* Iterate over protocols and find matching cid range */
1748 for (p
= 0; p
< MAX_CONN_TYPES
; p
++) {
1749 p_map
= &p_mngr
->acquired
[p
];
1751 if (!p_map
->cid_map
)
1753 if (cid
>= p_map
->start_cid
&&
1754 cid
< p_map
->start_cid
+ p_map
->max_count
)
1759 if (p
== MAX_CONN_TYPES
) {
1760 DP_NOTICE(p_hwfn
, "Invalid CID %d", cid
);
1764 rel_cid
= cid
- p_map
->start_cid
;
1765 if (!test_bit(rel_cid
, p_map
->cid_map
)) {
1766 DP_NOTICE(p_hwfn
, "CID %d not acquired", cid
);
1772 void qed_cxt_release_cid(struct qed_hwfn
*p_hwfn
, u32 cid
)
1774 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1775 enum protocol_type type
;
1779 /* Test acquired and find matching per-protocol map */
1780 b_acquired
= qed_cxt_test_cid_acquired(p_hwfn
, cid
, &type
);
1785 rel_cid
= cid
- p_mngr
->acquired
[type
].start_cid
;
1786 __clear_bit(rel_cid
, p_mngr
->acquired
[type
].cid_map
);
1789 int qed_cxt_get_cid_info(struct qed_hwfn
*p_hwfn
, struct qed_cxt_info
*p_info
)
1791 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1792 u32 conn_cxt_size
, hw_p_size
, cxts_per_p
, line
;
1793 enum protocol_type type
;
1796 /* Test acquired and find matching per-protocol map */
1797 b_acquired
= qed_cxt_test_cid_acquired(p_hwfn
, p_info
->iid
, &type
);
1802 /* set the protocl type */
1803 p_info
->type
= type
;
1805 /* compute context virtual pointer */
1806 hw_p_size
= p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUC
].p_size
.val
;
1808 conn_cxt_size
= CONN_CXT_SIZE(p_hwfn
);
1809 cxts_per_p
= ILT_PAGE_IN_BYTES(hw_p_size
) / conn_cxt_size
;
1810 line
= p_info
->iid
/ cxts_per_p
;
1812 /* Make sure context is allocated (dynamic allocation) */
1813 if (!p_mngr
->ilt_shadow
[line
].p_virt
)
1816 p_info
->p_cxt
= p_mngr
->ilt_shadow
[line
].p_virt
+
1817 p_info
->iid
% cxts_per_p
* conn_cxt_size
;
1819 DP_VERBOSE(p_hwfn
, (QED_MSG_ILT
| QED_MSG_CXT
),
1820 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1821 p_info
->iid
/ cxts_per_p
, p_info
->p_cxt
, p_info
->iid
);
1826 static void qed_rdma_set_pf_params(struct qed_hwfn
*p_hwfn
,
1827 struct qed_rdma_pf_params
*p_params
)
1829 u32 num_cons
, num_tasks
, num_qps
, num_mrs
, num_srqs
;
1830 enum protocol_type proto
;
1832 num_mrs
= min_t(u32
, RDMA_MAX_TIDS
, p_params
->num_mrs
);
1833 num_tasks
= num_mrs
; /* each mr uses a single task id */
1834 num_srqs
= min_t(u32
, 32 * 1024, p_params
->num_srqs
);
1836 switch (p_hwfn
->hw_info
.personality
) {
1837 case QED_PCI_ETH_ROCE
:
1838 num_qps
= min_t(u32
, ROCE_MAX_QPS
, p_params
->num_qps
);
1839 num_cons
= num_qps
* 2; /* each QP requires two connections */
1840 proto
= PROTOCOLID_ROCE
;
1846 if (num_cons
&& num_tasks
) {
1847 qed_cxt_set_proto_cid_count(p_hwfn
, proto
, num_cons
, 0);
1849 /* Deliberatly passing ROCE for tasks id. This is because
1850 * iWARP / RoCE share the task id.
1852 qed_cxt_set_proto_tid_count(p_hwfn
, PROTOCOLID_ROCE
,
1853 QED_CXT_ROCE_TID_SEG
, 1,
1855 qed_cxt_set_srq_count(p_hwfn
, num_srqs
);
1857 DP_INFO(p_hwfn
->cdev
,
1858 "RDMA personality used without setting params!\n");
1862 int qed_cxt_set_pf_params(struct qed_hwfn
*p_hwfn
)
1864 /* Set the number of required CORE connections */
1865 u32 core_cids
= 1; /* SPQ */
1867 if (p_hwfn
->using_ll2
)
1869 qed_cxt_set_proto_cid_count(p_hwfn
, PROTOCOLID_CORE
, core_cids
, 0);
1871 switch (p_hwfn
->hw_info
.personality
) {
1872 case QED_PCI_ETH_ROCE
:
1874 qed_rdma_set_pf_params(p_hwfn
,
1876 pf_params
.rdma_pf_params
);
1877 /* no need for break since RoCE coexist with Ethernet */
1881 struct qed_eth_pf_params
*p_params
=
1882 &p_hwfn
->pf_params
.eth_pf_params
;
1884 qed_cxt_set_proto_cid_count(p_hwfn
, PROTOCOLID_ETH
,
1885 p_params
->num_cons
, 1);
1890 struct qed_iscsi_pf_params
*p_params
;
1892 p_params
= &p_hwfn
->pf_params
.iscsi_pf_params
;
1894 if (p_params
->num_cons
&& p_params
->num_tasks
) {
1895 qed_cxt_set_proto_cid_count(p_hwfn
,
1900 qed_cxt_set_proto_tid_count(p_hwfn
,
1902 QED_CXT_ISCSI_TID_SEG
,
1904 p_params
->num_tasks
,
1907 DP_INFO(p_hwfn
->cdev
,
1908 "Iscsi personality used without setting params!\n");
1919 int qed_cxt_get_tid_mem_info(struct qed_hwfn
*p_hwfn
,
1920 struct qed_tid_mem
*p_info
)
1922 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1923 u32 proto
, seg
, total_lines
, i
, shadow_line
;
1924 struct qed_ilt_client_cfg
*p_cli
;
1925 struct qed_ilt_cli_blk
*p_fl_seg
;
1926 struct qed_tid_seg
*p_seg_info
;
1928 /* Verify the personality */
1929 switch (p_hwfn
->hw_info
.personality
) {
1931 proto
= PROTOCOLID_ISCSI
;
1932 seg
= QED_CXT_ISCSI_TID_SEG
;
1938 p_cli
= &p_mngr
->clients
[ILT_CLI_CDUT
];
1942 p_seg_info
= &p_mngr
->conn_cfg
[proto
].tid_seg
[seg
];
1943 if (!p_seg_info
->has_fl_mem
)
1946 p_fl_seg
= &p_cli
->pf_blks
[CDUT_FL_SEG_BLK(seg
, PF
)];
1947 total_lines
= DIV_ROUND_UP(p_fl_seg
->total_size
,
1948 p_fl_seg
->real_size_in_page
);
1950 for (i
= 0; i
< total_lines
; i
++) {
1951 shadow_line
= i
+ p_fl_seg
->start_line
-
1952 p_hwfn
->p_cxt_mngr
->pf_start_line
;
1953 p_info
->blocks
[i
] = p_mngr
->ilt_shadow
[shadow_line
].p_virt
;
1955 p_info
->waste
= ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) -
1956 p_fl_seg
->real_size_in_page
;
1957 p_info
->tid_size
= p_mngr
->task_type_size
[p_seg_info
->type
];
1958 p_info
->num_tids_per_block
= p_fl_seg
->real_size_in_page
/
1964 /* This function is very RoCE oriented, if another protocol in the future
1965 * will want this feature we'll need to modify the function to be more generic
1968 qed_cxt_dynamic_ilt_alloc(struct qed_hwfn
*p_hwfn
,
1969 enum qed_cxt_elem_type elem_type
, u32 iid
)
1971 u32 reg_offset
, shadow_line
, elem_size
, hw_p_size
, elems_per_p
, line
;
1972 struct qed_ilt_client_cfg
*p_cli
;
1973 struct qed_ilt_cli_blk
*p_blk
;
1974 struct qed_ptt
*p_ptt
;
1980 switch (elem_type
) {
1982 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUC
];
1983 elem_size
= CONN_CXT_SIZE(p_hwfn
);
1984 p_blk
= &p_cli
->pf_blks
[CDUC_BLK
];
1987 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_TSDM
];
1988 elem_size
= SRQ_CXT_SIZE
;
1989 p_blk
= &p_cli
->pf_blks
[SRQ_BLK
];
1992 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUT
];
1993 elem_size
= TYPE1_TASK_CXT_SIZE(p_hwfn
);
1994 p_blk
= &p_cli
->pf_blks
[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG
)];
1997 DP_NOTICE(p_hwfn
, "-EINVALID elem type = %d", elem_type
);
2001 /* Calculate line in ilt */
2002 hw_p_size
= p_cli
->p_size
.val
;
2003 elems_per_p
= ILT_PAGE_IN_BYTES(hw_p_size
) / elem_size
;
2004 line
= p_blk
->start_line
+ (iid
/ elems_per_p
);
2005 shadow_line
= line
- p_hwfn
->p_cxt_mngr
->pf_start_line
;
2007 /* If line is already allocated, do nothing, otherwise allocate it and
2008 * write it to the PSWRQ2 registers.
2009 * This section can be run in parallel from different contexts and thus
2010 * a mutex protection is needed.
2013 mutex_lock(&p_hwfn
->p_cxt_mngr
->mutex
);
2015 if (p_hwfn
->p_cxt_mngr
->ilt_shadow
[shadow_line
].p_virt
)
2018 p_ptt
= qed_ptt_acquire(p_hwfn
);
2021 "QED_TIME_OUT on ptt acquire - dynamic allocation");
2026 p_virt
= dma_alloc_coherent(&p_hwfn
->cdev
->pdev
->dev
,
2027 p_blk
->real_size_in_page
,
2028 &p_phys
, GFP_KERNEL
);
2033 memset(p_virt
, 0, p_blk
->real_size_in_page
);
2035 /* configuration of refTagMask to 0xF is required for RoCE DIF MR only,
2036 * to compensate for a HW bug, but it is configured even if DIF is not
2037 * enabled. This is harmless and allows us to avoid a dedicated API. We
2038 * configure the field for all of the contexts on the newly allocated
2041 if (elem_type
== QED_ELEM_TASK
) {
2043 u8
*elem_start
= (u8
*)p_virt
;
2044 union type1_task_context
*elem
;
2046 for (elem_i
= 0; elem_i
< elems_per_p
; elem_i
++) {
2047 elem
= (union type1_task_context
*)elem_start
;
2048 SET_FIELD(elem
->roce_ctx
.tdif_context
.flags1
,
2049 TDIF_TASK_CONTEXT_REFTAGMASK
, 0xf);
2050 elem_start
+= TYPE1_TASK_CXT_SIZE(p_hwfn
);
2054 p_hwfn
->p_cxt_mngr
->ilt_shadow
[shadow_line
].p_virt
= p_virt
;
2055 p_hwfn
->p_cxt_mngr
->ilt_shadow
[shadow_line
].p_phys
= p_phys
;
2056 p_hwfn
->p_cxt_mngr
->ilt_shadow
[shadow_line
].size
=
2057 p_blk
->real_size_in_page
;
2059 /* compute absolute offset */
2060 reg_offset
= PSWRQ2_REG_ILT_MEMORY
+
2061 (line
* ILT_REG_SIZE_IN_BYTES
* ILT_ENTRY_IN_REGS
);
2064 SET_FIELD(ilt_hw_entry
, ILT_ENTRY_VALID
, 1ULL);
2065 SET_FIELD(ilt_hw_entry
,
2067 (p_hwfn
->p_cxt_mngr
->ilt_shadow
[shadow_line
].p_phys
>> 12));
2069 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2070 qed_dmae_host2grc(p_hwfn
, p_ptt
, (u64
) (uintptr_t)&ilt_hw_entry
,
2071 reg_offset
, sizeof(ilt_hw_entry
) / sizeof(u32
), 0);
2073 if (elem_type
== QED_ELEM_CXT
) {
2074 u32 last_cid_allocated
= (1 + (iid
/ elems_per_p
)) *
2077 /* Update the relevant register in the parser */
2078 qed_wr(p_hwfn
, p_ptt
, PRS_REG_ROCE_DEST_QP_MAX_PF
,
2079 last_cid_allocated
- 1);
2081 if (!p_hwfn
->b_rdma_enabled_in_prs
) {
2082 /* Enable RoCE search */
2083 qed_wr(p_hwfn
, p_ptt
, p_hwfn
->rdma_prs_search_reg
, 1);
2084 p_hwfn
->b_rdma_enabled_in_prs
= true;
2089 qed_ptt_release(p_hwfn
, p_ptt
);
2091 mutex_unlock(&p_hwfn
->p_cxt_mngr
->mutex
);
2096 /* This function is very RoCE oriented, if another protocol in the future
2097 * will want this feature we'll need to modify the function to be more generic
2100 qed_cxt_free_ilt_range(struct qed_hwfn
*p_hwfn
,
2101 enum qed_cxt_elem_type elem_type
,
2102 u32 start_iid
, u32 count
)
2104 u32 start_line
, end_line
, shadow_start_line
, shadow_end_line
;
2105 u32 reg_offset
, elem_size
, hw_p_size
, elems_per_p
;
2106 struct qed_ilt_client_cfg
*p_cli
;
2107 struct qed_ilt_cli_blk
*p_blk
;
2108 u32 end_iid
= start_iid
+ count
;
2109 struct qed_ptt
*p_ptt
;
2110 u64 ilt_hw_entry
= 0;
2113 switch (elem_type
) {
2115 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUC
];
2116 elem_size
= CONN_CXT_SIZE(p_hwfn
);
2117 p_blk
= &p_cli
->pf_blks
[CDUC_BLK
];
2120 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_TSDM
];
2121 elem_size
= SRQ_CXT_SIZE
;
2122 p_blk
= &p_cli
->pf_blks
[SRQ_BLK
];
2125 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUT
];
2126 elem_size
= TYPE1_TASK_CXT_SIZE(p_hwfn
);
2127 p_blk
= &p_cli
->pf_blks
[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG
)];
2130 DP_NOTICE(p_hwfn
, "-EINVALID elem type = %d", elem_type
);
2134 /* Calculate line in ilt */
2135 hw_p_size
= p_cli
->p_size
.val
;
2136 elems_per_p
= ILT_PAGE_IN_BYTES(hw_p_size
) / elem_size
;
2137 start_line
= p_blk
->start_line
+ (start_iid
/ elems_per_p
);
2138 end_line
= p_blk
->start_line
+ (end_iid
/ elems_per_p
);
2139 if (((end_iid
+ 1) / elems_per_p
) != (end_iid
/ elems_per_p
))
2142 shadow_start_line
= start_line
- p_hwfn
->p_cxt_mngr
->pf_start_line
;
2143 shadow_end_line
= end_line
- p_hwfn
->p_cxt_mngr
->pf_start_line
;
2145 p_ptt
= qed_ptt_acquire(p_hwfn
);
2148 "QED_TIME_OUT on ptt acquire - dynamic allocation");
2152 for (i
= shadow_start_line
; i
< shadow_end_line
; i
++) {
2153 if (!p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].p_virt
)
2156 dma_free_coherent(&p_hwfn
->cdev
->pdev
->dev
,
2157 p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].size
,
2158 p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].p_virt
,
2159 p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].p_phys
);
2161 p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].p_virt
= NULL
;
2162 p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].p_phys
= 0;
2163 p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].size
= 0;
2165 /* compute absolute offset */
2166 reg_offset
= PSWRQ2_REG_ILT_MEMORY
+
2167 ((start_line
++) * ILT_REG_SIZE_IN_BYTES
*
2170 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2173 qed_dmae_host2grc(p_hwfn
, p_ptt
,
2174 (u64
) (uintptr_t) &ilt_hw_entry
,
2176 sizeof(ilt_hw_entry
) / sizeof(u32
),
2180 qed_ptt_release(p_hwfn
, p_ptt
);
2185 int qed_cxt_free_proto_ilt(struct qed_hwfn
*p_hwfn
, enum protocol_type proto
)
2190 /* Free Connection CXT */
2191 rc
= qed_cxt_free_ilt_range(p_hwfn
, QED_ELEM_CXT
,
2192 qed_cxt_get_proto_cid_start(p_hwfn
,
2194 qed_cxt_get_proto_cid_count(p_hwfn
,
2201 rc
= qed_cxt_free_ilt_range(p_hwfn
, QED_ELEM_TASK
, 0,
2202 qed_cxt_get_proto_tid_count(p_hwfn
, proto
));
2207 rc
= qed_cxt_free_ilt_range(p_hwfn
, QED_ELEM_SRQ
, 0,
2208 qed_cxt_get_srq_count(p_hwfn
));
2213 int qed_cxt_get_task_ctx(struct qed_hwfn
*p_hwfn
,
2214 u32 tid
, u8 ctx_type
, void **pp_task_ctx
)
2216 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
2217 struct qed_ilt_client_cfg
*p_cli
;
2218 struct qed_ilt_cli_blk
*p_seg
;
2219 struct qed_tid_seg
*p_seg_info
;
2222 u32 tid_size
, ilt_idx
;
2223 u32 num_tids_per_block
;
2225 /* Verify the personality */
2226 switch (p_hwfn
->hw_info
.personality
) {
2228 proto
= PROTOCOLID_ISCSI
;
2229 seg
= QED_CXT_ISCSI_TID_SEG
;
2235 p_cli
= &p_mngr
->clients
[ILT_CLI_CDUT
];
2239 p_seg_info
= &p_mngr
->conn_cfg
[proto
].tid_seg
[seg
];
2241 if (ctx_type
== QED_CTX_WORKING_MEM
) {
2242 p_seg
= &p_cli
->pf_blks
[CDUT_SEG_BLK(seg
)];
2243 } else if (ctx_type
== QED_CTX_FL_MEM
) {
2244 if (!p_seg_info
->has_fl_mem
)
2246 p_seg
= &p_cli
->pf_blks
[CDUT_FL_SEG_BLK(seg
, PF
)];
2250 total_lines
= DIV_ROUND_UP(p_seg
->total_size
, p_seg
->real_size_in_page
);
2251 tid_size
= p_mngr
->task_type_size
[p_seg_info
->type
];
2252 num_tids_per_block
= p_seg
->real_size_in_page
/ tid_size
;
2254 if (total_lines
< tid
/ num_tids_per_block
)
2257 ilt_idx
= tid
/ num_tids_per_block
+ p_seg
->start_line
-
2258 p_mngr
->pf_start_line
;
2259 *pp_task_ctx
= (u8
*)p_mngr
->ilt_shadow
[ilt_idx
].p_virt
+
2260 (tid
% num_tids_per_block
) * tid_size
;