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qed: Add missing 100g init mode
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_dev.c
1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9 #include <linux/types.h>
10 #include <asm/byteorder.h>
11 #include <linux/io.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16 #include <linux/mutex.h>
17 #include <linux/pci.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/etherdevice.h>
21 #include <linux/qed/qed_chain.h>
22 #include <linux/qed/qed_if.h>
23 #include "qed.h"
24 #include "qed_cxt.h"
25 #include "qed_dcbx.h"
26 #include "qed_dev_api.h"
27 #include "qed_hsi.h"
28 #include "qed_hw.h"
29 #include "qed_init_ops.h"
30 #include "qed_int.h"
31 #include "qed_mcp.h"
32 #include "qed_reg_addr.h"
33 #include "qed_sp.h"
34 #include "qed_sriov.h"
35 #include "qed_vf.h"
36
37 static spinlock_t qm_lock;
38 static bool qm_lock_init = false;
39
40 /* API common to all protocols */
41 enum BAR_ID {
42 BAR_ID_0, /* used for GRC */
43 BAR_ID_1 /* Used for doorbells */
44 };
45
46 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
47 enum BAR_ID bar_id)
48 {
49 u32 bar_reg = (bar_id == BAR_ID_0 ?
50 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
51 u32 val;
52
53 if (IS_VF(p_hwfn->cdev))
54 return 1 << 17;
55
56 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
57 if (val)
58 return 1 << (val + 15);
59
60 /* Old MFW initialized above registered only conditionally */
61 if (p_hwfn->cdev->num_hwfns > 1) {
62 DP_INFO(p_hwfn,
63 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
64 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
65 } else {
66 DP_INFO(p_hwfn,
67 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
68 return 512 * 1024;
69 }
70 }
71
72 void qed_init_dp(struct qed_dev *cdev,
73 u32 dp_module, u8 dp_level)
74 {
75 u32 i;
76
77 cdev->dp_level = dp_level;
78 cdev->dp_module = dp_module;
79 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
80 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
81
82 p_hwfn->dp_level = dp_level;
83 p_hwfn->dp_module = dp_module;
84 }
85 }
86
87 void qed_init_struct(struct qed_dev *cdev)
88 {
89 u8 i;
90
91 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
92 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
93
94 p_hwfn->cdev = cdev;
95 p_hwfn->my_id = i;
96 p_hwfn->b_active = false;
97
98 mutex_init(&p_hwfn->dmae_info.mutex);
99 }
100
101 /* hwfn 0 is always active */
102 cdev->hwfns[0].b_active = true;
103
104 /* set the default cache alignment to 128 */
105 cdev->cache_shift = 7;
106 }
107
108 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
109 {
110 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
111
112 kfree(qm_info->qm_pq_params);
113 qm_info->qm_pq_params = NULL;
114 kfree(qm_info->qm_vport_params);
115 qm_info->qm_vport_params = NULL;
116 kfree(qm_info->qm_port_params);
117 qm_info->qm_port_params = NULL;
118 kfree(qm_info->wfq_data);
119 qm_info->wfq_data = NULL;
120 }
121
122 void qed_resc_free(struct qed_dev *cdev)
123 {
124 int i;
125
126 if (IS_VF(cdev))
127 return;
128
129 kfree(cdev->fw_data);
130 cdev->fw_data = NULL;
131
132 kfree(cdev->reset_stats);
133
134 for_each_hwfn(cdev, i) {
135 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
136
137 kfree(p_hwfn->p_tx_cids);
138 p_hwfn->p_tx_cids = NULL;
139 kfree(p_hwfn->p_rx_cids);
140 p_hwfn->p_rx_cids = NULL;
141 }
142
143 for_each_hwfn(cdev, i) {
144 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
145
146 qed_cxt_mngr_free(p_hwfn);
147 qed_qm_info_free(p_hwfn);
148 qed_spq_free(p_hwfn);
149 qed_eq_free(p_hwfn, p_hwfn->p_eq);
150 qed_consq_free(p_hwfn, p_hwfn->p_consq);
151 qed_int_free(p_hwfn);
152 qed_iov_free(p_hwfn);
153 qed_dmae_info_free(p_hwfn);
154 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
155 }
156 }
157
158 static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
159 {
160 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
161 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
162 struct init_qm_port_params *p_qm_port;
163 u16 num_pqs, multi_cos_tcs = 1;
164 u8 pf_wfq = qm_info->pf_wfq;
165 u32 pf_rl = qm_info->pf_rl;
166 u16 num_vfs = 0;
167
168 #ifdef CONFIG_QED_SRIOV
169 if (p_hwfn->cdev->p_iov_info)
170 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
171 #endif
172 memset(qm_info, 0, sizeof(*qm_info));
173
174 num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */
175 num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
176
177 /* Sanity checking that setup requires legal number of resources */
178 if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
179 DP_ERR(p_hwfn,
180 "Need too many Physical queues - 0x%04x when only %04x are available\n",
181 num_pqs, RESC_NUM(p_hwfn, QED_PQ));
182 return -EINVAL;
183 }
184
185 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
186 */
187 qm_info->qm_pq_params = kcalloc(num_pqs,
188 sizeof(struct init_qm_pq_params),
189 b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
190 if (!qm_info->qm_pq_params)
191 goto alloc_err;
192
193 qm_info->qm_vport_params = kcalloc(num_vports,
194 sizeof(struct init_qm_vport_params),
195 b_sleepable ? GFP_KERNEL
196 : GFP_ATOMIC);
197 if (!qm_info->qm_vport_params)
198 goto alloc_err;
199
200 qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS,
201 sizeof(struct init_qm_port_params),
202 b_sleepable ? GFP_KERNEL
203 : GFP_ATOMIC);
204 if (!qm_info->qm_port_params)
205 goto alloc_err;
206
207 qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data),
208 b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
209 if (!qm_info->wfq_data)
210 goto alloc_err;
211
212 vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
213
214 /* First init per-TC PQs */
215 for (i = 0; i < multi_cos_tcs; i++) {
216 struct init_qm_pq_params *params =
217 &qm_info->qm_pq_params[curr_queue++];
218
219 if (p_hwfn->hw_info.personality == QED_PCI_ETH) {
220 params->vport_id = vport_id;
221 params->tc_id = p_hwfn->hw_info.non_offload_tc;
222 params->wrr_group = 1;
223 } else {
224 params->vport_id = vport_id;
225 params->tc_id = p_hwfn->hw_info.offload_tc;
226 params->wrr_group = 1;
227 }
228 }
229
230 /* Then init pure-LB PQ */
231 qm_info->pure_lb_pq = curr_queue;
232 qm_info->qm_pq_params[curr_queue].vport_id =
233 (u8) RESC_START(p_hwfn, QED_VPORT);
234 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
235 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
236 curr_queue++;
237
238 qm_info->offload_pq = 0;
239 /* Then init per-VF PQs */
240 vf_offset = curr_queue;
241 for (i = 0; i < num_vfs; i++) {
242 /* First vport is used by the PF */
243 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
244 qm_info->qm_pq_params[curr_queue].tc_id =
245 p_hwfn->hw_info.non_offload_tc;
246 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
247 curr_queue++;
248 }
249
250 qm_info->vf_queues_offset = vf_offset;
251 qm_info->num_pqs = num_pqs;
252 qm_info->num_vports = num_vports;
253
254 /* Initialize qm port parameters */
255 num_ports = p_hwfn->cdev->num_ports_in_engines;
256 for (i = 0; i < num_ports; i++) {
257 p_qm_port = &qm_info->qm_port_params[i];
258 p_qm_port->active = 1;
259 p_qm_port->num_active_phys_tcs = 4;
260 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
261 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
262 }
263
264 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
265
266 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
267
268 qm_info->num_vf_pqs = num_vfs;
269 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
270
271 for (i = 0; i < qm_info->num_vports; i++)
272 qm_info->qm_vport_params[i].vport_wfq = 1;
273
274 qm_info->vport_rl_en = 1;
275 qm_info->vport_wfq_en = 1;
276 qm_info->pf_rl = pf_rl;
277 qm_info->pf_wfq = pf_wfq;
278
279 return 0;
280
281 alloc_err:
282 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
283 qed_qm_info_free(p_hwfn);
284 return -ENOMEM;
285 }
286
287 /* This function reconfigures the QM pf on the fly.
288 * For this purpose we:
289 * 1. reconfigure the QM database
290 * 2. set new values to runtime arrat
291 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
292 * 4. activate init tool in QM_PF stage
293 * 5. send an sdm_qm_cmd through rbc interface to release the QM
294 */
295 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
296 {
297 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
298 bool b_rc;
299 int rc;
300
301 /* qm_info is allocated in qed_init_qm_info() which is already called
302 * from qed_resc_alloc() or previous call of qed_qm_reconf().
303 * The allocated size may change each init, so we free it before next
304 * allocation.
305 */
306 qed_qm_info_free(p_hwfn);
307
308 /* initialize qed's qm data structure */
309 rc = qed_init_qm_info(p_hwfn, false);
310 if (rc)
311 return rc;
312
313 /* stop PF's qm queues */
314 spin_lock_bh(&qm_lock);
315 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
316 qm_info->start_pq, qm_info->num_pqs);
317 spin_unlock_bh(&qm_lock);
318 if (!b_rc)
319 return -EINVAL;
320
321 /* clear the QM_PF runtime phase leftovers from previous init */
322 qed_init_clear_rt_data(p_hwfn);
323
324 /* prepare QM portion of runtime array */
325 qed_qm_init_pf(p_hwfn);
326
327 /* activate init tool on runtime array */
328 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
329 p_hwfn->hw_info.hw_mode);
330 if (rc)
331 return rc;
332
333 /* start PF's qm queues */
334 spin_lock_bh(&qm_lock);
335 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
336 qm_info->start_pq, qm_info->num_pqs);
337 spin_unlock_bh(&qm_lock);
338 if (!b_rc)
339 return -EINVAL;
340
341 return 0;
342 }
343
344 int qed_resc_alloc(struct qed_dev *cdev)
345 {
346 struct qed_consq *p_consq;
347 struct qed_eq *p_eq;
348 int i, rc = 0;
349
350 if (IS_VF(cdev))
351 return rc;
352
353 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
354 if (!cdev->fw_data)
355 return -ENOMEM;
356
357 /* Allocate Memory for the Queue->CID mapping */
358 for_each_hwfn(cdev, i) {
359 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
360 int tx_size = sizeof(struct qed_hw_cid_data) *
361 RESC_NUM(p_hwfn, QED_L2_QUEUE);
362 int rx_size = sizeof(struct qed_hw_cid_data) *
363 RESC_NUM(p_hwfn, QED_L2_QUEUE);
364
365 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL);
366 if (!p_hwfn->p_tx_cids) {
367 DP_NOTICE(p_hwfn,
368 "Failed to allocate memory for Tx Cids\n");
369 rc = -ENOMEM;
370 goto alloc_err;
371 }
372
373 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
374 if (!p_hwfn->p_rx_cids) {
375 DP_NOTICE(p_hwfn,
376 "Failed to allocate memory for Rx Cids\n");
377 rc = -ENOMEM;
378 goto alloc_err;
379 }
380 }
381
382 for_each_hwfn(cdev, i) {
383 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
384
385 /* First allocate the context manager structure */
386 rc = qed_cxt_mngr_alloc(p_hwfn);
387 if (rc)
388 goto alloc_err;
389
390 /* Set the HW cid/tid numbers (in the contest manager)
391 * Must be done prior to any further computations.
392 */
393 rc = qed_cxt_set_pf_params(p_hwfn);
394 if (rc)
395 goto alloc_err;
396
397 /* Prepare and process QM requirements */
398 rc = qed_init_qm_info(p_hwfn, true);
399 if (rc)
400 goto alloc_err;
401
402 /* Compute the ILT client partition */
403 rc = qed_cxt_cfg_ilt_compute(p_hwfn);
404 if (rc)
405 goto alloc_err;
406
407 /* CID map / ILT shadow table / T2
408 * The talbes sizes are determined by the computations above
409 */
410 rc = qed_cxt_tables_alloc(p_hwfn);
411 if (rc)
412 goto alloc_err;
413
414 /* SPQ, must follow ILT because initializes SPQ context */
415 rc = qed_spq_alloc(p_hwfn);
416 if (rc)
417 goto alloc_err;
418
419 /* SP status block allocation */
420 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
421 RESERVED_PTT_DPC);
422
423 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
424 if (rc)
425 goto alloc_err;
426
427 rc = qed_iov_alloc(p_hwfn);
428 if (rc)
429 goto alloc_err;
430
431 /* EQ */
432 p_eq = qed_eq_alloc(p_hwfn, 256);
433 if (!p_eq) {
434 rc = -ENOMEM;
435 goto alloc_err;
436 }
437 p_hwfn->p_eq = p_eq;
438
439 p_consq = qed_consq_alloc(p_hwfn);
440 if (!p_consq) {
441 rc = -ENOMEM;
442 goto alloc_err;
443 }
444 p_hwfn->p_consq = p_consq;
445
446 /* DMA info initialization */
447 rc = qed_dmae_info_alloc(p_hwfn);
448 if (rc) {
449 DP_NOTICE(p_hwfn,
450 "Failed to allocate memory for dmae_info structure\n");
451 goto alloc_err;
452 }
453
454 /* DCBX initialization */
455 rc = qed_dcbx_info_alloc(p_hwfn);
456 if (rc) {
457 DP_NOTICE(p_hwfn,
458 "Failed to allocate memory for dcbx structure\n");
459 goto alloc_err;
460 }
461 }
462
463 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
464 if (!cdev->reset_stats) {
465 DP_NOTICE(cdev, "Failed to allocate reset statistics\n");
466 rc = -ENOMEM;
467 goto alloc_err;
468 }
469
470 return 0;
471
472 alloc_err:
473 qed_resc_free(cdev);
474 return rc;
475 }
476
477 void qed_resc_setup(struct qed_dev *cdev)
478 {
479 int i;
480
481 if (IS_VF(cdev))
482 return;
483
484 for_each_hwfn(cdev, i) {
485 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
486
487 qed_cxt_mngr_setup(p_hwfn);
488 qed_spq_setup(p_hwfn);
489 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
490 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
491
492 /* Read shadow of current MFW mailbox */
493 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
494 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
495 p_hwfn->mcp_info->mfw_mb_cur,
496 p_hwfn->mcp_info->mfw_mb_length);
497
498 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
499
500 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
501 }
502 }
503
504 #define FINAL_CLEANUP_POLL_CNT (100)
505 #define FINAL_CLEANUP_POLL_TIME (10)
506 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
507 struct qed_ptt *p_ptt, u16 id, bool is_vf)
508 {
509 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
510 int rc = -EBUSY;
511
512 addr = GTT_BAR0_MAP_REG_USDM_RAM +
513 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
514
515 if (is_vf)
516 id += 0x10;
517
518 command |= X_FINAL_CLEANUP_AGG_INT <<
519 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
520 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
521 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
522 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
523
524 /* Make sure notification is not set before initiating final cleanup */
525 if (REG_RD(p_hwfn, addr)) {
526 DP_NOTICE(
527 p_hwfn,
528 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
529 REG_WR(p_hwfn, addr, 0);
530 }
531
532 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
533 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
534 id, command);
535
536 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
537
538 /* Poll until completion */
539 while (!REG_RD(p_hwfn, addr) && count--)
540 msleep(FINAL_CLEANUP_POLL_TIME);
541
542 if (REG_RD(p_hwfn, addr))
543 rc = 0;
544 else
545 DP_NOTICE(p_hwfn,
546 "Failed to receive FW final cleanup notification\n");
547
548 /* Cleanup afterwards */
549 REG_WR(p_hwfn, addr, 0);
550
551 return rc;
552 }
553
554 static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
555 {
556 int hw_mode = 0;
557
558 hw_mode = (1 << MODE_BB_B0);
559
560 switch (p_hwfn->cdev->num_ports_in_engines) {
561 case 1:
562 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
563 break;
564 case 2:
565 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
566 break;
567 case 4:
568 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
569 break;
570 default:
571 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
572 p_hwfn->cdev->num_ports_in_engines);
573 return;
574 }
575
576 switch (p_hwfn->cdev->mf_mode) {
577 case QED_MF_DEFAULT:
578 case QED_MF_NPAR:
579 hw_mode |= 1 << MODE_MF_SI;
580 break;
581 case QED_MF_OVLAN:
582 hw_mode |= 1 << MODE_MF_SD;
583 break;
584 default:
585 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
586 hw_mode |= 1 << MODE_MF_SI;
587 }
588
589 hw_mode |= 1 << MODE_ASIC;
590
591 if (p_hwfn->cdev->num_hwfns > 1)
592 hw_mode |= 1 << MODE_100G;
593
594 p_hwfn->hw_info.hw_mode = hw_mode;
595
596 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
597 "Configuring function for hw_mode: 0x%08x\n",
598 p_hwfn->hw_info.hw_mode);
599 }
600
601 /* Init run time data for all PFs on an engine. */
602 static void qed_init_cau_rt_data(struct qed_dev *cdev)
603 {
604 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
605 int i, sb_id;
606
607 for_each_hwfn(cdev, i) {
608 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
609 struct qed_igu_info *p_igu_info;
610 struct qed_igu_block *p_block;
611 struct cau_sb_entry sb_entry;
612
613 p_igu_info = p_hwfn->hw_info.p_igu_info;
614
615 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
616 sb_id++) {
617 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
618 if (!p_block->is_pf)
619 continue;
620
621 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
622 p_block->function_id,
623 0, 0);
624 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2,
625 sb_entry);
626 }
627 }
628 }
629
630 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
631 struct qed_ptt *p_ptt,
632 int hw_mode)
633 {
634 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
635 struct qed_qm_common_rt_init_params params;
636 struct qed_dev *cdev = p_hwfn->cdev;
637 u32 concrete_fid;
638 int rc = 0;
639 u8 vf_id;
640
641 qed_init_cau_rt_data(cdev);
642
643 /* Program GTT windows */
644 qed_gtt_init(p_hwfn);
645
646 if (p_hwfn->mcp_info) {
647 if (p_hwfn->mcp_info->func_info.bandwidth_max)
648 qm_info->pf_rl_en = 1;
649 if (p_hwfn->mcp_info->func_info.bandwidth_min)
650 qm_info->pf_wfq_en = 1;
651 }
652
653 memset(&params, 0, sizeof(params));
654 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
655 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
656 params.pf_rl_en = qm_info->pf_rl_en;
657 params.pf_wfq_en = qm_info->pf_wfq_en;
658 params.vport_rl_en = qm_info->vport_rl_en;
659 params.vport_wfq_en = qm_info->vport_wfq_en;
660 params.port_params = qm_info->qm_port_params;
661
662 qed_qm_common_rt_init(p_hwfn, &params);
663
664 qed_cxt_hw_init_common(p_hwfn);
665
666 /* Close gate from NIG to BRB/Storm; By default they are open, but
667 * we close them to prevent NIG from passing data to reset blocks.
668 * Should have been done in the ENGINE phase, but init-tool lacks
669 * proper port-pretend capabilities.
670 */
671 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
672 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
673 qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
674 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
675 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
676 qed_port_unpretend(p_hwfn, p_ptt);
677
678 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
679 if (rc != 0)
680 return rc;
681
682 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
683 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
684
685 /* Disable relaxed ordering in the PCI config space */
686 qed_wr(p_hwfn, p_ptt, 0x20b4,
687 qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10);
688
689 for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
690 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
691 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
692 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
693 }
694 /* pretend to original PF */
695 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
696
697 return rc;
698 }
699
700 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
701 struct qed_ptt *p_ptt,
702 int hw_mode)
703 {
704 int rc = 0;
705
706 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
707 hw_mode);
708 return rc;
709 }
710
711 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
712 struct qed_ptt *p_ptt,
713 struct qed_tunn_start_params *p_tunn,
714 int hw_mode,
715 bool b_hw_start,
716 enum qed_int_mode int_mode,
717 bool allow_npar_tx_switch)
718 {
719 u8 rel_pf_id = p_hwfn->rel_pf_id;
720 int rc = 0;
721
722 if (p_hwfn->mcp_info) {
723 struct qed_mcp_function_info *p_info;
724
725 p_info = &p_hwfn->mcp_info->func_info;
726 if (p_info->bandwidth_min)
727 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
728
729 /* Update rate limit once we'll actually have a link */
730 p_hwfn->qm_info.pf_rl = 100000;
731 }
732
733 qed_cxt_hw_init_pf(p_hwfn);
734
735 qed_int_igu_init_rt(p_hwfn);
736
737 /* Set VLAN in NIG if needed */
738 if (hw_mode & (1 << MODE_MF_SD)) {
739 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
740 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
741 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
742 p_hwfn->hw_info.ovlan);
743 }
744
745 /* Enable classification by MAC if needed */
746 if (hw_mode & (1 << MODE_MF_SI)) {
747 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
748 "Configuring TAGMAC_CLS_TYPE\n");
749 STORE_RT_REG(p_hwfn,
750 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
751 }
752
753 /* Protocl Configuration */
754 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0);
755 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
756 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
757
758 /* Cleanup chip from previous driver if such remains exist */
759 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
760 if (rc != 0)
761 return rc;
762
763 /* PF Init sequence */
764 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
765 if (rc)
766 return rc;
767
768 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
769 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
770 if (rc)
771 return rc;
772
773 /* Pure runtime initializations - directly to the HW */
774 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
775
776 if (b_hw_start) {
777 /* enable interrupts */
778 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
779
780 /* send function start command */
781 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
782 allow_npar_tx_switch);
783 if (rc)
784 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
785 }
786 return rc;
787 }
788
789 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
790 struct qed_ptt *p_ptt,
791 u8 enable)
792 {
793 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
794
795 /* Change PF in PXP */
796 qed_wr(p_hwfn, p_ptt,
797 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
798
799 /* wait until value is set - try for 1 second every 50us */
800 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
801 val = qed_rd(p_hwfn, p_ptt,
802 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
803 if (val == set_val)
804 break;
805
806 usleep_range(50, 60);
807 }
808
809 if (val != set_val) {
810 DP_NOTICE(p_hwfn,
811 "PFID_ENABLE_MASTER wasn't changed after a second\n");
812 return -EAGAIN;
813 }
814
815 return 0;
816 }
817
818 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
819 struct qed_ptt *p_main_ptt)
820 {
821 /* Read shadow of current MFW mailbox */
822 qed_mcp_read_mb(p_hwfn, p_main_ptt);
823 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
824 p_hwfn->mcp_info->mfw_mb_cur,
825 p_hwfn->mcp_info->mfw_mb_length);
826 }
827
828 int qed_hw_init(struct qed_dev *cdev,
829 struct qed_tunn_start_params *p_tunn,
830 bool b_hw_start,
831 enum qed_int_mode int_mode,
832 bool allow_npar_tx_switch,
833 const u8 *bin_fw_data)
834 {
835 u32 load_code, param;
836 int rc, mfw_rc, i;
837
838 if (IS_PF(cdev)) {
839 rc = qed_init_fw_data(cdev, bin_fw_data);
840 if (rc != 0)
841 return rc;
842 }
843
844 for_each_hwfn(cdev, i) {
845 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
846
847 if (IS_VF(cdev)) {
848 p_hwfn->b_int_enabled = 1;
849 continue;
850 }
851
852 /* Enable DMAE in PXP */
853 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
854
855 qed_calc_hw_mode(p_hwfn);
856
857 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
858 &load_code);
859 if (rc) {
860 DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n");
861 return rc;
862 }
863
864 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
865
866 DP_VERBOSE(p_hwfn, QED_MSG_SP,
867 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
868 rc, load_code);
869
870 p_hwfn->first_on_engine = (load_code ==
871 FW_MSG_CODE_DRV_LOAD_ENGINE);
872
873 if (!qm_lock_init) {
874 spin_lock_init(&qm_lock);
875 qm_lock_init = true;
876 }
877
878 switch (load_code) {
879 case FW_MSG_CODE_DRV_LOAD_ENGINE:
880 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
881 p_hwfn->hw_info.hw_mode);
882 if (rc)
883 break;
884 /* Fall into */
885 case FW_MSG_CODE_DRV_LOAD_PORT:
886 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
887 p_hwfn->hw_info.hw_mode);
888 if (rc)
889 break;
890
891 /* Fall into */
892 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
893 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
894 p_tunn, p_hwfn->hw_info.hw_mode,
895 b_hw_start, int_mode,
896 allow_npar_tx_switch);
897 break;
898 default:
899 rc = -EINVAL;
900 break;
901 }
902
903 if (rc)
904 DP_NOTICE(p_hwfn,
905 "init phase failed for loadcode 0x%x (rc %d)\n",
906 load_code, rc);
907
908 /* ACK mfw regardless of success or failure of initialization */
909 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
910 DRV_MSG_CODE_LOAD_DONE,
911 0, &load_code, &param);
912 if (rc)
913 return rc;
914 if (mfw_rc) {
915 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
916 return mfw_rc;
917 }
918
919 /* send DCBX attention request command */
920 DP_VERBOSE(p_hwfn,
921 QED_MSG_DCB,
922 "sending phony dcbx set command to trigger DCBx attention handling\n");
923 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
924 DRV_MSG_CODE_SET_DCBX,
925 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
926 &load_code, &param);
927 if (mfw_rc) {
928 DP_NOTICE(p_hwfn,
929 "Failed to send DCBX attention request\n");
930 return mfw_rc;
931 }
932
933 p_hwfn->hw_init_done = true;
934 }
935
936 return 0;
937 }
938
939 #define QED_HW_STOP_RETRY_LIMIT (10)
940 static inline void qed_hw_timers_stop(struct qed_dev *cdev,
941 struct qed_hwfn *p_hwfn,
942 struct qed_ptt *p_ptt)
943 {
944 int i;
945
946 /* close timers */
947 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
948 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
949
950 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
951 if ((!qed_rd(p_hwfn, p_ptt,
952 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
953 (!qed_rd(p_hwfn, p_ptt,
954 TM_REG_PF_SCAN_ACTIVE_TASK)))
955 break;
956
957 /* Dependent on number of connection/tasks, possibly
958 * 1ms sleep is required between polls
959 */
960 usleep_range(1000, 2000);
961 }
962
963 if (i < QED_HW_STOP_RETRY_LIMIT)
964 return;
965
966 DP_NOTICE(p_hwfn,
967 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
968 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
969 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
970 }
971
972 void qed_hw_timers_stop_all(struct qed_dev *cdev)
973 {
974 int j;
975
976 for_each_hwfn(cdev, j) {
977 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
978 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
979
980 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
981 }
982 }
983
984 int qed_hw_stop(struct qed_dev *cdev)
985 {
986 int rc = 0, t_rc;
987 int j;
988
989 for_each_hwfn(cdev, j) {
990 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
991 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
992
993 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
994
995 if (IS_VF(cdev)) {
996 qed_vf_pf_int_cleanup(p_hwfn);
997 continue;
998 }
999
1000 /* mark the hw as uninitialized... */
1001 p_hwfn->hw_init_done = false;
1002
1003 rc = qed_sp_pf_stop(p_hwfn);
1004 if (rc)
1005 DP_NOTICE(p_hwfn,
1006 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1007
1008 qed_wr(p_hwfn, p_ptt,
1009 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1010
1011 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1012 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1013 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1014 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1015 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1016
1017 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1018
1019 /* Disable Attention Generation */
1020 qed_int_igu_disable_int(p_hwfn, p_ptt);
1021
1022 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1023 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1024
1025 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1026
1027 /* Need to wait 1ms to guarantee SBs are cleared */
1028 usleep_range(1000, 2000);
1029 }
1030
1031 if (IS_PF(cdev)) {
1032 /* Disable DMAE in PXP - in CMT, this should only be done for
1033 * first hw-function, and only after all transactions have
1034 * stopped for all active hw-functions.
1035 */
1036 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0],
1037 cdev->hwfns[0].p_main_ptt, false);
1038 if (t_rc != 0)
1039 rc = t_rc;
1040 }
1041
1042 return rc;
1043 }
1044
1045 void qed_hw_stop_fastpath(struct qed_dev *cdev)
1046 {
1047 int j;
1048
1049 for_each_hwfn(cdev, j) {
1050 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1051 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1052
1053 if (IS_VF(cdev)) {
1054 qed_vf_pf_int_cleanup(p_hwfn);
1055 continue;
1056 }
1057
1058 DP_VERBOSE(p_hwfn,
1059 NETIF_MSG_IFDOWN,
1060 "Shutting down the fastpath\n");
1061
1062 qed_wr(p_hwfn, p_ptt,
1063 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1064
1065 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1066 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1067 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1068 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1069 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1070
1071 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1072
1073 /* Need to wait 1ms to guarantee SBs are cleared */
1074 usleep_range(1000, 2000);
1075 }
1076 }
1077
1078 void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1079 {
1080 if (IS_VF(p_hwfn->cdev))
1081 return;
1082
1083 /* Re-open incoming traffic */
1084 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1085 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1086 }
1087
1088 static int qed_reg_assert(struct qed_hwfn *hwfn,
1089 struct qed_ptt *ptt, u32 reg,
1090 bool expected)
1091 {
1092 u32 assert_val = qed_rd(hwfn, ptt, reg);
1093
1094 if (assert_val != expected) {
1095 DP_NOTICE(hwfn, "Value at address 0x%x != 0x%08x\n",
1096 reg, expected);
1097 return -EINVAL;
1098 }
1099
1100 return 0;
1101 }
1102
1103 int qed_hw_reset(struct qed_dev *cdev)
1104 {
1105 int rc = 0;
1106 u32 unload_resp, unload_param;
1107 int i;
1108
1109 for_each_hwfn(cdev, i) {
1110 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1111
1112 if (IS_VF(cdev)) {
1113 rc = qed_vf_pf_reset(p_hwfn);
1114 if (rc)
1115 return rc;
1116 continue;
1117 }
1118
1119 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n");
1120
1121 /* Check for incorrect states */
1122 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1123 QM_REG_USG_CNT_PF_TX, 0);
1124 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1125 QM_REG_USG_CNT_PF_OTHER, 0);
1126
1127 /* Disable PF in HW blocks */
1128 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1129 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1130 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1131 TCFC_REG_STRONG_ENABLE_PF, 0);
1132 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1133 CCFC_REG_STRONG_ENABLE_PF, 0);
1134
1135 /* Send unload command to MCP */
1136 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1137 DRV_MSG_CODE_UNLOAD_REQ,
1138 DRV_MB_PARAM_UNLOAD_WOL_MCP,
1139 &unload_resp, &unload_param);
1140 if (rc) {
1141 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n");
1142 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1143 }
1144
1145 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1146 DRV_MSG_CODE_UNLOAD_DONE,
1147 0, &unload_resp, &unload_param);
1148 if (rc) {
1149 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n");
1150 return rc;
1151 }
1152 }
1153
1154 return rc;
1155 }
1156
1157 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1158 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1159 {
1160 qed_ptt_pool_free(p_hwfn);
1161 kfree(p_hwfn->hw_info.p_igu_info);
1162 }
1163
1164 /* Setup bar access */
1165 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
1166 {
1167 /* clear indirect access */
1168 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1169 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1170 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1171 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1172
1173 /* Clean Previous errors if such exist */
1174 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1175 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
1176 1 << p_hwfn->abs_pf_id);
1177
1178 /* enable internal target-read */
1179 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1180 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1181 }
1182
1183 static void get_function_id(struct qed_hwfn *p_hwfn)
1184 {
1185 /* ME Register */
1186 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR);
1187
1188 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1189
1190 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1191 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1192 PXP_CONCRETE_FID_PFID);
1193 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1194 PXP_CONCRETE_FID_PORT);
1195 }
1196
1197 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1198 {
1199 u32 *feat_num = p_hwfn->hw_info.feat_num;
1200 int num_features = 1;
1201
1202 feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
1203 num_features,
1204 RESC_NUM(p_hwfn, QED_L2_QUEUE));
1205 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1206 "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1207 feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB),
1208 num_features);
1209 }
1210
1211 static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
1212 {
1213 u32 *resc_start = p_hwfn->hw_info.resc_start;
1214 u8 num_funcs = p_hwfn->num_funcs_on_engine;
1215 u32 *resc_num = p_hwfn->hw_info.resc_num;
1216 struct qed_sb_cnt_info sb_cnt_info;
1217 int i, max_vf_vlan_filters;
1218
1219 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1220
1221 #ifdef CONFIG_QED_SRIOV
1222 max_vf_vlan_filters = QED_ETH_MAX_VF_NUM_VLAN_FILTERS;
1223 #else
1224 max_vf_vlan_filters = 0;
1225 #endif
1226
1227 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1228
1229 resc_num[QED_SB] = min_t(u32,
1230 (MAX_SB_PER_PATH_BB / num_funcs),
1231 sb_cnt_info.sb_cnt);
1232 resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;
1233 resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
1234 resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
1235 resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
1236 resc_num[QED_RL] = 8;
1237 resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
1238 resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
1239 num_funcs;
1240 resc_num[QED_ILT] = 950;
1241
1242 for (i = 0; i < QED_MAX_RESC; i++)
1243 resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
1244
1245 qed_hw_set_feat(p_hwfn);
1246
1247 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1248 "The numbers for each resource are:\n"
1249 "SB = %d start = %d\n"
1250 "L2_QUEUE = %d start = %d\n"
1251 "VPORT = %d start = %d\n"
1252 "PQ = %d start = %d\n"
1253 "RL = %d start = %d\n"
1254 "MAC = %d start = %d\n"
1255 "VLAN = %d start = %d\n"
1256 "ILT = %d start = %d\n",
1257 p_hwfn->hw_info.resc_num[QED_SB],
1258 p_hwfn->hw_info.resc_start[QED_SB],
1259 p_hwfn->hw_info.resc_num[QED_L2_QUEUE],
1260 p_hwfn->hw_info.resc_start[QED_L2_QUEUE],
1261 p_hwfn->hw_info.resc_num[QED_VPORT],
1262 p_hwfn->hw_info.resc_start[QED_VPORT],
1263 p_hwfn->hw_info.resc_num[QED_PQ],
1264 p_hwfn->hw_info.resc_start[QED_PQ],
1265 p_hwfn->hw_info.resc_num[QED_RL],
1266 p_hwfn->hw_info.resc_start[QED_RL],
1267 p_hwfn->hw_info.resc_num[QED_MAC],
1268 p_hwfn->hw_info.resc_start[QED_MAC],
1269 p_hwfn->hw_info.resc_num[QED_VLAN],
1270 p_hwfn->hw_info.resc_start[QED_VLAN],
1271 p_hwfn->hw_info.resc_num[QED_ILT],
1272 p_hwfn->hw_info.resc_start[QED_ILT]);
1273 }
1274
1275 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn,
1276 struct qed_ptt *p_ptt)
1277 {
1278 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
1279 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
1280 struct qed_mcp_link_params *link;
1281
1282 /* Read global nvm_cfg address */
1283 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1284
1285 /* Verify MCP has initialized it */
1286 if (!nvm_cfg_addr) {
1287 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1288 return -EINVAL;
1289 }
1290
1291 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
1292 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1293
1294 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1295 offsetof(struct nvm_cfg1, glob) +
1296 offsetof(struct nvm_cfg1_glob, core_cfg);
1297
1298 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
1299
1300 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1301 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
1302 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G:
1303 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
1304 break;
1305 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G:
1306 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
1307 break;
1308 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G:
1309 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
1310 break;
1311 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F:
1312 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
1313 break;
1314 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E:
1315 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
1316 break;
1317 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G:
1318 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
1319 break;
1320 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G:
1321 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
1322 break;
1323 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G:
1324 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
1325 break;
1326 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G:
1327 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
1328 break;
1329 default:
1330 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n",
1331 core_cfg);
1332 break;
1333 }
1334
1335 /* Read default link configuration */
1336 link = &p_hwfn->mcp_info->link_input;
1337 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1338 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1339 link_temp = qed_rd(p_hwfn, p_ptt,
1340 port_cfg_addr +
1341 offsetof(struct nvm_cfg1_port, speed_cap_mask));
1342 link->speed.advertised_speeds =
1343 link_temp & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1344
1345 p_hwfn->mcp_info->link_capabilities.speed_capabilities =
1346 link->speed.advertised_speeds;
1347
1348 link_temp = qed_rd(p_hwfn, p_ptt,
1349 port_cfg_addr +
1350 offsetof(struct nvm_cfg1_port, link_settings));
1351 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1352 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1353 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1354 link->speed.autoneg = true;
1355 break;
1356 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1357 link->speed.forced_speed = 1000;
1358 break;
1359 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1360 link->speed.forced_speed = 10000;
1361 break;
1362 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1363 link->speed.forced_speed = 25000;
1364 break;
1365 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1366 link->speed.forced_speed = 40000;
1367 break;
1368 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1369 link->speed.forced_speed = 50000;
1370 break;
1371 case NVM_CFG1_PORT_DRV_LINK_SPEED_100G:
1372 link->speed.forced_speed = 100000;
1373 break;
1374 default:
1375 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n",
1376 link_temp);
1377 }
1378
1379 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1380 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1381 link->pause.autoneg = !!(link_temp &
1382 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1383 link->pause.forced_rx = !!(link_temp &
1384 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1385 link->pause.forced_tx = !!(link_temp &
1386 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1387 link->loopback_mode = 0;
1388
1389 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1390 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1391 link->speed.forced_speed, link->speed.advertised_speeds,
1392 link->speed.autoneg, link->pause.autoneg);
1393
1394 /* Read Multi-function information from shmem */
1395 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1396 offsetof(struct nvm_cfg1, glob) +
1397 offsetof(struct nvm_cfg1_glob, generic_cont0);
1398
1399 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
1400
1401 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1402 NVM_CFG1_GLOB_MF_MODE_OFFSET;
1403
1404 switch (mf_mode) {
1405 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
1406 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
1407 break;
1408 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
1409 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
1410 break;
1411 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1412 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
1413 break;
1414 }
1415 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1416 p_hwfn->cdev->mf_mode);
1417
1418 /* Read Multi-function information from shmem */
1419 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1420 offsetof(struct nvm_cfg1, glob) +
1421 offsetof(struct nvm_cfg1_glob, device_capabilities);
1422
1423 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
1424 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1425 __set_bit(QED_DEV_CAP_ETH,
1426 &p_hwfn->hw_info.device_capabilities);
1427
1428 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1429 }
1430
1431 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1432 {
1433 u32 reg_function_hide, tmp, eng_mask;
1434 u8 num_funcs;
1435
1436 num_funcs = MAX_NUM_PFS_BB;
1437
1438 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1439 * in the other bits are selected.
1440 * Bits 1-15 are for functions 1-15, respectively, and their value is
1441 * '0' only for enabled functions (function 0 always exists and
1442 * enabled).
1443 * In case of CMT, only the "even" functions are enabled, and thus the
1444 * number of functions for both hwfns is learnt from the same bits.
1445 */
1446 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
1447
1448 if (reg_function_hide & 0x1) {
1449 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) {
1450 num_funcs = 0;
1451 eng_mask = 0xaaaa;
1452 } else {
1453 num_funcs = 1;
1454 eng_mask = 0x5554;
1455 }
1456
1457 /* Get the number of the enabled functions on the engine */
1458 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
1459 while (tmp) {
1460 if (tmp & 0x1)
1461 num_funcs++;
1462 tmp >>= 0x1;
1463 }
1464 }
1465
1466 p_hwfn->num_funcs_on_engine = num_funcs;
1467
1468 DP_VERBOSE(p_hwfn,
1469 NETIF_MSG_PROBE,
1470 "PF [rel_id %d, abs_id %d] within the %d enabled functions on the engine\n",
1471 p_hwfn->rel_pf_id,
1472 p_hwfn->abs_pf_id,
1473 p_hwfn->num_funcs_on_engine);
1474 }
1475
1476 static int
1477 qed_get_hw_info(struct qed_hwfn *p_hwfn,
1478 struct qed_ptt *p_ptt,
1479 enum qed_pci_personality personality)
1480 {
1481 u32 port_mode;
1482 int rc;
1483
1484 /* Since all information is common, only first hwfns should do this */
1485 if (IS_LEAD_HWFN(p_hwfn)) {
1486 rc = qed_iov_hw_info(p_hwfn);
1487 if (rc)
1488 return rc;
1489 }
1490
1491 /* Read the port mode */
1492 port_mode = qed_rd(p_hwfn, p_ptt,
1493 CNIG_REG_NW_PORT_MODE_BB_B0);
1494
1495 if (port_mode < 3) {
1496 p_hwfn->cdev->num_ports_in_engines = 1;
1497 } else if (port_mode <= 5) {
1498 p_hwfn->cdev->num_ports_in_engines = 2;
1499 } else {
1500 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
1501 p_hwfn->cdev->num_ports_in_engines);
1502
1503 /* Default num_ports_in_engines to something */
1504 p_hwfn->cdev->num_ports_in_engines = 1;
1505 }
1506
1507 qed_hw_get_nvm_info(p_hwfn, p_ptt);
1508
1509 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
1510 if (rc)
1511 return rc;
1512
1513 if (qed_mcp_is_init(p_hwfn))
1514 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
1515 p_hwfn->mcp_info->func_info.mac);
1516 else
1517 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
1518
1519 if (qed_mcp_is_init(p_hwfn)) {
1520 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
1521 p_hwfn->hw_info.ovlan =
1522 p_hwfn->mcp_info->func_info.ovlan;
1523
1524 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
1525 }
1526
1527 if (qed_mcp_is_init(p_hwfn)) {
1528 enum qed_pci_personality protocol;
1529
1530 protocol = p_hwfn->mcp_info->func_info.protocol;
1531 p_hwfn->hw_info.personality = protocol;
1532 }
1533
1534 qed_get_num_funcs(p_hwfn, p_ptt);
1535
1536 qed_hw_get_resc(p_hwfn);
1537
1538 return rc;
1539 }
1540
1541 static int qed_get_dev_info(struct qed_dev *cdev)
1542 {
1543 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1544 u32 tmp;
1545
1546 /* Read Vendor Id / Device Id */
1547 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID,
1548 &cdev->vendor_id);
1549 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID,
1550 &cdev->device_id);
1551 cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1552 MISCS_REG_CHIP_NUM);
1553 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1554 MISCS_REG_CHIP_REV);
1555 MASK_FIELD(CHIP_REV, cdev->chip_rev);
1556
1557 cdev->type = QED_DEV_TYPE_BB;
1558 /* Learn number of HW-functions */
1559 tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1560 MISCS_REG_CMT_ENABLED_FOR_PAIR);
1561
1562 if (tmp & (1 << p_hwfn->rel_pf_id)) {
1563 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
1564 cdev->num_hwfns = 2;
1565 } else {
1566 cdev->num_hwfns = 1;
1567 }
1568
1569 cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1570 MISCS_REG_CHIP_TEST_REG) >> 4;
1571 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
1572 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
1573 MISCS_REG_CHIP_METAL);
1574 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
1575
1576 DP_INFO(cdev->hwfns,
1577 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
1578 cdev->chip_num, cdev->chip_rev,
1579 cdev->chip_bond_id, cdev->chip_metal);
1580
1581 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
1582 DP_NOTICE(cdev->hwfns,
1583 "The chip type/rev (BB A0) is not supported!\n");
1584 return -EINVAL;
1585 }
1586
1587 return 0;
1588 }
1589
1590 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
1591 void __iomem *p_regview,
1592 void __iomem *p_doorbells,
1593 enum qed_pci_personality personality)
1594 {
1595 int rc = 0;
1596
1597 /* Split PCI bars evenly between hwfns */
1598 p_hwfn->regview = p_regview;
1599 p_hwfn->doorbells = p_doorbells;
1600
1601 if (IS_VF(p_hwfn->cdev))
1602 return qed_vf_hw_prepare(p_hwfn);
1603
1604 /* Validate that chip access is feasible */
1605 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
1606 DP_ERR(p_hwfn,
1607 "Reading the ME register returns all Fs; Preventing further chip access\n");
1608 return -EINVAL;
1609 }
1610
1611 get_function_id(p_hwfn);
1612
1613 /* Allocate PTT pool */
1614 rc = qed_ptt_pool_alloc(p_hwfn);
1615 if (rc) {
1616 DP_NOTICE(p_hwfn, "Failed to prepare hwfn's hw\n");
1617 goto err0;
1618 }
1619
1620 /* Allocate the main PTT */
1621 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
1622
1623 /* First hwfn learns basic information, e.g., number of hwfns */
1624 if (!p_hwfn->my_id) {
1625 rc = qed_get_dev_info(p_hwfn->cdev);
1626 if (rc != 0)
1627 goto err1;
1628 }
1629
1630 qed_hw_hwfn_prepare(p_hwfn);
1631
1632 /* Initialize MCP structure */
1633 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
1634 if (rc) {
1635 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
1636 goto err1;
1637 }
1638
1639 /* Read the device configuration information from the HW and SHMEM */
1640 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
1641 if (rc) {
1642 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
1643 goto err2;
1644 }
1645
1646 /* Allocate the init RT array and initialize the init-ops engine */
1647 rc = qed_init_alloc(p_hwfn);
1648 if (rc) {
1649 DP_NOTICE(p_hwfn, "Failed to allocate the init array\n");
1650 goto err2;
1651 }
1652
1653 return rc;
1654 err2:
1655 if (IS_LEAD_HWFN(p_hwfn))
1656 qed_iov_free_hw_info(p_hwfn->cdev);
1657 qed_mcp_free(p_hwfn);
1658 err1:
1659 qed_hw_hwfn_free(p_hwfn);
1660 err0:
1661 return rc;
1662 }
1663
1664 int qed_hw_prepare(struct qed_dev *cdev,
1665 int personality)
1666 {
1667 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1668 int rc;
1669
1670 /* Store the precompiled init data ptrs */
1671 if (IS_PF(cdev))
1672 qed_init_iro_array(cdev);
1673
1674 /* Initialize the first hwfn - will learn number of hwfns */
1675 rc = qed_hw_prepare_single(p_hwfn,
1676 cdev->regview,
1677 cdev->doorbells, personality);
1678 if (rc)
1679 return rc;
1680
1681 personality = p_hwfn->hw_info.personality;
1682
1683 /* Initialize the rest of the hwfns */
1684 if (cdev->num_hwfns > 1) {
1685 void __iomem *p_regview, *p_doorbell;
1686 u8 __iomem *addr;
1687
1688 /* adjust bar offset for second engine */
1689 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
1690 p_regview = addr;
1691
1692 /* adjust doorbell bar offset for second engine */
1693 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
1694 p_doorbell = addr;
1695
1696 /* prepare second hw function */
1697 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
1698 p_doorbell, personality);
1699
1700 /* in case of error, need to free the previously
1701 * initiliazed hwfn 0.
1702 */
1703 if (rc) {
1704 if (IS_PF(cdev)) {
1705 qed_init_free(p_hwfn);
1706 qed_mcp_free(p_hwfn);
1707 qed_hw_hwfn_free(p_hwfn);
1708 }
1709 }
1710 }
1711
1712 return rc;
1713 }
1714
1715 void qed_hw_remove(struct qed_dev *cdev)
1716 {
1717 int i;
1718
1719 for_each_hwfn(cdev, i) {
1720 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1721
1722 if (IS_VF(cdev)) {
1723 qed_vf_pf_release(p_hwfn);
1724 continue;
1725 }
1726
1727 qed_init_free(p_hwfn);
1728 qed_hw_hwfn_free(p_hwfn);
1729 qed_mcp_free(p_hwfn);
1730 }
1731
1732 qed_iov_free_hw_info(cdev);
1733 }
1734
1735 int qed_chain_alloc(struct qed_dev *cdev,
1736 enum qed_chain_use_mode intended_use,
1737 enum qed_chain_mode mode,
1738 u16 num_elems,
1739 size_t elem_size,
1740 struct qed_chain *p_chain)
1741 {
1742 dma_addr_t p_pbl_phys = 0;
1743 void *p_pbl_virt = NULL;
1744 dma_addr_t p_phys = 0;
1745 void *p_virt = NULL;
1746 u16 page_cnt = 0;
1747 size_t size;
1748
1749 if (mode == QED_CHAIN_MODE_SINGLE)
1750 page_cnt = 1;
1751 else
1752 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
1753
1754 size = page_cnt * QED_CHAIN_PAGE_SIZE;
1755 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
1756 size, &p_phys, GFP_KERNEL);
1757 if (!p_virt) {
1758 DP_NOTICE(cdev, "Failed to allocate chain mem\n");
1759 goto nomem;
1760 }
1761
1762 if (mode == QED_CHAIN_MODE_PBL) {
1763 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
1764 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
1765 size, &p_pbl_phys,
1766 GFP_KERNEL);
1767 if (!p_pbl_virt) {
1768 DP_NOTICE(cdev, "Failed to allocate chain pbl mem\n");
1769 goto nomem;
1770 }
1771
1772 qed_chain_pbl_init(p_chain, p_virt, p_phys, page_cnt,
1773 (u8)elem_size, intended_use,
1774 p_pbl_phys, p_pbl_virt);
1775 } else {
1776 qed_chain_init(p_chain, p_virt, p_phys, page_cnt,
1777 (u8)elem_size, intended_use, mode);
1778 }
1779
1780 return 0;
1781
1782 nomem:
1783 dma_free_coherent(&cdev->pdev->dev,
1784 page_cnt * QED_CHAIN_PAGE_SIZE,
1785 p_virt, p_phys);
1786 dma_free_coherent(&cdev->pdev->dev,
1787 page_cnt * QED_CHAIN_PBL_ENTRY_SIZE,
1788 p_pbl_virt, p_pbl_phys);
1789
1790 return -ENOMEM;
1791 }
1792
1793 void qed_chain_free(struct qed_dev *cdev,
1794 struct qed_chain *p_chain)
1795 {
1796 size_t size;
1797
1798 if (!p_chain->p_virt_addr)
1799 return;
1800
1801 if (p_chain->mode == QED_CHAIN_MODE_PBL) {
1802 size = p_chain->page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
1803 dma_free_coherent(&cdev->pdev->dev, size,
1804 p_chain->pbl.p_virt_table,
1805 p_chain->pbl.p_phys_table);
1806 }
1807
1808 size = p_chain->page_cnt * QED_CHAIN_PAGE_SIZE;
1809 dma_free_coherent(&cdev->pdev->dev, size,
1810 p_chain->p_virt_addr,
1811 p_chain->p_phys_addr);
1812 }
1813
1814 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn,
1815 u16 src_id, u16 *dst_id)
1816 {
1817 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
1818 u16 min, max;
1819
1820 min = (u16)RESC_START(p_hwfn, QED_L2_QUEUE);
1821 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
1822 DP_NOTICE(p_hwfn,
1823 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
1824 src_id, min, max);
1825
1826 return -EINVAL;
1827 }
1828
1829 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
1830
1831 return 0;
1832 }
1833
1834 int qed_fw_vport(struct qed_hwfn *p_hwfn,
1835 u8 src_id, u8 *dst_id)
1836 {
1837 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
1838 u8 min, max;
1839
1840 min = (u8)RESC_START(p_hwfn, QED_VPORT);
1841 max = min + RESC_NUM(p_hwfn, QED_VPORT);
1842 DP_NOTICE(p_hwfn,
1843 "vport id [%d] is not valid, available indices [%d - %d]\n",
1844 src_id, min, max);
1845
1846 return -EINVAL;
1847 }
1848
1849 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
1850
1851 return 0;
1852 }
1853
1854 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn,
1855 u8 src_id, u8 *dst_id)
1856 {
1857 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
1858 u8 min, max;
1859
1860 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
1861 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
1862 DP_NOTICE(p_hwfn,
1863 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
1864 src_id, min, max);
1865
1866 return -EINVAL;
1867 }
1868
1869 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
1870
1871 return 0;
1872 }
1873
1874 /* Calculate final WFQ values for all vports and configure them.
1875 * After this configuration each vport will have
1876 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
1877 */
1878 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
1879 struct qed_ptt *p_ptt,
1880 u32 min_pf_rate)
1881 {
1882 struct init_qm_vport_params *vport_params;
1883 int i;
1884
1885 vport_params = p_hwfn->qm_info.qm_vport_params;
1886
1887 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
1888 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
1889
1890 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
1891 min_pf_rate;
1892 qed_init_vport_wfq(p_hwfn, p_ptt,
1893 vport_params[i].first_tx_pq_id,
1894 vport_params[i].vport_wfq);
1895 }
1896 }
1897
1898 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
1899 u32 min_pf_rate)
1900
1901 {
1902 int i;
1903
1904 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
1905 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
1906 }
1907
1908 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
1909 struct qed_ptt *p_ptt,
1910 u32 min_pf_rate)
1911 {
1912 struct init_qm_vport_params *vport_params;
1913 int i;
1914
1915 vport_params = p_hwfn->qm_info.qm_vport_params;
1916
1917 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
1918 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
1919 qed_init_vport_wfq(p_hwfn, p_ptt,
1920 vport_params[i].first_tx_pq_id,
1921 vport_params[i].vport_wfq);
1922 }
1923 }
1924
1925 /* This function performs several validations for WFQ
1926 * configuration and required min rate for a given vport
1927 * 1. req_rate must be greater than one percent of min_pf_rate.
1928 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
1929 * rates to get less than one percent of min_pf_rate.
1930 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
1931 */
1932 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
1933 u16 vport_id, u32 req_rate,
1934 u32 min_pf_rate)
1935 {
1936 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
1937 int non_requested_count = 0, req_count = 0, i, num_vports;
1938
1939 num_vports = p_hwfn->qm_info.num_vports;
1940
1941 /* Accounting for the vports which are configured for WFQ explicitly */
1942 for (i = 0; i < num_vports; i++) {
1943 u32 tmp_speed;
1944
1945 if ((i != vport_id) &&
1946 p_hwfn->qm_info.wfq_data[i].configured) {
1947 req_count++;
1948 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
1949 total_req_min_rate += tmp_speed;
1950 }
1951 }
1952
1953 /* Include current vport data as well */
1954 req_count++;
1955 total_req_min_rate += req_rate;
1956 non_requested_count = num_vports - req_count;
1957
1958 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
1959 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1960 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
1961 vport_id, req_rate, min_pf_rate);
1962 return -EINVAL;
1963 }
1964
1965 if (num_vports > QED_WFQ_UNIT) {
1966 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1967 "Number of vports is greater than %d\n",
1968 QED_WFQ_UNIT);
1969 return -EINVAL;
1970 }
1971
1972 if (total_req_min_rate > min_pf_rate) {
1973 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1974 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
1975 total_req_min_rate, min_pf_rate);
1976 return -EINVAL;
1977 }
1978
1979 total_left_rate = min_pf_rate - total_req_min_rate;
1980
1981 left_rate_per_vp = total_left_rate / non_requested_count;
1982 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
1983 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1984 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
1985 left_rate_per_vp, min_pf_rate);
1986 return -EINVAL;
1987 }
1988
1989 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
1990 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
1991
1992 for (i = 0; i < num_vports; i++) {
1993 if (p_hwfn->qm_info.wfq_data[i].configured)
1994 continue;
1995
1996 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
1997 }
1998
1999 return 0;
2000 }
2001
2002 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
2003 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
2004 {
2005 struct qed_mcp_link_state *p_link;
2006 int rc = 0;
2007
2008 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
2009
2010 if (!p_link->min_pf_rate) {
2011 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
2012 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
2013 return rc;
2014 }
2015
2016 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
2017
2018 if (rc == 0)
2019 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
2020 p_link->min_pf_rate);
2021 else
2022 DP_NOTICE(p_hwfn,
2023 "Validation failed while configuring min rate\n");
2024
2025 return rc;
2026 }
2027
2028 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
2029 struct qed_ptt *p_ptt,
2030 u32 min_pf_rate)
2031 {
2032 bool use_wfq = false;
2033 int rc = 0;
2034 u16 i;
2035
2036 /* Validate all pre configured vports for wfq */
2037 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2038 u32 rate;
2039
2040 if (!p_hwfn->qm_info.wfq_data[i].configured)
2041 continue;
2042
2043 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
2044 use_wfq = true;
2045
2046 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
2047 if (rc) {
2048 DP_NOTICE(p_hwfn,
2049 "WFQ validation failed while configuring min rate\n");
2050 break;
2051 }
2052 }
2053
2054 if (!rc && use_wfq)
2055 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2056 else
2057 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2058
2059 return rc;
2060 }
2061
2062 /* Main API for qed clients to configure vport min rate.
2063 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
2064 * rate - Speed in Mbps needs to be assigned to a given vport.
2065 */
2066 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
2067 {
2068 int i, rc = -EINVAL;
2069
2070 /* Currently not supported; Might change in future */
2071 if (cdev->num_hwfns > 1) {
2072 DP_NOTICE(cdev,
2073 "WFQ configuration is not supported for this device\n");
2074 return rc;
2075 }
2076
2077 for_each_hwfn(cdev, i) {
2078 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2079 struct qed_ptt *p_ptt;
2080
2081 p_ptt = qed_ptt_acquire(p_hwfn);
2082 if (!p_ptt)
2083 return -EBUSY;
2084
2085 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
2086
2087 if (!rc) {
2088 qed_ptt_release(p_hwfn, p_ptt);
2089 return rc;
2090 }
2091
2092 qed_ptt_release(p_hwfn, p_ptt);
2093 }
2094
2095 return rc;
2096 }
2097
2098 /* API to configure WFQ from mcp link change */
2099 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate)
2100 {
2101 int i;
2102
2103 for_each_hwfn(cdev, i) {
2104 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2105
2106 __qed_configure_vp_wfq_on_link_change(p_hwfn,
2107 p_hwfn->p_dpc_ptt,
2108 min_pf_rate);
2109 }
2110 }
2111
2112 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
2113 struct qed_ptt *p_ptt,
2114 struct qed_mcp_link_state *p_link,
2115 u8 max_bw)
2116 {
2117 int rc = 0;
2118
2119 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
2120
2121 if (!p_link->line_speed && (max_bw != 100))
2122 return rc;
2123
2124 p_link->speed = (p_link->line_speed * max_bw) / 100;
2125 p_hwfn->qm_info.pf_rl = p_link->speed;
2126
2127 /* Since the limiter also affects Tx-switched traffic, we don't want it
2128 * to limit such traffic in case there's no actual limit.
2129 * In that case, set limit to imaginary high boundary.
2130 */
2131 if (max_bw == 100)
2132 p_hwfn->qm_info.pf_rl = 100000;
2133
2134 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
2135 p_hwfn->qm_info.pf_rl);
2136
2137 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2138 "Configured MAX bandwidth to be %08x Mb/sec\n",
2139 p_link->speed);
2140
2141 return rc;
2142 }
2143
2144 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
2145 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
2146 {
2147 int i, rc = -EINVAL;
2148
2149 if (max_bw < 1 || max_bw > 100) {
2150 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
2151 return rc;
2152 }
2153
2154 for_each_hwfn(cdev, i) {
2155 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2156 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2157 struct qed_mcp_link_state *p_link;
2158 struct qed_ptt *p_ptt;
2159
2160 p_link = &p_lead->mcp_info->link_output;
2161
2162 p_ptt = qed_ptt_acquire(p_hwfn);
2163 if (!p_ptt)
2164 return -EBUSY;
2165
2166 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
2167 p_link, max_bw);
2168
2169 qed_ptt_release(p_hwfn, p_ptt);
2170
2171 if (rc)
2172 break;
2173 }
2174
2175 return rc;
2176 }
2177
2178 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
2179 struct qed_ptt *p_ptt,
2180 struct qed_mcp_link_state *p_link,
2181 u8 min_bw)
2182 {
2183 int rc = 0;
2184
2185 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
2186 p_hwfn->qm_info.pf_wfq = min_bw;
2187
2188 if (!p_link->line_speed)
2189 return rc;
2190
2191 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
2192
2193 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
2194
2195 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2196 "Configured MIN bandwidth to be %d Mb/sec\n",
2197 p_link->min_pf_rate);
2198
2199 return rc;
2200 }
2201
2202 /* Main API to configure PF min bandwidth where bw range is [1-100] */
2203 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
2204 {
2205 int i, rc = -EINVAL;
2206
2207 if (min_bw < 1 || min_bw > 100) {
2208 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
2209 return rc;
2210 }
2211
2212 for_each_hwfn(cdev, i) {
2213 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2214 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
2215 struct qed_mcp_link_state *p_link;
2216 struct qed_ptt *p_ptt;
2217
2218 p_link = &p_lead->mcp_info->link_output;
2219
2220 p_ptt = qed_ptt_acquire(p_hwfn);
2221 if (!p_ptt)
2222 return -EBUSY;
2223
2224 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
2225 p_link, min_bw);
2226 if (rc) {
2227 qed_ptt_release(p_hwfn, p_ptt);
2228 return rc;
2229 }
2230
2231 if (p_link->min_pf_rate) {
2232 u32 min_rate = p_link->min_pf_rate;
2233
2234 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
2235 p_ptt,
2236 min_rate);
2237 }
2238
2239 qed_ptt_release(p_hwfn, p_ptt);
2240 }
2241
2242 return rc;
2243 }
2244
2245 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2246 {
2247 struct qed_mcp_link_state *p_link;
2248
2249 p_link = &p_hwfn->mcp_info->link_output;
2250
2251 if (p_link->min_pf_rate)
2252 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
2253 p_link->min_pf_rate);
2254
2255 memset(p_hwfn->qm_info.wfq_data, 0,
2256 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
2257 }
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