1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
9 #include <linux/types.h>
10 #include <asm/byteorder.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16 #include <linux/mutex.h>
17 #include <linux/pci.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/etherdevice.h>
21 #include <linux/qed/qed_chain.h>
22 #include <linux/qed/qed_if.h>
26 #include "qed_dev_api.h"
29 #include "qed_init_ops.h"
32 #include "qed_reg_addr.h"
34 #include "qed_sriov.h"
37 static spinlock_t qm_lock
;
38 static bool qm_lock_init
= false;
40 /* API common to all protocols */
42 BAR_ID_0
, /* used for GRC */
43 BAR_ID_1
/* Used for doorbells */
46 static u32
qed_hw_bar_size(struct qed_hwfn
*p_hwfn
,
49 u32 bar_reg
= (bar_id
== BAR_ID_0
?
50 PGLUE_B_REG_PF_BAR0_SIZE
: PGLUE_B_REG_PF_BAR1_SIZE
);
53 if (IS_VF(p_hwfn
->cdev
))
56 val
= qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
, bar_reg
);
58 return 1 << (val
+ 15);
60 /* Old MFW initialized above registered only conditionally */
61 if (p_hwfn
->cdev
->num_hwfns
> 1) {
63 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
64 return BAR_ID_0
? 256 * 1024 : 512 * 1024;
67 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
72 void qed_init_dp(struct qed_dev
*cdev
,
73 u32 dp_module
, u8 dp_level
)
77 cdev
->dp_level
= dp_level
;
78 cdev
->dp_module
= dp_module
;
79 for (i
= 0; i
< MAX_HWFNS_PER_DEVICE
; i
++) {
80 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
82 p_hwfn
->dp_level
= dp_level
;
83 p_hwfn
->dp_module
= dp_module
;
87 void qed_init_struct(struct qed_dev
*cdev
)
91 for (i
= 0; i
< MAX_HWFNS_PER_DEVICE
; i
++) {
92 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
96 p_hwfn
->b_active
= false;
98 mutex_init(&p_hwfn
->dmae_info
.mutex
);
101 /* hwfn 0 is always active */
102 cdev
->hwfns
[0].b_active
= true;
104 /* set the default cache alignment to 128 */
105 cdev
->cache_shift
= 7;
108 static void qed_qm_info_free(struct qed_hwfn
*p_hwfn
)
110 struct qed_qm_info
*qm_info
= &p_hwfn
->qm_info
;
112 kfree(qm_info
->qm_pq_params
);
113 qm_info
->qm_pq_params
= NULL
;
114 kfree(qm_info
->qm_vport_params
);
115 qm_info
->qm_vport_params
= NULL
;
116 kfree(qm_info
->qm_port_params
);
117 qm_info
->qm_port_params
= NULL
;
118 kfree(qm_info
->wfq_data
);
119 qm_info
->wfq_data
= NULL
;
122 void qed_resc_free(struct qed_dev
*cdev
)
129 kfree(cdev
->fw_data
);
130 cdev
->fw_data
= NULL
;
132 kfree(cdev
->reset_stats
);
134 for_each_hwfn(cdev
, i
) {
135 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
137 kfree(p_hwfn
->p_tx_cids
);
138 p_hwfn
->p_tx_cids
= NULL
;
139 kfree(p_hwfn
->p_rx_cids
);
140 p_hwfn
->p_rx_cids
= NULL
;
143 for_each_hwfn(cdev
, i
) {
144 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
146 qed_cxt_mngr_free(p_hwfn
);
147 qed_qm_info_free(p_hwfn
);
148 qed_spq_free(p_hwfn
);
149 qed_eq_free(p_hwfn
, p_hwfn
->p_eq
);
150 qed_consq_free(p_hwfn
, p_hwfn
->p_consq
);
151 qed_int_free(p_hwfn
);
152 qed_iov_free(p_hwfn
);
153 qed_dmae_info_free(p_hwfn
);
154 qed_dcbx_info_free(p_hwfn
, p_hwfn
->p_dcbx_info
);
158 static int qed_init_qm_info(struct qed_hwfn
*p_hwfn
)
160 u8 num_vports
, vf_offset
= 0, i
, vport_id
, num_ports
, curr_queue
= 0;
161 struct qed_qm_info
*qm_info
= &p_hwfn
->qm_info
;
162 struct init_qm_port_params
*p_qm_port
;
163 u16 num_pqs
, multi_cos_tcs
= 1;
166 #ifdef CONFIG_QED_SRIOV
167 if (p_hwfn
->cdev
->p_iov_info
)
168 num_vfs
= p_hwfn
->cdev
->p_iov_info
->total_vfs
;
170 memset(qm_info
, 0, sizeof(*qm_info
));
172 num_pqs
= multi_cos_tcs
+ num_vfs
+ 1; /* The '1' is for pure-LB */
173 num_vports
= (u8
)RESC_NUM(p_hwfn
, QED_VPORT
);
175 /* Sanity checking that setup requires legal number of resources */
176 if (num_pqs
> RESC_NUM(p_hwfn
, QED_PQ
)) {
178 "Need too many Physical queues - 0x%04x when only %04x are available\n",
179 num_pqs
, RESC_NUM(p_hwfn
, QED_PQ
));
183 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
185 qm_info
->qm_pq_params
= kzalloc(sizeof(*qm_info
->qm_pq_params
) *
186 num_pqs
, GFP_KERNEL
);
187 if (!qm_info
->qm_pq_params
)
190 qm_info
->qm_vport_params
= kzalloc(sizeof(*qm_info
->qm_vport_params
) *
191 num_vports
, GFP_KERNEL
);
192 if (!qm_info
->qm_vport_params
)
195 qm_info
->qm_port_params
= kzalloc(sizeof(*qm_info
->qm_port_params
) *
196 MAX_NUM_PORTS
, GFP_KERNEL
);
197 if (!qm_info
->qm_port_params
)
200 qm_info
->wfq_data
= kcalloc(num_vports
, sizeof(*qm_info
->wfq_data
),
202 if (!qm_info
->wfq_data
)
205 vport_id
= (u8
)RESC_START(p_hwfn
, QED_VPORT
);
207 /* First init per-TC PQs */
208 for (i
= 0; i
< multi_cos_tcs
; i
++) {
209 struct init_qm_pq_params
*params
=
210 &qm_info
->qm_pq_params
[curr_queue
++];
212 if (p_hwfn
->hw_info
.personality
== QED_PCI_ETH
) {
213 params
->vport_id
= vport_id
;
214 params
->tc_id
= p_hwfn
->hw_info
.non_offload_tc
;
215 params
->wrr_group
= 1;
217 params
->vport_id
= vport_id
;
218 params
->tc_id
= p_hwfn
->hw_info
.offload_tc
;
219 params
->wrr_group
= 1;
223 /* Then init pure-LB PQ */
224 qm_info
->pure_lb_pq
= curr_queue
;
225 qm_info
->qm_pq_params
[curr_queue
].vport_id
=
226 (u8
) RESC_START(p_hwfn
, QED_VPORT
);
227 qm_info
->qm_pq_params
[curr_queue
].tc_id
= PURE_LB_TC
;
228 qm_info
->qm_pq_params
[curr_queue
].wrr_group
= 1;
231 qm_info
->offload_pq
= 0;
232 /* Then init per-VF PQs */
233 vf_offset
= curr_queue
;
234 for (i
= 0; i
< num_vfs
; i
++) {
235 /* First vport is used by the PF */
236 qm_info
->qm_pq_params
[curr_queue
].vport_id
= vport_id
+ i
+ 1;
237 qm_info
->qm_pq_params
[curr_queue
].tc_id
=
238 p_hwfn
->hw_info
.non_offload_tc
;
239 qm_info
->qm_pq_params
[curr_queue
].wrr_group
= 1;
243 qm_info
->vf_queues_offset
= vf_offset
;
244 qm_info
->num_pqs
= num_pqs
;
245 qm_info
->num_vports
= num_vports
;
247 /* Initialize qm port parameters */
248 num_ports
= p_hwfn
->cdev
->num_ports_in_engines
;
249 for (i
= 0; i
< num_ports
; i
++) {
250 p_qm_port
= &qm_info
->qm_port_params
[i
];
251 p_qm_port
->active
= 1;
252 p_qm_port
->num_active_phys_tcs
= 4;
253 p_qm_port
->num_pbf_cmd_lines
= PBF_MAX_CMD_LINES
/ num_ports
;
254 p_qm_port
->num_btb_blocks
= BTB_MAX_BLOCKS
/ num_ports
;
257 qm_info
->max_phys_tcs_per_port
= NUM_OF_PHYS_TCS
;
259 qm_info
->start_pq
= (u16
)RESC_START(p_hwfn
, QED_PQ
);
261 qm_info
->num_vf_pqs
= num_vfs
;
262 qm_info
->start_vport
= (u8
) RESC_START(p_hwfn
, QED_VPORT
);
264 for (i
= 0; i
< qm_info
->num_vports
; i
++)
265 qm_info
->qm_vport_params
[i
].vport_wfq
= 1;
269 qm_info
->vport_rl_en
= 1;
270 qm_info
->vport_wfq_en
= 1;
275 DP_NOTICE(p_hwfn
, "Failed to allocate memory for QM params\n");
276 qed_qm_info_free(p_hwfn
);
280 /* This function reconfigures the QM pf on the fly.
281 * For this purpose we:
282 * 1. reconfigure the QM database
283 * 2. set new values to runtime arrat
284 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
285 * 4. activate init tool in QM_PF stage
286 * 5. send an sdm_qm_cmd through rbc interface to release the QM
288 int qed_qm_reconf(struct qed_hwfn
*p_hwfn
, struct qed_ptt
*p_ptt
)
290 struct qed_qm_info
*qm_info
= &p_hwfn
->qm_info
;
294 /* qm_info is allocated in qed_init_qm_info() which is already called
295 * from qed_resc_alloc() or previous call of qed_qm_reconf().
296 * The allocated size may change each init, so we free it before next
299 qed_qm_info_free(p_hwfn
);
301 /* initialize qed's qm data structure */
302 rc
= qed_init_qm_info(p_hwfn
);
306 /* stop PF's qm queues */
307 spin_lock_bh(&qm_lock
);
308 b_rc
= qed_send_qm_stop_cmd(p_hwfn
, p_ptt
, false, true,
309 qm_info
->start_pq
, qm_info
->num_pqs
);
310 spin_unlock_bh(&qm_lock
);
314 /* clear the QM_PF runtime phase leftovers from previous init */
315 qed_init_clear_rt_data(p_hwfn
);
317 /* prepare QM portion of runtime array */
318 qed_qm_init_pf(p_hwfn
);
320 /* activate init tool on runtime array */
321 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_QM_PF
, p_hwfn
->rel_pf_id
,
322 p_hwfn
->hw_info
.hw_mode
);
326 /* start PF's qm queues */
327 spin_lock_bh(&qm_lock
);
328 b_rc
= qed_send_qm_stop_cmd(p_hwfn
, p_ptt
, true, true,
329 qm_info
->start_pq
, qm_info
->num_pqs
);
330 spin_unlock_bh(&qm_lock
);
337 int qed_resc_alloc(struct qed_dev
*cdev
)
339 struct qed_consq
*p_consq
;
346 cdev
->fw_data
= kzalloc(sizeof(*cdev
->fw_data
), GFP_KERNEL
);
350 /* Allocate Memory for the Queue->CID mapping */
351 for_each_hwfn(cdev
, i
) {
352 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
353 int tx_size
= sizeof(struct qed_hw_cid_data
) *
354 RESC_NUM(p_hwfn
, QED_L2_QUEUE
);
355 int rx_size
= sizeof(struct qed_hw_cid_data
) *
356 RESC_NUM(p_hwfn
, QED_L2_QUEUE
);
358 p_hwfn
->p_tx_cids
= kzalloc(tx_size
, GFP_KERNEL
);
359 if (!p_hwfn
->p_tx_cids
) {
361 "Failed to allocate memory for Tx Cids\n");
366 p_hwfn
->p_rx_cids
= kzalloc(rx_size
, GFP_KERNEL
);
367 if (!p_hwfn
->p_rx_cids
) {
369 "Failed to allocate memory for Rx Cids\n");
375 for_each_hwfn(cdev
, i
) {
376 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
378 /* First allocate the context manager structure */
379 rc
= qed_cxt_mngr_alloc(p_hwfn
);
383 /* Set the HW cid/tid numbers (in the contest manager)
384 * Must be done prior to any further computations.
386 rc
= qed_cxt_set_pf_params(p_hwfn
);
390 /* Prepare and process QM requirements */
391 rc
= qed_init_qm_info(p_hwfn
);
395 /* Compute the ILT client partition */
396 rc
= qed_cxt_cfg_ilt_compute(p_hwfn
);
400 /* CID map / ILT shadow table / T2
401 * The talbes sizes are determined by the computations above
403 rc
= qed_cxt_tables_alloc(p_hwfn
);
407 /* SPQ, must follow ILT because initializes SPQ context */
408 rc
= qed_spq_alloc(p_hwfn
);
412 /* SP status block allocation */
413 p_hwfn
->p_dpc_ptt
= qed_get_reserved_ptt(p_hwfn
,
416 rc
= qed_int_alloc(p_hwfn
, p_hwfn
->p_main_ptt
);
420 rc
= qed_iov_alloc(p_hwfn
);
425 p_eq
= qed_eq_alloc(p_hwfn
, 256);
432 p_consq
= qed_consq_alloc(p_hwfn
);
437 p_hwfn
->p_consq
= p_consq
;
439 /* DMA info initialization */
440 rc
= qed_dmae_info_alloc(p_hwfn
);
443 "Failed to allocate memory for dmae_info structure\n");
447 /* DCBX initialization */
448 rc
= qed_dcbx_info_alloc(p_hwfn
);
451 "Failed to allocate memory for dcbx structure\n");
456 cdev
->reset_stats
= kzalloc(sizeof(*cdev
->reset_stats
), GFP_KERNEL
);
457 if (!cdev
->reset_stats
) {
458 DP_NOTICE(cdev
, "Failed to allocate reset statistics\n");
470 void qed_resc_setup(struct qed_dev
*cdev
)
477 for_each_hwfn(cdev
, i
) {
478 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
480 qed_cxt_mngr_setup(p_hwfn
);
481 qed_spq_setup(p_hwfn
);
482 qed_eq_setup(p_hwfn
, p_hwfn
->p_eq
);
483 qed_consq_setup(p_hwfn
, p_hwfn
->p_consq
);
485 /* Read shadow of current MFW mailbox */
486 qed_mcp_read_mb(p_hwfn
, p_hwfn
->p_main_ptt
);
487 memcpy(p_hwfn
->mcp_info
->mfw_mb_shadow
,
488 p_hwfn
->mcp_info
->mfw_mb_cur
,
489 p_hwfn
->mcp_info
->mfw_mb_length
);
491 qed_int_setup(p_hwfn
, p_hwfn
->p_main_ptt
);
493 qed_iov_setup(p_hwfn
, p_hwfn
->p_main_ptt
);
497 #define FINAL_CLEANUP_POLL_CNT (100)
498 #define FINAL_CLEANUP_POLL_TIME (10)
499 int qed_final_cleanup(struct qed_hwfn
*p_hwfn
,
500 struct qed_ptt
*p_ptt
, u16 id
, bool is_vf
)
502 u32 command
= 0, addr
, count
= FINAL_CLEANUP_POLL_CNT
;
505 addr
= GTT_BAR0_MAP_REG_USDM_RAM
+
506 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn
->rel_pf_id
);
511 command
|= X_FINAL_CLEANUP_AGG_INT
<<
512 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT
;
513 command
|= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT
;
514 command
|= id
<< SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT
;
515 command
|= SDM_COMP_TYPE_AGG_INT
<< SDM_OP_GEN_COMP_TYPE_SHIFT
;
517 /* Make sure notification is not set before initiating final cleanup */
518 if (REG_RD(p_hwfn
, addr
)) {
521 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
522 REG_WR(p_hwfn
, addr
, 0);
525 DP_VERBOSE(p_hwfn
, QED_MSG_IOV
,
526 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
529 qed_wr(p_hwfn
, p_ptt
, XSDM_REG_OPERATION_GEN
, command
);
531 /* Poll until completion */
532 while (!REG_RD(p_hwfn
, addr
) && count
--)
533 msleep(FINAL_CLEANUP_POLL_TIME
);
535 if (REG_RD(p_hwfn
, addr
))
539 "Failed to receive FW final cleanup notification\n");
541 /* Cleanup afterwards */
542 REG_WR(p_hwfn
, addr
, 0);
547 static void qed_calc_hw_mode(struct qed_hwfn
*p_hwfn
)
551 hw_mode
= (1 << MODE_BB_B0
);
553 switch (p_hwfn
->cdev
->num_ports_in_engines
) {
555 hw_mode
|= 1 << MODE_PORTS_PER_ENG_1
;
558 hw_mode
|= 1 << MODE_PORTS_PER_ENG_2
;
561 hw_mode
|= 1 << MODE_PORTS_PER_ENG_4
;
564 DP_NOTICE(p_hwfn
, "num_ports_in_engine = %d not supported\n",
565 p_hwfn
->cdev
->num_ports_in_engines
);
569 switch (p_hwfn
->cdev
->mf_mode
) {
572 hw_mode
|= 1 << MODE_MF_SI
;
575 hw_mode
|= 1 << MODE_MF_SD
;
578 DP_NOTICE(p_hwfn
, "Unsupported MF mode, init as DEFAULT\n");
579 hw_mode
|= 1 << MODE_MF_SI
;
582 hw_mode
|= 1 << MODE_ASIC
;
584 p_hwfn
->hw_info
.hw_mode
= hw_mode
;
587 /* Init run time data for all PFs on an engine. */
588 static void qed_init_cau_rt_data(struct qed_dev
*cdev
)
590 u32 offset
= CAU_REG_SB_VAR_MEMORY_RT_OFFSET
;
593 for_each_hwfn(cdev
, i
) {
594 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
595 struct qed_igu_info
*p_igu_info
;
596 struct qed_igu_block
*p_block
;
597 struct cau_sb_entry sb_entry
;
599 p_igu_info
= p_hwfn
->hw_info
.p_igu_info
;
601 for (sb_id
= 0; sb_id
< QED_MAPPING_MEMORY_SIZE(cdev
);
603 p_block
= &p_igu_info
->igu_map
.igu_blocks
[sb_id
];
607 qed_init_cau_sb_entry(p_hwfn
, &sb_entry
,
608 p_block
->function_id
,
610 STORE_RT_REG_AGG(p_hwfn
, offset
+ sb_id
* 2,
616 static int qed_hw_init_common(struct qed_hwfn
*p_hwfn
,
617 struct qed_ptt
*p_ptt
,
620 struct qed_qm_info
*qm_info
= &p_hwfn
->qm_info
;
621 struct qed_qm_common_rt_init_params params
;
622 struct qed_dev
*cdev
= p_hwfn
->cdev
;
627 qed_init_cau_rt_data(cdev
);
629 /* Program GTT windows */
630 qed_gtt_init(p_hwfn
);
632 if (p_hwfn
->mcp_info
) {
633 if (p_hwfn
->mcp_info
->func_info
.bandwidth_max
)
634 qm_info
->pf_rl_en
= 1;
635 if (p_hwfn
->mcp_info
->func_info
.bandwidth_min
)
636 qm_info
->pf_wfq_en
= 1;
639 memset(¶ms
, 0, sizeof(params
));
640 params
.max_ports_per_engine
= p_hwfn
->cdev
->num_ports_in_engines
;
641 params
.max_phys_tcs_per_port
= qm_info
->max_phys_tcs_per_port
;
642 params
.pf_rl_en
= qm_info
->pf_rl_en
;
643 params
.pf_wfq_en
= qm_info
->pf_wfq_en
;
644 params
.vport_rl_en
= qm_info
->vport_rl_en
;
645 params
.vport_wfq_en
= qm_info
->vport_wfq_en
;
646 params
.port_params
= qm_info
->qm_port_params
;
648 qed_qm_common_rt_init(p_hwfn
, ¶ms
);
650 qed_cxt_hw_init_common(p_hwfn
);
652 /* Close gate from NIG to BRB/Storm; By default they are open, but
653 * we close them to prevent NIG from passing data to reset blocks.
654 * Should have been done in the ENGINE phase, but init-tool lacks
655 * proper port-pretend capabilities.
657 qed_wr(p_hwfn
, p_ptt
, NIG_REG_RX_BRB_OUT_EN
, 0);
658 qed_wr(p_hwfn
, p_ptt
, NIG_REG_STORM_OUT_EN
, 0);
659 qed_port_pretend(p_hwfn
, p_ptt
, p_hwfn
->port_id
^ 1);
660 qed_wr(p_hwfn
, p_ptt
, NIG_REG_RX_BRB_OUT_EN
, 0);
661 qed_wr(p_hwfn
, p_ptt
, NIG_REG_STORM_OUT_EN
, 0);
662 qed_port_unpretend(p_hwfn
, p_ptt
);
664 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_ENGINE
, ANY_PHASE_ID
, hw_mode
);
668 qed_wr(p_hwfn
, p_ptt
, PSWRQ2_REG_L2P_VALIDATE_VFID
, 0);
669 qed_wr(p_hwfn
, p_ptt
, PGLUE_B_REG_USE_CLIENTID_IN_TAG
, 1);
671 /* Disable relaxed ordering in the PCI config space */
672 qed_wr(p_hwfn
, p_ptt
, 0x20b4,
673 qed_rd(p_hwfn
, p_ptt
, 0x20b4) & ~0x10);
675 for (vf_id
= 0; vf_id
< MAX_NUM_VFS_BB
; vf_id
++) {
676 concrete_fid
= qed_vfid_to_concrete(p_hwfn
, vf_id
);
677 qed_fid_pretend(p_hwfn
, p_ptt
, (u16
) concrete_fid
);
678 qed_wr(p_hwfn
, p_ptt
, CCFC_REG_STRONG_ENABLE_VF
, 0x1);
680 /* pretend to original PF */
681 qed_fid_pretend(p_hwfn
, p_ptt
, p_hwfn
->rel_pf_id
);
686 static int qed_hw_init_port(struct qed_hwfn
*p_hwfn
,
687 struct qed_ptt
*p_ptt
,
692 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_PORT
, p_hwfn
->port_id
,
697 static int qed_hw_init_pf(struct qed_hwfn
*p_hwfn
,
698 struct qed_ptt
*p_ptt
,
699 struct qed_tunn_start_params
*p_tunn
,
702 enum qed_int_mode int_mode
,
703 bool allow_npar_tx_switch
)
705 u8 rel_pf_id
= p_hwfn
->rel_pf_id
;
708 if (p_hwfn
->mcp_info
) {
709 struct qed_mcp_function_info
*p_info
;
711 p_info
= &p_hwfn
->mcp_info
->func_info
;
712 if (p_info
->bandwidth_min
)
713 p_hwfn
->qm_info
.pf_wfq
= p_info
->bandwidth_min
;
715 /* Update rate limit once we'll actually have a link */
716 p_hwfn
->qm_info
.pf_rl
= 100000;
719 qed_cxt_hw_init_pf(p_hwfn
);
721 qed_int_igu_init_rt(p_hwfn
);
723 /* Set VLAN in NIG if needed */
724 if (hw_mode
& (1 << MODE_MF_SD
)) {
725 DP_VERBOSE(p_hwfn
, NETIF_MSG_HW
, "Configuring LLH_FUNC_TAG\n");
726 STORE_RT_REG(p_hwfn
, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET
, 1);
727 STORE_RT_REG(p_hwfn
, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET
,
728 p_hwfn
->hw_info
.ovlan
);
731 /* Enable classification by MAC if needed */
732 if (hw_mode
& (1 << MODE_MF_SI
)) {
733 DP_VERBOSE(p_hwfn
, NETIF_MSG_HW
,
734 "Configuring TAGMAC_CLS_TYPE\n");
736 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET
, 1);
739 /* Protocl Configuration */
740 STORE_RT_REG(p_hwfn
, PRS_REG_SEARCH_TCP_RT_OFFSET
, 0);
741 STORE_RT_REG(p_hwfn
, PRS_REG_SEARCH_FCOE_RT_OFFSET
, 0);
742 STORE_RT_REG(p_hwfn
, PRS_REG_SEARCH_ROCE_RT_OFFSET
, 0);
744 /* Cleanup chip from previous driver if such remains exist */
745 rc
= qed_final_cleanup(p_hwfn
, p_ptt
, rel_pf_id
, false);
749 /* PF Init sequence */
750 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_PF
, rel_pf_id
, hw_mode
);
754 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
755 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_QM_PF
, rel_pf_id
, hw_mode
);
759 /* Pure runtime initializations - directly to the HW */
760 qed_int_igu_init_pure_rt(p_hwfn
, p_ptt
, true, true);
763 /* enable interrupts */
764 qed_int_igu_enable(p_hwfn
, p_ptt
, int_mode
);
766 /* send function start command */
767 rc
= qed_sp_pf_start(p_hwfn
, p_tunn
, p_hwfn
->cdev
->mf_mode
,
768 allow_npar_tx_switch
);
770 DP_NOTICE(p_hwfn
, "Function start ramrod failed\n");
775 static int qed_change_pci_hwfn(struct qed_hwfn
*p_hwfn
,
776 struct qed_ptt
*p_ptt
,
779 u32 delay_idx
= 0, val
, set_val
= enable
? 1 : 0;
781 /* Change PF in PXP */
782 qed_wr(p_hwfn
, p_ptt
,
783 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, set_val
);
785 /* wait until value is set - try for 1 second every 50us */
786 for (delay_idx
= 0; delay_idx
< 20000; delay_idx
++) {
787 val
= qed_rd(p_hwfn
, p_ptt
,
788 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
);
792 usleep_range(50, 60);
795 if (val
!= set_val
) {
797 "PFID_ENABLE_MASTER wasn't changed after a second\n");
804 static void qed_reset_mb_shadow(struct qed_hwfn
*p_hwfn
,
805 struct qed_ptt
*p_main_ptt
)
807 /* Read shadow of current MFW mailbox */
808 qed_mcp_read_mb(p_hwfn
, p_main_ptt
);
809 memcpy(p_hwfn
->mcp_info
->mfw_mb_shadow
,
810 p_hwfn
->mcp_info
->mfw_mb_cur
,
811 p_hwfn
->mcp_info
->mfw_mb_length
);
814 int qed_hw_init(struct qed_dev
*cdev
,
815 struct qed_tunn_start_params
*p_tunn
,
817 enum qed_int_mode int_mode
,
818 bool allow_npar_tx_switch
,
819 const u8
*bin_fw_data
)
821 u32 load_code
, param
;
825 rc
= qed_init_fw_data(cdev
, bin_fw_data
);
830 for_each_hwfn(cdev
, i
) {
831 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
834 p_hwfn
->b_int_enabled
= 1;
838 /* Enable DMAE in PXP */
839 rc
= qed_change_pci_hwfn(p_hwfn
, p_hwfn
->p_main_ptt
, true);
841 qed_calc_hw_mode(p_hwfn
);
843 rc
= qed_mcp_load_req(p_hwfn
, p_hwfn
->p_main_ptt
,
846 DP_NOTICE(p_hwfn
, "Failed sending LOAD_REQ command\n");
850 qed_reset_mb_shadow(p_hwfn
, p_hwfn
->p_main_ptt
);
852 DP_VERBOSE(p_hwfn
, QED_MSG_SP
,
853 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
856 p_hwfn
->first_on_engine
= (load_code
==
857 FW_MSG_CODE_DRV_LOAD_ENGINE
);
860 spin_lock_init(&qm_lock
);
865 case FW_MSG_CODE_DRV_LOAD_ENGINE
:
866 rc
= qed_hw_init_common(p_hwfn
, p_hwfn
->p_main_ptt
,
867 p_hwfn
->hw_info
.hw_mode
);
871 case FW_MSG_CODE_DRV_LOAD_PORT
:
872 rc
= qed_hw_init_port(p_hwfn
, p_hwfn
->p_main_ptt
,
873 p_hwfn
->hw_info
.hw_mode
);
878 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
879 rc
= qed_hw_init_pf(p_hwfn
, p_hwfn
->p_main_ptt
,
880 p_tunn
, p_hwfn
->hw_info
.hw_mode
,
881 b_hw_start
, int_mode
,
882 allow_npar_tx_switch
);
891 "init phase failed for loadcode 0x%x (rc %d)\n",
894 /* ACK mfw regardless of success or failure of initialization */
895 mfw_rc
= qed_mcp_cmd(p_hwfn
, p_hwfn
->p_main_ptt
,
896 DRV_MSG_CODE_LOAD_DONE
,
897 0, &load_code
, ¶m
);
901 DP_NOTICE(p_hwfn
, "Failed sending LOAD_DONE command\n");
905 /* send DCBX attention request command */
908 "sending phony dcbx set command to trigger DCBx attention handling\n");
909 mfw_rc
= qed_mcp_cmd(p_hwfn
, p_hwfn
->p_main_ptt
,
910 DRV_MSG_CODE_SET_DCBX
,
911 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT
,
915 "Failed to send DCBX attention request\n");
919 p_hwfn
->hw_init_done
= true;
925 #define QED_HW_STOP_RETRY_LIMIT (10)
926 static inline void qed_hw_timers_stop(struct qed_dev
*cdev
,
927 struct qed_hwfn
*p_hwfn
,
928 struct qed_ptt
*p_ptt
)
933 qed_wr(p_hwfn
, p_ptt
, TM_REG_PF_ENABLE_CONN
, 0x0);
934 qed_wr(p_hwfn
, p_ptt
, TM_REG_PF_ENABLE_TASK
, 0x0);
936 for (i
= 0; i
< QED_HW_STOP_RETRY_LIMIT
; i
++) {
937 if ((!qed_rd(p_hwfn
, p_ptt
,
938 TM_REG_PF_SCAN_ACTIVE_CONN
)) &&
939 (!qed_rd(p_hwfn
, p_ptt
,
940 TM_REG_PF_SCAN_ACTIVE_TASK
)))
943 /* Dependent on number of connection/tasks, possibly
944 * 1ms sleep is required between polls
946 usleep_range(1000, 2000);
949 if (i
< QED_HW_STOP_RETRY_LIMIT
)
953 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
954 (u8
)qed_rd(p_hwfn
, p_ptt
, TM_REG_PF_SCAN_ACTIVE_CONN
),
955 (u8
)qed_rd(p_hwfn
, p_ptt
, TM_REG_PF_SCAN_ACTIVE_TASK
));
958 void qed_hw_timers_stop_all(struct qed_dev
*cdev
)
962 for_each_hwfn(cdev
, j
) {
963 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[j
];
964 struct qed_ptt
*p_ptt
= p_hwfn
->p_main_ptt
;
966 qed_hw_timers_stop(cdev
, p_hwfn
, p_ptt
);
970 int qed_hw_stop(struct qed_dev
*cdev
)
975 for_each_hwfn(cdev
, j
) {
976 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[j
];
977 struct qed_ptt
*p_ptt
= p_hwfn
->p_main_ptt
;
979 DP_VERBOSE(p_hwfn
, NETIF_MSG_IFDOWN
, "Stopping hw/fw\n");
982 qed_vf_pf_int_cleanup(p_hwfn
);
986 /* mark the hw as uninitialized... */
987 p_hwfn
->hw_init_done
= false;
989 rc
= qed_sp_pf_stop(p_hwfn
);
992 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
994 qed_wr(p_hwfn
, p_ptt
,
995 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF
, 0x1);
997 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_TCP
, 0x0);
998 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_UDP
, 0x0);
999 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_FCOE
, 0x0);
1000 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_ROCE
, 0x0);
1001 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_OPENFLOW
, 0x0);
1003 qed_hw_timers_stop(cdev
, p_hwfn
, p_ptt
);
1005 /* Disable Attention Generation */
1006 qed_int_igu_disable_int(p_hwfn
, p_ptt
);
1008 qed_wr(p_hwfn
, p_ptt
, IGU_REG_LEADING_EDGE_LATCH
, 0);
1009 qed_wr(p_hwfn
, p_ptt
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
1011 qed_int_igu_init_pure_rt(p_hwfn
, p_ptt
, false, true);
1013 /* Need to wait 1ms to guarantee SBs are cleared */
1014 usleep_range(1000, 2000);
1018 /* Disable DMAE in PXP - in CMT, this should only be done for
1019 * first hw-function, and only after all transactions have
1020 * stopped for all active hw-functions.
1022 t_rc
= qed_change_pci_hwfn(&cdev
->hwfns
[0],
1023 cdev
->hwfns
[0].p_main_ptt
, false);
1031 void qed_hw_stop_fastpath(struct qed_dev
*cdev
)
1035 for_each_hwfn(cdev
, j
) {
1036 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[j
];
1037 struct qed_ptt
*p_ptt
= p_hwfn
->p_main_ptt
;
1040 qed_vf_pf_int_cleanup(p_hwfn
);
1046 "Shutting down the fastpath\n");
1048 qed_wr(p_hwfn
, p_ptt
,
1049 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF
, 0x1);
1051 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_TCP
, 0x0);
1052 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_UDP
, 0x0);
1053 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_FCOE
, 0x0);
1054 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_ROCE
, 0x0);
1055 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_OPENFLOW
, 0x0);
1057 qed_int_igu_init_pure_rt(p_hwfn
, p_ptt
, false, false);
1059 /* Need to wait 1ms to guarantee SBs are cleared */
1060 usleep_range(1000, 2000);
1064 void qed_hw_start_fastpath(struct qed_hwfn
*p_hwfn
)
1066 if (IS_VF(p_hwfn
->cdev
))
1069 /* Re-open incoming traffic */
1070 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
1071 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF
, 0x0);
1074 static int qed_reg_assert(struct qed_hwfn
*hwfn
,
1075 struct qed_ptt
*ptt
, u32 reg
,
1078 u32 assert_val
= qed_rd(hwfn
, ptt
, reg
);
1080 if (assert_val
!= expected
) {
1081 DP_NOTICE(hwfn
, "Value at address 0x%x != 0x%08x\n",
1089 int qed_hw_reset(struct qed_dev
*cdev
)
1092 u32 unload_resp
, unload_param
;
1095 for_each_hwfn(cdev
, i
) {
1096 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
1099 rc
= qed_vf_pf_reset(p_hwfn
);
1105 DP_VERBOSE(p_hwfn
, NETIF_MSG_IFDOWN
, "Resetting hw/fw\n");
1107 /* Check for incorrect states */
1108 qed_reg_assert(p_hwfn
, p_hwfn
->p_main_ptt
,
1109 QM_REG_USG_CNT_PF_TX
, 0);
1110 qed_reg_assert(p_hwfn
, p_hwfn
->p_main_ptt
,
1111 QM_REG_USG_CNT_PF_OTHER
, 0);
1113 /* Disable PF in HW blocks */
1114 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, DORQ_REG_PF_DB_ENABLE
, 0);
1115 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, QM_REG_PF_EN
, 0);
1116 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
1117 TCFC_REG_STRONG_ENABLE_PF
, 0);
1118 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
1119 CCFC_REG_STRONG_ENABLE_PF
, 0);
1121 /* Send unload command to MCP */
1122 rc
= qed_mcp_cmd(p_hwfn
, p_hwfn
->p_main_ptt
,
1123 DRV_MSG_CODE_UNLOAD_REQ
,
1124 DRV_MB_PARAM_UNLOAD_WOL_MCP
,
1125 &unload_resp
, &unload_param
);
1127 DP_NOTICE(p_hwfn
, "qed_hw_reset: UNLOAD_REQ failed\n");
1128 unload_resp
= FW_MSG_CODE_DRV_UNLOAD_ENGINE
;
1131 rc
= qed_mcp_cmd(p_hwfn
, p_hwfn
->p_main_ptt
,
1132 DRV_MSG_CODE_UNLOAD_DONE
,
1133 0, &unload_resp
, &unload_param
);
1135 DP_NOTICE(p_hwfn
, "qed_hw_reset: UNLOAD_DONE failed\n");
1143 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1144 static void qed_hw_hwfn_free(struct qed_hwfn
*p_hwfn
)
1146 qed_ptt_pool_free(p_hwfn
);
1147 kfree(p_hwfn
->hw_info
.p_igu_info
);
1150 /* Setup bar access */
1151 static void qed_hw_hwfn_prepare(struct qed_hwfn
*p_hwfn
)
1153 /* clear indirect access */
1154 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, PGLUE_B_REG_PGL_ADDR_88_F0
, 0);
1155 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, PGLUE_B_REG_PGL_ADDR_8C_F0
, 0);
1156 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, PGLUE_B_REG_PGL_ADDR_90_F0
, 0);
1157 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, PGLUE_B_REG_PGL_ADDR_94_F0
, 0);
1159 /* Clean Previous errors if such exist */
1160 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
1161 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR
,
1162 1 << p_hwfn
->abs_pf_id
);
1164 /* enable internal target-read */
1165 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
1166 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
1169 static void get_function_id(struct qed_hwfn
*p_hwfn
)
1172 p_hwfn
->hw_info
.opaque_fid
= (u16
)REG_RD(p_hwfn
, PXP_PF_ME_OPAQUE_ADDR
);
1174 p_hwfn
->hw_info
.concrete_fid
= REG_RD(p_hwfn
, PXP_PF_ME_CONCRETE_ADDR
);
1176 p_hwfn
->abs_pf_id
= (p_hwfn
->hw_info
.concrete_fid
>> 16) & 0xf;
1177 p_hwfn
->rel_pf_id
= GET_FIELD(p_hwfn
->hw_info
.concrete_fid
,
1178 PXP_CONCRETE_FID_PFID
);
1179 p_hwfn
->port_id
= GET_FIELD(p_hwfn
->hw_info
.concrete_fid
,
1180 PXP_CONCRETE_FID_PORT
);
1183 static void qed_hw_set_feat(struct qed_hwfn
*p_hwfn
)
1185 u32
*feat_num
= p_hwfn
->hw_info
.feat_num
;
1186 int num_features
= 1;
1188 feat_num
[QED_PF_L2_QUE
] = min_t(u32
, RESC_NUM(p_hwfn
, QED_SB
) /
1190 RESC_NUM(p_hwfn
, QED_L2_QUEUE
));
1191 DP_VERBOSE(p_hwfn
, NETIF_MSG_PROBE
,
1192 "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1193 feat_num
[QED_PF_L2_QUE
], RESC_NUM(p_hwfn
, QED_SB
),
1197 static void qed_hw_get_resc(struct qed_hwfn
*p_hwfn
)
1199 u32
*resc_start
= p_hwfn
->hw_info
.resc_start
;
1200 u8 num_funcs
= p_hwfn
->num_funcs_on_engine
;
1201 u32
*resc_num
= p_hwfn
->hw_info
.resc_num
;
1202 struct qed_sb_cnt_info sb_cnt_info
;
1203 int i
, max_vf_vlan_filters
;
1205 memset(&sb_cnt_info
, 0, sizeof(sb_cnt_info
));
1207 #ifdef CONFIG_QED_SRIOV
1208 max_vf_vlan_filters
= QED_ETH_MAX_VF_NUM_VLAN_FILTERS
;
1210 max_vf_vlan_filters
= 0;
1213 qed_int_get_num_sbs(p_hwfn
, &sb_cnt_info
);
1215 resc_num
[QED_SB
] = min_t(u32
,
1216 (MAX_SB_PER_PATH_BB
/ num_funcs
),
1217 sb_cnt_info
.sb_cnt
);
1218 resc_num
[QED_L2_QUEUE
] = MAX_NUM_L2_QUEUES_BB
/ num_funcs
;
1219 resc_num
[QED_VPORT
] = MAX_NUM_VPORTS_BB
/ num_funcs
;
1220 resc_num
[QED_RSS_ENG
] = ETH_RSS_ENGINE_NUM_BB
/ num_funcs
;
1221 resc_num
[QED_PQ
] = MAX_QM_TX_QUEUES_BB
/ num_funcs
;
1222 resc_num
[QED_RL
] = 8;
1223 resc_num
[QED_MAC
] = ETH_NUM_MAC_FILTERS
/ num_funcs
;
1224 resc_num
[QED_VLAN
] = (ETH_NUM_VLAN_FILTERS
- 1 /*For vlan0*/) /
1226 resc_num
[QED_ILT
] = 950;
1228 for (i
= 0; i
< QED_MAX_RESC
; i
++)
1229 resc_start
[i
] = resc_num
[i
] * p_hwfn
->rel_pf_id
;
1231 qed_hw_set_feat(p_hwfn
);
1233 DP_VERBOSE(p_hwfn
, NETIF_MSG_PROBE
,
1234 "The numbers for each resource are:\n"
1235 "SB = %d start = %d\n"
1236 "L2_QUEUE = %d start = %d\n"
1237 "VPORT = %d start = %d\n"
1238 "PQ = %d start = %d\n"
1239 "RL = %d start = %d\n"
1240 "MAC = %d start = %d\n"
1241 "VLAN = %d start = %d\n"
1242 "ILT = %d start = %d\n",
1243 p_hwfn
->hw_info
.resc_num
[QED_SB
],
1244 p_hwfn
->hw_info
.resc_start
[QED_SB
],
1245 p_hwfn
->hw_info
.resc_num
[QED_L2_QUEUE
],
1246 p_hwfn
->hw_info
.resc_start
[QED_L2_QUEUE
],
1247 p_hwfn
->hw_info
.resc_num
[QED_VPORT
],
1248 p_hwfn
->hw_info
.resc_start
[QED_VPORT
],
1249 p_hwfn
->hw_info
.resc_num
[QED_PQ
],
1250 p_hwfn
->hw_info
.resc_start
[QED_PQ
],
1251 p_hwfn
->hw_info
.resc_num
[QED_RL
],
1252 p_hwfn
->hw_info
.resc_start
[QED_RL
],
1253 p_hwfn
->hw_info
.resc_num
[QED_MAC
],
1254 p_hwfn
->hw_info
.resc_start
[QED_MAC
],
1255 p_hwfn
->hw_info
.resc_num
[QED_VLAN
],
1256 p_hwfn
->hw_info
.resc_start
[QED_VLAN
],
1257 p_hwfn
->hw_info
.resc_num
[QED_ILT
],
1258 p_hwfn
->hw_info
.resc_start
[QED_ILT
]);
1261 static int qed_hw_get_nvm_info(struct qed_hwfn
*p_hwfn
,
1262 struct qed_ptt
*p_ptt
)
1264 u32 nvm_cfg1_offset
, mf_mode
, addr
, generic_cont0
, core_cfg
;
1265 u32 port_cfg_addr
, link_temp
, nvm_cfg_addr
, device_capabilities
;
1266 struct qed_mcp_link_params
*link
;
1268 /* Read global nvm_cfg address */
1269 nvm_cfg_addr
= qed_rd(p_hwfn
, p_ptt
, MISC_REG_GEN_PURP_CR0
);
1271 /* Verify MCP has initialized it */
1272 if (!nvm_cfg_addr
) {
1273 DP_NOTICE(p_hwfn
, "Shared memory not initialized\n");
1277 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
1278 nvm_cfg1_offset
= qed_rd(p_hwfn
, p_ptt
, nvm_cfg_addr
+ 4);
1280 addr
= MCP_REG_SCRATCH
+ nvm_cfg1_offset
+
1281 offsetof(struct nvm_cfg1
, glob
) +
1282 offsetof(struct nvm_cfg1_glob
, core_cfg
);
1284 core_cfg
= qed_rd(p_hwfn
, p_ptt
, addr
);
1286 switch ((core_cfg
& NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK
) >>
1287 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET
) {
1288 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G
:
1289 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_2X40G
;
1291 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G
:
1292 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_2X50G
;
1294 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G
:
1295 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_1X100G
;
1297 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F
:
1298 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_4X10G_F
;
1300 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E
:
1301 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_4X10G_E
;
1303 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G
:
1304 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_4X20G
;
1306 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G
:
1307 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_1X40G
;
1309 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G
:
1310 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_2X25G
;
1312 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G
:
1313 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_1X25G
;
1316 DP_NOTICE(p_hwfn
, "Unknown port mode in 0x%08x\n",
1321 /* Read default link configuration */
1322 link
= &p_hwfn
->mcp_info
->link_input
;
1323 port_cfg_addr
= MCP_REG_SCRATCH
+ nvm_cfg1_offset
+
1324 offsetof(struct nvm_cfg1
, port
[MFW_PORT(p_hwfn
)]);
1325 link_temp
= qed_rd(p_hwfn
, p_ptt
,
1327 offsetof(struct nvm_cfg1_port
, speed_cap_mask
));
1328 link
->speed
.advertised_speeds
=
1329 link_temp
& NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK
;
1331 p_hwfn
->mcp_info
->link_capabilities
.speed_capabilities
=
1332 link
->speed
.advertised_speeds
;
1334 link_temp
= qed_rd(p_hwfn
, p_ptt
,
1336 offsetof(struct nvm_cfg1_port
, link_settings
));
1337 switch ((link_temp
& NVM_CFG1_PORT_DRV_LINK_SPEED_MASK
) >>
1338 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET
) {
1339 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG
:
1340 link
->speed
.autoneg
= true;
1342 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G
:
1343 link
->speed
.forced_speed
= 1000;
1345 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G
:
1346 link
->speed
.forced_speed
= 10000;
1348 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G
:
1349 link
->speed
.forced_speed
= 25000;
1351 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G
:
1352 link
->speed
.forced_speed
= 40000;
1354 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G
:
1355 link
->speed
.forced_speed
= 50000;
1357 case NVM_CFG1_PORT_DRV_LINK_SPEED_100G
:
1358 link
->speed
.forced_speed
= 100000;
1361 DP_NOTICE(p_hwfn
, "Unknown Speed in 0x%08x\n",
1365 link_temp
&= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK
;
1366 link_temp
>>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET
;
1367 link
->pause
.autoneg
= !!(link_temp
&
1368 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG
);
1369 link
->pause
.forced_rx
= !!(link_temp
&
1370 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX
);
1371 link
->pause
.forced_tx
= !!(link_temp
&
1372 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX
);
1373 link
->loopback_mode
= 0;
1375 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
1376 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1377 link
->speed
.forced_speed
, link
->speed
.advertised_speeds
,
1378 link
->speed
.autoneg
, link
->pause
.autoneg
);
1380 /* Read Multi-function information from shmem */
1381 addr
= MCP_REG_SCRATCH
+ nvm_cfg1_offset
+
1382 offsetof(struct nvm_cfg1
, glob
) +
1383 offsetof(struct nvm_cfg1_glob
, generic_cont0
);
1385 generic_cont0
= qed_rd(p_hwfn
, p_ptt
, addr
);
1387 mf_mode
= (generic_cont0
& NVM_CFG1_GLOB_MF_MODE_MASK
) >>
1388 NVM_CFG1_GLOB_MF_MODE_OFFSET
;
1391 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED
:
1392 p_hwfn
->cdev
->mf_mode
= QED_MF_OVLAN
;
1394 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0
:
1395 p_hwfn
->cdev
->mf_mode
= QED_MF_NPAR
;
1397 case NVM_CFG1_GLOB_MF_MODE_DEFAULT
:
1398 p_hwfn
->cdev
->mf_mode
= QED_MF_DEFAULT
;
1401 DP_INFO(p_hwfn
, "Multi function mode is %08x\n",
1402 p_hwfn
->cdev
->mf_mode
);
1404 /* Read Multi-function information from shmem */
1405 addr
= MCP_REG_SCRATCH
+ nvm_cfg1_offset
+
1406 offsetof(struct nvm_cfg1
, glob
) +
1407 offsetof(struct nvm_cfg1_glob
, device_capabilities
);
1409 device_capabilities
= qed_rd(p_hwfn
, p_ptt
, addr
);
1410 if (device_capabilities
& NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET
)
1411 __set_bit(QED_DEV_CAP_ETH
,
1412 &p_hwfn
->hw_info
.device_capabilities
);
1414 return qed_mcp_fill_shmem_func_info(p_hwfn
, p_ptt
);
1417 static void qed_get_num_funcs(struct qed_hwfn
*p_hwfn
, struct qed_ptt
*p_ptt
)
1419 u32 reg_function_hide
, tmp
, eng_mask
;
1422 num_funcs
= MAX_NUM_PFS_BB
;
1424 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1425 * in the other bits are selected.
1426 * Bits 1-15 are for functions 1-15, respectively, and their value is
1427 * '0' only for enabled functions (function 0 always exists and
1429 * In case of CMT, only the "even" functions are enabled, and thus the
1430 * number of functions for both hwfns is learnt from the same bits.
1432 reg_function_hide
= qed_rd(p_hwfn
, p_ptt
, MISCS_REG_FUNCTION_HIDE
);
1434 if (reg_function_hide
& 0x1) {
1435 if (QED_PATH_ID(p_hwfn
) && p_hwfn
->cdev
->num_hwfns
== 1) {
1443 /* Get the number of the enabled functions on the engine */
1444 tmp
= (reg_function_hide
^ 0xffffffff) & eng_mask
;
1452 p_hwfn
->num_funcs_on_engine
= num_funcs
;
1456 "PF [rel_id %d, abs_id %d] within the %d enabled functions on the engine\n",
1459 p_hwfn
->num_funcs_on_engine
);
1463 qed_get_hw_info(struct qed_hwfn
*p_hwfn
,
1464 struct qed_ptt
*p_ptt
,
1465 enum qed_pci_personality personality
)
1470 /* Since all information is common, only first hwfns should do this */
1471 if (IS_LEAD_HWFN(p_hwfn
)) {
1472 rc
= qed_iov_hw_info(p_hwfn
);
1477 /* Read the port mode */
1478 port_mode
= qed_rd(p_hwfn
, p_ptt
,
1479 CNIG_REG_NW_PORT_MODE_BB_B0
);
1481 if (port_mode
< 3) {
1482 p_hwfn
->cdev
->num_ports_in_engines
= 1;
1483 } else if (port_mode
<= 5) {
1484 p_hwfn
->cdev
->num_ports_in_engines
= 2;
1486 DP_NOTICE(p_hwfn
, "PORT MODE: %d not supported\n",
1487 p_hwfn
->cdev
->num_ports_in_engines
);
1489 /* Default num_ports_in_engines to something */
1490 p_hwfn
->cdev
->num_ports_in_engines
= 1;
1493 qed_hw_get_nvm_info(p_hwfn
, p_ptt
);
1495 rc
= qed_int_igu_read_cam(p_hwfn
, p_ptt
);
1499 if (qed_mcp_is_init(p_hwfn
))
1500 ether_addr_copy(p_hwfn
->hw_info
.hw_mac_addr
,
1501 p_hwfn
->mcp_info
->func_info
.mac
);
1503 eth_random_addr(p_hwfn
->hw_info
.hw_mac_addr
);
1505 if (qed_mcp_is_init(p_hwfn
)) {
1506 if (p_hwfn
->mcp_info
->func_info
.ovlan
!= QED_MCP_VLAN_UNSET
)
1507 p_hwfn
->hw_info
.ovlan
=
1508 p_hwfn
->mcp_info
->func_info
.ovlan
;
1510 qed_mcp_cmd_port_init(p_hwfn
, p_ptt
);
1513 if (qed_mcp_is_init(p_hwfn
)) {
1514 enum qed_pci_personality protocol
;
1516 protocol
= p_hwfn
->mcp_info
->func_info
.protocol
;
1517 p_hwfn
->hw_info
.personality
= protocol
;
1520 qed_get_num_funcs(p_hwfn
, p_ptt
);
1522 qed_hw_get_resc(p_hwfn
);
1527 static int qed_get_dev_info(struct qed_dev
*cdev
)
1529 struct qed_hwfn
*p_hwfn
= QED_LEADING_HWFN(cdev
);
1532 /* Read Vendor Id / Device Id */
1533 pci_read_config_word(cdev
->pdev
, PCI_VENDOR_ID
,
1535 pci_read_config_word(cdev
->pdev
, PCI_DEVICE_ID
,
1537 cdev
->chip_num
= (u16
)qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1538 MISCS_REG_CHIP_NUM
);
1539 cdev
->chip_rev
= (u16
)qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1540 MISCS_REG_CHIP_REV
);
1541 MASK_FIELD(CHIP_REV
, cdev
->chip_rev
);
1543 cdev
->type
= QED_DEV_TYPE_BB
;
1544 /* Learn number of HW-functions */
1545 tmp
= qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1546 MISCS_REG_CMT_ENABLED_FOR_PAIR
);
1548 if (tmp
& (1 << p_hwfn
->rel_pf_id
)) {
1549 DP_NOTICE(cdev
->hwfns
, "device in CMT mode\n");
1550 cdev
->num_hwfns
= 2;
1552 cdev
->num_hwfns
= 1;
1555 cdev
->chip_bond_id
= qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1556 MISCS_REG_CHIP_TEST_REG
) >> 4;
1557 MASK_FIELD(CHIP_BOND_ID
, cdev
->chip_bond_id
);
1558 cdev
->chip_metal
= (u16
)qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1559 MISCS_REG_CHIP_METAL
);
1560 MASK_FIELD(CHIP_METAL
, cdev
->chip_metal
);
1562 DP_INFO(cdev
->hwfns
,
1563 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
1564 cdev
->chip_num
, cdev
->chip_rev
,
1565 cdev
->chip_bond_id
, cdev
->chip_metal
);
1567 if (QED_IS_BB(cdev
) && CHIP_REV_IS_A0(cdev
)) {
1568 DP_NOTICE(cdev
->hwfns
,
1569 "The chip type/rev (BB A0) is not supported!\n");
1576 static int qed_hw_prepare_single(struct qed_hwfn
*p_hwfn
,
1577 void __iomem
*p_regview
,
1578 void __iomem
*p_doorbells
,
1579 enum qed_pci_personality personality
)
1583 /* Split PCI bars evenly between hwfns */
1584 p_hwfn
->regview
= p_regview
;
1585 p_hwfn
->doorbells
= p_doorbells
;
1587 if (IS_VF(p_hwfn
->cdev
))
1588 return qed_vf_hw_prepare(p_hwfn
);
1590 /* Validate that chip access is feasible */
1591 if (REG_RD(p_hwfn
, PXP_PF_ME_OPAQUE_ADDR
) == 0xffffffff) {
1593 "Reading the ME register returns all Fs; Preventing further chip access\n");
1597 get_function_id(p_hwfn
);
1599 /* Allocate PTT pool */
1600 rc
= qed_ptt_pool_alloc(p_hwfn
);
1602 DP_NOTICE(p_hwfn
, "Failed to prepare hwfn's hw\n");
1606 /* Allocate the main PTT */
1607 p_hwfn
->p_main_ptt
= qed_get_reserved_ptt(p_hwfn
, RESERVED_PTT_MAIN
);
1609 /* First hwfn learns basic information, e.g., number of hwfns */
1610 if (!p_hwfn
->my_id
) {
1611 rc
= qed_get_dev_info(p_hwfn
->cdev
);
1616 qed_hw_hwfn_prepare(p_hwfn
);
1618 /* Initialize MCP structure */
1619 rc
= qed_mcp_cmd_init(p_hwfn
, p_hwfn
->p_main_ptt
);
1621 DP_NOTICE(p_hwfn
, "Failed initializing mcp command\n");
1625 /* Read the device configuration information from the HW and SHMEM */
1626 rc
= qed_get_hw_info(p_hwfn
, p_hwfn
->p_main_ptt
, personality
);
1628 DP_NOTICE(p_hwfn
, "Failed to get HW information\n");
1632 /* Allocate the init RT array and initialize the init-ops engine */
1633 rc
= qed_init_alloc(p_hwfn
);
1635 DP_NOTICE(p_hwfn
, "Failed to allocate the init array\n");
1641 if (IS_LEAD_HWFN(p_hwfn
))
1642 qed_iov_free_hw_info(p_hwfn
->cdev
);
1643 qed_mcp_free(p_hwfn
);
1645 qed_hw_hwfn_free(p_hwfn
);
1650 int qed_hw_prepare(struct qed_dev
*cdev
,
1653 struct qed_hwfn
*p_hwfn
= QED_LEADING_HWFN(cdev
);
1656 /* Store the precompiled init data ptrs */
1658 qed_init_iro_array(cdev
);
1660 /* Initialize the first hwfn - will learn number of hwfns */
1661 rc
= qed_hw_prepare_single(p_hwfn
,
1663 cdev
->doorbells
, personality
);
1667 personality
= p_hwfn
->hw_info
.personality
;
1669 /* Initialize the rest of the hwfns */
1670 if (cdev
->num_hwfns
> 1) {
1671 void __iomem
*p_regview
, *p_doorbell
;
1674 /* adjust bar offset for second engine */
1675 addr
= cdev
->regview
+ qed_hw_bar_size(p_hwfn
, BAR_ID_0
) / 2;
1678 /* adjust doorbell bar offset for second engine */
1679 addr
= cdev
->doorbells
+ qed_hw_bar_size(p_hwfn
, BAR_ID_1
) / 2;
1682 /* prepare second hw function */
1683 rc
= qed_hw_prepare_single(&cdev
->hwfns
[1], p_regview
,
1684 p_doorbell
, personality
);
1686 /* in case of error, need to free the previously
1687 * initiliazed hwfn 0.
1691 qed_init_free(p_hwfn
);
1692 qed_mcp_free(p_hwfn
);
1693 qed_hw_hwfn_free(p_hwfn
);
1701 void qed_hw_remove(struct qed_dev
*cdev
)
1705 for_each_hwfn(cdev
, i
) {
1706 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
1709 qed_vf_pf_release(p_hwfn
);
1713 qed_init_free(p_hwfn
);
1714 qed_hw_hwfn_free(p_hwfn
);
1715 qed_mcp_free(p_hwfn
);
1718 qed_iov_free_hw_info(cdev
);
1721 int qed_chain_alloc(struct qed_dev
*cdev
,
1722 enum qed_chain_use_mode intended_use
,
1723 enum qed_chain_mode mode
,
1726 struct qed_chain
*p_chain
)
1728 dma_addr_t p_pbl_phys
= 0;
1729 void *p_pbl_virt
= NULL
;
1730 dma_addr_t p_phys
= 0;
1731 void *p_virt
= NULL
;
1735 if (mode
== QED_CHAIN_MODE_SINGLE
)
1738 page_cnt
= QED_CHAIN_PAGE_CNT(num_elems
, elem_size
, mode
);
1740 size
= page_cnt
* QED_CHAIN_PAGE_SIZE
;
1741 p_virt
= dma_alloc_coherent(&cdev
->pdev
->dev
,
1742 size
, &p_phys
, GFP_KERNEL
);
1744 DP_NOTICE(cdev
, "Failed to allocate chain mem\n");
1748 if (mode
== QED_CHAIN_MODE_PBL
) {
1749 size
= page_cnt
* QED_CHAIN_PBL_ENTRY_SIZE
;
1750 p_pbl_virt
= dma_alloc_coherent(&cdev
->pdev
->dev
,
1754 DP_NOTICE(cdev
, "Failed to allocate chain pbl mem\n");
1758 qed_chain_pbl_init(p_chain
, p_virt
, p_phys
, page_cnt
,
1759 (u8
)elem_size
, intended_use
,
1760 p_pbl_phys
, p_pbl_virt
);
1762 qed_chain_init(p_chain
, p_virt
, p_phys
, page_cnt
,
1763 (u8
)elem_size
, intended_use
, mode
);
1769 dma_free_coherent(&cdev
->pdev
->dev
,
1770 page_cnt
* QED_CHAIN_PAGE_SIZE
,
1772 dma_free_coherent(&cdev
->pdev
->dev
,
1773 page_cnt
* QED_CHAIN_PBL_ENTRY_SIZE
,
1774 p_pbl_virt
, p_pbl_phys
);
1779 void qed_chain_free(struct qed_dev
*cdev
,
1780 struct qed_chain
*p_chain
)
1784 if (!p_chain
->p_virt_addr
)
1787 if (p_chain
->mode
== QED_CHAIN_MODE_PBL
) {
1788 size
= p_chain
->page_cnt
* QED_CHAIN_PBL_ENTRY_SIZE
;
1789 dma_free_coherent(&cdev
->pdev
->dev
, size
,
1790 p_chain
->pbl
.p_virt_table
,
1791 p_chain
->pbl
.p_phys_table
);
1794 size
= p_chain
->page_cnt
* QED_CHAIN_PAGE_SIZE
;
1795 dma_free_coherent(&cdev
->pdev
->dev
, size
,
1796 p_chain
->p_virt_addr
,
1797 p_chain
->p_phys_addr
);
1800 int qed_fw_l2_queue(struct qed_hwfn
*p_hwfn
,
1801 u16 src_id
, u16
*dst_id
)
1803 if (src_id
>= RESC_NUM(p_hwfn
, QED_L2_QUEUE
)) {
1806 min
= (u16
)RESC_START(p_hwfn
, QED_L2_QUEUE
);
1807 max
= min
+ RESC_NUM(p_hwfn
, QED_L2_QUEUE
);
1809 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
1815 *dst_id
= RESC_START(p_hwfn
, QED_L2_QUEUE
) + src_id
;
1820 int qed_fw_vport(struct qed_hwfn
*p_hwfn
,
1821 u8 src_id
, u8
*dst_id
)
1823 if (src_id
>= RESC_NUM(p_hwfn
, QED_VPORT
)) {
1826 min
= (u8
)RESC_START(p_hwfn
, QED_VPORT
);
1827 max
= min
+ RESC_NUM(p_hwfn
, QED_VPORT
);
1829 "vport id [%d] is not valid, available indices [%d - %d]\n",
1835 *dst_id
= RESC_START(p_hwfn
, QED_VPORT
) + src_id
;
1840 int qed_fw_rss_eng(struct qed_hwfn
*p_hwfn
,
1841 u8 src_id
, u8
*dst_id
)
1843 if (src_id
>= RESC_NUM(p_hwfn
, QED_RSS_ENG
)) {
1846 min
= (u8
)RESC_START(p_hwfn
, QED_RSS_ENG
);
1847 max
= min
+ RESC_NUM(p_hwfn
, QED_RSS_ENG
);
1849 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
1855 *dst_id
= RESC_START(p_hwfn
, QED_RSS_ENG
) + src_id
;
1860 /* Calculate final WFQ values for all vports and configure them.
1861 * After this configuration each vport will have
1862 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
1864 static void qed_configure_wfq_for_all_vports(struct qed_hwfn
*p_hwfn
,
1865 struct qed_ptt
*p_ptt
,
1868 struct init_qm_vport_params
*vport_params
;
1871 vport_params
= p_hwfn
->qm_info
.qm_vport_params
;
1873 for (i
= 0; i
< p_hwfn
->qm_info
.num_vports
; i
++) {
1874 u32 wfq_speed
= p_hwfn
->qm_info
.wfq_data
[i
].min_speed
;
1876 vport_params
[i
].vport_wfq
= (wfq_speed
* QED_WFQ_UNIT
) /
1878 qed_init_vport_wfq(p_hwfn
, p_ptt
,
1879 vport_params
[i
].first_tx_pq_id
,
1880 vport_params
[i
].vport_wfq
);
1884 static void qed_init_wfq_default_param(struct qed_hwfn
*p_hwfn
,
1890 for (i
= 0; i
< p_hwfn
->qm_info
.num_vports
; i
++)
1891 p_hwfn
->qm_info
.qm_vport_params
[i
].vport_wfq
= 1;
1894 static void qed_disable_wfq_for_all_vports(struct qed_hwfn
*p_hwfn
,
1895 struct qed_ptt
*p_ptt
,
1898 struct init_qm_vport_params
*vport_params
;
1901 vport_params
= p_hwfn
->qm_info
.qm_vport_params
;
1903 for (i
= 0; i
< p_hwfn
->qm_info
.num_vports
; i
++) {
1904 qed_init_wfq_default_param(p_hwfn
, min_pf_rate
);
1905 qed_init_vport_wfq(p_hwfn
, p_ptt
,
1906 vport_params
[i
].first_tx_pq_id
,
1907 vport_params
[i
].vport_wfq
);
1911 /* This function performs several validations for WFQ
1912 * configuration and required min rate for a given vport
1913 * 1. req_rate must be greater than one percent of min_pf_rate.
1914 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
1915 * rates to get less than one percent of min_pf_rate.
1916 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
1918 static int qed_init_wfq_param(struct qed_hwfn
*p_hwfn
,
1919 u16 vport_id
, u32 req_rate
,
1922 u32 total_req_min_rate
= 0, total_left_rate
= 0, left_rate_per_vp
= 0;
1923 int non_requested_count
= 0, req_count
= 0, i
, num_vports
;
1925 num_vports
= p_hwfn
->qm_info
.num_vports
;
1927 /* Accounting for the vports which are configured for WFQ explicitly */
1928 for (i
= 0; i
< num_vports
; i
++) {
1931 if ((i
!= vport_id
) &&
1932 p_hwfn
->qm_info
.wfq_data
[i
].configured
) {
1934 tmp_speed
= p_hwfn
->qm_info
.wfq_data
[i
].min_speed
;
1935 total_req_min_rate
+= tmp_speed
;
1939 /* Include current vport data as well */
1941 total_req_min_rate
+= req_rate
;
1942 non_requested_count
= num_vports
- req_count
;
1944 if (req_rate
< min_pf_rate
/ QED_WFQ_UNIT
) {
1945 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
1946 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
1947 vport_id
, req_rate
, min_pf_rate
);
1951 if (num_vports
> QED_WFQ_UNIT
) {
1952 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
1953 "Number of vports is greater than %d\n",
1958 if (total_req_min_rate
> min_pf_rate
) {
1959 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
1960 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
1961 total_req_min_rate
, min_pf_rate
);
1965 total_left_rate
= min_pf_rate
- total_req_min_rate
;
1967 left_rate_per_vp
= total_left_rate
/ non_requested_count
;
1968 if (left_rate_per_vp
< min_pf_rate
/ QED_WFQ_UNIT
) {
1969 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
1970 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
1971 left_rate_per_vp
, min_pf_rate
);
1975 p_hwfn
->qm_info
.wfq_data
[vport_id
].min_speed
= req_rate
;
1976 p_hwfn
->qm_info
.wfq_data
[vport_id
].configured
= true;
1978 for (i
= 0; i
< num_vports
; i
++) {
1979 if (p_hwfn
->qm_info
.wfq_data
[i
].configured
)
1982 p_hwfn
->qm_info
.wfq_data
[i
].min_speed
= left_rate_per_vp
;
1988 static int __qed_configure_vport_wfq(struct qed_hwfn
*p_hwfn
,
1989 struct qed_ptt
*p_ptt
, u16 vp_id
, u32 rate
)
1991 struct qed_mcp_link_state
*p_link
;
1994 p_link
= &p_hwfn
->cdev
->hwfns
[0].mcp_info
->link_output
;
1996 if (!p_link
->min_pf_rate
) {
1997 p_hwfn
->qm_info
.wfq_data
[vp_id
].min_speed
= rate
;
1998 p_hwfn
->qm_info
.wfq_data
[vp_id
].configured
= true;
2002 rc
= qed_init_wfq_param(p_hwfn
, vp_id
, rate
, p_link
->min_pf_rate
);
2005 qed_configure_wfq_for_all_vports(p_hwfn
, p_ptt
,
2006 p_link
->min_pf_rate
);
2009 "Validation failed while configuring min rate\n");
2014 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn
*p_hwfn
,
2015 struct qed_ptt
*p_ptt
,
2018 bool use_wfq
= false;
2022 /* Validate all pre configured vports for wfq */
2023 for (i
= 0; i
< p_hwfn
->qm_info
.num_vports
; i
++) {
2026 if (!p_hwfn
->qm_info
.wfq_data
[i
].configured
)
2029 rate
= p_hwfn
->qm_info
.wfq_data
[i
].min_speed
;
2032 rc
= qed_init_wfq_param(p_hwfn
, i
, rate
, min_pf_rate
);
2035 "WFQ validation failed while configuring min rate\n");
2041 qed_configure_wfq_for_all_vports(p_hwfn
, p_ptt
, min_pf_rate
);
2043 qed_disable_wfq_for_all_vports(p_hwfn
, p_ptt
, min_pf_rate
);
2048 /* Main API for qed clients to configure vport min rate.
2049 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
2050 * rate - Speed in Mbps needs to be assigned to a given vport.
2052 int qed_configure_vport_wfq(struct qed_dev
*cdev
, u16 vp_id
, u32 rate
)
2054 int i
, rc
= -EINVAL
;
2056 /* Currently not supported; Might change in future */
2057 if (cdev
->num_hwfns
> 1) {
2059 "WFQ configuration is not supported for this device\n");
2063 for_each_hwfn(cdev
, i
) {
2064 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
2065 struct qed_ptt
*p_ptt
;
2067 p_ptt
= qed_ptt_acquire(p_hwfn
);
2071 rc
= __qed_configure_vport_wfq(p_hwfn
, p_ptt
, vp_id
, rate
);
2074 qed_ptt_release(p_hwfn
, p_ptt
);
2078 qed_ptt_release(p_hwfn
, p_ptt
);
2084 /* API to configure WFQ from mcp link change */
2085 void qed_configure_vp_wfq_on_link_change(struct qed_dev
*cdev
, u32 min_pf_rate
)
2089 for_each_hwfn(cdev
, i
) {
2090 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
2092 __qed_configure_vp_wfq_on_link_change(p_hwfn
,
2098 int __qed_configure_pf_max_bandwidth(struct qed_hwfn
*p_hwfn
,
2099 struct qed_ptt
*p_ptt
,
2100 struct qed_mcp_link_state
*p_link
,
2105 p_hwfn
->mcp_info
->func_info
.bandwidth_max
= max_bw
;
2107 if (!p_link
->line_speed
&& (max_bw
!= 100))
2110 p_link
->speed
= (p_link
->line_speed
* max_bw
) / 100;
2111 p_hwfn
->qm_info
.pf_rl
= p_link
->speed
;
2113 /* Since the limiter also affects Tx-switched traffic, we don't want it
2114 * to limit such traffic in case there's no actual limit.
2115 * In that case, set limit to imaginary high boundary.
2118 p_hwfn
->qm_info
.pf_rl
= 100000;
2120 rc
= qed_init_pf_rl(p_hwfn
, p_ptt
, p_hwfn
->rel_pf_id
,
2121 p_hwfn
->qm_info
.pf_rl
);
2123 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
2124 "Configured MAX bandwidth to be %08x Mb/sec\n",
2130 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
2131 int qed_configure_pf_max_bandwidth(struct qed_dev
*cdev
, u8 max_bw
)
2133 int i
, rc
= -EINVAL
;
2135 if (max_bw
< 1 || max_bw
> 100) {
2136 DP_NOTICE(cdev
, "PF max bw valid range is [1-100]\n");
2140 for_each_hwfn(cdev
, i
) {
2141 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
2142 struct qed_hwfn
*p_lead
= QED_LEADING_HWFN(cdev
);
2143 struct qed_mcp_link_state
*p_link
;
2144 struct qed_ptt
*p_ptt
;
2146 p_link
= &p_lead
->mcp_info
->link_output
;
2148 p_ptt
= qed_ptt_acquire(p_hwfn
);
2152 rc
= __qed_configure_pf_max_bandwidth(p_hwfn
, p_ptt
,
2155 qed_ptt_release(p_hwfn
, p_ptt
);
2164 int __qed_configure_pf_min_bandwidth(struct qed_hwfn
*p_hwfn
,
2165 struct qed_ptt
*p_ptt
,
2166 struct qed_mcp_link_state
*p_link
,
2171 p_hwfn
->mcp_info
->func_info
.bandwidth_min
= min_bw
;
2172 p_hwfn
->qm_info
.pf_wfq
= min_bw
;
2174 if (!p_link
->line_speed
)
2177 p_link
->min_pf_rate
= (p_link
->line_speed
* min_bw
) / 100;
2179 rc
= qed_init_pf_wfq(p_hwfn
, p_ptt
, p_hwfn
->rel_pf_id
, min_bw
);
2181 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
2182 "Configured MIN bandwidth to be %d Mb/sec\n",
2183 p_link
->min_pf_rate
);
2188 /* Main API to configure PF min bandwidth where bw range is [1-100] */
2189 int qed_configure_pf_min_bandwidth(struct qed_dev
*cdev
, u8 min_bw
)
2191 int i
, rc
= -EINVAL
;
2193 if (min_bw
< 1 || min_bw
> 100) {
2194 DP_NOTICE(cdev
, "PF min bw valid range is [1-100]\n");
2198 for_each_hwfn(cdev
, i
) {
2199 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
2200 struct qed_hwfn
*p_lead
= QED_LEADING_HWFN(cdev
);
2201 struct qed_mcp_link_state
*p_link
;
2202 struct qed_ptt
*p_ptt
;
2204 p_link
= &p_lead
->mcp_info
->link_output
;
2206 p_ptt
= qed_ptt_acquire(p_hwfn
);
2210 rc
= __qed_configure_pf_min_bandwidth(p_hwfn
, p_ptt
,
2213 qed_ptt_release(p_hwfn
, p_ptt
);
2217 if (p_link
->min_pf_rate
) {
2218 u32 min_rate
= p_link
->min_pf_rate
;
2220 rc
= __qed_configure_vp_wfq_on_link_change(p_hwfn
,
2225 qed_ptt_release(p_hwfn
, p_ptt
);
2231 void qed_clean_wfq_db(struct qed_hwfn
*p_hwfn
, struct qed_ptt
*p_ptt
)
2233 struct qed_mcp_link_state
*p_link
;
2235 p_link
= &p_hwfn
->mcp_info
->link_output
;
2237 if (p_link
->min_pf_rate
)
2238 qed_disable_wfq_for_all_vports(p_hwfn
, p_ptt
,
2239 p_link
->min_pf_rate
);
2241 memset(p_hwfn
->qm_info
.wfq_data
, 0,
2242 sizeof(*p_hwfn
->qm_info
.wfq_data
) * p_hwfn
->qm_info
.num_vports
);