drivers/net/ethernet/qlogic/qed/qed_hsi.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef _QED_HSI_H
  10 #define _QED_HSI_H
  11
  12 #include <linux/types.h>
  13 #include <linux/io.h>
  14 #include <linux/bitops.h>
  15 #include <linux/delay.h>
  16 #include <linux/kernel.h>
  17 #include <linux/list.h>
  18 #include <linux/slab.h>
  19 #include <linux/qed/common_hsi.h>
  20 #include <linux/qed/storage_common.h>
  21 #include <linux/qed/tcp_common.h>
  22 #include <linux/qed/eth_common.h>
  23 #include <linux/qed/iscsi_common.h>
  24 #include <linux/qed/rdma_common.h>
  25 #include <linux/qed/roce_common.h>
  26
  27 struct qed_hwfn;
  28 struct qed_ptt;
  29
  30 /* opcodes for the event ring */
  31 enum common_event_opcode {
  32         COMMON_EVENT_PF_START,
  33         COMMON_EVENT_PF_STOP,
  34         COMMON_EVENT_VF_START,
  35         COMMON_EVENT_VF_STOP,
  36         COMMON_EVENT_VF_PF_CHANNEL,
  37         COMMON_EVENT_VF_FLR,
  38         COMMON_EVENT_PF_UPDATE,
  39         COMMON_EVENT_MALICIOUS_VF,
  40         COMMON_EVENT_RL_UPDATE,
  41         COMMON_EVENT_EMPTY,
  42         MAX_COMMON_EVENT_OPCODE
  43 };
  44
  45 /* Common Ramrod Command IDs */
  46 enum common_ramrod_cmd_id {
  47         COMMON_RAMROD_UNUSED,
  48         COMMON_RAMROD_PF_START,
  49         COMMON_RAMROD_PF_STOP,
  50         COMMON_RAMROD_VF_START,
  51         COMMON_RAMROD_VF_STOP,
  52         COMMON_RAMROD_PF_UPDATE,
  53         COMMON_RAMROD_RL_UPDATE,
  54         COMMON_RAMROD_EMPTY,
  55         MAX_COMMON_RAMROD_CMD_ID
  56 };
  57
  58 /* The core storm context for the Ystorm */
  59 struct ystorm_core_conn_st_ctx {
  60         __le32 reserved[4];
  61 };
  62
  63 /* The core storm context for the Pstorm */
  64 struct pstorm_core_conn_st_ctx {
  65         __le32 reserved[4];
  66 };
  67
  68 /* Core Slowpath Connection storm context of Xstorm */
  69 struct xstorm_core_conn_st_ctx {
  70         __le32 spq_base_lo;
  71         __le32 spq_base_hi;
  72         struct regpair consolid_base_addr;
  73         __le16 spq_cons;
  74         __le16 consolid_cons;
  75         __le32 reserved0[55];
  76 };
  77
  78 struct xstorm_core_conn_ag_ctx {
  79         u8 reserved0;
  80         u8 core_state;
  81         u8 flags0;
  82 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1
  83 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
  84 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK          0x1
  85 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT         1
  86 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK          0x1
  87 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT         2
  88 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK       0x1
  89 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT      3
  90 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK          0x1
  91 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT         4
  92 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK          0x1
  93 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT         5
  94 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK          0x1
  95 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT         6
  96 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK          0x1
  97 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT         7
  98         u8 flags1;
  99 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK          0x1
 100 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT         0
 101 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK          0x1
 102 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT         1
 103 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK          0x1
 104 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT         2
 105 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK              0x1
 106 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT             3
 107 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK              0x1
 108 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT             4
 109 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK              0x1
 110 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT             5
 111 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK     0x1
 112 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT    6
 113 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK       0x1
 114 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT      7
 115         u8 flags2;
 116 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK        0x3
 117 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT       0
 118 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK        0x3
 119 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT       2
 120 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK        0x3
 121 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT       4
 122 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK        0x3
 123 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT       6
 124         u8 flags3;
 125 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK        0x3
 126 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT       0
 127 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK        0x3
 128 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT       2
 129 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK        0x3
 130 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT       4
 131 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK        0x3
 132 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT       6
 133         u8 flags4;
 134 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK        0x3
 135 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT       0
 136 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK        0x3
 137 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT       2
 138 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK       0x3
 139 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT      4
 140 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK       0x3
 141 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT      6
 142         u8 flags5;
 143 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK       0x3
 144 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT      0
 145 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK       0x3
 146 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT      2
 147 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK       0x3
 148 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT      4
 149 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK       0x3
 150 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT      6
 151         u8 flags6;
 152 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK   0x3
 153 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT  0
 154 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK               0x3
 155 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT              2
 156 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK              0x3
 157 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT             4
 158 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK       0x3
 159 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT      6
 160         u8 flags7;
 161 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK           0x3
 162 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT          0
 163 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK         0x3
 164 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT        2
 165 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK          0x3
 166 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT         4
 167 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK              0x1
 168 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT             6
 169 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK              0x1
 170 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT             7
 171         u8 flags8;
 172 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK      0x1
 173 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT     0
 174 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK      0x1
 175 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT     1
 176 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK      0x1
 177 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT     2
 178 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK      0x1
 179 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT     3
 180 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK      0x1
 181 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT     4
 182 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK      0x1
 183 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT     5
 184 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK      0x1
 185 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT     6
 186 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK      0x1
 187 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT     7
 188         u8 flags9;
 189 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK                     0x1
 190 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT                    0
 191 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK                     0x1
 192 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT                    1
 193 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK                     0x1
 194 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT                    2
 195 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK                     0x1
 196 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT                    3
 197 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK                     0x1
 198 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT                    4
 199 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK                     0x1
 200 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT                    5
 201 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK        0x1
 202 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT       6
 203 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK                     0x1
 204 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT                    7
 205         u8 flags10;
 206 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK           0x1
 207 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT          0
 208 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK    0x1
 209 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT   1
 210 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK        0x1
 211 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT       2
 212 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK         0x1
 213 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT        3
 214 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK       0x1
 215 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT      4
 216 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK             0x1
 217 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT            5
 218 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK         0x1
 219 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT        6
 220 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK         0x1
 221 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT        7
 222         u8 flags11;
 223 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK         0x1
 224 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT        0
 225 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK         0x1
 226 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT        1
 227 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK     0x1
 228 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT    2
 229 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK            0x1
 230 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT           3
 231 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK            0x1
 232 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT           4
 233 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK            0x1
 234 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT           5
 235 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK       0x1
 236 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT      6
 237 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK            0x1
 238 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT           7
 239         u8 flags12;
 240 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK           0x1
 241 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT          0
 242 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK           0x1
 243 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT          1
 244 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK       0x1
 245 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT      2
 246 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK       0x1
 247 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT      3
 248 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK           0x1
 249 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT          4
 250 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK           0x1
 251 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT          5
 252 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK           0x1
 253 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT          6
 254 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK           0x1
 255 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT          7
 256         u8 flags13;
 257 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK           0x1
 258 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT          0
 259 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK           0x1
 260 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT          1
 261 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK       0x1
 262 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT      2
 263 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK       0x1
 264 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT      3
 265 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK       0x1
 266 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT      4
 267 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK       0x1
 268 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT      5
 269 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK       0x1
 270 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT      6
 271 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK       0x1
 272 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT      7
 273         u8 flags14;
 274 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK      0x1
 275 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT     0
 276 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK      0x1
 277 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT     1
 278 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK      0x1
 279 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT     2
 280 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK      0x1
 281 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT     3
 282 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK      0x1
 283 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT     4
 284 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK      0x1
 285 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT     5
 286 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK       0x3
 287 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT      6
 288         u8 byte2;
 289         __le16 physical_q0;
 290         __le16 consolid_prod;
 291         __le16 reserved16;
 292         __le16 tx_bd_cons;
 293         __le16 tx_bd_or_spq_prod;
 294         __le16 word5;
 295         __le16 conn_dpi;
 296         u8 byte3;
 297         u8 byte4;
 298         u8 byte5;
 299         u8 byte6;
 300         __le32 reg0;
 301         __le32 reg1;
 302         __le32 reg2;
 303         __le32 reg3;
 304         __le32 reg4;
 305         __le32 reg5;
 306         __le32 reg6;
 307         __le16 word7;
 308         __le16 word8;
 309         __le16 word9;
 310         __le16 word10;
 311         __le32 reg7;
 312         __le32 reg8;
 313         __le32 reg9;
 314         u8 byte7;
 315         u8 byte8;
 316         u8 byte9;
 317         u8 byte10;
 318         u8 byte11;
 319         u8 byte12;
 320         u8 byte13;
 321         u8 byte14;
 322         u8 byte15;
 323         u8 byte16;
 324         __le16 word11;
 325         __le32 reg10;
 326         __le32 reg11;
 327         __le32 reg12;
 328         __le32 reg13;
 329         __le32 reg14;
 330         __le32 reg15;
 331         __le32 reg16;
 332         __le32 reg17;
 333         __le32 reg18;
 334         __le32 reg19;
 335         __le16 word12;
 336         __le16 word13;
 337         __le16 word14;
 338         __le16 word15;
 339 };
 340
 341 struct tstorm_core_conn_ag_ctx {
 342         u8 byte0;
 343         u8 byte1;
 344         u8 flags0;
 345 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK       0x1
 346 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT      0
 347 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK       0x1
 348 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT      1
 349 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK       0x1
 350 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT      2
 351 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK       0x1
 352 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT      3
 353 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK       0x1
 354 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT      4
 355 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK       0x1
 356 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT      5
 357 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK        0x3
 358 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT       6
 359         u8 flags1;
 360 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK        0x3
 361 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT       0
 362 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK        0x3
 363 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT       2
 364 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK        0x3
 365 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT       4
 366 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK        0x3
 367 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT       6
 368         u8 flags2;
 369 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK        0x3
 370 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT       0
 371 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK        0x3
 372 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT       2
 373 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK        0x3
 374 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT       4
 375 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK        0x3
 376 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT       6
 377         u8 flags3;
 378 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK        0x3
 379 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT       0
 380 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK       0x3
 381 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT      2
 382 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK      0x1
 383 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT     4
 384 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK      0x1
 385 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT     5
 386 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK      0x1
 387 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT     6
 388 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK      0x1
 389 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT     7
 390         u8 flags4;
 391 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK      0x1
 392 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT     0
 393 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK      0x1
 394 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT     1
 395 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK      0x1
 396 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT     2
 397 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK      0x1
 398 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT     3
 399 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK      0x1
 400 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT     4
 401 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK      0x1
 402 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT     5
 403 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK     0x1
 404 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT    6
 405 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK    0x1
 406 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT   7
 407         u8 flags5;
 408 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK    0x1
 409 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT   0
 410 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK    0x1
 411 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT   1
 412 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK    0x1
 413 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT   2
 414 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK    0x1
 415 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT   3
 416 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK    0x1
 417 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT   4
 418 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK    0x1
 419 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT   5
 420 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK    0x1
 421 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT   6
 422 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK    0x1
 423 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT   7
 424         __le32 reg0;
 425         __le32 reg1;
 426         __le32 reg2;
 427         __le32 reg3;
 428         __le32 reg4;
 429         __le32 reg5;
 430         __le32 reg6;
 431         __le32 reg7;
 432         __le32 reg8;
 433         u8 byte2;
 434         u8 byte3;
 435         __le16 word0;
 436         u8 byte4;
 437         u8 byte5;
 438         __le16 word1;
 439         __le16 word2;
 440         __le16 word3;
 441         __le32 reg9;
 442         __le32 reg10;
 443 };
 444
 445 struct ustorm_core_conn_ag_ctx {
 446         u8 reserved;
 447         u8 byte1;
 448         u8 flags0;
 449 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK       0x1
 450 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT      0
 451 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK       0x1
 452 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT      1
 453 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK        0x3
 454 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT       2
 455 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK        0x3
 456 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT       4
 457 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK        0x3
 458 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT       6
 459         u8 flags1;
 460 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK        0x3
 461 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT       0
 462 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK        0x3
 463 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT       2
 464 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK        0x3
 465 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT       4
 466 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK        0x3
 467 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT       6
 468         u8 flags2;
 469 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK      0x1
 470 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT     0
 471 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK      0x1
 472 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT     1
 473 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK      0x1
 474 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT     2
 475 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK      0x1
 476 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT     3
 477 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK      0x1
 478 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT     4
 479 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK      0x1
 480 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT     5
 481 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK      0x1
 482 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT     6
 483 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK    0x1
 484 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT   7
 485         u8 flags3;
 486 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK    0x1
 487 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT   0
 488 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK    0x1
 489 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT   1
 490 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK    0x1
 491 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT   2
 492 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK    0x1
 493 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT   3
 494 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK    0x1
 495 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT   4
 496 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK    0x1
 497 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT   5
 498 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK    0x1
 499 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT   6
 500 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK    0x1
 501 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT   7
 502         u8 byte2;
 503         u8 byte3;
 504         __le16 word0;
 505         __le16 word1;
 506         __le32 rx_producers;
 507         __le32 reg1;
 508         __le32 reg2;
 509         __le32 reg3;
 510         __le16 word2;
 511         __le16 word3;
 512 };
 513
 514 /* The core storm context for the Mstorm */
 515 struct mstorm_core_conn_st_ctx {
 516         __le32 reserved[24];
 517 };
 518
 519 /* The core storm context for the Ustorm */
 520 struct ustorm_core_conn_st_ctx {
 521         __le32 reserved[4];
 522 };
 523
 524 /* core connection context */
 525 struct core_conn_context {
 526         struct ystorm_core_conn_st_ctx ystorm_st_context;
 527         struct regpair ystorm_st_padding[2];
 528         struct pstorm_core_conn_st_ctx pstorm_st_context;
 529         struct regpair pstorm_st_padding[2];
 530         struct xstorm_core_conn_st_ctx xstorm_st_context;
 531         struct xstorm_core_conn_ag_ctx xstorm_ag_context;
 532         struct tstorm_core_conn_ag_ctx tstorm_ag_context;
 533         struct ustorm_core_conn_ag_ctx ustorm_ag_context;
 534         struct mstorm_core_conn_st_ctx mstorm_st_context;
 535         struct ustorm_core_conn_st_ctx ustorm_st_context;
 536         struct regpair ustorm_st_padding[2];
 537 };
 538
 539 struct eth_mstorm_per_pf_stat {
 540         struct regpair gre_discard_pkts;
 541         struct regpair vxlan_discard_pkts;
 542         struct regpair geneve_discard_pkts;
 543         struct regpair lb_discard_pkts;
 544 };
 545
 546 struct eth_mstorm_per_queue_stat {
 547         struct regpair ttl0_discard;
 548         struct regpair packet_too_big_discard;
 549         struct regpair no_buff_discard;
 550         struct regpair not_active_discard;
 551         struct regpair tpa_coalesced_pkts;
 552         struct regpair tpa_coalesced_events;
 553         struct regpair tpa_aborts_num;
 554         struct regpair tpa_coalesced_bytes;
 555 };
 556
 557 /* Ethernet TX Per PF */
 558 struct eth_pstorm_per_pf_stat {
 559         struct regpair sent_lb_ucast_bytes;
 560         struct regpair sent_lb_mcast_bytes;
 561         struct regpair sent_lb_bcast_bytes;
 562         struct regpair sent_lb_ucast_pkts;
 563         struct regpair sent_lb_mcast_pkts;
 564         struct regpair sent_lb_bcast_pkts;
 565         struct regpair sent_gre_bytes;
 566         struct regpair sent_vxlan_bytes;
 567         struct regpair sent_geneve_bytes;
 568         struct regpair sent_gre_pkts;
 569         struct regpair sent_vxlan_pkts;
 570         struct regpair sent_geneve_pkts;
 571         struct regpair gre_drop_pkts;
 572         struct regpair vxlan_drop_pkts;
 573         struct regpair geneve_drop_pkts;
 574 };
 575
 576 /* Ethernet TX Per Queue Stats */
 577 struct eth_pstorm_per_queue_stat {
 578         struct regpair sent_ucast_bytes;
 579         struct regpair sent_mcast_bytes;
 580         struct regpair sent_bcast_bytes;
 581         struct regpair sent_ucast_pkts;
 582         struct regpair sent_mcast_pkts;
 583         struct regpair sent_bcast_pkts;
 584         struct regpair error_drop_pkts;
 585 };
 586
 587 /* ETH Rx producers data */
 588 struct eth_rx_rate_limit {
 589         __le16 mult;
 590         __le16 cnst;
 591         u8 add_sub_cnst;
 592         u8 reserved0;
 593         __le16 reserved1;
 594 };
 595
 596 struct eth_ustorm_per_pf_stat {
 597         struct regpair rcv_lb_ucast_bytes;
 598         struct regpair rcv_lb_mcast_bytes;
 599         struct regpair rcv_lb_bcast_bytes;
 600         struct regpair rcv_lb_ucast_pkts;
 601         struct regpair rcv_lb_mcast_pkts;
 602         struct regpair rcv_lb_bcast_pkts;
 603         struct regpair rcv_gre_bytes;
 604         struct regpair rcv_vxlan_bytes;
 605         struct regpair rcv_geneve_bytes;
 606         struct regpair rcv_gre_pkts;
 607         struct regpair rcv_vxlan_pkts;
 608         struct regpair rcv_geneve_pkts;
 609 };
 610
 611 struct eth_ustorm_per_queue_stat {
 612         struct regpair rcv_ucast_bytes;
 613         struct regpair rcv_mcast_bytes;
 614         struct regpair rcv_bcast_bytes;
 615         struct regpair rcv_ucast_pkts;
 616         struct regpair rcv_mcast_pkts;
 617         struct regpair rcv_bcast_pkts;
 618 };
 619
 620 /* Event Ring Next Page Address */
 621 struct event_ring_next_addr {
 622         struct regpair addr;
 623         __le32 reserved[2];
 624 };
 625
 626 /* Event Ring Element */
 627 union event_ring_element {
 628         struct event_ring_entry entry;
 629         struct event_ring_next_addr next_addr;
 630 };
 631
 632 /* Major and Minor hsi Versions */
 633 struct hsi_fp_ver_struct {
 634         u8 minor_ver_arr[2];
 635         u8 major_ver_arr[2];
 636 };
 637
 638 /* Mstorm non-triggering VF zone */
 639 struct mstorm_non_trigger_vf_zone {
 640         struct eth_mstorm_per_queue_stat eth_queue_stat;
 641         struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF];
 642 };
 643
 644 /* Mstorm VF zone */
 645 struct mstorm_vf_zone {
 646         struct mstorm_non_trigger_vf_zone non_trigger;
 647
 648 };
 649
 650 /* personality per PF */
 651 enum personality_type {
 652         BAD_PERSONALITY_TYP,
 653         PERSONALITY_ISCSI,
 654         PERSONALITY_RESERVED2,
 655         PERSONALITY_RDMA_AND_ETH,
 656         PERSONALITY_RESERVED3,
 657         PERSONALITY_CORE,
 658         PERSONALITY_ETH,
 659         PERSONALITY_RESERVED4,
 660         MAX_PERSONALITY_TYPE
 661 };
 662
 663 /* tunnel configuration */
 664 struct pf_start_tunnel_config {
 665         u8 set_vxlan_udp_port_flg;
 666         u8 set_geneve_udp_port_flg;
 667         u8 tx_enable_vxlan;
 668         u8 tx_enable_l2geneve;
 669         u8 tx_enable_ipgeneve;
 670         u8 tx_enable_l2gre;
 671         u8 tx_enable_ipgre;
 672         u8 tunnel_clss_vxlan;
 673         u8 tunnel_clss_l2geneve;
 674         u8 tunnel_clss_ipgeneve;
 675         u8 tunnel_clss_l2gre;
 676         u8 tunnel_clss_ipgre;
 677         __le16 vxlan_udp_port;
 678         __le16 geneve_udp_port;
 679 };
 680
 681 /* Ramrod data for PF start ramrod */
 682 struct pf_start_ramrod_data {
 683         struct regpair event_ring_pbl_addr;
 684         struct regpair consolid_q_pbl_addr;
 685         struct pf_start_tunnel_config tunnel_config;
 686         __le16 event_ring_sb_id;
 687         u8 base_vf_id;
 688         u8 num_vfs;
 689         u8 event_ring_num_pages;
 690         u8 event_ring_sb_index;
 691         u8 path_id;
 692         u8 warning_as_error;
 693         u8 dont_log_ramrods;
 694         u8 personality;
 695         __le16 log_type_mask;
 696         u8 mf_mode;
 697         u8 integ_phase;
 698         u8 allow_npar_tx_switching;
 699         u8 inner_to_outer_pri_map[8];
 700         u8 pri_map_valid;
 701         __le32 outer_tag;
 702         struct hsi_fp_ver_struct hsi_fp_ver;
 703
 704 };
 705
 706 struct protocol_dcb_data {
 707         u8 dcb_enable_flag;
 708         u8 dcb_priority;
 709         u8 dcb_tc;
 710         u8 reserved;
 711 };
 712
 713 struct pf_update_tunnel_config {
 714         u8 update_rx_pf_clss;
 715         u8 update_tx_pf_clss;
 716         u8 set_vxlan_udp_port_flg;
 717         u8 set_geneve_udp_port_flg;
 718         u8 tx_enable_vxlan;
 719         u8 tx_enable_l2geneve;
 720         u8 tx_enable_ipgeneve;
 721         u8 tx_enable_l2gre;
 722         u8 tx_enable_ipgre;
 723         u8 tunnel_clss_vxlan;
 724         u8 tunnel_clss_l2geneve;
 725         u8 tunnel_clss_ipgeneve;
 726         u8 tunnel_clss_l2gre;
 727         u8 tunnel_clss_ipgre;
 728         __le16 vxlan_udp_port;
 729         __le16 geneve_udp_port;
 730         __le16 reserved[3];
 731 };
 732
 733 struct pf_update_ramrod_data {
 734         u8 pf_id;
 735         u8 update_eth_dcb_data_flag;
 736         u8 update_fcoe_dcb_data_flag;
 737         u8 update_iscsi_dcb_data_flag;
 738         u8 update_roce_dcb_data_flag;
 739         u8 update_iwarp_dcb_data_flag;
 740         u8 update_mf_vlan_flag;
 741         u8 reserved;
 742         struct protocol_dcb_data eth_dcb_data;
 743         struct protocol_dcb_data fcoe_dcb_data;
 744         struct protocol_dcb_data iscsi_dcb_data;
 745         struct protocol_dcb_data roce_dcb_data;
 746         struct protocol_dcb_data iwarp_dcb_data;
 747         __le16 mf_vlan;
 748         __le16 reserved2;
 749         struct pf_update_tunnel_config tunnel_config;
 750 };
 751
 752 /* Ports mode */
 753 enum ports_mode {
 754         ENGX2_PORTX1,
 755         ENGX2_PORTX2,
 756         ENGX1_PORTX1,
 757         ENGX1_PORTX2,
 758         ENGX1_PORTX4,
 759         MAX_PORTS_MODE
 760 };
 761
 762 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
 763 enum protocol_version_array_key {
 764         ETH_VER_KEY = 0,
 765         ROCE_VER_KEY,
 766         MAX_PROTOCOL_VERSION_ARRAY_KEY
 767 };
 768
 769 /* Pstorm non-triggering VF zone */
 770 struct pstorm_non_trigger_vf_zone {
 771         struct eth_pstorm_per_queue_stat eth_queue_stat;
 772         struct regpair reserved[2];
 773 };
 774
 775 /* Pstorm VF zone */
 776 struct pstorm_vf_zone {
 777         struct pstorm_non_trigger_vf_zone non_trigger;
 778         struct regpair reserved[7];
 779 };
 780
 781 /* Ramrod Header of SPQE */
 782 struct ramrod_header {
 783         __le32 cid;
 784         u8 cmd_id;
 785         u8 protocol_id;
 786         __le16 echo;
 787 };
 788
 789 /* Slowpath Element (SPQE) */
 790 struct slow_path_element {
 791         struct ramrod_header hdr;
 792         struct regpair data_ptr;
 793 };
 794
 795 /* Tstorm non-triggering VF zone */
 796 struct tstorm_non_trigger_vf_zone {
 797         struct regpair reserved[2];
 798 };
 799
 800 struct tstorm_per_port_stat {
 801         struct regpair trunc_error_discard;
 802         struct regpair mac_error_discard;
 803         struct regpair mftag_filter_discard;
 804         struct regpair eth_mac_filter_discard;
 805         struct regpair reserved[5];
 806         struct regpair eth_irregular_pkt;
 807         struct regpair reserved1[2];
 808         struct regpair eth_gre_tunn_filter_discard;
 809         struct regpair eth_vxlan_tunn_filter_discard;
 810         struct regpair eth_geneve_tunn_filter_discard;
 811 };
 812
 813 /* Tstorm VF zone */
 814 struct tstorm_vf_zone {
 815         struct tstorm_non_trigger_vf_zone non_trigger;
 816 };
 817
 818 /* Tunnel classification scheme */
 819 enum tunnel_clss {
 820         TUNNEL_CLSS_MAC_VLAN = 0,
 821         TUNNEL_CLSS_MAC_VNI,
 822         TUNNEL_CLSS_INNER_MAC_VLAN,
 823         TUNNEL_CLSS_INNER_MAC_VNI,
 824         TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
 825         MAX_TUNNEL_CLSS
 826 };
 827
 828 /* Ustorm non-triggering VF zone */
 829 struct ustorm_non_trigger_vf_zone {
 830         struct eth_ustorm_per_queue_stat eth_queue_stat;
 831         struct regpair vf_pf_msg_addr;
 832 };
 833
 834 /* Ustorm triggering VF zone */
 835 struct ustorm_trigger_vf_zone {
 836         u8 vf_pf_msg_valid;
 837         u8 reserved[7];
 838 };
 839
 840 /* Ustorm VF zone */
 841 struct ustorm_vf_zone {
 842         struct ustorm_non_trigger_vf_zone non_trigger;
 843         struct ustorm_trigger_vf_zone trigger;
 844 };
 845
 846 /* VF-PF channel data */
 847 struct vf_pf_channel_data {
 848         __le32 ready;
 849         u8 valid;
 850         u8 reserved0;
 851         __le16 reserved1;
 852 };
 853
 854 /* Ramrod data for VF start ramrod */
 855 struct vf_start_ramrod_data {
 856         u8 vf_id;
 857         u8 enable_flr_ack;
 858         __le16 opaque_fid;
 859         u8 personality;
 860         u8 reserved[7];
 861         struct hsi_fp_ver_struct hsi_fp_ver;
 862
 863 };
 864
 865 /* Ramrod data for VF start ramrod */
 866 struct vf_stop_ramrod_data {
 867         u8 vf_id;
 868         u8 reserved0;
 869         __le16 reserved1;
 870         __le32 reserved2;
 871 };
 872
 873 /* Attentions status block */
 874 struct atten_status_block {
 875         __le32 atten_bits;
 876         __le32 atten_ack;
 877         __le16 reserved0;
 878         __le16 sb_index;
 879         __le32 reserved1;
 880 };
 881
 882 enum command_type_bit {
 883         IGU_COMMAND_TYPE_NOP = 0,
 884         IGU_COMMAND_TYPE_SET = 1,
 885         MAX_COMMAND_TYPE_BIT
 886 };
 887
 888 /* DMAE command */
 889 struct dmae_cmd {
 890         __le32 opcode;
 891 #define DMAE_CMD_SRC_MASK               0x1
 892 #define DMAE_CMD_SRC_SHIFT              0
 893 #define DMAE_CMD_DST_MASK               0x3
 894 #define DMAE_CMD_DST_SHIFT              1
 895 #define DMAE_CMD_C_DST_MASK             0x1
 896 #define DMAE_CMD_C_DST_SHIFT            3
 897 #define DMAE_CMD_CRC_RESET_MASK         0x1
 898 #define DMAE_CMD_CRC_RESET_SHIFT        4
 899 #define DMAE_CMD_SRC_ADDR_RESET_MASK    0x1
 900 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT   5
 901 #define DMAE_CMD_DST_ADDR_RESET_MASK    0x1
 902 #define DMAE_CMD_DST_ADDR_RESET_SHIFT   6
 903 #define DMAE_CMD_COMP_FUNC_MASK         0x1
 904 #define DMAE_CMD_COMP_FUNC_SHIFT        7
 905 #define DMAE_CMD_COMP_WORD_EN_MASK      0x1
 906 #define DMAE_CMD_COMP_WORD_EN_SHIFT     8
 907 #define DMAE_CMD_COMP_CRC_EN_MASK       0x1
 908 #define DMAE_CMD_COMP_CRC_EN_SHIFT      9
 909 #define DMAE_CMD_COMP_CRC_OFFSET_MASK   0x7
 910 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
 911 #define DMAE_CMD_RESERVED1_MASK         0x1
 912 #define DMAE_CMD_RESERVED1_SHIFT        13
 913 #define DMAE_CMD_ENDIANITY_MODE_MASK    0x3
 914 #define DMAE_CMD_ENDIANITY_MODE_SHIFT   14
 915 #define DMAE_CMD_ERR_HANDLING_MASK      0x3
 916 #define DMAE_CMD_ERR_HANDLING_SHIFT     16
 917 #define DMAE_CMD_PORT_ID_MASK           0x3
 918 #define DMAE_CMD_PORT_ID_SHIFT          18
 919 #define DMAE_CMD_SRC_PF_ID_MASK         0xF
 920 #define DMAE_CMD_SRC_PF_ID_SHIFT        20
 921 #define DMAE_CMD_DST_PF_ID_MASK         0xF
 922 #define DMAE_CMD_DST_PF_ID_SHIFT        24
 923 #define DMAE_CMD_SRC_VF_ID_VALID_MASK   0x1
 924 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
 925 #define DMAE_CMD_DST_VF_ID_VALID_MASK   0x1
 926 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
 927 #define DMAE_CMD_RESERVED2_MASK         0x3
 928 #define DMAE_CMD_RESERVED2_SHIFT        30
 929         __le32 src_addr_lo;
 930         __le32 src_addr_hi;
 931         __le32 dst_addr_lo;
 932         __le32 dst_addr_hi;
 933         __le16 length_dw;
 934         __le16 opcode_b;
 935 #define DMAE_CMD_SRC_VF_ID_MASK         0xFF
 936 #define DMAE_CMD_SRC_VF_ID_SHIFT        0
 937 #define DMAE_CMD_DST_VF_ID_MASK         0xFF
 938 #define DMAE_CMD_DST_VF_ID_SHIFT        8
 939         __le32 comp_addr_lo;
 940         __le32 comp_addr_hi;
 941         __le32 comp_val;
 942         __le32 crc32;
 943         __le32 crc_32_c;
 944         __le16 crc16;
 945         __le16 crc16_c;
 946         __le16 crc10;
 947         __le16 reserved;
 948         __le16 xsum16;
 949         __le16 xsum8;
 950 };
 951
 952 enum dmae_cmd_comp_crc_en_enum {
 953         dmae_cmd_comp_crc_disabled,
 954         dmae_cmd_comp_crc_enabled,
 955         MAX_DMAE_CMD_COMP_CRC_EN_ENUM
 956 };
 957
 958 enum dmae_cmd_comp_func_enum {
 959         dmae_cmd_comp_func_to_src,
 960         dmae_cmd_comp_func_to_dst,
 961         MAX_DMAE_CMD_COMP_FUNC_ENUM
 962 };
 963
 964 enum dmae_cmd_comp_word_en_enum {
 965         dmae_cmd_comp_word_disabled,
 966         dmae_cmd_comp_word_enabled,
 967         MAX_DMAE_CMD_COMP_WORD_EN_ENUM
 968 };
 969
 970 enum dmae_cmd_c_dst_enum {
 971         dmae_cmd_c_dst_pcie,
 972         dmae_cmd_c_dst_grc,
 973         MAX_DMAE_CMD_C_DST_ENUM
 974 };
 975
 976 enum dmae_cmd_dst_enum {
 977         dmae_cmd_dst_none_0,
 978         dmae_cmd_dst_pcie,
 979         dmae_cmd_dst_grc,
 980         dmae_cmd_dst_none_3,
 981         MAX_DMAE_CMD_DST_ENUM
 982 };
 983
 984 enum dmae_cmd_error_handling_enum {
 985         dmae_cmd_error_handling_send_regular_comp,
 986         dmae_cmd_error_handling_send_comp_with_err,
 987         dmae_cmd_error_handling_dont_send_comp,
 988         MAX_DMAE_CMD_ERROR_HANDLING_ENUM
 989 };
 990
 991 enum dmae_cmd_src_enum {
 992         dmae_cmd_src_pcie,
 993         dmae_cmd_src_grc,
 994         MAX_DMAE_CMD_SRC_ENUM
 995 };
 996
 997 /* IGU cleanup command */
 998 struct igu_cleanup {
 999         __le32 sb_id_and_flags;
1000 #define IGU_CLEANUP_RESERVED0_MASK      0x7FFFFFF
1001 #define IGU_CLEANUP_RESERVED0_SHIFT     0
1002 #define IGU_CLEANUP_CLEANUP_SET_MASK    0x1
1003 #define IGU_CLEANUP_CLEANUP_SET_SHIFT   27
1004 #define IGU_CLEANUP_CLEANUP_TYPE_MASK   0x7
1005 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT  28
1006 #define IGU_CLEANUP_COMMAND_TYPE_MASK   0x1
1007 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT  31
1008         __le32 reserved1;
1009 };
1010
1011 /* IGU firmware driver command */
1012 union igu_command {
1013         struct igu_prod_cons_update prod_cons_update;
1014         struct igu_cleanup cleanup;
1015 };
1016
1017 /* IGU firmware driver command */
1018 struct igu_command_reg_ctrl {
1019         __le16 opaque_fid;
1020         __le16 igu_command_reg_ctrl_fields;
1021 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK  0xFFF
1022 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1023 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK      0x7
1024 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT     12
1025 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK  0x1
1026 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1027 };
1028
1029 /* IGU mapping line structure */
1030 struct igu_mapping_line {
1031         __le32 igu_mapping_line_fields;
1032 #define IGU_MAPPING_LINE_VALID_MASK             0x1
1033 #define IGU_MAPPING_LINE_VALID_SHIFT            0
1034 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK     0xFF
1035 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT    1
1036 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK   0xFF
1037 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT  9
1038 #define IGU_MAPPING_LINE_PF_VALID_MASK          0x1
1039 #define IGU_MAPPING_LINE_PF_VALID_SHIFT         17
1040 #define IGU_MAPPING_LINE_IPS_GROUP_MASK         0x3F
1041 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT        18
1042 #define IGU_MAPPING_LINE_RESERVED_MASK          0xFF
1043 #define IGU_MAPPING_LINE_RESERVED_SHIFT         24
1044 };
1045
1046 /* IGU MSIX line structure */
1047 struct igu_msix_vector {
1048         struct regpair address;
1049         __le32 data;
1050         __le32 msix_vector_fields;
1051 #define IGU_MSIX_VECTOR_MASK_BIT_MASK           0x1
1052 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT          0
1053 #define IGU_MSIX_VECTOR_RESERVED0_MASK          0x7FFF
1054 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT         1
1055 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK       0xFF
1056 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT      16
1057 #define IGU_MSIX_VECTOR_RESERVED1_MASK          0xFF
1058 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT         24
1059 };
1060
1061 struct mstorm_core_conn_ag_ctx {
1062         u8 byte0;
1063         u8 byte1;
1064         u8 flags0;
1065 #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK       0x1
1066 #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT      0
1067 #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK       0x1
1068 #define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT      1
1069 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK        0x3
1070 #define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT       2
1071 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK        0x3
1072 #define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT       4
1073 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK        0x3
1074 #define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT       6
1075         u8 flags1;
1076 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK      0x1
1077 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT     0
1078 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK      0x1
1079 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT     1
1080 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK      0x1
1081 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT     2
1082 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK    0x1
1083 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT   3
1084 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK    0x1
1085 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT   4
1086 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK    0x1
1087 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT   5
1088 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK    0x1
1089 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT   6
1090 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK    0x1
1091 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT   7
1092         __le16 word0;
1093         __le16 word1;
1094         __le32 reg0;
1095         __le32 reg1;
1096 };
1097
1098 /* per encapsulation type enabling flags */
1099 struct prs_reg_encapsulation_type_en {
1100         u8 flags;
1101 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK          0x1
1102 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT         0
1103 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK           0x1
1104 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT          1
1105 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK                 0x1
1106 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT                2
1107 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK                 0x1
1108 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT                3
1109 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK       0x1
1110 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT      4
1111 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK        0x1
1112 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT       5
1113 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK                     0x3
1114 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT                    6
1115 };
1116
1117 enum pxp_tph_st_hint {
1118         TPH_ST_HINT_BIDIR,
1119         TPH_ST_HINT_REQUESTER,
1120         TPH_ST_HINT_TARGET,
1121         TPH_ST_HINT_TARGET_PRIO,
1122         MAX_PXP_TPH_ST_HINT
1123 };
1124
1125 /* QM hardware structure of enable bypass credit mask */
1126 struct qm_rf_bypass_mask {
1127         u8 flags;
1128 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK          0x1
1129 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT         0
1130 #define QM_RF_BYPASS_MASK_RESERVED0_MASK        0x1
1131 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT       1
1132 #define QM_RF_BYPASS_MASK_PFWFQ_MASK            0x1
1133 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT           2
1134 #define QM_RF_BYPASS_MASK_VPWFQ_MASK            0x1
1135 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT           3
1136 #define QM_RF_BYPASS_MASK_PFRL_MASK             0x1
1137 #define QM_RF_BYPASS_MASK_PFRL_SHIFT            4
1138 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK          0x1
1139 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT         5
1140 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK          0x1
1141 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT         6
1142 #define QM_RF_BYPASS_MASK_RESERVED1_MASK        0x1
1143 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT       7
1144 };
1145
1146 /* QM hardware structure of opportunistic credit mask */
1147 struct qm_rf_opportunistic_mask {
1148         __le16 flags;
1149 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK           0x1
1150 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT          0
1151 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK           0x1
1152 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT          1
1153 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK             0x1
1154 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT            2
1155 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK             0x1
1156 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT            3
1157 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK              0x1
1158 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT             4
1159 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK           0x1
1160 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT          5
1161 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK           0x1
1162 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT          6
1163 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK         0x1
1164 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT        7
1165 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK        0x1
1166 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT       8
1167 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK         0x7F
1168 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT        9
1169 };
1170
1171 /* QM hardware structure of QM map memory */
1172 struct qm_rf_pq_map {
1173         __le32 reg;
1174 #define QM_RF_PQ_MAP_PQ_VALID_MASK              0x1
1175 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT             0
1176 #define QM_RF_PQ_MAP_RL_ID_MASK                 0xFF
1177 #define QM_RF_PQ_MAP_RL_ID_SHIFT                1
1178 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK              0x1FF
1179 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT             9
1180 #define QM_RF_PQ_MAP_VOQ_MASK                   0x1F
1181 #define QM_RF_PQ_MAP_VOQ_SHIFT                  18
1182 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK      0x3
1183 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT     23
1184 #define QM_RF_PQ_MAP_RL_VALID_MASK              0x1
1185 #define QM_RF_PQ_MAP_RL_VALID_SHIFT             25
1186 #define QM_RF_PQ_MAP_RESERVED_MASK              0x3F
1187 #define QM_RF_PQ_MAP_RESERVED_SHIFT             26
1188 };
1189
1190 /* Completion params for aggregated interrupt completion */
1191 struct sdm_agg_int_comp_params {
1192         __le16 params;
1193 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK      0x3F
1194 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT     0
1195 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK  0x1
1196 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1197 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK     0x1FF
1198 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT    7
1199 };
1200
1201 /* SDM operation gen command (generate aggregative interrupt) */
1202 struct sdm_op_gen {
1203         __le32 command;
1204 #define SDM_OP_GEN_COMP_PARAM_MASK      0xFFFF
1205 #define SDM_OP_GEN_COMP_PARAM_SHIFT     0
1206 #define SDM_OP_GEN_COMP_TYPE_MASK       0xF
1207 #define SDM_OP_GEN_COMP_TYPE_SHIFT      16
1208 #define SDM_OP_GEN_RESERVED_MASK        0xFFF
1209 #define SDM_OP_GEN_RESERVED_SHIFT       20
1210 };
1211
1212 struct ystorm_core_conn_ag_ctx {
1213         u8 byte0;
1214         u8 byte1;
1215         u8 flags0;
1216 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK       0x1
1217 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT      0
1218 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK       0x1
1219 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT      1
1220 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK        0x3
1221 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT       2
1222 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK        0x3
1223 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT       4
1224 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK        0x3
1225 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT       6
1226         u8 flags1;
1227 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK      0x1
1228 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT     0
1229 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK      0x1
1230 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT     1
1231 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK      0x1
1232 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT     2
1233 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK    0x1
1234 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT   3
1235 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK    0x1
1236 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT   4
1237 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK    0x1
1238 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT   5
1239 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK    0x1
1240 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT   6
1241 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK    0x1
1242 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT   7
1243         u8 byte2;
1244         u8 byte3;
1245         __le16 word0;
1246         __le32 reg0;
1247         __le32 reg1;
1248         __le16 word1;
1249         __le16 word2;
1250         __le16 word3;
1251         __le16 word4;
1252         __le32 reg2;
1253         __le32 reg3;
1254 };
1255
1256 /****************************************/
1257 /* Debug Tools HSI constants and macros */
1258 /****************************************/
1259
1260 enum block_addr {
1261         GRCBASE_GRC = 0x50000,
1262         GRCBASE_MISCS = 0x9000,
1263         GRCBASE_MISC = 0x8000,
1264         GRCBASE_DBU = 0xa000,
1265         GRCBASE_PGLUE_B = 0x2a8000,
1266         GRCBASE_CNIG = 0x218000,
1267         GRCBASE_CPMU = 0x30000,
1268         GRCBASE_NCSI = 0x40000,
1269         GRCBASE_OPTE = 0x53000,
1270         GRCBASE_BMB = 0x540000,
1271         GRCBASE_PCIE = 0x54000,
1272         GRCBASE_MCP = 0xe00000,
1273         GRCBASE_MCP2 = 0x52000,
1274         GRCBASE_PSWHST = 0x2a0000,
1275         GRCBASE_PSWHST2 = 0x29e000,
1276         GRCBASE_PSWRD = 0x29c000,
1277         GRCBASE_PSWRD2 = 0x29d000,
1278         GRCBASE_PSWWR = 0x29a000,
1279         GRCBASE_PSWWR2 = 0x29b000,
1280         GRCBASE_PSWRQ = 0x280000,
1281         GRCBASE_PSWRQ2 = 0x240000,
1282         GRCBASE_PGLCS = 0x0,
1283         GRCBASE_DMAE = 0xc000,
1284         GRCBASE_PTU = 0x560000,
1285         GRCBASE_TCM = 0x1180000,
1286         GRCBASE_MCM = 0x1200000,
1287         GRCBASE_UCM = 0x1280000,
1288         GRCBASE_XCM = 0x1000000,
1289         GRCBASE_YCM = 0x1080000,
1290         GRCBASE_PCM = 0x1100000,
1291         GRCBASE_QM = 0x2f0000,
1292         GRCBASE_TM = 0x2c0000,
1293         GRCBASE_DORQ = 0x100000,
1294         GRCBASE_BRB = 0x340000,
1295         GRCBASE_SRC = 0x238000,
1296         GRCBASE_PRS = 0x1f0000,
1297         GRCBASE_TSDM = 0xfb0000,
1298         GRCBASE_MSDM = 0xfc0000,
1299         GRCBASE_USDM = 0xfd0000,
1300         GRCBASE_XSDM = 0xf80000,
1301         GRCBASE_YSDM = 0xf90000,
1302         GRCBASE_PSDM = 0xfa0000,
1303         GRCBASE_TSEM = 0x1700000,
1304         GRCBASE_MSEM = 0x1800000,
1305         GRCBASE_USEM = 0x1900000,
1306         GRCBASE_XSEM = 0x1400000,
1307         GRCBASE_YSEM = 0x1500000,
1308         GRCBASE_PSEM = 0x1600000,
1309         GRCBASE_RSS = 0x238800,
1310         GRCBASE_TMLD = 0x4d0000,
1311         GRCBASE_MULD = 0x4e0000,
1312         GRCBASE_YULD = 0x4c8000,
1313         GRCBASE_XYLD = 0x4c0000,
1314         GRCBASE_PRM = 0x230000,
1315         GRCBASE_PBF_PB1 = 0xda0000,
1316         GRCBASE_PBF_PB2 = 0xda4000,
1317         GRCBASE_RPB = 0x23c000,
1318         GRCBASE_BTB = 0xdb0000,
1319         GRCBASE_PBF = 0xd80000,
1320         GRCBASE_RDIF = 0x300000,
1321         GRCBASE_TDIF = 0x310000,
1322         GRCBASE_CDU = 0x580000,
1323         GRCBASE_CCFC = 0x2e0000,
1324         GRCBASE_TCFC = 0x2d0000,
1325         GRCBASE_IGU = 0x180000,
1326         GRCBASE_CAU = 0x1c0000,
1327         GRCBASE_UMAC = 0x51000,
1328         GRCBASE_XMAC = 0x210000,
1329         GRCBASE_DBG = 0x10000,
1330         GRCBASE_NIG = 0x500000,
1331         GRCBASE_WOL = 0x600000,
1332         GRCBASE_BMBN = 0x610000,
1333         GRCBASE_IPC = 0x20000,
1334         GRCBASE_NWM = 0x800000,
1335         GRCBASE_NWS = 0x700000,
1336         GRCBASE_MS = 0x6a0000,
1337         GRCBASE_PHY_PCIE = 0x620000,
1338         GRCBASE_LED = 0x6b8000,
1339         GRCBASE_MISC_AEU = 0x8000,
1340         GRCBASE_BAR0_MAP = 0x1c00000,
1341         MAX_BLOCK_ADDR
1342 };
1343
1344 enum block_id {
1345         BLOCK_GRC,
1346         BLOCK_MISCS,
1347         BLOCK_MISC,
1348         BLOCK_DBU,
1349         BLOCK_PGLUE_B,
1350         BLOCK_CNIG,
1351         BLOCK_CPMU,
1352         BLOCK_NCSI,
1353         BLOCK_OPTE,
1354         BLOCK_BMB,
1355         BLOCK_PCIE,
1356         BLOCK_MCP,
1357         BLOCK_MCP2,
1358         BLOCK_PSWHST,
1359         BLOCK_PSWHST2,
1360         BLOCK_PSWRD,
1361         BLOCK_PSWRD2,
1362         BLOCK_PSWWR,
1363         BLOCK_PSWWR2,
1364         BLOCK_PSWRQ,
1365         BLOCK_PSWRQ2,
1366         BLOCK_PGLCS,
1367         BLOCK_DMAE,
1368         BLOCK_PTU,
1369         BLOCK_TCM,
1370         BLOCK_MCM,
1371         BLOCK_UCM,
1372         BLOCK_XCM,
1373         BLOCK_YCM,
1374         BLOCK_PCM,
1375         BLOCK_QM,
1376         BLOCK_TM,
1377         BLOCK_DORQ,
1378         BLOCK_BRB,
1379         BLOCK_SRC,
1380         BLOCK_PRS,
1381         BLOCK_TSDM,
1382         BLOCK_MSDM,
1383         BLOCK_USDM,
1384         BLOCK_XSDM,
1385         BLOCK_YSDM,
1386         BLOCK_PSDM,
1387         BLOCK_TSEM,
1388         BLOCK_MSEM,
1389         BLOCK_USEM,
1390         BLOCK_XSEM,
1391         BLOCK_YSEM,
1392         BLOCK_PSEM,
1393         BLOCK_RSS,
1394         BLOCK_TMLD,
1395         BLOCK_MULD,
1396         BLOCK_YULD,
1397         BLOCK_XYLD,
1398         BLOCK_PRM,
1399         BLOCK_PBF_PB1,
1400         BLOCK_PBF_PB2,
1401         BLOCK_RPB,
1402         BLOCK_BTB,
1403         BLOCK_PBF,
1404         BLOCK_RDIF,
1405         BLOCK_TDIF,
1406         BLOCK_CDU,
1407         BLOCK_CCFC,
1408         BLOCK_TCFC,
1409         BLOCK_IGU,
1410         BLOCK_CAU,
1411         BLOCK_UMAC,
1412         BLOCK_XMAC,
1413         BLOCK_DBG,
1414         BLOCK_NIG,
1415         BLOCK_WOL,
1416         BLOCK_BMBN,
1417         BLOCK_IPC,
1418         BLOCK_NWM,
1419         BLOCK_NWS,
1420         BLOCK_MS,
1421         BLOCK_PHY_PCIE,
1422         BLOCK_LED,
1423         BLOCK_MISC_AEU,
1424         BLOCK_BAR0_MAP,
1425         MAX_BLOCK_ID
1426 };
1427
1428 /* binary debug buffer types */
1429 enum bin_dbg_buffer_type {
1430         BIN_BUF_DBG_MODE_TREE,
1431         BIN_BUF_DBG_DUMP_REG,
1432         BIN_BUF_DBG_DUMP_MEM,
1433         BIN_BUF_DBG_IDLE_CHK_REGS,
1434         BIN_BUF_DBG_IDLE_CHK_IMMS,
1435         BIN_BUF_DBG_IDLE_CHK_RULES,
1436         BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
1437         BIN_BUF_DBG_ATTN_BLOCKS,
1438         BIN_BUF_DBG_ATTN_REGS,
1439         BIN_BUF_DBG_ATTN_INDEXES,
1440         BIN_BUF_DBG_ATTN_NAME_OFFSETS,
1441         BIN_BUF_DBG_PARSING_STRINGS,
1442         MAX_BIN_DBG_BUFFER_TYPE
1443 };
1444
1445 /* Chip IDs */
1446 enum chip_ids {
1447         CHIP_RESERVED,
1448         CHIP_BB_B0,
1449         CHIP_RESERVED2,
1450         MAX_CHIP_IDS
1451 };
1452
1453 /* Attention bit mapping */
1454 struct dbg_attn_bit_mapping {
1455         __le16 data;
1456 #define DBG_ATTN_BIT_MAPPING_VAL_MASK                   0x7FFF
1457 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT                  0
1458 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK     0x1
1459 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT    15
1460 };
1461
1462 /* Attention block per-type data */
1463 struct dbg_attn_block_type_data {
1464         __le16 names_offset;
1465         __le16 reserved1;
1466         u8 num_regs;
1467         u8 reserved2;
1468         __le16 regs_offset;
1469 };
1470
1471 /* Block attentions */
1472 struct dbg_attn_block {
1473         struct dbg_attn_block_type_data per_type_data[2];
1474 };
1475
1476 /* Attention register result */
1477 struct dbg_attn_reg_result {
1478         __le32 data;
1479 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK    0xFFFFFF
1480 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT   0
1481 #define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_MASK   0xFF
1482 #define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_SHIFT  24
1483         __le16 attn_idx_offset;
1484         __le16 reserved;
1485         __le32 sts_val;
1486         __le32 mask_val;
1487 };
1488
1489 /* Attention block result */
1490 struct dbg_attn_block_result {
1491         u8 block_id;
1492         u8 data;
1493 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK    0x3
1494 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT   0
1495 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK     0x3F
1496 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT    2
1497         __le16 names_offset;
1498         struct dbg_attn_reg_result reg_results[15];
1499 };
1500
1501 /* mode header */
1502 struct dbg_mode_hdr {
1503         __le16 data;
1504 #define DBG_MODE_HDR_EVAL_MODE_MASK             0x1
1505 #define DBG_MODE_HDR_EVAL_MODE_SHIFT            0
1506 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK      0x7FFF
1507 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT     1
1508 };
1509
1510 /* Attention register */
1511 struct dbg_attn_reg {
1512         struct dbg_mode_hdr mode;
1513         __le16 attn_idx_offset;
1514         __le32 data;
1515 #define DBG_ATTN_REG_STS_ADDRESS_MASK   0xFFFFFF
1516 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT  0
1517 #define DBG_ATTN_REG_NUM_ATTN_IDX_MASK  0xFF
1518 #define DBG_ATTN_REG_NUM_ATTN_IDX_SHIFT 24
1519         __le32 sts_clr_address;
1520         __le32 mask_address;
1521 };
1522
1523 /* attention types */
1524 enum dbg_attn_type {
1525         ATTN_TYPE_INTERRUPT,
1526         ATTN_TYPE_PARITY,
1527         MAX_DBG_ATTN_TYPE
1528 };
1529
1530 /* Debug status codes */
1531 enum dbg_status {
1532         DBG_STATUS_OK,
1533         DBG_STATUS_APP_VERSION_NOT_SET,
1534         DBG_STATUS_UNSUPPORTED_APP_VERSION,
1535         DBG_STATUS_DBG_BLOCK_NOT_RESET,
1536         DBG_STATUS_INVALID_ARGS,
1537         DBG_STATUS_OUTPUT_ALREADY_SET,
1538         DBG_STATUS_INVALID_PCI_BUF_SIZE,
1539         DBG_STATUS_PCI_BUF_ALLOC_FAILED,
1540         DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
1541         DBG_STATUS_TOO_MANY_INPUTS,
1542         DBG_STATUS_INPUT_OVERLAP,
1543         DBG_STATUS_HW_ONLY_RECORDING,
1544         DBG_STATUS_STORM_ALREADY_ENABLED,
1545         DBG_STATUS_STORM_NOT_ENABLED,
1546         DBG_STATUS_BLOCK_ALREADY_ENABLED,
1547         DBG_STATUS_BLOCK_NOT_ENABLED,
1548         DBG_STATUS_NO_INPUT_ENABLED,
1549         DBG_STATUS_NO_FILTER_TRIGGER_64B,
1550         DBG_STATUS_FILTER_ALREADY_ENABLED,
1551         DBG_STATUS_TRIGGER_ALREADY_ENABLED,
1552         DBG_STATUS_TRIGGER_NOT_ENABLED,
1553         DBG_STATUS_CANT_ADD_CONSTRAINT,
1554         DBG_STATUS_TOO_MANY_TRIGGER_STATES,
1555         DBG_STATUS_TOO_MANY_CONSTRAINTS,
1556         DBG_STATUS_RECORDING_NOT_STARTED,
1557         DBG_STATUS_DATA_DIDNT_TRIGGER,
1558         DBG_STATUS_NO_DATA_RECORDED,
1559         DBG_STATUS_DUMP_BUF_TOO_SMALL,
1560         DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
1561         DBG_STATUS_UNKNOWN_CHIP,
1562         DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
1563         DBG_STATUS_BLOCK_IN_RESET,
1564         DBG_STATUS_INVALID_TRACE_SIGNATURE,
1565         DBG_STATUS_INVALID_NVRAM_BUNDLE,
1566         DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
1567         DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
1568         DBG_STATUS_NVRAM_READ_FAILED,
1569         DBG_STATUS_IDLE_CHK_PARSE_FAILED,
1570         DBG_STATUS_MCP_TRACE_BAD_DATA,
1571         DBG_STATUS_MCP_TRACE_NO_META,
1572         DBG_STATUS_MCP_COULD_NOT_HALT,
1573         DBG_STATUS_MCP_COULD_NOT_RESUME,
1574         DBG_STATUS_DMAE_FAILED,
1575         DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
1576         DBG_STATUS_IGU_FIFO_BAD_DATA,
1577         DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
1578         DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
1579         DBG_STATUS_REG_FIFO_BAD_DATA,
1580         DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
1581         DBG_STATUS_DBG_ARRAY_NOT_SET,
1582         MAX_DBG_STATUS
1583 };
1584
1585 /********************************/
1586 /* HSI Init Functions constants */
1587 /********************************/
1588
1589 /* Number of VLAN priorities */
1590 #define NUM_OF_VLAN_PRIORITIES  8
1591
1592 /* QM per-port init parameters */
1593 struct init_qm_port_params {
1594         u8 active;
1595         u8 active_phys_tcs;
1596         __le16 num_pbf_cmd_lines;
1597         __le16 num_btb_blocks;
1598         __le16 reserved;
1599 };
1600
1601 /* QM per-PQ init parameters */
1602 struct init_qm_pq_params {
1603         u8 vport_id;
1604         u8 tc_id;
1605         u8 wrr_group;
1606         u8 rl_valid;
1607 };
1608
1609 /* QM per-vport init parameters */
1610 struct init_qm_vport_params {
1611         __le32 vport_rl;
1612         __le16 vport_wfq;
1613         __le16 first_tx_pq_id[NUM_OF_TCS];
1614 };
1615
1616 /**************************************/
1617 /* Init Tool HSI constants and macros */
1618 /**************************************/
1619
1620 /* Width of GRC address in bits (addresses are specified in dwords) */
1621 #define GRC_ADDR_BITS   23
1622 #define MAX_GRC_ADDR    ((1 << GRC_ADDR_BITS) - 1)
1623
1624 /* indicates an init that should be applied to any phase ID */
1625 #define ANY_PHASE_ID    0xffff
1626
1627 /* Max size in dwords of a zipped array */
1628 #define MAX_ZIPPED_SIZE 8192
1629
1630 enum init_modes {
1631         MODE_RESERVED,
1632         MODE_BB_B0,
1633         MODE_RESERVED2,
1634         MODE_ASIC,
1635         MODE_RESERVED3,
1636         MODE_RESERVED4,
1637         MODE_RESERVED5,
1638         MODE_RESERVED6,
1639         MODE_SF,
1640         MODE_MF_SD,
1641         MODE_MF_SI,
1642         MODE_PORTS_PER_ENG_1,
1643         MODE_PORTS_PER_ENG_2,
1644         MODE_PORTS_PER_ENG_4,
1645         MODE_100G,
1646         MODE_40G,
1647         MODE_RESERVED7,
1648         MAX_INIT_MODES
1649 };
1650
1651 enum init_phases {
1652         PHASE_ENGINE,
1653         PHASE_PORT,
1654         PHASE_PF,
1655         PHASE_VF,
1656         PHASE_QM_PF,
1657         MAX_INIT_PHASES
1658 };
1659
1660 enum init_split_types {
1661         SPLIT_TYPE_NONE,
1662         SPLIT_TYPE_PORT,
1663         SPLIT_TYPE_PF,
1664         SPLIT_TYPE_PORT_PF,
1665         SPLIT_TYPE_VF,
1666         MAX_INIT_SPLIT_TYPES
1667 };
1668
1669 /* Binary buffer header */
1670 struct bin_buffer_hdr {
1671         __le32 offset;
1672         __le32 length;
1673 };
1674
1675 /* binary init buffer types */
1676 enum bin_init_buffer_type {
1677         BIN_BUF_FW_VER_INFO,
1678         BIN_BUF_INIT_CMD,
1679         BIN_BUF_INIT_VAL,
1680         BIN_BUF_INIT_MODE_TREE,
1681         BIN_BUF_IRO,
1682         MAX_BIN_INIT_BUFFER_TYPE
1683 };
1684
1685 /* init array header: raw */
1686 struct init_array_raw_hdr {
1687         __le32 data;
1688 #define INIT_ARRAY_RAW_HDR_TYPE_MASK    0xF
1689 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT   0
1690 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK  0xFFFFFFF
1691 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
1692 };
1693
1694 /* init array header: standard */
1695 struct init_array_standard_hdr {
1696         __le32 data;
1697 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK       0xF
1698 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT      0
1699 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK       0xFFFFFFF
1700 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT      4
1701 };
1702
1703 /* init array header: zipped */
1704 struct init_array_zipped_hdr {
1705         __le32 data;
1706 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK         0xF
1707 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT        0
1708 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK  0xFFFFFFF
1709 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
1710 };
1711
1712 /* init array header: pattern */
1713 struct init_array_pattern_hdr {
1714         __le32 data;
1715 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK                0xF
1716 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT               0
1717 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK        0xF
1718 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT       4
1719 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK         0xFFFFFF
1720 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT        8
1721 };
1722
1723 /* init array header union */
1724 union init_array_hdr {
1725         struct init_array_raw_hdr raw;
1726         struct init_array_standard_hdr standard;
1727         struct init_array_zipped_hdr zipped;
1728         struct init_array_pattern_hdr pattern;
1729 };
1730
1731 /* init array types */
1732 enum init_array_types {
1733         INIT_ARR_STANDARD,
1734         INIT_ARR_ZIPPED,
1735         INIT_ARR_PATTERN,
1736         MAX_INIT_ARRAY_TYPES
1737 };
1738
1739 /* init operation: callback */
1740 struct init_callback_op {
1741         __le32 op_data;
1742 #define INIT_CALLBACK_OP_OP_MASK        0xF
1743 #define INIT_CALLBACK_OP_OP_SHIFT       0
1744 #define INIT_CALLBACK_OP_RESERVED_MASK  0xFFFFFFF
1745 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
1746         __le16 callback_id;
1747         __le16 block_id;
1748 };
1749
1750 /* init operation: delay */
1751 struct init_delay_op {
1752         __le32 op_data;
1753 #define INIT_DELAY_OP_OP_MASK           0xF
1754 #define INIT_DELAY_OP_OP_SHIFT          0
1755 #define INIT_DELAY_OP_RESERVED_MASK     0xFFFFFFF
1756 #define INIT_DELAY_OP_RESERVED_SHIFT    4
1757         __le32 delay;
1758 };
1759
1760 /* init operation: if_mode */
1761 struct init_if_mode_op {
1762         __le32 op_data;
1763 #define INIT_IF_MODE_OP_OP_MASK                 0xF
1764 #define INIT_IF_MODE_OP_OP_SHIFT                0
1765 #define INIT_IF_MODE_OP_RESERVED1_MASK          0xFFF
1766 #define INIT_IF_MODE_OP_RESERVED1_SHIFT         4
1767 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK         0xFFFF
1768 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT        16
1769         __le16 reserved2;
1770         __le16 modes_buf_offset;
1771 };
1772
1773 /* init operation: if_phase */
1774 struct init_if_phase_op {
1775         __le32 op_data;
1776 #define INIT_IF_PHASE_OP_OP_MASK                0xF
1777 #define INIT_IF_PHASE_OP_OP_SHIFT               0
1778 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK       0x1
1779 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT      4
1780 #define INIT_IF_PHASE_OP_RESERVED1_MASK         0x7FF
1781 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT        5
1782 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK        0xFFFF
1783 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT       16
1784         __le32 phase_data;
1785 #define INIT_IF_PHASE_OP_PHASE_MASK             0xFF
1786 #define INIT_IF_PHASE_OP_PHASE_SHIFT            0
1787 #define INIT_IF_PHASE_OP_RESERVED2_MASK         0xFF
1788 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT        8
1789 #define INIT_IF_PHASE_OP_PHASE_ID_MASK          0xFFFF
1790 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT         16
1791 };
1792
1793 /* init mode operators */
1794 enum init_mode_ops {
1795         INIT_MODE_OP_NOT,
1796         INIT_MODE_OP_OR,
1797         INIT_MODE_OP_AND,
1798         MAX_INIT_MODE_OPS
1799 };
1800
1801 /* init operation: raw */
1802 struct init_raw_op {
1803         __le32 op_data;
1804 #define INIT_RAW_OP_OP_MASK             0xF
1805 #define INIT_RAW_OP_OP_SHIFT            0
1806 #define INIT_RAW_OP_PARAM1_MASK         0xFFFFFFF
1807 #define INIT_RAW_OP_PARAM1_SHIFT        4
1808         __le32 param2;
1809 };
1810
1811 /* init array params */
1812 struct init_op_array_params {
1813         __le16 size;
1814         __le16 offset;
1815 };
1816
1817 /* Write init operation arguments */
1818 union init_write_args {
1819         __le32 inline_val;
1820         __le32 zeros_count;
1821         __le32 array_offset;
1822         struct init_op_array_params runtime;
1823 };
1824
1825 /* init operation: write */
1826 struct init_write_op {
1827         __le32 data;
1828 #define INIT_WRITE_OP_OP_MASK           0xF
1829 #define INIT_WRITE_OP_OP_SHIFT          0
1830 #define INIT_WRITE_OP_SOURCE_MASK       0x7
1831 #define INIT_WRITE_OP_SOURCE_SHIFT      4
1832 #define INIT_WRITE_OP_RESERVED_MASK     0x1
1833 #define INIT_WRITE_OP_RESERVED_SHIFT    7
1834 #define INIT_WRITE_OP_WIDE_BUS_MASK     0x1
1835 #define INIT_WRITE_OP_WIDE_BUS_SHIFT    8
1836 #define INIT_WRITE_OP_ADDRESS_MASK      0x7FFFFF
1837 #define INIT_WRITE_OP_ADDRESS_SHIFT     9
1838         union init_write_args args;
1839 };
1840
1841 /* init operation: read */
1842 struct init_read_op {
1843         __le32 op_data;
1844 #define INIT_READ_OP_OP_MASK            0xF
1845 #define INIT_READ_OP_OP_SHIFT           0
1846 #define INIT_READ_OP_POLL_TYPE_MASK     0xF
1847 #define INIT_READ_OP_POLL_TYPE_SHIFT    4
1848 #define INIT_READ_OP_RESERVED_MASK      0x1
1849 #define INIT_READ_OP_RESERVED_SHIFT     8
1850 #define INIT_READ_OP_ADDRESS_MASK       0x7FFFFF
1851 #define INIT_READ_OP_ADDRESS_SHIFT      9
1852         __le32 expected_val;
1853
1854 };
1855
1856 /* Init operations union */
1857 union init_op {
1858         struct init_raw_op raw;
1859         struct init_write_op write;
1860         struct init_read_op read;
1861         struct init_if_mode_op if_mode;
1862         struct init_if_phase_op if_phase;
1863         struct init_callback_op callback;
1864         struct init_delay_op delay;
1865 };
1866
1867 /* Init command operation types */
1868 enum init_op_types {
1869         INIT_OP_READ,
1870         INIT_OP_WRITE,
1871         INIT_OP_IF_MODE,
1872         INIT_OP_IF_PHASE,
1873         INIT_OP_DELAY,
1874         INIT_OP_CALLBACK,
1875         MAX_INIT_OP_TYPES
1876 };
1877
1878 /* init polling types */
1879 enum init_poll_types {
1880         INIT_POLL_NONE,
1881         INIT_POLL_EQ,
1882         INIT_POLL_OR,
1883         INIT_POLL_AND,
1884         MAX_INIT_POLL_TYPES
1885 };
1886
1887 /* init source types */
1888 enum init_source_types {
1889         INIT_SRC_INLINE,
1890         INIT_SRC_ZEROS,
1891         INIT_SRC_ARRAY,
1892         INIT_SRC_RUNTIME,
1893         MAX_INIT_SOURCE_TYPES
1894 };
1895
1896 /* Internal RAM Offsets macro data */
1897 struct iro {
1898         __le32 base;
1899         __le16 m1;
1900         __le16 m2;
1901         __le16 m3;
1902         __le16 size;
1903 };
1904
1905 /**
1906  * @brief qed_dbg_print_attn - Prints attention registers values in the specified results struct.
1907  *
1908  * @param p_hwfn
1909  * @param results - Pointer to the attention read results
1910  *
1911  * @return error if one of the following holds:
1912  *      - the version wasn't set
1913  * Otherwise, returns ok.
1914  */
1915 enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
1916                                    struct dbg_attn_block_result *results);
1917
1918 #define MAX_NAME_LEN    16
1919
1920 /* Win 2 */
1921 #define GTT_BAR0_MAP_REG_IGU_CMD \
1922         0x00f000UL
1923
1924 /* Win 3 */
1925 #define GTT_BAR0_MAP_REG_TSDM_RAM \
1926         0x010000UL
1927
1928 /* Win 4 */
1929 #define GTT_BAR0_MAP_REG_MSDM_RAM \
1930         0x011000UL
1931
1932 /* Win 5 */
1933 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 \
1934         0x012000UL
1935
1936 /* Win 6 */
1937 #define GTT_BAR0_MAP_REG_USDM_RAM \
1938         0x013000UL
1939
1940 /* Win 7 */
1941 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 \
1942         0x014000UL
1943
1944 /* Win 8 */
1945 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 \
1946         0x015000UL
1947
1948 /* Win 9 */
1949 #define GTT_BAR0_MAP_REG_XSDM_RAM \
1950         0x016000UL
1951
1952 /* Win 10 */
1953 #define GTT_BAR0_MAP_REG_YSDM_RAM \
1954         0x017000UL
1955
1956 /* Win 11 */
1957 #define GTT_BAR0_MAP_REG_PSDM_RAM \
1958         0x018000UL
1959
1960 /**
1961  * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
1962  *
1963  * Returns the required host memory size in 4KB units.
1964  * Must be called before all QM init HSI functions.
1965  *
1966  * @param pf_id - physical function ID
1967  * @param num_pf_cids - number of connections used by this PF
1968  * @param num_vf_cids - number of connections used by VFs of this PF
1969  * @param num_tids - number of tasks used by this PF
1970  * @param num_pf_pqs - number of PQs used by this PF
1971  * @param num_vf_pqs - number of PQs used by VFs of this PF
1972  *
1973  * @return The required host memory size in 4KB units.
1974  */
1975 u32 qed_qm_pf_mem_size(u8 pf_id,
1976                        u32 num_pf_cids,
1977                        u32 num_vf_cids,
1978                        u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
1979
1980 struct qed_qm_common_rt_init_params {
1981         u8 max_ports_per_engine;
1982         u8 max_phys_tcs_per_port;
1983         bool pf_rl_en;
1984         bool pf_wfq_en;
1985         bool vport_rl_en;
1986         bool vport_wfq_en;
1987         struct init_qm_port_params *port_params;
1988 };
1989
1990 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
1991                           struct qed_qm_common_rt_init_params *p_params);
1992
1993 struct qed_qm_pf_rt_init_params {
1994         u8 port_id;
1995         u8 pf_id;
1996         u8 max_phys_tcs_per_port;
1997         bool is_first_pf;
1998         u32 num_pf_cids;
1999         u32 num_vf_cids;
2000         u32 num_tids;
2001         u16 start_pq;
2002         u16 num_pf_pqs;
2003         u16 num_vf_pqs;
2004         u8 start_vport;
2005         u8 num_vports;
2006         u8 pf_wfq;
2007         u32 pf_rl;
2008         struct init_qm_pq_params *pq_params;
2009         struct init_qm_vport_params *vport_params;
2010 };
2011
2012 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
2013         struct qed_ptt *p_ptt,
2014         struct qed_qm_pf_rt_init_params *p_params);
2015
2016 /**
2017  * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
2018  *
2019  * @param p_hwfn
2020  * @param p_ptt - ptt window used for writing the registers
2021  * @param pf_id - PF ID
2022  * @param pf_wfq - WFQ weight. Must be non-zero.
2023  *
2024  * @return 0 on success, -1 on error.
2025  */
2026 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
2027                     struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
2028
2029 /**
2030  * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
2031  *
2032  * @param p_hwfn
2033  * @param p_ptt - ptt window used for writing the registers
2034  * @param pf_id - PF ID
2035  * @param pf_rl - rate limit in Mb/sec units
2036  *
2037  * @return 0 on success, -1 on error.
2038  */
2039 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
2040                    struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
2041
2042 /**
2043  * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
2044  *
2045  * @param p_hwfn
2046  * @param p_ptt - ptt window used for writing the registers
2047  * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
2048  *        with the VPORT for each TC. This array is filled by
2049  *        qed_qm_pf_rt_init
2050  * @param vport_wfq - WFQ weight. Must be non-zero.
2051  *
2052  * @return 0 on success, -1 on error.
2053  */
2054 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
2055                        struct qed_ptt *p_ptt,
2056                        u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);
2057
2058 /**
2059  * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT
2060  *
2061  * @param p_hwfn
2062  * @param p_ptt - ptt window used for writing the registers
2063  * @param vport_id - VPORT ID
2064  * @param vport_rl - rate limit in Mb/sec units
2065  *
2066  * @return 0 on success, -1 on error.
2067  */
2068 int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
2069                       struct qed_ptt *p_ptt, u8 vport_id, u32 vport_rl);
2070 /**
2071  * @brief qed_send_qm_stop_cmd  Sends a stop command to the QM
2072  *
2073  * @param p_hwfn
2074  * @param p_ptt
2075  * @param is_release_cmd - true for release, false for stop.
2076  * @param is_tx_pq - true for Tx PQs, false for Other PQs.
2077  * @param start_pq - first PQ ID to stop
2078  * @param num_pqs - Number of PQs to stop, starting from start_pq.
2079  *
2080  * @return bool, true if successful, false if timeout occured while waiting for QM command done.
2081  */
2082 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
2083                           struct qed_ptt *p_ptt,
2084                           bool is_release_cmd,
2085                           bool is_tx_pq, u16 start_pq, u16 num_pqs);
2086
2087 /**
2088  * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
2089  *
2090  * @param p_ptt - ptt window used for writing the registers.
2091  * @param dest_port - vxlan destination udp port.
2092  */
2093 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
2094                              struct qed_ptt *p_ptt, u16 dest_port);
2095
2096 /**
2097  * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
2098  *
2099  * @param p_ptt - ptt window used for writing the registers.
2100  * @param vxlan_enable - vxlan enable flag.
2101  */
2102 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
2103                           struct qed_ptt *p_ptt, bool vxlan_enable);
2104
2105 /**
2106  * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
2107  *
2108  * @param p_ptt - ptt window used for writing the registers.
2109  * @param eth_gre_enable - eth GRE enable enable flag.
2110  * @param ip_gre_enable - IP GRE enable enable flag.
2111  */
2112 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
2113                         struct qed_ptt *p_ptt,
2114                         bool eth_gre_enable, bool ip_gre_enable);
2115
2116 /**
2117  * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
2118  *
2119  * @param p_ptt - ptt window used for writing the registers.
2120  * @param dest_port - geneve destination udp port.
2121  */
2122 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
2123                               struct qed_ptt *p_ptt, u16 dest_port);
2124
2125 /**
2126  * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
2127  *
2128  * @param p_ptt - ptt window used for writing the registers.
2129  * @param eth_geneve_enable - eth GENEVE enable enable flag.
2130  * @param ip_geneve_enable - IP GENEVE enable enable flag.
2131  */
2132 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
2133                            struct qed_ptt *p_ptt,
2134                            bool eth_geneve_enable, bool ip_geneve_enable);
2135
2136 #define YSTORM_FLOW_CONTROL_MODE_OFFSET                 (IRO[0].base)
2137 #define YSTORM_FLOW_CONTROL_MODE_SIZE                   (IRO[0].size)
2138 #define TSTORM_PORT_STAT_OFFSET(port_id) \
2139         (IRO[1].base + ((port_id) * IRO[1].m1))
2140 #define TSTORM_PORT_STAT_SIZE                           (IRO[1].size)
2141 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
2142         (IRO[3].base + ((vf_id) * IRO[3].m1))
2143 #define USTORM_VF_PF_CHANNEL_READY_SIZE                 (IRO[3].size)
2144 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
2145         (IRO[4].base + (pf_id) * IRO[4].m1)
2146 #define USTORM_FLR_FINAL_ACK_SIZE                       (IRO[4].size)
2147 #define USTORM_EQE_CONS_OFFSET(pf_id) \
2148         (IRO[5].base + ((pf_id) * IRO[5].m1))
2149 #define USTORM_EQE_CONS_SIZE                            (IRO[5].size)
2150 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
2151         (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
2152 #define USTORM_ETH_QUEUE_ZONE_SIZE                      (IRO[6].size)
2153 #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
2154         (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
2155 #define USTORM_COMMON_QUEUE_CONS_SIZE                   (IRO[7].size)
2156 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
2157         (IRO[18].base + ((stat_counter_id) * IRO[18].m1))
2158 #define MSTORM_QUEUE_STAT_SIZE                          (IRO[18].size)
2159 #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
2160         (IRO[19].base + ((queue_id) * IRO[19].m1))
2161 #define MSTORM_ETH_PF_PRODS_SIZE                        (IRO[19].size)
2162 #define MSTORM_TPA_TIMEOUT_US_OFFSET                    (IRO[20].base)
2163 #define MSTORM_TPA_TIMEOUT_US_SIZE                      (IRO[20].size)
2164 #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
2165         (IRO[21].base + ((pf_id) * IRO[21].m1))
2166 #define MSTORM_ETH_PF_STAT_SIZE                         (IRO[21].size)
2167 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
2168         (IRO[22].base + ((stat_counter_id) * IRO[22].m1))
2169 #define USTORM_QUEUE_STAT_SIZE                          (IRO[22].size)
2170 #define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
2171         (IRO[23].base + ((pf_id) * IRO[23].m1))
2172 #define USTORM_ETH_PF_STAT_SIZE                         (IRO[23].size)
2173 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
2174         (IRO[24].base + ((stat_counter_id) * IRO[24].m1))
2175 #define PSTORM_QUEUE_STAT_SIZE                          (IRO[24].size)
2176 #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
2177         (IRO[25].base + ((pf_id) * IRO[25].m1))
2178 #define PSTORM_ETH_PF_STAT_SIZE                         (IRO[25].size)
2179 #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethtype) \
2180         (IRO[26].base + ((ethtype) * IRO[26].m1))
2181 #define PSTORM_CTL_FRAME_ETHTYPE_SIZE                   (IRO[26].size)
2182 #define TSTORM_ETH_PRS_INPUT_OFFSET                     (IRO[27].base)
2183 #define TSTORM_ETH_PRS_INPUT_SIZE                       (IRO[27].size)
2184 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
2185         (IRO[28].base + ((pf_id) * IRO[28].m1))
2186 #define ETH_RX_RATE_LIMIT_SIZE                          (IRO[28].size)
2187 #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
2188         (IRO[29].base + ((queue_id) * IRO[29].m1))
2189 #define XSTORM_ETH_QUEUE_ZONE_SIZE                      (IRO[29].size)
2190
2191 static const struct iro iro_arr[46] = {
2192         {0x0, 0x0, 0x0, 0x0, 0x8},
2193         {0x4cb0, 0x78, 0x0, 0x0, 0x78},
2194         {0x6318, 0x20, 0x0, 0x0, 0x20},
2195         {0xb00, 0x8, 0x0, 0x0, 0x4},
2196         {0xa80, 0x8, 0x0, 0x0, 0x4},
2197         {0x0, 0x8, 0x0, 0x0, 0x2},
2198         {0x80, 0x8, 0x0, 0x0, 0x4},
2199         {0x84, 0x8, 0x0, 0x0, 0x2},
2200         {0x4bc0, 0x0, 0x0, 0x0, 0x78},
2201         {0x3df0, 0x0, 0x0, 0x0, 0x78},
2202         {0x29b0, 0x0, 0x0, 0x0, 0x78},
2203         {0x4c38, 0x0, 0x0, 0x0, 0x78},
2204         {0x4a48, 0x0, 0x0, 0x0, 0x78},
2205         {0x7e48, 0x0, 0x0, 0x0, 0x78},
2206         {0xa28, 0x8, 0x0, 0x0, 0x8},
2207         {0x60f8, 0x10, 0x0, 0x0, 0x10},
2208         {0xb820, 0x30, 0x0, 0x0, 0x30},
2209         {0x95b8, 0x30, 0x0, 0x0, 0x30},
2210         {0x4c18, 0x80, 0x0, 0x0, 0x40},
2211         {0x1f8, 0x4, 0x0, 0x0, 0x4},
2212         {0xc9a8, 0x0, 0x0, 0x0, 0x4},
2213         {0x4c58, 0x80, 0x0, 0x0, 0x20},
2214         {0x8050, 0x40, 0x0, 0x0, 0x30},
2215         {0xe770, 0x60, 0x0, 0x0, 0x60},
2216         {0x2b48, 0x80, 0x0, 0x0, 0x38},
2217         {0xdf88, 0x78, 0x0, 0x0, 0x78},
2218         {0x1f8, 0x4, 0x0, 0x0, 0x4},
2219         {0xacf0, 0x0, 0x0, 0x0, 0xf0},
2220         {0xade0, 0x8, 0x0, 0x0, 0x8},
2221         {0x1f8, 0x8, 0x0, 0x0, 0x8},
2222         {0xac0, 0x8, 0x0, 0x0, 0x8},
2223         {0x2578, 0x8, 0x0, 0x0, 0x8},
2224         {0x24f8, 0x8, 0x0, 0x0, 0x8},
2225         {0x0, 0x8, 0x0, 0x0, 0x8},
2226         {0x200, 0x10, 0x8, 0x0, 0x8},
2227         {0xb78, 0x10, 0x8, 0x0, 0x2},
2228         {0xd888, 0x38, 0x0, 0x0, 0x24},
2229         {0x12120, 0x10, 0x0, 0x0, 0x8},
2230         {0x11b20, 0x38, 0x0, 0x0, 0x18},
2231         {0xa8c0, 0x30, 0x0, 0x0, 0x10},
2232         {0x86f8, 0x28, 0x0, 0x0, 0x18},
2233         {0xeff8, 0x10, 0x0, 0x0, 0x10},
2234         {0xdd08, 0x48, 0x0, 0x0, 0x38},
2235         {0xf460, 0x20, 0x0, 0x0, 0x20},
2236         {0x2b80, 0x80, 0x0, 0x0, 0x10},
2237         {0x5000, 0x10, 0x0, 0x0, 0x10},
2238 };
2239
2240 /* Runtime array offsets */
2241 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
2242 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
2243 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
2244 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
2245 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
2246 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
2247 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
2248 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
2249 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
2250 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
2251 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
2252 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
2253 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
2254 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
2255 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
2256 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
2257 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
2258 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
2259 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
2260 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
2261 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
2262 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
2263 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
2264 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
2265 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
2266 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
2267 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
2268 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
2269 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
2270 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
2271 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
2272 #define CAU_REG_PI_MEMORY_RT_OFFSET 2233
2273 #define CAU_REG_PI_MEMORY_RT_SIZE 4416
2274 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
2275 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
2276 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
2277 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
2278 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
2279 #define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
2280 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
2281 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
2282 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
2283 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
2284 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
2285 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
2286 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
2287 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
2288 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
2289 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
2290 #define SRC_REG_FIRSTFREE_RT_OFFSET 6665
2291 #define SRC_REG_FIRSTFREE_RT_SIZE 2
2292 #define SRC_REG_LASTFREE_RT_OFFSET 6667
2293 #define SRC_REG_LASTFREE_RT_SIZE 2
2294 #define SRC_REG_COUNTFREE_RT_OFFSET 6669
2295 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
2296 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
2297 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
2298 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
2299 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
2300 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
2301 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676
2302 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677
2303 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678
2304 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679
2305 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680
2306 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681
2307 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682
2308 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683
2309 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684
2310 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685
2311 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686
2312 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687
2313 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688
2314 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
2315 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
2316 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691
2317 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692
2318 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693
2319 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694
2320 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695
2321 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696
2322 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697
2323 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698
2324 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699
2325 #define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6700
2326 #define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6701
2327 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6702
2328 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6703
2329 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6704
2330 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
2331 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 28704
2332 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28705
2333 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28706
2334 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28707
2335 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28708
2336 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28709
2337 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28710
2338 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28711
2339 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28712
2340 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28713
2341 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28714
2342 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
2343 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29130
2344 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
2345 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 29642
2346 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 29643
2347 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 29644
2348 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29645
2349 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29646
2350 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29647
2351 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29648
2352 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29649
2353 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29650
2354 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29651
2355 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29652
2356 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29653
2357 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29654
2358 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29655
2359 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29656
2360 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29657
2361 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29658
2362 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29659
2363 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29660
2364 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29661
2365 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29662
2366 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29663
2367 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29664
2368 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29665
2369 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29666
2370 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29667
2371 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29668
2372 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29669
2373 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29670
2374 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29671
2375 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29672
2376 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29673
2377 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29674
2378 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29675
2379 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29676
2380 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29677
2381 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29678
2382 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29679
2383 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29680
2384 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29681
2385 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29682
2386 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29683
2387 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29684
2388 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29685
2389 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29686
2390 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29687
2391 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29688
2392 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29689
2393 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29690
2394 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29691
2395 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29692
2396 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29693
2397 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29694
2398 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29695
2399 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29696
2400 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29697
2401 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29698
2402 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29699
2403 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29700
2404 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29701
2405 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29702
2406 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29703
2407 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29704
2408 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29705
2409 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29706
2410 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29707
2411 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29708
2412 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29709
2413 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
2414 #define QM_REG_VOQCRDLINE_RT_OFFSET 29837
2415 #define QM_REG_VOQCRDLINE_RT_SIZE 20
2416 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29857
2417 #define QM_REG_VOQINITCRDLINE_RT_SIZE 20
2418 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29877
2419 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29878
2420 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29879
2421 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29880
2422 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29881
2423 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29882
2424 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29883
2425 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29884
2426 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29885
2427 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29886
2428 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29887
2429 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29888
2430 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29889
2431 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29890
2432 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29891
2433 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29892
2434 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29893
2435 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29894
2436 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29895
2437 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29896
2438 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29897
2439 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29898
2440 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29899
2441 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29900
2442 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29901
2443 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29902
2444 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29903
2445 #define QM_REG_PQTX2PF_0_RT_OFFSET 29904
2446 #define QM_REG_PQTX2PF_1_RT_OFFSET 29905
2447 #define QM_REG_PQTX2PF_2_RT_OFFSET 29906
2448 #define QM_REG_PQTX2PF_3_RT_OFFSET 29907
2449 #define QM_REG_PQTX2PF_4_RT_OFFSET 29908
2450 #define QM_REG_PQTX2PF_5_RT_OFFSET 29909
2451 #define QM_REG_PQTX2PF_6_RT_OFFSET 29910
2452 #define QM_REG_PQTX2PF_7_RT_OFFSET 29911
2453 #define QM_REG_PQTX2PF_8_RT_OFFSET 29912
2454 #define QM_REG_PQTX2PF_9_RT_OFFSET 29913
2455 #define QM_REG_PQTX2PF_10_RT_OFFSET 29914
2456 #define QM_REG_PQTX2PF_11_RT_OFFSET 29915
2457 #define QM_REG_PQTX2PF_12_RT_OFFSET 29916
2458 #define QM_REG_PQTX2PF_13_RT_OFFSET 29917
2459 #define QM_REG_PQTX2PF_14_RT_OFFSET 29918
2460 #define QM_REG_PQTX2PF_15_RT_OFFSET 29919
2461 #define QM_REG_PQTX2PF_16_RT_OFFSET 29920
2462 #define QM_REG_PQTX2PF_17_RT_OFFSET 29921
2463 #define QM_REG_PQTX2PF_18_RT_OFFSET 29922
2464 #define QM_REG_PQTX2PF_19_RT_OFFSET 29923
2465 #define QM_REG_PQTX2PF_20_RT_OFFSET 29924
2466 #define QM_REG_PQTX2PF_21_RT_OFFSET 29925
2467 #define QM_REG_PQTX2PF_22_RT_OFFSET 29926
2468 #define QM_REG_PQTX2PF_23_RT_OFFSET 29927
2469 #define QM_REG_PQTX2PF_24_RT_OFFSET 29928
2470 #define QM_REG_PQTX2PF_25_RT_OFFSET 29929
2471 #define QM_REG_PQTX2PF_26_RT_OFFSET 29930
2472 #define QM_REG_PQTX2PF_27_RT_OFFSET 29931
2473 #define QM_REG_PQTX2PF_28_RT_OFFSET 29932
2474 #define QM_REG_PQTX2PF_29_RT_OFFSET 29933
2475 #define QM_REG_PQTX2PF_30_RT_OFFSET 29934
2476 #define QM_REG_PQTX2PF_31_RT_OFFSET 29935
2477 #define QM_REG_PQTX2PF_32_RT_OFFSET 29936
2478 #define QM_REG_PQTX2PF_33_RT_OFFSET 29937
2479 #define QM_REG_PQTX2PF_34_RT_OFFSET 29938
2480 #define QM_REG_PQTX2PF_35_RT_OFFSET 29939
2481 #define QM_REG_PQTX2PF_36_RT_OFFSET 29940
2482 #define QM_REG_PQTX2PF_37_RT_OFFSET 29941
2483 #define QM_REG_PQTX2PF_38_RT_OFFSET 29942
2484 #define QM_REG_PQTX2PF_39_RT_OFFSET 29943
2485 #define QM_REG_PQTX2PF_40_RT_OFFSET 29944
2486 #define QM_REG_PQTX2PF_41_RT_OFFSET 29945
2487 #define QM_REG_PQTX2PF_42_RT_OFFSET 29946
2488 #define QM_REG_PQTX2PF_43_RT_OFFSET 29947
2489 #define QM_REG_PQTX2PF_44_RT_OFFSET 29948
2490 #define QM_REG_PQTX2PF_45_RT_OFFSET 29949
2491 #define QM_REG_PQTX2PF_46_RT_OFFSET 29950
2492 #define QM_REG_PQTX2PF_47_RT_OFFSET 29951
2493 #define QM_REG_PQTX2PF_48_RT_OFFSET 29952
2494 #define QM_REG_PQTX2PF_49_RT_OFFSET 29953
2495 #define QM_REG_PQTX2PF_50_RT_OFFSET 29954
2496 #define QM_REG_PQTX2PF_51_RT_OFFSET 29955
2497 #define QM_REG_PQTX2PF_52_RT_OFFSET 29956
2498 #define QM_REG_PQTX2PF_53_RT_OFFSET 29957
2499 #define QM_REG_PQTX2PF_54_RT_OFFSET 29958
2500 #define QM_REG_PQTX2PF_55_RT_OFFSET 29959
2501 #define QM_REG_PQTX2PF_56_RT_OFFSET 29960
2502 #define QM_REG_PQTX2PF_57_RT_OFFSET 29961
2503 #define QM_REG_PQTX2PF_58_RT_OFFSET 29962
2504 #define QM_REG_PQTX2PF_59_RT_OFFSET 29963
2505 #define QM_REG_PQTX2PF_60_RT_OFFSET 29964
2506 #define QM_REG_PQTX2PF_61_RT_OFFSET 29965
2507 #define QM_REG_PQTX2PF_62_RT_OFFSET 29966
2508 #define QM_REG_PQTX2PF_63_RT_OFFSET 29967
2509 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 29968
2510 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 29969
2511 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 29970
2512 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 29971
2513 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 29972
2514 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 29973
2515 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 29974
2516 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 29975
2517 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 29976
2518 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 29977
2519 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 29978
2520 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 29979
2521 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 29980
2522 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 29981
2523 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 29982
2524 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 29983
2525 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29984
2526 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29985
2527 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29986
2528 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29987
2529 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29988
2530 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29989
2531 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29990
2532 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29991
2533 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29992
2534 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29993
2535 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29994
2536 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29995
2537 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29996
2538 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256
2539 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30252
2540 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
2541 #define QM_REG_RLGLBLCRD_RT_OFFSET 30508
2542 #define QM_REG_RLGLBLCRD_RT_SIZE 256
2543 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30764
2544 #define QM_REG_RLPFPERIOD_RT_OFFSET 30765
2545 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30766
2546 #define QM_REG_RLPFINCVAL_RT_OFFSET 30767
2547 #define QM_REG_RLPFINCVAL_RT_SIZE 16
2548 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30783
2549 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
2550 #define QM_REG_RLPFCRD_RT_OFFSET 30799
2551 #define QM_REG_RLPFCRD_RT_SIZE 16
2552 #define QM_REG_RLPFENABLE_RT_OFFSET 30815
2553 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30816
2554 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30817
2555 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16
2556 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30833
2557 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
2558 #define QM_REG_WFQPFCRD_RT_OFFSET 30849
2559 #define QM_REG_WFQPFCRD_RT_SIZE 160
2560 #define QM_REG_WFQPFENABLE_RT_OFFSET 31009
2561 #define QM_REG_WFQVPENABLE_RT_OFFSET 31010
2562 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 31011
2563 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512
2564 #define QM_REG_TXPQMAP_RT_OFFSET 31523
2565 #define QM_REG_TXPQMAP_RT_SIZE 512
2566 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 32035
2567 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512
2568 #define QM_REG_WFQVPCRD_RT_OFFSET 32547
2569 #define QM_REG_WFQVPCRD_RT_SIZE 512
2570 #define QM_REG_WFQVPMAP_RT_OFFSET 33059
2571 #define QM_REG_WFQVPMAP_RT_SIZE 512
2572 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33571
2573 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
2574 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33731
2575 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33732
2576 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33733
2577 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33734
2578 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33735
2579 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33736
2580 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33737
2581 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33738
2582 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
2583 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33742
2584 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
2585 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33746
2586 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
2587 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33750
2588 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33751
2589 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
2590 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33783
2591 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
2592 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33799
2593 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
2594 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33815
2595 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
2596 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33831
2597 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
2598 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33847
2599 #define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 33848
2600 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33849
2601 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33850
2602 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33851
2603 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33852
2604 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33853
2605 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33854
2606 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33855
2607 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33856
2608 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33857
2609 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33858
2610 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33859
2611 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33860
2612 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33861
2613 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33862
2614 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33863
2615 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33864
2616 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33865
2617 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33866
2618 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33867
2619 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33868
2620 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33869
2621 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33870
2622 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33871
2623 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33872
2624 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33873
2625 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33874
2626 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33875
2627 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33876
2628 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33877
2629 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33878
2630 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33879
2631 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33880
2632 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33881
2633 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33882
2634 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33883
2635 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33884
2636 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33885
2637 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33886
2638 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33887
2639 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33888
2640 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33889
2641 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33890
2642 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33891
2643 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33892
2644 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33893
2645 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33894
2646 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33895
2647 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33896
2648 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33897
2649 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33898
2650 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33899
2651 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33900
2652 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33901
2653 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33902
2654 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33903
2655 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33904
2656 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33905
2657 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33906
2658 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33907
2659 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33908
2660 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33909
2661 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33910
2662 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33911
2663 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33912
2664 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33913
2665 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33914
2666 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33915
2667 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33916
2668 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33917
2669 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33918
2670 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33919
2671 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33920
2672 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33921
2673 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33922
2674 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33923
2675 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 33924
2676
2677 #define RUNTIME_ARRAY_SIZE 33925
2678
2679 /* The eth storm context for the Tstorm */
2680 struct tstorm_eth_conn_st_ctx {
2681         __le32 reserved[4];
2682 };
2683
2684 /* The eth storm context for the Pstorm */
2685 struct pstorm_eth_conn_st_ctx {
2686         __le32 reserved[8];
2687 };
2688
2689 /* The eth storm context for the Xstorm */
2690 struct xstorm_eth_conn_st_ctx {
2691         __le32 reserved[60];
2692 };
2693
2694 struct xstorm_eth_conn_ag_ctx {
2695         u8 reserved0;
2696         u8 eth_state;
2697         u8 flags0;
2698 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK        0x1
2699 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT       0
2700 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK           0x1
2701 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT          1
2702 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK           0x1
2703 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT          2
2704 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK        0x1
2705 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT       3
2706 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK           0x1
2707 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT          4
2708 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK           0x1
2709 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT          5
2710 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK           0x1
2711 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT          6
2712 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK           0x1
2713 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT          7
2714                 u8 flags1;
2715 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK           0x1
2716 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT          0
2717 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK           0x1
2718 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT          1
2719 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK           0x1
2720 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT          2
2721 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK               0x1
2722 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT              3
2723 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK               0x1
2724 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT              4
2725 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK               0x1
2726 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT              5
2727 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK      0x1
2728 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT     6
2729 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK        0x1
2730 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT       7
2731         u8 flags2;
2732 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK         0x3
2733 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT                0
2734 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK         0x3
2735 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT                2
2736 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK         0x3
2737 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT                4
2738 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK         0x3
2739 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT                6
2740         u8 flags3;
2741 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK         0x3
2742 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT                0
2743 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK         0x3
2744 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT                2
2745 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK         0x3
2746 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT                4
2747 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK         0x3
2748 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT                6
2749                 u8 flags4;
2750 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK         0x3
2751 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT                0
2752 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK         0x3
2753 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT                2
2754 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK                0x3
2755 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT               4
2756 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK                0x3
2757 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT               6
2758         u8 flags5;
2759 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK                0x3
2760 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT               0
2761 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK                0x3
2762 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT               2
2763 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK                0x3
2764 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT               4
2765 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK                0x3
2766 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT               6
2767         u8 flags6;
2768 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK    0x3
2769 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT   0
2770 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK    0x3
2771 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT   2
2772 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK               0x3
2773 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT              4
2774 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK        0x3
2775 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT       6
2776         u8 flags7;
2777 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK            0x3
2778 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT           0
2779 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK          0x3
2780 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT         2
2781 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK           0x3
2782 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT          4
2783 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK               0x1
2784 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT              6
2785 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK               0x1
2786 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT              7
2787         u8 flags8;
2788 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK               0x1
2789 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT              0
2790 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK               0x1
2791 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT              1
2792 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK               0x1
2793 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT              2
2794 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK               0x1
2795 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT              3
2796 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK               0x1
2797 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT              4
2798 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK               0x1
2799 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT              5
2800 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK               0x1
2801 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT              6
2802 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK               0x1
2803 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT              7
2804         u8 flags9;
2805 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK              0x1
2806 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT             0
2807 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK              0x1
2808 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT             1
2809 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK              0x1
2810 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT             2
2811 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK              0x1
2812 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT             3
2813 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK              0x1
2814 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT             4
2815 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK              0x1
2816 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT             5
2817 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
2818 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
2819 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
2820 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
2821         u8 flags10;
2822 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK            0x1
2823 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT           0
2824 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK     0x1
2825 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT    1
2826 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK         0x1
2827 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT        2
2828 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK          0x1
2829 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT         3
2830 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK        0x1
2831 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT       4
2832 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
2833 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2834 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK          0x1
2835 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT         6
2836 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK          0x1
2837 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT         7
2838         u8 flags11;
2839 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK          0x1
2840 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT         0
2841 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK          0x1
2842 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT         1
2843 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK      0x1
2844 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT     2
2845 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK             0x1
2846 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT            3
2847 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK             0x1
2848 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT            4
2849 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK             0x1
2850 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT            5
2851 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK        0x1
2852 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT       6
2853 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK             0x1
2854 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT            7
2855         u8 flags12;
2856 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK            0x1
2857 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT           0
2858 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK            0x1
2859 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT           1
2860 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK        0x1
2861 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT       2
2862 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK        0x1
2863 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT       3
2864 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK            0x1
2865 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT           4
2866 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK            0x1
2867 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT           5
2868 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK            0x1
2869 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT           6
2870 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK            0x1
2871 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT           7
2872         u8 flags13;
2873 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK            0x1
2874 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT           0
2875 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK            0x1
2876 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT           1
2877 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK        0x1
2878 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT       2
2879 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK        0x1
2880 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT       3
2881 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK        0x1
2882 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT       4
2883 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK        0x1
2884 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT       5
2885 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK        0x1
2886 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT       6
2887 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK        0x1
2888 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT       7
2889         u8 flags14;
2890 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK    0x1
2891 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT   0
2892 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK  0x1
2893 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
2894 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
2895 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
2896 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
2897 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
2898 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK      0x1
2899 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT     4
2900 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK    0x1
2901 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT   5
2902 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK          0x3
2903 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT         6
2904         u8 edpm_event_id;
2905         __le16 physical_q0;
2906         __le16 quota;
2907         __le16 edpm_num_bds;
2908         __le16 tx_bd_cons;
2909         __le16 tx_bd_prod;
2910         __le16 tx_class;
2911         __le16 conn_dpi;
2912         u8 byte3;
2913         u8 byte4;
2914         u8 byte5;
2915         u8 byte6;
2916         __le32 reg0;
2917         __le32 reg1;
2918         __le32 reg2;
2919         __le32 reg3;
2920         __le32 reg4;
2921         __le32 reg5;
2922         __le32 reg6;
2923         __le16 word7;
2924         __le16 word8;
2925         __le16 word9;
2926         __le16 word10;
2927         __le32 reg7;
2928         __le32 reg8;
2929         __le32 reg9;
2930         u8 byte7;
2931         u8 byte8;
2932         u8 byte9;
2933         u8 byte10;
2934         u8 byte11;
2935         u8 byte12;
2936         u8 byte13;
2937         u8 byte14;
2938         u8 byte15;
2939         u8 byte16;
2940         __le16 word11;
2941         __le32 reg10;
2942         __le32 reg11;
2943         __le32 reg12;
2944         __le32 reg13;
2945         __le32 reg14;
2946         __le32 reg15;
2947         __le32 reg16;
2948         __le32 reg17;
2949         __le32 reg18;
2950         __le32 reg19;
2951         __le16 word12;
2952         __le16 word13;
2953         __le16 word14;
2954         __le16 word15;
2955 };
2956
2957 /* The eth storm context for the Ystorm */
2958 struct ystorm_eth_conn_st_ctx {
2959         __le32 reserved[8];
2960 };
2961
2962 struct ystorm_eth_conn_ag_ctx {
2963         u8 byte0;
2964         u8 state;
2965         u8 flags0;
2966 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK                0x1
2967 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT               0
2968 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK                0x1
2969 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT               1
2970 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK   0x3
2971 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT  2
2972 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK    0x3
2973 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT   4
2974 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK                 0x3
2975 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT                6
2976         u8 flags1;
2977 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK        0x1
2978 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT       0
2979 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK         0x1
2980 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT        1
2981 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK                       0x1
2982 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                      2
2983 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK                     0x1
2984 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT                    3
2985 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK                     0x1
2986 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT                    4
2987 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK                     0x1
2988 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT                    5
2989 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK                     0x1
2990 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT                    6
2991 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK                     0x1
2992 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT                    7
2993         u8 tx_q0_int_coallecing_timeset;
2994         u8 byte3;
2995         __le16 word0;
2996         __le32 terminate_spqe;
2997         __le32 reg1;
2998         __le16 tx_bd_cons_upd;
2999         __le16 word2;
3000         __le16 word3;
3001         __le16 word4;
3002         __le32 reg2;
3003         __le32 reg3;
3004 };
3005
3006 struct tstorm_eth_conn_ag_ctx {
3007         u8 byte0;
3008         u8 byte1;
3009         u8 flags0;
3010 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK                0x1
3011 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT               0
3012 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK                0x1
3013 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT               1
3014 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK                0x1
3015 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT               2
3016 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK                0x1
3017 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT               3
3018 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK                0x1
3019 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT               4
3020 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK                0x1
3021 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT               5
3022 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK                 0x3
3023 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT                6
3024         u8 flags1;
3025 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK                 0x3
3026 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT                0
3027 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK                 0x3
3028 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT                2
3029 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK                 0x3
3030 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT                4
3031 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK                 0x3
3032 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT                6
3033         u8 flags2;
3034 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK                 0x3
3035 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT                0
3036 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK                 0x3
3037 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT                2
3038 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK                 0x3
3039 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT                4
3040 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK                 0x3
3041 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT                6
3042         u8 flags3;
3043 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK                 0x3
3044 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT                0
3045 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK                0x3
3046 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT               2
3047 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK               0x1
3048 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT              4
3049 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK               0x1
3050 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT              5
3051 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK               0x1
3052 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT              6
3053 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK               0x1
3054 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT              7
3055         u8 flags4;
3056 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK               0x1
3057 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT              0
3058 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK               0x1
3059 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT              1
3060 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK               0x1
3061 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT              2
3062 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK               0x1
3063 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT              3
3064 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK               0x1
3065 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT              4
3066 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK               0x1
3067 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT              5
3068 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK              0x1
3069 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT             6
3070 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK             0x1
3071 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT            7
3072         u8 flags5;
3073 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK             0x1
3074 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT            0
3075 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK             0x1
3076 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT            1
3077 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK             0x1
3078 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT            2
3079 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK             0x1
3080 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT            3
3081 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK             0x1
3082 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT            4
3083 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK            0x1
3084 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT           5
3085 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK             0x1
3086 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT            6
3087 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK             0x1
3088 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT            7
3089         __le32 reg0;
3090         __le32 reg1;
3091         __le32 reg2;
3092         __le32 reg3;
3093         __le32 reg4;
3094         __le32 reg5;
3095         __le32 reg6;
3096         __le32 reg7;
3097         __le32 reg8;
3098         u8 byte2;
3099         u8 byte3;
3100         __le16 rx_bd_cons;
3101         u8 byte4;
3102         u8 byte5;
3103         __le16 rx_bd_prod;
3104         __le16 word2;
3105         __le16 word3;
3106         __le32 reg9;
3107         __le32 reg10;
3108 };
3109
3110 struct ustorm_eth_conn_ag_ctx {
3111         u8 byte0;
3112         u8 byte1;
3113         u8 flags0;
3114 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK                        0x1
3115 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT                       0
3116 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK                        0x1
3117 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT                       1
3118 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK         0x3
3119 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT        2
3120 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK         0x3
3121 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT        4
3122 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK                         0x3
3123 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT                        6
3124         u8 flags1;
3125 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK                         0x3
3126 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT                        0
3127 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK                   0x3
3128 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT                  2
3129 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK                   0x3
3130 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT                  4
3131 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK           0x3
3132 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT          6
3133         u8 flags2;
3134 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK      0x1
3135 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT     0
3136 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK      0x1
3137 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT     1
3138 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK                       0x1
3139 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                      2
3140 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK                       0x1
3141 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT                      3
3142 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK                0x1
3143 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT               4
3144 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK                0x1
3145 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT               5
3146 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK        0x1
3147 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT       6
3148 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK                     0x1
3149 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT                    7
3150         u8 flags3;
3151 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK                     0x1
3152 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT                    0
3153 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK                     0x1
3154 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT                    1
3155 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK                     0x1
3156 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT                    2
3157 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK                     0x1
3158 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT                    3
3159 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK                     0x1
3160 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT                    4
3161 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK                     0x1
3162 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT                    5
3163 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK                     0x1
3164 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT                    6
3165 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK                     0x1
3166 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT                    7
3167         u8 byte2;
3168         u8 byte3;
3169         __le16 word0;
3170         __le16 tx_bd_cons;
3171         __le32 reg0;
3172         __le32 reg1;
3173         __le32 reg2;
3174         __le32 tx_int_coallecing_timeset;
3175         __le16 tx_drv_bd_cons;
3176         __le16 rx_drv_cqe_cons;
3177 };
3178
3179 /* The eth storm context for the Ustorm */
3180 struct ustorm_eth_conn_st_ctx {
3181         __le32 reserved[40];
3182 };
3183
3184 /* The eth storm context for the Mstorm */
3185 struct mstorm_eth_conn_st_ctx {
3186         __le32 reserved[8];
3187 };
3188
3189 /* eth connection context */
3190 struct eth_conn_context {
3191         struct tstorm_eth_conn_st_ctx tstorm_st_context;
3192         struct regpair tstorm_st_padding[2];
3193         struct pstorm_eth_conn_st_ctx pstorm_st_context;
3194         struct xstorm_eth_conn_st_ctx xstorm_st_context;
3195         struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
3196         struct ystorm_eth_conn_st_ctx ystorm_st_context;
3197         struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
3198         struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
3199         struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
3200         struct ustorm_eth_conn_st_ctx ustorm_st_context;
3201         struct mstorm_eth_conn_st_ctx mstorm_st_context;
3202 };
3203
3204 /* opcodes for the event ring */
3205 enum eth_event_opcode {
3206         ETH_EVENT_UNUSED,
3207         ETH_EVENT_VPORT_START,
3208         ETH_EVENT_VPORT_UPDATE,
3209         ETH_EVENT_VPORT_STOP,
3210         ETH_EVENT_TX_QUEUE_START,
3211         ETH_EVENT_TX_QUEUE_STOP,
3212         ETH_EVENT_RX_QUEUE_START,
3213         ETH_EVENT_RX_QUEUE_UPDATE,
3214         ETH_EVENT_RX_QUEUE_STOP,
3215         ETH_EVENT_FILTERS_UPDATE,
3216         ETH_EVENT_RESERVED,
3217         ETH_EVENT_RESERVED2,
3218         ETH_EVENT_RESERVED3,
3219         ETH_EVENT_RX_ADD_UDP_FILTER,
3220         ETH_EVENT_RX_DELETE_UDP_FILTER,
3221         ETH_EVENT_RESERVED4,
3222         ETH_EVENT_RESERVED5,
3223         MAX_ETH_EVENT_OPCODE
3224 };
3225
3226 /* Classify rule types in E2/E3 */
3227 enum eth_filter_action {
3228         ETH_FILTER_ACTION_UNUSED,
3229         ETH_FILTER_ACTION_REMOVE,
3230         ETH_FILTER_ACTION_ADD,
3231         ETH_FILTER_ACTION_REMOVE_ALL,
3232         MAX_ETH_FILTER_ACTION
3233 };
3234
3235 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
3236 struct eth_filter_cmd {
3237         u8 type;
3238         u8 vport_id;
3239         u8 action;
3240         u8 reserved0;
3241         __le32 vni;
3242         __le16 mac_lsb;
3243         __le16 mac_mid;
3244         __le16 mac_msb;
3245         __le16 vlan_id;
3246 };
3247
3248 /*      $$KEEP_ENDIANNESS$$ */
3249 struct eth_filter_cmd_header {
3250         u8 rx;
3251         u8 tx;
3252         u8 cmd_cnt;
3253         u8 assert_on_error;
3254         u8 reserved1[4];
3255 };
3256
3257 /* Ethernet filter types: mac/vlan/pair */
3258 enum eth_filter_type {
3259         ETH_FILTER_TYPE_UNUSED,
3260         ETH_FILTER_TYPE_MAC,
3261         ETH_FILTER_TYPE_VLAN,
3262         ETH_FILTER_TYPE_PAIR,
3263         ETH_FILTER_TYPE_INNER_MAC,
3264         ETH_FILTER_TYPE_INNER_VLAN,
3265         ETH_FILTER_TYPE_INNER_PAIR,
3266         ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
3267         ETH_FILTER_TYPE_MAC_VNI_PAIR,
3268         ETH_FILTER_TYPE_VNI,
3269         MAX_ETH_FILTER_TYPE
3270 };
3271
3272 /* Ethernet Ramrod Command IDs */
3273 enum eth_ramrod_cmd_id {
3274         ETH_RAMROD_UNUSED,
3275         ETH_RAMROD_VPORT_START,
3276         ETH_RAMROD_VPORT_UPDATE,
3277         ETH_RAMROD_VPORT_STOP,
3278         ETH_RAMROD_RX_QUEUE_START,
3279         ETH_RAMROD_RX_QUEUE_STOP,
3280         ETH_RAMROD_TX_QUEUE_START,
3281         ETH_RAMROD_TX_QUEUE_STOP,
3282         ETH_RAMROD_FILTERS_UPDATE,
3283         ETH_RAMROD_RX_QUEUE_UPDATE,
3284         ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
3285         ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
3286         ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
3287         ETH_RAMROD_RX_ADD_UDP_FILTER,
3288         ETH_RAMROD_RX_DELETE_UDP_FILTER,
3289         ETH_RAMROD_RX_CREATE_GFT_ACTION,
3290         ETH_RAMROD_GFT_UPDATE_FILTER,
3291         MAX_ETH_RAMROD_CMD_ID
3292 };
3293
3294 /* return code from eth sp ramrods */
3295 struct eth_return_code {
3296         u8 value;
3297 #define ETH_RETURN_CODE_ERR_CODE_MASK   0x1F
3298 #define ETH_RETURN_CODE_ERR_CODE_SHIFT  0
3299 #define ETH_RETURN_CODE_RESERVED_MASK   0x3
3300 #define ETH_RETURN_CODE_RESERVED_SHIFT  5
3301 #define ETH_RETURN_CODE_RX_TX_MASK      0x1
3302 #define ETH_RETURN_CODE_RX_TX_SHIFT     7
3303 };
3304
3305 /* What to do in case an error occurs */
3306 enum eth_tx_err {
3307         ETH_TX_ERR_DROP,
3308         ETH_TX_ERR_ASSERT_MALICIOUS,
3309         MAX_ETH_TX_ERR
3310 };
3311
3312 /* Array of the different error type behaviors */
3313 struct eth_tx_err_vals {
3314         __le16 values;
3315 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK                  0x1
3316 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT                 0
3317 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK                   0x1
3318 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT                  1
3319 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK                  0x1
3320 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT                 2
3321 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK                0x1
3322 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT               3
3323 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK        0x1
3324 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT       4
3325 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK                      0x1
3326 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT                     5
3327 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK              0x1
3328 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT             6
3329 #define ETH_TX_ERR_VALS_RESERVED_MASK                           0x1FF
3330 #define ETH_TX_ERR_VALS_RESERVED_SHIFT                          7
3331 };
3332
3333 /* vport rss configuration data */
3334 struct eth_vport_rss_config {
3335         __le16 capabilities;
3336 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK               0x1
3337 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT              0
3338 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK               0x1
3339 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT              1
3340 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK           0x1
3341 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT          2
3342 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK           0x1
3343 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT          3
3344 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK           0x1
3345 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT          4
3346 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK           0x1
3347 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT          5
3348 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK         0x1
3349 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT        6
3350 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK                     0x1FF
3351 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT                    7
3352         u8 rss_id;
3353         u8 rss_mode;
3354         u8 update_rss_key;
3355         u8 update_rss_ind_table;
3356         u8 update_rss_capabilities;
3357         u8 tbl_size;
3358         __le32 reserved2[2];
3359         __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
3360
3361         __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
3362         __le32 reserved3[2];
3363 };
3364
3365 /* eth vport RSS mode */
3366 enum eth_vport_rss_mode {
3367         ETH_VPORT_RSS_MODE_DISABLED,
3368         ETH_VPORT_RSS_MODE_REGULAR,
3369         MAX_ETH_VPORT_RSS_MODE
3370 };
3371
3372 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
3373 struct eth_vport_rx_mode {
3374         __le16 state;
3375 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK           0x1
3376 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT          0
3377 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK         0x1
3378 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT        1
3379 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK   0x1
3380 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT  2
3381 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK           0x1
3382 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT          3
3383 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK         0x1
3384 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT        4
3385 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK         0x1
3386 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT        5
3387 #define ETH_VPORT_RX_MODE_RESERVED1_MASK                0x3FF
3388 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT               6
3389         __le16 reserved2[3];
3390 };
3391
3392 /* Command for setting tpa parameters */
3393 struct eth_vport_tpa_param {
3394         u8 tpa_ipv4_en_flg;
3395         u8 tpa_ipv6_en_flg;
3396         u8 tpa_ipv4_tunn_en_flg;
3397         u8 tpa_ipv6_tunn_en_flg;
3398         u8 tpa_pkt_split_flg;
3399         u8 tpa_hdr_data_split_flg;
3400         u8 tpa_gro_consistent_flg;
3401
3402         u8 tpa_max_aggs_num;
3403
3404         __le16 tpa_max_size;
3405         __le16 tpa_min_size_to_start;
3406
3407         __le16 tpa_min_size_to_cont;
3408         u8 max_buff_num;
3409         u8 reserved;
3410 };
3411
3412 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
3413 struct eth_vport_tx_mode {
3414         __le16 state;
3415 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK           0x1
3416 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT          0
3417 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK         0x1
3418 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT        1
3419 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK           0x1
3420 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT          2
3421 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK         0x1
3422 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT        3
3423 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK         0x1
3424 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT        4
3425 #define ETH_VPORT_TX_MODE_RESERVED1_MASK                0x7FF
3426 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT               5
3427         __le16 reserved2[3];
3428 };
3429
3430 /* Ramrod data for rx queue start ramrod */
3431 struct rx_queue_start_ramrod_data {
3432         __le16 rx_queue_id;
3433         __le16 num_of_pbl_pages;
3434         __le16 bd_max_bytes;
3435         __le16 sb_id;
3436         u8 sb_index;
3437         u8 vport_id;
3438         u8 default_rss_queue_flg;
3439         u8 complete_cqe_flg;
3440         u8 complete_event_flg;
3441         u8 stats_counter_id;
3442         u8 pin_context;
3443         u8 pxp_tph_valid_bd;
3444         u8 pxp_tph_valid_pkt;
3445         u8 pxp_st_hint;
3446
3447         __le16 pxp_st_index;
3448         u8 pmd_mode;
3449
3450         u8 notify_en;
3451         u8 toggle_val;
3452
3453         u8 vf_rx_prod_index;
3454
3455         u8 reserved[6];
3456         __le16 reserved1;
3457         struct regpair cqe_pbl_addr;
3458         struct regpair bd_base;
3459         struct regpair reserved2;
3460 };
3461
3462 /* Ramrod data for rx queue start ramrod */
3463 struct rx_queue_stop_ramrod_data {
3464         __le16 rx_queue_id;
3465         u8 complete_cqe_flg;
3466         u8 complete_event_flg;
3467         u8 vport_id;
3468         u8 reserved[3];
3469 };
3470
3471 /* Ramrod data for rx queue update ramrod */
3472 struct rx_queue_update_ramrod_data {
3473         __le16 rx_queue_id;
3474         u8 complete_cqe_flg;
3475         u8 complete_event_flg;
3476         u8 vport_id;
3477         u8 reserved[4];
3478         u8 reserved1;
3479         u8 reserved2;
3480         u8 reserved3;
3481         __le16 reserved4;
3482         __le16 reserved5;
3483         struct regpair reserved6;
3484 };
3485
3486 /* Ramrod data for rx Add UDP Filter */
3487 struct rx_udp_filter_data {
3488         __le16 action_icid;
3489         __le16 vlan_id;
3490         u8 ip_type;
3491         u8 tenant_id_exists;
3492         __le16 reserved1;
3493         __le32 ip_dst_addr[4];
3494         __le32 ip_src_addr[4];
3495         __le16 udp_dst_port;
3496         __le16 udp_src_port;
3497         __le32 tenant_id;
3498 };
3499
3500 /* Ramrod data for rx queue start ramrod */
3501 struct tx_queue_start_ramrod_data {
3502         __le16 sb_id;
3503         u8 sb_index;
3504         u8 vport_id;
3505         u8 reserved0;
3506         u8 stats_counter_id;
3507         __le16 qm_pq_id;
3508         u8 flags;
3509 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK   0x1
3510 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT  0
3511 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK       0x1
3512 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT      1
3513 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK       0x1
3514 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT      2
3515 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK                0x1
3516 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT               3
3517 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK               0x1
3518 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT              4
3519 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK             0x1
3520 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT            5
3521 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK               0x3
3522 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT              6
3523         u8 pxp_st_hint;
3524         u8 pxp_tph_valid_bd;
3525         u8 pxp_tph_valid_pkt;
3526         __le16 pxp_st_index;
3527         __le16 comp_agg_size;
3528         __le16 queue_zone_id;
3529         __le16 test_dup_count;
3530         __le16 pbl_size;
3531         __le16 tx_queue_id;
3532
3533         struct regpair pbl_base_addr;
3534         struct regpair bd_cons_address;
3535 };
3536
3537 /* Ramrod data for tx queue stop ramrod */
3538 struct tx_queue_stop_ramrod_data {
3539         __le16 reserved[4];
3540 };
3541
3542 /* Ramrod data for vport update ramrod */
3543 struct vport_filter_update_ramrod_data {
3544         struct eth_filter_cmd_header filter_cmd_hdr;
3545         struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
3546 };
3547
3548 /* Ramrod data for vport start ramrod */
3549 struct vport_start_ramrod_data {
3550         u8 vport_id;
3551         u8 sw_fid;
3552         __le16 mtu;
3553         u8 drop_ttl0_en;
3554         u8 inner_vlan_removal_en;
3555         struct eth_vport_rx_mode rx_mode;
3556         struct eth_vport_tx_mode tx_mode;
3557         struct eth_vport_tpa_param tpa_param;
3558         __le16 default_vlan;
3559         u8 tx_switching_en;
3560         u8 anti_spoofing_en;
3561
3562         u8 default_vlan_en;
3563
3564         u8 handle_ptp_pkts;
3565         u8 silent_vlan_removal_en;
3566         u8 untagged;
3567         struct eth_tx_err_vals tx_err_behav;
3568
3569         u8 zero_placement_offset;
3570         u8 ctl_frame_mac_check_en;
3571         u8 ctl_frame_ethtype_check_en;
3572         u8 reserved[5];
3573 };
3574
3575 /* Ramrod data for vport stop ramrod */
3576 struct vport_stop_ramrod_data {
3577         u8 vport_id;
3578         u8 reserved[7];
3579 };
3580
3581 /* Ramrod data for vport update ramrod */
3582 struct vport_update_ramrod_data_cmn {
3583         u8 vport_id;
3584         u8 update_rx_active_flg;
3585         u8 rx_active_flg;
3586         u8 update_tx_active_flg;
3587         u8 tx_active_flg;
3588         u8 update_rx_mode_flg;
3589         u8 update_tx_mode_flg;
3590         u8 update_approx_mcast_flg;
3591
3592         u8 update_rss_flg;
3593         u8 update_inner_vlan_removal_en_flg;
3594
3595         u8 inner_vlan_removal_en;
3596         u8 update_tpa_param_flg;
3597         u8 update_tpa_en_flg;
3598         u8 update_tx_switching_en_flg;
3599
3600         u8 tx_switching_en;
3601         u8 update_anti_spoofing_en_flg;
3602
3603         u8 anti_spoofing_en;
3604         u8 update_handle_ptp_pkts;
3605
3606         u8 handle_ptp_pkts;
3607         u8 update_default_vlan_en_flg;
3608
3609         u8 default_vlan_en;
3610
3611         u8 update_default_vlan_flg;
3612
3613         __le16 default_vlan;
3614         u8 update_accept_any_vlan_flg;
3615
3616         u8 accept_any_vlan;
3617         u8 silent_vlan_removal_en;
3618         u8 update_mtu_flg;
3619
3620         __le16 mtu;
3621         u8 reserved[2];
3622 };
3623
3624 struct vport_update_ramrod_mcast {
3625         __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
3626 };
3627
3628 /* Ramrod data for vport update ramrod */
3629 struct vport_update_ramrod_data {
3630         struct vport_update_ramrod_data_cmn common;
3631
3632         struct eth_vport_rx_mode rx_mode;
3633         struct eth_vport_tx_mode tx_mode;
3634         struct eth_vport_tpa_param tpa_param;
3635         struct vport_update_ramrod_mcast approx_mcast;
3636         struct eth_vport_rss_config rss_config;
3637 };
3638
3639 struct mstorm_rdma_task_st_ctx {
3640         struct regpair temp[4];
3641 };
3642
3643 struct rdma_close_func_ramrod_data {
3644         u8 cnq_start_offset;
3645         u8 num_cnqs;
3646         u8 vf_id;
3647         u8 vf_valid;
3648         u8 reserved[4];
3649 };
3650
3651 struct rdma_cnq_params {
3652         __le16 sb_num;
3653         u8 sb_index;
3654         u8 num_pbl_pages;
3655         __le32 reserved;
3656         struct regpair pbl_base_addr;
3657         __le16 queue_zone_num;
3658         u8 reserved1[6];
3659 };
3660
3661 struct rdma_create_cq_ramrod_data {
3662         struct regpair cq_handle;
3663         struct regpair pbl_addr;
3664         __le32 max_cqes;
3665         __le16 pbl_num_pages;
3666         __le16 dpi;
3667         u8 is_two_level_pbl;
3668         u8 cnq_id;
3669         u8 pbl_log_page_size;
3670         u8 toggle_bit;
3671         __le16 int_timeout;
3672         __le16 reserved1;
3673 };
3674
3675 struct rdma_deregister_tid_ramrod_data {
3676         __le32 itid;
3677         __le32 reserved;
3678 };
3679
3680 struct rdma_destroy_cq_output_params {
3681         __le16 cnq_num;
3682         __le16 reserved0;
3683         __le32 reserved1;
3684 };
3685
3686 struct rdma_destroy_cq_ramrod_data {
3687         struct regpair output_params_addr;
3688 };
3689
3690 enum rdma_event_opcode {
3691         RDMA_EVENT_UNUSED,
3692         RDMA_EVENT_FUNC_INIT,
3693         RDMA_EVENT_FUNC_CLOSE,
3694         RDMA_EVENT_REGISTER_MR,
3695         RDMA_EVENT_DEREGISTER_MR,
3696         RDMA_EVENT_CREATE_CQ,
3697         RDMA_EVENT_RESIZE_CQ,
3698         RDMA_EVENT_DESTROY_CQ,
3699         RDMA_EVENT_CREATE_SRQ,
3700         RDMA_EVENT_MODIFY_SRQ,
3701         RDMA_EVENT_DESTROY_SRQ,
3702         MAX_RDMA_EVENT_OPCODE
3703 };
3704
3705 enum rdma_fw_return_code {
3706         RDMA_RETURN_OK = 0,
3707         RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
3708         RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
3709         RDMA_RETURN_RESIZE_CQ_ERR,
3710         RDMA_RETURN_NIG_DRAIN_REQ,
3711         MAX_RDMA_FW_RETURN_CODE
3712 };
3713
3714 struct rdma_init_func_hdr {
3715         u8 cnq_start_offset;
3716         u8 num_cnqs;
3717         u8 cq_ring_mode;
3718         u8 cnp_vlan_priority;
3719         __le32 cnp_send_timeout;
3720         u8 cnp_dscp;
3721         u8 vf_id;
3722         u8 vf_valid;
3723         u8 reserved[5];
3724 };
3725
3726 struct rdma_init_func_ramrod_data {
3727         struct rdma_init_func_hdr params_header;
3728         struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
3729 };
3730
3731 enum rdma_ramrod_cmd_id {
3732         RDMA_RAMROD_UNUSED,
3733         RDMA_RAMROD_FUNC_INIT,
3734         RDMA_RAMROD_FUNC_CLOSE,
3735         RDMA_RAMROD_REGISTER_MR,
3736         RDMA_RAMROD_DEREGISTER_MR,
3737         RDMA_RAMROD_CREATE_CQ,
3738         RDMA_RAMROD_RESIZE_CQ,
3739         RDMA_RAMROD_DESTROY_CQ,
3740         RDMA_RAMROD_CREATE_SRQ,
3741         RDMA_RAMROD_MODIFY_SRQ,
3742         RDMA_RAMROD_DESTROY_SRQ,
3743         MAX_RDMA_RAMROD_CMD_ID
3744 };
3745
3746 struct rdma_register_tid_ramrod_data {
3747         __le32 flags;
3748 #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_MASK             0x3FFFF
3749 #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_SHIFT            0
3750 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK      0x1F
3751 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT     18
3752 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK      0x1
3753 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT     23
3754 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK         0x1
3755 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT        24
3756 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK             0x1
3757 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT            25
3758 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK        0x1
3759 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT       26
3760 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK       0x1
3761 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT      27
3762 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK      0x1
3763 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT     28
3764 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK        0x1
3765 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT       29
3766 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK         0x1
3767 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT        30
3768 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK     0x1
3769 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT    31
3770         u8 flags1;
3771 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK  0x1F
3772 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
3773 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK           0x7
3774 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT          5
3775         u8 flags2;
3776 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK             0x1
3777 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT            0
3778 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK    0x1
3779 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT   1
3780 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK          0x3F
3781 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT         2
3782         u8 key;
3783         u8 length_hi;
3784         u8 vf_id;
3785         u8 vf_valid;
3786         __le16 pd;
3787         __le32 length_lo;
3788         __le32 itid;
3789         __le32 reserved2;
3790         struct regpair va;
3791         struct regpair pbl_base;
3792         struct regpair dif_error_addr;
3793         struct regpair dif_runt_addr;
3794         __le32 reserved3[2];
3795 };
3796
3797 struct rdma_resize_cq_output_params {
3798         __le32 old_cq_cons;
3799         __le32 old_cq_prod;
3800 };
3801
3802 struct rdma_resize_cq_ramrod_data {
3803         u8 flags;
3804 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK        0x1
3805 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT       0
3806 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK  0x1
3807 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
3808 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK          0x3F
3809 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT         2
3810         u8 pbl_log_page_size;
3811         __le16 pbl_num_pages;
3812         __le32 max_cqes;
3813         struct regpair pbl_addr;
3814         struct regpair output_params_addr;
3815 };
3816
3817 struct rdma_srq_context {
3818         struct regpair temp[8];
3819 };
3820
3821 struct rdma_srq_create_ramrod_data {
3822         struct regpair pbl_base_addr;
3823         __le16 pages_in_srq_pbl;
3824         __le16 pd_id;
3825         struct rdma_srq_id srq_id;
3826         __le16 page_size;
3827         __le16 reserved1;
3828         __le32 reserved2;
3829         struct regpair producers_addr;
3830 };
3831
3832 struct rdma_srq_destroy_ramrod_data {
3833         struct rdma_srq_id srq_id;
3834         __le32 reserved;
3835 };
3836
3837 struct rdma_srq_modify_ramrod_data {
3838         struct rdma_srq_id srq_id;
3839         __le32 wqe_limit;
3840 };
3841
3842 struct ystorm_rdma_task_st_ctx {
3843         struct regpair temp[4];
3844 };
3845
3846 struct ystorm_rdma_task_ag_ctx {
3847         u8 reserved;
3848         u8 byte1;
3849         __le16 msem_ctx_upd_seq;
3850         u8 flags0;
3851 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF
3852 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
3853 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1
3854 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
3855 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1
3856 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
3857 #define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK            0x1
3858 #define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT           6
3859 #define YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK             0x1
3860 #define YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT            7
3861         u8 flags1;
3862 #define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3
3863 #define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
3864 #define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3
3865 #define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
3866 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK       0x3
3867 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT      4
3868 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1
3869 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
3870 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1
3871 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
3872         u8 flags2;
3873 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK             0x1
3874 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT            0
3875 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1
3876 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
3877 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1
3878 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
3879 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1
3880 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
3881 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1
3882 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
3883 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1
3884 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
3885 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1
3886 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
3887 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1
3888 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
3889         u8 key;
3890         __le32 mw_cnt;
3891         u8 ref_cnt_seq;
3892         u8 ctx_upd_seq;
3893         __le16 dif_flags;
3894         __le16 tx_ref_count;
3895         __le16 last_used_ltid;
3896         __le16 parent_mr_lo;
3897         __le16 parent_mr_hi;
3898         __le32 fbo_lo;
3899         __le32 fbo_hi;
3900 };
3901
3902 struct mstorm_rdma_task_ag_ctx {
3903         u8 reserved;
3904         u8 byte1;
3905         __le16 icid;
3906         u8 flags0;
3907 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF
3908 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
3909 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1
3910 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
3911 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1
3912 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
3913 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK             0x1
3914 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT            6
3915 #define MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK             0x1
3916 #define MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT            7
3917         u8 flags1;
3918 #define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3
3919 #define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
3920 #define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3
3921 #define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
3922 #define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK              0x3
3923 #define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT             4
3924 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1
3925 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
3926 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1
3927 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
3928         u8 flags2;
3929 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK            0x1
3930 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT           0
3931 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1
3932 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
3933 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1
3934 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
3935 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1
3936 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
3937 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1
3938 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
3939 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1
3940 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
3941 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1
3942 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
3943 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1
3944 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
3945         u8 key;
3946         __le32 mw_cnt;
3947         u8 ref_cnt_seq;
3948         u8 ctx_upd_seq;
3949         __le16 dif_flags;
3950         __le16 tx_ref_count;
3951         __le16 last_used_ltid;
3952         __le16 parent_mr_lo;
3953         __le16 parent_mr_hi;
3954         __le32 fbo_lo;
3955         __le32 fbo_hi;
3956 };
3957
3958 struct ustorm_rdma_task_st_ctx {
3959         struct regpair temp[2];
3960 };
3961
3962 struct ustorm_rdma_task_ag_ctx {
3963         u8 reserved;
3964         u8 byte1;
3965         __le16 icid;
3966         u8 flags0;
3967 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF
3968 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
3969 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1
3970 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
3971 #define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK          0x1
3972 #define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT         5
3973 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK     0x3
3974 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT    6
3975         u8 flags1;
3976 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK   0x3
3977 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT  0
3978 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK           0x3
3979 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT          2
3980 #define USTORM_RDMA_TASK_AG_CTX_CF3_MASK                     0x3
3981 #define USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT                    4
3982 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK            0x3
3983 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT           6
3984         u8 flags2;
3985 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK  0x1
3986 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
3987 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK               0x1
3988 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT              1
3989 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK               0x1
3990 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT              2
3991 #define USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK                   0x1
3992 #define USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT                  3
3993 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK         0x1
3994 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT        4
3995 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK                 0x1
3996 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT                5
3997 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK                 0x1
3998 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT                6
3999 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK                 0x1
4000 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT                7
4001         u8 flags3;
4002 #define USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK                 0x1
4003 #define USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT                0
4004 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK                 0x1
4005 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT                1
4006 #define USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK                 0x1
4007 #define USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT                2
4008 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK                 0x1
4009 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT                3
4010 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK          0xF
4011 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT         4
4012         __le32 dif_err_intervals;
4013         __le32 dif_error_1st_interval;
4014         __le32 reg2;
4015         __le32 dif_runt_value;
4016         __le32 reg4;
4017         __le32 reg5;
4018 };
4019
4020 struct rdma_task_context {
4021         struct ystorm_rdma_task_st_ctx ystorm_st_context;
4022         struct ystorm_rdma_task_ag_ctx ystorm_ag_context;
4023         struct tdif_task_context tdif_context;
4024         struct mstorm_rdma_task_ag_ctx mstorm_ag_context;
4025         struct mstorm_rdma_task_st_ctx mstorm_st_context;
4026         struct rdif_task_context rdif_context;
4027         struct ustorm_rdma_task_st_ctx ustorm_st_context;
4028         struct regpair ustorm_st_padding[2];
4029         struct ustorm_rdma_task_ag_ctx ustorm_ag_context;
4030 };
4031
4032 enum rdma_tid_type {
4033         RDMA_TID_REGISTERED_MR,
4034         RDMA_TID_FMR,
4035         RDMA_TID_MW_TYPE1,
4036         RDMA_TID_MW_TYPE2A,
4037         MAX_RDMA_TID_TYPE
4038 };
4039
4040 struct mstorm_rdma_conn_ag_ctx {
4041         u8 byte0;
4042         u8 byte1;
4043         u8 flags0;
4044 #define MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK     0x1
4045 #define MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT    0
4046 #define MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK     0x1
4047 #define MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT    1
4048 #define MSTORM_RDMA_CONN_AG_CTX_CF0_MASK      0x3
4049 #define MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT     2
4050 #define MSTORM_RDMA_CONN_AG_CTX_CF1_MASK      0x3
4051 #define MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT     4
4052 #define MSTORM_RDMA_CONN_AG_CTX_CF2_MASK      0x3
4053 #define MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT     6
4054         u8 flags1;
4055 #define MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK    0x1
4056 #define MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT   0
4057 #define MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK    0x1
4058 #define MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT   1
4059 #define MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK    0x1
4060 #define MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT   2
4061 #define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK  0x1
4062 #define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
4063 #define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK  0x1
4064 #define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
4065 #define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK  0x1
4066 #define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
4067 #define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK  0x1
4068 #define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
4069 #define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK  0x1
4070 #define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
4071         __le16 word0;
4072         __le16 word1;
4073         __le32 reg0;
4074         __le32 reg1;
4075 };
4076
4077 struct tstorm_rdma_conn_ag_ctx {
4078         u8 reserved0;
4079         u8 byte1;
4080         u8 flags0;
4081 #define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1
4082 #define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
4083 #define TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK                  0x1
4084 #define TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT                 1
4085 #define TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK                  0x1
4086 #define TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT                 2
4087 #define TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK                  0x1
4088 #define TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT                 3
4089 #define TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK                  0x1
4090 #define TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT                 4
4091 #define TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK                  0x1
4092 #define TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT                 5
4093 #define TSTORM_RDMA_CONN_AG_CTX_CF0_MASK                   0x3
4094 #define TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT                  6
4095         u8 flags1;
4096 #define TSTORM_RDMA_CONN_AG_CTX_CF1_MASK                   0x3
4097 #define TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT                  0
4098 #define TSTORM_RDMA_CONN_AG_CTX_CF2_MASK                   0x3
4099 #define TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT                  2
4100 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK     0x3
4101 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT    4
4102 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK           0x3
4103 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT          6
4104         u8 flags2;
4105 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK       0x3
4106 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT      0
4107 #define TSTORM_RDMA_CONN_AG_CTX_CF6_MASK                   0x3
4108 #define TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT                  2
4109 #define TSTORM_RDMA_CONN_AG_CTX_CF7_MASK                   0x3
4110 #define TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT                  4
4111 #define TSTORM_RDMA_CONN_AG_CTX_CF8_MASK                   0x3
4112 #define TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT                  6
4113         u8 flags3;
4114 #define TSTORM_RDMA_CONN_AG_CTX_CF9_MASK                   0x3
4115 #define TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT                  0
4116 #define TSTORM_RDMA_CONN_AG_CTX_CF10_MASK                  0x3
4117 #define TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT                 2
4118 #define TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK                 0x1
4119 #define TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT                4
4120 #define TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK                 0x1
4121 #define TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT                5
4122 #define TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK                 0x1
4123 #define TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT                6
4124 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK  0x1
4125 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
4126         u8 flags4;
4127 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK        0x1
4128 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT       0
4129 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK    0x1
4130 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT   1
4131 #define TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK                 0x1
4132 #define TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT                2
4133 #define TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK                 0x1
4134 #define TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT                3
4135 #define TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK                 0x1
4136 #define TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT                4
4137 #define TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK                 0x1
4138 #define TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT                5
4139 #define TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK                0x1
4140 #define TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT               6
4141 #define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK               0x1
4142 #define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT              7
4143         u8 flags5;
4144 #define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK               0x1
4145 #define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT              0
4146 #define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK               0x1
4147 #define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT              1
4148 #define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK               0x1
4149 #define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT              2
4150 #define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK               0x1
4151 #define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT              3
4152 #define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK               0x1
4153 #define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT              4
4154 #define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK               0x1
4155 #define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT              5
4156 #define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK               0x1
4157 #define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT              6
4158 #define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK               0x1
4159 #define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT              7
4160         __le32 reg0;
4161         __le32 reg1;
4162         __le32 reg2;
4163         __le32 reg3;
4164         __le32 reg4;
4165         __le32 reg5;
4166         __le32 reg6;
4167         __le32 reg7;
4168         __le32 reg8;
4169         u8 byte2;
4170         u8 byte3;
4171         __le16 word0;
4172         u8 byte4;
4173         u8 byte5;
4174         __le16 word1;
4175         __le16 word2;
4176         __le16 word3;
4177         __le32 reg9;
4178         __le32 reg10;
4179 };
4180
4181 struct tstorm_rdma_task_ag_ctx {
4182         u8 byte0;
4183         u8 byte1;
4184         __le16 word0;
4185         u8 flags0;
4186 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK  0xF
4187 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
4188 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK     0x1
4189 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT    4
4190 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK     0x1
4191 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT    5
4192 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK     0x1
4193 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT    6
4194 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK     0x1
4195 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT    7
4196         u8 flags1;
4197 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK     0x1
4198 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT    0
4199 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK     0x1
4200 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT    1
4201 #define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK      0x3
4202 #define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT     2
4203 #define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK      0x3
4204 #define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT     4
4205 #define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK      0x3
4206 #define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT     6
4207         u8 flags2;
4208 #define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK      0x3
4209 #define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT     0
4210 #define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK      0x3
4211 #define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT     2
4212 #define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK      0x3
4213 #define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT     4
4214 #define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK      0x3
4215 #define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT     6
4216         u8 flags3;
4217 #define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK      0x3
4218 #define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT     0
4219 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK    0x1
4220 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT   2
4221 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK    0x1
4222 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT   3
4223 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK    0x1
4224 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT   4
4225 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK    0x1
4226 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT   5
4227 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK    0x1
4228 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT   6
4229 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK    0x1
4230 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT   7
4231         u8 flags4;
4232 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK    0x1
4233 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT   0
4234 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK    0x1
4235 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT   1
4236 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK  0x1
4237 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
4238 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK  0x1
4239 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
4240 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK  0x1
4241 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
4242 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK  0x1
4243 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
4244 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK  0x1
4245 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
4246 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK  0x1
4247 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
4248         u8 byte2;
4249         __le16 word1;
4250         __le32 reg0;
4251         u8 byte3;
4252         u8 byte4;
4253         __le16 word2;
4254         __le16 word3;
4255         __le16 word4;
4256         __le32 reg1;
4257         __le32 reg2;
4258 };
4259
4260 struct ustorm_rdma_conn_ag_ctx {
4261         u8 reserved;
4262         u8 byte1;
4263         u8 flags0;
4264 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK     0x1
4265 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT    0
4266 #define USTORM_RDMA_CONN_AG_CTX_BIT1_MASK             0x1
4267 #define USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT            1
4268 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK      0x3
4269 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT     2
4270 #define USTORM_RDMA_CONN_AG_CTX_CF1_MASK              0x3
4271 #define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT             4
4272 #define USTORM_RDMA_CONN_AG_CTX_CF2_MASK              0x3
4273 #define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT             6
4274         u8 flags1;
4275 #define USTORM_RDMA_CONN_AG_CTX_CF3_MASK              0x3
4276 #define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT             0
4277 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK     0x3
4278 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT    2
4279 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK        0x3
4280 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT       4
4281 #define USTORM_RDMA_CONN_AG_CTX_CF6_MASK              0x3
4282 #define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT             6
4283         u8 flags2;
4284 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK   0x1
4285 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT  0
4286 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK            0x1
4287 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT           1
4288 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK            0x1
4289 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT           2
4290 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK            0x1
4291 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT           3
4292 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK  0x1
4293 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
4294 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK     0x1
4295 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT    5
4296 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK            0x1
4297 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT           6
4298 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK         0x1
4299 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT        7
4300         u8 flags3;
4301 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK            0x1
4302 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT           0
4303 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK          0x1
4304 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT         1
4305 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK          0x1
4306 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT         2
4307 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK          0x1
4308 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT         3
4309 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK          0x1
4310 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT         4
4311 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK          0x1
4312 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT         5
4313 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK          0x1
4314 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT         6
4315 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK          0x1
4316 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT         7
4317         u8 byte2;
4318         u8 byte3;
4319         __le16 conn_dpi;
4320         __le16 word1;
4321         __le32 cq_cons;
4322         __le32 cq_se_prod;
4323         __le32 cq_prod;
4324         __le32 reg3;
4325         __le16 int_timeout;
4326         __le16 word3;
4327 };
4328
4329 struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
4330         u8 reserved0;
4331         u8 state;
4332         u8 flags0;
4333 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK      0x1
4334 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT     0
4335 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK              0x1
4336 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT             1
4337 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK              0x1
4338 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT             2
4339 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK      0x1
4340 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT     3
4341 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK              0x1
4342 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT             4
4343 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK              0x1
4344 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT             5
4345 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK              0x1
4346 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT             6
4347 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK              0x1
4348 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT             7
4349         u8 flags1;
4350 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK              0x1
4351 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT             0
4352 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK              0x1
4353 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT             1
4354 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK             0x1
4355 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT            2
4356 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK             0x1
4357 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT            3
4358 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK             0x1
4359 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT            4
4360 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_MASK             0x1
4361 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_SHIFT            5
4362 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK             0x1
4363 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT            6
4364 #define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK      0x1
4365 #define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT     7
4366         u8 flags2;
4367 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK               0x3
4368 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT              0
4369 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK               0x3
4370 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT              2
4371 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK               0x3
4372 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT              4
4373 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK               0x3
4374 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT              6
4375         u8 flags3;
4376 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK               0x3
4377 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT              0
4378 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK               0x3
4379 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT              2
4380 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK               0x3
4381 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT              4
4382 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK       0x3
4383 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT      6
4384         u8 flags4;
4385 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK               0x3
4386 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT              0
4387 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK               0x3
4388 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT              2
4389 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK              0x3
4390 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT             4
4391 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK              0x3
4392 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT             6
4393         u8 flags5;
4394 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK              0x3
4395 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT             0
4396 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK              0x3
4397 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT             2
4398 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK              0x3
4399 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT             4
4400 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK              0x3
4401 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT             6
4402         u8 flags6;
4403 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK              0x3
4404 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT             0
4405 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK              0x3
4406 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT             2
4407 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK              0x3
4408 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT             4
4409 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK              0x3
4410 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT             6
4411         u8 flags7;
4412 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK              0x3
4413 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT             0
4414 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK              0x3
4415 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT             2
4416 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK         0x3
4417 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT        4
4418 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK             0x1
4419 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT            6
4420 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK             0x1
4421 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT            7
4422         u8 flags8;
4423 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK             0x1
4424 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT            0
4425 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK             0x1
4426 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT            1
4427 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK             0x1
4428 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT            2
4429 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK             0x1
4430 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT            3
4431 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK             0x1
4432 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT            4
4433 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK    0x1
4434 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT   5
4435 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK             0x1
4436 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT            6
4437 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK             0x1
4438 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT            7
4439         u8 flags9;
4440 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK            0x1
4441 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT           0
4442 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK            0x1
4443 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT           1
4444 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK            0x1
4445 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT           2
4446 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK            0x1
4447 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT           3
4448 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK            0x1
4449 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT           4
4450 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK            0x1
4451 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT           5
4452 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK            0x1
4453 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT           6
4454 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK            0x1
4455 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT           7
4456         u8 flags10;
4457 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK            0x1
4458 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT           0
4459 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK            0x1
4460 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT           1
4461 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK            0x1
4462 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT           2
4463 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK            0x1
4464 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT           3
4465 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK      0x1
4466 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT     4
4467 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK            0x1
4468 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT           5
4469 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK           0x1
4470 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT          6
4471 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK           0x1
4472 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT          7
4473         u8 flags11;
4474 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK           0x1
4475 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT          0
4476 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK           0x1
4477 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT          1
4478 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK           0x1
4479 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT          2
4480 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK           0x1
4481 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT          3
4482 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK           0x1
4483 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT          4
4484 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK           0x1
4485 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT          5
4486 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK      0x1
4487 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT     6
4488 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK           0x1
4489 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT          7
4490         u8 flags12;
4491 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK          0x1
4492 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT         0
4493 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK          0x1
4494 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT         1
4495 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK      0x1
4496 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT     2
4497 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK      0x1
4498 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT     3
4499 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK          0x1
4500 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT         4
4501 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK          0x1
4502 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT         5
4503 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK          0x1
4504 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT         6
4505 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK          0x1
4506 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT         7
4507         u8 flags13;
4508 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK          0x1
4509 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT         0
4510 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK          0x1
4511 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT         1
4512 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK      0x1
4513 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT     2
4514 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK      0x1
4515 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT     3
4516 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK      0x1
4517 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT     4
4518 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK      0x1
4519 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT     5
4520 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK      0x1
4521 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT     6
4522 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK      0x1
4523 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT     7
4524         u8 flags14;
4525 #define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK         0x1
4526 #define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT        0
4527 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK             0x1
4528 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT            1
4529 #define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK      0x3
4530 #define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT     2
4531 #define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK          0x1
4532 #define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT         4
4533 #define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK  0x1
4534 #define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
4535 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK              0x3
4536 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT             6
4537         u8 byte2;
4538         __le16 physical_q0;
4539         __le16 word1;
4540         __le16 word2;
4541         __le16 word3;
4542         __le16 word4;
4543         __le16 word5;
4544         __le16 conn_dpi;
4545         u8 byte3;
4546         u8 byte4;
4547         u8 byte5;
4548         u8 byte6;
4549         __le32 reg0;
4550         __le32 reg1;
4551         __le32 reg2;
4552         __le32 snd_nxt_psn;
4553         __le32 reg4;
4554 };
4555
4556 struct xstorm_rdma_conn_ag_ctx {
4557         u8 reserved0;
4558         u8 state;
4559         u8 flags0;
4560 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK      0x1
4561 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
4562 #define XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK              0x1
4563 #define XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT             1
4564 #define XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK              0x1
4565 #define XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT             2
4566 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK      0x1
4567 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT     3
4568 #define XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK              0x1
4569 #define XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT             4
4570 #define XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK              0x1
4571 #define XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT             5
4572 #define XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK              0x1
4573 #define XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT             6
4574 #define XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK              0x1
4575 #define XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT             7
4576         u8 flags1;
4577 #define XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK              0x1
4578 #define XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT             0
4579 #define XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK              0x1
4580 #define XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT             1
4581 #define XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK             0x1
4582 #define XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT            2
4583 #define XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK             0x1
4584 #define XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT            3
4585 #define XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK             0x1
4586 #define XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT            4
4587 #define XSTORM_RDMA_CONN_AG_CTX_BIT13_MASK             0x1
4588 #define XSTORM_RDMA_CONN_AG_CTX_BIT13_SHIFT            5
4589 #define XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK             0x1
4590 #define XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT            6
4591 #define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK      0x1
4592 #define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT     7
4593         u8 flags2;
4594 #define XSTORM_RDMA_CONN_AG_CTX_CF0_MASK               0x3
4595 #define XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT              0
4596 #define XSTORM_RDMA_CONN_AG_CTX_CF1_MASK               0x3
4597 #define XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT              2
4598 #define XSTORM_RDMA_CONN_AG_CTX_CF2_MASK               0x3
4599 #define XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT              4
4600 #define XSTORM_RDMA_CONN_AG_CTX_CF3_MASK               0x3
4601 #define XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT              6
4602         u8 flags3;
4603 #define XSTORM_RDMA_CONN_AG_CTX_CF4_MASK               0x3
4604 #define XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT              0
4605 #define XSTORM_RDMA_CONN_AG_CTX_CF5_MASK               0x3
4606 #define XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT              2
4607 #define XSTORM_RDMA_CONN_AG_CTX_CF6_MASK               0x3
4608 #define XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT              4
4609 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK       0x3
4610 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT      6
4611         u8 flags4;
4612 #define XSTORM_RDMA_CONN_AG_CTX_CF8_MASK               0x3
4613 #define XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT              0
4614 #define XSTORM_RDMA_CONN_AG_CTX_CF9_MASK               0x3
4615 #define XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT              2
4616 #define XSTORM_RDMA_CONN_AG_CTX_CF10_MASK              0x3
4617 #define XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT             4
4618 #define XSTORM_RDMA_CONN_AG_CTX_CF11_MASK              0x3
4619 #define XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT             6
4620         u8 flags5;
4621 #define XSTORM_RDMA_CONN_AG_CTX_CF12_MASK              0x3
4622 #define XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT             0
4623 #define XSTORM_RDMA_CONN_AG_CTX_CF13_MASK              0x3
4624 #define XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT             2
4625 #define XSTORM_RDMA_CONN_AG_CTX_CF14_MASK              0x3
4626 #define XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT             4
4627 #define XSTORM_RDMA_CONN_AG_CTX_CF15_MASK              0x3
4628 #define XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT             6
4629         u8 flags6;
4630 #define XSTORM_RDMA_CONN_AG_CTX_CF16_MASK              0x3
4631 #define XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT             0
4632 #define XSTORM_RDMA_CONN_AG_CTX_CF17_MASK              0x3
4633 #define XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT             2
4634 #define XSTORM_RDMA_CONN_AG_CTX_CF18_MASK              0x3
4635 #define XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT             4
4636 #define XSTORM_RDMA_CONN_AG_CTX_CF19_MASK              0x3
4637 #define XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT             6
4638         u8 flags7;
4639 #define XSTORM_RDMA_CONN_AG_CTX_CF20_MASK              0x3
4640 #define XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT             0
4641 #define XSTORM_RDMA_CONN_AG_CTX_CF21_MASK              0x3
4642 #define XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT             2
4643 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK         0x3
4644 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT        4
4645 #define XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK             0x1
4646 #define XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT            6
4647 #define XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK             0x1
4648 #define XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT            7
4649         u8 flags8;
4650 #define XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK             0x1
4651 #define XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT            0
4652 #define XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK             0x1
4653 #define XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT            1
4654 #define XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK             0x1
4655 #define XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT            2
4656 #define XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK             0x1
4657 #define XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT            3
4658 #define XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK             0x1
4659 #define XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT            4
4660 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK    0x1
4661 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT   5
4662 #define XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK             0x1
4663 #define XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT            6
4664 #define XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK             0x1
4665 #define XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT            7
4666         u8 flags9;
4667 #define XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK            0x1
4668 #define XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT           0
4669 #define XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK            0x1
4670 #define XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT           1
4671 #define XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK            0x1
4672 #define XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT           2
4673 #define XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK            0x1
4674 #define XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT           3
4675 #define XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK            0x1
4676 #define XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT           4
4677 #define XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK            0x1
4678 #define XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT           5
4679 #define XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK            0x1
4680 #define XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT           6
4681 #define XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK            0x1
4682 #define XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT           7
4683         u8 flags10;
4684 #define XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK            0x1
4685 #define XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT           0
4686 #define XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK            0x1
4687 #define XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT           1
4688 #define XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK            0x1
4689 #define XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT           2
4690 #define XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK            0x1
4691 #define XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT           3
4692 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK      0x1
4693 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT     4
4694 #define XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK            0x1
4695 #define XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT           5
4696 #define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK           0x1
4697 #define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT          6
4698 #define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK           0x1
4699 #define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT          7
4700         u8 flags11;
4701 #define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK           0x1
4702 #define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT          0
4703 #define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK           0x1
4704 #define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT          1
4705 #define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK           0x1
4706 #define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT          2
4707 #define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK           0x1
4708 #define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT          3
4709 #define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK           0x1
4710 #define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT          4
4711 #define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK           0x1
4712 #define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT          5
4713 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK      0x1
4714 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT     6
4715 #define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK           0x1
4716 #define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT          7
4717         u8 flags12;
4718 #define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK          0x1
4719 #define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT         0
4720 #define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK          0x1
4721 #define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT         1
4722 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK      0x1
4723 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT     2
4724 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK      0x1
4725 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT     3
4726 #define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK          0x1
4727 #define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT         4
4728 #define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK          0x1
4729 #define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT         5
4730 #define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK          0x1
4731 #define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT         6
4732 #define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK          0x1
4733 #define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT         7
4734         u8 flags13;
4735 #define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK          0x1
4736 #define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT         0
4737 #define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK          0x1
4738 #define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT         1
4739 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK      0x1
4740 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT     2
4741 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK      0x1
4742 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT     3
4743 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK      0x1
4744 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT     4
4745 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK      0x1
4746 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT     5
4747 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK      0x1
4748 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT     6
4749 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK      0x1
4750 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT     7
4751         u8 flags14;
4752 #define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK         0x1
4753 #define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT        0
4754 #define XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK             0x1
4755 #define XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT            1
4756 #define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK      0x3
4757 #define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT     2
4758 #define XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK          0x1
4759 #define XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT         4
4760 #define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK  0x1
4761 #define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
4762 #define XSTORM_RDMA_CONN_AG_CTX_CF23_MASK              0x3
4763 #define XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT             6
4764         u8 byte2;
4765         __le16 physical_q0;
4766         __le16 word1;
4767         __le16 word2;
4768         __le16 word3;
4769         __le16 word4;
4770         __le16 word5;
4771         __le16 conn_dpi;
4772         u8 byte3;
4773         u8 byte4;
4774         u8 byte5;
4775         u8 byte6;
4776         __le32 reg0;
4777         __le32 reg1;
4778         __le32 reg2;
4779         __le32 snd_nxt_psn;
4780         __le32 reg4;
4781         __le32 reg5;
4782         __le32 reg6;
4783 };
4784
4785 struct ystorm_rdma_conn_ag_ctx {
4786         u8 byte0;
4787         u8 byte1;
4788         u8 flags0;
4789 #define YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK     0x1
4790 #define YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT    0
4791 #define YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK     0x1
4792 #define YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT    1
4793 #define YSTORM_RDMA_CONN_AG_CTX_CF0_MASK      0x3
4794 #define YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT     2
4795 #define YSTORM_RDMA_CONN_AG_CTX_CF1_MASK      0x3
4796 #define YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT     4
4797 #define YSTORM_RDMA_CONN_AG_CTX_CF2_MASK      0x3
4798 #define YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT     6
4799         u8 flags1;
4800 #define YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK    0x1
4801 #define YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT   0
4802 #define YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK    0x1
4803 #define YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT   1
4804 #define YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK    0x1
4805 #define YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT   2
4806 #define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK  0x1
4807 #define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
4808 #define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK  0x1
4809 #define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
4810 #define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK  0x1
4811 #define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
4812 #define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK  0x1
4813 #define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
4814 #define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK  0x1
4815 #define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
4816         u8 byte2;
4817         u8 byte3;
4818         __le16 word0;
4819         __le32 reg0;
4820         __le32 reg1;
4821         __le16 word1;
4822         __le16 word2;
4823         __le16 word3;
4824         __le16 word4;
4825         __le32 reg2;
4826         __le32 reg3;
4827 };
4828
4829 struct mstorm_roce_conn_st_ctx {
4830         struct regpair temp[6];
4831 };
4832
4833 struct pstorm_roce_conn_st_ctx {
4834         struct regpair temp[16];
4835 };
4836
4837 struct ystorm_roce_conn_st_ctx {
4838         struct regpair temp[2];
4839 };
4840
4841 struct xstorm_roce_conn_st_ctx {
4842         struct regpair temp[22];
4843 };
4844
4845 struct tstorm_roce_conn_st_ctx {
4846         struct regpair temp[30];
4847 };
4848
4849 struct ustorm_roce_conn_st_ctx {
4850         struct regpair temp[12];
4851 };
4852
4853 struct roce_conn_context {
4854         struct ystorm_roce_conn_st_ctx ystorm_st_context;
4855         struct regpair ystorm_st_padding[2];
4856         struct pstorm_roce_conn_st_ctx pstorm_st_context;
4857         struct xstorm_roce_conn_st_ctx xstorm_st_context;
4858         struct regpair xstorm_st_padding[2];
4859         struct xstorm_rdma_conn_ag_ctx xstorm_ag_context;
4860         struct tstorm_rdma_conn_ag_ctx tstorm_ag_context;
4861         struct timers_context timer_context;
4862         struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
4863         struct tstorm_roce_conn_st_ctx tstorm_st_context;
4864         struct mstorm_roce_conn_st_ctx mstorm_st_context;
4865         struct ustorm_roce_conn_st_ctx ustorm_st_context;
4866         struct regpair ustorm_st_padding[2];
4867 };
4868
4869 struct roce_create_qp_req_ramrod_data {
4870         __le16 flags;
4871 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK          0x3
4872 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT         0
4873 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK  0x1
4874 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
4875 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK        0x1
4876 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT       3
4877 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK                  0x7
4878 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT                 4
4879 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK             0x1
4880 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT            7
4881 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK        0xF
4882 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT       8
4883 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK          0xF
4884 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT         12
4885         u8 max_ord;
4886         u8 traffic_class;
4887         u8 hop_limit;
4888         u8 orq_num_pages;
4889         __le16 p_key;
4890         __le32 flow_label;
4891         __le32 dst_qp_id;
4892         __le32 ack_timeout_val;
4893         __le32 initial_psn;
4894         __le16 mtu;
4895         __le16 pd;
4896         __le16 sq_num_pages;
4897         __le16 reseved2;
4898         struct regpair sq_pbl_addr;
4899         struct regpair orq_pbl_addr;
4900         __le16 local_mac_addr[3];
4901         __le16 remote_mac_addr[3];
4902         __le16 vlan_id;
4903         __le16 udp_src_port;
4904         __le32 src_gid[4];
4905         __le32 dst_gid[4];
4906         struct regpair qp_handle_for_cqe;
4907         struct regpair qp_handle_for_async;
4908         u8 stats_counter_id;
4909         u8 reserved3[7];
4910         __le32 cq_cid;
4911         __le16 physical_queue0;
4912         __le16 dpi;
4913 };
4914
4915 struct roce_create_qp_resp_ramrod_data {
4916         __le16 flags;
4917 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK          0x3
4918 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT         0
4919 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK           0x1
4920 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT          2
4921 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK           0x1
4922 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT          3
4923 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK            0x1
4924 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT           4
4925 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK              0x1
4926 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT             5
4927 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK  0x1
4928 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
4929 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED0_MASK            0x1
4930 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED0_SHIFT           7
4931 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK                  0x7
4932 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT                 8
4933 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK    0x1F
4934 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT   11
4935         u8 max_ird;
4936         u8 traffic_class;
4937         u8 hop_limit;
4938         u8 irq_num_pages;
4939         __le16 p_key;
4940         __le32 flow_label;
4941         __le32 dst_qp_id;
4942         u8 stats_counter_id;
4943         u8 reserved1;
4944         __le16 mtu;
4945         __le32 initial_psn;
4946         __le16 pd;
4947         __le16 rq_num_pages;
4948         struct rdma_srq_id srq_id;
4949         struct regpair rq_pbl_addr;
4950         struct regpair irq_pbl_addr;
4951         __le16 local_mac_addr[3];
4952         __le16 remote_mac_addr[3];
4953         __le16 vlan_id;
4954         __le16 udp_src_port;
4955         __le32 src_gid[4];
4956         __le32 dst_gid[4];
4957         struct regpair qp_handle_for_cqe;
4958         struct regpair qp_handle_for_async;
4959         __le32 reserved2[2];
4960         __le32 cq_cid;
4961         __le16 physical_queue0;
4962         __le16 dpi;
4963 };
4964
4965 struct roce_destroy_qp_req_output_params {
4966         __le32 num_bound_mw;
4967         __le32 reserved;
4968 };
4969
4970 struct roce_destroy_qp_req_ramrod_data {
4971         struct regpair output_params_addr;
4972 };
4973
4974 struct roce_destroy_qp_resp_output_params {
4975         __le32 num_invalidated_mw;
4976         __le32 reserved;
4977 };
4978
4979 struct roce_destroy_qp_resp_ramrod_data {
4980         struct regpair output_params_addr;
4981 };
4982
4983 enum roce_event_opcode {
4984         ROCE_EVENT_CREATE_QP = 11,
4985         ROCE_EVENT_MODIFY_QP,
4986         ROCE_EVENT_QUERY_QP,
4987         ROCE_EVENT_DESTROY_QP,
4988         MAX_ROCE_EVENT_OPCODE
4989 };
4990
4991 struct roce_modify_qp_req_ramrod_data {
4992         __le16 flags;
4993 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK      0x1
4994 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT     0
4995 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK      0x1
4996 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT     1
4997 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK  0x1
4998 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
4999 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK            0x1
5000 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT           3
5001 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK   0x1
5002 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT  4
5003 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK          0x1
5004 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT         5
5005 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK      0x1
5006 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT     6
5007 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK    0x1
5008 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT   7
5009 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK      0x1
5010 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT     8
5011 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK              0x1
5012 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT             9
5013 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK                  0x7
5014 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT                 10
5015 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK            0x7
5016 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT           13
5017         u8 fields;
5018 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK        0xF
5019 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT       0
5020 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK          0xF
5021 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT         4
5022         u8 max_ord;
5023         u8 traffic_class;
5024         u8 hop_limit;
5025         __le16 p_key;
5026         __le32 flow_label;
5027         __le32 ack_timeout_val;
5028         __le16 mtu;
5029         __le16 reserved2;
5030         __le32 reserved3[3];
5031         __le32 src_gid[4];
5032         __le32 dst_gid[4];
5033 };
5034
5035 struct roce_modify_qp_resp_ramrod_data {
5036         __le16 flags;
5037 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK        0x1
5038 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT       0
5039 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK             0x1
5040 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT            1
5041 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK             0x1
5042 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT            2
5043 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK              0x1
5044 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT             3
5045 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK              0x1
5046 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT             4
5047 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK     0x1
5048 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT    5
5049 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK            0x1
5050 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT           6
5051 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK                0x1
5052 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT               7
5053 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK  0x1
5054 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
5055 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK        0x1
5056 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT       9
5057 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK              0x3F
5058 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT             10
5059         u8 fields;
5060 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK                    0x7
5061 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT                   0
5062 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK      0x1F
5063 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT     3
5064         u8 max_ird;
5065         u8 traffic_class;
5066         u8 hop_limit;
5067         __le16 p_key;
5068         __le32 flow_label;
5069         __le16 mtu;
5070         __le16 reserved2;
5071         __le32 src_gid[4];
5072         __le32 dst_gid[4];
5073 };
5074
5075 struct roce_query_qp_req_output_params {
5076         __le32 psn;
5077         __le32 flags;
5078 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK          0x1
5079 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT         0
5080 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK  0x1
5081 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
5082 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK        0x3FFFFFFF
5083 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT       2
5084 };
5085
5086 struct roce_query_qp_req_ramrod_data {
5087         struct regpair output_params_addr;
5088 };
5089
5090 struct roce_query_qp_resp_output_params {
5091         __le32 psn;
5092         __le32 err_flag;
5093 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK  0x1
5094 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
5095 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK  0x7FFFFFFF
5096 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
5097 };
5098
5099 struct roce_query_qp_resp_ramrod_data {
5100         struct regpair output_params_addr;
5101 };
5102
5103 enum roce_ramrod_cmd_id {
5104         ROCE_RAMROD_CREATE_QP = 11,
5105         ROCE_RAMROD_MODIFY_QP,
5106         ROCE_RAMROD_QUERY_QP,
5107         ROCE_RAMROD_DESTROY_QP,
5108         MAX_ROCE_RAMROD_CMD_ID
5109 };
5110
5111 struct mstorm_roce_req_conn_ag_ctx {
5112         u8 byte0;
5113         u8 byte1;
5114         u8 flags0;
5115 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK     0x1
5116 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT    0
5117 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK     0x1
5118 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT    1
5119 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK      0x3
5120 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT     2
5121 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK      0x3
5122 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT     4
5123 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK      0x3
5124 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT     6
5125         u8 flags1;
5126 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK    0x1
5127 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT   0
5128 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK    0x1
5129 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT   1
5130 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK    0x1
5131 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT   2
5132 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK  0x1
5133 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
5134 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK  0x1
5135 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
5136 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK  0x1
5137 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
5138 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK  0x1
5139 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
5140 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK  0x1
5141 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
5142         __le16 word0;
5143         __le16 word1;
5144         __le32 reg0;
5145         __le32 reg1;
5146 };
5147
5148 struct mstorm_roce_resp_conn_ag_ctx {
5149         u8 byte0;
5150         u8 byte1;
5151         u8 flags0;
5152 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK     0x1
5153 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT    0
5154 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK     0x1
5155 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT    1
5156 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK      0x3
5157 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT     2
5158 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK      0x3
5159 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT     4
5160 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK      0x3
5161 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT     6
5162         u8 flags1;
5163 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK    0x1
5164 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT   0
5165 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK    0x1
5166 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT   1
5167 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK    0x1
5168 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT   2
5169 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK  0x1
5170 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
5171 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK  0x1
5172 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
5173 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK  0x1
5174 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
5175 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK  0x1
5176 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
5177 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK  0x1
5178 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
5179         __le16 word0;
5180         __le16 word1;
5181         __le32 reg0;
5182         __le32 reg1;
5183 };
5184
5185 enum roce_flavor {
5186         PLAIN_ROCE /* RoCE v1 */ ,
5187         RROCE_IPV4 /* RoCE v2 (Routable RoCE) over ipv4 */ ,
5188         RROCE_IPV6 /* RoCE v2 (Routable RoCE) over ipv6 */ ,
5189         MAX_ROCE_FLAVOR
5190 };
5191
5192 struct tstorm_roce_req_conn_ag_ctx {
5193         u8 reserved0;
5194         u8 state;
5195         u8 flags0;
5196 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK                0x1
5197 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT               0
5198 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK            0x1
5199 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT           1
5200 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK        0x1
5201 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT       2
5202 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK                        0x1
5203 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT                       3
5204 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK                0x1
5205 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT               4
5206 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK                  0x1
5207 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT                 5
5208 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK                    0x3
5209 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT                   6
5210         u8 flags1;
5211 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK                         0x3
5212 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT                        0
5213 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK                 0x3
5214 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT                2
5215 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK           0x3
5216 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT          4
5217 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK                 0x3
5218 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT                6
5219         u8 flags2;
5220 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK             0x3
5221 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT            0
5222 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK                0x3
5223 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT               2
5224 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK           0x3
5225 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT          4
5226 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK               0x3
5227 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT              6
5228         u8 flags3;
5229 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK     0x3
5230 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT    0
5231 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK       0x3
5232 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT      2
5233 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK                 0x1
5234 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT                4
5235 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK                       0x1
5236 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT                      5
5237 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK              0x1
5238 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT             6
5239 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK        0x1
5240 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT       7
5241         u8 flags4;
5242 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK              0x1
5243 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT             0
5244 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK          0x1
5245 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT         1
5246 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK             0x1
5247 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT            2
5248 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK        0x1
5249 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT       3
5250 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK            0x1
5251 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT           4
5252 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK  0x1
5253 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
5254 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK    0x1
5255 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT   6
5256 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK                     0x1
5257 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT                    7
5258         u8 flags5;
5259 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK                     0x1
5260 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT                    0
5261 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK                     0x1
5262 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT                    1
5263 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK                     0x1
5264 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT                    2
5265 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK                     0x1
5266 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT                    3
5267 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK                     0x1
5268 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT                    4
5269 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK              0x1
5270 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT             5
5271 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK                     0x1
5272 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT                    6
5273 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK                     0x1
5274 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT                    7
5275         __le32 reg0;
5276         __le32 snd_nxt_psn;
5277         __le32 snd_max_psn;
5278         __le32 orq_prod;
5279         __le32 reg4;
5280         __le32 reg5;
5281         __le32 reg6;
5282         __le32 reg7;
5283         __le32 reg8;
5284         u8 tx_cqe_error_type;
5285         u8 orq_cache_idx;
5286         __le16 snd_sq_cons_th;
5287         u8 byte4;
5288         u8 byte5;
5289         __le16 snd_sq_cons;
5290         __le16 word2;
5291         __le16 word3;
5292         __le32 reg9;
5293         __le32 reg10;
5294 };
5295
5296 struct tstorm_roce_resp_conn_ag_ctx {
5297         u8 byte0;
5298         u8 state;
5299         u8 flags0;
5300 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK        0x1
5301 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT       0
5302 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK                0x1
5303 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT               1
5304 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK                0x1
5305 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT               2
5306 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK                0x1
5307 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT               3
5308 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK        0x1
5309 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT       4
5310 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK                0x1
5311 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT               5
5312 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK                 0x3
5313 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT                6
5314         u8 flags1;
5315 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK         0x3
5316 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT        0
5317 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK         0x3
5318 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT        2
5319 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK                 0x3
5320 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT                4
5321 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK         0x3
5322 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT        6
5323         u8 flags2;
5324 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK     0x3
5325 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT    0
5326 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK                 0x3
5327 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT                2
5328 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK                 0x3
5329 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT                4
5330 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK                 0x3
5331 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT                6
5332         u8 flags3;
5333 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK                 0x3
5334 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT                0
5335 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK                0x3
5336 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT               2
5337 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK               0x1
5338 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT              4
5339 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK      0x1
5340 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT     5
5341 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK      0x1
5342 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT     6
5343 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK               0x1
5344 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT              7
5345         u8 flags4;
5346 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK      0x1
5347 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT     0
5348 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK  0x1
5349 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
5350 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK               0x1
5351 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT              2
5352 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK               0x1
5353 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT              3
5354 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK               0x1
5355 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT              4
5356 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK               0x1
5357 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT              5
5358 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK              0x1
5359 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT             6
5360 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK             0x1
5361 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT            7
5362         u8 flags5;
5363 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK             0x1
5364 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT            0
5365 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK             0x1
5366 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT            1
5367 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK             0x1
5368 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT            2
5369 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK             0x1
5370 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT            3
5371 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK             0x1
5372 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT            4
5373 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK          0x1
5374 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT         5
5375 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK             0x1
5376 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT            6
5377 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK             0x1
5378 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT            7
5379         __le32 psn_and_rxmit_id_echo;
5380         __le32 reg1;
5381         __le32 reg2;
5382         __le32 reg3;
5383         __le32 reg4;
5384         __le32 reg5;
5385         __le32 reg6;
5386         __le32 reg7;
5387         __le32 reg8;
5388         u8 tx_async_error_type;
5389         u8 byte3;
5390         __le16 rq_cons;
5391         u8 byte4;
5392         u8 byte5;
5393         __le16 rq_prod;
5394         __le16 conn_dpi;
5395         __le16 irq_cons;
5396         __le32 num_invlidated_mw;
5397         __le32 reg10;
5398 };
5399
5400 struct ustorm_roce_req_conn_ag_ctx {
5401         u8 byte0;
5402         u8 byte1;
5403         u8 flags0;
5404 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK     0x1
5405 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT    0
5406 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK     0x1
5407 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT    1
5408 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK      0x3
5409 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT     2
5410 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK      0x3
5411 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT     4
5412 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK      0x3
5413 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT     6
5414         u8 flags1;
5415 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK      0x3
5416 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT     0
5417 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK      0x3
5418 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT     2
5419 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK      0x3
5420 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT     4
5421 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK      0x3
5422 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT     6
5423         u8 flags2;
5424 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK    0x1
5425 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT   0
5426 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK    0x1
5427 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT   1
5428 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK    0x1
5429 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT   2
5430 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK    0x1
5431 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT   3
5432 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK    0x1
5433 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT   4
5434 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK    0x1
5435 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT   5
5436 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK    0x1
5437 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT   6
5438 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK  0x1
5439 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
5440         u8 flags3;
5441 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK  0x1
5442 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
5443 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK  0x1
5444 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
5445 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK  0x1
5446 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
5447 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK  0x1
5448 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
5449 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK  0x1
5450 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
5451 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK  0x1
5452 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
5453 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK  0x1
5454 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
5455 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK  0x1
5456 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
5457         u8 byte2;
5458         u8 byte3;
5459         __le16 word0;
5460         __le16 word1;
5461         __le32 reg0;
5462         __le32 reg1;
5463         __le32 reg2;
5464         __le32 reg3;
5465         __le16 word2;
5466         __le16 word3;
5467 };
5468
5469 struct ustorm_roce_resp_conn_ag_ctx {
5470         u8 byte0;
5471         u8 byte1;
5472         u8 flags0;
5473 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK     0x1
5474 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT    0
5475 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK     0x1
5476 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT    1
5477 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK      0x3
5478 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT     2
5479 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK      0x3
5480 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT     4
5481 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK      0x3
5482 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT     6
5483         u8 flags1;
5484 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK      0x3
5485 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT     0
5486 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK      0x3
5487 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT     2
5488 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK      0x3
5489 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT     4
5490 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK      0x3
5491 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT     6
5492         u8 flags2;
5493 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK    0x1
5494 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT   0
5495 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK    0x1
5496 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT   1
5497 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK    0x1
5498 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT   2
5499 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK    0x1
5500 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT   3
5501 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK    0x1
5502 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT   4
5503 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK    0x1
5504 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT   5
5505 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK    0x1
5506 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT   6
5507 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK  0x1
5508 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
5509         u8 flags3;
5510 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK  0x1
5511 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
5512 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK  0x1
5513 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
5514 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK  0x1
5515 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
5516 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK  0x1
5517 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
5518 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK  0x1
5519 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
5520 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK  0x1
5521 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
5522 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK  0x1
5523 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
5524 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK  0x1
5525 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
5526         u8 byte2;
5527         u8 byte3;
5528         __le16 word0;
5529         __le16 word1;
5530         __le32 reg0;
5531         __le32 reg1;
5532         __le32 reg2;
5533         __le32 reg3;
5534         __le16 word2;
5535         __le16 word3;
5536 };
5537
5538 struct xstorm_roce_req_conn_ag_ctx {
5539         u8 reserved0;
5540         u8 state;
5541         u8 flags0;
5542 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK        0x1
5543 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT       0
5544 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK           0x1
5545 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT          1
5546 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK           0x1
5547 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT          2
5548 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK        0x1
5549 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT       3
5550 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK           0x1
5551 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT          4
5552 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK           0x1
5553 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT          5
5554 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK           0x1
5555 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT          6
5556 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK           0x1
5557 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT          7
5558         u8 flags1;
5559 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK           0x1
5560 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT          0
5561 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK           0x1
5562 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT          1
5563 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK               0x1
5564 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT              2
5565 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK               0x1
5566 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT              3
5567 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK               0x1
5568 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT              4
5569 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK               0x1
5570 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT              5
5571 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK         0x1
5572 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT        6
5573 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK        0x1
5574 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT       7
5575         u8 flags2;
5576 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK                 0x3
5577 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT                0
5578 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK                 0x3
5579 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT                2
5580 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK                 0x3
5581 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT                4
5582 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK                 0x3
5583 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT                6
5584         u8 flags3;
5585 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK         0x3
5586 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT        0
5587 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK         0x3
5588 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT        2
5589 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK        0x3
5590 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT       4
5591 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK         0x3
5592 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT        6
5593         u8 flags4;
5594 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK                 0x3
5595 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT                0
5596 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK                 0x3
5597 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT                2
5598 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK                0x3
5599 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT               4
5600 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK                0x3
5601 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT               6
5602         u8 flags5;
5603 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK                0x3
5604 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT               0
5605 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK                0x3
5606 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT               2
5607 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK        0x3
5608 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT       4
5609 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK                0x3
5610 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT               6
5611         u8 flags6;
5612 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK                0x3
5613 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT               0
5614 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK                0x3
5615 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT               2
5616 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK                0x3
5617 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT               4
5618 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK                0x3
5619 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT               6
5620         u8 flags7;
5621 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK                0x3
5622 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT               0
5623 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK                0x3
5624 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT               2
5625 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK           0x3
5626 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT          4
5627 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK               0x1
5628 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT              6
5629 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK               0x1
5630 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT              7
5631         u8 flags8;
5632 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK               0x1
5633 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT              0
5634 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK               0x1
5635 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT              1
5636 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK      0x1
5637 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT     2
5638 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK      0x1
5639 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT     3
5640 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK     0x1
5641 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT    4
5642 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK      0x1
5643 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT     5
5644 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK               0x1
5645 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT              6
5646 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK               0x1
5647 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT              7
5648         u8 flags9;
5649 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK              0x1
5650 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT             0
5651 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK              0x1
5652 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT             1
5653 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK              0x1
5654 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT             2
5655 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK              0x1
5656 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT             3
5657 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK     0x1
5658 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT    4
5659 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK              0x1
5660 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT             5
5661 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK              0x1
5662 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT             6
5663 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK              0x1
5664 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT             7
5665         u8 flags10;
5666 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK              0x1
5667 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT             0
5668 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK              0x1
5669 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT             1
5670 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK              0x1
5671 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT             2
5672 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK              0x1
5673 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT             3
5674 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK        0x1
5675 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT       4
5676 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK              0x1
5677 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT             5
5678 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK             0x1
5679 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT            6
5680 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK             0x1
5681 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT            7
5682         u8 flags11;
5683 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK             0x1
5684 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT            0
5685 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK             0x1
5686 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT            1
5687 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK             0x1
5688 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT            2
5689 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK             0x1
5690 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT            3
5691 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK             0x1
5692 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT            4
5693 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK  0x1
5694 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
5695 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK        0x1
5696 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT       6
5697 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK             0x1
5698 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT            7
5699         u8 flags12;
5700 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK          0x1
5701 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT         0
5702 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK            0x1
5703 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT           1
5704 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK        0x1
5705 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT       2
5706 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK        0x1
5707 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT       3
5708 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK   0x1
5709 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT  4
5710 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK            0x1
5711 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT           5
5712 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK   0x1
5713 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT  6
5714 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK     0x1
5715 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT    7
5716         u8 flags13;
5717 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK            0x1
5718 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT           0
5719 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK            0x1
5720 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT           1
5721 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK        0x1
5722 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT       2
5723 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK        0x1
5724 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT       3
5725 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK        0x1
5726 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT       4
5727 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK        0x1
5728 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT       5
5729 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK        0x1
5730 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT       6
5731 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK        0x1
5732 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT       7
5733         u8 flags14;
5734 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK      0x1
5735 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT     0
5736 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK               0x1
5737 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT              1
5738 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK        0x3
5739 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT       2
5740 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK            0x1
5741 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT           4
5742 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK    0x1
5743 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT   5
5744 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK                0x3
5745 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT               6
5746         u8 byte2;
5747         __le16 physical_q0;
5748         __le16 word1;
5749         __le16 sq_cmp_cons;
5750         __le16 sq_cons;
5751         __le16 sq_prod;
5752         __le16 word5;
5753         __le16 conn_dpi;
5754         u8 byte3;
5755         u8 byte4;
5756         u8 byte5;
5757         u8 byte6;
5758         __le32 lsn;
5759         __le32 ssn;
5760         __le32 snd_una_psn;
5761         __le32 snd_nxt_psn;
5762         __le32 reg4;
5763         __le32 orq_cons_th;
5764         __le32 orq_cons;
5765 };
5766
5767 struct xstorm_roce_resp_conn_ag_ctx {
5768         u8 reserved0;
5769         u8 state;
5770         u8 flags0;
5771 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK      0x1
5772 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
5773 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK         0x1
5774 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT        1
5775 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK         0x1
5776 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT        2
5777 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK      0x1
5778 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT     3
5779 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK         0x1
5780 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT        4
5781 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK         0x1
5782 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT        5
5783 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK         0x1
5784 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT        6
5785 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK         0x1
5786 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT        7
5787         u8 flags1;
5788 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK         0x1
5789 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT        0
5790 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK         0x1
5791 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT        1
5792 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK             0x1
5793 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT            2
5794 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK             0x1
5795 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT            3
5796 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK             0x1
5797 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT            4
5798 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK             0x1
5799 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT            5
5800 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK       0x1
5801 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT      6
5802 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK      0x1
5803 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT     7
5804         u8 flags2;
5805 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK               0x3
5806 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT              0
5807 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK               0x3
5808 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT              2
5809 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK               0x3
5810 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT              4
5811 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK               0x3
5812 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT              6
5813         u8 flags3;
5814 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK          0x3
5815 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT         0
5816 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK       0x3
5817 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT      2
5818 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK      0x3
5819 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT     4
5820 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK       0x3
5821 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT      6
5822         u8 flags4;
5823 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK               0x3
5824 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT              0
5825 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK               0x3
5826 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT              2
5827 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK              0x3
5828 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT             4
5829 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK              0x3
5830 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT             6
5831         u8 flags5;
5832 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK              0x3
5833 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT             0
5834 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK              0x3
5835 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT             2
5836 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK              0x3
5837 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT             4
5838 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK              0x3
5839 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT             6
5840         u8 flags6;
5841 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK              0x3
5842 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT             0
5843 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK              0x3
5844 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT             2
5845 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK              0x3
5846 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT             4
5847 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK              0x3
5848 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT             6
5849         u8 flags7;
5850 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK              0x3
5851 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT             0
5852 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK              0x3
5853 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT             2
5854 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK         0x3
5855 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT        4
5856 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK             0x1
5857 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT            6
5858 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK             0x1
5859 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT            7
5860         u8 flags8;
5861 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK             0x1
5862 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT            0
5863 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK             0x1
5864 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT            1
5865 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK       0x1
5866 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT      2
5867 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK    0x1
5868 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT   3
5869 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK   0x1
5870 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT  4
5871 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK    0x1
5872 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT   5
5873 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK             0x1
5874 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT            6
5875 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK             0x1
5876 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT            7
5877         u8 flags9;
5878 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK            0x1
5879 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT           0
5880 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK            0x1
5881 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT           1
5882 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK            0x1
5883 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT           2
5884 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK            0x1
5885 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT           3
5886 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK            0x1
5887 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT           4
5888 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK            0x1
5889 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT           5
5890 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK            0x1
5891 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT           6
5892 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK            0x1
5893 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT           7
5894         u8 flags10;
5895 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK            0x1
5896 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT           0
5897 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK            0x1
5898 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT           1
5899 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK            0x1
5900 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT           2
5901 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK            0x1
5902 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT           3
5903 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK      0x1
5904 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT     4
5905 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK            0x1
5906 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT           5
5907 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK           0x1
5908 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT          6
5909 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK           0x1
5910 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT          7
5911         u8 flags11;
5912 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK           0x1
5913 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT          0
5914 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK           0x1
5915 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT          1
5916 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK           0x1
5917 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT          2
5918 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK           0x1
5919 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT          3
5920 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK           0x1
5921 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT          4
5922 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK           0x1
5923 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT          5
5924 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK      0x1
5925 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT     6
5926 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK           0x1
5927 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT          7
5928         u8 flags12;
5929 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK          0x1
5930 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT         0
5931 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK  0x1
5932 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1
5933 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK      0x1
5934 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT     2
5935 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK      0x1
5936 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT     3
5937 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK          0x1
5938 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT         4
5939 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK          0x1
5940 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT         5
5941 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK          0x1
5942 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT         6
5943 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK          0x1
5944 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT         7
5945         u8 flags13;
5946 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK          0x1
5947 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT         0
5948 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK          0x1
5949 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT         1
5950 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK      0x1
5951 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT     2
5952 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK      0x1
5953 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT     3
5954 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK      0x1
5955 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT     4
5956 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK      0x1
5957 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT     5
5958 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK      0x1
5959 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT     6
5960 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK      0x1
5961 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT     7
5962         u8 flags14;
5963 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK             0x1
5964 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT            0
5965 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK             0x1
5966 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT            1
5967 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK             0x1
5968 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT            2
5969 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK             0x1
5970 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT            3
5971 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK             0x1
5972 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT            4
5973 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK             0x1
5974 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT            5
5975 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK              0x3
5976 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT             6
5977         u8 byte2;
5978         __le16 physical_q0;
5979         __le16 word1;
5980         __le16 irq_prod;
5981         __le16 word3;
5982         __le16 word4;
5983         __le16 word5;
5984         __le16 irq_cons;
5985         u8 rxmit_opcode;
5986         u8 byte4;
5987         u8 byte5;
5988         u8 byte6;
5989         __le32 rxmit_psn_and_id;
5990         __le32 rxmit_bytes_length;
5991         __le32 psn;
5992         __le32 reg3;
5993         __le32 reg4;
5994         __le32 reg5;
5995         __le32 msn_and_syndrome;
5996 };
5997
5998 struct ystorm_roce_req_conn_ag_ctx {
5999         u8 byte0;
6000         u8 byte1;
6001         u8 flags0;
6002 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK     0x1
6003 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT    0
6004 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK     0x1
6005 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT    1
6006 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK      0x3
6007 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT     2
6008 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK      0x3
6009 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT     4
6010 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK      0x3
6011 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT     6
6012         u8 flags1;
6013 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK    0x1
6014 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT   0
6015 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK    0x1
6016 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT   1
6017 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK    0x1
6018 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT   2
6019 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK  0x1
6020 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
6021 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK  0x1
6022 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
6023 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK  0x1
6024 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
6025 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK  0x1
6026 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
6027 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK  0x1
6028 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
6029         u8 byte2;
6030         u8 byte3;
6031         __le16 word0;
6032         __le32 reg0;
6033         __le32 reg1;
6034         __le16 word1;
6035         __le16 word2;
6036         __le16 word3;
6037         __le16 word4;
6038         __le32 reg2;
6039         __le32 reg3;
6040 };
6041
6042 struct ystorm_roce_resp_conn_ag_ctx {
6043         u8 byte0;
6044         u8 byte1;
6045         u8 flags0;
6046 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK     0x1
6047 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT    0
6048 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK     0x1
6049 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT    1
6050 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK      0x3
6051 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT     2
6052 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK      0x3
6053 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT     4
6054 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK      0x3
6055 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT     6
6056         u8 flags1;
6057 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK    0x1
6058 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT   0
6059 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK    0x1
6060 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT   1
6061 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK    0x1
6062 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT   2
6063 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK  0x1
6064 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
6065 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK  0x1
6066 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
6067 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK  0x1
6068 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
6069 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK  0x1
6070 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
6071 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK  0x1
6072 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
6073         u8 byte2;
6074         u8 byte3;
6075         __le16 word0;
6076         __le32 reg0;
6077         __le32 reg1;
6078         __le16 word1;
6079         __le16 word2;
6080         __le16 word3;
6081         __le16 word4;
6082         __le32 reg2;
6083         __le32 reg3;
6084 };
6085
6086 struct ystorm_iscsi_conn_st_ctx {
6087         __le32 reserved[4];
6088 };
6089
6090 struct pstorm_iscsi_tcp_conn_st_ctx {
6091         __le32 tcp[32];
6092         __le32 iscsi[4];
6093 };
6094
6095 struct xstorm_iscsi_tcp_conn_st_ctx {
6096         __le32 reserved_iscsi[40];
6097         __le32 reserved_tcp[4];
6098 };
6099
6100 struct xstorm_iscsi_conn_ag_ctx {
6101         u8 cdu_validation;
6102         u8 state;
6103         u8 flags0;
6104 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK                0x1
6105 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT               0
6106 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK                0x1
6107 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT               1
6108 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK                   0x1
6109 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT                  2
6110 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK                0x1
6111 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT               3
6112 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK                        0x1
6113 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT                       4
6114 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK                   0x1
6115 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT                  5
6116 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK                        0x1
6117 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT                       6
6118 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK                        0x1
6119 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT                       7
6120         u8 flags1;
6121 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK                        0x1
6122 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT                       0
6123 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK                        0x1
6124 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT                       1
6125 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK                       0x1
6126 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT                      2
6127 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK                       0x1
6128 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT                      3
6129 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK                       0x1
6130 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT                      4
6131 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK                       0x1
6132 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT                      5
6133 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK                       0x1
6134 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT                      6
6135 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK                 0x1
6136 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT                7
6137         u8 flags2;
6138 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK                         0x3
6139 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT                        0
6140 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK                         0x3
6141 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT                        2
6142 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK                         0x3
6143 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT                        4
6144 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK              0x3
6145 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT             6
6146         u8 flags3;
6147 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK                         0x3
6148 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT                        0
6149 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK                         0x3
6150 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT                        2
6151 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK                         0x3
6152 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT                        4
6153 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK                         0x3
6154 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT                        6
6155         u8 flags4;
6156 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK                         0x3
6157 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT                        0
6158 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK                         0x3
6159 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT                        2
6160 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK                        0x3
6161 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT                       4
6162 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK                        0x3
6163 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT                       6
6164         u8 flags5;
6165 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK                        0x3
6166 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT                       0
6167 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK                        0x3
6168 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT                       2
6169 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK                        0x3
6170 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT                       4
6171 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK     0x3
6172 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT    6
6173         u8 flags6;
6174 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK                        0x3
6175 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT                       0
6176 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK                        0x3
6177 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT                       2
6178 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK                        0x3
6179 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT                       4
6180 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK                    0x3
6181 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT                   6
6182         u8 flags7;
6183 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK                    0x3
6184 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT                   0
6185 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q1_MASK                    0x3
6186 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q1_SHIFT                   2
6187 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK                   0x3
6188 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT                  4
6189 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK                       0x1
6190 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT                      6
6191 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK                       0x1
6192 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT                      7
6193         u8 flags8;
6194 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK                       0x1
6195 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT                      0
6196 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK           0x1
6197 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT          1
6198 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK                       0x1
6199 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT                      2
6200 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK                       0x1
6201 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT                      3
6202 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK                       0x1
6203 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT                      4
6204 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK                       0x1
6205 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT                      5
6206 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK                       0x1
6207 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT                      6
6208 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK                       0x1
6209 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT                      7
6210         u8 flags9;
6211 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK                      0x1
6212 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT                     0
6213 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK                      0x1
6214 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT                     1
6215 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK                      0x1
6216 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT                     2
6217 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK                      0x1
6218 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT                     3
6219 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK                      0x1
6220 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT                     4
6221 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK  0x1
6222 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
6223 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK                      0x1
6224 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT                     6
6225 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK                      0x1
6226 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT                     7
6227         u8 flags10;
6228 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK                      0x1
6229 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT                     0
6230 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK                 0x1
6231 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT                1
6232 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK                 0x1
6233 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT                2
6234 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q1_EN_MASK                 0x1
6235 #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT                3
6236 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK                0x1
6237 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT               4
6238 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK        0x1
6239 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT       5
6240 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK                     0x1
6241 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT                    6
6242 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK    0x1
6243 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT   7
6244         u8 flags11;
6245 #define XSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK                     0x1
6246 #define XSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT                    0
6247 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK                     0x1
6248 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT                    1
6249 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK                   0x1
6250 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT                  2
6251 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK                     0x1
6252 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT                    3
6253 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK                     0x1
6254 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT                    4
6255 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK                     0x1
6256 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT                    5
6257 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK                0x1
6258 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT               6
6259 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK                     0x1
6260 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT                    7
6261         u8 flags12;
6262 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK              0x1
6263 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT             0
6264 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK                    0x1
6265 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT                   1
6266 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK                0x1
6267 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT               2
6268 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK                0x1
6269 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT               3
6270 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK                    0x1
6271 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT                   4
6272 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK                    0x1
6273 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT                   5
6274 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK                    0x1
6275 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT                   6
6276 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK                    0x1
6277 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT                   7
6278         u8 flags13;
6279 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK            0x1
6280 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT           0
6281 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK              0x1
6282 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT             1
6283 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK                0x1
6284 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT               2
6285 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK                0x1
6286 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT               3
6287 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK                0x1
6288 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT               4
6289 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK                0x1
6290 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT               5
6291 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK                0x1
6292 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT               6
6293 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK                0x1
6294 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT               7
6295         u8 flags14;
6296 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK                       0x1
6297 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT                      0
6298 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK                       0x1
6299 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT                      1
6300 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK                       0x1
6301 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT                      2
6302 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK                       0x1
6303 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT                      3
6304 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK                       0x1
6305 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT                      4
6306 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK             0x1
6307 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT            5
6308 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK           0x3
6309 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT          6
6310         u8 byte2;
6311         __le16 physical_q0;
6312         __le16 physical_q1;
6313         __le16 dummy_dorq_var;
6314         __le16 sq_cons;
6315         __le16 sq_prod;
6316         __le16 word5;
6317         __le16 slow_io_total_data_tx_update;
6318         u8 byte3;
6319         u8 byte4;
6320         u8 byte5;
6321         u8 byte6;
6322         __le32 reg0;
6323         __le32 reg1;
6324         __le32 reg2;
6325         __le32 more_to_send_seq;
6326         __le32 reg4;
6327         __le32 reg5;
6328         __le32 hq_scan_next_relevant_ack;
6329         __le16 r2tq_prod;
6330         __le16 r2tq_cons;
6331         __le16 hq_prod;
6332         __le16 hq_cons;
6333         __le32 remain_seq;
6334         __le32 bytes_to_next_pdu;
6335         __le32 hq_tcp_seq;
6336         u8 byte7;
6337         u8 byte8;
6338         u8 byte9;
6339         u8 byte10;
6340         u8 byte11;
6341         u8 byte12;
6342         u8 byte13;
6343         u8 byte14;
6344         u8 byte15;
6345         u8 byte16;
6346         __le16 word11;
6347         __le32 reg10;
6348         __le32 reg11;
6349         __le32 exp_stat_sn;
6350         __le32 reg13;
6351         __le32 reg14;
6352         __le32 reg15;
6353         __le32 reg16;
6354         __le32 reg17;
6355 };
6356
6357 struct tstorm_iscsi_conn_ag_ctx {
6358         u8 reserved0;
6359         u8 state;
6360         u8 flags0;
6361 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1
6362 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
6363 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK               0x1
6364 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT              1
6365 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK               0x1
6366 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT              2
6367 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK               0x1
6368 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT              3
6369 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK               0x1
6370 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT              4
6371 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK               0x1
6372 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT              5
6373 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK                0x3
6374 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT               6
6375         u8 flags1;
6376 #define TSTORM_ISCSI_CONN_AG_CTX_CF1_MASK                0x3
6377 #define TSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT               0
6378 #define TSTORM_ISCSI_CONN_AG_CTX_CF2_MASK                0x3
6379 #define TSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT               2
6380 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK     0x3
6381 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT    4
6382 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK                0x3
6383 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT               6
6384         u8 flags2;
6385 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK                0x3
6386 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT               0
6387 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK                0x3
6388 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT               2
6389 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK                0x3
6390 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT               4
6391 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK                0x3
6392 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT               6
6393         u8 flags3;
6394 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK           0x3
6395 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT          0
6396 #define TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK               0x3
6397 #define TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT              2
6398 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK              0x1
6399 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT             4
6400 #define TSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK              0x1
6401 #define TSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT             5
6402 #define TSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK              0x1
6403 #define TSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT             6
6404 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK  0x1
6405 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
6406         u8 flags4;
6407 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK              0x1
6408 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT             0
6409 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK              0x1
6410 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT             1
6411 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK              0x1
6412 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT             2
6413 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK              0x1
6414 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT             3
6415 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK              0x1
6416 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT             4
6417 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK        0x1
6418 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT       5
6419 #define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK             0x1
6420 #define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT            6
6421 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK            0x1
6422 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT           7
6423         u8 flags5;
6424 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK            0x1
6425 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT           0
6426 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK            0x1
6427 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT           1
6428 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK            0x1
6429 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT           2
6430 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK            0x1
6431 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT           3
6432 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK            0x1
6433 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT           4
6434 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK            0x1
6435 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT           5
6436 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK            0x1
6437 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT           6
6438 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK            0x1
6439 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT           7
6440         __le32 reg0;
6441         __le32 reg1;
6442         __le32 reg2;
6443         __le32 reg3;
6444         __le32 reg4;
6445         __le32 reg5;
6446         __le32 reg6;
6447         __le32 reg7;
6448         __le32 reg8;
6449         u8 byte2;
6450         u8 byte3;
6451         __le16 word0;
6452 };
6453
6454 struct ustorm_iscsi_conn_ag_ctx {
6455         u8 byte0;
6456         u8 byte1;
6457         u8 flags0;
6458 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK     0x1
6459 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT    0
6460 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK     0x1
6461 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT    1
6462 #define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK      0x3
6463 #define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT     2
6464 #define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK      0x3
6465 #define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT     4
6466 #define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK      0x3
6467 #define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT     6
6468         u8 flags1;
6469 #define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK      0x3
6470 #define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT     0
6471 #define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK      0x3
6472 #define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT     2
6473 #define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK      0x3
6474 #define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT     4
6475 #define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK      0x3
6476 #define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT     6
6477         u8 flags2;
6478 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK    0x1
6479 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT   0
6480 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK    0x1
6481 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT   1
6482 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK    0x1
6483 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT   2
6484 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK    0x1
6485 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT   3
6486 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK    0x1
6487 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT   4
6488 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK    0x1
6489 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT   5
6490 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK    0x1
6491 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT   6
6492 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK  0x1
6493 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
6494         u8 flags3;
6495 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK  0x1
6496 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
6497 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK  0x1
6498 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
6499 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK  0x1
6500 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
6501 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK  0x1
6502 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
6503 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK  0x1
6504 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
6505 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK  0x1
6506 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
6507 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK  0x1
6508 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
6509 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK  0x1
6510 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
6511         u8 byte2;
6512         u8 byte3;
6513         __le16 word0;
6514         __le16 word1;
6515         __le32 reg0;
6516         __le32 reg1;
6517         __le32 reg2;
6518         __le32 reg3;
6519         __le16 word2;
6520         __le16 word3;
6521 };
6522
6523 struct tstorm_iscsi_conn_st_ctx {
6524         __le32 reserved[40];
6525 };
6526
6527 struct mstorm_iscsi_conn_ag_ctx {
6528         u8 reserved;
6529         u8 state;
6530         u8 flags0;
6531 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK     0x1
6532 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT    0
6533 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK     0x1
6534 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT    1
6535 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK      0x3
6536 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT     2
6537 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK      0x3
6538 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT     4
6539 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK      0x3
6540 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT     6
6541         u8 flags1;
6542 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK    0x1
6543 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT   0
6544 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK    0x1
6545 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT   1
6546 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK    0x1
6547 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT   2
6548 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK  0x1
6549 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
6550 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK  0x1
6551 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
6552 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK  0x1
6553 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
6554 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK  0x1
6555 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
6556 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK  0x1
6557 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
6558         __le16 word0;
6559         __le16 word1;
6560         __le32 reg0;
6561         __le32 reg1;
6562 };
6563
6564 struct mstorm_iscsi_tcp_conn_st_ctx {
6565         __le32 reserved_tcp[20];
6566         __le32 reserved_iscsi[8];
6567 };
6568
6569 struct ustorm_iscsi_conn_st_ctx {
6570         __le32 reserved[52];
6571 };
6572
6573 struct iscsi_conn_context {
6574         struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
6575         struct regpair ystorm_st_padding[2];
6576         struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
6577         struct regpair pstorm_st_padding[2];
6578         struct pb_context xpb2_context;
6579         struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
6580         struct regpair xstorm_st_padding[2];
6581         struct xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
6582         struct tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
6583         struct regpair tstorm_ag_padding[2];
6584         struct timers_context timer_context;
6585         struct ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
6586         struct pb_context upb_context;
6587         struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
6588         struct regpair tstorm_st_padding[2];
6589         struct mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
6590         struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
6591         struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
6592 };
6593
6594 struct iscsi_init_ramrod_params {
6595         struct iscsi_spe_func_init iscsi_init_spe;
6596         struct tcp_init_params tcp_init;
6597 };
6598
6599 struct ystorm_iscsi_conn_ag_ctx {
6600         u8 byte0;
6601         u8 byte1;
6602         u8 flags0;
6603 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK     0x1
6604 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT    0
6605 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK     0x1
6606 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT    1
6607 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK      0x3
6608 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT     2
6609 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK      0x3
6610 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT     4
6611 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK      0x3
6612 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT     6
6613         u8 flags1;
6614 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK    0x1
6615 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT   0
6616 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK    0x1
6617 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT   1
6618 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK    0x1
6619 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT   2
6620 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK  0x1
6621 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
6622 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK  0x1
6623 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
6624 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK  0x1
6625 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
6626 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK  0x1
6627 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
6628 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK  0x1
6629 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
6630         u8 byte2;
6631         u8 byte3;
6632         __le16 word0;
6633         __le32 reg0;
6634         __le32 reg1;
6635         __le16 word1;
6636         __le16 word2;
6637         __le16 word3;
6638         __le16 word4;
6639         __le32 reg2;
6640         __le32 reg3;
6641 };
6642 #define VF_MAX_STATIC 192
6643
6644 #define MCP_GLOB_PATH_MAX       2
6645 #define MCP_PORT_MAX            2
6646 #define MCP_GLOB_PORT_MAX       4
6647 #define MCP_GLOB_FUNC_MAX       16
6648
6649 /* Offset from the beginning of the MCP scratchpad */
6650 #define OFFSIZE_OFFSET_SHIFT    0
6651 #define OFFSIZE_OFFSET_MASK     0x0000ffff
6652 /* Size of specific element (not the whole array if any) */
6653 #define OFFSIZE_SIZE_SHIFT      16
6654 #define OFFSIZE_SIZE_MASK       0xffff0000
6655
6656 #define SECTION_OFFSET(_offsize) ((((_offsize &                 \
6657                                      OFFSIZE_OFFSET_MASK) >>    \
6658                                     OFFSIZE_OFFSET_SHIFT) << 2))
6659
6660 #define QED_SECTION_SIZE(_offsize) (((_offsize &                \
6661                                       OFFSIZE_SIZE_MASK) >>     \
6662                                      OFFSIZE_SIZE_SHIFT) << 2)
6663
6664 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH +                  \
6665                                      SECTION_OFFSET(_offsize) +         \
6666                                      (QED_SECTION_SIZE(_offsize) * idx))
6667
6668 #define SECTION_OFFSIZE_ADDR(_pub_base, _section)       \
6669         (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
6670
6671 /* PHY configuration */
6672 struct eth_phy_cfg {
6673         u32 speed;
6674 #define ETH_SPEED_AUTONEG       0
6675 #define ETH_SPEED_SMARTLINQ     0x8
6676
6677         u32 pause;
6678 #define ETH_PAUSE_NONE          0x0
6679 #define ETH_PAUSE_AUTONEG       0x1
6680 #define ETH_PAUSE_RX            0x2
6681 #define ETH_PAUSE_TX            0x4
6682
6683         u32 adv_speed;
6684         u32 loopback_mode;
6685 #define ETH_LOOPBACK_NONE               (0)
6686 #define ETH_LOOPBACK_INT_PHY            (1)
6687 #define ETH_LOOPBACK_EXT_PHY            (2)
6688 #define ETH_LOOPBACK_EXT                (3)
6689 #define ETH_LOOPBACK_MAC                (4)
6690
6691         u32 feature_config_flags;
6692 #define ETH_EEE_MODE_ADV_LPI            (1 << 0)
6693 };
6694
6695 struct port_mf_cfg {
6696         u32 dynamic_cfg;
6697 #define PORT_MF_CFG_OV_TAG_MASK         0x0000ffff
6698 #define PORT_MF_CFG_OV_TAG_SHIFT        0
6699 #define PORT_MF_CFG_OV_TAG_DEFAULT      PORT_MF_CFG_OV_TAG_MASK
6700
6701         u32 reserved[1];
6702 };
6703
6704 struct eth_stats {
6705         u64 r64;
6706         u64 r127;
6707         u64 r255;
6708         u64 r511;
6709         u64 r1023;
6710         u64 r1518;
6711         u64 r1522;
6712         u64 r2047;
6713         u64 r4095;
6714         u64 r9216;
6715         u64 r16383;
6716         u64 rfcs;
6717         u64 rxcf;
6718         u64 rxpf;
6719         u64 rxpp;
6720         u64 raln;
6721         u64 rfcr;
6722         u64 rovr;
6723         u64 rjbr;
6724         u64 rund;
6725         u64 rfrg;
6726         u64 t64;
6727         u64 t127;
6728         u64 t255;
6729         u64 t511;
6730         u64 t1023;
6731         u64 t1518;
6732         u64 t2047;
6733         u64 t4095;
6734         u64 t9216;
6735         u64 t16383;
6736         u64 txpf;
6737         u64 txpp;
6738         u64 tlpiec;
6739         u64 tncl;
6740         u64 rbyte;
6741         u64 rxuca;
6742         u64 rxmca;
6743         u64 rxbca;
6744         u64 rxpok;
6745         u64 tbyte;
6746         u64 txuca;
6747         u64 txmca;
6748         u64 txbca;
6749         u64 txcf;
6750 };
6751
6752 struct brb_stats {
6753         u64 brb_truncate[8];
6754         u64 brb_discard[8];
6755 };
6756
6757 struct port_stats {
6758         struct brb_stats brb;
6759         struct eth_stats eth;
6760 };
6761
6762 struct couple_mode_teaming {
6763         u8 port_cmt[MCP_GLOB_PORT_MAX];
6764 #define PORT_CMT_IN_TEAM        (1 << 0)
6765
6766 #define PORT_CMT_PORT_ROLE      (1 << 1)
6767 #define PORT_CMT_PORT_INACTIVE  (0 << 1)
6768 #define PORT_CMT_PORT_ACTIVE    (1 << 1)
6769
6770 #define PORT_CMT_TEAM_MASK      (1 << 2)
6771 #define PORT_CMT_TEAM0          (0 << 2)
6772 #define PORT_CMT_TEAM1          (1 << 2)
6773 };
6774
6775 #define LLDP_CHASSIS_ID_STAT_LEN        4
6776 #define LLDP_PORT_ID_STAT_LEN           4
6777 #define DCBX_MAX_APP_PROTOCOL           32
6778 #define MAX_SYSTEM_LLDP_TLV_DATA        32
6779
6780 enum _lldp_agent {
6781         LLDP_NEAREST_BRIDGE = 0,
6782         LLDP_NEAREST_NON_TPMR_BRIDGE,
6783         LLDP_NEAREST_CUSTOMER_BRIDGE,
6784         LLDP_MAX_LLDP_AGENTS
6785 };
6786
6787 struct lldp_config_params_s {
6788         u32 config;
6789 #define LLDP_CONFIG_TX_INTERVAL_MASK    0x000000ff
6790 #define LLDP_CONFIG_TX_INTERVAL_SHIFT   0
6791 #define LLDP_CONFIG_HOLD_MASK           0x00000f00
6792 #define LLDP_CONFIG_HOLD_SHIFT          8
6793 #define LLDP_CONFIG_MAX_CREDIT_MASK     0x0000f000
6794 #define LLDP_CONFIG_MAX_CREDIT_SHIFT    12
6795 #define LLDP_CONFIG_ENABLE_RX_MASK      0x40000000
6796 #define LLDP_CONFIG_ENABLE_RX_SHIFT     30
6797 #define LLDP_CONFIG_ENABLE_TX_MASK      0x80000000
6798 #define LLDP_CONFIG_ENABLE_TX_SHIFT     31
6799         u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
6800         u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
6801 };
6802
6803 struct lldp_status_params_s {
6804         u32 prefix_seq_num;
6805         u32 status;
6806         u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
6807         u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
6808         u32 suffix_seq_num;
6809 };
6810
6811 struct dcbx_ets_feature {
6812         u32 flags;
6813 #define DCBX_ETS_ENABLED_MASK   0x00000001
6814 #define DCBX_ETS_ENABLED_SHIFT  0
6815 #define DCBX_ETS_WILLING_MASK   0x00000002
6816 #define DCBX_ETS_WILLING_SHIFT  1
6817 #define DCBX_ETS_ERROR_MASK     0x00000004
6818 #define DCBX_ETS_ERROR_SHIFT    2
6819 #define DCBX_ETS_CBS_MASK       0x00000008
6820 #define DCBX_ETS_CBS_SHIFT      3
6821 #define DCBX_ETS_MAX_TCS_MASK   0x000000f0
6822 #define DCBX_ETS_MAX_TCS_SHIFT  4
6823 #define DCBX_ISCSI_OOO_TC_MASK  0x00000f00
6824 #define DCBX_ISCSI_OOO_TC_SHIFT 8
6825         u32 pri_tc_tbl[1];
6826 #define DCBX_ISCSI_OOO_TC       (4)
6827
6828 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_ISCSI_OOO_TC + 1)
6829 #define DCBX_CEE_STRICT_PRIORITY        0xf
6830         u32 tc_bw_tbl[2];
6831         u32 tc_tsa_tbl[2];
6832 #define DCBX_ETS_TSA_STRICT     0
6833 #define DCBX_ETS_TSA_CBS        1
6834 #define DCBX_ETS_TSA_ETS        2
6835 };
6836
6837 struct dcbx_app_priority_entry {
6838         u32 entry;
6839 #define DCBX_APP_PRI_MAP_MASK           0x000000ff
6840 #define DCBX_APP_PRI_MAP_SHIFT          0
6841 #define DCBX_APP_PRI_0                  0x01
6842 #define DCBX_APP_PRI_1                  0x02
6843 #define DCBX_APP_PRI_2                  0x04
6844 #define DCBX_APP_PRI_3                  0x08
6845 #define DCBX_APP_PRI_4                  0x10
6846 #define DCBX_APP_PRI_5                  0x20
6847 #define DCBX_APP_PRI_6                  0x40
6848 #define DCBX_APP_PRI_7                  0x80
6849 #define DCBX_APP_SF_MASK                0x00000300
6850 #define DCBX_APP_SF_SHIFT               8
6851 #define DCBX_APP_SF_ETHTYPE             0
6852 #define DCBX_APP_SF_PORT                1
6853 #define DCBX_APP_SF_IEEE_MASK           0x0000f000
6854 #define DCBX_APP_SF_IEEE_SHIFT          12
6855 #define DCBX_APP_SF_IEEE_RESERVED       0
6856 #define DCBX_APP_SF_IEEE_ETHTYPE        1
6857 #define DCBX_APP_SF_IEEE_TCP_PORT       2
6858 #define DCBX_APP_SF_IEEE_UDP_PORT       3
6859 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT   4
6860
6861 #define DCBX_APP_PROTOCOL_ID_MASK       0xffff0000
6862 #define DCBX_APP_PROTOCOL_ID_SHIFT      16
6863 };
6864
6865 struct dcbx_app_priority_feature {
6866         u32 flags;
6867 #define DCBX_APP_ENABLED_MASK           0x00000001
6868 #define DCBX_APP_ENABLED_SHIFT          0
6869 #define DCBX_APP_WILLING_MASK           0x00000002
6870 #define DCBX_APP_WILLING_SHIFT          1
6871 #define DCBX_APP_ERROR_MASK             0x00000004
6872 #define DCBX_APP_ERROR_SHIFT            2
6873 #define DCBX_APP_MAX_TCS_MASK           0x0000f000
6874 #define DCBX_APP_MAX_TCS_SHIFT          12
6875 #define DCBX_APP_NUM_ENTRIES_MASK       0x00ff0000
6876 #define DCBX_APP_NUM_ENTRIES_SHIFT      16
6877         struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
6878 };
6879
6880 struct dcbx_features {
6881         struct dcbx_ets_feature ets;
6882         u32 pfc;
6883 #define DCBX_PFC_PRI_EN_BITMAP_MASK     0x000000ff
6884 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT    0
6885 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0    0x01
6886 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1    0x02
6887 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2    0x04
6888 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3    0x08
6889 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4    0x10
6890 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5    0x20
6891 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6    0x40
6892 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7    0x80
6893
6894 #define DCBX_PFC_FLAGS_MASK             0x0000ff00
6895 #define DCBX_PFC_FLAGS_SHIFT            8
6896 #define DCBX_PFC_CAPS_MASK              0x00000f00
6897 #define DCBX_PFC_CAPS_SHIFT             8
6898 #define DCBX_PFC_MBC_MASK               0x00004000
6899 #define DCBX_PFC_MBC_SHIFT              14
6900 #define DCBX_PFC_WILLING_MASK           0x00008000
6901 #define DCBX_PFC_WILLING_SHIFT          15
6902 #define DCBX_PFC_ENABLED_MASK           0x00010000
6903 #define DCBX_PFC_ENABLED_SHIFT          16
6904 #define DCBX_PFC_ERROR_MASK             0x00020000
6905 #define DCBX_PFC_ERROR_SHIFT            17
6906
6907         struct dcbx_app_priority_feature app;
6908 };
6909
6910 struct dcbx_local_params {
6911         u32 config;
6912 #define DCBX_CONFIG_VERSION_MASK        0x00000007
6913 #define DCBX_CONFIG_VERSION_SHIFT       0
6914 #define DCBX_CONFIG_VERSION_DISABLED    0
6915 #define DCBX_CONFIG_VERSION_IEEE        1
6916 #define DCBX_CONFIG_VERSION_CEE         2
6917 #define DCBX_CONFIG_VERSION_STATIC      4
6918
6919         u32 flags;
6920         struct dcbx_features features;
6921 };
6922
6923 struct dcbx_mib {
6924         u32 prefix_seq_num;
6925         u32 flags;
6926         struct dcbx_features features;
6927         u32 suffix_seq_num;
6928 };
6929
6930 struct lldp_system_tlvs_buffer_s {
6931         u16 valid;
6932         u16 length;
6933         u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
6934 };
6935
6936 struct dcb_dscp_map {
6937         u32 flags;
6938 #define DCB_DSCP_ENABLE_MASK    0x1
6939 #define DCB_DSCP_ENABLE_SHIFT   0
6940 #define DCB_DSCP_ENABLE 1
6941         u32 dscp_pri_map[8];
6942 };
6943
6944 struct public_global {
6945         u32 max_path;
6946         u32 max_ports;
6947         u32 debug_mb_offset;
6948         u32 phymod_dbg_mb_offset;
6949         struct couple_mode_teaming cmt;
6950         s32 internal_temperature;
6951         u32 mfw_ver;
6952         u32 running_bundle_id;
6953         s32 external_temperature;
6954         u32 mdump_reason;
6955 };
6956
6957 struct fw_flr_mb {
6958         u32 aggint;
6959         u32 opgen_addr;
6960         u32 accum_ack;
6961 };
6962
6963 struct public_path {
6964         struct fw_flr_mb flr_mb;
6965         u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
6966
6967         u32 process_kill;
6968 #define PROCESS_KILL_COUNTER_MASK       0x0000ffff
6969 #define PROCESS_KILL_COUNTER_SHIFT      0
6970 #define PROCESS_KILL_GLOB_AEU_BIT_MASK  0xffff0000
6971 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
6972 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
6973 };
6974
6975 struct public_port {
6976         u32 validity_map;
6977
6978         u32 link_status;
6979 #define LINK_STATUS_LINK_UP                     0x00000001
6980 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK       0x0000001e
6981 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD    (1 << 1)
6982 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD    (2 << 1)
6983 #define LINK_STATUS_SPEED_AND_DUPLEX_10G        (3 << 1)
6984 #define LINK_STATUS_SPEED_AND_DUPLEX_20G        (4 << 1)
6985 #define LINK_STATUS_SPEED_AND_DUPLEX_40G        (5 << 1)
6986 #define LINK_STATUS_SPEED_AND_DUPLEX_50G        (6 << 1)
6987 #define LINK_STATUS_SPEED_AND_DUPLEX_100G       (7 << 1)
6988 #define LINK_STATUS_SPEED_AND_DUPLEX_25G        (8 << 1)
6989
6990 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED      0x00000020
6991
6992 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE     0x00000040
6993 #define LINK_STATUS_PARALLEL_DETECTION_USED     0x00000080
6994
6995 #define LINK_STATUS_PFC_ENABLED                         0x00000100
6996 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
6997 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
6998 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE            0x00000800
6999 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE            0x00001000
7000 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE            0x00002000
7001 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE            0x00004000
7002 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE           0x00008000
7003 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE            0x00010000
7004
7005 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
7006 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0 << 18)
7007 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1 << 18)
7008 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2 << 18)
7009 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3 << 18)
7010
7011 #define LINK_STATUS_SFP_TX_FAULT                        0x00100000
7012 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00200000
7013 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00400000
7014 #define LINK_STATUS_RX_SIGNAL_PRESENT                   0x00800000
7015 #define LINK_STATUS_MAC_LOCAL_FAULT                     0x01000000
7016 #define LINK_STATUS_MAC_REMOTE_FAULT                    0x02000000
7017 #define LINK_STATUS_UNSUPPORTED_SPD_REQ                 0x04000000
7018
7019         u32 link_status1;
7020         u32 ext_phy_fw_version;
7021         u32 drv_phy_cfg_addr;
7022
7023         u32 port_stx;
7024
7025         u32 stat_nig_timer;
7026
7027         struct port_mf_cfg port_mf_config;
7028         struct port_stats stats;
7029
7030         u32 media_type;
7031 #define MEDIA_UNSPECIFIED       0x0
7032 #define MEDIA_SFPP_10G_FIBER    0x1
7033 #define MEDIA_XFP_FIBER         0x2
7034 #define MEDIA_DA_TWINAX         0x3
7035 #define MEDIA_BASE_T            0x4
7036 #define MEDIA_SFP_1G_FIBER      0x5
7037 #define MEDIA_MODULE_FIBER      0x6
7038 #define MEDIA_KR                0xf0
7039 #define MEDIA_NOT_PRESENT       0xff
7040
7041         u32 lfa_status;
7042         u32 link_change_count;
7043
7044         struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
7045         struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
7046         struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
7047
7048         /* DCBX related MIB */
7049         struct dcbx_local_params local_admin_dcbx_mib;
7050         struct dcbx_mib remote_dcbx_mib;
7051         struct dcbx_mib operational_dcbx_mib;
7052
7053         u32 reserved[2];
7054         u32 transceiver_data;
7055 #define ETH_TRANSCEIVER_STATE_MASK      0x000000FF
7056 #define ETH_TRANSCEIVER_STATE_SHIFT     0x00000000
7057 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
7058 #define ETH_TRANSCEIVER_STATE_PRESENT   0x00000001
7059 #define ETH_TRANSCEIVER_STATE_VALID     0x00000003
7060 #define ETH_TRANSCEIVER_STATE_UPDATING  0x00000008
7061
7062         u32 wol_info;
7063         u32 wol_pkt_len;
7064         u32 wol_pkt_details;
7065         struct dcb_dscp_map dcb_dscp_map;
7066 };
7067
7068 struct public_func {
7069         u32 reserved0[2];
7070
7071         u32 mtu_size;
7072
7073         u32 reserved[7];
7074
7075         u32 config;
7076 #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
7077 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING          0x00000002
7078 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT    0x00000001
7079
7080 #define FUNC_MF_CFG_PROTOCOL_MASK       0x000000f0
7081 #define FUNC_MF_CFG_PROTOCOL_SHIFT      4
7082 #define FUNC_MF_CFG_PROTOCOL_ETHERNET   0x00000000
7083 #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000010
7084 #define FUNC_MF_CFG_PROTOCOL_ROCE               0x00000030
7085 #define FUNC_MF_CFG_PROTOCOL_MAX        0x00000030
7086
7087 #define FUNC_MF_CFG_MIN_BW_MASK         0x0000ff00
7088 #define FUNC_MF_CFG_MIN_BW_SHIFT        8
7089 #define FUNC_MF_CFG_MIN_BW_DEFAULT      0x00000000
7090 #define FUNC_MF_CFG_MAX_BW_MASK         0x00ff0000
7091 #define FUNC_MF_CFG_MAX_BW_SHIFT        16
7092 #define FUNC_MF_CFG_MAX_BW_DEFAULT      0x00640000
7093
7094         u32 status;
7095 #define FUNC_STATUS_VLINK_DOWN          0x00000001
7096
7097         u32 mac_upper;
7098 #define FUNC_MF_CFG_UPPERMAC_MASK       0x0000ffff
7099 #define FUNC_MF_CFG_UPPERMAC_SHIFT      0
7100 #define FUNC_MF_CFG_UPPERMAC_DEFAULT    FUNC_MF_CFG_UPPERMAC_MASK
7101         u32 mac_lower;
7102 #define FUNC_MF_CFG_LOWERMAC_DEFAULT    0xffffffff
7103
7104         u32 fcoe_wwn_port_name_upper;
7105         u32 fcoe_wwn_port_name_lower;
7106
7107         u32 fcoe_wwn_node_name_upper;
7108         u32 fcoe_wwn_node_name_lower;
7109
7110         u32 ovlan_stag;
7111 #define FUNC_MF_CFG_OV_STAG_MASK        0x0000ffff
7112 #define FUNC_MF_CFG_OV_STAG_SHIFT       0
7113 #define FUNC_MF_CFG_OV_STAG_DEFAULT     FUNC_MF_CFG_OV_STAG_MASK
7114
7115         u32 pf_allocation;
7116
7117         u32 preserve_data;
7118
7119         u32 driver_last_activity_ts;
7120
7121         u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
7122
7123         u32 drv_id;
7124 #define DRV_ID_PDA_COMP_VER_MASK        0x0000ffff
7125 #define DRV_ID_PDA_COMP_VER_SHIFT       0
7126
7127 #define DRV_ID_MCP_HSI_VER_MASK         0x00ff0000
7128 #define DRV_ID_MCP_HSI_VER_SHIFT        16
7129 #define DRV_ID_MCP_HSI_VER_CURRENT      (1 << DRV_ID_MCP_HSI_VER_SHIFT)
7130
7131 #define DRV_ID_DRV_TYPE_MASK            0x7f000000
7132 #define DRV_ID_DRV_TYPE_SHIFT           24
7133 #define DRV_ID_DRV_TYPE_UNKNOWN         (0 << DRV_ID_DRV_TYPE_SHIFT)
7134 #define DRV_ID_DRV_TYPE_LINUX           (1 << DRV_ID_DRV_TYPE_SHIFT)
7135
7136 #define DRV_ID_DRV_INIT_HW_MASK         0x80000000
7137 #define DRV_ID_DRV_INIT_HW_SHIFT        31
7138 #define DRV_ID_DRV_INIT_HW_FLAG         (1 << DRV_ID_DRV_INIT_HW_SHIFT)
7139 };
7140
7141 struct mcp_mac {
7142         u32 mac_upper;
7143         u32 mac_lower;
7144 };
7145
7146 struct mcp_val64 {
7147         u32 lo;
7148         u32 hi;
7149 };
7150
7151 struct mcp_file_att {
7152         u32 nvm_start_addr;
7153         u32 len;
7154 };
7155
7156 struct bist_nvm_image_att {
7157         u32 return_code;
7158         u32 image_type;
7159         u32 nvm_start_addr;
7160         u32 len;
7161 };
7162
7163 #define MCP_DRV_VER_STR_SIZE 16
7164 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
7165 #define MCP_DRV_NVM_BUF_LEN 32
7166 struct drv_version_stc {
7167         u32 version;
7168         u8 name[MCP_DRV_VER_STR_SIZE - 4];
7169 };
7170
7171 struct lan_stats_stc {
7172         u64 ucast_rx_pkts;
7173         u64 ucast_tx_pkts;
7174         u32 fcs_err;
7175         u32 rserved;
7176 };
7177
7178 struct ocbb_data_stc {
7179         u32 ocbb_host_addr;
7180         u32 ocsd_host_addr;
7181         u32 ocsd_req_update_interval;
7182 };
7183
7184 #define MAX_NUM_OF_SENSORS 7
7185 struct temperature_status_stc {
7186         u32 num_of_sensors;
7187         u32 sensor[MAX_NUM_OF_SENSORS];
7188 };
7189
7190 /* crash dump configuration header */
7191 struct mdump_config_stc {
7192         u32 version;
7193         u32 config;
7194         u32 epoc;
7195         u32 num_of_logs;
7196         u32 valid_logs;
7197 };
7198
7199 union drv_union_data {
7200         u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
7201         struct mcp_mac wol_mac;
7202
7203         struct eth_phy_cfg drv_phy_cfg;
7204
7205         struct mcp_val64 val64;
7206
7207         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
7208
7209         struct mcp_file_att file_att;
7210
7211         u32 ack_vf_disabled[VF_MAX_STATIC / 32];
7212
7213         struct drv_version_stc drv_version;
7214
7215         struct lan_stats_stc lan_stats;
7216         u64 reserved_stats[11];
7217         struct ocbb_data_stc ocbb_info;
7218         struct temperature_status_stc temp_info;
7219         struct bist_nvm_image_att nvm_image_att;
7220         struct mdump_config_stc mdump_config;
7221 };
7222
7223 struct public_drv_mb {
7224         u32 drv_mb_header;
7225 #define DRV_MSG_CODE_MASK                       0xffff0000
7226 #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
7227 #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
7228 #define DRV_MSG_CODE_INIT_HW                    0x12000000
7229 #define DRV_MSG_CODE_UNLOAD_REQ                 0x20000000
7230 #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
7231 #define DRV_MSG_CODE_INIT_PHY                   0x22000000
7232 #define DRV_MSG_CODE_LINK_RESET                 0x23000000
7233 #define DRV_MSG_CODE_SET_DCBX                   0x25000000
7234
7235 #define DRV_MSG_CODE_BW_UPDATE_ACK              0x32000000
7236 #define DRV_MSG_CODE_NIG_DRAIN                  0x30000000
7237 #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
7238 #define DRV_MSG_CODE_CFG_VF_MSIX                0xc0010000
7239 #define DRV_MSG_CODE_MCP_RESET                  0x00090000
7240 #define DRV_MSG_CODE_SET_VERSION                0x000f0000
7241
7242 #define DRV_MSG_CODE_BIST_TEST                  0x001e0000
7243 #define DRV_MSG_CODE_SET_LED_MODE               0x00200000
7244
7245 #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
7246
7247         u32 drv_mb_param;
7248 #define DRV_MB_PARAM_UNLOAD_WOL_MCP             0x00000001
7249 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK           0x000000FF
7250 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT          3
7251 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT    0
7252 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK     0x000000FF
7253 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT   8
7254 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK    0x0000FF00
7255 #define DRV_MB_PARAM_LLDP_SEND_MASK             0x00000001
7256 #define DRV_MB_PARAM_LLDP_SEND_SHIFT            0
7257
7258
7259 #define DRV_MB_PARAM_SET_LED_MODE_OPER          0x0
7260 #define DRV_MB_PARAM_SET_LED_MODE_ON            0x1
7261 #define DRV_MB_PARAM_SET_LED_MODE_OFF           0x2
7262
7263 #define DRV_MB_PARAM_BIST_REGISTER_TEST         1
7264 #define DRV_MB_PARAM_BIST_CLOCK_TEST            2
7265
7266 #define DRV_MB_PARAM_BIST_RC_UNKNOWN            0
7267 #define DRV_MB_PARAM_BIST_RC_PASSED             1
7268 #define DRV_MB_PARAM_BIST_RC_FAILED             2
7269 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER  3
7270
7271 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT      0
7272 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK       0x000000FF
7273
7274         u32 fw_mb_header;
7275 #define FW_MSG_CODE_MASK                        0xffff0000
7276 #define FW_MSG_CODE_DRV_LOAD_ENGINE             0x10100000
7277 #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
7278 #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
7279 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA        0x10200000
7280 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI        0x10210000
7281 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG       0x10220000
7282 #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
7283 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE           0x20110000
7284 #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20120000
7285 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20130000
7286 #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
7287 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE        0xb0010000
7288 #define FW_MSG_CODE_OK                          0x00160000
7289
7290 #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
7291
7292         u32 fw_mb_param;
7293
7294         u32 drv_pulse_mb;
7295 #define DRV_PULSE_SEQ_MASK                      0x00007fff
7296 #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
7297 #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
7298
7299         u32 mcp_pulse_mb;
7300 #define MCP_PULSE_SEQ_MASK                      0x00007fff
7301 #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
7302 #define MCP_EVENT_MASK                          0xffff0000
7303 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
7304
7305         union drv_union_data union_data;
7306 };
7307
7308 enum MFW_DRV_MSG_TYPE {
7309         MFW_DRV_MSG_LINK_CHANGE,
7310         MFW_DRV_MSG_FLR_FW_ACK_FAILED,
7311         MFW_DRV_MSG_VF_DISABLED,
7312         MFW_DRV_MSG_LLDP_DATA_UPDATED,
7313         MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
7314         MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
7315         MFW_DRV_MSG_RESERVED4,
7316         MFW_DRV_MSG_BW_UPDATE,
7317         MFW_DRV_MSG_BW_UPDATE5,
7318         MFW_DRV_MSG_BW_UPDATE6,
7319         MFW_DRV_MSG_BW_UPDATE7,
7320         MFW_DRV_MSG_BW_UPDATE8,
7321         MFW_DRV_MSG_BW_UPDATE9,
7322         MFW_DRV_MSG_BW_UPDATE10,
7323         MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
7324         MFW_DRV_MSG_BW_UPDATE11,
7325         MFW_DRV_MSG_MAX
7326 };
7327
7328 #define MFW_DRV_MSG_MAX_DWORDS(msgs)    (((msgs - 1) >> 2) + 1)
7329 #define MFW_DRV_MSG_DWORD(msg_id)       (msg_id >> 2)
7330 #define MFW_DRV_MSG_OFFSET(msg_id)      ((msg_id & 0x3) << 3)
7331 #define MFW_DRV_MSG_MASK(msg_id)        (0xff << MFW_DRV_MSG_OFFSET(msg_id))
7332
7333 struct public_mfw_mb {
7334         u32 sup_msgs;
7335         u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
7336         u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
7337 };
7338
7339 enum public_sections {
7340         PUBLIC_DRV_MB,
7341         PUBLIC_MFW_MB,
7342         PUBLIC_GLOBAL,
7343         PUBLIC_PATH,
7344         PUBLIC_PORT,
7345         PUBLIC_FUNC,
7346         PUBLIC_MAX_SECTIONS
7347 };
7348
7349 struct mcp_public_data {
7350         u32 num_sections;
7351         u32 sections[PUBLIC_MAX_SECTIONS];
7352         struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
7353         struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
7354         struct public_global global;
7355         struct public_path path[MCP_GLOB_PATH_MAX];
7356         struct public_port port[MCP_GLOB_PORT_MAX];
7357         struct public_func func[MCP_GLOB_FUNC_MAX];
7358 };
7359
7360 struct nvm_cfg_mac_address {
7361         u32 mac_addr_hi;
7362 #define NVM_CFG_MAC_ADDRESS_HI_MASK     0x0000FFFF
7363 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET   0
7364         u32 mac_addr_lo;
7365 };
7366
7367 struct nvm_cfg1_glob {
7368         u32 generic_cont0;
7369 #define NVM_CFG1_GLOB_MF_MODE_MASK              0x00000FF0
7370 #define NVM_CFG1_GLOB_MF_MODE_OFFSET            4
7371 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED        0x0
7372 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT           0x1
7373 #define NVM_CFG1_GLOB_MF_MODE_SPIO4             0x2
7374 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0           0x3
7375 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5           0x4
7376 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0           0x5
7377 #define NVM_CFG1_GLOB_MF_MODE_BD                0x6
7378 #define NVM_CFG1_GLOB_MF_MODE_UFP               0x7
7379         u32 engineering_change[3];
7380         u32 manufacturing_id;
7381         u32 serial_number[4];
7382         u32 pcie_cfg;
7383         u32 mgmt_traffic;
7384         u32 core_cfg;
7385 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK            0x000000FF
7386 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET          0
7387 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G        0x0
7388 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G           0x1
7389 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G       0x2
7390 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F         0x3
7391 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E      0x4
7392 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G        0x5
7393 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G           0xB
7394 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G           0xC
7395 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G           0xD
7396 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G           0xE
7397         u32 e_lane_cfg1;
7398         u32 e_lane_cfg2;
7399         u32 f_lane_cfg1;
7400         u32 f_lane_cfg2;
7401         u32 mps10_preemphasis;
7402         u32 mps10_driver_current;
7403         u32 mps25_preemphasis;
7404         u32 mps25_driver_current;
7405         u32 pci_id;
7406         u32 pci_subsys_id;
7407         u32 bar;
7408         u32 mps10_txfir_main;
7409         u32 mps10_txfir_post;
7410         u32 mps25_txfir_main;
7411         u32 mps25_txfir_post;
7412         u32 manufacture_ver;
7413         u32 manufacture_time;
7414         u32 led_global_settings;
7415         u32 generic_cont1;
7416         u32 mbi_version;
7417         u32 mbi_date;
7418         u32 misc_sig;
7419         u32 device_capabilities;
7420 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET      0x1
7421 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI         0x4
7422 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE          0x8
7423         u32 power_dissipated;
7424         u32 power_consumed;
7425         u32 efi_version;
7426         u32 multi_network_modes_capability;
7427         u32 reserved[41];
7428 };
7429
7430 struct nvm_cfg1_path {
7431         u32 reserved[30];
7432 };
7433
7434 struct nvm_cfg1_port {
7435         u32 reserved__m_relocated_to_option_123;
7436         u32 reserved__m_relocated_to_option_124;
7437         u32 generic_cont0;
7438 #define NVM_CFG1_PORT_DCBX_MODE_MASK                            0x000F0000
7439 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET                          16
7440 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED                        0x0
7441 #define NVM_CFG1_PORT_DCBX_MODE_IEEE                            0x1
7442 #define NVM_CFG1_PORT_DCBX_MODE_CEE                             0x2
7443 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC                         0x3
7444 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK            0x00F00000
7445 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET          20
7446 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET        0x1
7447 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE            0x2
7448 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI           0x4
7449         u32 pcie_cfg;
7450         u32 features;
7451         u32 speed_cap_mask;
7452 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK            0x0000FFFF
7453 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET          0
7454 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G              0x1
7455 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G             0x2
7456 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G             0x8
7457 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G             0x10
7458 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G             0x20
7459 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G         0x40
7460         u32 link_settings;
7461 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK                       0x0000000F
7462 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET                     0
7463 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG                    0x0
7464 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G                         0x1
7465 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G                        0x2
7466 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G                        0x4
7467 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G                        0x5
7468 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G                        0x6
7469 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G                    0x7
7470 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ                  0x8
7471 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK                     0x00000070
7472 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET                   4
7473 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG                  0x1
7474 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX                       0x2
7475 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX                       0x4
7476         u32 phy_cfg;
7477         u32 mgmt_traffic;
7478         u32 ext_phy;
7479         u32 mba_cfg1;
7480         u32 mba_cfg2;
7481         u32 vf_cfg;
7482         struct nvm_cfg_mac_address lldp_mac_address;
7483         u32 led_port_settings;
7484         u32 transceiver_00;
7485         u32 device_ids;
7486         u32 board_cfg;
7487         u32 mnm_10g_cap;
7488         u32 mnm_10g_ctrl;
7489         u32 mnm_10g_misc;
7490         u32 mnm_25g_cap;
7491         u32 mnm_25g_ctrl;
7492         u32 mnm_25g_misc;
7493         u32 mnm_40g_cap;
7494         u32 mnm_40g_ctrl;
7495         u32 mnm_40g_misc;
7496         u32 mnm_50g_cap;
7497         u32 mnm_50g_ctrl;
7498         u32 mnm_50g_misc;
7499         u32 mnm_100g_cap;
7500         u32 mnm_100g_ctrl;
7501         u32 mnm_100g_misc;
7502         u32 reserved[116];
7503 };
7504
7505 struct nvm_cfg1_func {
7506         struct nvm_cfg_mac_address mac_address;
7507         u32 rsrv1;
7508         u32 rsrv2;
7509         u32 device_id;
7510         u32 cmn_cfg;
7511         u32 pci_cfg;
7512         struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
7513         struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
7514         u32 preboot_generic_cfg;
7515         u32 reserved[8];
7516 };
7517
7518 struct nvm_cfg1 {
7519         struct nvm_cfg1_glob glob;
7520         struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
7521         struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
7522         struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
7523 };
7524 #endif